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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-10-02 10:54:08 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-10-06 02:04:16 -0400 |
| commit | b00f996cce04424af4dc38a112edcd6900e5de92 (patch) | |
| tree | 56a9670d40fec6828ae0b17a6c1f16195698d03f /src/import/chips/p9/procedures/hwp | |
| parent | c4fc0ca3312c163fedf76200161f616176891ddd (diff) | |
| download | talos-sbe-b00f996cce04424af4dc38a112edcd6900e5de92.tar.gz talos-sbe-b00f996cce04424af4dc38a112edcd6900e5de92.zip | |
p9_sbe_tp_enable_ridi -- restore old behavior for cache contained mode support
Enable TP RIDI in this step for Cronus only, in cache contained mode
Change-Id: I58635087fe6a924db32ada48a34f5df65fc44aa7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47000
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47006
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C index aabd8ce3..fb4986ff 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C @@ -38,10 +38,33 @@ //## auto_generated #include "p9_sbe_tp_enable_ridi.H" +#include "p9_perv_scom_addresses.H" fapi2::ReturnCode p9_sbe_tp_enable_ridi(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { - // This function is now a stub, functionality has been moved to p9_sbe_nest_enable_ridi.C + // outside of Cronus cache contained mode, this function is now a stub, + // functionality for the mainline IPL has been moved to p9_sbe_nest_enable_ridi.C +#ifndef __PPE_ + fapi2::buffer<uint64_t> l_data64; + uint8_t l_system_ipl_phase; + FAPI_DBG("Entering ..."); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_system_ipl_phase), + "Error from FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)"); + + if (l_system_ipl_phase == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) + { + FAPI_INF("Enable Recievers, Drivers DI1 & DI2"); + //Setting ROOT_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + l_data64.setBit<19>(); //PIB.ROOT_CTRL1.TP_RI_DC_B = 1 + l_data64.setBit<20>(); //PIB.ROOT_CTRL1.TP_DI1_DC_B = 1 + l_data64.setBit<21>(); //PIB.ROOT_CTRL1.TP_DI2_DC_B = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + FAPI_DBG("Exiting ..."); + } + +fapi_try_exit: +#endif return fapi2::current_err; } |
