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author | Ben Gass <bgass@us.ibm.com> | 2016-12-07 16:58:46 -0600 |
---|---|---|
committer | spashabk-in <shakeebbk@in.ibm.com> | 2016-12-20 05:18:51 -0600 |
commit | 8d07cb04ffb38e68b48b3bd17bebfd27d7dc0a50 (patch) | |
tree | ce2b545b8fbd21c3b128512026a5c817add35398 /src/import/chips/p9/procedures/hwp | |
parent | 1530962a1d0646bfab325c825f1426843298f8b4 (diff) | |
download | talos-sbe-8d07cb04ffb38e68b48b3bd17bebfd27d7dc0a50.tar.gz talos-sbe-8d07cb04ffb38e68b48b3bd17bebfd27d7dc0a50.zip |
p9_hcd_cache_chiplet_reset skip entire vcs workaround in sim
Running the whole thing takes too long. Only doing a part
of the rings causes initR issues because the fences are
being dropped at the end of the workaround.
Change-Id: I9cd12c2e7b4d1fcb718f42f8a5c8e85ccdae2350
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33556
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33558
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C | 194 |
1 files changed, 95 insertions, 99 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C index 2fa17ccf..7a1897ef 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -301,49 +301,44 @@ p9_hcd_dd1_vcs_workaround( uint32_t l_loop; #ifndef __PPE__ - //This is to skip flushing the entire eq ring to 1's in simulation - //for the HW388878 workaround + //Skip the entire work-around in simulation to save time. + //Only flushing part of the rings to 1's causes initR issues + //because the fences are being dropped at the end of the workaround. fapi2::buffer<uint8_t> l_attr_is_simulation; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_attr_is_simulation)); -#endif - l_regions = p9hcd::CLK_REGION_PERV | - p9hcd::CLK_REGION_EX0_L2 | - p9hcd::CLK_REGION_EX1_L2; + if (!l_attr_is_simulation) + { - // ---------------------------------------------------- - // Scan1 initialize region:Perv/L20/L21 type:Fure rings - // Note: must also scan partial good "bad" L2 rings, - // and clock start&stop their latches, as well - // ---------------------------------------------------- +#endif - FAPI_DBG("Assert Vital clock regional fence via CPLT_CTRL1[3]"); - FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3))); + l_regions = p9hcd::CLK_REGION_PERV | + p9hcd::CLK_REGION_EX0_L2 | + p9hcd::CLK_REGION_EX1_L2; - FAPI_DBG("Assert regional fences of scanned regions via CPLT_CTRL1[4,8,9]"); - FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, l_regions)); + // ---------------------------------------------------- + // Scan1 initialize region:Perv/L20/L21 type:Fure rings + // Note: must also scan partial good "bad" L2 rings, + // and clock start&stop their latches, as well + // ---------------------------------------------------- - FAPI_DBG("Clear clock region register via CLK_REGION"); - FAPI_TRY(putScom(i_target, EQ_CLK_REGION, MASK_ZERO)); + FAPI_DBG("Assert Vital clock regional fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3))); - FAPI_DBG("Setup scan select register via SCAN_REGION_TYPE[4,8,9,48,51]"); - FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, - (l_regions | p9hcd::SCAN_TYPE_FUNC | p9hcd::SCAN_TYPE_REGF))); + FAPI_DBG("Assert regional fences of scanned regions via CPLT_CTRL1[4,8,9]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, l_regions)); - FAPI_DBG("Write scan data register via 0x1003E040"); + FAPI_DBG("Clear clock region register via CLK_REGION"); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, MASK_ZERO)); -#ifndef __PPE__ + FAPI_DBG("Setup scan select register via SCAN_REGION_TYPE[4,8,9,48,51]"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, + (l_regions | p9hcd::SCAN_TYPE_FUNC | p9hcd::SCAN_TYPE_REGF))); + + FAPI_DBG("Write scan data register via 0x1003E040"); - if (l_attr_is_simulation) - { - FAPI_DBG("SIMULATION ONLY WRITE ONCE"); - FAPI_TRY(putScom(i_target, 0x1003E040, MASK_ALL)); - } - else - { -#endif for (l_loop = 0; l_loop <= DD1_EQ_FURE_RING_LENGTH / 64; l_loop++) { @@ -351,100 +346,101 @@ p9_hcd_dd1_vcs_workaround( FAPI_TRY(putScom(i_target, 0x1003E040, MASK_ALL)); } -#ifndef __PPE__ - } -#endif + // ------------------------------- + // Start Perv/L20/L21 clocks + // ------------------------------- - // ------------------------------- - // Start Perv/L20/L21 clocks - // ------------------------------- + FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); - FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); - FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + FAPI_DBG("Start cache clocks(perv/l20/l21) via CLK_REGION"); + l_data64 = (p9hcd::CLK_START_CMD | l_regions | p9hcd::CLK_THOLD_ARY); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); - FAPI_DBG("Start cache clocks(perv/l20/l21) via CLK_REGION"); - l_data64 = (p9hcd::CLK_START_CMD | l_regions | p9hcd::CLK_THOLD_ARY); - FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + FAPI_DBG("Poll for perv/l20/l21 clocks running via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); - FAPI_DBG("Poll for perv/l20/l21 clocks running via CPLT_STAT0[8]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); - do - { - FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); - } - while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + "perv/l20/l21 Clock Start Timeout"); - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), - "perv/l20/l21 Clock Start Timeout"); + FAPI_DBG("Check perv/l20/l21 clocks running"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); - FAPI_DBG("Check perv/l20/l21 clocks running"); - FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); + FAPI_ASSERT(((l_data64 & l_regions) == 0), + fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64), + "perv/l20/l21 Clock Start Failed"); + FAPI_DBG("perv/l20/l21 clocks running now"); - FAPI_ASSERT(((l_data64 & l_regions) == 0), - fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64), - "perv/l20/l21 Clock Start Failed"); - FAPI_DBG("perv/l20/l21 clocks running now"); + // ------------------------------- + // Turn on power headers for VCS + // ------------------------------- - // ------------------------------- - // Turn on power headers for VCS - // ------------------------------- + FAPI_TRY(p9_common_poweronoff<fapi2::TARGET_TYPE_EQ>(i_target, p9power::POWER_ON_VCS)); - FAPI_TRY(p9_common_poweronoff<fapi2::TARGET_TYPE_EQ>(i_target, p9power::POWER_ON_VCS)); + // Because common module raises those fences, we need to lower them here. + FAPI_DBG("Drop vital thold via NET_CTRL0[16]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16))); - // Because common module raises those fences, we need to lower them here. - FAPI_DBG("Drop vital thold via NET_CTRL0[16]"); - FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16))); + FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(26))); - FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]"); - FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(26))); + FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25))); - FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); - FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25))); + // ------------------------------- + // Stop Perv/L20/L21 clocks + // ------------------------------- - // ------------------------------- - // Stop Perv/L20/L21 clocks - // ------------------------------- + FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); - FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); - FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + FAPI_DBG("Stop perv/l20/l21 clocks via CLK_REGION"); + l_data64 = (p9hcd::CLK_STOP_CMD | l_regions | p9hcd::CLK_THOLD_ARY); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); - FAPI_DBG("Stop perv/l20/l21 clocks via CLK_REGION"); - l_data64 = (p9hcd::CLK_STOP_CMD | l_regions | p9hcd::CLK_THOLD_ARY); - FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + FAPI_DBG("Poll for perv/l20/l21 clocks stopped via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); - FAPI_DBG("Poll for perv/l20/l21 clocks stopped via CPLT_STAT0[8]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); - do - { - FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); - } - while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64), + "perv/l20/l21 Clock Stop Timeout"); - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CACHECLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64), - "perv/l20/l21 Clock Stop Timeout"); + FAPI_DBG("Check perv/l20/l21 clocks stopped"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); - FAPI_DBG("Check perv/l20/l21 clocks stopped"); - FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); + FAPI_ASSERT((((~l_data64) & l_regions) == 0), + fapi2::PMPROC_CACHECLKSTOP_FAILED().set_EQCLKSTAT(l_data64), + "perv/l20/l21 Clock Stop Failed"); + FAPI_DBG("perv/l20/l21 clocks stopped now"); - FAPI_ASSERT((((~l_data64) & l_regions) == 0), - fapi2::PMPROC_CACHECLKSTOP_FAILED().set_EQCLKSTAT(l_data64), - "perv/l20/l21 Clock Stop Failed"); - FAPI_DBG("perv/l20/l21 clocks stopped now"); + // ------------------------------- + // Clean up + // ------------------------------- - // ------------------------------- - // Clean up - // ------------------------------- + FAPI_DBG("Drop Vital clock regional fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(3))); - FAPI_DBG("Drop Vital clock regional fence via CPLT_CTRL1[3]"); - FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(3))); + FAPI_DBG("Drop Perv/L20/L21 regional fences via CPLT_CTRL1[4,8,9]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, l_regions)); - FAPI_DBG("Drop Perv/L20/L21 regional fences via CPLT_CTRL1[4,8,9]"); - FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, l_regions)); +#ifndef __PPE__ + } + +#endif fapi_try_exit: |