diff options
| author | Amit Kumar <akumar3@us.ibm.com> | 2017-01-13 00:52:04 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-01-17 23:59:42 -0500 |
| commit | 3856467f1133e0cea0d8535d479551aaa4bd2c81 (patch) | |
| tree | 3349c46aa690abfb091c462fdb687fac6bffab77 /src/import/chips/p9/procedures/hwp | |
| parent | 04df965bfac57f2195f3cbba79906086240ebe34 (diff) | |
| download | talos-sbe-3856467f1133e0cea0d8535d479551aaa4bd2c81.tar.gz talos-sbe-3856467f1133e0cea0d8535d479551aaa4bd2c81.zip | |
SGPE HWP : tune PFET controller polling
Change-Id: I37f067f88c422f29b131329436b3a96475e24e75
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34819
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34858
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C index 3049363f..08abf36b 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -73,7 +73,12 @@ const uint64_t PPM_PFSNS[2] = { C_PPM_PFSNS, EQ_PPM_PFSNS }; -enum { FSM_IDLE_POLLING_HW_NS_DELAY = 10000, +// With a PFET step delay of 250ns and 8 steps, the PFET controller needs ~2us to +// complete. A 500 delay keeps the SGPE off of the PCB bus to let other traffic +// through while potentially adding .5us to the STOP11 time. For this and the SBE +// usage of this (istep 4), this trade-off is acceptable. + +enum { FSM_IDLE_POLLING_HW_NS_DELAY = 500, FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 320000, PFET_STATE_LENGTH = 2, VXX_PG_SEL_LEN = 4 |
