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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-02-07 20:50:01 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-05-27 13:05:34 -0400 |
| commit | 3a302c892abb5dc2a2670b79666843809fb33407 (patch) | |
| tree | 247a74ac7a7625016a1f8ccce600345eb6dfab28 /src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C | |
| parent | 426ea6f2e98fe3472087206d4b48526a49c01541 (diff) | |
| download | talos-sbe-3a302c892abb5dc2a2670b79666843809fb33407.tar.gz talos-sbe-3a302c892abb5dc2a2670b79666843809fb33407.zip | |
support chip swap in memory map via FBC XOR mask programming
p9_sbe_fabricinit.C
p9.fbc.ab_hp.scom.initfile
set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC
group/chip ID attribute values, prior to island mode FBC init
cleanup register/field constant todos
p9_fbc_utils.C
parametrize p9_fbc_utils_get_chip_base_address to support calculation of
origin address based on:
- effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS)
- effective FBC drawer origin -- effective FBC group ID + chip ID=0
(EFF_FBC_GRP_ID_ONLY)
- absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS)
p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support)
set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY
configures BAR address based on drawer base + HRMOR
p9_sbe_load_bootloader.C
set p9_fbc_utils_get_chip_base_address call for bootloader load to use
EFF_FBC_GRP_ID_ONLY (drawer)
store XSCOM/LPC BAR into bootloader config data structure in exception vector
(based on chip offset)
p9_mss_eff_grouping.C (MCS/HTM BARs)
p9_pcie_config.C (PCIE MMIO BARs)
p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR)
p9_sbe_scominit.C (XSCOM/LPC BARs)
p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs)
set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS
p9_setup_sbe_config.C
p9_sbe_attr_setup.C
transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox
p9_xip_customize.C
init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image
Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37776
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C index acf90b78..2e743e7a 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -258,9 +258,10 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C #endif // determine base address - // = (chip non-mirrored base address) + (hostboot HRMOR offset) + // = (drawer non-mirrored base address) + (hostboot HRMOR offset) // min MCS base size is 4GB, local HB will always be below FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + EFF_FBC_GRP_ID_ONLY, l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, |
