support chip swap in memory map via FBC XOR mask programming

p9_sbe_fabricinit.C
p9.fbc.ab_hp.scom.initfile
  set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC
  group/chip ID attribute values, prior to island mode FBC init

  cleanup register/field constant todos

p9_fbc_utils.C
  parametrize p9_fbc_utils_get_chip_base_address to support calculation of
  origin address based on:
    - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS)
    - effective FBC drawer origin -- effective FBC group ID + chip ID=0
      (EFF_FBC_GRP_ID_ONLY)
    - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS)

p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY
  configures BAR address based on drawer base + HRMOR

p9_sbe_load_bootloader.C
  set p9_fbc_utils_get_chip_base_address call for bootloader load to use
  EFF_FBC_GRP_ID_ONLY (drawer)

  store XSCOM/LPC BAR into bootloader config data structure in exception vector
  (based on chip offset)

p9_mss_eff_grouping.C (MCS/HTM BARs)
p9_pcie_config.C (PCIE MMIO BARs)
p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR)
p9_sbe_scominit.C (XSCOM/LPC BARs)
p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox

p9_xip_customize.C
  init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image

Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37776
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 10 insertions, 7 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
index 9120e625..b8b426e8 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
@@ -55,18 +55,21 @@ enum SbeBootloaderVersion
     // Keep initial version formatted as it was originally
     INIT = 0x901,
     // Later versions use format [release:2][version:2]
-    SAB_ADDED = 0x00090002
+    SAB_ADDED = 0x00090002,
+    MMIO_BARS_ADDED = 0x00090003,
 };
 
 // Structure starts at the bootloader zero address
 struct BootloaderConfigData_t
 {
-    uint32_t version;  // Some kind of version field so we know if there is new data being added
-    uint8_t sbeBootSide;  // 0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
-    uint8_t pnorBootSide;  // 0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
-    uint16_t pnorSizeMB;  // Size of PNOR in MB  [ATTR_PNOR_SIZE]
-    uint64_t blLoadSize;  // Size of Load (Exception vectors and Bootloader)
-    uint8_t secureAccessBit;
+    uint32_t version;         // bytes  4:7  Version field so we know if there is new data being added
+    uint8_t sbeBootSide;      // byte   8    0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
+    uint8_t pnorBootSide;     // byte   9    0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
+    uint16_t pnorSizeMB;      // bytes 10:11 Size of PNOR in MB  [ATTR_PNOR_SIZE]
+    uint64_t blLoadSize;      // bytes 12:19 Size of Load (Exception vectors and Bootloader)
+    uint8_t secureAccessBit;  // byte  20
+    uint64_t xscomBAR;        // bytes 21:28 XSCOM MMIO BAR
+    uint64_t lpcBAR;          // bytes 29:36 LPC MMIO BAR
 };
 
 #endif