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author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2017-01-05 17:55:19 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-01-06 23:28:27 -0500 |
commit | 8f574bb53e1db2c8b92d58a40140a113a6f5f3a3 (patch) | |
tree | f4dfd5ac0fe97b63a1c73efd437dfb414ea52f52 /src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C | |
parent | 7e13b0e08009ec0347ff91e10ae841b33918361c (diff) | |
download | talos-sbe-8f574bb53e1db2c8b92d58a40140a113a6f5f3a3.tar.gz talos-sbe-8f574bb53e1db2c8b92d58a40140a113a6f5f3a3.zip |
Increasing delay for l3_flush based on HW requirements
Change-Id: I358c59c69d121ddab43c335a835253dea01b359f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34465
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34467
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C b/src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C index e9619077..e7ba964f 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_l3_flush.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,7 +55,7 @@ extern "C" { const uint32_t P9_L3_FLUSH_SIM_CYCLE_DELAY = 1000000; //If the L3 purge is not completed in P9_L3_FLUSH_TIMEOUT delays, fail with error - const uint32_t P9_L3_FLUSH_TIMEOUT_COUNT = 20; + const uint32_t P9_L3_FLUSH_TIMEOUT_COUNT = 40; //-------------------------------------------------------------------------- // HWP entry point |