Secure memory allocation and setup

p9_mss_eff_grouping.C:
  - determines whether secure mem is requested, reserves smf space
  - always reserve smf at end of range because of end-of-range bit
  - set addr15 when reporting smf base address
  - mask off group_id(0) via chip address extension if smf is enabled
  - updated to set value of attr_smf_enabled
  - enhanced error reporting with smf config/supported values
  - made values reported to attr_mss_mcs_group_32 more clear

p9_mss_setup_bars.C:
  - set MCFGPA/MCFGPMA registers with SMF data
  - fixed scom registers for MCFGPA/MCFGPMA hole setup
  - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711
  - added assert to check for HOLE1 and SMF enable overlaps

p9_query_mssinfo.C:
  - updated to print out SMF reservations
  - print out HTM/OCC/SMF reservations regardless of mirroring enable

p9_fbc_utils.C:
  - prevent group_id(0)=1 from affecting mappable memory ranges

p9_sbe_fabricinit.C:
  - mask off group_id(0) via chip address extension if smf is enabled

p9_setup_sbe_config.C, p9_sbe_attr_setup.C:
  - use scratch_reg6 bit(16) to pass smf_config value

initfiles:
  - removed setup to use other addr bits as secure bit; core only uses addr15
  - added setup for ncu addr15 value in hcode
  - always set addr15 config bit in bridge unit if smf is supported
  - set addr15 bit across all mcs if smf is enabled
  - added in settings to enable smf in nmmu unit
  - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported

attributes:
  - ATTR_SMF_ENABLE is a system level attribute
  - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported)

CQ:HW451708
CQ:HW451711
Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 29 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
index 74c93788..f66c1160 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
@@ -44,6 +44,7 @@ constexpr uint64_t literal_0x000000000000 = 0x000000000000;
 constexpr uint64_t literal_0x910000040F00 = 0x910000040F00;
 constexpr uint64_t literal_0x911100000F00 = 0x911100000F00;
 constexpr uint64_t literal_0x991100000F00 = 0x991100000F00;
+constexpr uint64_t literal_0b110 = 0b110;
 constexpr uint64_t literal_0b11111 = 0b11111;
 constexpr uint64_t literal_0x00E = 0x00E;
 constexpr uint64_t literal_0x000 = 0x000;
@@ -63,6 +64,8 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW414700));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c03ull, l_scom_buffer ));
@@ -206,6 +209,20 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             FAPI_TRY(fapi2::putScom(TGT0, 0x5012c47ull, l_scom_buffer));
         }
         {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5012c4cull, l_scom_buffer ));
+
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<0, 3, 61, uint64_t>(literal_0b110 );
+                }
+
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5012c4cull, l_scom_buffer));
+            }
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c52ull, l_scom_buffer ));
 
             l_scom_buffer.insert<30, 1, 59, uint64_t>(literal_0b11111 );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
index a0cdaf54..3b6a9b28 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
@@ -36,6 +36,7 @@ constexpr uint64_t literal_0b0001 = 0b0001;
 constexpr uint64_t literal_0b1000 = 0b1000;
 constexpr uint64_t literal_0x40 = 0x40;
 constexpr uint64_t literal_0x8 = 0x8;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_6 = 6;
 constexpr uint64_t literal_0 = 0;
 constexpr uint64_t literal_15 = 15;
@@ -57,6 +58,8 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
         fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::ATTR_CHIP_EC_FEATURE_HW440920_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW440920;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW440920, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW440920));
         fapi2::buffer<uint64_t> l_scom_buffer;
@@ -141,6 +144,15 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x1001100cull, l_scom_buffer ));
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_0b10 );
+                }
+            }
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
                     && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10))
                 || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6)