diff options
| author | Ben Gass <bgass@us.ibm.com> | 2016-09-15 14:11:53 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-22 10:21:52 -0400 |
| commit | acde4329791d68af6f3822346a7038303b67ea6c (patch) | |
| tree | b4e52350e63d9dc34dfecad5e78740e1610a0e63 /src/import/chips/p9/common | |
| parent | a62943076325f9d966b62518f363d178257577cb (diff) | |
| download | talos-sbe-acde4329791d68af6f3822346a7038303b67ea6c.tar.gz talos-sbe-acde4329791d68af6f3822346a7038303b67ea6c.zip | |
Header file updates based on 9067 figtree
Associated changes based on constant name changes.
Add wregister part_decl and access fields.
Change-Id: I74810bb75430981bfcc0d964823fe249866a1dcf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29797
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Yang Fan Liu <shliuyf@cn.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29801
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common')
17 files changed, 53875 insertions, 23624 deletions
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses.H index c2d9020f..6396e10f 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses.H @@ -38797,6 +38797,116 @@ REG64( MCA_5_HWMS7 , RULL(0x08010A57 REG64( MCA_6_HWMS7 , RULL(0x08010A97), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); REG64( MCA_7_HWMS7 , RULL(0x08010AD7), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); +REG64( MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG , RULL(0x07011006), SH_UNT_MCA , SH_ACS_SCOM_RW ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_ACTION0_REG , RULL(0x07011006), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_ACTION0_REG , RULL(0x08011006), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); + +REG64( MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG , RULL(0x07011007), SH_UNT_MCA , SH_ACS_SCOM_RW ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_ACTION1_REG , RULL(0x07011007), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_ACTION1_REG , RULL(0x08011007), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); + +REG64( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG , RULL(0x07011003), SH_UNT_MCA , SH_ACS_SCOM_RW ); +REG64( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011004), SH_UNT_MCA , SH_ACS_SCOM1_AND ); +REG64( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011005), SH_UNT_MCA , SH_ACS_SCOM2_OR ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_MASK_REG , RULL(0x07011003), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011004), SH_UNT_MCA_0 , SH_ACS_SCOM1_AND ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011005), SH_UNT_MCA_0 , SH_ACS_SCOM2_OR ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_MASK_REG , RULL(0x08011003), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011004), SH_UNT_MCA_4 , SH_ACS_SCOM1_AND ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011005), SH_UNT_MCA_4 , SH_ACS_SCOM2_OR ); + +REG64( MCA_IOM_PHY0_DDRPHY_FIR_REG , RULL(0x07011000), SH_UNT_MCA , SH_ACS_SCOM_RW ); +REG64( MCA_IOM_PHY0_DDRPHY_FIR_REG_AND , RULL(0x07011001), SH_UNT_MCA , SH_ACS_SCOM1_AND ); +REG64( MCA_IOM_PHY0_DDRPHY_FIR_REG_OR , RULL(0x07011002), SH_UNT_MCA , SH_ACS_SCOM2_OR ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_REG , RULL(0x07011000), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_REG_AND , RULL(0x07011001), SH_UNT_MCA_0 , SH_ACS_SCOM1_AND ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_REG_OR , RULL(0x07011002), SH_UNT_MCA_0 , SH_ACS_SCOM2_OR ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_REG , RULL(0x08011000), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_REG_AND , RULL(0x08011001), SH_UNT_MCA_4 , SH_ACS_SCOM1_AND ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_REG_OR , RULL(0x08011002), SH_UNT_MCA_4 , SH_ACS_SCOM2_OR ); + +REG64( MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG , RULL(0x07011008), SH_UNT_MCA , + SH_ACS_SCOM_WCLRREG ); +REG64( MCA_0_IOM_PHY0_DDRPHY_FIR_WOF_REG , RULL(0x07011008), SH_UNT_MCA_0 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCA_4_IOM_PHY0_DDRPHY_FIR_WOF_REG , RULL(0x08011008), SH_UNT_MCA_4 , + SH_ACS_SCOM_WCLRREG ); + +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_ACTION0_REG , RULL(0x07011406), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_ACTION0_REG , RULL(0x08011406), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); + +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_ACTION1_REG , RULL(0x07011407), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_ACTION1_REG , RULL(0x08011407), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); + +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_MASK_REG , RULL(0x07011403), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011404), SH_UNT_MCA_1 , SH_ACS_SCOM1_AND ); +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011405), SH_UNT_MCA_1 , SH_ACS_SCOM2_OR ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_MASK_REG , RULL(0x08011403), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011404), SH_UNT_MCA_5 , SH_ACS_SCOM1_AND ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011405), SH_UNT_MCA_5 , SH_ACS_SCOM2_OR ); + +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_REG , RULL(0x07011400), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_REG_AND , RULL(0x07011401), SH_UNT_MCA_1 , SH_ACS_SCOM1_AND ); +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_REG_OR , RULL(0x07011402), SH_UNT_MCA_1 , SH_ACS_SCOM2_OR ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_REG , RULL(0x08011400), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_REG_AND , RULL(0x08011401), SH_UNT_MCA_5 , SH_ACS_SCOM1_AND ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_REG_OR , RULL(0x08011402), SH_UNT_MCA_5 , SH_ACS_SCOM2_OR ); + +REG64( MCA_1_IOM_PHY1_DDRPHY_FIR_WOF_REG , RULL(0x07011408), SH_UNT_MCA_1 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCA_5_IOM_PHY1_DDRPHY_FIR_WOF_REG , RULL(0x08011408), SH_UNT_MCA_5 , + SH_ACS_SCOM_WCLRREG ); + +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_ACTION0_REG , RULL(0x07011806), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_ACTION0_REG , RULL(0x08011806), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); + +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_ACTION1_REG , RULL(0x07011807), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_ACTION1_REG , RULL(0x08011807), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); + +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_MASK_REG , RULL(0x07011803), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011804), SH_UNT_MCA_2 , SH_ACS_SCOM1_AND ); +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011805), SH_UNT_MCA_2 , SH_ACS_SCOM2_OR ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_MASK_REG , RULL(0x08011803), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011804), SH_UNT_MCA_6 , SH_ACS_SCOM1_AND ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011805), SH_UNT_MCA_6 , SH_ACS_SCOM2_OR ); + +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_REG , RULL(0x07011800), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_REG_AND , RULL(0x07011801), SH_UNT_MCA_2 , SH_ACS_SCOM1_AND ); +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_REG_OR , RULL(0x07011802), SH_UNT_MCA_2 , SH_ACS_SCOM2_OR ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_REG , RULL(0x08011800), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_REG_AND , RULL(0x08011801), SH_UNT_MCA_6 , SH_ACS_SCOM1_AND ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_REG_OR , RULL(0x08011802), SH_UNT_MCA_6 , SH_ACS_SCOM2_OR ); + +REG64( MCA_2_IOM_PHY2_DDRPHY_FIR_WOF_REG , RULL(0x07011808), SH_UNT_MCA_2 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCA_6_IOM_PHY2_DDRPHY_FIR_WOF_REG , RULL(0x08011808), SH_UNT_MCA_6 , + SH_ACS_SCOM_WCLRREG ); + +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_ACTION0_REG , RULL(0x07011C06), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_ACTION0_REG , RULL(0x08011C06), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); + +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_ACTION1_REG , RULL(0x07011C07), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_ACTION1_REG , RULL(0x08011C07), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); + +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_MASK_REG , RULL(0x07011C03), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011C04), SH_UNT_MCA_3 , SH_ACS_SCOM1_AND ); +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011C05), SH_UNT_MCA_3 , SH_ACS_SCOM2_OR ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_MASK_REG , RULL(0x08011C03), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011C04), SH_UNT_MCA_7 , SH_ACS_SCOM1_AND ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011C05), SH_UNT_MCA_7 , SH_ACS_SCOM2_OR ); + +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_REG , RULL(0x07011C00), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_REG_AND , RULL(0x07011C01), SH_UNT_MCA_3 , SH_ACS_SCOM1_AND ); +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_REG_OR , RULL(0x07011C02), SH_UNT_MCA_3 , SH_ACS_SCOM2_OR ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_REG , RULL(0x08011C00), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_REG_AND , RULL(0x08011C01), SH_UNT_MCA_7 , SH_ACS_SCOM1_AND ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_REG_OR , RULL(0x08011C02), SH_UNT_MCA_7 , SH_ACS_SCOM2_OR ); + +REG64( MCA_3_IOM_PHY3_DDRPHY_FIR_WOF_REG , RULL(0x07011C08), SH_UNT_MCA_3 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCA_7_IOM_PHY3_DDRPHY_FIR_WOF_REG , RULL(0x08011C08), SH_UNT_MCA_7 , + SH_ACS_SCOM_WCLRREG ); + REG64( MCA_MASK , RULL(0x07010A03), SH_UNT_MCA , SH_ACS_SCOM_RW ); REG64( MCA_MASK_AND , RULL(0x07010A04), SH_UNT_MCA , SH_ACS_SCOM1_AND ); REG64( MCA_MASK_OR , RULL(0x07010A05), SH_UNT_MCA , SH_ACS_SCOM2_OR ); @@ -38931,6 +39041,16 @@ REG64( MCA_5_MBARPC0Q , RULL(0x08010974 REG64( MCA_6_MBARPC0Q , RULL(0x080109B4), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); REG64( MCA_7_MBARPC0Q , RULL(0x080109F4), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); +REG64( MCA_MBARSVD0 , RULL(0x07010933), SH_UNT_MCA , SH_ACS_SCOM_RO ); +REG64( MCA_0_MBARSVD0 , RULL(0x07010933), SH_UNT_MCA_0 , SH_ACS_SCOM_RO ); +REG64( MCA_1_MBARSVD0 , RULL(0x07010973), SH_UNT_MCA_1 , SH_ACS_SCOM_RO ); +REG64( MCA_2_MBARSVD0 , RULL(0x070109B3), SH_UNT_MCA_2 , SH_ACS_SCOM_RO ); +REG64( MCA_3_MBARSVD0 , RULL(0x070109F3), SH_UNT_MCA_3 , SH_ACS_SCOM_RO ); +REG64( MCA_4_MBARSVD0 , RULL(0x08010933), SH_UNT_MCA_4 , SH_ACS_SCOM_RO ); +REG64( MCA_5_MBARSVD0 , RULL(0x08010973), SH_UNT_MCA_5 , SH_ACS_SCOM_RO ); +REG64( MCA_6_MBARSVD0 , RULL(0x080109B3), SH_UNT_MCA_6 , SH_ACS_SCOM_RO ); +REG64( MCA_7_MBARSVD0 , RULL(0x080109F3), SH_UNT_MCA_7 , SH_ACS_SCOM_RO ); + REG64( MCA_MBASTR0Q , RULL(0x07010935), SH_UNT_MCA , SH_ACS_SCOM_RW ); REG64( MCA_0_MBASTR0Q , RULL(0x07010935), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); REG64( MCA_1_MBASTR0Q , RULL(0x07010975), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); @@ -39877,6 +39997,17 @@ REG64( MCS_3_MCFIRMASK , RULL(0x03010883 REG64( MCS_3_MCFIRMASK_AND , RULL(0x03010884), SH_UNT_MCS_3 , SH_ACS_SCOM1_AND ); REG64( MCS_3_MCFIRMASK_OR , RULL(0x03010885), SH_UNT_MCS_3 , SH_ACS_SCOM2_OR ); +REG64( MCS_MCFIRWOF , RULL(0x05010808), SH_UNT_MCS , + SH_ACS_SCOM_WCLRREG ); +REG64( MCS_0_MCFIRWOF , RULL(0x05010808), SH_UNT_MCS_0 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCS_1_MCFIRWOF , RULL(0x05010888), SH_UNT_MCS_1 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCS_2_MCFIRWOF , RULL(0x03010808), SH_UNT_MCS_2 , + SH_ACS_SCOM_WCLRREG ); +REG64( MCS_3_MCFIRWOF , RULL(0x03010888), SH_UNT_MCS_3 , + SH_ACS_SCOM_WCLRREG ); + REG64( MCS_MCLFSR , RULL(0x05010814), SH_UNT_MCS , SH_ACS_SCOM_RW ); REG64( MCS_0_MCLFSR , RULL(0x05010814), SH_UNT_MCS_0 , SH_ACS_SCOM_RW ); REG64( MCS_1_MCLFSR , RULL(0x05010894), SH_UNT_MCS_1 , SH_ACS_SCOM_RW ); @@ -40033,6 +40164,35 @@ REG64( MCS_PORT02_MCPERF3 , RULL(0x0501082B REG64( MCS_PORT13_MCPERF3 , RULL(0x0501083B), SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ); +REG64( MCS_MCRSVD19 , RULL(0x05010819), SH_UNT_MCS , SH_ACS_SCOM_RO ); +REG64( MCS_0_MCRSVD19 , RULL(0x05010819), SH_UNT_MCS_0 , SH_ACS_SCOM_RO ); +REG64( MCS_1_MCRSVD19 , RULL(0x05010899), SH_UNT_MCS_1 , SH_ACS_SCOM_RO ); +REG64( MCS_2_MCRSVD19 , RULL(0x03010819), SH_UNT_MCS_2 , SH_ACS_SCOM_RO ); +REG64( MCS_3_MCRSVD19 , RULL(0x03010899), SH_UNT_MCS_3 , SH_ACS_SCOM_RO ); + +REG64( MCS_0_PORT02_MCRSVD2F , RULL(0x0501082F), SH_UNT_MCS_0_PORT02, + SH_ACS_SCOM_RO ); +REG64( MCS_1_PORT02_MCRSVD2F , RULL(0x050108AF), SH_UNT_MCS_1_PORT02, + SH_ACS_SCOM_RO ); +REG64( MCS_2_PORT02_MCRSVD2F , RULL(0x0301082F), SH_UNT_MCS_2_PORT02, + SH_ACS_SCOM_RO ); +REG64( MCS_3_PORT02_MCRSVD2F , RULL(0x030108AF), SH_UNT_MCS_3_PORT02, + SH_ACS_SCOM_RO ); +REG64( MCS_PORT02_MCRSVD2F , RULL(0x0501082F), SH_UNT_MCS_PORT02, + SH_ACS_SCOM_RO ); + +REG64( MCS_MCRSVDE , RULL(0x0501080E), SH_UNT_MCS , SH_ACS_SCOM_RO ); +REG64( MCS_0_MCRSVDE , RULL(0x0501080E), SH_UNT_MCS_0 , SH_ACS_SCOM_RO ); +REG64( MCS_1_MCRSVDE , RULL(0x0501088E), SH_UNT_MCS_1 , SH_ACS_SCOM_RO ); +REG64( MCS_2_MCRSVDE , RULL(0x0301080E), SH_UNT_MCS_2 , SH_ACS_SCOM_RO ); +REG64( MCS_3_MCRSVDE , RULL(0x0301088E), SH_UNT_MCS_3 , SH_ACS_SCOM_RO ); + +REG64( MCS_MCRSVDF , RULL(0x0501080F), SH_UNT_MCS , SH_ACS_SCOM_RO ); +REG64( MCS_0_MCRSVDF , RULL(0x0501080F), SH_UNT_MCS_0 , SH_ACS_SCOM_RO ); +REG64( MCS_1_MCRSVDF , RULL(0x0501088F), SH_UNT_MCS_1 , SH_ACS_SCOM_RO ); +REG64( MCS_2_MCRSVDF , RULL(0x0301080F), SH_UNT_MCS_2 , SH_ACS_SCOM_RO ); +REG64( MCS_3_MCRSVDF , RULL(0x0301088F), SH_UNT_MCS_3 , SH_ACS_SCOM_RO ); + REG64( MCS_MCSYNC , RULL(0x05010815), SH_UNT_MCS , SH_ACS_SCOM_RW ); REG64( MCS_0_MCSYNC , RULL(0x05010815), SH_UNT_MCS_0 , SH_ACS_SCOM_RW ); REG64( MCS_1_MCSYNC , RULL(0x05010895), SH_UNT_MCS_1 , SH_ACS_SCOM_RW ); @@ -40094,116 +40254,6 @@ REG64( MCA_5_MSR , RULL(0x08010A4C REG64( MCA_6_MSR , RULL(0x08010A8C), SH_UNT_MCA_6 , SH_ACS_SCOM_RO ); REG64( MCA_7_MSR , RULL(0x08010ACC), SH_UNT_MCA_7 , SH_ACS_SCOM_RO ); -REG64( MCA_PHY0_DDRPHY_FIR_ACTION0_REG , RULL(0x07011006), SH_UNT_MCA , SH_ACS_SCOM_RW ); -REG64( MCA_0_PHY0_DDRPHY_FIR_ACTION0_REG , RULL(0x07011006), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); -REG64( MCA_4_PHY0_DDRPHY_FIR_ACTION0_REG , RULL(0x08011006), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); - -REG64( MCA_PHY0_DDRPHY_FIR_ACTION1_REG , RULL(0x07011007), SH_UNT_MCA , SH_ACS_SCOM_RW ); -REG64( MCA_0_PHY0_DDRPHY_FIR_ACTION1_REG , RULL(0x07011007), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); -REG64( MCA_4_PHY0_DDRPHY_FIR_ACTION1_REG , RULL(0x08011007), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); - -REG64( MCA_PHY0_DDRPHY_FIR_MASK_REG , RULL(0x07011003), SH_UNT_MCA , SH_ACS_SCOM_RW ); -REG64( MCA_PHY0_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011004), SH_UNT_MCA , SH_ACS_SCOM1_AND ); -REG64( MCA_PHY0_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011005), SH_UNT_MCA , SH_ACS_SCOM2_OR ); -REG64( MCA_0_PHY0_DDRPHY_FIR_MASK_REG , RULL(0x07011003), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); -REG64( MCA_0_PHY0_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011004), SH_UNT_MCA_0 , SH_ACS_SCOM1_AND ); -REG64( MCA_0_PHY0_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011005), SH_UNT_MCA_0 , SH_ACS_SCOM2_OR ); -REG64( MCA_4_PHY0_DDRPHY_FIR_MASK_REG , RULL(0x08011003), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); -REG64( MCA_4_PHY0_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011004), SH_UNT_MCA_4 , SH_ACS_SCOM1_AND ); -REG64( MCA_4_PHY0_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011005), SH_UNT_MCA_4 , SH_ACS_SCOM2_OR ); - -REG64( MCA_PHY0_DDRPHY_FIR_REG , RULL(0x07011000), SH_UNT_MCA , SH_ACS_SCOM_RW ); -REG64( MCA_PHY0_DDRPHY_FIR_REG_AND , RULL(0x07011001), SH_UNT_MCA , SH_ACS_SCOM1_AND ); -REG64( MCA_PHY0_DDRPHY_FIR_REG_OR , RULL(0x07011002), SH_UNT_MCA , SH_ACS_SCOM2_OR ); -REG64( MCA_0_PHY0_DDRPHY_FIR_REG , RULL(0x07011000), SH_UNT_MCA_0 , SH_ACS_SCOM_RW ); -REG64( MCA_0_PHY0_DDRPHY_FIR_REG_AND , RULL(0x07011001), SH_UNT_MCA_0 , SH_ACS_SCOM1_AND ); -REG64( MCA_0_PHY0_DDRPHY_FIR_REG_OR , RULL(0x07011002), SH_UNT_MCA_0 , SH_ACS_SCOM2_OR ); -REG64( MCA_4_PHY0_DDRPHY_FIR_REG , RULL(0x08011000), SH_UNT_MCA_4 , SH_ACS_SCOM_RW ); -REG64( MCA_4_PHY0_DDRPHY_FIR_REG_AND , RULL(0x08011001), SH_UNT_MCA_4 , SH_ACS_SCOM1_AND ); -REG64( MCA_4_PHY0_DDRPHY_FIR_REG_OR , RULL(0x08011002), SH_UNT_MCA_4 , SH_ACS_SCOM2_OR ); - -REG64( MCA_PHY0_DDRPHY_FIR_WOF_REG , RULL(0x07011008), SH_UNT_MCA , - SH_ACS_SCOM_WCLRREG ); -REG64( MCA_0_PHY0_DDRPHY_FIR_WOF_REG , RULL(0x07011008), SH_UNT_MCA_0 , - SH_ACS_SCOM_WCLRREG ); -REG64( MCA_4_PHY0_DDRPHY_FIR_WOF_REG , RULL(0x08011008), SH_UNT_MCA_4 , - SH_ACS_SCOM_WCLRREG ); - -REG64( MCA_1_PHY1_DDRPHY_FIR_ACTION0_REG , RULL(0x07011406), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); -REG64( MCA_5_PHY1_DDRPHY_FIR_ACTION0_REG , RULL(0x08011406), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); - -REG64( MCA_1_PHY1_DDRPHY_FIR_ACTION1_REG , RULL(0x07011407), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); -REG64( MCA_5_PHY1_DDRPHY_FIR_ACTION1_REG , RULL(0x08011407), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); - -REG64( MCA_1_PHY1_DDRPHY_FIR_MASK_REG , RULL(0x07011403), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); -REG64( MCA_1_PHY1_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011404), SH_UNT_MCA_1 , SH_ACS_SCOM1_AND ); -REG64( MCA_1_PHY1_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011405), SH_UNT_MCA_1 , SH_ACS_SCOM2_OR ); -REG64( MCA_5_PHY1_DDRPHY_FIR_MASK_REG , RULL(0x08011403), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); -REG64( MCA_5_PHY1_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011404), SH_UNT_MCA_5 , SH_ACS_SCOM1_AND ); -REG64( MCA_5_PHY1_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011405), SH_UNT_MCA_5 , SH_ACS_SCOM2_OR ); - -REG64( MCA_1_PHY1_DDRPHY_FIR_REG , RULL(0x07011400), SH_UNT_MCA_1 , SH_ACS_SCOM_RW ); -REG64( MCA_1_PHY1_DDRPHY_FIR_REG_AND , RULL(0x07011401), SH_UNT_MCA_1 , SH_ACS_SCOM1_AND ); -REG64( MCA_1_PHY1_DDRPHY_FIR_REG_OR , RULL(0x07011402), SH_UNT_MCA_1 , SH_ACS_SCOM2_OR ); -REG64( MCA_5_PHY1_DDRPHY_FIR_REG , RULL(0x08011400), SH_UNT_MCA_5 , SH_ACS_SCOM_RW ); -REG64( MCA_5_PHY1_DDRPHY_FIR_REG_AND , RULL(0x08011401), SH_UNT_MCA_5 , SH_ACS_SCOM1_AND ); -REG64( MCA_5_PHY1_DDRPHY_FIR_REG_OR , RULL(0x08011402), SH_UNT_MCA_5 , SH_ACS_SCOM2_OR ); - -REG64( MCA_1_PHY1_DDRPHY_FIR_WOF_REG , RULL(0x07011408), SH_UNT_MCA_1 , - SH_ACS_SCOM_WCLRREG ); -REG64( MCA_5_PHY1_DDRPHY_FIR_WOF_REG , RULL(0x08011408), SH_UNT_MCA_5 , - SH_ACS_SCOM_WCLRREG ); - -REG64( MCA_2_PHY2_DDRPHY_FIR_ACTION0_REG , RULL(0x07011806), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); -REG64( MCA_6_PHY2_DDRPHY_FIR_ACTION0_REG , RULL(0x08011806), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); - -REG64( MCA_2_PHY2_DDRPHY_FIR_ACTION1_REG , RULL(0x07011807), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); -REG64( MCA_6_PHY2_DDRPHY_FIR_ACTION1_REG , RULL(0x08011807), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); - -REG64( MCA_2_PHY2_DDRPHY_FIR_MASK_REG , RULL(0x07011803), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); -REG64( MCA_2_PHY2_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011804), SH_UNT_MCA_2 , SH_ACS_SCOM1_AND ); -REG64( MCA_2_PHY2_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011805), SH_UNT_MCA_2 , SH_ACS_SCOM2_OR ); -REG64( MCA_6_PHY2_DDRPHY_FIR_MASK_REG , RULL(0x08011803), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); -REG64( MCA_6_PHY2_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011804), SH_UNT_MCA_6 , SH_ACS_SCOM1_AND ); -REG64( MCA_6_PHY2_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011805), SH_UNT_MCA_6 , SH_ACS_SCOM2_OR ); - -REG64( MCA_2_PHY2_DDRPHY_FIR_REG , RULL(0x07011800), SH_UNT_MCA_2 , SH_ACS_SCOM_RW ); -REG64( MCA_2_PHY2_DDRPHY_FIR_REG_AND , RULL(0x07011801), SH_UNT_MCA_2 , SH_ACS_SCOM1_AND ); -REG64( MCA_2_PHY2_DDRPHY_FIR_REG_OR , RULL(0x07011802), SH_UNT_MCA_2 , SH_ACS_SCOM2_OR ); -REG64( MCA_6_PHY2_DDRPHY_FIR_REG , RULL(0x08011800), SH_UNT_MCA_6 , SH_ACS_SCOM_RW ); -REG64( MCA_6_PHY2_DDRPHY_FIR_REG_AND , RULL(0x08011801), SH_UNT_MCA_6 , SH_ACS_SCOM1_AND ); -REG64( MCA_6_PHY2_DDRPHY_FIR_REG_OR , RULL(0x08011802), SH_UNT_MCA_6 , SH_ACS_SCOM2_OR ); - -REG64( MCA_2_PHY2_DDRPHY_FIR_WOF_REG , RULL(0x07011808), SH_UNT_MCA_2 , - SH_ACS_SCOM_WCLRREG ); -REG64( MCA_6_PHY2_DDRPHY_FIR_WOF_REG , RULL(0x08011808), SH_UNT_MCA_6 , - SH_ACS_SCOM_WCLRREG ); - -REG64( MCA_3_PHY3_DDRPHY_FIR_ACTION0_REG , RULL(0x07011C06), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); -REG64( MCA_7_PHY3_DDRPHY_FIR_ACTION0_REG , RULL(0x08011C06), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); - -REG64( MCA_3_PHY3_DDRPHY_FIR_ACTION1_REG , RULL(0x07011C07), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); -REG64( MCA_7_PHY3_DDRPHY_FIR_ACTION1_REG , RULL(0x08011C07), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); - -REG64( MCA_3_PHY3_DDRPHY_FIR_MASK_REG , RULL(0x07011C03), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); -REG64( MCA_3_PHY3_DDRPHY_FIR_MASK_REG_AND , RULL(0x07011C04), SH_UNT_MCA_3 , SH_ACS_SCOM1_AND ); -REG64( MCA_3_PHY3_DDRPHY_FIR_MASK_REG_OR , RULL(0x07011C05), SH_UNT_MCA_3 , SH_ACS_SCOM2_OR ); -REG64( MCA_7_PHY3_DDRPHY_FIR_MASK_REG , RULL(0x08011C03), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); -REG64( MCA_7_PHY3_DDRPHY_FIR_MASK_REG_AND , RULL(0x08011C04), SH_UNT_MCA_7 , SH_ACS_SCOM1_AND ); -REG64( MCA_7_PHY3_DDRPHY_FIR_MASK_REG_OR , RULL(0x08011C05), SH_UNT_MCA_7 , SH_ACS_SCOM2_OR ); - -REG64( MCA_3_PHY3_DDRPHY_FIR_REG , RULL(0x07011C00), SH_UNT_MCA_3 , SH_ACS_SCOM_RW ); -REG64( MCA_3_PHY3_DDRPHY_FIR_REG_AND , RULL(0x07011C01), SH_UNT_MCA_3 , SH_ACS_SCOM1_AND ); -REG64( MCA_3_PHY3_DDRPHY_FIR_REG_OR , RULL(0x07011C02), SH_UNT_MCA_3 , SH_ACS_SCOM2_OR ); -REG64( MCA_7_PHY3_DDRPHY_FIR_REG , RULL(0x08011C00), SH_UNT_MCA_7 , SH_ACS_SCOM_RW ); -REG64( MCA_7_PHY3_DDRPHY_FIR_REG_AND , RULL(0x08011C01), SH_UNT_MCA_7 , SH_ACS_SCOM1_AND ); -REG64( MCA_7_PHY3_DDRPHY_FIR_REG_OR , RULL(0x08011C02), SH_UNT_MCA_7 , SH_ACS_SCOM2_OR ); - -REG64( MCA_3_PHY3_DDRPHY_FIR_WOF_REG , RULL(0x07011C08), SH_UNT_MCA_3 , - SH_ACS_SCOM_WCLRREG ); -REG64( MCA_7_PHY3_DDRPHY_FIR_WOF_REG , RULL(0x08011C08), SH_UNT_MCA_7 , - SH_ACS_SCOM_WCLRREG ); - REG64( MCA_PSCOM_ERROR_MASK , RULL(0x07010002), SH_UNT_MCA , SH_ACS_SCOM ); REG64( MCA_0_PSCOM_ERROR_MASK , RULL(0x07010002), SH_UNT_MCA_0 , SH_ACS_SCOM ); REG64( MCA_4_PSCOM_ERROR_MASK , RULL(0x08010002), SH_UNT_MCA_4 , SH_ACS_SCOM ); diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H index 5a531ee0..45f70471 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H @@ -3420,24 +3420,30 @@ REG64_FLD( MCA_CERR1_ECC_CTL_TCHN_PERR , 2 , SH_UN SH_FLD_ECC_CTL_TCHN_PERR ); REG64_FLD( MCA_CERR1_ECC_CTL_CMPMODE_ERR , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ECC_CTL_CMPMODE_ERR ); -REG64_FLD( MCA_CERR1_ECC_CTL_SCH_PERR , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ECC_CTL_SCH_PERR ); +REG64_FLD( MCA_CERR1_ECC_CTL_SCHCTL_PERR , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_SCHCTL_PERR ); REG64_FLD( MCA_CERR1_ECC_CTL_PCTL_PERR , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ECC_CTL_PCTL_PERR ); REG64_FLD( MCA_CERR1_ECC_CTL_TGST_PERR , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_ECC_CTL_TGST_PERR ); -REG64_FLD( MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_CERR1_ECC_CTL_SCHTAB_PERR , 7 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_SCHTAB_PERR ); +REG64_FLD( MCA_CERR1_ECC_PIPE_PCX_PERR , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_PCX_PERR ); +REG64_FLD( MCA_CERR1_ECC_PIPE_SYND_PERR , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_SYND_PERR ); +REG64_FLD( MCA_CERR1_ECC_PIPE_2SYM_PERR , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_2SYM_PERR ); +REG64_FLD( MCA_CERR1_ECC_PIPE_CPLX_PERR , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_CPLX_PERR ); +REG64_FLD( MCA_CERR1_ECC_PIPE_EP2_PERR , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_PIPE_EP2_PERR ); +REG64_FLD( MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR , 13 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR ); -REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_0 , 8 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ECC_PIPE_PARITY_ERROR_0 ); -REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_1 , 9 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ECC_PIPE_PARITY_ERROR_1 ); -REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_2 , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ECC_PIPE_PARITY_ERROR_2 ); -REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_3 , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_ECC_PIPE_PARITY_ERROR_3 ); -REG64_FLD( MCA_CERR1_PHY_PARITY_HOLD_OUT , 12 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_PHY_PARITY_HOLD_OUT ); +REG64_FLD( MCA_CERR1_PHY_RPTR_PARITY_ERROR , 14 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_PHY_RPTR_PARITY_ERROR ); +REG64_FLD( MCA_CERR1_ECC_CTL_RPD_PERR , 15 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_ECC_CTL_RPD_PERR ); REG64_FLD( MCA_CERR1_WDF_ASYNC_ERROR , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_WDF_ASYNC_ERROR ); REG64_FLD( MCA_CERR1_WDF_BUFFER_CE , 17 , SH_UNT_MCA , SH_ACS_SCOM_RO , @@ -3461,6 +3467,10 @@ REG64_FLD( MCBIST_CLKRATIO_RATIO , 0 , SH_UN SH_FLD_RATIO ); REG64_FLD( MCBIST_CLKRATIO_RATIO_LEN , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , SH_FLD_RATIO_LEN ); +REG64_FLD( MCBIST_CLKRATIO_CFG0_SYNC_MODE , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_CFG0_SYNC_MODE ); +REG64_FLD( MCBIST_CLKRATIO_CFG1_SYNC_MODE , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RO , + SH_FLD_CFG1_SYNC_MODE ); REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_ENABLE , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_DBG_ENABLE ); @@ -4327,6 +4337,8 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC , 56 SH_FLD_ADR0_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR0_CAL_CKTS_ACTIVE ); @@ -4346,6 +4358,8 @@ REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC , 56 SH_FLD_ADR1_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ADR1_CAL_CKTS_ACTIVE ); @@ -5049,22 +5063,18 @@ REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS_LE REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CNTL ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CNTL_LEN ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_INJECT_FIR_ERR0 ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_INJECT_FIR_ERR1 ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_INJECT_FIR_ERR2 ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_INJECT_FIR_ERR3 ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR4 , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_INJECT_FIR_ERR4 ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_VPROTH_CTL ); -REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_VPROTH_CTL_LEN ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0_4 , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR0_4 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1_5 , 55 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR1_5 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2_6 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR2_6 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3_7 , 57 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR3_7 ); +REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR , 58 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_INJECT_FIR_ERR ); REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DISABLE_PARITY_CHECKER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DISABLE_PARITY_CHECKER ); @@ -6693,101 +6703,141 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER , 48 , SH_FLD_01_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_LOWER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_23_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_UPPER ); REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_RESERVED_63 , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_4_RESERVED_63 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_SLAVE_VREG_OVERRIDE ); @@ -7335,6 +7385,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7356,6 +7408,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7377,6 +7431,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7398,6 +7454,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7419,6 +7477,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC , 56 , SH_ SH_FLD_4_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7440,6 +7500,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7461,6 +7523,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC , 56 , SH SH_FLD_01_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_01_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7482,6 +7546,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7503,6 +7569,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC , 56 , SH SH_FLD_23_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_23_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -7524,6 +7592,8 @@ REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC , 56 , SH_ SH_FLD_4_RXREG_REF_SEL_DC ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_RXREG_REF_SEL_DC_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY0 , 59 , SH_UNT_MCA , + SH_ACS_SCOM_RW , SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY0 ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_DRVREN_MODE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_DRVREN_MODE ); REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_CAL_CKTS_ACTIVE , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -18709,10 +18779,10 @@ REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC , 48 , SH_UN REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN , 16 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_PERIODIC_LEN ); -REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_PROTOCOL ); -REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_PROTOCOL_LEN ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PDA_ENABLE_OVERRIDE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PDA_ENABLE_OVERRIDE ); +REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PDA_ENABLE_OVERRIDE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PDA_ENABLE_OVERRIDE_LEN ); REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DATA_MUX4_1MODE , 52 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_DATA_MUX4_1MODE ); REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION , 54 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -19180,8 +19250,10 @@ REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB , 58 , SH_UN SH_FLD_WR_FIFO_STAB ); REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_RX , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RX ); -REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_TX_TRISTATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_TX_TRISTATE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DP_TX_TRISTATE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DP_TX_TRISTATE ); +REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ADR_TX_TRISTATE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_ADR_TX_TRISTATE ); REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VREG_S , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_VREG_S ); @@ -19798,6 +19870,8 @@ REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS , 62 , SH_UN REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL , 63 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_EN_RESET_WR_DELAY_WL ); +REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_PDA_RANKDELAY_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_PDA_RANKDELAY_ENABLE ); REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MRS_CMD_DQ_ON ); REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -22275,6 +22349,73 @@ REG64_FLD( MCA_HWMS7_CONFIRMED , 8 , SH_UN REG64_FLD( MCA_HWMS7_EXIT_1 , 9 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_EXIT_1 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0_LEN ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1_LEN ); + +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR0_LEN ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_DDR1_LEN ); + +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_CKSTP , 48 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_FSM_CKSTP ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_CKSTP , 49 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_PARITY_CKSTP ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR0_CALIBRATION_ERROR , 50 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_CALIBRATION_ERROR ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_ERR , 51 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_FSM_ERR ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_ERR , 52 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR0_PARITY_ERR ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR01_PARITY_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR01_PARITY_ERR ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_CKSTP , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_FSM_CKSTP ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_CKSTP , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_PARITY_CKSTP ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR1_CALIBRATION_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_CALIBRATION_ERROR ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_ERR , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_FSM_ERR ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_DDR1_PARITY_ERR ); + +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_0 , 54 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_0 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_1 , 55 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_1 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_2 , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_2 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_3 , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_3 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_4 , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_4 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_5 , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_5 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_6 , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_6 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_REG_ERROR_7 , 61 , SH_UNT_MCA , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_7 ); + +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR0 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR0_LEN ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR1 ); +REG64_FLD( MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, + SH_FLD_DDR1_LEN ); + REG64_FLD( MCA_MASK_FIR , 0 , SH_UNT_MCA , SH_ACS_SCOM2_OR , SH_FLD_FIR ); REG64_FLD( MCA_MASK_FIR_LEN , 64 , SH_UNT_MCA , SH_ACS_SCOM2_OR , @@ -22509,10 +22650,12 @@ REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL , 57 , SH_UN SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL ); REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN ); -REG64_FLD( MCA_MBASTR0Q_RESERVED_61_63 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_61_63 ); -REG64_FLD( MCA_MBASTR0Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_61_63_LEN ); +REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TB_SEL , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_OCC_DEADMAN_TB_SEL ); +REG64_FLD( MCA_MBASTR0Q_RESERVED_62_63 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63 ); +REG64_FLD( MCA_MBASTR0Q_RESERVED_62_63_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63_LEN ); REG64_FLD( MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP ); @@ -22618,12 +22761,10 @@ REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_SPEC_ATTN , 59 , SH_UN SH_FLD_CFG_ENABLE_SPEC_ATTN ); REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_HOST_ATTN , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_ENABLE_HOST_ATTN ); -REG64_FLD( MCA_MBA_CAL0Q_CFG_DISABLE_RESET_RECOVER , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_CFG_DISABLE_RESET_RECOVER ); -REG64_FLD( MCA_MBA_CAL0Q_RESERVED_62_63 , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_62_63 ); -REG64_FLD( MCA_MBA_CAL0Q_RESERVED_62_63_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_62_63_LEN ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_61_63 , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63 ); +REG64_FLD( MCA_MBA_CAL0Q_RESERVED_61_63_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63_LEN ); REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE ); @@ -22991,8 +23132,8 @@ REG64_FLD( MCA_MBA_ERR_REPORTQ_RCMD_ASYNC_IF , 24 , SH_UN SH_FLD_RCMD_ASYNC_IF ); REG64_FLD( MCA_MBA_ERR_REPORTQ_PF_PROMOTE_ASYNC_IF , 25 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_PF_PROMOTE_ASYNC_IF ); -REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_26 , 26 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_26 ); +REG64_FLD( MCA_MBA_ERR_REPORTQ_CANCEL_ACK_ASYNC_IF , 26 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CANCEL_ACK_ASYNC_IF ); REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT , 27 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_FARB_CMD_PE_HOLD_OUT ); REG64_FLD( MCA_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT , 28 , SH_UNT_MCA , SH_ACS_SCOM_RO , @@ -23032,10 +23173,10 @@ REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_WEN , 39 , SH_UN SH_FLD_CFG_INJECT_PARITY_ERR_WEN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 , 40 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 ); -REG64_FLD( MCA_MBA_FARB0Q_RESERVED_41_42 , 41 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_41_42 ); -REG64_FLD( MCA_MBA_FARB0Q_RESERVED_41_42_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_41_42_LEN ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE , 41 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BW_WINDOW_SIZE ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_BW_WINDOW_SIZE_LEN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME , 43 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_PARITY_DETECT_TIME ); REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -23056,13 +23197,11 @@ REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN , 58 , SH_UN SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN ); REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT , 59 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT ); -REG64_FLD( MCA_MBA_FARB0Q_RESERVED_60_61 , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_60_61 ); -REG64_FLD( MCA_MBA_FARB0Q_RESERVED_60_61_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_60_61_LEN ); -REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE , 62 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB0Q_CFG_FINISH_WR_BEFORE_RD , 60 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_CFG_FINISH_WR_BEFORE_RD ); +REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE , 61 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OPT_RD_SIZE ); -REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , +REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_CFG_OPT_RD_SIZE_LEN ); REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -23286,28 +23425,28 @@ REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63_LEN , 7 , SH_UN REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT , 0 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_BW_SNAPSHOT ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_BW_SNAPSHOT_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE , 10 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE , 11 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_CKE_PUP_STATE ); REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_CKE_PUP_STATE_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_STR_STATE , 14 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_MBA_FARB6Q_CFG_STR_STATE , 15 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_STR_STATE ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH , 15 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH , 16 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_RRQ_DEPTH ); REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_RRQ_DEPTH_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH , 20 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH , 21 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_WRQ_DEPTH ); -REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RO , +REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_WRQ_DEPTH_LEN ); REG64_FLD( MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY , 26 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_RCD_PARITY_DLY ); REG64_FLD( MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_CFG_RCD_PARITY_DLY_LEN ); -REG64_FLD( MCA_MBA_FARB6Q_RESERVED_31 , 31 , SH_UNT_MCA , SH_ACS_SCOM_RO , - SH_FLD_RESERVED_31 ); +REG64_FLD( MCA_MBA_FARB6Q_CFG_EVENTN , 31 , SH_UNT_MCA , SH_ACS_SCOM_RO , + SH_FLD_CFG_EVENTN ); REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP , 0 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_EMER_THROTTLE_IP ); @@ -24369,8 +24508,8 @@ REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN , 4 , SH_UN SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN ); REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE , 32 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_PAUSE_ON_SCE ); -REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_CFG_PAUSE_ON_MCE ); +REG64_FLD( MCBIST_MBSTRQ_RESERVED_33 , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_33 ); REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_PAUSE_ON_MPE ); REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_UE , 35 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -24446,10 +24585,12 @@ REG64_FLD( MCBIST_MBUER3Q_RESERVED_38_39_LEN , 2 , SH_UN REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_CLEAN , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_ENABLE_CLEAN ); -REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_READ_DATA_FROM_AMOC , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_ENABLE_READ_DATA_FROM_AMOC ); -REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_READ_DATA_FROM_AMOC_LEN , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN ); +REG64_FLD( MCS_PORT02_MCAMOC_FORCE_PF_DROP0 , 1 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_FORCE_PF_DROP0 ); +REG64_FLD( MCS_PORT02_MCAMOC_FORCE_PF_DROP1 , 2 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_FORCE_PF_DROP1 ); +REG64_FLD( MCS_PORT02_MCAMOC_RESERVED0 , 3 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED0 ); REG64_FLD( MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_WRTO_AMO_COLLISION_RULES ); REG64_FLD( MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN , 25 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , @@ -24463,10 +24604,12 @@ REG64_FLD( MCS_PORT02_MCAMOC_RESERVED1_LEN , 2 , SH_UN REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_CLEAN , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_ENABLE_CLEAN ); -REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_READ_DATA_FROM_AMOC , 1 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_ENABLE_READ_DATA_FROM_AMOC ); -REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_READ_DATA_FROM_AMOC_LEN , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN ); +REG64_FLD( MCS_PORT13_MCAMOC_FORCE_PF_DROP0 , 1 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_FORCE_PF_DROP0 ); +REG64_FLD( MCS_PORT13_MCAMOC_FORCE_PF_DROP1 , 2 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_FORCE_PF_DROP1 ); +REG64_FLD( MCS_PORT13_MCAMOC_RESERVED0 , 3 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_RESERVED0 ); REG64_FLD( MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_WRTO_AMO_COLLISION_RULES ); REG64_FLD( MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN , 25 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , @@ -24690,10 +24833,12 @@ REG64_FLD( MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS , 11 , SH_UN SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS ); REG64_FLD( MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS , 12 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_CCS_RETRY_DIS ); -REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_34 , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_13_34 ); -REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_34_LEN , 22 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_13_34_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_33 , 13 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_13_33 ); +REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_33_LEN , 21 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_13_33_LEN ); +REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK , 34 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK ); REG64_FLD( MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK , 35 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_RESET_CNTS_START_OF_RANK ); REG64_FLD( MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE , 36 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , @@ -26052,6 +26197,8 @@ REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN_LEN , 16 , SH_UN SH_FLD_EVENT_BUS_EN_LEN ); REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_ENABLE , 16 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , SH_FLD_EVENT_BUS_ENABLE ); +REG64_FLD( MCS_PORT13_MCEBUSEN3_EBUS_16A_SELECT , 17 , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW , + SH_FLD_EBUS_16A_SELECT ); REG64_FLD( MCS_PORT02_MCEPSQ_JITTER_EPSILON , 0 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_JITTER_EPSILON ); @@ -26130,12 +26277,12 @@ REG64_FLD( MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0 , 8 , SH_UN SH_FLD_WRITE_ERR_INJECT0 ); REG64_FLD( MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_WRITE_ERR_INJECT0_LEN ); -REG64_FLD( MCS_PORT02_MCERRINJ_RCMD_ERR_INJ , 12 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , +REG64_FLD( MCS_PORT02_MCERRINJ_READ_PAR_NOT_SEQ , 12 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_READ_PAR_NOT_SEQ ); +REG64_FLD( MCS_PORT02_MCERRINJ_RCMD_ERR_INJ , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_RCMD_ERR_INJ ); -REG64_FLD( MCS_PORT02_MCERRINJ_PF_PROMOTE_ERR_INJ , 13 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , +REG64_FLD( MCS_PORT02_MCERRINJ_PF_PROMOTE_ERR_INJ , 14 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_PF_PROMOTE_ERR_INJ ); -REG64_FLD( MCS_PORT02_MCERRINJ_READ_PAR_NOT_SEQ , 14 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_READ_PAR_NOT_SEQ ); REG64_FLD( MCS_PORT02_MCERRINJ_RESET_KEEPER , 15 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_RESET_KEEPER ); @@ -26151,12 +26298,12 @@ REG64_FLD( MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0 , 8 , SH_UN SH_FLD_WRITE_ERR_INJECT0 ); REG64_FLD( MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_WRITE_ERR_INJECT0_LEN ); -REG64_FLD( MCS_PORT13_MCERRINJ_RCMD_ERR_INJ , 12 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , +REG64_FLD( MCS_PORT13_MCERRINJ_READ_PAR_NOT_SEQ , 12 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_READ_PAR_NOT_SEQ ); +REG64_FLD( MCS_PORT13_MCERRINJ_RCMD_ERR_INJ , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_RCMD_ERR_INJ ); -REG64_FLD( MCS_PORT13_MCERRINJ_PF_PROMOTE_ERR_INJ , 13 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , +REG64_FLD( MCS_PORT13_MCERRINJ_PF_PROMOTE_ERR_INJ , 14 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_PF_PROMOTE_ERR_INJ ); -REG64_FLD( MCS_PORT13_MCERRINJ_READ_PAR_NOT_SEQ , 14 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_READ_PAR_NOT_SEQ ); REG64_FLD( MCS_PORT13_MCERRINJ_RESET_KEEPER , 15 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_RESET_KEEPER ); @@ -26336,6 +26483,11 @@ REG64_FLD( MCS_MCFIRMASK_FIR_MASK , 0 , SH_UN REG64_FLD( MCS_MCFIRMASK_FIR_MASK_LEN , 26 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); +REG64_FLD( MCS_MCFIRWOF_WOF , 0 , SH_UNT_MCS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( MCS_MCFIRWOF_WOF_LEN , 26 , SH_UNT_MCS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RETRY_LPC_LFSR_SELECT ); REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , @@ -27145,8 +27297,8 @@ REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3 , 27 , SH_UN SH_FLD_PF_CONF_RETRY_THRESH3 ); REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3_LEN , 4 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , SH_FLD_PF_CONF_RETRY_THRESH3_LEN ); -REG64_FLD( MCS_PORT02_MCPERF3_RESERVED31 , 31 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED31 ); +REG64_FLD( MCS_PORT02_MCPERF3_EN_WRITE_MDI1_RETRY_UE , 31 , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW , + SH_FLD_EN_WRITE_MDI1_RETRY_UE ); REG64_FLD( MCS_PORT13_MCPERF3_EN_DROP_PLS_F_FULL , 0 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_EN_DROP_PLS_F_FULL ); @@ -27186,8 +27338,8 @@ REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3 , 27 , SH_UN SH_FLD_PF_CONF_RETRY_THRESH3 ); REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3_LEN , 4 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , SH_FLD_PF_CONF_RETRY_THRESH3_LEN ); -REG64_FLD( MCS_PORT13_MCPERF3_RESERVED31 , 31 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , - SH_FLD_RESERVED31 ); +REG64_FLD( MCS_PORT13_MCPERF3_EN_WRITE_MDI1_RETRY_UE , 31 , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW , + SH_FLD_EN_WRITE_MDI1_RETRY_UE ); REG64_FLD( MCS_MCSYNC_CHANNEL_SELECT , 0 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_CHANNEL_SELECT ); @@ -27400,10 +27552,24 @@ REG64_FLD( MCS_MCWATCNTL_RCTRL_DEBUG_SEL , 36 , SH_UN SH_FLD_RCTRL_DEBUG_SEL ); REG64_FLD( MCS_MCWATCNTL_RCTRL_DEBUG_SEL_LEN , 3 , SH_UNT_MCS , SH_ACS_SCOM_RW , SH_FLD_RCTRL_DEBUG_SEL_LEN ); -REG64_FLD( MCS_MCWATCNTL_RESERVED_39_63 , 39 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_39_63 ); -REG64_FLD( MCS_MCWATCNTL_RESERVED_39_63_LEN , 25 , SH_UNT_MCS , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_39_63_LEN ); +REG64_FLD( MCS_MCWATCNTL_AND_WAT_OUTPUTS , 39 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_AND_WAT_OUTPUTS ); +REG64_FLD( MCS_MCWATCNTL_DEBUG_COUNTER_CONTROLS , 40 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_COUNTER_CONTROLS ); +REG64_FLD( MCS_MCWATCNTL_DEBUG_COUNTER_CONTROLS_LEN , 16 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_COUNTER_CONTROLS_LEN ); +REG64_FLD( MCS_MCWATCNTL_RESERVED_56_59 , 56 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_59 ); +REG64_FLD( MCS_MCWATCNTL_RESERVED_56_59_LEN , 4 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_59_LEN ); +REG64_FLD( MCS_MCWATCNTL_DEBUG_COUNTER_EN , 60 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_COUNTER_EN ); +REG64_FLD( MCS_MCWATCNTL_DEBUG_COUNTER_RESET , 61 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_DEBUG_COUNTER_RESET ); +REG64_FLD( MCS_MCWATCNTL_RESERVED_62_63 , 62 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63 ); +REG64_FLD( MCS_MCWATCNTL_RESERVED_62_63_LEN , 2 , SH_UNT_MCS , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_62_63_LEN ); REG64_FLD( MCS_MCWATDATA_MCWATDATA0 , 0 , SH_UNT_MCS , SH_ACS_SCOM_RO , SH_FLD_MCWATDATA0 ); @@ -27419,79 +27585,6 @@ REG64_FLD( MCA_MSR_RANK , 16 , SH_UN REG64_FLD( MCA_MSR_RANK_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RO , SH_FLD_RANK_LEN ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR0 ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR0_LEN ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR1 ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR1_LEN ); - -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR0 ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR0_LEN ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR1 ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_DDR1_LEN ); - -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_CKSTP , 48 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_FSM_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_CKSTP , 49 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_PARITY_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_CALIBRATION_ERROR , 50 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_CALIBRATION_ERROR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_ERR , 51 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_FSM_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_ERR , 52 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_PARITY_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR01_PARITY_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR01_PARITY_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_CKSTP , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_FSM_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_CKSTP , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_PARITY_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_CALIBRATION_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_CALIBRATION_ERROR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_ERR , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_FSM_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_PARITY_ERR ); - -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_FSM_CKSTP , 48 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_FSM_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_PARITY_CKSTP , 49 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_PARITY_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_CALIBRATION_ERROR , 50 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_CALIBRATION_ERROR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_FSM_ERR , 51 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_FSM_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_PARITY_ERR , 52 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR0_PARITY_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR01_PARITY_ERR , 53 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR01_PARITY_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_FSM_CKSTP , 56 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_FSM_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_PARITY_CKSTP , 57 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_PARITY_CKSTP ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_CALIBRATION_ERROR , 58 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_CALIBRATION_ERROR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_FSM_ERR , 59 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_FSM_ERR ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_PARITY_ERR , 60 , SH_UNT_MCA , SH_ACS_SCOM2_OR , - SH_FLD_DDR1_PARITY_ERR ); - -REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, - SH_FLD_DDR0 ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR0_LEN , 6 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, - SH_FLD_DDR0_LEN ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR1 , 56 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, - SH_FLD_DDR1 ); -REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR1_LEN , 5 , SH_UNT_MCA , SH_ACS_SCOM_WCLRREG, - SH_FLD_DDR1_LEN ); - REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_MCA , SH_ACS_SCOM , @@ -27700,8 +27793,8 @@ REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_UE_RETRY , 3 , SH_UN SH_FLD_MBSECCQ_DISABLE_UE_RETRY ); REG64_FLD( MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_5 , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_5 ); +REG64_FLD( MCA_RECR_MBSECCQ_SLOW_EXIT_REDUCTION , 5 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_SLOW_EXIT_REDUCTION ); REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY , 6 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_READ_POINTER_DELAY ); REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , @@ -27750,13 +27843,17 @@ REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION_LEN , 2 , SH_UN SH_FLD_MBSECCQ_DATA_INVERSION_LEN ); REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING , 32 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39 , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_33_39 ); -REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_MBSECCQ_RESERVED_33_39_LEN ); +REG64_FLD( MCA_RECR_MBSECCQ_MAINT_NO_RETRY_UE , 33 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_MAINT_NO_RETRY_UE ); +REG64_FLD( MCA_RECR_MBSECCQ_MAINT_NO_RETRY_MPE , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_MAINT_NO_RETRY_MPE ); +REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_BYPASS_TEMPLATE_A , 35 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_DISABLE_BYPASS_TEMPLATE_A ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_36_43 , 36 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_36_43 ); +REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_36_43_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MBSECCQ_RESERVED_36_43_LEN ); -REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_MCA , SH_ACS_SCOM , @@ -27797,8 +27894,28 @@ REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_MCA , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -27890,6 +28007,14 @@ REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_ SH_FLD_MATCH_NOT_MODE ); REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_MCA , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_MCA , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL , 0 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , SH_FLD_CFG_WAT_EVENT_SEL ); @@ -28165,8 +28290,8 @@ REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_COR_DIS , 1 , SH_UN SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS ); REG64_FLD( MCA_WRTCFG_RESET_KEEPER , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_RESET_KEEPER ); -REG64_FLD( MCA_WRTCFG_SPARE , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , - SH_FLD_SPARE ); +REG64_FLD( MCA_WRTCFG_MPIPL , 3 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_MPIPL ); REG64_FLD( MCA_WRTCFG_ASYNC_INJ , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_ASYNC_INJ ); REG64_FLD( MCA_WRTCFG_ASYNC_INJ_LEN , 4 , SH_UNT_MCA , SH_ACS_SCOM_RW , diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index e2a91e3c..82f24380 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -45,7 +45,10 @@ //FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE, // 12); + static const uint64_t SH_FLD_COMMAND_LIST_TIMEOUT_SPEC = 99990000; +static const uint64_t SH_FLD_CFG_PAUSE_ON_MCE = 99990001; + REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC , 9 , SH_UNT_MCS , SH_ACS_SCOM2_OR , SH_FLD_COMMAND_LIST_TIMEOUT_SPEC ); @@ -61,4 +64,8 @@ REG64_FLD( MCA_DDRPHY_WC_RTT_WR_CTL_SWAP_ENABLE_P0 , 49 , SH_UN REG64_FLD( MCBIST_MCBCFGQ_CFG_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK , 34 , SH_UNT_MCA , SH_ACS_SCOM_RW , 0 ); +REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE , 33 , SH_UNT_MCBIST , SH_ACS_SCOM_RW , + SH_FLD_CFG_PAUSE_ON_MCE ); + + #endif diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses.H index 89806796..852af502 100644 --- a/src/import/chips/p9/common/include/p9_misc_scom_addresses.H +++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses.H @@ -464,34 +464,34 @@ REG64( PHB_4_BARE_REG , RULL(0x04011494 REG64( PHB_5_BARE_REG , RULL(0x040114D4), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); REG64( PU_BCDE_CTL_OCI , RULL(0xC0040080), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCDE_CTL_PIB , RULL(0x00064010), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCDE_CTL_PIB , RULL(0x00068010), SH_UNT , SH_ACS_PIB ); REG64( PU_BCDE_OCIBAR_OCI , RULL(0xC00400A0), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCDE_OCIBAR_PIB , RULL(0x00064014), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCDE_OCIBAR_PIB , RULL(0x00068014), SH_UNT , SH_ACS_PIB ); REG64( PU_BCDE_PBADR_OCI , RULL(0xC0040098), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCDE_PBADR_PIB , RULL(0x00064013), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCDE_PBADR_PIB , RULL(0x00068013), SH_UNT , SH_ACS_PIB ); REG64( PU_BCDE_SET_OCI , RULL(0xC0040088), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCDE_SET_PIB , RULL(0x00064011), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCDE_SET_PIB , RULL(0x00068011), SH_UNT , SH_ACS_PIB ); REG64( PU_BCDE_STAT_OCI , RULL(0xC0040090), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCDE_STAT_PIB , RULL(0x00064012), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCDE_STAT_PIB , RULL(0x00068012), SH_UNT , SH_ACS_PIB ); REG64( PU_BCUE_CTL_OCI , RULL(0xC00400A8), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCUE_CTL_PIB , RULL(0x00064015), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCUE_CTL_PIB , RULL(0x00068015), SH_UNT , SH_ACS_PIB ); REG64( PU_BCUE_OCIBAR_OCI , RULL(0xC00400C8), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCUE_OCIBAR_PIB , RULL(0x00064019), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCUE_OCIBAR_PIB , RULL(0x00068019), SH_UNT , SH_ACS_PIB ); REG64( PU_BCUE_PBADR_OCI , RULL(0xC00400C0), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCUE_PBADR_PIB , RULL(0x00064018), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCUE_PBADR_PIB , RULL(0x00068018), SH_UNT , SH_ACS_PIB ); REG64( PU_BCUE_SET_OCI , RULL(0xC00400B0), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCUE_SET_PIB , RULL(0x00064016), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCUE_SET_PIB , RULL(0x00068016), SH_UNT , SH_ACS_PIB ); REG64( PU_BCUE_STAT_OCI , RULL(0xC00400B8), SH_UNT , SH_ACS_OCI ); -REG64( PU_BCUE_STAT_PIB , RULL(0x00064017), SH_UNT , SH_ACS_PIB ); +REG64( PU_BCUE_STAT_PIB , RULL(0x00068017), SH_UNT , SH_ACS_PIB ); REG64( PU_NPU_BDF2PE_00_CONFIG , RULL(0x050113A0), SH_UNT_PU_NPU , SH_ACS_SCOM ); REG64( PU_NPU0_CTL_BDF2PE_00_CONFIG , RULL(0x0501108A), SH_UNT_PU_NPU0_CTL, @@ -1720,31 +1720,6 @@ REG64( PU_CME10_CME_LCL_ICSR_PPE , RULL(0x10E01072 REG64( PU_CME11_CME_LCL_ICSR_PPE , RULL(0x10E020720), SH_UNT_PU_CME11 , SH_ACS_PPE ); -REG64( PU_CME0_CME_LCL_LMCR_PPE , RULL(0x1090101A0), SH_UNT_PU_CME0 , - SH_ACS_PPE ); -REG64( PU_CME1_CME_LCL_LMCR_PPE , RULL(0x1090201A0), SH_UNT_PU_CME1 , - SH_ACS_PPE ); -REG64( PU_CME2_CME_LCL_LMCR_PPE , RULL(0x10A0101A0), SH_UNT_PU_CME2 , - SH_ACS_PPE ); -REG64( PU_CME3_CME_LCL_LMCR_PPE , RULL(0x10A0201A0), SH_UNT_PU_CME3 , - SH_ACS_PPE ); -REG64( PU_CME4_CME_LCL_LMCR_PPE , RULL(0x10B0101A0), SH_UNT_PU_CME4 , - SH_ACS_PPE ); -REG64( PU_CME5_CME_LCL_LMCR_PPE , RULL(0x10B0201A0), SH_UNT_PU_CME5 , - SH_ACS_PPE ); -REG64( PU_CME6_CME_LCL_LMCR_PPE , RULL(0x10C0101A0), SH_UNT_PU_CME6 , - SH_ACS_PPE ); -REG64( PU_CME7_CME_LCL_LMCR_PPE , RULL(0x10C0201A0), SH_UNT_PU_CME7 , - SH_ACS_PPE ); -REG64( PU_CME8_CME_LCL_LMCR_PPE , RULL(0x10D0101A0), SH_UNT_PU_CME8 , - SH_ACS_PPE ); -REG64( PU_CME9_CME_LCL_LMCR_PPE , RULL(0x10D0201A0), SH_UNT_PU_CME9 , - SH_ACS_PPE ); -REG64( PU_CME10_CME_LCL_LMCR_PPE , RULL(0x10E0101A0), SH_UNT_PU_CME10 , - SH_ACS_PPE ); -REG64( PU_CME11_CME_LCL_LMCR_PPE , RULL(0x10E0201A0), SH_UNT_PU_CME11 , - SH_ACS_PPE ); - REG64( PU_CME0_CME_LCL_PECESR0_PPE , RULL(0x109010280), SH_UNT_PU_CME0 , SH_ACS_PPE ); REG64( PU_CME1_CME_LCL_PECESR0_PPE , RULL(0x109020280), SH_UNT_PU_CME1 , @@ -2043,6 +2018,79 @@ REG64( PU_CME10_CME_SCOM_IDCR_PPE , RULL(0x10E0106A REG64( PU_CME11_CME_SCOM_IDCR_PPE , RULL(0x10E0206A0), SH_UNT_PU_CME11 , SH_ACS_PPE ); +REG64( PU_CME0_CME_SCOM_LMCR_PPE , RULL(0x1090101A0), SH_UNT_PU_CME0 , + SH_ACS_PPE ); +REG64( PU_CME0_CME_SCOM_LMCR_PPE1 , RULL(0x1090101B8), SH_UNT_PU_CME0 , + SH_ACS_PPE1 ); +REG64( PU_CME0_CME_SCOM_LMCR_PPE2 , RULL(0x1090101B0), SH_UNT_PU_CME0 , + SH_ACS_PPE2 ); +REG64( PU_CME1_CME_SCOM_LMCR_PPE , RULL(0x1090201A0), SH_UNT_PU_CME1 , + SH_ACS_PPE ); +REG64( PU_CME1_CME_SCOM_LMCR_PPE1 , RULL(0x1090201B8), SH_UNT_PU_CME1 , + SH_ACS_PPE1 ); +REG64( PU_CME1_CME_SCOM_LMCR_PPE2 , RULL(0x1090201B0), SH_UNT_PU_CME1 , + SH_ACS_PPE2 ); +REG64( PU_CME2_CME_SCOM_LMCR_PPE , RULL(0x10A0101A0), SH_UNT_PU_CME2 , + SH_ACS_PPE ); +REG64( PU_CME2_CME_SCOM_LMCR_PPE1 , RULL(0x10A0101B8), SH_UNT_PU_CME2 , + SH_ACS_PPE1 ); +REG64( PU_CME2_CME_SCOM_LMCR_PPE2 , RULL(0x10A0101B0), SH_UNT_PU_CME2 , + SH_ACS_PPE2 ); +REG64( PU_CME3_CME_SCOM_LMCR_PPE , RULL(0x10A0201A0), SH_UNT_PU_CME3 , + SH_ACS_PPE ); +REG64( PU_CME3_CME_SCOM_LMCR_PPE1 , RULL(0x10A0201B8), SH_UNT_PU_CME3 , + SH_ACS_PPE1 ); +REG64( PU_CME3_CME_SCOM_LMCR_PPE2 , RULL(0x10A0201B0), SH_UNT_PU_CME3 , + SH_ACS_PPE2 ); +REG64( PU_CME4_CME_SCOM_LMCR_PPE , RULL(0x10B0101A0), SH_UNT_PU_CME4 , + SH_ACS_PPE ); +REG64( PU_CME4_CME_SCOM_LMCR_PPE1 , RULL(0x10B0101B8), SH_UNT_PU_CME4 , + SH_ACS_PPE1 ); +REG64( PU_CME4_CME_SCOM_LMCR_PPE2 , RULL(0x10B0101B0), SH_UNT_PU_CME4 , + SH_ACS_PPE2 ); +REG64( PU_CME5_CME_SCOM_LMCR_PPE , RULL(0x10B0201A0), SH_UNT_PU_CME5 , + SH_ACS_PPE ); +REG64( PU_CME5_CME_SCOM_LMCR_PPE1 , RULL(0x10B0201B8), SH_UNT_PU_CME5 , + SH_ACS_PPE1 ); +REG64( PU_CME5_CME_SCOM_LMCR_PPE2 , RULL(0x10B0201B0), SH_UNT_PU_CME5 , + SH_ACS_PPE2 ); +REG64( PU_CME6_CME_SCOM_LMCR_PPE , RULL(0x10C0101A0), SH_UNT_PU_CME6 , + SH_ACS_PPE ); +REG64( PU_CME6_CME_SCOM_LMCR_PPE1 , RULL(0x10C0101B8), SH_UNT_PU_CME6 , + SH_ACS_PPE1 ); +REG64( PU_CME6_CME_SCOM_LMCR_PPE2 , RULL(0x10C0101B0), SH_UNT_PU_CME6 , + SH_ACS_PPE2 ); +REG64( PU_CME7_CME_SCOM_LMCR_PPE , RULL(0x10C0201A0), SH_UNT_PU_CME7 , + SH_ACS_PPE ); +REG64( PU_CME7_CME_SCOM_LMCR_PPE1 , RULL(0x10C0201B8), SH_UNT_PU_CME7 , + SH_ACS_PPE1 ); +REG64( PU_CME7_CME_SCOM_LMCR_PPE2 , RULL(0x10C0201B0), SH_UNT_PU_CME7 , + SH_ACS_PPE2 ); +REG64( PU_CME8_CME_SCOM_LMCR_PPE , RULL(0x10D0101A0), SH_UNT_PU_CME8 , + SH_ACS_PPE ); +REG64( PU_CME8_CME_SCOM_LMCR_PPE1 , RULL(0x10D0101B8), SH_UNT_PU_CME8 , + SH_ACS_PPE1 ); +REG64( PU_CME8_CME_SCOM_LMCR_PPE2 , RULL(0x10D0101B0), SH_UNT_PU_CME8 , + SH_ACS_PPE2 ); +REG64( PU_CME9_CME_SCOM_LMCR_PPE , RULL(0x10D0201A0), SH_UNT_PU_CME9 , + SH_ACS_PPE ); +REG64( PU_CME9_CME_SCOM_LMCR_PPE1 , RULL(0x10D0201B8), SH_UNT_PU_CME9 , + SH_ACS_PPE1 ); +REG64( PU_CME9_CME_SCOM_LMCR_PPE2 , RULL(0x10D0201B0), SH_UNT_PU_CME9 , + SH_ACS_PPE2 ); +REG64( PU_CME10_CME_SCOM_LMCR_PPE , RULL(0x10E0101A0), SH_UNT_PU_CME10 , + SH_ACS_PPE ); +REG64( PU_CME10_CME_SCOM_LMCR_PPE1 , RULL(0x10E0101B8), SH_UNT_PU_CME10 , + SH_ACS_PPE1 ); +REG64( PU_CME10_CME_SCOM_LMCR_PPE2 , RULL(0x10E0101B0), SH_UNT_PU_CME10 , + SH_ACS_PPE2 ); +REG64( PU_CME11_CME_SCOM_LMCR_PPE , RULL(0x10E0201A0), SH_UNT_PU_CME11 , + SH_ACS_PPE ); +REG64( PU_CME11_CME_SCOM_LMCR_PPE1 , RULL(0x10E0201B8), SH_UNT_PU_CME11 , + SH_ACS_PPE1 ); +REG64( PU_CME11_CME_SCOM_LMCR_PPE2 , RULL(0x10E0201B0), SH_UNT_PU_CME11 , + SH_ACS_PPE2 ); + REG64( PU_CME0_CME_SCOM_PMCRS0_PPE , RULL(0x109010240), SH_UNT_PU_CME0 , SH_ACS_PPE ); REG64( PU_CME1_CME_SCOM_PMCRS0_PPE , RULL(0x109020240), SH_UNT_PU_CME1 , @@ -3075,18 +3123,18 @@ REG64( PU_NPU2_NTL0_CREQ_HA_PTR , RULL(0x050112D0 REG64( PU_NPU2_NTL1_CREQ_HA_PTR , RULL(0x050112F0), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_CSAR , RULL(0x0501240D), SH_UNT , - SH_ACS_SCOM_RW ); //DUPS: 09011058, 0C011058, +REG64( PU_CSAR , RULL(0x0C01104D), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0901104D, 0C01104D, -REG64( PU_CSCR , RULL(0x0501240A), SH_UNT , - SH_ACS_SCOM_RW ); //DUPS: 09011055, 0C011055, -REG64( PU_CSCR_CLEAR , RULL(0x0501240B), SH_UNT , - SH_ACS_SCOM1_CLEAR ); //DUPS: 09011001, 0C011001, -REG64( PU_CSCR_OR , RULL(0x0501240C), SH_UNT , - SH_ACS_SCOM2_OR ); //DUPS: 09011002, 0C011002, +REG64( PU_CSCR , RULL(0x0C01104A), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0901104A, 0C01104A, +REG64( PU_CSCR_CLEAR , RULL(0x0C01104B), SH_UNT , + SH_ACS_SCOM1_CLEAR ); //DUPS: 0901104B, 0C01104B, +REG64( PU_CSCR_OR , RULL(0x0C01104C), SH_UNT , + SH_ACS_SCOM2_OR ); //DUPS: 0901104C, 0C01104C, -REG64( PU_CSDR , RULL(0x0501240E), SH_UNT , - SH_ACS_SCOM_RW ); //DUPS: 09011059, 0C011059, +REG64( PU_CSDR , RULL(0x0C01104E), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0901104E, 0C01104E, REG64( PU_NPU0_CTL_CTL_STATUS , RULL(0x05011092), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); @@ -3725,6 +3773,11 @@ REG64( PU_OTPROM0_ECID_PART9_REGISTER , RULL(0x00018009 REG64( PU_OTPROM1_ECID_PART9_REGISTER , RULL(0x00018049), SH_UNT_PU_OTPROM1, SH_ACS_SCOM ); +REG64( PEC_EDRAM_STATUS , RULL(0x0D0F0029), SH_UNT_PEC , SH_ACS_SCOM ); +REG64( PEC_0_EDRAM_STATUS , RULL(0x0D0F0029), SH_UNT_PEC_0 , SH_ACS_SCOM ); +REG64( PEC_1_EDRAM_STATUS , RULL(0x0E0F0029), SH_UNT_PEC_1 , SH_ACS_SCOM ); +REG64( PEC_2_EDRAM_STATUS , RULL(0x0F0F0029), SH_UNT_PEC_2 , SH_ACS_SCOM ); + REG64( PU_EECNT_REG , RULL(0x05012809), SH_UNT , SH_ACS_SCOM ); REG64( PU_EFT_HI_PRIOR_RCV_FIFO_ASB , RULL(0x020110C6), SH_UNT , SH_ACS_SCOM ); @@ -3753,6 +3806,22 @@ REG64( PU_EHHCA_FIR_REG , RULL(0x05012980 REG64( PU_EHHCA_FIR_REG_AND , RULL(0x05012981), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_EHHCA_FIR_REG_OR , RULL(0x05012982), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( PU_EMPTY_10 , RULL(0x05012910), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_EMPTY_1B , RULL(0x0501291B), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_ENHCA_FIR_ACTION0_REG , RULL(0x05012946), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_ENHCA_FIR_ACTION1_REG , RULL(0x05012947), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_ENHCA_FIR_MASK_REG , RULL(0x05012943), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_ENHCA_FIR_MASK_REG_AND , RULL(0x05012944), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_ENHCA_FIR_MASK_REG_OR , RULL(0x05012945), SH_UNT , SH_ACS_SCOM2_OR ); + +REG64( PU_ENHCA_FIR_REG , RULL(0x05012940), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_ENHCA_FIR_REG_AND , RULL(0x05012941), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_ENHCA_FIR_REG_OR , RULL(0x05012942), SH_UNT , SH_ACS_SCOM2_OR ); + REG64( PU_NPU0_SM0_EPSILON_CONFIG , RULL(0x05011002), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); REG64( PU_NPU0_SM1_EPSILON_CONFIG , RULL(0x05011022), SH_UNT_PU_NPU0_SM1, @@ -4045,6 +4114,7 @@ REG64( PEC_2_FIR_STATUS_REG_OR , RULL(0x0F010C02 REG64( PU_FIR_WOF_REG , RULL(0x04011808), SH_UNT , SH_ACS_SCOM_WCLRREG ); + REG64( PEC_FIR_WOF_REG , RULL(0x0D010C08), SH_UNT_PEC , SH_ACS_SCOM_WCLRREG ); REG64( PEC_0_FIR_WOF_REG , RULL(0x0D010C08), SH_UNT_PEC_0 , @@ -4081,6 +4151,8 @@ REG64( PU_NPU_CTL_FREEZE_STATE , RULL(0x05011395 REG64( PU_FSB_DOWNFIFO_DATA_IN , RULL(0x000B0010), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_FSB_DOWNFIFO_MTC , RULL(0x000B0016), SH_UNT , SH_ACS_SCOM_RW ); + REG64( PU_FSB_DOWNFIFO_REQ_RESET , RULL(0x000B0013), SH_UNT , SH_ACS_SCOM_WO ); REG64( PU_FSB_DOWNFIFO_SIG_EOT , RULL(0x000B0012), SH_UNT , SH_ACS_SCOM_WO ); @@ -4352,6 +4424,24 @@ REG64( PU_GPE3_PPE_XIRAMRA , RULL(0x00066011 REG64( PU_GPE3_PPE_XIXCR , RULL(0x00066010), SH_UNT , SH_ACS_SCOM_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG +REG64( PU_GPIO_INPUT , RULL(0x000B0050), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_GPIO_INT_COND , RULL(0x000B005E), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_GPIO_INT_ENABLE , RULL(0x000B005D), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_GPIO_INT_POLARITY , RULL(0x000B005C), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_GPIO_INT_STATUS , RULL(0x000B0057), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_GPIO_MODE , RULL(0x000B0059), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_GPIO_OUTPUT_SCOM , RULL(0x000B0051), SH_UNT , SH_ACS_SCOM ); +REG64( PU_GPIO_OUTPUT_SCOM1 , RULL(0x000B0052), SH_UNT , SH_ACS_SCOM1 ); +REG64( PU_GPIO_OUTPUT_SCOM2 , RULL(0x000B0053), SH_UNT , SH_ACS_SCOM2 ); + +REG64( PU_GPIO_OUTPUT_EN , RULL(0x000B0054), SH_UNT , SH_ACS_SCOM ); + REG64( PU_NPU0_SM0_GPU_BAR , RULL(0x05011004), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); REG64( PU_NPU0_SM1_GPU_BAR , RULL(0x05011024), SH_UNT_PU_NPU0_SM1, @@ -4450,21 +4540,32 @@ REG64( PEC_0_HANG_PULSE_6_REG , RULL(0x0D0F0026 REG64( PEC_1_HANG_PULSE_6_REG , RULL(0x0E0F0026), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); REG64( PEC_2_HANG_PULSE_6_REG , RULL(0x0F0F0026), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); -REG64( PU_HCA_BAR , RULL(0x0501298A), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_HCA_BAR , RULL(0x0501294A), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0501298A, + +REG64( PU_HCA_COUNT_BAR , RULL(0x0501294B), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0501298B, -REG64( PU_HCA_COUNT_BAR , RULL(0x0501298B), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_HCA_DECAY1 , RULL(0x0501294C), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_HCA_DROP , RULL(0x05012991), SH_UNT , SH_ACS_SCOM_RO ); +REG64( PU_HCA_DECAY2 , RULL(0x0501294D), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_HCA_DROP , RULL(0x05012951), SH_UNT , + SH_ACS_SCOM_RO ); //DUPS: 05012991, REG64( PU_HCA_FLUSH , RULL(0x05012990), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_HCA_MIRROR_BAR , RULL(0x05012993), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_HCA_MIRROR_BAR , RULL(0x05012953), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 05012993, -REG64( PU_HCA_MODES , RULL(0x0501298F), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_HCA_MODES , RULL(0x0501294F), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0501298F, -REG64( PU_HCA_REF_BAR , RULL(0x0501298E), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_HCA_REF_BAR , RULL(0x0501294E), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0501298E, -REG64( PU_HCA_RESET , RULL(0x05012992), SH_UNT , SH_ACS_SCOM_W ); +REG64( PU_HCA_RESET , RULL(0x05012952), SH_UNT , + SH_ACS_SCOM_W ); //DUPS: 05012992, REG64( PEC_HEARTBEAT_REG , RULL(0x0D0F0018), SH_UNT_PEC , SH_ACS_SCOM ); REG64( PEC_0_HEARTBEAT_REG , RULL(0x0D0F0018), SH_UNT_PEC_0 , SH_ACS_SCOM ); @@ -4746,8 +4847,12 @@ REG64( PU_INT_CQ_ERR_INFO3 , RULL(0x0501303D REG64( PU_INT_CQ_ERR_RPT_HOLD , RULL(0x05013039), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_INT_CQ_FIR , RULL(0x05013030), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_CQ_FIR_AND , RULL(0x05013031), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_INT_CQ_FIR_OR , RULL(0x05013032), SH_UNT , SH_ACS_SCOM2_OR ); REG64( PU_INT_CQ_FIRMASK , RULL(0x05013033), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_CQ_FIRMASK_AND , RULL(0x05013034), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_INT_CQ_FIRMASK_OR , RULL(0x05013035), SH_UNT , SH_ACS_SCOM2_OR ); REG64( PU_INT_CQ_IC_BAR , RULL(0x05013010), SH_UNT , SH_ACS_SCOM_RW ); @@ -4761,6 +4866,10 @@ REG64( PU_INT_CQ_PC_BAR , RULL(0x05013016 REG64( PU_INT_CQ_PC_BARM , RULL(0x05013017), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_CQ_PGM_DBG0 , RULL(0x05013000), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_CQ_PGM_DBG1 , RULL(0x05013001), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_CQ_PMC_0 , RULL(0x05013028), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_INT_CQ_PMC_1 , RULL(0x05013029), SH_UNT , SH_ACS_SCOM_RO ); @@ -4781,10 +4890,22 @@ REG64( PU_INT_CQ_PM_CTL , RULL(0x05013027 REG64( PU_INT_CQ_RST_CTL , RULL(0x05013023), SH_UNT , SH_ACS_SCOM ); +REG64( PU_INT_CQ_SWI_CMD1 , RULL(0x05013004), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_CQ_SWI_CMD2 , RULL(0x05013005), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_CQ_SWI_CMD3 , RULL(0x05013006), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_CQ_SWI_CMD4 , RULL(0x05013007), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_CQ_SWI_CMD5 , RULL(0x05013008), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_CQ_SWI_RSP , RULL(0x05013009), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_INT_CQ_TAR , RULL(0x0501301E), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_CQ_TDR , RULL(0x0501301F), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_CQ_TM1_BAR , RULL(0x05013012), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_CQ_TM2_BAR , RULL(0x05013014), SH_UNT , SH_ACS_SCOM_RW ); @@ -4793,6 +4914,9 @@ REG64( PU_INT_CQ_VC_BAR , RULL(0x05013018 REG64( PU_INT_CQ_VC_BARM , RULL(0x05013019), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_CQ_WOF , RULL(0x05013038), SH_UNT , + SH_ACS_SCOM_WCLRPART ); + REG64( PU_NPU_NTL1_INT_LOG_PE0 , RULL(0x050113E0), SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM ); @@ -4859,6 +4983,8 @@ REG64( PU_INT_PC_AT_KILL_MASK , RULL(0x05013117 REG64( PU_INT_PC_DBG_ECC , RULL(0x05013131), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_DBG_INT , RULL(0x05013132), SH_UNT , SH_ACS_SCOM_RW ); + REG64( PU_INT_PC_DBG_PMC , RULL(0x05013134), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_PC_DBG_PMC_ATX0 , RULL(0x05013135), SH_UNT , SH_ACS_SCOM_RW ); @@ -4913,6 +5039,10 @@ REG64( PU_INT_PC_GLOBAL_CFG , RULL(0x05013110 REG64( PU_INT_PC_IVE_BLOCK_MODE , RULL(0x05013113), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_LSI_TRIG_EOI , RULL(0x05013128), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_PC_LSI_TRIG_LD , RULL(0x05013129), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_PC_MMIO_ARB , RULL(0x0501311A), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_PC_PCMD_ARB , RULL(0x05013118), SH_UNT , SH_ACS_SCOM_RW ); @@ -4925,12 +5055,16 @@ REG64( PU_INT_PC_VPC_CACHE_EN , RULL(0x05013161 REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA0 , RULL(0x05013168), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA1 , RULL(0x05013169), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA2 , RULL(0x0501316A), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA3 , RULL(0x0501316B), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA4 , RULL(0x0501316C), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA5 , RULL(0x0501316D), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA6 , RULL(0x0501316E), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA7 , RULL(0x0501316F), SH_UNT , SH_ACS_SCOM_RW ); @@ -4983,6 +5117,8 @@ REG64( PU_INT_PC_VRQ_VPC_CRD , RULL(0x0501311E REG64( PU_INT_PC_VSD_TABLE_ADDR , RULL(0x05013111), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VSD_TABLE_DATA , RULL(0x05013112), SH_UNT , SH_ACS_SCOM ); + REG64( PU_NPU_CTL_INT_REQ , RULL(0x05011397), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); @@ -4990,8 +5126,16 @@ REG64( PU_INT_TCTXT_CFG , RULL(0x05013100 REG64( PU_INT_TCTXT_EN0 , RULL(0x05013108), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_TCTXT_EN0_RESET , RULL(0x0501310A), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_TCTXT_EN0_SET , RULL(0x05013109), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_TCTXT_EN1 , RULL(0x0501310C), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_TCTXT_EN1_RESET , RULL(0x0501310E), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_TCTXT_EN1_SET , RULL(0x0501310D), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_TCTXT_INDIR0 , RULL(0x05013104), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_TCTXT_INDIR1 , RULL(0x05013105), SH_UNT , SH_ACS_SCOM_RW ); @@ -5178,6 +5322,8 @@ REG64( PU_INT_VC_VPS_BLOCK_MODE , RULL(0x05013205 REG64( PU_INT_VC_VSD_TABLE_ADDR , RULL(0x05013201), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_VC_VSD_TABLE_DATA , RULL(0x05013202), SH_UNT , SH_ACS_SCOM ); + REG64( PU_INT_VC_WOF_ERR_G0 , RULL(0x05013274), SH_UNT , SH_ACS_SCOM_CLRPART ); @@ -5429,14 +5575,19 @@ REG64( PU_MCD1_MCD_FIR_MASK_REG , RULL(0x03011003 REG64( PU_MCD1_MCD_FIR_MASK_REG_AND , RULL(0x03011004), SH_UNT_PU_MCD1 , SH_ACS_SCOM1_AND ); REG64( PU_MCD1_MCD_FIR_MASK_REG_OR , RULL(0x03011005), SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR ); +REG64( PU_MCD_FIR_WOF_REG , RULL(0x03011408), SH_UNT , + SH_ACS_SCOM_WCLRREG ); +REG64( PU_MCD1_MCD_FIR_WOF_REG , RULL(0x03011008), SH_UNT_PU_MCD1 , + SH_ACS_SCOM_WCLRREG ); + REG64( PU_MIB_XIICAC , RULL(0x000E0009), SH_UNT , - SH_ACS_SCOM_RO ); //DUPS: 05012419, 09011053, 0C011053, + SH_ACS_SCOM_RO ); //DUPS: 05012419, 09011059, 0C011059, REG64( PU_MIB_XIMEM , RULL(0x000E0007), SH_UNT , - SH_ACS_SCOM_RO ); //DUPS: 05012417, 09011051, 0C011051, + SH_ACS_SCOM_RO ); //DUPS: 05012417, 09011057, 0C011057, REG64( PU_MIB_XISGB , RULL(0x000E0008), SH_UNT , - SH_ACS_SCOM_RO ); //DUPS: 05012418, 09011052, 0C011052, + SH_ACS_SCOM_RO ); //DUPS: 05012418, 09011058, 0C011058, REG64( PU_MIB_XISIB , RULL(0x000E0006), SH_UNT , SH_ACS_SCOM_RO ); @@ -6085,6 +6236,21 @@ REG64( PU_NPU_SM1_NPU_Q_DMA_R , RULL(0x05011325 REG64( PU_NPU_CTL_NPU_VERSION , RULL(0x05011390), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( PEC_NRDSTKOVR_REG , RULL(0x04010C08), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_0_NRDSTKOVR_REG , RULL(0x04010C08), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); +REG64( PEC_1_NRDSTKOVR_REG , RULL(0x04011008), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); +REG64( PEC_2_NRDSTKOVR_REG , RULL(0x04011408), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); + +REG64( PEC_NSTQSTKOVR_REG , RULL(0x04010C0A), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_0_NSTQSTKOVR_REG , RULL(0x04010C0A), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); +REG64( PEC_1_NSTQSTKOVR_REG , RULL(0x0401100A), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); +REG64( PEC_2_NSTQSTKOVR_REG , RULL(0x0401140A), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); + +REG64( PEC_NWRSTKOVR_REG , RULL(0x04010C09), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_0_NWRSTKOVR_REG , RULL(0x04010C09), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); +REG64( PEC_1_NWRSTKOVR_REG , RULL(0x04011009), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); +REG64( PEC_2_NWRSTKOVR_REG , RULL(0x04011409), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); + REG64( PU_NXCQ_PB_MODE_REG , RULL(0x02011095), SH_UNT , SH_ACS_SCOM ); REG64( PU_NX_CQ_FIR_ACTION0_REG , RULL(0x02011086), SH_UNT , SH_ACS_SCOM_RW ); @@ -7627,27 +7793,27 @@ REG64( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG , RULL(0x0E0108CB SH_ACS_SCOM_RO ); REG64( PU_PBAMODE_OCI , RULL(0xC0040000), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAMODE_PIB , RULL(0x00064000), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAMODE_PIB , RULL(0x00068000), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAOCCACT , RULL(0x0501284A), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_PBAPBOCR0_OCI , RULL(0xC00400D0), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAPBOCR0_PIB , RULL(0x0006401A), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAPBOCR0_PIB , RULL(0x0006801A), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAPBOCR1_OCI , RULL(0xC00400D8), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAPBOCR1_PIB , RULL(0x0006401B), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAPBOCR1_PIB , RULL(0x0006801B), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAPBOCR2_OCI , RULL(0xC00400E0), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAPBOCR2_PIB , RULL(0x0006401C), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAPBOCR2_PIB , RULL(0x0006801C), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAPBOCR3_OCI , RULL(0xC00400E8), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAPBOCR3_PIB , RULL(0x0006401D), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAPBOCR3_PIB , RULL(0x0006801D), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAPBOCR4_OCI , RULL(0xC00400F0), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAPBOCR4_PIB , RULL(0x0006401E), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAPBOCR4_PIB , RULL(0x0006801E), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAPBOCR5_OCI , RULL(0xC00400F8), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAPBOCR5_PIB , RULL(0x0006401F), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAPBOCR5_PIB , RULL(0x0006801F), SH_UNT , SH_ACS_PIB ); REG64( PU_PBARBUFVAL0 , RULL(0x05012850), SH_UNT , SH_ACS_SCOM_RO ); @@ -7662,47 +7828,53 @@ REG64( PU_PBARBUFVAL4 , RULL(0x05012854 REG64( PU_PBARBUFVAL5 , RULL(0x05012855), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_PBASLVCTL0_OCI , RULL(0xC0040020), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBASLVCTL0_PIB , RULL(0x00064004), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBASLVCTL0_PIB , RULL(0x00068004), SH_UNT , SH_ACS_PIB ); REG64( PU_PBASLVCTL1_OCI , RULL(0xC0040028), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBASLVCTL1_PIB , RULL(0x00064005), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBASLVCTL1_PIB , RULL(0x00068005), SH_UNT , SH_ACS_PIB ); REG64( PU_PBASLVCTL2_OCI , RULL(0xC0040030), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBASLVCTL2_PIB , RULL(0x00064006), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBASLVCTL2_PIB , RULL(0x00068006), SH_UNT , SH_ACS_PIB ); REG64( PU_PBASLVCTL3_OCI , RULL(0xC0040038), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBASLVCTL3_PIB , RULL(0x00064007), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBASLVCTL3_PIB , RULL(0x00068007), SH_UNT , SH_ACS_PIB ); REG64( PU_PBASLVRST_OCI , RULL(0xC0040008), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBASLVRST_PIB , RULL(0x00064001), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBASLVRST_PIB , RULL(0x00068001), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAWBUFVAL0 , RULL(0x05012858), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_PBAWBUFVAL1 , RULL(0x05012859), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_PBAXCFG_OCI , RULL(0xC0040108), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXCFG_PIB , RULL(0x00064021), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXCFG_PIB , RULL(0x00068021), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXRCVSTAT_OCI , RULL(0xC0040120), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXRCVSTAT_PIB , RULL(0x00064024), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXRCVSTAT_PIB , RULL(0x00068024), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXSHBR0_OCI , RULL(0xC0040130), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXSHBR0_PIB , RULL(0x00064026), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXSHBR0_PIB , RULL(0x00068026), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXSHBR1_OCI , RULL(0xC0040150), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXSHBR1_PIB , RULL(0x0006402A), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXSHBR1_PIB , RULL(0x0006802A), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXSHCS0_OCI , RULL(0xC0040138), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXSHCS0_PIB , RULL(0x00064027), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXSHCS0_PIB , RULL(0x00068027), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXSHCS1_OCI , RULL(0xC0040158), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXSHCS1_PIB , RULL(0x0006402B), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXSHCS1_PIB , RULL(0x0006802B), SH_UNT , SH_ACS_PIB ); + +REG64( PU_PBAXSHINC0_OCI , RULL(0xC0040140), SH_UNT , SH_ACS_OCI ); +REG64( PU_PBAXSHINC0_PIB , RULL(0x00068028), SH_UNT , SH_ACS_PIB ); + +REG64( PU_PBAXSHINC1_OCI , RULL(0xC0040160), SH_UNT , SH_ACS_OCI ); +REG64( PU_PBAXSHINC1_PIB , RULL(0x0006802C), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXSNDSTAT_OCI , RULL(0xC0040110), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXSNDSTAT_PIB , RULL(0x00064022), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXSNDSTAT_PIB , RULL(0x00068022), SH_UNT , SH_ACS_PIB ); REG64( PU_PBAXSNDTX_OCI , RULL(0xC0040100), SH_UNT , SH_ACS_OCI ); -REG64( PU_PBAXSNDTX_PIB , RULL(0x00064020), SH_UNT , SH_ACS_PIB ); +REG64( PU_PBAXSNDTX_PIB , RULL(0x00068020), SH_UNT , SH_ACS_PIB ); REG64( PEC_PBCQEINJ_REG , RULL(0x04010C02), SH_UNT_PEC , SH_ACS_SCOM_RW ); REG64( PEC_0_PBCQEINJ_REG , RULL(0x04010C02), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); @@ -7810,6 +7982,8 @@ REG64( PU_IOE_PBO_MAILBOX_CTL_REG , RULL(0x0501382E REG64( PU_IOE_PBO_MAILBOX_DATA_REG , RULL(0x0501382F), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_PB_BOGUS_0D_REG , RULL(0x0501340D), SH_UNT , SH_ACS_SCOM_RO ); + REG64( PU_PB_CENT_SM0_PB_CENT_CNPME , RULL(0x05011C13), SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM ); @@ -7935,6 +8109,15 @@ REG64( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1 , RULL(0x05011C2B REG64( PU_PB_CENT_SM0_PB_CENT_TRACE , RULL(0x05011C12), SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM ); +REG64( PU_PB_CENT_SM1_PB_CENT_UNUSED_2D , RULL(0x05011C2D), SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM ); + +REG64( PU_PB_CENT_SM1_PB_CENT_UNUSED_36 , RULL(0x05011C36), SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM ); + +REG64( PU_PB_CENT_SM1_PB_CENT_UNUSED_37 , RULL(0x05011C37), SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM ); + REG64( PU_PB_EAST_FIR_ACTION0_REG , RULL(0x05012006), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_PB_EAST_FIR_ACTION1_REG , RULL(0x05012007), SH_UNT , SH_ACS_SCOM_RW ); @@ -8050,6 +8233,9 @@ REG64( PU_PB_IOE_FIR_REG , RULL(0x05013400 REG64( PU_PB_IOE_FIR_REG_AND , RULL(0x05013401), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_PB_IOE_FIR_REG_OR , RULL(0x05013402), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( PU_PB_IOE_FIR_WOF_REG , RULL(0x05013408), SH_UNT , + SH_ACS_SCOM_WCLRREG ); + REG64( PU_IOE_PB_IOO_FIR_ACTION0_REG , RULL(0x05013806), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); REG64( PU_IOE_PB_IOO_FIR_ACTION1_REG , RULL(0x05013807), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); @@ -8062,6 +8248,9 @@ REG64( PU_IOE_PB_IOO_FIR_REG , RULL(0x05013800 REG64( PU_IOE_PB_IOO_FIR_REG_AND , RULL(0x05013801), SH_UNT_PU_IOE , SH_ACS_SCOM1_AND ); REG64( PU_IOE_PB_IOO_FIR_REG_OR , RULL(0x05013802), SH_UNT_PU_IOE , SH_ACS_SCOM2_OR ); +REG64( PU_IOE_PB_IOO_FIR_WOF_REG , RULL(0x05013808), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); + REG64( PU_PB_MISC_CFG , RULL(0x05013423), SH_UNT , SH_ACS_SCOM ); REG64( PU_IOE_PB_MISC_CFG , RULL(0x05013823), SH_UNT_PU_IOE , SH_ACS_SCOM ); @@ -8116,6 +8305,8 @@ REG64( PU_IOE_PB_OLINK_SYN_67_REG , RULL(0x05013817 REG64( PU_PB_PERFTRACE_CFG_REG , RULL(0x05013429), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_IOE_PB_PERFTRACE_CFG_REG , RULL(0x05013829), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_PB_PPE_BOGUS_16_REG , RULL(0x05012416), SH_UNT , SH_ACS_SCOM_RO ); + REG64( PU_PB_PPE_LFIR , RULL(0x05012400), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_PB_PPE_LFIR_AND , RULL(0x05012401), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_PB_PPE_LFIR_OR , RULL(0x05012402), SH_UNT , SH_ACS_SCOM2_OR ); @@ -8128,6 +8319,9 @@ REG64( PU_PB_PPE_LFIRMASK , RULL(0x05012403 REG64( PU_PB_PPE_LFIRMASK_AND , RULL(0x05012404), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_PB_PPE_LFIRMASK_OR , RULL(0x05012405), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( PU_PB_PPE_LFIRWOF , RULL(0x05012408), SH_UNT , + SH_ACS_SCOM_WCLRREG ); + REG64( PU_PB_PR0123_ERR , RULL(0x05013427), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_IOE_PB_PR0123_ERR , RULL(0x05013827), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); @@ -8270,6 +8464,46 @@ REG64( PEC_0_PECAPP_SEC_BAR , RULL(0x0D010801 REG64( PEC_1_PECAPP_SEC_BAR , RULL(0x0E010801), SH_UNT_PEC_1 , SH_ACS_SCOM ); REG64( PEC_2_PECAPP_SEC_BAR , RULL(0x0F010801), SH_UNT_PEC_2 , SH_ACS_SCOM ); +REG64( PHB_PERF_CFG_REG , RULL(0x0D010917), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PERF_CFG_REG , RULL(0x0D010917), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PERF_CFG_REG , RULL(0x0E010917), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PERF_CFG_REG , RULL(0x0E010957), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PERF_CFG_REG , RULL(0x0F010917), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PERF_CFG_REG , RULL(0x0F010957), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PERF_CFG_REG , RULL(0x0F010997), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + +REG64( PHB_PERF_CNT0_REG , RULL(0x0D010918), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PERF_CNT0_REG , RULL(0x0D010918), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PERF_CNT0_REG , RULL(0x0E010918), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PERF_CNT0_REG , RULL(0x0E010958), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PERF_CNT0_REG , RULL(0x0F010918), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PERF_CNT0_REG , RULL(0x0F010958), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PERF_CNT0_REG , RULL(0x0F010998), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + +REG64( PHB_PERF_CNT1_REG , RULL(0x0D010919), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PERF_CNT1_REG , RULL(0x0D010919), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PERF_CNT1_REG , RULL(0x0E010919), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PERF_CNT1_REG , RULL(0x0E010959), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PERF_CNT1_REG , RULL(0x0F010919), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PERF_CNT1_REG , RULL(0x0F010959), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PERF_CNT1_REG , RULL(0x0F010999), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + +REG64( PHB_PERF_CNT2_REG , RULL(0x0D01091A), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PERF_CNT2_REG , RULL(0x0D01091A), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PERF_CNT2_REG , RULL(0x0E01091A), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PERF_CNT2_REG , RULL(0x0E01095A), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PERF_CNT2_REG , RULL(0x0F01091A), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PERF_CNT2_REG , RULL(0x0F01095A), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PERF_CNT2_REG , RULL(0x0F01099A), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + +REG64( PHB_PERF_CNT3_REG , RULL(0x0D01091B), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PERF_CNT3_REG , RULL(0x0D01091B), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PERF_CNT3_REG , RULL(0x0E01091B), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PERF_CNT3_REG , RULL(0x0E01095B), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PERF_CNT3_REG , RULL(0x0F01091B), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PERF_CNT3_REG , RULL(0x0F01095B), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PERF_CNT3_REG , RULL(0x0F01099B), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + REG64( NV_PERF_CONFIG , RULL(0x050110CE), SH_UNT_NV , SH_ACS_SCOM ); REG64( NV_0_PERF_CONFIG , RULL(0x050110CE), SH_UNT_NV_0 , SH_ACS_SCOM ); REG64( NV_1_PERF_CONFIG , RULL(0x050110EE), SH_UNT_NV_1 , SH_ACS_SCOM ); @@ -8597,6 +8831,54 @@ REG64( PU_PBAIB_STACK5_PFIR_REG_AND , RULL(0x0E0108C1 REG64( PU_PBAIB_STACK5_PFIR_REG_OR , RULL(0x0E0108C2), SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR ); +REG64( PHB_PHB4_SCOM_HVIAR , RULL(0x0D010900), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PHB4_SCOM_HVIAR , RULL(0x0D010900), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PHB4_SCOM_HVIAR , RULL(0x0E010900), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PHB4_SCOM_HVIAR , RULL(0x0E010940), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PHB4_SCOM_HVIAR , RULL(0x0F010900), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PHB4_SCOM_HVIAR , RULL(0x0F010940), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PHB4_SCOM_HVIAR , RULL(0x0F010980), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + +REG64( PHB_PHB4_SCOM_HVIDR , RULL(0x0D010901), SH_UNT_PHB , SH_ACS_SCOM_RO ); +REG64( PHB_0_PHB4_SCOM_HVIDR , RULL(0x0D010901), SH_UNT_PHB_0 , SH_ACS_SCOM_RO ); +REG64( PHB_1_PHB4_SCOM_HVIDR , RULL(0x0E010901), SH_UNT_PHB_1 , SH_ACS_SCOM_RO ); +REG64( PHB_2_PHB4_SCOM_HVIDR , RULL(0x0E010941), SH_UNT_PHB_2 , SH_ACS_SCOM_RO ); +REG64( PHB_3_PHB4_SCOM_HVIDR , RULL(0x0F010901), SH_UNT_PHB_3 , SH_ACS_SCOM_RO ); +REG64( PHB_4_PHB4_SCOM_HVIDR , RULL(0x0F010941), SH_UNT_PHB_4 , SH_ACS_SCOM_RO ); +REG64( PHB_5_PHB4_SCOM_HVIDR , RULL(0x0F010981), SH_UNT_PHB_5 , SH_ACS_SCOM_RO ); + +REG64( PHB_PHB4_SCOM_HVIDWR , RULL(0x0D010901), SH_UNT_PHB , SH_ACS_SCOM_WO ); +REG64( PHB_0_PHB4_SCOM_HVIDWR , RULL(0x0D010901), SH_UNT_PHB_0 , SH_ACS_SCOM_WO ); +REG64( PHB_1_PHB4_SCOM_HVIDWR , RULL(0x0E010901), SH_UNT_PHB_1 , SH_ACS_SCOM_WO ); +REG64( PHB_2_PHB4_SCOM_HVIDWR , RULL(0x0E010941), SH_UNT_PHB_2 , SH_ACS_SCOM_WO ); +REG64( PHB_3_PHB4_SCOM_HVIDWR , RULL(0x0F010901), SH_UNT_PHB_3 , SH_ACS_SCOM_WO ); +REG64( PHB_4_PHB4_SCOM_HVIDWR , RULL(0x0F010941), SH_UNT_PHB_4 , SH_ACS_SCOM_WO ); +REG64( PHB_5_PHB4_SCOM_HVIDWR , RULL(0x0F010981), SH_UNT_PHB_5 , SH_ACS_SCOM_WO ); + +REG64( PHB_PHB4_SCOM_UVIAR , RULL(0x0D010902), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PHB4_SCOM_UVIAR , RULL(0x0D010902), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PHB4_SCOM_UVIAR , RULL(0x0E010902), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PHB4_SCOM_UVIAR , RULL(0x0E010942), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PHB4_SCOM_UVIAR , RULL(0x0F010902), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PHB4_SCOM_UVIAR , RULL(0x0F010942), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PHB4_SCOM_UVIAR , RULL(0x0F010982), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + +REG64( PHB_PHB4_SCOM_UVIDR , RULL(0x0D010903), SH_UNT_PHB , SH_ACS_SCOM_RO ); +REG64( PHB_0_PHB4_SCOM_UVIDR , RULL(0x0D010903), SH_UNT_PHB_0 , SH_ACS_SCOM_RO ); +REG64( PHB_1_PHB4_SCOM_UVIDR , RULL(0x0E010903), SH_UNT_PHB_1 , SH_ACS_SCOM_RO ); +REG64( PHB_2_PHB4_SCOM_UVIDR , RULL(0x0E010943), SH_UNT_PHB_2 , SH_ACS_SCOM_RO ); +REG64( PHB_3_PHB4_SCOM_UVIDR , RULL(0x0F010903), SH_UNT_PHB_3 , SH_ACS_SCOM_RO ); +REG64( PHB_4_PHB4_SCOM_UVIDR , RULL(0x0F010943), SH_UNT_PHB_4 , SH_ACS_SCOM_RO ); +REG64( PHB_5_PHB4_SCOM_UVIDR , RULL(0x0F010983), SH_UNT_PHB_5 , SH_ACS_SCOM_RO ); + +REG64( PHB_PHB4_SCOM_UVIDWR , RULL(0x0D010903), SH_UNT_PHB , SH_ACS_SCOM_WO ); +REG64( PHB_0_PHB4_SCOM_UVIDWR , RULL(0x0D010903), SH_UNT_PHB_0 , SH_ACS_SCOM_WO ); +REG64( PHB_1_PHB4_SCOM_UVIDWR , RULL(0x0E010903), SH_UNT_PHB_1 , SH_ACS_SCOM_WO ); +REG64( PHB_2_PHB4_SCOM_UVIDWR , RULL(0x0E010943), SH_UNT_PHB_2 , SH_ACS_SCOM_WO ); +REG64( PHB_3_PHB4_SCOM_UVIDWR , RULL(0x0F010903), SH_UNT_PHB_3 , SH_ACS_SCOM_WO ); +REG64( PHB_4_PHB4_SCOM_UVIDWR , RULL(0x0F010943), SH_UNT_PHB_4 , SH_ACS_SCOM_WO ); +REG64( PHB_5_PHB4_SCOM_UVIDWR , RULL(0x0F010983), SH_UNT_PHB_5 , SH_ACS_SCOM_WO ); + REG64( PEC_0_STACK0_PHBBAR_REG , RULL(0x04010C52), SH_UNT_PEC_0_STACK0, SH_ACS_SCOM ); REG64( PEC_0_STACK1_PHBBAR_REG , RULL(0x04010C92), SH_UNT_PEC_0_STACK1, @@ -8734,23 +9016,46 @@ REG64( CAPP_PMU_CNTRB_REG , RULL(0x02010825 REG64( CAPP_0_PMU_CNTRB_REG , RULL(0x02010825), SH_UNT_CAPP_0 , SH_ACS_SCOM ); REG64( CAPP_1_PMU_CNTRB_REG , RULL(0x04010825), SH_UNT_CAPP_1 , SH_ACS_SCOM ); +REG64( PU_PPE_FIR_ACTION0_REG , RULL(0x0C011046), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0C011046, + +REG64( PU_PPE_FIR_ACTION1_REG , RULL(0x0C011047), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0C011047, + +REG64( PU_PPE_FIR_MASK_REG , RULL(0x0C011043), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0C011043, +REG64( PU_PPE_FIR_MASK_REG_AND , RULL(0x0C011044), SH_UNT , + SH_ACS_SCOM1_AND ); //DUPS: 0C011044, +REG64( PU_PPE_FIR_MASK_REG_OR , RULL(0x0C011045), SH_UNT , + SH_ACS_SCOM2_OR ); //DUPS: 0C011045, + +REG64( PU_PPE_FIR_REG , RULL(0x0C011040), SH_UNT , + SH_ACS_SCOM_RW ); //DUPS: 0C011040, +REG64( PU_PPE_FIR_REG_AND , RULL(0x0C011041), SH_UNT , + SH_ACS_SCOM1_AND ); //DUPS: 0C011041, +REG64( PU_PPE_FIR_REG_OR , RULL(0x0C011042), SH_UNT , + SH_ACS_SCOM2_OR ); //DUPS: 0C011042, + +REG64( PU_PPE_FIR_WOF_REG , RULL(0x0C011048), SH_UNT , + SH_ACS_SCOM_WCLRREG ); //DUPS: 0C011048, + REG64( PU_PPE_XIDBGPRO , RULL(0x000E0005), SH_UNT , - SH_ACS_SCOM ); //DUPS: 05012415, 0901104F, 0C01104F, + SH_ACS_SCOM ); //DUPS: 05012415, 09011055, 0C011055, REG64( PU_PPE_XIRAMDBG , RULL(0x000E0003), SH_UNT , - SH_ACS_SCOM ); //DUPS: 05012413, 0901104D, 0C01104D, + SH_ACS_SCOM ); //DUPS: 05012413, 09011053, 0C011053, REG64( PU_PPE_XIRAMEDR , RULL(0x000E0004), SH_UNT , - SH_ACS_SCOM ); //DUPS: 05012414, 0901104E, 0C01104E, + SH_ACS_SCOM ); //DUPS: 05012414, 09011054, 0C011054, REG64( PU_PPE_XIRAMGA , RULL(0x000E0002), SH_UNT , - SH_ACS_SCOM_WO ); //DUPS: 05012412, 0901104C, 0C01104C, + SH_ACS_SCOM_WO ); //DUPS: 05012412, 09011052, 0C011052, REG64( PU_PPE_XIRAMRA , RULL(0x000E0001), SH_UNT , - SH_ACS_SCOM_WO ); //DUPS: 05012411, 0901104B, 0C01104B, + SH_ACS_SCOM_WO ); //DUPS: 05012411, 09011051, 0C011051, REG64( PU_PPE_XIXCR , RULL(0x000E0000), SH_UNT , - SH_ACS_SCOM_WO ); //DUPS: 05012410, 0901104A, 0C01104A, + SH_ACS_SCOM_WO ); //DUPS: 05012410, 09011050, 0C011050, REG64( NV_PRB_HA_PTR , RULL(0x050110D1), SH_UNT_NV , SH_ACS_SCOM ); REG64( NV_0_PRB_HA_PTR , RULL(0x050110D1), SH_UNT_NV_0 , SH_ACS_SCOM ); @@ -8762,6 +9067,11 @@ REG64( PU_NPU2_NTL0_PRB_HA_PTR , RULL(0x050112D1 REG64( PU_NPU2_NTL1_PRB_HA_PTR , RULL(0x050112F1), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PEC_PRDSTKOVR_REG , RULL(0x0D010802), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_0_PRDSTKOVR_REG , RULL(0x0D010802), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); +REG64( PEC_1_PRDSTKOVR_REG , RULL(0x0E010802), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); +REG64( PEC_2_PRDSTKOVR_REG , RULL(0x0F010802), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); + REG64( PEC_PREDV_REG , RULL(0x04010C06), SH_UNT_PEC , SH_ACS_SCOM_RW ); REG64( PEC_0_PREDV_REG , RULL(0x04010C06), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); REG64( PEC_1_PREDV_REG , RULL(0x04011006), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); @@ -8987,6 +9297,48 @@ REG64( PU_NPU0_REM1 , RULL(0x050110AE REG64( PU_NPU1_REM1 , RULL(0x050111AE), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); REG64( PU_NPU2_REM1 , RULL(0x050112AE), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); +REG64( PHB_RESERVED1_REG , RULL(0x0D01084C), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_RESERVED1_REG , RULL(0x0D01084C), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_RESERVED1_REG , RULL(0x0E01084C), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_RESERVED1_REG , RULL(0x0E01088C), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_RESERVED1_REG , RULL(0x0F01084C), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_RESERVED1_REG , RULL(0x0F01088C), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_RESERVED1_REG , RULL(0x0F0108CC), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK1_RESERVED1_REG , RULL(0x0D01088C), SH_UNT_PU_PBAIB_STACK1, + SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK2_RESERVED1_REG , RULL(0x0D0108CC), SH_UNT_PU_PBAIB_STACK2, + SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK5_RESERVED1_REG , RULL(0x0E0108CC), SH_UNT_PU_PBAIB_STACK5, + SH_ACS_SCOM_RW ); + +REG64( PHB_RESERVED2_REG , RULL(0x0D01084D), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_RESERVED2_REG , RULL(0x0D01084D), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_RESERVED2_REG , RULL(0x0E01084D), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_RESERVED2_REG , RULL(0x0E01088D), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_RESERVED2_REG , RULL(0x0F01084D), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_RESERVED2_REG , RULL(0x0F01088D), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_RESERVED2_REG , RULL(0x0F0108CD), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK1_RESERVED2_REG , RULL(0x0D01088D), SH_UNT_PU_PBAIB_STACK1, + SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK2_RESERVED2_REG , RULL(0x0D0108CD), SH_UNT_PU_PBAIB_STACK2, + SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK5_RESERVED2_REG , RULL(0x0E0108CD), SH_UNT_PU_PBAIB_STACK5, + SH_ACS_SCOM_RW ); + +REG64( PHB_RESERVED3_REG , RULL(0x0D01084E), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_RESERVED3_REG , RULL(0x0D01084E), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_RESERVED3_REG , RULL(0x0E01084E), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_RESERVED3_REG , RULL(0x0E01088E), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_RESERVED3_REG , RULL(0x0F01084E), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_RESERVED3_REG , RULL(0x0F01088E), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_RESERVED3_REG , RULL(0x0F0108CE), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK1_RESERVED3_REG , RULL(0x0D01088E), SH_UNT_PU_PBAIB_STACK1, + SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK2_RESERVED3_REG , RULL(0x0D0108CE), SH_UNT_PU_PBAIB_STACK2, + SH_ACS_SCOM_RW ); +REG64( PU_PBAIB_STACK5_RESERVED3_REG , RULL(0x0E0108CE), SH_UNT_PU_PBAIB_STACK5, + SH_ACS_SCOM_RW ); + REG64( PU_RESET_REGISTER , RULL(0x00010001), SH_UNT , SH_ACS_SCOM ); REG64( PU_RESET_REGISTER_B , RULL(0x000A0001), SH_UNT , @@ -9083,25 +9435,80 @@ REG64( PU_RX_PSI_MODE , RULL(0x04011821 REG64( PU_RX_PSI_STATUS , RULL(0x04011822), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_SCAN32 , RULL(0x0D038000), SH_UNT_PEC , SH_ACS_SCOM ); +REG64( PEC_0_SCAN32 , RULL(0x0D038000), SH_UNT_PEC_0 , SH_ACS_SCOM ); +REG64( PEC_1_SCAN32 , RULL(0x0E038000), SH_UNT_PEC_1 , SH_ACS_SCOM ); +REG64( PEC_2_SCAN32 , RULL(0x0F038000), SH_UNT_PEC_2 , SH_ACS_SCOM ); + +REG64( PEC_SCAN_CAPTUREDR , RULL(0x0D03C000), SH_UNT_PEC , SH_ACS_SCOM ); +REG64( PEC_0_SCAN_CAPTUREDR , RULL(0x0D03C000), SH_UNT_PEC_0 , SH_ACS_SCOM ); +REG64( PEC_1_SCAN_CAPTUREDR , RULL(0x0E03C000), SH_UNT_PEC_1 , SH_ACS_SCOM ); +REG64( PEC_2_SCAN_CAPTUREDR , RULL(0x0F03C000), SH_UNT_PEC_2 , SH_ACS_SCOM ); + REG64( PEC_SCAN_REGION_TYPE , RULL(0x0D030005), SH_UNT_PEC , SH_ACS_SCOM ); REG64( PEC_0_SCAN_REGION_TYPE , RULL(0x0D030005), SH_UNT_PEC_0 , SH_ACS_SCOM ); REG64( PEC_1_SCAN_REGION_TYPE , RULL(0x0E030005), SH_UNT_PEC_1 , SH_ACS_SCOM ); REG64( PEC_2_SCAN_REGION_TYPE , RULL(0x0F030005), SH_UNT_PEC_2 , SH_ACS_SCOM ); -REG64( PU_SCOM_PPE_CNTL , RULL(0x09011060), SH_UNT , +REG64( PEC_SCOM0X01 , RULL(0x80000BC10D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); //DUPS: 800000C10D010C3F, 800001810D010C3F, 800001C10D010C3F, 800003C10D010C3F, 800003810D010C3F, 800002C10D010C3F, 800002810D010C3F, 800009C10D010C3F, 800009810D010C3F, 800008C10D010C3F, 800008810D010C3F, 80000BC10D010C3F, 80000B810D010C3F, 80000AC10D010C3F, 80000A810D010C3F, +REG64( PEC_0_SCOM0X01 , RULL(0x80000BC10D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); //DUPS: 800000C10D010C3F, 800001810D010C3F, 800001C10D010C3F, 800003C10D010C3F, 800003810D010C3F, 800002C10D010C3F, 800002810D010C3F, 800009C10D010C3F, 800009810D010C3F, 800008C10D010C3F, 800008810D010C3F, 80000BC10D010C3F, 80000B810D010C3F, 80000AC10D010C3F, 80000A810D010C3F, +REG64( PEC_1_SCOM0X01 , RULL(0x80000BC10E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); //DUPS: 800000C10E010C3F, 800001810E010C3F, 800001C10E010C3F, 800003C10E010C3F, 800003810E010C3F, 800002C10E010C3F, 800002810E010C3F, 800009C10E010C3F, 800009810E010C3F, 800008C10E010C3F, 800008810E010C3F, 80000BC10E010C3F, 80000B810E010C3F, 80000AC10E010C3F, 80000A810E010C3F, +REG64( PEC_2_SCOM0X01 , RULL(0x80000BC10F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); //DUPS: 800000C10F010C3F, 800001810F010C3F, 800001C10F010C3F, 800003C10F010C3F, 800003810F010C3F, 800002C10F010C3F, 800002810F010C3F, 800009C10F010C3F, 800009810F010C3F, 800008C10F010C3F, 800008810F010C3F, 80000BC10F010C3F, 80000B810F010C3F, 80000AC10F010C3F, 80000A810F010C3F, + +REG64( PEC_SCOM0X04 , RULL(0x80000BC40D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); //DUPS: 800000C40D010C3F, 800001840D010C3F, 800001C40D010C3F, 800003C40D010C3F, 800003840D010C3F, 800002C40D010C3F, 800002840D010C3F, 800009C40D010C3F, 800009840D010C3F, 800008C40D010C3F, 800008840D010C3F, 80000BC40D010C3F, 80000B840D010C3F, 80000AC40D010C3F, 80000A840D010C3F, +REG64( PEC_0_SCOM0X04 , RULL(0x80000BC40D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); //DUPS: 800000C40D010C3F, 800001840D010C3F, 800001C40D010C3F, 800003C40D010C3F, 800003840D010C3F, 800002C40D010C3F, 800002840D010C3F, 800009C40D010C3F, 800009840D010C3F, 800008C40D010C3F, 800008840D010C3F, 80000BC40D010C3F, 80000B840D010C3F, 80000AC40D010C3F, 80000A840D010C3F, +REG64( PEC_1_SCOM0X04 , RULL(0x80000BC40E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); //DUPS: 800000C40E010C3F, 800001840E010C3F, 800001C40E010C3F, 800003C40E010C3F, 800003840E010C3F, 800002C40E010C3F, 800002840E010C3F, 800009C40E010C3F, 800009840E010C3F, 800008C40E010C3F, 800008840E010C3F, 80000BC40E010C3F, 80000B840E010C3F, 80000AC40E010C3F, 80000A840E010C3F, +REG64( PEC_2_SCOM0X04 , RULL(0x80000BC40F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); //DUPS: 800000C40F010C3F, 800001840F010C3F, 800001C40F010C3F, 800003C40F010C3F, 800003840F010C3F, 800002C40F010C3F, 800002840F010C3F, 800009C40F010C3F, 800009840F010C3F, 800008C40F010C3F, 800008840F010C3F, 80000BC40F010C3F, 80000B840F010C3F, 80000AC40F010C3F, 80000A840F010C3F, + +REG64( PEC_SCOM0X05 , RULL(0x80000BC50D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); //DUPS: 800000C50D010C3F, 800001850D010C3F, 800001C50D010C3F, 800003C50D010C3F, 800003850D010C3F, 800002C50D010C3F, 800002850D010C3F, 800009C50D010C3F, 800009850D010C3F, 800008C50D010C3F, 800008850D010C3F, 80000BC50D010C3F, 80000B850D010C3F, 80000AC50D010C3F, 80000A850D010C3F, +REG64( PEC_0_SCOM0X05 , RULL(0x80000BC50D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); //DUPS: 800000C50D010C3F, 800001850D010C3F, 800001C50D010C3F, 800003C50D010C3F, 800003850D010C3F, 800002C50D010C3F, 800002850D010C3F, 800009C50D010C3F, 800009850D010C3F, 800008C50D010C3F, 800008850D010C3F, 80000BC50D010C3F, 80000B850D010C3F, 80000AC50D010C3F, 80000A850D010C3F, +REG64( PEC_1_SCOM0X05 , RULL(0x80000BC50E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); //DUPS: 800000C50E010C3F, 800001850E010C3F, 800001C50E010C3F, 800003C50E010C3F, 800003850E010C3F, 800002C50E010C3F, 800002850E010C3F, 800009C50E010C3F, 800009850E010C3F, 800008C50E010C3F, 800008850E010C3F, 80000BC50E010C3F, 80000B850E010C3F, 80000AC50E010C3F, 80000A850E010C3F, +REG64( PEC_2_SCOM0X05 , RULL(0x80000BC50F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); //DUPS: 800000C50F010C3F, 800001850F010C3F, 800001C50F010C3F, 800003C50F010C3F, 800003850F010C3F, 800002C50F010C3F, 800002850F010C3F, 800009C50F010C3F, 800009850F010C3F, 800008C50F010C3F, 800008850F010C3F, 80000BC50F010C3F, 80000B850F010C3F, 80000AC50F010C3F, 80000A850F010C3F, + +REG64( PEC_SCOM0X2B , RULL(0x80000BEB0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); //DUPS: 800000EB0D010C3F, 800001AB0D010C3F, 800001EB0D010C3F, 800003EB0D010C3F, 800003AB0D010C3F, 800002EB0D010C3F, 800002AB0D010C3F, 800009EB0D010C3F, 800009AB0D010C3F, 800008EB0D010C3F, 800008AB0D010C3F, 80000BEB0D010C3F, 80000BAB0D010C3F, 80000AEB0D010C3F, 80000AAB0D010C3F, +REG64( PEC_0_SCOM0X2B , RULL(0x80000BEB0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); //DUPS: 800000EB0D010C3F, 800001AB0D010C3F, 800001EB0D010C3F, 800003EB0D010C3F, 800003AB0D010C3F, 800002EB0D010C3F, 800002AB0D010C3F, 800009EB0D010C3F, 800009AB0D010C3F, 800008EB0D010C3F, 800008AB0D010C3F, 80000BEB0D010C3F, 80000BAB0D010C3F, 80000AEB0D010C3F, 80000AAB0D010C3F, +REG64( PEC_1_SCOM0X2B , RULL(0x80000BEB0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); //DUPS: 800000EB0E010C3F, 800001AB0E010C3F, 800001EB0E010C3F, 800003EB0E010C3F, 800003AB0E010C3F, 800002EB0E010C3F, 800002AB0E010C3F, 800009EB0E010C3F, 800009AB0E010C3F, 800008EB0E010C3F, 800008AB0E010C3F, 80000BEB0E010C3F, 80000BAB0E010C3F, 80000AEB0E010C3F, 80000AAB0E010C3F, +REG64( PEC_2_SCOM0X2B , RULL(0x80000BEB0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); //DUPS: 800000EB0F010C3F, 800001AB0F010C3F, 800001EB0F010C3F, 800003EB0F010C3F, 800003AB0F010C3F, 800002EB0F010C3F, 800002AB0F010C3F, 800009EB0F010C3F, 800009AB0F010C3F, 800008EB0F010C3F, 800008AB0F010C3F, 80000BEB0F010C3F, 80000BAB0F010C3F, 80000AEB0F010C3F, 80000AAB0F010C3F, + +REG64( PEC_SCOM0X2C , RULL(0x80000BEC0D010C3F), SH_UNT_PEC , + SH_ACS_SCOM ); //DUPS: 800000EC0D010C3F, 800001AC0D010C3F, 800001EC0D010C3F, 800003EC0D010C3F, 800003AC0D010C3F, 800002EC0D010C3F, 800002AC0D010C3F, 800009EC0D010C3F, 800009AC0D010C3F, 800008EC0D010C3F, 800008AC0D010C3F, 80000BEC0D010C3F, 80000BAC0D010C3F, 80000AEC0D010C3F, 80000AAC0D010C3F, +REG64( PEC_0_SCOM0X2C , RULL(0x80000BEC0D010C3F), SH_UNT_PEC_0 , + SH_ACS_SCOM ); //DUPS: 800000EC0D010C3F, 800001AC0D010C3F, 800001EC0D010C3F, 800003EC0D010C3F, 800003AC0D010C3F, 800002EC0D010C3F, 800002AC0D010C3F, 800009EC0D010C3F, 800009AC0D010C3F, 800008EC0D010C3F, 800008AC0D010C3F, 80000BEC0D010C3F, 80000BAC0D010C3F, 80000AEC0D010C3F, 80000AAC0D010C3F, +REG64( PEC_1_SCOM0X2C , RULL(0x80000BEC0E010C3F), SH_UNT_PEC_1 , + SH_ACS_SCOM ); //DUPS: 800000EC0E010C3F, 800001AC0E010C3F, 800001EC0E010C3F, 800003EC0E010C3F, 800003AC0E010C3F, 800002EC0E010C3F, 800002AC0E010C3F, 800009EC0E010C3F, 800009AC0E010C3F, 800008EC0E010C3F, 800008AC0E010C3F, 80000BEC0E010C3F, 80000BAC0E010C3F, 80000AEC0E010C3F, 80000AAC0E010C3F, +REG64( PEC_2_SCOM0X2C , RULL(0x80000BEC0F010C3F), SH_UNT_PEC_2 , + SH_ACS_SCOM ); //DUPS: 800000EC0F010C3F, 800001AC0F010C3F, 800001EC0F010C3F, 800003EC0F010C3F, 800003AC0F010C3F, 800002EC0F010C3F, 800002AC0F010C3F, 800009EC0F010C3F, 800009AC0F010C3F, 800008EC0F010C3F, 800008AC0F010C3F, 80000BEC0F010C3F, 80000BAC0F010C3F, 80000AEC0F010C3F, 80000AAC0F010C3F, + +REG64( PU_SCOM_PPE_CNTL , RULL(0x0C011060), SH_UNT , SH_ACS_SCOM ); //DUPS: 0C011060, -REG64( PU_SCOM_PPE_FLAGS , RULL(0x09011063), SH_UNT , +REG64( PU_SCOM_PPE_FLAGS , RULL(0x0C011063), SH_UNT , SH_ACS_SCOM_RW ); //DUPS: 0C011063, -REG64( PU_SCOM_PPE_FLAGS_OR , RULL(0x09011064), SH_UNT , +REG64( PU_SCOM_PPE_FLAGS_OR , RULL(0x0C011064), SH_UNT , SH_ACS_SCOM1_OR ); //DUPS: 0C011064, -REG64( PU_SCOM_PPE_FLAGS_CLEAR , RULL(0x09011065), SH_UNT , +REG64( PU_SCOM_PPE_FLAGS_CLEAR , RULL(0x0C011065), SH_UNT , SH_ACS_SCOM2_CLEAR ); //DUPS: 0C011065, -REG64( PU_SCOM_PPE_WORK_REG1 , RULL(0x09011061), SH_UNT , +REG64( PU_SCOM_PPE_WORK_REG1 , RULL(0x0C011061), SH_UNT , SH_ACS_SCOM ); //DUPS: 0C011061, -REG64( PU_SCOM_PPE_WORK_REG2 , RULL(0x09011062), SH_UNT , +REG64( PU_SCOM_PPE_WORK_REG2 , RULL(0x0C011062), SH_UNT , SH_ACS_SCOM ); //DUPS: 0C011062, REG64( PU_SCRATCH0_PPE , RULL(0xC0001000), SH_UNT , SH_ACS_PPE ); @@ -9397,6 +9804,9 @@ REG64( PU_SYNC_FIR_REG , RULL(0x050129C0 REG64( PU_SYNC_FIR_REG_AND , RULL(0x050129C1), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_SYNC_FIR_REG_OR , RULL(0x050129C2), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( PU_SYNC_FIR_WOF_REG , RULL(0x050129C8), SH_UNT , + SH_ACS_SCOM_WCLRREG ); + REG64( PU_NPU_SM1_TCE_KILL , RULL(0x05011324), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM ); @@ -10096,6 +10506,74 @@ REG64( CAPP_TLBI_ERROR_REPORT , RULL(0x0201080D REG64( CAPP_0_TLBI_ERROR_REPORT , RULL(0x0201080D), SH_UNT_CAPP_0 , SH_ACS_SCOM ); REG64( CAPP_1_TLBI_ERROR_REPORT , RULL(0x0401080D), SH_UNT_CAPP_1 , SH_ACS_SCOM ); +REG64( CAPP_TLBI_FILTER_REG0 , RULL(0x02010870), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG0 , RULL(0x02010870), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG0 , RULL(0x04010870), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG1 , RULL(0x02010871), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG1 , RULL(0x02010871), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG1 , RULL(0x04010871), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG10 , RULL(0x0201087A), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG10 , RULL(0x0201087A), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG10 , RULL(0x0401087A), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG11 , RULL(0x0201087B), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG11 , RULL(0x0201087B), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG11 , RULL(0x0401087B), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG12 , RULL(0x0201087C), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG12 , RULL(0x0201087C), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG12 , RULL(0x0401087C), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG13 , RULL(0x0201087D), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG13 , RULL(0x0201087D), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG13 , RULL(0x0401087D), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG14 , RULL(0x0201087E), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG14 , RULL(0x0201087E), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG14 , RULL(0x0401087E), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG15 , RULL(0x0201087F), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG15 , RULL(0x0201087F), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG15 , RULL(0x0401087F), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG2 , RULL(0x02010872), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG2 , RULL(0x02010872), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG2 , RULL(0x04010872), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG3 , RULL(0x02010873), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG3 , RULL(0x02010873), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG3 , RULL(0x04010873), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG4 , RULL(0x02010874), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG4 , RULL(0x02010874), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG4 , RULL(0x04010874), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG5 , RULL(0x02010875), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG5 , RULL(0x02010875), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG5 , RULL(0x04010875), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG6 , RULL(0x02010876), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG6 , RULL(0x02010876), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG6 , RULL(0x04010876), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG7 , RULL(0x02010877), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG7 , RULL(0x02010877), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG7 , RULL(0x04010877), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG8 , RULL(0x02010878), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG8 , RULL(0x02010878), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG8 , RULL(0x04010878), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_FILTER_REG9 , RULL(0x02010879), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_FILTER_REG9 , RULL(0x02010879), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_FILTER_REG9 , RULL(0x04010879), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TLBI_QOS , RULL(0x0201084C), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_QOS , RULL(0x0201084C), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_QOS , RULL(0x0401084C), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + REG64( PU_TOD_CMD_REG , RULL(0x0009002A), SH_UNT , SH_ACS_SCOM ); REG64( PU_TOD_DATA_RCV_REG , RULL(0x00090029), SH_UNT , SH_ACS_SCOM_RO ); @@ -10216,6 +10694,8 @@ REG64( PU_VAS_PGMIG7 , RULL(0x03011847 REG64( PU_VAS_PMCNTL , RULL(0x03011830), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_VAS_RESERVE , RULL(0x03011828), SH_UNT , SH_ACS_SCOM_RO ); + REG64( PU_VAS_RGERRRPT , RULL(0x0301182C), SH_UNT , SH_ACS_SCOM ); REG64( PU_VAS_RMABAR , RULL(0x0301180E), SH_UNT , SH_ACS_SCOM_RW ); diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H index 59907281..5dfc6a1c 100644 --- a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H @@ -41,6 +41,264 @@ #include <p9_scom_template_consts.H> #include <p9_misc_scom_addresses_fld_fixes.H> +REG64_FLD( PHB_ACT0_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_ACT0_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_ACT0_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACT0_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_ACT0_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_ACT0_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_ACT0_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_ACT0_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_ACT0_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_ACT0_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_ACT0_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_ACT0_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_ACT0_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_ACT0_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_ACT0_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_ACT0_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_ACT0_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACT0_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_ACT0_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_ACT0_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_ACT0_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_ACT0_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_ACT0_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACT0_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_ACT0_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + +REG64_FLD( PHB_ACTION1_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_ACTION1_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_ACTION1_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACTION1_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_ACTION1_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_ACTION1_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_ACTION1_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_ACTION1_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_ACTION1_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_ACTION1_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_ACTION1_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_ACTION1_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_ACTION1_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_ACTION1_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_ACTION1_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_ACTION1_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_ACTION1_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_ACTION1_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_ACTION1_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , @@ -259,6 +517,8 @@ REG64_FLD( PU_ALTD_CMD_REG_FBC_AXTYPE , 6 , SH_UN SH_FLD_FBC_AXTYPE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_DATA_ONLY , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DATA_ONLY ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_PICK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_LOCK_PICK ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCKED , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_LOCKED ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID , 12 , SH_UNT , SH_ACS_SCOM , @@ -295,10 +555,10 @@ REG64_FLD( PU_ALTD_DATA_REG_FBC , 0 , SH_UN REG64_FLD( PU_ALTD_DATA_REG_FBC_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FBC_LEN ); -REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_FBC_WITH_PRE_QUIESCE ); -REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT , 23 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WITH_PBINIT_LOW_WAIT ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WITH_PRE_QUIESCE ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN , 20 , SH_UNT , SH_ACS_SCOM , @@ -310,6 +570,8 @@ REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT , 54 , SH_UN REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ALTD_BUSY , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ALTD_BUSY ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WAIT_CMD_ARBIT ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDR_DONE , 2 , SH_UNT , SH_ACS_SCOM , @@ -355,6 +617,8 @@ REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE , 59 , SH_UN REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_CRESP_VALUE_LEN ); +REG64_FLD( CAPP_APCFG_SPARE1 , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE1 ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_PHB_SEL ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -367,6 +631,8 @@ REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE , 8 , SH_UN SH_FLD_SPEC_HPC_DIR_STATE ); REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SPEC_HPC_DIR_STATE_LEN ); +REG64_FLD( CAPP_APCFG_SPARE , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE ); REG64_FLD( CAPP_APCFG_APCCTL_P9_MODE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_P9_MODE ); REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR , 15 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -414,6 +680,10 @@ REG64_FLD( CAPP_APCTL_APCCTL_HANG_DEAD , 8 , SH_UN SH_FLD_APCCTL_HANG_DEAD ); REG64_FLD( CAPP_APCTL_APCCTL_CFG_BKILL_INC , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_CFG_BKILL_INC ); +REG64_FLD( CAPP_APCTL_DCACHE_MODE , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DCACHE_MODE ); +REG64_FLD( CAPP_APCTL_DCACHE_REPORTS_PHYSICAL , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE ); REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF , 13 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -424,6 +694,8 @@ REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE_LEN , 3 , SH_UN SH_FLD_SCPTGT_LFSR_MODE_LEN ); REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT , 17 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT ); +REG64_FLD( CAPP_APCTL_SPARE , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE ); REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE , 39 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WR_EPSILON_VALUE ); REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -433,6 +705,8 @@ REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY , 56 , SH_UN REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_MAX_RETRY_LEN ); +REG64_FLD( CAPP_APC_ARRY_ADDR_ENCD_ARRAY_SELECT , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ENCD_ARRAY_SELECT ); REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_ADDRESS ); REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -554,6 +828,13 @@ REG64_FLD( CAPP_ASE_TUPLE3_TID_LEN , 16 , SH_UN REG64_FLD( CAPP_ASE_TUPLE3_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); +REG64_FLD( PEC_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ATTN ); +REG64_FLD( PEC_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RECOV ); +REG64_FLD( PEC_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -721,6 +1002,9 @@ REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT , 10 , SH_UN REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT_LEN , 6 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_TIMEOUT_LEN ); +REG64_FLD( PEC_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ATTN ); + REG64_FLD( PU_BANK0_MCD_BOT_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_BANK0_MCD_BOT_CPG , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -20953,6 +21237,10 @@ REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -20963,6 +21251,8 @@ REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20988,6 +21278,10 @@ REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -20998,6 +21292,8 @@ REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21023,6 +21319,10 @@ REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -21033,6 +21333,8 @@ REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21058,6 +21360,10 @@ REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -21068,6 +21374,8 @@ REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21093,6 +21401,10 @@ REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -21103,6 +21415,8 @@ REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21128,6 +21442,10 @@ REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -21138,6 +21456,8 @@ REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21163,6 +21483,10 @@ REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -21173,6 +21497,8 @@ REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21198,6 +21524,10 @@ REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -21208,6 +21538,8 @@ REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21233,6 +21565,10 @@ REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -21243,6 +21579,8 @@ REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21268,6 +21606,10 @@ REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -21278,6 +21620,8 @@ REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21303,6 +21647,10 @@ REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -21313,6 +21661,8 @@ REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21338,6 +21688,10 @@ REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -21348,6 +21702,8 @@ REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); @@ -22597,6 +22953,66 @@ REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UN REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); +REG64_FLD( PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -22933,186 +23349,6 @@ REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND , 0 , SH_UN REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME4_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME3_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME3_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME11_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME11_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME2_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME2_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME5_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME5_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME9_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME9_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME6_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME6_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME10_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME10_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME8_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME8_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME1_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME1_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME0_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME0_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - -REG64_FLD( PU_CME7_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( PU_CME7_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -25897,6 +26133,738 @@ REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME4_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME3_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME11_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME2_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME5_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME9_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME6_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME10_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME8_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME1_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME0_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( PU_CME7_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SET_ECC_INJECT_ERR ); + REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -29989,8 +30957,8 @@ REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -30050,8 +31018,8 @@ REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -30111,8 +31079,8 @@ REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -30172,8 +31140,8 @@ REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -30233,8 +31201,8 @@ REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -30294,8 +31262,8 @@ REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -30355,8 +31323,8 @@ REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -30416,8 +31384,8 @@ REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -30477,8 +31445,8 @@ REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -30538,8 +31506,8 @@ REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -30599,8 +31567,8 @@ REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -30660,8 +31628,8 @@ REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -32281,6 +33249,246 @@ REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO ); +REG64_FLD( PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PCBM_INFO_LEN ); + REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_WITHSTART ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR , 1 , SH_UNT , SH_ACS_SCOM , @@ -36278,6 +37486,33 @@ REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UN REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); +REG64_FLD( PEC_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_TRIP_HISTORY ); +REG64_FLD( PEC_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_PULSE_CNT ); +REG64_FLD( PEC_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_RD ); +REG64_FLD( PEC_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_WR ); +REG64_FLD( PEC_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_DTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L1RESULTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L2RESULTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L3RESULTS ); +REG64_FLD( PEC_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); +REG64_FLD( PEC_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_MEASURE_VOLT ); +REG64_FLD( PEC_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_SHIFT_SENSOR ); + REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0 , 1 , SH_UNT , SH_ACS_SCOM , @@ -36599,42 +37834,42 @@ REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UN REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOX_MUX_VSEL ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOX_MUX_VSEL_LEN ); -REG64_FLD( PEC_CPLT_CONF1_UNUSED , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE0_IOVALID_DC , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE0_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE1_IOVALID_DC , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE1_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE2_IOVALID_DC , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE2_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE3_IOVALID_DC , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE3_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE4_IOVALID_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE4_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PBE5_IOVALID_DC , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBE5_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PSI_IOVALID_DC , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PSI_IOVALID_DC ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_12D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_13D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_14D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_15D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_16D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_17D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_18D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_0D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_1D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_2D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_3D ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_IOVALID , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_IOVALID ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_5D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_6D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_7D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_8D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_9D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_10D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_11D ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_SWAP_DC , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_SWAP_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_LANE_CFG_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_LANE_CFG_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_OVERRIDE , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_OVERRIDE ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_DC_LEN ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -36653,12 +37888,12 @@ REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UN SH_FLD_FREE_USAGE_26D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_28D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_29D ); -REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_30D ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PCS , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_SYS_RESET_PCS ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PMA , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_SYS_RESET_PMA ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_HSSPORWREN , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_HSSPORWREN ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); @@ -36793,16 +38028,16 @@ REG64_FLD( PEC_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UN SH_FLD_TC_REGION1_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION3_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION4_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION5_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION6_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION7_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_7B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_8B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_9B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_10B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_11B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_12B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -37481,10 +38716,18 @@ REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE , 8 , SH_UN SH_FLD_SNPBE_TRIGGER_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNPBE_UOP_TRIGGER_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_TLBI_TRIGGER_SEL , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_TRIGGER_SEL ); +REG64_FLD( CAPP_CXA_TRIGCTL_XPT_TRIGGER_SEL , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_TRIGGER_SEL ); REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_MUX_PORT_SEL ); REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_MUX_PORT_SEL_LEN ); +REG64_FLD( CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_MUX_PORT_SEL ); +REG64_FLD( CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_MUX_PORT_SEL_LEN ); REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0 ); @@ -38557,10 +39800,14 @@ REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -38569,15 +39816,23 @@ REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N3_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N3_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , @@ -38586,15 +39841,23 @@ REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N1_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N1_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -38603,15 +39866,23 @@ REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N2_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N2_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PEC , SH_ACS_SCOM , @@ -38620,15 +39891,23 @@ REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PEC_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PEC_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , @@ -38637,6 +39916,10 @@ REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PU_N0_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PU_N0_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); @@ -40497,6 +41780,20 @@ REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL , 4 , SH_UN REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_SEL_LEN ); +REG64_FLD( PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + +REG64_FLD( PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + REG64_FLD( CAPP_DFSUOP1_WORD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WORD ); REG64_FLD( CAPP_DFSUOP1_WORD_LEN , 56 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -41314,6 +42611,16 @@ REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9 , 0 , SH_UN REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_9_LEN ); +REG64_FLD( PEC_EDRAM_STATUS_STAT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STAT ); +REG64_FLD( PEC_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STAT_LEN ); + +REG64_FLD( PU_EECNT_REG_EECNT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EECNT ); +REG64_FLD( PU_EECNT_REG_EECNT_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EECNT_LEN ); + REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , @@ -41689,6 +42996,190 @@ REG64_FLD( PU_EHHCA_FIR_REG_SCOM_ERROR , 34 , SH_UN REG64_FLD( PU_EHHCA_FIR_REG_PARITY_ERROR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION0_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PARITY_ERROR ); + +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_ACTION1_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PARITY_ERROR ); + +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_SPARE_ERROR_MASK , 21 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_ERROR_MASK ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_MASK_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PARITY_ERROR ); + +REG64_FLD( PU_ENHCA_FIR_REG_DPX0_DAT_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_UE ); +REG64_FLD( PU_ENHCA_FIR_REG_DPX0_DAT_SUE , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_SUE ); +REG64_FLD( PU_ENHCA_FIR_REG_DPX0_DAT_CE , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DPX0_DAT_CE ); +REG64_FLD( PU_ENHCA_FIR_REG_CO_DROP_COUNTER_FULL , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_CO_DROP_COUNTER_FULL ); +REG64_FLD( PU_ENHCA_FIR_REG_DATA_HANG_DETECT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DATA_HANG_DETECT ); +REG64_FLD( PU_ENHCA_FIR_REG_UNEXPECTED_DATA_OR_CRESP , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTED_DATA_OR_CRESP ); +REG64_FLD( PU_ENHCA_FIR_REG_INTERNAL_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBDAT_XSTOP_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_ALTDSM_XSTOP_ERROR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_XCSMP_XSTOP_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBADR_XSTOP_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_SND_XSTOP_ERROR , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_RCV_XSTOP_ERROR , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_XSTOP_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBDAT_RECOV_ERROR , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBDAT_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_ALTDSM_RECOV_ERROR , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_ALTDSM_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_XCSMP_RECOV_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_XCSMP_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_PBADR_RECOV_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_PBADR_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_SND_RECOV_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_SND_RECOV_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_ADU_RCV_RRC , 19 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ADU_RCV_RRC ); +REG64_FLD( PU_ENHCA_FIR_REG_NHTM_SCON_E , 20 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_NHTM_SCON_E ); +REG64_FLD( PU_ENHCA_FIR_REG_SPARE_ERROR , 21 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_SCOM_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERROR ); +REG64_FLD( PU_ENHCA_FIR_REG_PARITY_ERROR , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PARITY_ERROR ); + REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -42067,8 +43558,8 @@ REG64_FLD( PEC_ERROR_REG_PCB_INTERFACE , 16 , SH_UN SH_FLD_PCB_INTERFACE ); REG64_FLD( PEC_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); -REG64_FLD( PEC_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_CHIPLET_GRID_SKITTER ); +REG64_FLD( PEC_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( PEC_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( PEC_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_PEC , SH_ACS_SCOM , @@ -42086,10 +43577,163 @@ REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK , 25 , SH_UN REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); -REG64_FLD( PEC_ERROR_STATUS_ERRORS , 0 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_ERRORS ); -REG64_FLD( PEC_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_ERRORS_LEN ); +REG64_FLD( PEC_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_CMD_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_ADDR_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_DATA_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); +REG64_FLD( PEC_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_CONFLICT_ERR ); +REG64_FLD( PEC_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_COLLISION_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); +REG64_FLD( PEC_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_OPCG_TRIGGER_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PHASE_CNT_CORRUPTION_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_PREVENTED_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_SM_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_XSTOP_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_GPIO_REG_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLKCMD_REQUEST_ERR ); +REG64_FLD( PEC_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CBS_PROTOCOL_ERR ); +REG64_FLD( PEC_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_VITL_ALIGN_ERR ); +REG64_FLD( PEC_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT_SYNC_LVL_ERR ); +REG64_FLD( PEC_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR27 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR28 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR29 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR30 ); +REG64_FLD( PEC_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR31 ); + +REG64_FLD( CAPP_ERRRPT_APC_COLLISION , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC_COLLISION ); +REG64_FLD( CAPP_ERRRPT_FSM_SM_ERROR , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSM_SM_ERROR ); +REG64_FLD( CAPP_ERRRPT_RBUFSM_ERROR , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RBUFSM_ERROR ); +REG64_FLD( CAPP_ERRRPT_WBUF_SM_ERROR , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_WBUF_SM_ERROR ); +REG64_FLD( CAPP_ERRRPT_PERR_BAR_REG , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PERR_BAR_REG ); +REG64_FLD( CAPP_ERRRPT_PERR_NONBAR_REG , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PERR_NONBAR_REG ); +REG64_FLD( CAPP_ERRRPT_RTAG_HANG_EPOCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RTAG_HANG_EPOCH ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_CE_ERR , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_CE_ERR , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_UOP_REGS_CE_ERR , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UOP_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_UE_ERR , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_UE_ERR , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_UOP_REGS_UE_ERR , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UOP_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_ATAG_PERR , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP0_REGS_TTAG_PERR , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP0_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_ATAG_PERR , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP1_REGS_TTAG_PERR , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP1_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_FIR_ACTION1 , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIR_ACTION1 ); +REG64_FLD( CAPP_ERRRPT_FIR_ACTION2 , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIR_ACTION2 ); +REG64_FLD( CAPP_ERRRPT_FIR_ACTION3 , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIR_ACTION3 ); +REG64_FLD( CAPP_ERRRPT_UNEXPECTED_CRESP , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UNEXPECTED_CRESP ); +REG64_FLD( CAPP_ERRRPT_LD_CLASS_ARE_ERROR , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LD_CLASS_ARE_ERROR ); +REG64_FLD( CAPP_ERRRPT_ST_CLASS_ARE_ERROR , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ST_CLASS_ARE_ERROR ); +REG64_FLD( CAPP_ERRRPT_LD_CLASS_ACK_DEAD , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LD_CLASS_ACK_DEAD ); +REG64_FLD( CAPP_ERRRPT_FOREIGN_OP_HANG , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FOREIGN_OP_HANG ); +REG64_FLD( CAPP_ERRRPT_DOMESTIC_OP_HANG , 25 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DOMESTIC_OP_HANG ); +REG64_FLD( CAPP_ERRRPT_ST_CLASS_ACK_DEAD , 26 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ST_CLASS_ACK_DEAD ); +REG64_FLD( CAPP_ERRRPT_ACTIVATE_FSMERR , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ACTIVATE_FSMERR ); +REG64_FLD( CAPP_ERRRPT_SPARE1 , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE1 ); +REG64_FLD( CAPP_ERRRPT_SPARE2 , 29 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPARE2 ); +REG64_FLD( CAPP_ERRRPT_CMDQ_CE_ERR , 30 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CMDQ_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CMDQ_UE_ERR , 31 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CMDQ_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_CE_ERR , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_CE_ERR , 33 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_CE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_UE_ERR , 34 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_UE_ERR , 35 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_UE_ERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_ATAG_PERR , 36 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_ATAG_PERR , 37 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_ATAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP2_REGS_TTAG_PERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP2_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_CRSP3_REGS_TTAG_PERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CRSP3_REGS_TTAG_PERR ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR0 , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_CE_ERR0 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR1 , 41 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_CE_ERR1 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR2 , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_CE_ERR2 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR0 , 43 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_UE_ERR0 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR1 , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_UE_ERR1 ); +REG64_FLD( CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR2 , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPRTAG_REGS_UE_ERR2 ); REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS ); @@ -42208,6 +43852,38 @@ REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL , 0 , SH_UN REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CTL_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_STATE_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_ERR_HOLD ); +REG64_FLD( PEC_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , @@ -42238,6 +43914,36 @@ REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_DTS_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_VOLT_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT_LEN ); +REG64_FLD( PEC_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SAMPLE_DTS_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_MEASURE_VOLT_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_READ_CPM_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CPM_LT ); +REG64_FLD( PEC_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); REG64_FLD( PU_ESB_CI_BASE_BASE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE ); @@ -42265,8 +43971,8 @@ REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP , 4 , SH_UN SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN ); -REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_SPARE , 6 , SH_UNT , SH_ACS_SCOM , - SH_FLD_TP_PB_FUSE_SPARE ); +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_NP_NVLINK_DISABLE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TP_NP_NVLINK_DISABLE ); REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_0 ); @@ -42639,6 +44345,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_0 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_0_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_0 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_0_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_0 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_0_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42650,6 +44368,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_1_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_1 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_1_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_1 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_1_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_1 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_1_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42661,6 +44391,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_2_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_2 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_2_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_2 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_2_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_2 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_2_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42672,6 +44414,18 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3 , 0 , SH_UN SH_FLD_FIFO_BITS_READ0_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_3_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_3 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ2_3_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_3 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ3_3_LEN ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_3 ); +REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ4_3_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -42679,6 +44433,11 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PU_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION0 ); REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , @@ -42689,11 +44448,6 @@ REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0 , 0 , SH_UN REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION0_LEN ); -REG64_FLD( PU_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION0 ); -REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION0_LEN ); - REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , @@ -42704,6 +44458,11 @@ REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1 , 0 , SH_UN REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1_LEN ); +REG64_FLD( PU_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION1 ); REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , @@ -42714,11 +44473,6 @@ REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1 , 0 , SH_UN REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION1_LEN ); -REG64_FLD( PU_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION1 ); -REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACTION1_LEN ); - REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , @@ -42748,6 +44502,21 @@ REG64_FLD( PEC_FIR_MASK_IN6_LEN , 20 , SH_UN REG64_FLD( PEC_FIR_MASK_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN26 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED0 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED1 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED2 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED3 ); +REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED4 ); +REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + REG64_FLD( CAPP_FIR_MASK_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( CAPP_FIR_MASK_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -42928,21 +44697,6 @@ REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR0 , 35 , SH_UN REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR1 , 36 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED0 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED1 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED2 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED3 ); -REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED4 ); -REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); - REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERR_PIB ); REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB , 5 , SH_UNT , SH_ACS_SCOM , @@ -42970,6 +44724,21 @@ REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1 , 0 , SH_UN REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_1_LEN ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED0 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED1 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED2 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED3 ); +REG64_FLD( PU_FIR_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PSI_RESERVED4 ); +REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + REG64_FLD( CAPP_FIR_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( CAPP_FIR_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -43075,21 +44844,6 @@ REG64_FLD( CAPP_FIR_REG_SCOM_ERR2 , 50 , SH_UN REG64_FLD( CAPP_FIR_REG_SCOM_ERR , 51 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED0 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED1 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED2 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED3 ); -REG64_FLD( PU_FIR_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_PSI_RESERVED4 ); -REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR ); -REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); - REG64_FLD( PHB_FIR_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_COMMAND_INVALID ); REG64_FLD( PHB_FIR_REG_AIB_ADDRESS_INVALID , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -43196,6 +44950,10 @@ REG64_FLD( PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UN SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_FIR_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED02 ); REG64_FLD( PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -43208,6 +44966,8 @@ REG64_FLD( PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UN SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_RESERVED01 ); REG64_FLD( PHB_FIR_REG_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_PARITY_ERROR ); @@ -43549,6 +45309,11 @@ REG64_FLD( PEC_FIR_WOF_REG_WOF , 0 , SH_UN REG64_FLD( PEC_FIR_WOF_REG_WOF_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN ); +REG64_FLD( PU_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_FIR_WOF_REG_WOF_LEN , 7 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, @@ -43625,50 +45390,77 @@ REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_51 , 16 , SH_UN REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_52 , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_52 ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_DATA_IN_PORT ); +REG64_FLD( PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_DATA_IN_PORT_LEN ); + +REG32_FLD( PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DNFIFO_MCT ); +REG32_FLD( PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DNFIFO_MCT_LEN ); + +REG64_FLD( PU_FSB_DOWNFIFO_REQ_RESET_DNFIFO_REQ_RESET , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_REQ_RESET ); + +REG64_FLD( PU_FSB_DOWNFIFO_SIG_EOT_DNFIFO_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_DNFIFO_SIGNAL ); + +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_REQ_RESET_FR_SBE ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_REQ_RESET_FR_SP ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_FULL ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EMPTY ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_VALID_FLAGS ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EOT_FLAGS ); -REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_FSB_UPFIFO_ACK_EOT_UPFIFO_ACK , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_UPFIFO_ACK ); + +REG64_FLD( PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UPFIFO_DATA_OUT_PORT ); +REG64_FLD( PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_UPFIFO_DATA_OUT_PORT_LEN ); + +REG64_FLD( PU_FSB_UPFIFO_RESET_UPFIFO_RESET , 0 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_UPFIFO_RESET ); + +REG32_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_REQ_RESET_FR_SP ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_REQ_RESET_FR_SBE ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEQUEUED_EOT_FLAG ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EMPTY ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_LEN ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_VALID_FLAGS ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_VALID_FLAGS_LEN ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EOT_FLAGS ); -REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG32_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EOT_FLAGS_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -44020,6 +45812,11 @@ REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE0_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE0_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44035,14 +45832,52 @@ REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE0_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44050,6 +45885,12 @@ REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44057,12 +45898,24 @@ REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44102,23 +45955,103 @@ REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE0_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44253,6 +46186,11 @@ REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE1_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE1_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44268,14 +46206,52 @@ REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE1_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44283,6 +46259,12 @@ REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44290,12 +46272,24 @@ REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44335,23 +46329,103 @@ REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE1_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44486,6 +46560,11 @@ REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE2_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE2_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44501,14 +46580,52 @@ REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE2_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44516,6 +46633,12 @@ REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44523,12 +46646,24 @@ REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44568,23 +46703,103 @@ REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE2_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44719,6 +46934,11 @@ REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UN REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); +REG64_FLD( PU_GPE3_GPEXIIAR_IAR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR ); +REG64_FLD( PU_GPE3_GPEXIIAR_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IAR_LEN ); + REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , @@ -44734,14 +46954,52 @@ REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE3_GPEXIXSR_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); @@ -44749,6 +47007,12 @@ REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_POPULATE_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_POPULATE_PENDING ); +REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID ); +REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_VALID_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DCACHE_VALID_LEN ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -44756,12 +47020,24 @@ REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44801,23 +47077,103 @@ REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_GPE3_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -44855,6 +47211,60 @@ REG64_FLD( PU_GPE3_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); +REG64_FLD( PU_GPIO_INPUT_DIN_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIN_0 ); +REG64_FLD( PU_GPIO_INPUT_DIN_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIN_1 ); +REG64_FLD( PU_GPIO_INPUT_DIN_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIN_2 ); + +REG64_FLD( PU_GPIO_INT_COND_INT_COND_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_COND_0 ); +REG64_FLD( PU_GPIO_INT_COND_INT_COND_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_COND_1 ); +REG64_FLD( PU_GPIO_INT_COND_INT_COND_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_COND_2 ); + +REG64_FLD( PU_GPIO_INT_ENABLE_INT_EN_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_EN_0 ); +REG64_FLD( PU_GPIO_INT_ENABLE_INT_EN_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_EN_1 ); +REG64_FLD( PU_GPIO_INT_ENABLE_INT_EN_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_EN_2 ); + +REG64_FLD( PU_GPIO_INT_POLARITY_INT_POL_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_POL_0 ); +REG64_FLD( PU_GPIO_INT_POLARITY_INT_POL_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_POL_1 ); +REG64_FLD( PU_GPIO_INT_POLARITY_INT_POL_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_POL_2 ); + +REG64_FLD( PU_GPIO_INT_STATUS_INT_STAT_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_STAT_0 ); +REG64_FLD( PU_GPIO_INT_STATUS_INT_STAT_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_STAT_1 ); +REG64_FLD( PU_GPIO_INT_STATUS_INT_STAT_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INT_STAT_2 ); + +REG64_FLD( PU_GPIO_MODE_NUM_GPIO_PORTS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NUM_GPIO_PORTS ); +REG64_FLD( PU_GPIO_MODE_NUM_GPIO_PORTS_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NUM_GPIO_PORTS_LEN ); + +REG64_FLD( PU_GPIO_OUTPUT_DO_0 , 0 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_DO_0 ); +REG64_FLD( PU_GPIO_OUTPUT_DO_1 , 1 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_DO_1 ); +REG64_FLD( PU_GPIO_OUTPUT_DO_2 , 2 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_DO_2 ); + +REG64_FLD( PU_GPIO_OUTPUT_EN_DO_EN_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DO_EN_0 ); +REG64_FLD( PU_GPIO_OUTPUT_EN_DO_EN_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DO_EN_1 ); +REG64_FLD( PU_GPIO_OUTPUT_EN_DO_EN_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DO_EN_2 ); + REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -45863,6 +48273,26 @@ REG64_FLD( PU_HCA_COUNT_BAR_ADDR_LEN , 24 , SH_UN REG64_FLD( PU_HCA_COUNT_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); +REG64_FLD( PU_HCA_DECAY1_DECAY_SCOM_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_VALID ); +REG64_FLD( PU_HCA_DECAY1_DECAY_SCOM_COUNT , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_COUNT ); +REG64_FLD( PU_HCA_DECAY1_DECAY_SCOM_COUNT_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_COUNT_LEN ); + +REG64_FLD( PU_HCA_DECAY2_DECAY_SCOM_DELAY , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_DELAY ); +REG64_FLD( PU_HCA_DECAY2_DECAY_SCOM_DELAY_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_SCOM_DELAY_LEN ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR_COND , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR_COND ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR_COND_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR_COND_LEN ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR , 41 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR ); +REG64_FLD( PU_HCA_DECAY2_DECAY_ADDR_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DECAY_ADDR_LEN ); + REG64_FLD( PU_HCA_DROP_PIPE_COUNTER , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIPE_COUNTER ); REG64_FLD( PU_HCA_DROP_PIPE_COUNTER_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , @@ -47882,12 +50312,18 @@ REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6 , 4 , SH_UN SH_FLD_TSIZE_4_6 ); REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_TSIZE_4_6_LEN ); -REG64_FLD( PU_INT_CQ_ERR_INFO1_RESERVED_7 , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_RESERVED_7 ); -REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63 , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_ADDRESS_8_63 ); -REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63_LEN , 56 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_ADDRESS_8_63_LEN ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3 , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_BAR_VEC_0_3 ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_BAR_VEC_0_3_LEN ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_TTAG_0_16 , 11 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_TTAG_0_16 ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_TTAG_0_16_LEN , 17 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_TTAG_0_16_LEN ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_28_63 , 28 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_ADDRESS_28_63 ); +REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_28_63_LEN , 36 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_ADDRESS_28_63_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO2_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); @@ -47936,132 +50372,132 @@ REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48 , 0 , SH_UN REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_0_48_LEN ); -REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PI_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PI_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PI_ECC_SUE ); -REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ST_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ST_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_LD_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_LD_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE , 7 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CL_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CL_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RD_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RD_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AI_ECC_CE ); -REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AI_ECC_UE ); -REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AIB_IN_CMD_CTL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AIB_IN_CMD_PERR ); -REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR , 17 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AIB_IN_DAT_CTL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERROR ); -REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RCMDX_CI_ERR1 ); -REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 , 20 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RCMDX_CI_ERR2 ); -REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 , 21 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RCMDX_CI_ERR3 ); -REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RCVD_POISONED_CIST_DATA ); -REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MRT_ERR_NOT_VALID ); -REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MRT_ERR_PSIZE ); -REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_S_ERR ); -REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR , 26 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCTXT_PRESP_ERROR ); -REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG , 27 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WRQ_OP_HANG ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG , 28 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_OP_HANG ); -REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG , 29 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTQ_OP_HANG ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG , 30 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_DATA_HANG ); -REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG , 31 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STQ_DATA_HANG ); -REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_LDQ_DATA_HANG ); -REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP , 33 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WRQ_BAD_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP , 34 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_BAD_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP , 35 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTQ_BAD_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BAD_128K_VP_OP ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP , 37 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_ABORT_OP ); -REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR , 38 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_CRD_PERR ); -REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR , 39 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_CRD_AVAIL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR , 40 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_CRD_PERR ); -REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR , 41 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_CRD_AVAIL_PERR ); -REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR , 42 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CMD_QX_SEVERE_ERR ); -REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM , 43 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RDQ_ABORT_TRM ); -REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITED_CRESP ); -REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA , 45 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITED_PBDATA ); -REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); -REG64_FLD( PU_INT_CQ_FIR_RESERVED_47 , 47 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_47 ); -REG64_FLD( PU_INT_CQ_FIR_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PGM_DBG_ACCESS , 47 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PGM_DBG_ACCESS ); +REG64_FLD( PU_INT_CQ_FIR_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_48 ); -REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 , 49 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_FATAL_ERROR_0_2 ); -REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_FATAL_ERROR_0_2_LEN ); -REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 , 52 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 , 52 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_ERROR_0_2 ); -REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_ERROR_0_2_LEN ); -REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 , 55 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 , 55 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_INFO_ERROR_0_2 ); -REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PC_INFO_ERROR_0_2_LEN ); -REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 , 58 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 , 58 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_FATAL_ERROR_0_1 ); -REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_FATAL_ERROR_0_1_LEN ); -REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 , 60 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 , 60 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_RECOV_ERROR_0_1 ); -REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_RECOV_ERROR_0_1_LEN ); -REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 , 62 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 , 62 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_INFO_ERROR_0_1 ); -REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VC_INFO_ERROR_0_1_LEN ); -REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); -REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN , 64 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); REG64_FLD( PU_INT_CQ_IC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -48362,6 +50798,11 @@ REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37 , 21 , SH_UN REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_21_37_LEN ); +REG64_FLD( PU_INT_CQ_WOF_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_WOF ); +REG64_FLD( PU_INT_CQ_WOF_WOF_LEN , 64 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , @@ -48973,10 +51414,47 @@ REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31 , 30 , SH_UN REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_30_31_LEN ); -REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_15 ); -REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_15_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_VLD ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_1_3 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3 ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_LEVEL , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_LEVEL ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_LEVEL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_LEVEL_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_7_8 , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_7_8 ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_7_8_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_7_8_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID_LEN ); +REG64_FLD( PU_INT_PC_DBG_INT_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID_MASK , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID_MASK ); +REG64_FLD( PU_INT_PC_DBG_INT_DBG_THRDID_MASK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_THRDID_MASK_LEN ); + +REG64_FLD( PU_INT_PC_DBG_PMC_EN_ARX , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_ARX ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_ARX_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_ARX_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CRESP , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CRESP ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CRESP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CRESP_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CMD , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CMD ); +REG64_FLD( PU_INT_PC_DBG_PMC_EN_CMD_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EN_CMD_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_14_15 , 14 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_14_15 ); +REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_14_15_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_14_15_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); @@ -50090,12 +52568,12 @@ REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_22 , 22 , SH_UN REG64_FLD( PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_GROUP_EN ); -REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_TCTXT_CFG_CFG_TARGET_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_TARGET_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2 , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_2 ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_ACM_EN ); -REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_2_3 ); -REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_2_3_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_FUSE_CORE_EN ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_5 , 5 , SH_UNT , SH_ACS_SCOM_RW , @@ -50209,14 +52687,18 @@ REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN , 7 , SH_UN REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_EN ); -REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_VPD_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_BLOCK_VPD_EN ); -REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RCMD_FILTER_EN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_BLOCK_RCMD_FILTER_EN ); -REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9 , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_3_9 ); -REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_3_9_LEN ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_1_3 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3 ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3_LEN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_EN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_FILTER_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_VPC_EN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_FILTER_VPC_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_6_9 , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_6_9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_RESET_DELAY ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , @@ -50295,14 +52777,14 @@ REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI , 56 , SH_UN REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_EOI_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21 , 20 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_20_21 ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_20_21_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR , 22 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RELAXED_WR ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_PTAG_IN_AIBTAG , 23 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DISABLE_PTAG_IN_AIBTAG ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20 ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_EQP , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RELAXED_WR_EQP ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_DMA , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RELAXED_WR_DMA ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_IDX_IN_AIBTAG , 23 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_IDX_IN_AIBTAG ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_EOI_ESBE ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -50829,26 +53311,26 @@ REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP , 4 , SH_UN SH_FLD_CNT_EQP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_WAKEUP ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_WAKEUP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_LS ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_LS_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RESUME ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RESUME_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_EBB ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_EBB_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP , 20 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_GROUP ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_GROUP_LEN ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_BROADCAST ); -REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CNT_BROADCAST_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LS ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LS_LEN ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_BROADCAST_BL ); +REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_BROADCAST_BL_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_FWD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -52122,14 +54604,14 @@ REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP , 4 , SH_UN SH_FLD_CNT_IVVC_RESP ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVVC_RESP_LEN ); -REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_11 ); +REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_11_LEN ); +REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_WRITE ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_WRITE_LEN ); -REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15 , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_12_15 ); -REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_FETCH_REPLAY ); @@ -52219,20 +54701,208 @@ REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS , 27 , SH_UN REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); -REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR_LEN , 55 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_INVALID_STATE , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_INVALID_STATE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_CRD_ERROR , 1 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OFFSET_ERROR , 2 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_OFFSET_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DATA_ERROR , 3 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DATA_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ACCESS_ERROR , 4 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_ACCESS_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OVERFLOW , 5 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_IDX_ERROR , 6 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_IDX_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_UNDERFLOW , 7 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_UNDERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_STATE_ERROR , 8 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DIR_STATE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_WR_ERROR , 9 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DIR_WR_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_RD_ERROR , 10 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_DIR_RD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_UE , 11 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EQC_CREDIT_ERROR , 12 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EQC_CREDIT_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_TRIG_CRD_ERROR , 13 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_TRIG_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EFIFO_DIN_ERROR , 14 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EFIFO_DIN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_INPUT_BUF_ERROR , 15 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_INPUT_BUF_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EQ_ERROR , 16 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EQ_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_PQ_ERROR , 17 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_PQ_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_EQPQ_ERROR , 18 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_EQPQ_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_CE , 19 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IRQ_FIFO_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_CTRL_PTY_ERROR , 20 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_CTRL_PTY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_CMD_PTY_ERROR , 21 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_CMD_PTY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_SCOM_INTERNAL_ERROR , 22 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_SCOM_INTERNAL_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_UE , 23 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_UE , 24 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_DATA_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_PARITY_ERROR , 25 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_CMD_CRD_ERROR , 26 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_CMD_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_REGS_DATA_CRD_ERROR , 27 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_REGS_DATA_CRD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_CMD_ERROR , 28 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_CMD_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_RESP_TIMEOUT , 29 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_RESP_TIMEOUT ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_CE , 30 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_AIB_DATA_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_CE , 31 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ARX_TAG_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_LACK_OF_TAG , 32 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_LACK_OF_TAG ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_TAG_RELEASE_ERROR , 33 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_TAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_BAD_CAM_STATE , 34 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_BAD_CAM_STATE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_HIT , 35 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_MULTIPLE_HIT ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_PARITY_ERROR , 36 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_PRF_RQ , 37 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_MULTIPLE_PRF_RQ ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_TOO_LARGE_SLOTID , 38 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_TOO_LARGE_SLOTID ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_PRF_OVERFLOW , 39 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_PRF_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_PRF_UNDERFLOW , 40 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_PRF_UNDERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_CMD , 41 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_CMD ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_BAR , 42 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_IND_BAR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_PZ , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_IND_PZ ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_AT_INVALID_I , 44 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_AT_INVALID_I ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_CRD_PARITY_ERROR , 45 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_CRD_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_AT_SRAM_ECC_UE , 46 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_AT_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_BAR_SRAM_ECC_UE , 47 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_BAR_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_WB_SRAM_ECC_UE , 48 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_WB_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_SLOT_OVERFLOW , 49 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_SLOT_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_CRD_OVERFLOW , 50 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_CRD_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_CRD_UNDERFLOW , 51 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_CRD_UNDERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_INVALID_BAR , 52 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_INVALID_BAR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_PAGE_OVERFLOW , 53 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_PAGE_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G0_ATX_SRAM_ECC_CE , 54 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ATX_SRAM_ECC_CE ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_LEN ); -REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR_LEN , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CL_INDEX_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CL_INDEX_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CRD_OR_RESP_ERROR , 1 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CRD_OR_RESP_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PTAG_ASSIGN_ERROR , 2 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PTAG_ASSIGN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PTAG_RELEASE_ERROR , 3 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PTAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_REPLAY_ERROR , 4 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_REPLAY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PARITY_ERROR , 5 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_TAG_SRAM_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_STATE_SRAM_ECC_UE , 7 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_STATE_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_DATA_SRAM_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_DATA_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CTRL_SRAM_ECC_UE , 9 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CTRL_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_ARX_DATA_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_ARX_DATA_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_UNLOCK_FIFO_OVERFLOW , 11 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_UNLOCK_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_EOI_OVERFLOW , 12 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_EOI_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_EOI_TAG_ERROR , 13 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_EOI_TAG_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_SRAM_ECC_CE , 14 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_PROCESSING_ERROR , 15 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_PROCESSING_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_WATCH_ERROR , 16 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_WATCH_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_EQC_CONFIG_ERROR , 17 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_EQC_CONFIG_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_AIB_RESP_ERROR , 18 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_AIB_RESP_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PTAG_ASSIGN_ERROR , 19 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PTAG_ASSIGN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PTAG_RELEASE_ERROR , 20 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PTAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_REPLAY_ERROR , 21 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_REPLAY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PARITY_ERROR , 22 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_TAG_SRAM_ECC_UE , 23 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_STATE_SRAM_ECC_UE , 24 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_STATE_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_DATA_SRAM_ECC_UE , 25 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_DATA_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_UNLOCK_FIFO_OVERFLOW , 26 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_UNLOCK_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_SRAM_ECC_CE , 27 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_IVC_PROCESSING_ERROR , 28 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_IVC_PROCESSING_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_CL_INDEX_ERROR , 29 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_CL_INDEX_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_CRD_OR_RESP_ERROR , 30 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_CRD_OR_RESP_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PTAG_ASSIGN_ERROR , 31 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PTAG_ASSIGN_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PTAG_RELEASE_ERROR , 32 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PTAG_RELEASE_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_REPLAY_ERROR , 33 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_REPLAY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PARITY_ERROR , 34 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PARITY_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_TAG_SRAM_ECC_UE , 35 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_TAG_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_STATE_SRAM_ECC_UE , 36 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_STATE_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_DATA_SRAM_ECC_UE , 37 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_DATA_SRAM_ECC_UE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_UNLOCK_FIFO_OVERFLOW , 38 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_UNLOCK_FIFO_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_EOI_OVERFLOW , 39 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_EOI_OVERFLOW ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_EOI_TAG_ERROR , 40 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_EOI_TAG_ERROR ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_SRAM_ECC_CE , 41 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_SRAM_ECC_CE ); +REG64_FLD( PU_INT_VC_WOF_ERR_G1_SBC_PROCESSING_ERROR , 42 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_SBC_PROCESSING_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); @@ -52369,6 +55039,86 @@ REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT , 16 , SH_UN REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RAND_EVENT_LEN ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA0_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA0_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA1_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA1_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA10_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA10_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA11_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA11_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA12_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA12_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA13_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA13_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA14_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA14_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA15_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA15_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA2_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA2_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA3_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA3_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA4_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA4_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA5_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA5_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA6_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA6_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA7_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA7_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA8_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA8_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA9_DATA_BYTES , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES ); +REG64_FLD( CAPP_LINK_DELAY_RESP_DATA9_DATA_BYTES_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_BYTES_LEN ); + REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALUE ); REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE_LEN , 29 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -53162,6 +55912,135 @@ REG64_FLD( PU_LPC_STATUS_REG_VALID , 10 , SH_UN REG64_FLD( PU_LPC_STATUS_REG_ACK , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ACK ); +REG64_FLD( PHB_MASK_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_MASK_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_MASK_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_MASK_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_MASK_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_MASK_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_MASK_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_MASK_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_MASK_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_MASK_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_MASK_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_MASK_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_MASK_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_MASK_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_MASK_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_MASK_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_MASK_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_MASK_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_MASK_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_MASK_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_MASK_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_MASK_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_MASK_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_MASK_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_MASK_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_MASK_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_UE_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR , 1 , SH_UNT , SH_ACS_SCOM2_OR , @@ -53484,12 +56363,24 @@ REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( PU_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -53560,9 +56451,13 @@ REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH , 7 , SH_UN SH_FLD_PERF_PE_MATCH ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_PERF_PE_MATCH_LEN ); -REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_IPI_PS , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IPI_PS ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_IPI_OS , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IPI_OS ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD ); -REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN , 53 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN , 51 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD_LEN ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_STALL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -53744,6 +56639,8 @@ REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UN REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_0 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_0 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_BKINV_INTERLOCK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53756,6 +56653,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS , 9 , SH_UN SH_FLD_FBC_LFSR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_INV_AMORT_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_10_11 , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_10_11 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_DIN_ECC_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53786,6 +56685,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS , 25 , SH_UN SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_27 , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_MODE_THRESHOLD ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53821,6 +56722,22 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS , 21 , SH_UN SH_FLD_CAC_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LRU_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MULTIHIT_CHK_DIS , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MULTIHIT_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS505_FIX_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS505_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS510_FIX_DIS , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS510_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS511_FIX_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS511_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS544_FIX_DIS , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS544_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS554_FIX_DIS , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS554_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_28_31 , 29 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_28_31 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_28_31_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_28_31_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53829,6 +56746,12 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL , 36 , SH_UN SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51 , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_40_51 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_40_51_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS542_FIX_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS542_FIX_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TWSM_DIS ); @@ -53842,6 +56765,20 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN , 20 , SH_UN SH_FLD_INV_SINGLE_THREAD_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_CXT_CAC_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23 , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_22_23 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_22_23_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS487_EN , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS487_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_25 , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_25 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS526_EN , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS526_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29 , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_29 ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_29_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_MPSS_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53870,6 +56807,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L4_DIS , 49 , SH_UN SH_FLD_TW_LCO_RDX_PWC_L4_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN , 50 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PDE_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_51 , 51 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_51 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS , 53 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53880,6 +56819,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN , 55 , SH_UN SH_FLD_TW_RDX_PWC_SPLIT_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH , 56 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_VA_HASH ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_57 , 57 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_57 ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN , 58 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_PTE_UPD_INTR_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN , 59 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53915,6 +56856,16 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS , 25 , SH_UN SH_FLD_MULTIHIT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_EA_RANGE_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS426_FIX_DIS , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS426_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS486_FIX_DIS , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS486_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS505_FIX_DIS , 29 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS505_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS510_FIX_DIS , 30 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS510_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS512_FIX_DIS , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS512_FIX_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53923,14 +56874,28 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL , 36 , SH_UN SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); -REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS534_FIX_DIS , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS534_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS537_FIX_DIS , 41 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS537_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS540_FIX_DIS , 42 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS540_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543_FIX_DIS , 43 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS543_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_GUEST_PREF_PGSZ ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_GUEST_PREF_PGSZ_LEN ); -REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HOST_PREF_PGSZ ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HOST_PREF_PGSZ_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS542_FIX_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS542_FIX_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543B_FIX_EN , 53 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS543B_FIX_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS567_FIX_DIS , 54 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ISS567_FIX_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HRMOR ); @@ -54132,6 +57097,10 @@ REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL , 25 , SH_UN SH_FLD_TLB_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS1_STG1_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31 , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_31 ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31_LEN , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_27_31_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -54853,6 +57822,25 @@ REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UN REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_A ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_A_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_A_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_B , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_B ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_B_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_B_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_C , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_C ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_C_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_C_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_D , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_D ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_MUX_SEL_D_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_MUX_SEL_D_LEN ); +REG64_FLD( PEC_NESTTRC_REG_TRACE_ENABLE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_TRACE_ENABLE ); + REG64_FLD( PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); REG64_FLD( PEC_STACK0_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, @@ -54895,10 +57883,8 @@ REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_RCTRL , 19 , SH_UN SH_FLD_CPLT_RCTRL ); REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); -REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE0 ); -REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( PEC_STACK0_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( PEC_STACK0_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, @@ -54909,6 +57895,8 @@ REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PM_ACCESS ); REG64_FLD( PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); @@ -54950,6 +57938,10 @@ REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UN SH_FLD_CLK_PULSE_MODE ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); +REG64_FLD( PEC_STACK0_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS ); +REG64_FLD( PEC_STACK0_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); @@ -55213,6 +58205,39 @@ REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR , 48 , SH_UN REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MINOR_LEN ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK0_OVERRIDE ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK0_OVERRIDE_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK1_OVERRIDE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK1_OVERRIDE ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK1_OVERRIDE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_NRDSTKOVR_REG_N_RD_STACK_OVERRIDE_ENABLE , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_RD_STACK_OVERRIDE_ENABLE ); + +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK0_OVERRIDE ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK0_OVERRIDE_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK1_OVERRIDE , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK1_OVERRIDE ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK1_OVERRIDE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_NSTQSTKOVR_REG_N_ST_STACK_OVERRIDE_ENABLE , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_ST_STACK_OVERRIDE_ENABLE ); + +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK0_OVERRIDE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK1_OVERRIDE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK1_OVERRIDE_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_NWRSTKOVR_REG_N_WR_STACK_OVERRIDE_ENABLE , 24 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK_OVERRIDE_ENABLE ); + REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP , 1 , SH_UNT , SH_ACS_SCOM , @@ -55429,6 +58454,10 @@ REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_CRB_SUE , 28 , SH_UN SH_FLD_UMAC_CRB_SUE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_LOCAL_CSTOP , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_LOCAL_CSTOP ); +REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_SCOM_SAT_ERR , 30 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UMAC_SCOM_SAT_ERR ); +REG64_FLD( PU_NX_CQ_FIR_REG_SPARE , 31 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_FIRST_FAIL , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RNG_FIRST_FAIL ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_SECOND_FAIL , 33 , SH_UNT , SH_ACS_SCOM2_OR , @@ -55443,6 +58472,10 @@ REG64_FLD( PU_NX_CQ_FIR_REG_PBCQ_CNTRL_LOGIC_ERR , 37 , SH_UN SH_FLD_PBCQ_CNTRL_LOGIC_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_FAILED_LINK_ON_INTERRUPT , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FAILED_LINK_ON_INTERRUPT ); +REG64_FLD( PU_NX_CQ_FIR_REG_SPARES , 39 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARES ); +REG64_FLD( PU_NX_CQ_FIR_REG_SPARES_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARES_LEN ); REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE ); REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE_DUP , 43 , SH_UNT , SH_ACS_SCOM2_OR , @@ -55760,12 +58793,25 @@ REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT , 27 , SH_UN REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN ); +REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT ); +REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT_LEN ); REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); +REG64_FLD( PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT ); +REG64_FLD( PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN , 63 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT_LEN ); REG64_FLD( PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); +REG64_FLD( PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT ); +REG64_FLD( PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT_LEN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_NX_PBI_ERR_RPT_OUT_LEN ); + REG64_FLD( PU_NX_PMU0_CONTROL_REG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE , 1 , SH_UNT , SH_ACS_SCOM , @@ -56178,6 +59224,46 @@ REG64_FLD( PU_OCB_OCI_CCSR_RESERVED_24_LEN , 7 , SH_UN REG64_FLD( PU_OCB_OCI_CCSR_CHANGE_IN_PROGRESS , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHANGE_IN_PROGRESS ); +REG64_FLD( PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE0_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE1_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE2_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N ); +REG64_FLD( PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_GPE3_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCMD_A_N_RESERVED_0 ); REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -57055,6 +60141,26 @@ REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31 , 25 , SH_UN REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_24_31_LEN ); +REG64_FLD( PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_CRIT_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_DEBUG_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT2HALT_DELAY ); REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN , 20 , SH_UNT , SH_ACS_SCOM_RW , @@ -57285,6 +60391,16 @@ REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N , 0 , SH_UN REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N_LEN ); +REG64_FLD( PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N ); +REG64_FLD( PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_NONCRIT_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , @@ -58420,6 +61536,16 @@ REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N , 16 , SH_UN REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_N_LEN ); +REG64_FLD( PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N_LEN ); + +REG64_FLD( PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N ); +REG64_FLD( PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_UNCON_STATUS_N_LEN ); + REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG ); REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG_LEN , 24 , SH_UNT , SH_ACS_SCOM2_OR , @@ -58737,8 +61863,8 @@ REG64_FLD( PU_OCB_PIB_OCR_CRITICAL_INTERRUPT , 8 , SH_UN SH_FLD_CRITICAL_INTERRUPT ); REG64_FLD( PU_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SLAVE_RESET_TO_405_ENABLE ); -REG64_FLD( PU_OCB_PIB_OCR_OCR_DBG_HALT , 10 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_OCR_DBG_HALT ); +REG64_FLD( PU_OCB_PIB_OCR_OCC_DBG_HALT , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_OCC_DBG_HALT ); REG64_FLD( PU_OCB_PIB_OCR_SPARE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( PU_OCB_PIB_OCR_SPARE_LEN , 5 , SH_UNT , SH_ACS_SCOM2_OR , @@ -59119,8 +62245,8 @@ REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UN SH_FLD_MISR_INIT_WAIT ); REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); -REG64_FLD( PEC_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( PEC_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( PEC_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( PEC_OPCG_REG1_UNUSED2 , 50 , SH_UNT_PEC , SH_ACS_SCOM , @@ -59608,10 +62734,16 @@ REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK , 44 , SH_UN REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR_MASK , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_MASK ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED0 ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED0_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED0_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_DATASTART_MODE ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_DATASTART_MODE_LEN ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED1 , 19 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1 ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM , 20 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_TX_RESP_HWM ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -59636,11 +62768,169 @@ REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT , 36 , SH_UN SH_FLD_PE_ISMB_ERROR_INJECT ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ISMB_ERROR_INJECT_LEN ); +REG64_FLD( PEC_PBAIBHWCFG_REG_RESERVED2 , 39 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED2 ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT , 40 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PHB_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBHWCFG_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PHBRESET_PE , 1 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE , 2 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCITR_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE , 3 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXCCR_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE , 4 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIBTXDCR_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN , 5 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_OVERRUN ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR , 6 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_QCNT_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_TX_DAT_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE , 8 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE , 9 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE , 10 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE , 11 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_AVAIL_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE , 12 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_CMD_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE , 13 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PEAIB_DAT_CRD_PE ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR , 14 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PHBRESET_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_ASYNC_ERROR , 15 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_ASYNC_ERROR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR , 16 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_AIB_STACK_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR , 17 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_AIB_PEC_SCOM_ERR ); +REG64_FLD( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE , 18 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RO , + SH_FLD_PBAIB_FENCE_PCIE ); + REG64_FLD( PU_PBAMODE_RESERVED_0_3 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_3 ); REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN , 4 , SH_UNT , SH_ACS_PIB , @@ -60415,6 +63705,10 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE , 27 , SH_UN SH_FLD_PE_QFIFO_HOLD_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_QFIFO_HOLD_MODE_LEN ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED1 , 29 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1 ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED1_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_STRICT_ORDER_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN , 33 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -60431,6 +63725,8 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW , 38 , SH_UN SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW , 39 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_ENH_FLOW ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED2 , 40 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED2 ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG , 41 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_WR_VG ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP , 42 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -60441,6 +63737,10 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP , 44 , SH_UN SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE , 45 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED3 , 46 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED3 ); +REG64_FLD( PEC_PBCQHWCFG_REG_RESERVED3_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED3_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_WRITE_ORDERING ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -60650,6 +63950,8 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK , 53 , SH_UN SH_FLD_CFG_MC3_MCS0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC3_MCS1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_PB_CFG_CNPME_MASK , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_CNPME_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MCD_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -60771,6 +64073,39 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK , 58 , SH_UN SH_FLD_CFG_PE1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE2_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_PB_CFG_CNPMW_MASK , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_CNPMW_MASK ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ERROR , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CRESP_ERROR ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ADDR_ERROR , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CRESP_ADDR_ERROR ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_ERROR_OTHER , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_ERROR_OTHER ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTYPE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE_LEN , 7 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTYPE_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE , 10 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TSIZE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TSIZE_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG , 18 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTAG ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG_LEN , 22 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_TTAG_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_SCOPE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE_LEN , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_SCOPE_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP , 43 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_LEN , 5 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_CRESP_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_PRESP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP_LEN , 14 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_CFG_PRESP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE ); @@ -60918,6 +64253,15 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN , 16 , REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_PORT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_EXTDATASND_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_EXTDATASND_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_EXTDATARCV_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_EXTDATARCV_CNT_LEN ); + REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , @@ -61068,6 +64412,152 @@ REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7 , 56 , SH_UN REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL7_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN ); + REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61274,6 +64764,8 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_A_INDIRECT_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61357,6 +64849,8 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_CENT_A_INDIRECT_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61388,7 +64882,21 @@ REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP , 12 , SH_UN SH_FLD_CFG_APM_LM_LO_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_LM_LO_COMP_LEN ); - +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_LO_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_LO_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_HI_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_LM_HI_CNT_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_PBIXXX_INIT , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_PB_CENT_PBIXXX_INIT ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED , 1 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CENT_DBG_MAX_HANG_STAGE_REACHED ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61411,6 +64919,10 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK , 30 , SH_UN SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , @@ -61440,6 +64952,150 @@ REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP , 12 , SH_UN SH_FLD_CFG_APM_NM_LO_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_NM_LO_COMP_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_LO_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_LO_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_HI_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT_LEN , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_NM_HI_CNT_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0 , 0 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1 , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2 , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3 , 48 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN , 16 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C0 ); @@ -61568,6 +65224,15 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3 , 62 , SH_UN REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_PB_APM_RCMD_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_RCMD_CNT_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_INTDATA_CNT ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT_LEN , 32 , SH_UNT_PU_PB_CENT_SM1, + SH_ACS_SCOM , SH_FLD_PB_APM_INTDATA_CNT_LEN ); + REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , @@ -61948,6 +65613,162 @@ REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR , 32 , SH_UN REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH0 ); +REG64_FLD( PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0_LEN , 64 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH0_LEN ); + +REG64_FLD( PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH1 ); +REG64_FLD( PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1_LEN , 64 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_EAST_FW_SCRATCH1_LEN ); + +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_EN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_EN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_EN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_EN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_EN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_EN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_EN , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_EN , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_EN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID , 60 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN ); + +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_EN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_EN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_EN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_EN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_EN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_EN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_EN , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_EN , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_EN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID , 60 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN ); + REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT , SH_ACS_SCOM , @@ -62154,6 +65975,8 @@ REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UN SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_A_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_A_INDIRECT_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , @@ -62237,6 +66060,8 @@ REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UN SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_A_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_A_INDIRECT_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , @@ -62252,6 +66077,8 @@ REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UN REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); +REG64_FLD( PU_PB_EAST_MODE_PB_EAST_PBIXXX_INIT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_EAST_PBIXXX_INIT ); REG64_FLD( PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT , SH_ACS_SCOM , @@ -62274,12 +66101,18 @@ REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK , 30 , SH_UN SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); +REG64_FLD( PU_PB_EAST_MODE_PB_CFG_EAST_RESET_ERROR_CAPTURE , 63 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_CFG_EAST_RESET_ERROR_CAPTURE ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG ); @@ -62298,6 +66131,11 @@ REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UN REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); +REG64_FLD( PU_PB_EAST_SPARE_SPARE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE ); +REG64_FLD( PU_PB_EAST_SPARE_SPARE_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LEN ); + REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , @@ -62385,6 +66223,32 @@ REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT , 49 , SH_UN REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY_LEN ); + +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY_LEN ); +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY ); +REG64_FLD( PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY_LEN ); + REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, @@ -62626,11 +66490,652 @@ REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET , 0 , SH_UN SH_FLD_SET ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SET_LEN ); +REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RT_SPARE0 ); +REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RT_SPARE0_LEN ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1 , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2 , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3 , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3_LEN ); + +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1 , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2 , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3 , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3_LEN ); + +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1 , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2 , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2_LEN ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3 , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3 ); +REG64_FLD( PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3_LEN ); + +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE_LEN ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE ); +REG64_FLD( PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE_LEN ); + +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SUE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB23_SUE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB45_SUE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_UE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_UE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_CE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_CE_LEN ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_SUE ); +REG64_FLD( PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB67_SUE_LEN ); + +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CONTROL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_ADDR_PERR , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_DAT_HI_PERR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_DAT_LO_PERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_FRAME_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_PC0_CREDITERR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_PC1_CREDITERR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_PRSP_PTYERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_TTAG_PERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_VC0_CREDITERR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_VC1_CREDITERR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR0_RTAG_PTYERR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR0_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CONTROL_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_ADDR_PERR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_DAT_HI_PERR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_DAT_LO_PERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_FRAME_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_PC0_CREDITERR , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_PC1_CREDITERR , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_PRSP_PTYERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_TTAG_PERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_VC0_CREDITERR , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_VC1_CREDITERR , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR1_RTAG_PTYERR , 31 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR1_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CONTROL_ERROR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_ADDR_PERR , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC0_CREDITERR , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC1_CREDITERR , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC2_CREDITERR , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_CC3_CREDITERR , 37 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_DAT_HI_PERR , 38 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_DAT_LO_PERR , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_FRAME_CREDITERR , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_PC0_CREDITERR , 41 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_PC1_CREDITERR , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_PRSP_PTYERR , 43 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_TTAG_PERR , 44 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_VC0_CREDITERR , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_VC1_CREDITERR , 46 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR2_RTAG_PTYERR , 47 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR2_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CONTROL_ERROR , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_ADDR_PERR , 49 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_ADDR_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC0_CREDITERR , 50 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC1_CREDITERR , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC2_CREDITERR , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_CC3_CREDITERR , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_DAT_HI_PERR , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_DAT_LO_PERR , 55 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_FRAME_CREDITERR , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_PC0_CREDITERR , 57 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_PC1_CREDITERR , 58 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_PRSP_PTYERR , 59 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_TTAG_PERR , 60 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_TTAG_PERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_VC0_CREDITERR , 61 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_VC1_CREDITERR , 62 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM0123_ERR_FMR3_RTAG_PTYERR , 63 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR3_RTAG_PTYERR ); + +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CONTROL_ERROR , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_ADDR_PERR , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_DAT_HI_PERR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_DAT_LO_PERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_FRAME_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_PC0_CREDITERR , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_PC1_CREDITERR , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_PRSP_PTYERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_TTAG_PERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_VC0_CREDITERR , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_VC1_CREDITERR , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR0_RTAG_PTYERR , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CONTROL_ERROR , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_ADDR_PERR , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_DAT_HI_PERR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_DAT_LO_PERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_FRAME_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_PC0_CREDITERR , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_PC1_CREDITERR , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_PRSP_PTYERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_TTAG_PERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_VC0_CREDITERR , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_VC1_CREDITERR , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR1_RTAG_PTYERR , 31 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CONTROL_ERROR , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_ADDR_PERR , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_DAT_HI_PERR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_DAT_LO_PERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_FRAME_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_PC0_CREDITERR , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_PC1_CREDITERR , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_PRSP_PTYERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_TTAG_PERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_VC0_CREDITERR , 45 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_VC1_CREDITERR , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR2_RTAG_PTYERR , 47 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CONTROL_ERROR , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_ADDR_PERR , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_DAT_HI_PERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_DAT_LO_PERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_FRAME_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_PC0_CREDITERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_PC1_CREDITERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_PRSP_PTYERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_TTAG_PERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_VC0_CREDITERR , 61 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_VC1_CREDITERR , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM0123_ERR_FMR3_RTAG_PTYERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_RTAG_PTYERR ); + +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CONTROL_ERROR , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_ADDR_PERR , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_DAT_HI_PERR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_DAT_LO_PERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_FRAME_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_PC0_CREDITERR , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_PC1_CREDITERR , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_PRSP_PTYERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_TTAG_PERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_VC0_CREDITERR , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_VC1_CREDITERR , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR4_RTAG_PTYERR , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CONTROL_ERROR , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_ADDR_PERR , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_DAT_HI_PERR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_DAT_LO_PERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_FRAME_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_PC0_CREDITERR , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_PC1_CREDITERR , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_PRSP_PTYERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_TTAG_PERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_VC0_CREDITERR , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_VC1_CREDITERR , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR5_RTAG_PTYERR , 31 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CONTROL_ERROR , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_ADDR_PERR , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_DAT_HI_PERR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_DAT_LO_PERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_FRAME_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_PC0_CREDITERR , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_PC1_CREDITERR , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_PRSP_PTYERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_TTAG_PERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_VC0_CREDITERR , 45 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_VC1_CREDITERR , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR6_RTAG_PTYERR , 47 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_RTAG_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CONTROL_ERROR , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_ADDR_PERR , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_ADDR_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_DAT_HI_PERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_DAT_HI_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_DAT_LO_PERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_DAT_LO_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_FRAME_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_FRAME_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_PC0_CREDITERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_PC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_PC1_CREDITERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_PC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_PRSP_PTYERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_PRSP_PTYERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_TTAG_PERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_TTAG_PERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_VC0_CREDITERR , 61 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_VC1_CREDITERR , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_FM4567_ERR_FMR7_RTAG_PTYERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_RTAG_PTYERR ); + +REG64_FLD( PU_PB_FM45_ERR_FMR4_CONTROL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_ADDR_PERR , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_ADDR_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_DAT_HI_PERR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_DAT_LO_PERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_FRAME_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_PC0_CREDITERR , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_PC1_CREDITERR , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_PRSP_PTYERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_TTAG_PERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_TTAG_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_VC0_CREDITERR , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_VC1_CREDITERR , 14 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR4_RTAG_PTYERR , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR4_RTAG_PTYERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CONTROL_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CONTROL_ERROR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_ADDR_PERR , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_ADDR_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC2_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_CC3_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_DAT_HI_PERR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_HI_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_DAT_LO_PERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_DAT_LO_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_FRAME_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_FRAME_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_PC0_CREDITERR , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_PC1_CREDITERR , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_PRSP_PTYERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_PRSP_PTYERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_TTAG_PERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_TTAG_PERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_VC0_CREDITERR , 29 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC0_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_VC1_CREDITERR , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_VC1_CREDITERR ); +REG64_FLD( PU_PB_FM45_ERR_FMR5_RTAG_PTYERR , 31 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_FMR5_RTAG_PTYERR ); + REG64_FLD( PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_GATHERING , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -63308,6 +67813,11 @@ REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR_DUP , 62 , SH_UN REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR , 63 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); +REG64_FLD( PU_PB_IOE_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_PB_IOE_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN , 64 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -63568,6 +68078,11 @@ REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR_DUP , 62 , SH_UN REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_WOF_REG_WOF , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_IOE_PB_IOO_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IOE01_IS_LOGICAL_PAIR ); REG64_FLD( PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR , 1 , SH_UNT , SH_ACS_SCOM , @@ -63770,6 +68285,40 @@ REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT , 48 , SH_UN REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC1_LIMIT_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR0_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR1_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR2_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR3_LINK_DELAY_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR4_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR5_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR6_LINK_DELAY_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_LINK_DELAY ); +REG64_FLD( PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY_LEN , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_FMR7_LINK_DELAY_LEN ); + REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, @@ -64016,6 +68565,138 @@ REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UN REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_STAT_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB00_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB01_SCOM_SYN3_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB02_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB03_SCOM_SYN3_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB04_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB05_SCOM_SYN3_LEN ); + +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1 , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3 , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB06_SCOM_SYN3_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN0 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN0_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1 , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN1 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN1_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN2 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN2_LEN ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3 , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN3 ); +REG64_FLD( PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_DOB07_SCOM_SYN3_LEN ); + REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_ENABLE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE , 1 , SH_UNT , SH_ACS_SCOM_RW , @@ -64110,6 +68791,379 @@ REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK , 0 , SH_UN REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK_LEN , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); +REG64_FLD( PU_PB_PPE_LFIRWOF_LFIR_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_LFIR_WOF ); +REG64_FLD( PU_PB_PPE_LFIRWOF_LFIR_WOF_LEN , 14 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_LFIR_WOF_LEN ); + +REG64_FLD( PU_PB_PR0123_ERR_PRS0_ADDRESS_PTY , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_ATAG_PTY , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_CONTROL_ERROR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_PR0_CREDITERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_PR1_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_RTAG_PTY , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_TTAG_PTY , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_VC0_CREDITERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS0_VC1_CREDITERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_ADDRESS_PTY , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_ATAG_PTY , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_CONTROL_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_PR0_CREDITERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_PR1_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_RTAG_PTY , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_TTAG_PTY , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_VC0_CREDITERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS1_VC1_CREDITERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_ADDRESS_PTY , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_ATAG_PTY , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC0_CREDITERR , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC1_CREDITERR , 35 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC2_CREDITERR , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CC3_CREDITERR , 37 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_CONTROL_ERROR , 38 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_PR0_CREDITERR , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_PR1_CREDITERR , 40 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_RTAG_PTY , 41 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_TTAG_PTY , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_VC0_CREDITERR , 43 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS2_VC1_CREDITERR , 44 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_ADDRESS_PTY , 48 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_ATAG_PTY , 49 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ATAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC0_CREDITERR , 50 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC1_CREDITERR , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC2_CREDITERR , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CC3_CREDITERR , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_CONTROL_ERROR , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_PR0_CREDITERR , 55 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_PR1_CREDITERR , 56 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_RTAG_PTY , 57 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_RTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_TTAG_PTY , 58 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_TTAG_PTY ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_VC0_CREDITERR , 59 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR0123_ERR_PRS3_VC1_CREDITERR , 60 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC1_CREDITERR ); + +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_ADDRESS_PTY , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_ATAG_PTY , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_CONTROL_ERROR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_PR0_CREDITERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_PR1_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_RTAG_PTY , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_TTAG_PTY , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_VC0_CREDITERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS0_VC1_CREDITERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS0_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_ADDRESS_PTY , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_ATAG_PTY , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_CONTROL_ERROR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_PR0_CREDITERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_PR1_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_RTAG_PTY , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_TTAG_PTY , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_VC0_CREDITERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS1_VC1_CREDITERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS1_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_ADDRESS_PTY , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_ATAG_PTY , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_CONTROL_ERROR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_PR0_CREDITERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_PR1_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_RTAG_PTY , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_TTAG_PTY , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_VC0_CREDITERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS2_VC1_CREDITERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS2_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_ADDRESS_PTY , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_ATAG_PTY , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_CONTROL_ERROR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_PR0_CREDITERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_PR1_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_RTAG_PTY , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_TTAG_PTY , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_VC0_CREDITERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR0123_ERR_PRS3_VC1_CREDITERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS3_VC1_CREDITERR ); + +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_ADDRESS_PTY , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_ATAG_PTY , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC0_CREDITERR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC1_CREDITERR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC2_CREDITERR , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CC3_CREDITERR , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_CONTROL_ERROR , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_PR0_CREDITERR , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_PR1_CREDITERR , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_RTAG_PTY , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_TTAG_PTY , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_VC0_CREDITERR , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS4_VC1_CREDITERR , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_ADDRESS_PTY , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_ATAG_PTY , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC0_CREDITERR , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC1_CREDITERR , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC2_CREDITERR , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CC3_CREDITERR , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_CONTROL_ERROR , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_PR0_CREDITERR , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_PR1_CREDITERR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_RTAG_PTY , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_TTAG_PTY , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_VC0_CREDITERR , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS5_VC1_CREDITERR , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_ADDRESS_PTY , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_ATAG_PTY , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC0_CREDITERR , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC1_CREDITERR , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC2_CREDITERR , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CC3_CREDITERR , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_CONTROL_ERROR , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_PR0_CREDITERR , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_PR1_CREDITERR , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_RTAG_PTY , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_TTAG_PTY , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_VC0_CREDITERR , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS6_VC1_CREDITERR , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS6_VC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_ADDRESS_PTY , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_ADDRESS_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_ATAG_PTY , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_ATAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC0_CREDITERR , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC1_CREDITERR , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC2_CREDITERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC2_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CC3_CREDITERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CC3_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_CONTROL_ERROR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_CONTROL_ERROR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_PR0_CREDITERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_PR0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_PR1_CREDITERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_PR1_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_RTAG_PTY , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_RTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_TTAG_PTY , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_TTAG_PTY ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_VC0_CREDITERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_VC0_CREDITERR ); +REG64_FLD( PU_IOE_PB_PR4567_ERR_PRS7_VC1_CREDITERR , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RO , + SH_FLD_PRS7_VC1_CREDITERR ); + +REG64_FLD( PU_PB_PR45_ERR_PRS4_ADDRESS_PTY , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_ATAG_PTY , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_ATAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC0_CREDITERR , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC1_CREDITERR , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC2_CREDITERR , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CC3_CREDITERR , 5 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_CONTROL_ERROR , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_PR0_CREDITERR , 7 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_PR1_CREDITERR , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_RTAG_PTY , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_RTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_TTAG_PTY , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_TTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_VC0_CREDITERR , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS4_VC1_CREDITERR , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS4_VC1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_ADDRESS_PTY , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ADDRESS_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_ATAG_PTY , 17 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_ATAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC0_CREDITERR , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC1_CREDITERR , 19 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC2_CREDITERR , 20 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC2_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CC3_CREDITERR , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CC3_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_CONTROL_ERROR , 22 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_CONTROL_ERROR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_PR0_CREDITERR , 23 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_PR1_CREDITERR , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_PR1_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_RTAG_PTY , 25 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_RTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_TTAG_PTY , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_TTAG_PTY ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_VC0_CREDITERR , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC0_CREDITERR ); +REG64_FLD( PU_PB_PR45_ERR_PRS5_VC1_CREDITERR , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PRS5_VC1_CREDITERR ); + REG64_FLD( PU_PB_PSAVE_CFG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_PB_PSAVE_CFG_X0_ACT , 1 , SH_UNT , SH_ACS_SCOM , @@ -64166,6 +69220,396 @@ REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI , 43 , SH_UN REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X2_HI_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_00_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01 , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_01_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02 , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_02_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03 , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_03_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04 , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_04_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05 , 15 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_05_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06 , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_06_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07 , 21 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_07_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_08_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09 , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_09_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10 , 30 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_10_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11 , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_11_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12 , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_12_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13 , 39 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_13_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14 , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_14_LEN ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15 , 45 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15 ); +REG64_FLD( PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TDM_HUT_LUT_15_LEN ); + REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -64428,6 +69872,162 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH0 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0_LEN , 64 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH0_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH1 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1_LEN , 64 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , + SH_FLD_PB_WEST_FW_SCRATCH1_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_EN , 8 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_EN , 9 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_EN , 10 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_EN , 11 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID , 28 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID , 32 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID , 36 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID , 40 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID , 44 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID , 48 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID , 52 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID , 56 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID , 60 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN ); + REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64634,6 +70234,8 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_A_INDIRECT_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64717,6 +70319,8 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_U SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_A_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_A_INDIRECT_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64732,6 +70336,8 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_WEST_PBIXXX_INIT , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_WEST_PBIXXX_INIT ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , @@ -64754,16 +70360,18 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK , 30 , SH_UN SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); -REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , - SH_FLD_CFG_CPU_RATIO_OVERRIDE ); -REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , - SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_WEST_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, + SH_ACS_SCOM , SH_FLD_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_RESET_ERROR_CAPTURE , 63 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_CFG_WEST_RESET_ERROR_CAPTURE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG ); @@ -64782,6 +70390,11 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_WEST_SPARE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE_LEN , 64 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_PB_WEST_SPARE_LEN ); + REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , @@ -64825,6 +70438,63 @@ REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP , 0 , SH_UN REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP_LEN , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT_EN , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT_EN ); +REG64_FLD( PHB_PERF_CFG_REG_STOP_CORR_EN , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_STOP_CORR_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT0_LE_EN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT0_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT1_LE_EN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT1_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT2_LE_EN , 8 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT2_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT3_LE_EN , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT3_LE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT0_TE_EN , 10 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT0_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT1_TE_EN , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT1_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT2_TE_EN , 12 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT2_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_CNT3_TE_EN , 13 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_CNT3_TE_EN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT0_EVENT , 18 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT0_EVENT_LEN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_EVENT_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT1_EVENT , 26 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT1_EVENT_LEN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_EVENT_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT2_EVENT , 33 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT2_EVENT_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_EVENT_LEN ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT3_EVENT , 42 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_EVENT ); +REG64_FLD( PHB_PERF_CFG_REG_COUNT3_EVENT_LEN , 6 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_EVENT_LEN ); + +REG64_FLD( PHB_PERF_CNT0_REG_COUNT0_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_VALUE ); +REG64_FLD( PHB_PERF_CNT0_REG_COUNT0_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT0_VALUE_LEN ); + +REG64_FLD( PHB_PERF_CNT1_REG_COUNT1_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_VALUE ); +REG64_FLD( PHB_PERF_CNT1_REG_COUNT1_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT1_VALUE_LEN ); + +REG64_FLD( PHB_PERF_CNT2_REG_COUNT2_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_VALUE ); +REG64_FLD( PHB_PERF_CNT2_REG_COUNT2_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT2_VALUE_LEN ); + +REG64_FLD( PHB_PERF_CNT3_REG_COUNT3_VALUE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_VALUE ); +REG64_FLD( PHB_PERF_CNT3_REG_COUNT3_VALUE_LEN , 48 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_COUNT3_VALUE_LEN ); + REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -66085,6 +71755,46 @@ REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR , 0 , SH_UN REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR_LEN ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VLD , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_ADDR_VLD ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_4B , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_4B ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_AUTO_INC , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_AUTO_INC ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE , 51 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_ADDR_VALUE ); +REG64_FLD( PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE_LEN , 11 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_HV_REQ_ADDR_VALUE_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_HVIDR_SCOM_HV_REQ_READ_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_HV_REQ_READ_DATA ); +REG64_FLD( PHB_PHB4_SCOM_HVIDR_SCOM_HV_REQ_READ_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_HV_REQ_READ_DATA_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_HVIDWR_SCOM_HV_REQ_WRITE_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_HV_REQ_WRITE_DATA ); +REG64_FLD( PHB_PHB4_SCOM_HVIDWR_SCOM_HV_REQ_WRITE_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_HV_REQ_WRITE_DATA_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_REQ_ADDR_VLD , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_REQ_ADDR_VLD ); +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_AUTO_INC , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_AUTO_INC ); +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_REQ_ADDR_VALUE , 52 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_REQ_ADDR_VALUE ); +REG64_FLD( PHB_PHB4_SCOM_UVIAR_UV_REQ_ADDR_VALUE_LEN , 9 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_UV_REQ_ADDR_VALUE_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_UVIDR_SCOM_UV_REQ_READ_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_UV_REQ_READ_DATA ); +REG64_FLD( PHB_PHB4_SCOM_UVIDR_SCOM_UV_REQ_READ_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_RO , + SH_FLD_SCOM_UV_REQ_READ_DATA_LEN ); + +REG64_FLD( PHB_PHB4_SCOM_UVIDWR_SCOM_UV_REQ_WRITE_DATA , 0 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_UV_REQ_WRITE_DATA ); +REG64_FLD( PHB_PHB4_SCOM_UVIDWR_SCOM_UV_REQ_WRITE_DATA_LEN , 64 , SH_UNT_PHB , SH_ACS_SCOM_WO , + SH_FLD_SCOM_UV_REQ_WRITE_DATA_LEN ); + REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , @@ -66491,6 +72201,8 @@ REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB , 3 , SH_UN SH_FLD_ECC_UNCORRECTED_ERROR_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_PIB ); +REG64_FLD( PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_PIB , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAD_ARRAY_ADDRESS_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_RST_INTERRUPT_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB , 7 , SH_UNT , SH_ACS_SCOM , @@ -66543,6 +72255,11 @@ REG64_FLD( PU_PIB_RESET_REG_STATE , 1 , SH_UN REG64_FLD( PU_PIB_RESET_REG_ABORTED_CMD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORTED_CMD ); +REG64_FLD( PEC_PLL_LOCK_REG_LOCK , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCK ); +REG64_FLD( PEC_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCK_LEN ); + REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_EN ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -66551,6 +72268,10 @@ REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE , 32 , SH_UN SH_FLD_PE_PERFMON_READ_TYPE ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_READ_TYPE_LEN ); +REG64_FLD( PEC_PMONCTL_REG_RESERVED , 34 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED ); +REG64_FLD( PEC_PMONCTL_REG_RESERVED_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0 , 36 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE0 ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -66724,23 +72445,164 @@ REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3 , 48 , SH_UN REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_3_LEN ); +REG64_FLD( PU_PPE_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_PPE_FIR_ACTION0_REG_ACTION0_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_PPE_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_PPE_FIR_ACTION1_REG_ACTION1_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_PPE_FIR_MASK_REG_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ERROR_LEN , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_LEN ); +REG64_FLD( PU_PPE_FIR_MASK_REG_HALTED , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( PU_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG_TIMEOUT ); +REG64_FLD( PU_PPE_FIR_MASK_REG_MMIO_DATA_IN , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_DATA_IN ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MISSED_SCRUB_TICK ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ARB_ARY_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_UE ); +REG64_FLD( PU_PPE_FIR_MASK_REG_ARB_ARY_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_CE ); +REG64_FLD( PU_PPE_FIR_MASK_REG_RESERVED , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( PU_PPE_FIR_REG_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR ); +REG64_FLD( PU_PPE_FIR_REG_ERROR_LEN , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ERROR_LEN ); +REG64_FLD( PU_PPE_FIR_REG_HALTED , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( PU_PPE_FIR_REG_WATCHDOG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG_TIMEOUT ); +REG64_FLD( PU_PPE_FIR_REG_MMIO_DATA_IN , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_DATA_IN ); +REG64_FLD( PU_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MISSED_SCRUB_TICK ); +REG64_FLD( PU_PPE_FIR_REG_ARB_ARY_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_UE ); +REG64_FLD( PU_PPE_FIR_REG_ARB_ARY_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_CE ); +REG64_FLD( PU_PPE_FIR_REG_RESERVED , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( PU_PPE_FIR_REG_SCOMFIR_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR ); +REG64_FLD( PU_PPE_FIR_REG_SCOMFIR_ERROR_CLONE , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR_CLONE ); + +REG64_FLD( PU_PPE_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_PPE_FIR_WOF_REG_WOF_LEN , 13 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( PU_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( PU_PPE_XIDBGPRO_IAR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( PU_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( PU_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -66829,6 +72691,17 @@ REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END , 17 , SH_UN REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK0_OVERRIDE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK0_OVERRIDE_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK0_OVERRIDE_LEN ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK1_OVERRIDE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK1_OVERRIDE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK1_OVERRIDE_LEN ); +REG64_FLD( PEC_PRDSTKOVR_REG_N_WR_STACK_OVERRIDE_ENABLE , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_N_WR_STACK_OVERRIDE_ENABLE ); + REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_TIMEOUT_MASK ); REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -66852,6 +72725,11 @@ REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION , 32 , SH_UN REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRG_BIT_LOCATION_LEN ); +REG64_FLD( PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS ); +REG64_FLD( PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS_LEN ); + REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL ); REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -67983,6 +73861,68 @@ REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS , 0 , SH_UN REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_SM_RESET , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_SM_RESET ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_PSI_INTERRUPT_HIGH , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSI_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_OCC_INTERRUPT_HIGH , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OCC_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_FSI_INTERRUPT_HIGH , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSI_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LPC_INTERRUPT_HIGH , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LOCAL_INTERRUPT_HIGH , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_SYSTEM_ATTENTION_HIGH , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SYSTEM_ATTENTION_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_TPM_INTERRUPT_HIGH , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TPM_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_HIGH_LEN ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_SBE_OR_I2C_INTERRUPT_HIGH , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SBE_OR_I2C_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_DIO_INTERRUPT_HIGH , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIO_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_PSU_INTERRUPT_HIGH , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSU_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_I2C_C_INTERRUPT_HIGH , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2C_C_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_I2C_D_INTERRUPT_HIGH , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2C_D_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_I2C_E_INTERRUPT_HIGH , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2C_E_INTERRUPT_HIGH ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_RESERVED , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_RESERVED_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); +REG64_FLD( PU_PSIHB_INTERRUPT_LEVEL_PURE_SBE_INTERRUPT_HIGH , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PURE_SBE_INTERRUPT_HIGH ); + +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_PSI_INTERRUPT_PENDING , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSI_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_OCC_INTERRUPT_PENDING , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OCC_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_FSI_INTERRUPT_PENDING , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSI_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LPC_INTERRUPT_PENDING , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LOCAL_INTERRUPT_PENDING , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_SYSTEM_ATTENTION , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SYSTEM_ATTENTION ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_TPM_INTERRUPT_PENDING , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TPM_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LPC_OTHER_INTERRUPT_PENDING_LEN ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_SBE_INTERRUPT_PENDING , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SBE_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_DIO_INTERRUPT_PENDING , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DIO_INTERRUPT_PENDING ); +REG64_FLD( PU_PSIHB_INTERRUPT_STATUS_PSU_INTERRUPT_PENDING , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PSU_INTERRUPT_PENDING ); + REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE , 0 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_CMD_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE , 1 , SH_UNT , SH_ACS_SCOM2 , @@ -68576,6 +74516,9 @@ REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15 , 56 , SH_UN REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP15_LEN ); +REG64_FLD( PEC_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RECOV ); + REG64_FLD( PU_NPU0_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC ); REG64_FLD( PU_NPU0_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , @@ -68828,43 +74771,31 @@ REG64_FLD( PEC_RFIR_IN6 , 4 , SH_UN REG64_FLD( PEC_RFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6_LEN ); -REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , @@ -69016,8 +74947,55 @@ REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END , 17 , SH_UN REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); +REG64_FLD( PU_RX_CH_FSM_REG_RX_CH_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_CH_FSM ); +REG64_FLD( PU_RX_CH_FSM_REG_RX_CH_FSM_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_CH_FSM_LEN ); + +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_0 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_1 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_2 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_3 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_4 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_5 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_6 ); +REG64_FLD( PU_RX_CH_INTADDR_REG_SCOM_MODE_7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_7 ); + +REG64_FLD( PU_RX_CH_MISC_REG_FSM0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM0 ); +REG64_FLD( PU_RX_CH_MISC_REG_FSM0_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM0_LEN ); +REG64_FLD( PU_RX_CH_MISC_REG_FSM1 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM1 ); +REG64_FLD( PU_RX_CH_MISC_REG_FSM1_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM1_LEN ); +REG64_FLD( PU_RX_CH_MISC_REG_TFRAMESIZE , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE ); +REG64_FLD( PU_RX_CH_MISC_REG_TFRAMESIZE_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE_LEN ); +REG64_FLD( PU_RX_CH_MISC_REG_WEN0 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN0 ); +REG64_FLD( PU_RX_CH_MISC_REG_WEN1 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN1 ); +REG64_FLD( PU_RX_CH_MISC_REG_WEN2 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN2 ); +REG64_FLD( PU_RX_CH_MISC_REG_EN_SCRD , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_SCRD ); +REG64_FLD( PU_RX_CH_MISC_REG_STTRTOGX , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STTRTOGX ); + REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_RXRF ); +REG64_FLD( PU_RX_CTRL_STAT_REG_RXSC , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RXSC ); REG64_FLD( PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ECC_COR_RXRF_PSI ); REG64_FLD( PU_RX_CTRL_STAT_REG_CRC_MODE , 3 , SH_UNT , SH_ACS_SCOM , @@ -69031,6 +75009,77 @@ REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE , 6 , SH_UN REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHIP_PERSONALISATION ); +REG64_FLD( PU_RX_DBFF_REG0_DATA_BUFF0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0 ); +REG64_FLD( PU_RX_DBFF_REG0_DATA_BUFF0_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0_LEN ); + +REG64_FLD( PU_RX_DBFF_REG1_DATA_BUFF1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1 ); +REG64_FLD( PU_RX_DBFF_REG1_DATA_BUFF1_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1_LEN ); + +REG64_FLD( PU_RX_DF_FSM_REG_RX_DF_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_DF_FSM ); +REG64_FLD( PU_RX_DF_FSM_REG_RX_DF_FSM_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_DF_FSM_LEN ); + +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_RFGSHIFT_PCK , 0 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_RFGSHIFT_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_RZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_RZRTMP_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_DATA_PCK , 2 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_DATA_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXEI_SHIFT_PCK , 3 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXEI_SHIFT_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXEI_TRANSMIT_PCK , 4 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXEI_TRANSMIT_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXINS_OVERRUN , 5 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXINS_OVERRUN ); +REG64_FLD( PU_RX_ERROR_REG_C1_PSIRXBFF_DATA_PCK , 6 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSIRXBFF_DATA_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXBFF_DATAO_PCK , 7 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXBFF_DATAO_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXBFF_RFC_PCK , 8 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXBFF_RFC_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_FSM_PCK , 9 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_FSM_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRXLC_DATA_BUFF_PCK , 10 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRXLC_DATA_BUFF_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_DATA_PCK , 11 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_DATA_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_RADDR_PCK , 12 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_RADDR_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_RCTRL_PCK , 13 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_RCTRL_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRXLC_UE_RF , 14 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRXLC_UE_RF ); +REG64_FLD( PU_RX_ERROR_REG_C0_PSIRXLC_CE_RF , 15 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSIRXLC_CE_RF ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRXLC_DATA_GXST1_PCK_2N , 16 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRXLC_DATA_GXST1_PCK_2N ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRFACC_RADDR_PCK , 17 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRFACC_RADDR_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C2_PSIRFACC_RCTRL_PCK , 18 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSIRFACC_RCTRL_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRFACC_RFSM_PCK , 19 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_RFSM_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C3_PSIRFACC_RDL_FSM_PCK , 20 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_RDL_FSM_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C4_PSIRFACC_RXSC_PCK , 21 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C4_PSIRFACC_RXSC_PCK ); +REG64_FLD( PU_RX_ERROR_REG_C0_PSIRFACC_RLINK_STATE_LT_02 , 22 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSIRFACC_RLINK_STATE_LT_02 ); +REG64_FLD( PU_RX_ERROR_REG_C0_PSIRFACC_C_RXDATA_RDY_ERR , 23 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSIRFACC_C_RXDATA_RDY_ERR ); +REG64_FLD( PU_RX_ERROR_REG_C0_ERRACK_RISE , 24 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_ERRACK_RISE ); + +REG64_FLD( PU_RX_ERR_MODE_RX_ERR_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_ERR_MODE_0 ); +REG64_FLD( PU_RX_ERR_MODE_RX_ERR_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_ERR_MODE_1 ); + REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXINS_RFGSHIFT_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM , @@ -69079,7 +75128,11 @@ REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02 , 22 , SH_UN SH_FLD_PSIRFACC_RLINK_STATE_LT_02 ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR ); +REG64_FLD( PU_RX_MASK_REG_C0_ERRACK_RISE , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_C0_ERRACK_RISE ); +REG64_FLD( PU_RX_PSI_CNTL_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_CHECK_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_CHECK_EN ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL , 2 , SH_UNT , SH_ACS_SCOM , @@ -69124,6 +75177,12 @@ REG64_FLD( PU_RX_PSI_MODE_SPARE , 24 , SH_UN REG64_FLD( PU_RX_PSI_MODE_SPARE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL ); +REG64_FLD( PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL ); +REG64_FLD( PU_RX_PSI_STATUS_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL ); REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_LD_UNLD_DLY ); REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN , 4 , SH_UNT , SH_ACS_SCOM , @@ -69188,6 +75247,83 @@ REG64_FLD( PEC_SCAN_REGION_TYPE_CMSK , 58 , SH_UN REG64_FLD( PEC_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INEX ); +REG64_FLD( PEC_SCOM0X01_SDOCTL , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SDOCTL ); +REG64_FLD( PEC_SCOM0X01_SDOVAL , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SDOVAL ); +REG64_FLD( PEC_SCOM0X01_PCHKEN , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCHKEN ); +REG64_FLD( PEC_SCOM0X01_FRCERR , 53 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FRCERR ); +REG64_FLD( PEC_SCOM0X01_WRPSM , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRPSM ); +REG64_FLD( PEC_SCOM0X01_WPLPEN , 57 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WPLPEN ); +REG64_FLD( PEC_SCOM0X01_WRPMD , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRPMD ); +REG64_FLD( PEC_SCOM0X01_PRST , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRST ); +REG64_FLD( PEC_SCOM0X01_PATSEL , 60 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATSEL ); +REG64_FLD( PEC_SCOM0X01_PATSEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATSEL_LEN ); + +REG64_FLD( PEC_SCOM0X04_ROTA , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTA ); +REG64_FLD( PEC_SCOM0X04_ROTA_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTA_LEN ); +REG64_FLD( PEC_SCOM0X04_ROTB , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTB ); +REG64_FLD( PEC_SCOM0X04_ROTB_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROTB_LEN ); + +REG64_FLD( PEC_SCOM0X05_FREQFW , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREQFW ); +REG64_FLD( PEC_SCOM0X05_FREQFW_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREQFW_LEN ); +REG64_FLD( PEC_SCOM0X05_FWSNAP , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FWSNAP ); +REG64_FLD( PEC_SCOM0X05_FRCLEL , 57 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FRCLEL ); +REG64_FLD( PEC_SCOM0X05_ROT90 , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROT90 ); +REG64_FLD( PEC_SCOM0X05_ROT90_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ROT90_LEN ); + +REG64_FLD( PEC_SCOM0X2B_SMQM , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQM ); +REG64_FLD( PEC_SCOM0X2B_SMQM_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQM_LEN ); +REG64_FLD( PEC_SCOM0X2B_SMQ , 51 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQ ); +REG64_FLD( PEC_SCOM0X2B_SMQ_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMQ_LEN ); +REG64_FLD( PEC_SCOM0X2B_EMMD , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMMD ); +REG64_FLD( PEC_SCOM0X2B_EMMD_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMMD_LEN ); +REG64_FLD( PEC_SCOM0X2B_EMBRDY , 61 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMBRDY ); +REG64_FLD( PEC_SCOM0X2B_EMBUMP , 62 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMBUMP ); +REG64_FLD( PEC_SCOM0X2B_EMEN , 63 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMEN ); + +REG64_FLD( PEC_SCOM0X2C_EMF8 , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMF8 ); +REG64_FLD( PEC_SCOM0X2C_EMSF , 50 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMSF ); +REG64_FLD( PEC_SCOM0X2C_EMCNT , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCNT ); +REG64_FLD( PEC_SCOM0X2C_EMCNT_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCNT_LEN ); +REG64_FLD( PEC_SCOM0X2C_EMOFLO , 61 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMOFLO ); +REG64_FLD( PEC_SCOM0X2C_EMCRST , 62 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCRST ); +REG64_FLD( PEC_SCOM0X2C_EMCEN , 63 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EMCEN ); + REG64_FLD( PU_SCOM_PPE_CNTL_IORESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IORESET ); REG64_FLD( PU_SCOM_PPE_CNTL_PDWN , 1 , SH_UNT , SH_ACS_SCOM , @@ -69404,7 +75540,7 @@ REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UN SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); -REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -71215,16 +77351,18 @@ REG64_FLD( PEC_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); +REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( PEC_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); -REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNUSED1119 ); -REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNUSED1119_LEN ); +REG64_FLD( PEC_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PULSE_OUT_DIS ); +REG64_FLD( PEC_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1219 ); +REG64_FLD( PEC_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1219_LEN ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TRANSFER_SIZE ); @@ -71326,6 +77464,11 @@ REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR2 , 10 , SH_UN REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); +REG64_FLD( PU_SYNC_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( PU_SYNC_FIR_WOF_REG_WOF_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ALL , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ALL ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ONE , 2 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , @@ -71369,8 +77512,28 @@ REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71462,6 +77625,14 @@ REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71493,8 +77664,28 @@ REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71586,6 +77777,14 @@ REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71617,8 +77816,28 @@ REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71710,6 +77929,14 @@ REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71741,8 +77968,28 @@ REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71834,6 +78081,14 @@ REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71865,8 +78120,28 @@ REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -71958,6 +78233,14 @@ REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -71989,8 +78272,28 @@ REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72082,6 +78385,14 @@ REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72113,8 +78424,28 @@ REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72206,6 +78537,14 @@ REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72237,8 +78576,28 @@ REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72330,6 +78689,14 @@ REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72361,8 +78728,28 @@ REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72454,6 +78841,14 @@ REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72485,8 +78880,28 @@ REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72578,6 +78993,14 @@ REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72609,8 +79032,28 @@ REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72702,6 +79145,14 @@ REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72733,8 +79184,28 @@ REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72826,6 +79297,14 @@ REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72857,8 +79336,28 @@ REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -72950,6 +79449,14 @@ REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -72981,8 +79488,28 @@ REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73074,6 +79601,14 @@ REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73105,8 +79640,28 @@ REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73198,6 +79753,14 @@ REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73229,8 +79792,28 @@ REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73322,6 +79905,14 @@ REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73353,8 +79944,28 @@ REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73446,6 +80057,14 @@ REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73477,8 +80096,28 @@ REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73570,6 +80209,14 @@ REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73601,8 +80248,28 @@ REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73694,6 +80361,14 @@ REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73725,8 +80400,28 @@ REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73818,6 +80513,14 @@ REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73849,8 +80552,28 @@ REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -73942,6 +80665,14 @@ REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -73973,8 +80704,28 @@ REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74066,6 +80817,14 @@ REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74097,8 +80856,28 @@ REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74190,6 +80969,14 @@ REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74221,8 +81008,28 @@ REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74314,6 +81121,14 @@ REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74345,8 +81160,28 @@ REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74438,6 +81273,14 @@ REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74469,8 +81312,28 @@ REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74562,6 +81425,14 @@ REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74593,8 +81464,28 @@ REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74686,6 +81577,14 @@ REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74717,8 +81616,28 @@ REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74810,6 +81729,14 @@ REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74841,8 +81768,28 @@ REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -74934,6 +81881,14 @@ REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -74965,8 +81920,28 @@ REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -75058,6 +82033,14 @@ REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -75089,8 +82072,28 @@ REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -75182,6 +82185,14 @@ REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PU_NPU_SM2_TEST_CERR_ATR_ERR_INJ_PEND , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_ERR_INJ_PEND ); @@ -75196,10 +82207,74 @@ REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL , 58 , SH_UN REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITSEL_LEN ); +REG64_FLD( CAPP_TFMR_MAX_CYC_BET_STEPS , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MAX_CYC_BET_STEPS ); +REG64_FLD( CAPP_TFMR_MAX_CYC_BET_STEPS_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MAX_CYC_BET_STEPS_LEN ); +REG64_FLD( CAPP_TFMR_N_CLKS_PER_STEP , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_N_CLKS_PER_STEP ); +REG64_FLD( CAPP_TFMR_N_CLKS_PER_STEP_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_N_CLKS_PER_STEP_LEN ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT10 , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT10 ); +REG64_FLD( CAPP_TFMR_SYNC_BIT_SEL , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SYNC_BIT_SEL ); +REG64_FLD( CAPP_TFMR_SYNC_BIT_SEL_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SYNC_BIT_SEL_LEN ); +REG64_FLD( CAPP_TFMR_TB_ECLIPZ , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_ECLIPZ ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT15 , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT15 ); +REG64_FLD( CAPP_TFMR_LOAD_TOD_MOD , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LOAD_TOD_MOD ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT17 , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT17 ); +REG64_FLD( CAPP_TFMR_MOVE_CHIP_TOD_TO_TB , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MOVE_CHIP_TOD_TO_TB ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT19 , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT19 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT20 , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT20 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT21 , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT21 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT22 , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT22 ); +REG64_FLD( CAPP_TFMR_RESERVED_BIT23 , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_BIT23 ); +REG64_FLD( CAPP_TFMR_CLEAR_TB_ERRORS , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CLEAR_TB_ERRORS ); +REG64_FLD( CAPP_TFMR_TBST_CORRUPT , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_CORRUPT ); +REG64_FLD( CAPP_TFMR_TBST_ENCODED , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_ENCODED ); +REG64_FLD( CAPP_TFMR_TBST_ENCODED_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_ENCODED_LEN ); +REG64_FLD( CAPP_TFMR_TBST_LAST , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_LAST ); +REG64_FLD( CAPP_TFMR_TBST_LAST_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_LAST_LEN ); +REG64_FLD( CAPP_TFMR_TB_ENABLED , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_ENABLED ); +REG64_FLD( CAPP_TFMR_TB_VALID , 41 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_VALID ); +REG64_FLD( CAPP_TFMR_TB_SYNC_OCCURRED , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_SYNC_OCCURRED ); +REG64_FLD( CAPP_TFMR_TB_MISSING_SYNC , 43 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_MISSING_SYNC ); +REG64_FLD( CAPP_TFMR_TB_MISSING_STEP , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_MISSING_STEP ); +REG64_FLD( CAPP_TFMR_TB_RESIDUE_ERR , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_RESIDUE_ERR ); +REG64_FLD( CAPP_TFMR_FIRMWARE_CONTROL_ERROR , 46 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FIRMWARE_CONTROL_ERROR ); REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS , 47 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_TOD_STATUS ); REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_TOD_STATUS_LEN ); +REG64_FLD( CAPP_TFMR_CHIP_TOD_INTERRUPT , 51 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CHIP_TOD_INTERRUPT ); +REG64_FLD( CAPP_TFMR_TFMR_CORRUPT , 60 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TFMR_CORRUPT ); REG64_FLD( PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -75235,6 +82310,15 @@ REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UN SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); +REG64_FLD( PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1 ); +REG64_FLD( PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1_LEN ); + +REG64_FLD( PEC_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT ); +REG64_FLD( PEC_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT_LEN ); REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_VALUE ); @@ -75256,6 +82340,229 @@ REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR , 4 , SH_UN REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SNP_TTAG_PERR ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG0_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG1_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG1_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG10_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG10_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG11_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG11_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG12_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG12_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG13_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG13_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG14_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG14_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG15_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG15_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG2_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG2_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG3_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG3_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG4_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG4_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG5_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG5_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG6_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG6_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG7_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG7_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG8_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG8_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_FILTER_REG9_LVALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_PVALID , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PVALID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_PID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_LPID , 52 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_TLBI_FILTER_REG9_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); + +REG64_FLD( CAPP_TLBI_QOS_COMPARE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COMPARE ); +REG64_FLD( CAPP_TLBI_QOS_COMPARE_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COMPARE_LEN ); +REG64_FLD( CAPP_TLBI_QOS_INC , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_INC ); +REG64_FLD( CAPP_TLBI_QOS_INC_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_INC_LEN ); +REG64_FLD( CAPP_TLBI_QOS_DEC , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DEC ); +REG64_FLD( CAPP_TLBI_QOS_DEC_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DEC_LEN ); +REG64_FLD( CAPP_TLBI_QOS_EN , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EN ); + REG64_FLD( PU_TOD_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR ); REG64_FLD( PU_TOD_CMD_REG_ADR_LEN , 31 , SH_UNT , SH_ACS_SCOM , @@ -75282,12 +82589,57 @@ REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS_LEN , 4 , SH_UN REG64_FLD( PU_TRUST_CONTROL_FSP_TCE_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSP_TCE_ENABLE ); +REG64_FLD( PU_TRUST_CONTROL_SECURE_BOOTH , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SECURE_BOOTH ); REG64_FLD( PEC_TUNNEL_BAR_REG_PE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE ); REG64_FLD( PEC_TUNNEL_BAR_REG_PE_LEN , 43 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_LEN ); +REG64_FLD( PU_TX_CH_FSM_REG_TX_CH_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_CH_FSM ); +REG64_FLD( PU_TX_CH_FSM_REG_TX_CH_FSM_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_CH_FSM_LEN ); + +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_0 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_1 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_2 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_3 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_4 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_5 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_6 ); +REG64_FLD( PU_TX_CH_INTADDR_REG_SCOM_MODE_7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_MODE_7 ); + +REG64_FLD( PU_TX_CH_MISC_REG_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM ); +REG64_FLD( PU_TX_CH_MISC_REG_FSM_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM_LEN ); +REG64_FLD( PU_TX_CH_MISC_REG_TFRAMESIZE , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE ); +REG64_FLD( PU_TX_CH_MISC_REG_TFRAMESIZE_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TFRAMESIZE_LEN ); +REG64_FLD( PU_TX_CH_MISC_REG_WEN0 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN0 ); +REG64_FLD( PU_TX_CH_MISC_REG_WEN1 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN1 ); +REG64_FLD( PU_TX_CH_MISC_REG_WEN2 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WEN2 ); +REG64_FLD( PU_TX_CH_MISC_REG_DATA_REQ , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_REQ ); +REG64_FLD( PU_TX_CH_MISC_REG_START_TRANS , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_START_TRANS ); +REG64_FLD( PU_TX_CH_MISC_REG_GXDATAAVAIL_Q , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_GXDATAAVAIL_Q ); + REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_TXRF ); REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI , 1 , SH_UNT , SH_ACS_SCOM , @@ -75310,6 +82662,85 @@ REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE , 9 , SH_UN SH_FLD_FENCE_GX_INTERFACE ); REG64_FLD( PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_GX_ENABLE_OVERWRITE ); +REG64_FLD( PU_TX_CTRL_STAT_REG_TXSC , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TXSC ); + +REG64_FLD( PU_TX_DBFF_REG0_DATA_BUFF0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0 ); +REG64_FLD( PU_TX_DBFF_REG0_DATA_BUFF0_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF0_LEN ); + +REG64_FLD( PU_TX_DBFF_REG1_DATA_BUFF1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1 ); +REG64_FLD( PU_TX_DBFF_REG1_DATA_BUFF1_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_BUFF1_LEN ); + +REG64_FLD( PU_TX_DF_FSM_REG_TX_DF_FSM , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_DF_FSM ); +REG64_FLD( PU_TX_DF_FSM_REG_TX_DF_FSM_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_DF_FSM_LEN ); + +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_DATA_PCK , 0 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_DATA_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_TZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_TZRTMP_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXEI_SHIFT_PCK , 2 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXEI_SHIFT_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXEI_TRANSMIT_PCK , 3 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXEI_TRANSMIT_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_PARITY , 4 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_PARITY ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXINS_UNDERRUN , 5 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXINS_UNDERRUN ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXBFF_DATA_PCK , 6 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXBFF_DATA_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C1_PSITXBFF_TDO_PCK , 7 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C1_PSITXBFF_TDO_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXBFF_TFC_PCK , 8 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXBFF_TFC_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_FSM_PCK , 9 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_FSM_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_DATA_BUFF_PCK , 10 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_DATA_BUFF_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_TDO_PCK , 11 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_TDO_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_TADDR_PCK , 12 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_TADDR_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_TCTRL_PCK , 13 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_TCTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C2_PSITXLC_UE_RF , 14 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C2_PSITXLC_UE_RF ); +REG64_FLD( PU_TX_ERROR_REG_C0_PSITXLC_CE_RF , 15 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSITXLC_CE_RF ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_UE_GX_2N , 16 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_UE_GX_2N ); +REG64_FLD( PU_TX_ERROR_REG_C0_PSITXLC_CE_GX_2N , 17 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C0_PSITXLC_CE_GX_2N ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST2_PCK_2N , 18 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_DATA_GXST2_PCK_2N ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST3_PCK_2N , 19 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSITXLC_DATA_GXST3_PCK_2N ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TADDR_PCK , 20 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TADDR_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TCTRL_PCK , 21 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TCTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_CMD_CTRL_PCK , 22 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_CMD_CTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RSP_CTRL_PCK , 23 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_RSP_CTRL_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TFSM_PCK , 24 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TFSM_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_FSM_PCK , 25 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_FSM_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C4_PSIRFACC_TXSC_PCK , 26 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C4_PSIRFACC_TXSC_PCK ); +REG64_FLD( PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RETRY_ERR , 27 , SH_UNT , SH_ACS_SCOM1_OR , + SH_FLD_C3_PSIRFACC_TDL_RETRY_ERR ); + +REG64_FLD( PU_TX_ERR_MODE_TX_ERR_MODE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_ERR_MODE_0 ); +REG64_FLD( PU_TX_ERR_MODE_TX_ERR_MODE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_ERR_MODE_1 ); REG64_FLD( PU_TX_MASK_REG_PSITXINS_DATA_PCK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXINS_DATA_PCK ); @@ -75368,6 +82799,8 @@ REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TXSC_PCK , 26 , SH_UN REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TDL_RETRY_ERR ); +REG64_FLD( PU_TX_PSI_CNTL_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( PU_TX_PSI_CNTL_DRV_PATTERN_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DRV_PATTERN_EN ); REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL , 2 , SH_UNT , SH_ACS_SCOM , @@ -75430,6 +82863,10 @@ REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR , 4 , SH_UN SH_FLD_BIST_ERROR ); REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_ERROR_LEN ); +REG64_FLD( PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_PSI_BIST_DONE_RO_SIGNAL ); +REG64_FLD( PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TX_PSI_BIST_DONE_RO_SIGNAL_LEN ); REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_VALUE ); @@ -75872,6 +83309,8 @@ REG64_FLD( PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR , 21 , SH_UN SH_FLD_IN_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR ); +REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED23 ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR , 25 , SH_UNT , SH_ACS_SCOM2_OR , @@ -75979,6 +83418,8 @@ REG64_FLD( PU_VAS_FIR_REG_IN_PARITY_ERROR , 21 , SH_UN SH_FLD_IN_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_SW_CAST_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR ); +REG64_FLD( PU_VAS_FIR_REG_UNUSED23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED23 ); REG64_FLD( PU_VAS_FIR_REG_EG_ECC_SUE_ERROR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_ECC_SUE_ERROR , 25 , SH_UNT , SH_ACS_SCOM2_OR , @@ -76874,6 +84315,135 @@ REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PHB_WOF_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_WOF_REG_AIB_ADDRESSING_ERROR , 1 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_ADDRESSING_ERROR ); +REG64_FLD( PHB_WOF_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_WOF_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED , 3 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_WOF_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_WOF_REG_AIB_INF_CLASS_ERROR , 5 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_WOF_REG_PE_STOP_STATE_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PE_STOP_STATE_ERROR ); +REG64_FLD( PHB_WOF_REG_AIB_DAT_ERR_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_AIB_DAT_ERR_SIGNALED ); +REG64_FLD( PHB_WOF_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_WOF_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_WOF_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_WOF_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_WOF_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_REG_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_WOF_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_WOF_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_WOF_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_WOF_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_WOF_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED , 39 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED ); +REG64_FLD( PHB_WOF_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_WOF_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_WOF_REG_MRG_RESERVED01 , 54 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_RESERVED01 ); +REG64_FLD( PHB_WOF_REG_MRG_RESERVED02 , 55 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_MRG_RESERVED02 ); +REG64_FLD( PHB_WOF_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_COMMON_FATAL_ERRORS , 59 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_COMMON_FATAL_ERRORS ); +REG64_FLD( PHB_WOF_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_WOF_REG_TCE_RESERVED01 , 62 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_TCE_RESERVED01 ); +REG64_FLD( PHB_WOF_REG_LEM_FIR_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM_WCLRREG, + SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -77384,6 +84954,9 @@ REG64_FLD( PEC_XSTOP3_WAIT_CYCLES , 48 , SH_UN REG64_FLD( PEC_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); +REG64_FLD( PEC_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -78011,9 +85584,11 @@ REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREFEVOD , 10 , SH_UN SH_FLD_PREFEVOD ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_EAINJ , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_EAINJ ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_SPL_ONLY , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_SPL_ONLY ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 13 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1 ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses.H index 45e31c49..afb31b13 100644 --- a/src/import/chips/p9/common/include/p9_obus_scom_addresses.H +++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses.H @@ -239,6 +239,41 @@ #include <p9_obus_scom_addresses_fixes.H> +REG64( OBUS_FIR_ACTION0_REG , RULL(0x09010C06), SH_UNT_OBUS , SH_ACS_SCOM_RW ); +REG64( OBUS_0_FIR_ACTION0_REG , RULL(0x09010C06), SH_UNT_OBUS_0 , SH_ACS_SCOM_RW ); +REG64( OBUS_3_FIR_ACTION0_REG , RULL(0x0C010C06), SH_UNT_OBUS_3 , SH_ACS_SCOM_RW ); + +REG64( OBUS_FIR_ACTION1_REG , RULL(0x09010C07), SH_UNT_OBUS , SH_ACS_SCOM_RW ); +REG64( OBUS_0_FIR_ACTION1_REG , RULL(0x09010C07), SH_UNT_OBUS_0 , SH_ACS_SCOM_RW ); +REG64( OBUS_3_FIR_ACTION1_REG , RULL(0x0C010C07), SH_UNT_OBUS_3 , SH_ACS_SCOM_RW ); + +REG64( OBUS_FIR_MASK_REG , RULL(0x09010C03), SH_UNT_OBUS , SH_ACS_SCOM_RW ); +REG64( OBUS_FIR_MASK_REG_AND , RULL(0x09010C04), SH_UNT_OBUS , SH_ACS_SCOM1_AND ); +REG64( OBUS_FIR_MASK_REG_OR , RULL(0x09010C05), SH_UNT_OBUS , SH_ACS_SCOM2_OR ); +REG64( OBUS_0_FIR_MASK_REG , RULL(0x09010C03), SH_UNT_OBUS_0 , SH_ACS_SCOM_RW ); +REG64( OBUS_0_FIR_MASK_REG_AND , RULL(0x09010C04), SH_UNT_OBUS_0 , SH_ACS_SCOM1_AND ); +REG64( OBUS_0_FIR_MASK_REG_OR , RULL(0x09010C05), SH_UNT_OBUS_0 , SH_ACS_SCOM2_OR ); +REG64( OBUS_3_FIR_MASK_REG , RULL(0x0C010C03), SH_UNT_OBUS_3 , SH_ACS_SCOM_RW ); +REG64( OBUS_3_FIR_MASK_REG_AND , RULL(0x0C010C04), SH_UNT_OBUS_3 , SH_ACS_SCOM1_AND ); +REG64( OBUS_3_FIR_MASK_REG_OR , RULL(0x0C010C05), SH_UNT_OBUS_3 , SH_ACS_SCOM2_OR ); + +REG64( OBUS_FIR_REG , RULL(0x09010C00), SH_UNT_OBUS , SH_ACS_SCOM_RW ); +REG64( OBUS_FIR_REG_AND , RULL(0x09010C01), SH_UNT_OBUS , SH_ACS_SCOM1_AND ); +REG64( OBUS_FIR_REG_OR , RULL(0x09010C02), SH_UNT_OBUS , SH_ACS_SCOM2_OR ); +REG64( OBUS_0_FIR_REG , RULL(0x09010C00), SH_UNT_OBUS_0 , SH_ACS_SCOM_RW ); +REG64( OBUS_0_FIR_REG_AND , RULL(0x09010C01), SH_UNT_OBUS_0 , SH_ACS_SCOM1_AND ); +REG64( OBUS_0_FIR_REG_OR , RULL(0x09010C02), SH_UNT_OBUS_0 , SH_ACS_SCOM2_OR ); +REG64( OBUS_3_FIR_REG , RULL(0x0C010C00), SH_UNT_OBUS_3 , SH_ACS_SCOM_RW ); +REG64( OBUS_3_FIR_REG_AND , RULL(0x0C010C01), SH_UNT_OBUS_3 , SH_ACS_SCOM1_AND ); +REG64( OBUS_3_FIR_REG_OR , RULL(0x0C010C02), SH_UNT_OBUS_3 , SH_ACS_SCOM2_OR ); + +REG64( OBUS_FIR_WOF_REG , RULL(0x09010C08), SH_UNT_OBUS , + SH_ACS_SCOM_WCLRREG ); +REG64( OBUS_0_FIR_WOF_REG , RULL(0x09010C08), SH_UNT_OBUS_0 , + SH_ACS_SCOM_WCLRREG ); +REG64( OBUS_3_FIR_WOF_REG , RULL(0x0C010C08), SH_UNT_OBUS_3 , + SH_ACS_SCOM_WCLRREG ); + REG64( OBUS_LL0_IOOL_CONFIG , RULL(0x0901080A), SH_UNT_OBUS , SH_ACS_SCOM ); REG64( OBUS_0_LL0_IOOL_CONFIG , RULL(0x0901080A), SH_UNT_OBUS_0 , SH_ACS_SCOM ); @@ -251,6 +286,11 @@ REG64( OBUS_0_LL0_IOOL_DLL_STATUS , RULL(0x09010828 REG64( OBUS_LL0_IOOL_ERR_INJ_LFSR , RULL(0x0901081B), SH_UNT_OBUS , SH_ACS_SCOM ); REG64( OBUS_0_LL0_IOOL_ERR_INJ_LFSR , RULL(0x0901081B), SH_UNT_OBUS_0 , SH_ACS_SCOM ); +REG64( OBUS_LL0_IOOL_FIR_WOF_REG , RULL(0x09010808), SH_UNT_OBUS , + SH_ACS_SCOM_WCLRREG ); +REG64( OBUS_0_LL0_IOOL_FIR_WOF_REG , RULL(0x09010808), SH_UNT_OBUS_0 , + SH_ACS_SCOM_WCLRREG ); + REG64( OBUS_LL0_IOOL_LAT_MEASURE , RULL(0x0901080E), SH_UNT_OBUS , SH_ACS_SCOM ); REG64( OBUS_0_LL0_IOOL_LAT_MEASURE , RULL(0x0901080E), SH_UNT_OBUS_0 , SH_ACS_SCOM ); @@ -367,6 +407,9 @@ REG64( OBUS_3_LL3_IOOL_DLL_STATUS , RULL(0x0C010828 REG64( OBUS_3_LL3_IOOL_ERR_INJ_LFSR , RULL(0x0C01081B), SH_UNT_OBUS_3 , SH_ACS_SCOM ); +REG64( OBUS_3_LL3_IOOL_FIR_WOF_REG , RULL(0x0C010808), SH_UNT_OBUS_3 , + SH_ACS_SCOM_WCLRREG ); + REG64( OBUS_3_LL3_IOOL_LAT_MEASURE , RULL(0x0C01080E), SH_UNT_OBUS_3 , SH_ACS_SCOM ); REG64( OBUS_3_LL3_IOOL_LINK0_EDPL_STATUS , RULL(0x0C010824), SH_UNT_OBUS_3 , SH_ACS_SCOM_RO ); @@ -7080,6 +7123,13 @@ REG64( OBUS_0_RX0_RX_GLBSM_CNTL3_EO_PG , RULL(0x800AE800 REG64( OBUS_3_RX0_RX_GLBSM_CNTL3_EO_PG , RULL(0x800AE8000C010C3F), SH_UNT_OBUS_3 , SH_ACS_SCOM ); +REG64( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF00009010C3F), SH_UNT_OBUS , + SH_ACS_SCOM ); +REG64( OBUS_0_RX0_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF00009010C3F), SH_UNT_OBUS_0 , + SH_ACS_SCOM ); +REG64( OBUS_3_RX0_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF0000C010C3F), SH_UNT_OBUS_3 , + SH_ACS_SCOM ); + REG64( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB00009010C3F), SH_UNT_OBUS , SH_ACS_SCOM ); REG64( OBUS_0_RX0_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB00009010C3F), SH_UNT_OBUS_0 , diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H index cc4f4940..2e4954d4 100644 --- a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H @@ -41,6 +41,51 @@ #include <p9_scom_template_consts.H> #include <p9_obus_scom_addresses_fld_fixes.H> +REG64_FLD( OBUS_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_OBUS , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( OBUS_FIR_ACTION0_REG_ACTION0_LEN , 50 , SH_UNT_OBUS , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( OBUS_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_OBUS , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( OBUS_FIR_ACTION1_REG_ACTION1_LEN , 50 , SH_UNT_OBUS , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( OBUS_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR , 0 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( OBUS_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR , 1 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( OBUS_FIR_MASK_REG_GCR_HANG_ERROR , 2 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_GCR_HANG_ERROR ); +REG64_FLD( OBUS_FIR_MASK_REG_UNUSED , 3 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED ); +REG64_FLD( OBUS_FIR_MASK_REG_UNUSED_LEN , 45 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_LEN ); +REG64_FLD( OBUS_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 48 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( OBUS_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 49 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( OBUS_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR , 0 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( OBUS_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR , 1 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( OBUS_FIR_REG_GCR_HANG_ERROR , 2 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_GCR_HANG_ERROR ); +REG64_FLD( OBUS_FIR_REG_UNUSED , 3 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED ); +REG64_FLD( OBUS_FIR_REG_UNUSED_LEN , 45 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_LEN ); +REG64_FLD( OBUS_FIR_REG_SCOMFIR_ERROR , 48 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR ); +REG64_FLD( OBUS_FIR_REG_SCOMFIR_ERROR_CLONE , 49 , SH_UNT_OBUS , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR_CLONE ); + +REG64_FLD( OBUS_FIR_WOF_REG_WOF , 0 , SH_UNT_OBUS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( OBUS_FIR_WOF_REG_WOF_LEN , 50 , SH_UNT_OBUS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( OBUS_LL0_IOOL_CONFIG_LINK_PAIR , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LINK_PAIR ); REG64_FLD( OBUS_LL0_IOOL_CONFIG_DISABLE_SL_ECC , 1 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -205,6 +250,11 @@ REG64_FLD( OBUS_LL0_IOOL_ERR_INJ_LFSR_LFSR , 0 , SH_UN REG64_FLD( OBUS_LL0_IOOL_ERR_INJ_LFSR_LFSR_LEN , 61 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LFSR_LEN ); +REG64_FLD( OBUS_LL0_IOOL_FIR_WOF_REG_WOF , 0 , SH_UNT_OBUS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( OBUS_LL0_IOOL_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT_OBUS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LINK0_ROUND_TRIP_VALID ); REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP , 2 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -1430,6 +1480,13 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -1444,10 +1501,8 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -1503,16 +1558,61 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -1550,12 +1650,6 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -1714,6 +1808,11 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -1792,6 +1891,13 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -1806,10 +1912,8 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -1865,16 +1969,61 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -1912,12 +2061,6 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -2076,6 +2219,11 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2154,6 +2302,13 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2168,10 +2323,8 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -2227,16 +2380,61 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2274,12 +2472,6 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -2438,6 +2630,11 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2516,6 +2713,13 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2530,10 +2734,8 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -2589,16 +2791,61 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2636,12 +2883,6 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -2800,6 +3041,11 @@ REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2878,6 +3124,13 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2892,10 +3145,8 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -2951,16 +3202,61 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -2998,12 +3294,6 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -3162,6 +3452,11 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3240,6 +3535,13 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3254,10 +3556,8 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -3313,16 +3613,61 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3360,12 +3705,6 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -3524,6 +3863,11 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3602,6 +3946,13 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3616,10 +3967,8 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -3675,16 +4024,61 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3722,12 +4116,6 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -3886,6 +4274,11 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3964,6 +4357,13 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -3978,10 +4378,8 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -4037,16 +4435,61 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4084,12 +4527,6 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -4248,6 +4685,11 @@ REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4326,6 +4768,13 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4340,10 +4789,8 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -4399,16 +4846,61 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4446,12 +4938,6 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -4610,6 +5096,11 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4688,6 +5179,13 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4702,10 +5200,8 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -4761,16 +5257,61 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -4808,12 +5349,6 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -4972,6 +5507,11 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5050,6 +5590,13 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5064,10 +5611,8 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -5123,16 +5668,61 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5170,12 +5760,6 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -5334,6 +5918,11 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5412,6 +6001,13 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5426,10 +6022,8 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -5485,16 +6079,61 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5532,12 +6171,6 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -5696,6 +6329,11 @@ REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5774,6 +6412,13 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5788,10 +6433,8 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -5847,16 +6490,61 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -5894,12 +6582,6 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -6058,6 +6740,11 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6136,6 +6823,13 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6150,10 +6844,8 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -6209,16 +6901,61 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6256,12 +6993,6 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -6420,6 +7151,11 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6498,6 +7234,13 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6512,10 +7255,8 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -6571,16 +7312,61 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6618,12 +7404,6 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -6782,6 +7562,11 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6860,6 +7645,13 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6874,10 +7666,8 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -6933,16 +7723,61 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -6980,12 +7815,6 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -7144,6 +7973,11 @@ REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7222,6 +8056,13 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7236,10 +8077,8 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -7295,16 +8134,61 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7342,12 +8226,6 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -7506,6 +8384,11 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7584,6 +8467,13 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7598,10 +8488,8 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -7657,16 +8545,61 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7704,12 +8637,6 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -7868,6 +8795,11 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7946,6 +8878,13 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -7960,10 +8899,8 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -8019,16 +8956,61 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8066,12 +9048,6 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -8230,6 +9206,11 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8308,6 +9289,13 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8322,10 +9310,8 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -8381,16 +9367,61 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8428,12 +9459,6 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -8592,6 +9617,11 @@ REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8670,6 +9700,13 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8684,10 +9721,8 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -8743,16 +9778,61 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -8790,12 +9870,6 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -8954,6 +10028,11 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9032,6 +10111,13 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9046,10 +10132,8 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -9105,16 +10189,61 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9152,12 +10281,6 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -9316,6 +10439,11 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9394,6 +10522,13 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9408,10 +10543,8 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -9467,16 +10600,61 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9514,12 +10692,6 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -9678,6 +10850,11 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9756,6 +10933,13 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET , 62 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9770,10 +10954,8 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53 , SH_UN SH_FLD_SCOPE_MODE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SCOPE_MODE_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN , 55 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_BANK_PDWN_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BIST_PIPE_DATA_SHIFT ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DIG_PDWN ); @@ -9829,16 +11011,61 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN , 7 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_E_CTLE_COARSE ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -9876,12 +11103,6 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_HALFRATE_MODE ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_B_OFFSET_E0 ); @@ -10040,6 +11261,11 @@ REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10430,10 +11656,6 @@ REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_EDGE_OFFSET_CAL , 57 , SH REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_OFFSET_CAL , 58 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL ); -REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_QUAD_SEL ); -REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_QUAD_SEL_LEN ); REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC , 50 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IREF_RES_DAC ); REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10588,6 +11810,19 @@ REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH , 58 , SH_UN REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN , 6 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_BIST_EYE_B_WIDTH_LEN ); +REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_0 , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_1 , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10611,6 +11846,75 @@ REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN , 4 , SH_UN REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN , 60 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CTL_CLKDIST_PDWN ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL , 56 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN , 8 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN , 11 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_SATURATED_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL , 60 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL , 61 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL , 62 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_TIMER_SATURATED_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_IREF_PARITY_CHK_RO_SIGNAL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_IREF_PARITY_CHK_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_IREF_PARITY_CHK_RO_SIGNAL_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_IREF_PARITY_CHK_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PRVCPT_CHANGE_DET_RO_SIGNAL ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN , 9 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERR_INJ ); REG64_FLD( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN , 15 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10621,6 +11925,35 @@ REG64_FLD( OBUS_RX0_RX_FIR1_MASK_PG_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX0_RX_FIR1_MASK_PG_ERRS_LEN , 15 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL , 52 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL , 53 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL , 54 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL , 55 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL , 56 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL , 57 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL , 58 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL , 59 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL , 60 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL , 62 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERR_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CNT_SINGLE_LANE_RECAL ); REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR , 50 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10635,6 +11968,15 @@ REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE , 51 , SH_UN REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN , 5 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_MANUAL_RECAL_LANE_LEN ); +REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS , 62 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10657,6 +11999,43 @@ REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN , 12 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_CNT_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_CNT_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISGT_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISLT_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISEQ_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN , 9 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INT_REQ_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN , 16 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INT_REQ_RO_SIGNAL_LEN ); + +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN ); +REG64_FLD( OBUS_RX0_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL , 55 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_MANUAL_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_RX_ID1_PG_BUS_ID , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_BUS_ID ); REG64_FLD( OBUS_RX0_RX_ID1_PG_BUS_ID_LEN , 6 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10690,6 +12069,15 @@ REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10701,6 +12089,15 @@ REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -10759,6 +12156,15 @@ REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10770,6 +12176,15 @@ REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -10828,6 +12243,15 @@ REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10839,6 +12263,15 @@ REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -10897,6 +12330,15 @@ REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10908,6 +12350,15 @@ REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -10966,6 +12417,15 @@ REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -10977,6 +12437,15 @@ REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11035,6 +12504,15 @@ REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11046,6 +12524,15 @@ REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11104,6 +12591,15 @@ REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11115,6 +12611,15 @@ REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11173,6 +12678,15 @@ REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11184,6 +12698,15 @@ REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11242,6 +12765,15 @@ REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11253,6 +12785,15 @@ REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11311,6 +12852,15 @@ REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11322,6 +12872,15 @@ REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11380,6 +12939,15 @@ REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11391,6 +12959,15 @@ REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11449,6 +13026,15 @@ REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11460,6 +13046,15 @@ REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11518,6 +13113,15 @@ REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11529,6 +13133,15 @@ REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11587,6 +13200,15 @@ REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11598,6 +13220,15 @@ REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11656,6 +13287,15 @@ REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11667,6 +13307,15 @@ REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11725,6 +13374,15 @@ REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11736,6 +13394,15 @@ REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11794,6 +13461,15 @@ REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11805,6 +13481,15 @@ REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11863,6 +13548,15 @@ REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11874,6 +13568,15 @@ REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -11932,6 +13635,15 @@ REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -11943,6 +13655,15 @@ REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -12001,6 +13722,15 @@ REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12012,6 +13742,15 @@ REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -12070,6 +13809,15 @@ REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12081,6 +13829,15 @@ REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -12139,6 +13896,15 @@ REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12150,6 +13916,15 @@ REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -12208,6 +13983,15 @@ REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12219,6 +14003,15 @@ REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -12277,6 +14070,15 @@ REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUN_LANE ); REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12288,6 +14090,15 @@ REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT , 51 , SH_UN REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED , 52 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_DISABLED ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_INIT_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_DCCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_LANE_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_RECAL_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_CNTL1_O_PL_REGS_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_REGS_IORESET ); @@ -12339,6 +14150,11 @@ REG64_FLD( OBUS_RX_FIR_MASK_PB_ERRS , 48 , SH_UN REG64_FLD( OBUS_RX_FIR_MASK_PB_ERRS_LEN , 10 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( OBUS_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( OBUS_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL_LEN , 10 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_RX_FIR_RESET_PB_CLR_PAR_ERRS , 62 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( OBUS_RX_FIR_RESET_PB_RESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12610,10 +14426,14 @@ REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_OBUS , SH_ACS_SCOM , +REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_OBUS , SH_ACS_SCOM , +REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12622,6 +14442,10 @@ REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); @@ -12770,6 +14594,13 @@ REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UN REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( OBUS_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( OBUS_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( OBUS_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12903,8 +14734,6 @@ REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCES REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); -REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -12940,8 +14769,28 @@ REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_OBUS , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -13033,6 +14882,14 @@ REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_U SH_FLD_MATCH_NOT_MODE ); REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); @@ -13049,6 +14906,13 @@ REG64_FLD( OBUS_TCOB0_XTRA_TRACE_MODE_DATA , 0 , SH_UN REG64_FLD( OBUS_TCOB0_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_DATA_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13061,6 +14925,9 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13105,6 +14972,15 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13118,6 +14994,9 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13162,6 +15041,15 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13175,6 +15063,9 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13219,6 +15110,15 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13232,6 +15132,9 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13276,6 +15179,15 @@ REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13289,6 +15201,9 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13333,6 +15248,15 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13346,6 +15270,9 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13390,6 +15317,15 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13403,6 +15339,9 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13447,6 +15386,15 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13460,6 +15408,9 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13504,6 +15455,15 @@ REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13517,6 +15477,9 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13561,6 +15524,15 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13574,6 +15546,9 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13618,6 +15593,15 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13631,6 +15615,9 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13675,6 +15662,15 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13688,6 +15684,9 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13732,6 +15731,15 @@ REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13745,6 +15753,9 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13789,6 +15800,15 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13802,6 +15822,9 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13846,6 +15869,15 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13859,6 +15891,9 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13903,6 +15938,15 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13916,6 +15960,9 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -13960,6 +16007,15 @@ REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -13973,6 +16029,9 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14017,6 +16076,15 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14030,6 +16098,9 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14074,6 +16145,15 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14087,6 +16167,9 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14131,6 +16214,15 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14144,6 +16236,9 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14188,6 +16283,15 @@ REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14201,6 +16305,9 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14245,6 +16352,15 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14258,6 +16374,9 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14302,6 +16421,15 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14315,6 +16443,9 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14359,6 +16490,15 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); + +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL_IORESET , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_IORESET ); @@ -14372,6 +16512,9 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_UN REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14416,6 +16559,8 @@ REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN , 51 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PSEG_PRE_EN ); @@ -14516,6 +16661,9 @@ REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6 , 54 , SH_UN REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7 , 55 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CTL_SM_7 ); +REG64_FLD( OBUS_TX0_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_BIST_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_TDR_PULSE_WIDTH ); REG64_FLD( OBUS_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN , 8 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14589,6 +16737,19 @@ REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_ERRS_LEN , 5 , SH_UN REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_PL_ERR , 63 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_PL_ERR ); +REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL , 48 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL ); +REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL ); +REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL ); +REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL ); +REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL , 52 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL ); +REG64_FLD( OBUS_TX0_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL , 63 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERR_RO_SIGNAL ); + REG64_FLD( OBUS_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS , 62 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( OBUS_TX0_TX_FIR_RESET_PG_RESET , 63 , SH_UNT_OBUS , SH_ACS_SCOM , @@ -14620,11 +16781,39 @@ REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_8_9 , 56 , SH_UN REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_8_9_LEN , 2 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_8_9_LEN ); +REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_TEST_STATUS_RO_SIGNAL , 54 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_TEST_STATUS_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL2_PB_TX_ZCAL_TEST_DONE_RO_SIGNAL , 55 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_TEST_DONE_RO_SIGNAL ); + REG64_FLD( OBUS_TX_IMPCAL_NVAL_PB_ZCAL_N , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ZCAL_N ); REG64_FLD( OBUS_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN , 9 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ZCAL_N_LEN ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_DONE_RO_SIGNAL , 50 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_DONE_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_ERROR_RO_SIGNAL , 51 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_ERROR_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_BUSY_RO_SIGNAL , 52 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_BUSY_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_CMP_OUT_RO_SIGNAL , 54 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_CMP_OUT_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL , 55 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL ); +REG64_FLD( OBUS_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN , 9 , SH_UNT_OBUS , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN ); + REG64_FLD( OBUS_TX_IMPCAL_PVAL_PB_ZCAL_P , 48 , SH_UNT_OBUS , SH_ACS_SCOM , SH_FLD_ZCAL_P ); REG64_FLD( OBUS_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN , 9 , SH_UNT_OBUS , SH_ACS_SCOM , diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses.H index b01344a2..3ce196ba 100644 --- a/src/import/chips/p9/common/include/p9_perv_scom_addresses.H +++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses.H @@ -429,32 +429,37 @@ REG64( PERV_BIT_SEL_REG_2 , RULL(0x000F0008 REG64( PERV_PIB_BIT_SEL_REG_2 , RULL(0x000F0008), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_CBS_CS_FSI , RULL(0x00002801), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_CBS_CS_FSI_BYTE , RULL(0x00002804), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_CBS_CS_FSI_BYTE , RULL(0x00002804), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_CBS_CS_SCOM , RULL(0x00050001), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_CBS_CS , RULL(0x00050001), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_CBS_EL_FSI , RULL(0x00002803), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_CBS_EL_FSI_BYTE , RULL(0x0000280C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_CBS_EL_FSI_BYTE , RULL(0x0000280C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_CBS_EL_SCOM , RULL(0x00050003), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_CBS_EL , RULL(0x00050003), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_CBS_EL_HIST_FSI , RULL(0x00002806), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_CBS_EL_HIST_FSI_BYTE , RULL(0x00002818), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_CBS_EL_HIST_FSI_BYTE , RULL(0x00002818), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_CBS_EL_HIST_SCOM , RULL(0x00050006), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_CBS_EL_HIST , RULL(0x00050006), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_CBS_ENVSTAT_FSI , RULL(0x00002804), SH_UNT_PERV , SH_ACS_FSI ); +REG32( PERV_CBS_ENVSTAT_FSI_BYTE , RULL(0x00002810), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_CBS_ENVSTAT_SCOM , RULL(0x00050004), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_CBS_ENVSTAT , RULL(0x00050004), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_CBS_STAT_FSI , RULL(0x0000280B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_CBS_STAT_FSI_BYTE , RULL(0x0000282C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_CBS_STAT_FSI_BYTE , RULL(0x0000282C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_CBS_STAT_SCOM , RULL(0x0005000B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_CBS_STAT , RULL(0x0005000B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_CBS_TR_FSI , RULL(0x00002802), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_CBS_TR_FSI_BYTE , RULL(0x00002808), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_CBS_TR_FSI_BYTE , RULL(0x00002808), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_CBS_TR_SCOM , RULL(0x00050002), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_CBS_TR , RULL(0x00050002), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_CBS_TR_HIST_FSI , RULL(0x00002805), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_CBS_TR_HIST_FSI_BYTE , RULL(0x00002814), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_CBS_TR_HIST_FSI_BYTE , RULL(0x00002814), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_CBS_TR_HIST_SCOM , RULL(0x00050005), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_CBS_TR_HIST , RULL(0x00050005), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -3151,12 +3156,12 @@ REG32( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI_BYTE , RULL(0x00000C68 SH_ACS_FSI_BYTE ); REG32( PERV_DOORBELL_STATUS_CONTROL_1A_FSI , RULL(0x00002824), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_DOORBELL_STATUS_CONTROL_1A_FSI_BYTE , RULL(0x00002890), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_DOORBELL_STATUS_CONTROL_1A_FSI_BYTE , RULL(0x00002890), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_DOORBELL_STATUS_CONTROL_1A_SCOM , RULL(0x00050020), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_DOORBELL_STATUS_CONTROL_1A , RULL(0x00050020), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_DOORBELL_STATUS_CONTROL_2A_FSI , RULL(0x0000282C), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_DOORBELL_STATUS_CONTROL_2A_FSI_BYTE , RULL(0x000028B0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_DOORBELL_STATUS_CONTROL_2A_FSI_BYTE , RULL(0x000028B0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_DOORBELL_STATUS_CONTROL_2A_SCOM , RULL(0x00050028), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_DOORBELL_STATUS_CONTROL_2A , RULL(0x00050028), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -3250,6 +3255,51 @@ REG64( PERV_EC21_DTS_TRC_RESULT , RULL(0x35050003 REG64( PERV_EC22_DTS_TRC_RESULT , RULL(0x36050003), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); REG64( PERV_EC23_DTS_TRC_RESULT , RULL(0x37050003), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); +REG64( PERV_EDRAM_STATUS , RULL(0x000F0029), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_TP_EDRAM_STATUS , RULL(0x010F0029), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_EDRAM_STATUS , RULL(0x020F0029), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_EDRAM_STATUS , RULL(0x030F0029), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_EDRAM_STATUS , RULL(0x040F0029), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_EDRAM_STATUS , RULL(0x050F0029), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_EDRAM_STATUS , RULL(0x060F0029), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_EDRAM_STATUS , RULL(0x070F0029), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_EDRAM_STATUS , RULL(0x080F0029), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_EDRAM_STATUS , RULL(0x090F0029), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_EDRAM_STATUS , RULL(0x0C0F0029), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_EDRAM_STATUS , RULL(0x0D0F0029), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_EDRAM_STATUS , RULL(0x0E0F0029), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_EDRAM_STATUS , RULL(0x0F0F0029), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_EDRAM_STATUS , RULL(0x100F0029), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_EDRAM_STATUS , RULL(0x110F0029), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_EDRAM_STATUS , RULL(0x120F0029), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_EDRAM_STATUS , RULL(0x130F0029), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_EDRAM_STATUS , RULL(0x140F0029), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_EDRAM_STATUS , RULL(0x150F0029), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_EDRAM_STATUS , RULL(0x200F0029), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_EDRAM_STATUS , RULL(0x210F0029), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_EDRAM_STATUS , RULL(0x220F0029), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_EDRAM_STATUS , RULL(0x230F0029), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_EDRAM_STATUS , RULL(0x240F0029), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_EDRAM_STATUS , RULL(0x250F0029), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_EDRAM_STATUS , RULL(0x260F0029), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_EDRAM_STATUS , RULL(0x270F0029), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_EDRAM_STATUS , RULL(0x280F0029), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_EDRAM_STATUS , RULL(0x290F0029), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_EDRAM_STATUS , RULL(0x2A0F0029), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_EDRAM_STATUS , RULL(0x2B0F0029), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_EDRAM_STATUS , RULL(0x2C0F0029), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_EDRAM_STATUS , RULL(0x2D0F0029), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_EDRAM_STATUS , RULL(0x2E0F0029), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_EDRAM_STATUS , RULL(0x2F0F0029), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_EDRAM_STATUS , RULL(0x300F0029), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_EDRAM_STATUS , RULL(0x310F0029), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_EDRAM_STATUS , RULL(0x320F0029), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_EDRAM_STATUS , RULL(0x330F0029), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_EDRAM_STATUS , RULL(0x340F0029), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_EDRAM_STATUS , RULL(0x350F0029), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_EDRAM_STATUS , RULL(0x360F0029), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_EDRAM_STATUS , RULL(0x370F0029), SH_UNT_PERV_55 , SH_ACS_SCOM ); + REG64( PERV_ERROR_REG , RULL(0x000F001F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ERROR_REG , RULL(0x000F001F), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG64( PERV_TP_ERROR_REG , RULL(0x010F001F), SH_UNT_PERV_1 , SH_ACS_SCOM ); @@ -3487,27 +3537,30 @@ REG32( PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI_BYTE , RULL(0x00000C08 SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI , RULL(0x00002410), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI_BYTE , RULL(0x00002440), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI_BYTE , RULL(0x00002440), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI , RULL(0x00002415), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI_BYTE , RULL(0x00002454), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI_BYTE , RULL(0x00002454), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); + +REG32( PERV_FSB_FSB_DOWNFIFO_MTC_FSI , RULL(0x00002416), SH_UNT_PERV_FSB , SH_ACS_FSI ); +REG32( PERV_FSB_FSB_DOWNFIFO_MTC_FSI_BYTE , RULL(0x00002458), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_DOWNFIFO_RESET_FSI , RULL(0x00002414), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_DOWNFIFO_RESET_FSI_BYTE , RULL(0x00002450), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_DOWNFIFO_RESET_FSI_BYTE , RULL(0x00002450), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI , RULL(0x00002411), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI_BYTE , RULL(0x00002444), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI_BYTE , RULL(0x00002444), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_UPFIFO_DATA_IN_FSI , RULL(0x00002400), SH_UNT_PERV_FSB , SH_ACS_FSI ); REG32( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI , RULL(0x00002403), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI_BYTE , RULL(0x0000240C), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI_BYTE , RULL(0x0000240C), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI , RULL(0x00002402), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI_BYTE , RULL(0x00002408), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI_BYTE , RULL(0x00002408), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSB_FSB_UPFIFO_STATUS_FSI , RULL(0x00002401), SH_UNT_PERV_FSB , SH_ACS_FSI ); -REG64( PERV_FSB_FSB_UPFIFO_STATUS_FSI_BYTE , RULL(0x00002404), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); +REG32( PERV_FSB_FSB_UPFIFO_STATUS_FSI_BYTE , RULL(0x00002404), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ); REG32( PERV_FSISCRPD1_FSI , RULL(0x00001401), SH_UNT_PERV , SH_ACS_FSI ); REG32( PERV_FSISCRPD1_FSI_BYTE , RULL(0x00001404), SH_UNT_PERV , SH_ACS_FSI_BYTE ); @@ -4380,7 +4433,7 @@ REG32( PERV_FSI_B_SSTAT_FSI1 , RULL(0x00000814 SH_ACS_FSI1 ); //WARNING - VALUE SET SAME AS ANOTHER REG REG32( PERV_GPWRP_FSI , RULL(0x0000281F), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_GPWRP_FSI_BYTE , RULL(0x0000287C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_GPWRP_FSI_BYTE , RULL(0x0000287C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_GPWRP_SCOM , RULL(0x0005001F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_GPWRP , RULL(0x0005001F), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -5664,357 +5717,357 @@ REG64( PERV_PIB2OPB1_LSTAT , RULL(0x00020012 SH_ACS_SCOM_RO ); REG32( PERV_M1A_DATA_AREA_0_FSI , RULL(0x00002840), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_0_FSI_BYTE , RULL(0x00002900), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_0_FSI_BYTE , RULL(0x00002900), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_0_SCOM , RULL(0x00050040), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_0 , RULL(0x00050040), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_1_FSI , RULL(0x00002841), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_1_FSI_BYTE , RULL(0x00002904), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_1_FSI_BYTE , RULL(0x00002904), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_1_SCOM , RULL(0x00050041), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_1 , RULL(0x00050041), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_10_FSI , RULL(0x0000284A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_10_FSI_BYTE , RULL(0x00002928), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_10_FSI_BYTE , RULL(0x00002928), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_10_SCOM , RULL(0x0005004A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_10 , RULL(0x0005004A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_11_FSI , RULL(0x0000284B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_11_FSI_BYTE , RULL(0x0000292C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_11_FSI_BYTE , RULL(0x0000292C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_11_SCOM , RULL(0x0005004B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_11 , RULL(0x0005004B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_12_FSI , RULL(0x0000284C), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_12_FSI_BYTE , RULL(0x00002930), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_12_FSI_BYTE , RULL(0x00002930), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_12_SCOM , RULL(0x0005004C), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_12 , RULL(0x0005004C), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_13_FSI , RULL(0x0000284D), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_13_FSI_BYTE , RULL(0x00002934), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_13_FSI_BYTE , RULL(0x00002934), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_13_SCOM , RULL(0x0005004D), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_13 , RULL(0x0005004D), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_14_FSI , RULL(0x0000284E), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_14_FSI_BYTE , RULL(0x00002938), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_14_FSI_BYTE , RULL(0x00002938), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_14_SCOM , RULL(0x0005004E), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_14 , RULL(0x0005004E), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_15_FSI , RULL(0x0000284F), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_15_FSI_BYTE , RULL(0x0000293C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_15_FSI_BYTE , RULL(0x0000293C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_15_SCOM , RULL(0x0005004F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_15 , RULL(0x0005004F), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_2_FSI , RULL(0x00002842), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_2_FSI_BYTE , RULL(0x00002908), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_2_FSI_BYTE , RULL(0x00002908), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_2_SCOM , RULL(0x00050042), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_2 , RULL(0x00050042), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_3_FSI , RULL(0x00002843), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_3_FSI_BYTE , RULL(0x0000290C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_3_FSI_BYTE , RULL(0x0000290C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_3_SCOM , RULL(0x00050043), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_3 , RULL(0x00050043), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_4_FSI , RULL(0x00002844), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_4_FSI_BYTE , RULL(0x00002910), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_4_FSI_BYTE , RULL(0x00002910), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_4_SCOM , RULL(0x00050044), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_4 , RULL(0x00050044), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_5_FSI , RULL(0x00002845), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_5_FSI_BYTE , RULL(0x00002914), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_5_FSI_BYTE , RULL(0x00002914), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_5_SCOM , RULL(0x00050045), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_5 , RULL(0x00050045), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_6_FSI , RULL(0x00002846), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_6_FSI_BYTE , RULL(0x00002918), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_6_FSI_BYTE , RULL(0x00002918), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_6_SCOM , RULL(0x00050046), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_6 , RULL(0x00050046), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_7_FSI , RULL(0x00002847), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_7_FSI_BYTE , RULL(0x0000291C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_7_FSI_BYTE , RULL(0x0000291C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_7_SCOM , RULL(0x00050047), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_7 , RULL(0x00050047), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_8_FSI , RULL(0x00002848), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_8_FSI_BYTE , RULL(0x00002920), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_8_FSI_BYTE , RULL(0x00002920), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_8_SCOM , RULL(0x00050048), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_8 , RULL(0x00050048), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1A_DATA_AREA_9_FSI , RULL(0x00002849), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1A_DATA_AREA_9_FSI_BYTE , RULL(0x00002924), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1A_DATA_AREA_9_FSI_BYTE , RULL(0x00002924), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1A_DATA_AREA_9_SCOM , RULL(0x00050049), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1A_DATA_AREA_9 , RULL(0x00050049), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_0_FSI , RULL(0x00002880), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_0_FSI_BYTE , RULL(0x00002A00), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_0_FSI_BYTE , RULL(0x00002A00), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_0_SCOM , RULL(0x00050080), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_0 , RULL(0x00050080), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_1_FSI , RULL(0x00002881), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_1_FSI_BYTE , RULL(0x00002A04), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_1_FSI_BYTE , RULL(0x00002A04), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_1_SCOM , RULL(0x00050081), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_1 , RULL(0x00050081), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_10_FSI , RULL(0x0000288A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_10_FSI_BYTE , RULL(0x00002A28), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_10_FSI_BYTE , RULL(0x00002A28), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_10_SCOM , RULL(0x0005008A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_10 , RULL(0x0005008A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_11_FSI , RULL(0x0000288B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_11_FSI_BYTE , RULL(0x00002A2C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_11_FSI_BYTE , RULL(0x00002A2C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_11_SCOM , RULL(0x0005008B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_11 , RULL(0x0005008B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_12_FSI , RULL(0x0000288C), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_12_FSI_BYTE , RULL(0x00002A30), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_12_FSI_BYTE , RULL(0x00002A30), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_12_SCOM , RULL(0x0005008C), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_12 , RULL(0x0005008C), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_13_FSI , RULL(0x0000288D), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_13_FSI_BYTE , RULL(0x00002A34), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_13_FSI_BYTE , RULL(0x00002A34), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_13_SCOM , RULL(0x0005008D), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_13 , RULL(0x0005008D), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_14_FSI , RULL(0x0000288E), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_14_FSI_BYTE , RULL(0x00002A38), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_14_FSI_BYTE , RULL(0x00002A38), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_14_SCOM , RULL(0x0005008E), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_14 , RULL(0x0005008E), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_15_FSI , RULL(0x0000288F), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_15_FSI_BYTE , RULL(0x00002A3C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_15_FSI_BYTE , RULL(0x00002A3C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_15_SCOM , RULL(0x0005008F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_15 , RULL(0x0005008F), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_2_FSI , RULL(0x00002882), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_2_FSI_BYTE , RULL(0x00002A08), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_2_FSI_BYTE , RULL(0x00002A08), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_2_SCOM , RULL(0x00050082), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_2 , RULL(0x00050082), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_3_FSI , RULL(0x00002883), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_3_FSI_BYTE , RULL(0x00002A0C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_3_FSI_BYTE , RULL(0x00002A0C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_3_SCOM , RULL(0x00050083), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_3 , RULL(0x00050083), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_4_FSI , RULL(0x00002884), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_4_FSI_BYTE , RULL(0x00002A10), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_4_FSI_BYTE , RULL(0x00002A10), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_4_SCOM , RULL(0x00050084), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_4 , RULL(0x00050084), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_5_FSI , RULL(0x00002885), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_5_FSI_BYTE , RULL(0x00002A14), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_5_FSI_BYTE , RULL(0x00002A14), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_5_SCOM , RULL(0x00050085), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_5 , RULL(0x00050085), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_6_FSI , RULL(0x00002886), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_6_FSI_BYTE , RULL(0x00002A18), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_6_FSI_BYTE , RULL(0x00002A18), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_6_SCOM , RULL(0x00050086), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_6 , RULL(0x00050086), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_7_FSI , RULL(0x00002887), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_7_FSI_BYTE , RULL(0x00002A1C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_7_FSI_BYTE , RULL(0x00002A1C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_7_SCOM , RULL(0x00050087), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_7 , RULL(0x00050087), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_8_FSI , RULL(0x00002888), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_8_FSI_BYTE , RULL(0x00002A20), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_8_FSI_BYTE , RULL(0x00002A20), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_8_SCOM , RULL(0x00050088), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_8 , RULL(0x00050088), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M1B_DATA_AREA_9_FSI , RULL(0x00002889), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M1B_DATA_AREA_9_FSI_BYTE , RULL(0x00002A24), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M1B_DATA_AREA_9_FSI_BYTE , RULL(0x00002A24), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M1B_DATA_AREA_9_SCOM , RULL(0x00050089), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M1B_DATA_AREA_9 , RULL(0x00050089), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_0_FSI , RULL(0x000028C0), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_0_FSI_BYTE , RULL(0x00002B00), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_0_FSI_BYTE , RULL(0x00002B00), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_0_SCOM , RULL(0x000500C0), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_0 , RULL(0x000500C0), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_1_FSI , RULL(0x000028C1), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_1_FSI_BYTE , RULL(0x00002B04), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_1_FSI_BYTE , RULL(0x00002B04), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_1_SCOM , RULL(0x000500C1), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_1 , RULL(0x000500C1), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_10_FSI , RULL(0x000028CA), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_10_FSI_BYTE , RULL(0x00002B28), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_10_FSI_BYTE , RULL(0x00002B28), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_10_SCOM , RULL(0x000500CA), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_10 , RULL(0x000500CA), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_11_FSI , RULL(0x000028CB), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_11_FSI_BYTE , RULL(0x00002B2C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_11_FSI_BYTE , RULL(0x00002B2C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_11_SCOM , RULL(0x000500CB), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_11 , RULL(0x000500CB), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_12_FSI , RULL(0x000028CC), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_12_FSI_BYTE , RULL(0x00002B30), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_12_FSI_BYTE , RULL(0x00002B30), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_12_SCOM , RULL(0x000500CC), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_12 , RULL(0x000500CC), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_13_FSI , RULL(0x000028CD), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_13_FSI_BYTE , RULL(0x00002B34), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_13_FSI_BYTE , RULL(0x00002B34), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_13_SCOM , RULL(0x000500CD), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_13 , RULL(0x000500CD), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_14_FSI , RULL(0x000028CE), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_14_FSI_BYTE , RULL(0x00002B38), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_14_FSI_BYTE , RULL(0x00002B38), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_14_SCOM , RULL(0x000500CE), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_14 , RULL(0x000500CE), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_15_FSI , RULL(0x000028CF), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_15_FSI_BYTE , RULL(0x00002B3C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_15_FSI_BYTE , RULL(0x00002B3C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_15_SCOM , RULL(0x000500CF), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_15 , RULL(0x000500CF), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_2_FSI , RULL(0x000028C2), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_2_FSI_BYTE , RULL(0x00002B08), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_2_FSI_BYTE , RULL(0x00002B08), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_2_SCOM , RULL(0x000500C2), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_2 , RULL(0x000500C2), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_3_FSI , RULL(0x000028C3), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_3_FSI_BYTE , RULL(0x00002B0C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_3_FSI_BYTE , RULL(0x00002B0C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_3_SCOM , RULL(0x000500C3), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_3 , RULL(0x000500C3), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_4_FSI , RULL(0x000028C4), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_4_FSI_BYTE , RULL(0x00002B10), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_4_FSI_BYTE , RULL(0x00002B10), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_4_SCOM , RULL(0x000500C4), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_4 , RULL(0x000500C4), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_5_FSI , RULL(0x000028C5), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_5_FSI_BYTE , RULL(0x00002B14), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_5_FSI_BYTE , RULL(0x00002B14), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_5_SCOM , RULL(0x000500C5), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_5 , RULL(0x000500C5), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_6_FSI , RULL(0x000028C6), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_6_FSI_BYTE , RULL(0x00002B18), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_6_FSI_BYTE , RULL(0x00002B18), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_6_SCOM , RULL(0x000500C6), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_6 , RULL(0x000500C6), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_7_FSI , RULL(0x000028C7), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_7_FSI_BYTE , RULL(0x00002B1C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_7_FSI_BYTE , RULL(0x00002B1C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_7_SCOM , RULL(0x000500C7), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_7 , RULL(0x000500C7), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_8_FSI , RULL(0x000028C8), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_8_FSI_BYTE , RULL(0x00002B20), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_8_FSI_BYTE , RULL(0x00002B20), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_8_SCOM , RULL(0x000500C8), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_8 , RULL(0x000500C8), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2A_DATA_AREA_9_FSI , RULL(0x000028C9), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2A_DATA_AREA_9_FSI_BYTE , RULL(0x00002B24), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2A_DATA_AREA_9_FSI_BYTE , RULL(0x00002B24), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2A_DATA_AREA_9_SCOM , RULL(0x000500C9), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2A_DATA_AREA_9 , RULL(0x000500C9), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_0_FSI , RULL(0x00002900), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_0_FSI_BYTE , RULL(0x00002C00), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_0_FSI_BYTE , RULL(0x00002C00), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_0_SCOM , RULL(0x00050100), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_0 , RULL(0x00050100), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_1_FSI , RULL(0x00002901), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_1_FSI_BYTE , RULL(0x00002C04), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_1_FSI_BYTE , RULL(0x00002C04), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_1_SCOM , RULL(0x00050101), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_1 , RULL(0x00050101), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_10_FSI , RULL(0x0000290A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_10_FSI_BYTE , RULL(0x00002C28), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_10_FSI_BYTE , RULL(0x00002C28), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_10_SCOM , RULL(0x0005010A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_10 , RULL(0x0005010A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_11_FSI , RULL(0x0000290B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_11_FSI_BYTE , RULL(0x00002C2C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_11_FSI_BYTE , RULL(0x00002C2C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_11_SCOM , RULL(0x0005010B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_11 , RULL(0x0005010B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_12_FSI , RULL(0x0000290C), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_12_FSI_BYTE , RULL(0x00002C30), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_12_FSI_BYTE , RULL(0x00002C30), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_12_SCOM , RULL(0x0005010C), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_12 , RULL(0x0005010C), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_13_FSI , RULL(0x0000290D), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_13_FSI_BYTE , RULL(0x00002C34), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_13_FSI_BYTE , RULL(0x00002C34), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_13_SCOM , RULL(0x0005010D), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_13 , RULL(0x0005010D), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_14_FSI , RULL(0x0000290E), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_14_FSI_BYTE , RULL(0x00002C38), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_14_FSI_BYTE , RULL(0x00002C38), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_14_SCOM , RULL(0x0005010E), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_14 , RULL(0x0005010E), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_15_FSI , RULL(0x0000290F), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_15_FSI_BYTE , RULL(0x00002C3C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_15_FSI_BYTE , RULL(0x00002C3C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_15_SCOM , RULL(0x0005010F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_15 , RULL(0x0005010F), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_2_FSI , RULL(0x00002902), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_2_FSI_BYTE , RULL(0x00002C08), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_2_FSI_BYTE , RULL(0x00002C08), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_2_SCOM , RULL(0x00050102), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_2 , RULL(0x00050102), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_3_FSI , RULL(0x00002903), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_3_FSI_BYTE , RULL(0x00002C0C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_3_FSI_BYTE , RULL(0x00002C0C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_3_SCOM , RULL(0x00050103), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_3 , RULL(0x00050103), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_4_FSI , RULL(0x00002904), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_4_FSI_BYTE , RULL(0x00002C10), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_4_FSI_BYTE , RULL(0x00002C10), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_4_SCOM , RULL(0x00050104), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_4 , RULL(0x00050104), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_5_FSI , RULL(0x00002905), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_5_FSI_BYTE , RULL(0x00002C14), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_5_FSI_BYTE , RULL(0x00002C14), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_5_SCOM , RULL(0x00050105), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_5 , RULL(0x00050105), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_6_FSI , RULL(0x00002906), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_6_FSI_BYTE , RULL(0x00002C18), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_6_FSI_BYTE , RULL(0x00002C18), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_6_SCOM , RULL(0x00050106), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_6 , RULL(0x00050106), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_7_FSI , RULL(0x00002907), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_7_FSI_BYTE , RULL(0x00002C1C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_7_FSI_BYTE , RULL(0x00002C1C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_7_SCOM , RULL(0x00050107), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_7 , RULL(0x00050107), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_8_FSI , RULL(0x00002908), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_8_FSI_BYTE , RULL(0x00002C20), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_8_FSI_BYTE , RULL(0x00002C20), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_8_SCOM , RULL(0x00050108), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_8 , RULL(0x00050108), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_M2B_DATA_AREA_9_FSI , RULL(0x00002909), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_M2B_DATA_AREA_9_FSI_BYTE , RULL(0x00002C24), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_M2B_DATA_AREA_9_FSI_BYTE , RULL(0x00002C24), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_M2B_DATA_AREA_9_SCOM , RULL(0x00050109), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_M2B_DATA_AREA_9 , RULL(0x00050109), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI , RULL(0x00002821), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI_BYTE , RULL(0x00002884), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI_BYTE , RULL(0x00002884), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_A_SCOM , RULL(0x00050021), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_A , RULL(0x00050021), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI , RULL(0x00002825), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI_BYTE , RULL(0x00002894), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI_BYTE , RULL(0x00002894), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_B_SCOM , RULL(0x00050025), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_B , RULL(0x00050025), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI , RULL(0x00002822), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI_BYTE , RULL(0x00002888), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI_BYTE , RULL(0x00002888), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_A_SCOM , RULL(0x00050022), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_A , RULL(0x00050022), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI , RULL(0x00002826), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI_BYTE , RULL(0x00002898), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI_BYTE , RULL(0x00002898), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_B_SCOM , RULL(0x00050026), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_B , RULL(0x00050026), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI , RULL(0x00002823), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI_BYTE , RULL(0x0000288C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI_BYTE , RULL(0x0000288C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_A_SCOM , RULL(0x00050023), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_A , RULL(0x00050023), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI , RULL(0x00002827), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI_BYTE , RULL(0x0000289C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI_BYTE , RULL(0x0000289C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_B_SCOM , RULL(0x00050027), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_B , RULL(0x00050027), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); REG32( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI , RULL(0x00002833), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028CC), SH_UNT_PERV , +REG32( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028CC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM , RULL(0x00050033), SH_UNT_PERV , SH_ACS_SCOM_WOR ); REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM1 , RULL(0x00050034), SH_UNT_PERV , @@ -6025,60 +6078,60 @@ REG64( PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_CLEAR , RULL(0x00050 SH_ACS_SCOM1_CLEAR ); REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI , RULL(0x00002829), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI_BYTE , RULL(0x000028A4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI_BYTE , RULL(0x000028A4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_A_SCOM , RULL(0x00050029), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_A , RULL(0x00050029), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI , RULL(0x0000282D), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI_BYTE , RULL(0x000028B4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI_BYTE , RULL(0x000028B4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_B_SCOM , RULL(0x0005002D), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_B , RULL(0x0005002D), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI , RULL(0x0000282A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI_BYTE , RULL(0x000028A8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI_BYTE , RULL(0x000028A8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_A_SCOM , RULL(0x0005002A), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_A , RULL(0x0005002A), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI , RULL(0x0000282E), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI_BYTE , RULL(0x000028B8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI_BYTE , RULL(0x000028B8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_B_SCOM , RULL(0x0005002E), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_B , RULL(0x0005002E), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI , RULL(0x0000282B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI_BYTE , RULL(0x000028AC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI_BYTE , RULL(0x000028AC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_A_SCOM , RULL(0x0005002B), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_A , RULL(0x0005002B), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI , RULL(0x0000282F), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI_BYTE , RULL(0x000028BC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI_BYTE , RULL(0x000028BC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_B_SCOM , RULL(0x0005002F), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_B , RULL(0x0005002F), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI , RULL(0x00002831), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI_BYTE , RULL(0x000028C4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI_BYTE , RULL(0x000028C4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_SCOM , RULL(0x00050031), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS , RULL(0x00050031), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI , RULL(0x00002832), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI_BYTE , RULL(0x000028C8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI_BYTE , RULL(0x000028C8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_SCOM , RULL(0x00050032), SH_UNT_PERV , SH_ACS_SCOM_WCLEAR ); REG64( PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT , RULL(0x00050032), SH_UNT_PERV_0 , SH_ACS_SCOM_WCLEAR ); REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI , RULL(0x00002830), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI_BYTE , RULL(0x000028C0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI_BYTE , RULL(0x000028C0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_SCOM , RULL(0x00050030), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS , RULL(0x00050030), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI , RULL(0x00002835), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI_BYTE , RULL(0x000028D4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI_BYTE , RULL(0x000028D4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_SCOM , RULL(0x00050035), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT , RULL(0x00050035), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI , RULL(0x00002836), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI0 , RULL(0x00002837), SH_UNT_PERV , SH_ACS_FSI0 ); -REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028D8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028D8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_SCOM , RULL(0x00050036), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1 , RULL(0x00050036), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); @@ -7064,42 +7117,42 @@ REG32( PERV_PEEK4B4_FSI , RULL(0x000004B4 REG32( PERV_PEEK4B8_FSI , RULL(0x000004B8), SH_UNT_PERV , SH_ACS_FSI ); REG32( PERV_PERV_CTRL0_FSI , RULL(0x0000281A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL0_FSI_BYTE , RULL(0x00002868), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL0_FSI_BYTE , RULL(0x00002868), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL0_SCOM , RULL(0x0005001A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL0 , RULL(0x0005001A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL0_CLEAR_FSI , RULL(0x0000293A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL0_CLEAR_FSI_BYTE , RULL(0x00002CE8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL0_CLEAR_FSI_BYTE , RULL(0x00002CE8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL0_CLEAR_SCOM , RULL(0x0005013A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL0_CLEAR , RULL(0x0005013A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL0_COPY_FSI , RULL(0x0000291A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL0_COPY_FSI_BYTE , RULL(0x00002C68), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL0_COPY_FSI_BYTE , RULL(0x00002C68), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL0_COPY_SCOM , RULL(0x0005011A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL0_COPY , RULL(0x0005011A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL0_SET_FSI , RULL(0x0000292A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL0_SET_FSI_BYTE , RULL(0x00002CA8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL0_SET_FSI_BYTE , RULL(0x00002CA8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL0_SET_SCOM , RULL(0x0005012A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL0_SET , RULL(0x0005012A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL1_FSI , RULL(0x0000281B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL1_FSI_BYTE , RULL(0x0000286C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL1_FSI_BYTE , RULL(0x0000286C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL1_SCOM , RULL(0x0005001B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL1 , RULL(0x0005001B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL1_CLEAR_FSI , RULL(0x0000293B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL1_CLEAR_FSI_BYTE , RULL(0x00002CEC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL1_CLEAR_FSI_BYTE , RULL(0x00002CEC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL1_CLEAR_SCOM , RULL(0x0005013B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL1_CLEAR , RULL(0x0005013B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL1_COPY_FSI , RULL(0x0000291B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL1_COPY_FSI_BYTE , RULL(0x00002C6C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL1_COPY_FSI_BYTE , RULL(0x00002C6C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL1_COPY_SCOM , RULL(0x0005011B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL1_COPY , RULL(0x0005011B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_PERV_CTRL1_SET_FSI , RULL(0x0000292B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_PERV_CTRL1_SET_FSI_BYTE , RULL(0x00002CAC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_PERV_CTRL1_SET_FSI_BYTE , RULL(0x00002CAC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL1_SET_SCOM , RULL(0x0005012B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL1_SET , RULL(0x0005012B), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -8662,184 +8715,184 @@ REG64( PERV_RING_FENCE_MASK_LATCH_REG , RULL(0x00010008 REG64( PERV_TP_RING_FENCE_MASK_LATCH_REG , RULL(0x01010008), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL0_FSI , RULL(0x00002810), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL0_FSI_BYTE , RULL(0x00002840), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL0_FSI_BYTE , RULL(0x00002840), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL0_SCOM , RULL(0x00050010), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL0 , RULL(0x00050010), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL0_CLEAR_FSI , RULL(0x00002930), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL0_CLEAR_FSI_BYTE , RULL(0x00002CC0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL0_CLEAR_FSI_BYTE , RULL(0x00002CC0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL0_CLEAR_SCOM , RULL(0x00050130), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL0_CLEAR , RULL(0x00050130), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL0_COPY_FSI , RULL(0x00002910), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL0_COPY_FSI_BYTE , RULL(0x00002C40), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL0_COPY_FSI_BYTE , RULL(0x00002C40), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL0_COPY_SCOM , RULL(0x00050110), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL0_COPY , RULL(0x00050110), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL0_SET_FSI , RULL(0x00002920), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL0_SET_FSI_BYTE , RULL(0x00002C80), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL0_SET_FSI_BYTE , RULL(0x00002C80), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL0_SET_SCOM , RULL(0x00050120), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL0_SET , RULL(0x00050120), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL1_FSI , RULL(0x00002811), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL1_FSI_BYTE , RULL(0x00002844), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL1_FSI_BYTE , RULL(0x00002844), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL1_SCOM , RULL(0x00050011), SH_UNT_PERV , SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( PERV_PIB_ROOT_CTRL1 , RULL(0x00050011), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL1_CLEAR_FSI , RULL(0x00002931), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL1_CLEAR_FSI_BYTE , RULL(0x00002CC4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL1_CLEAR_FSI_BYTE , RULL(0x00002CC4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL1_CLEAR_SCOM , RULL(0x00050131), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL1_CLEAR , RULL(0x00050131), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL1_COPY_FSI , RULL(0x00002911), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL1_COPY_FSI_BYTE , RULL(0x00002C44), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL1_COPY_FSI_BYTE , RULL(0x00002C44), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL1_COPY_SCOM , RULL(0x00050111), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL1_COPY , RULL(0x00050111), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL1_SET_FSI , RULL(0x00002921), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL1_SET_FSI_BYTE , RULL(0x00002C84), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL1_SET_FSI_BYTE , RULL(0x00002C84), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL1_SET_SCOM , RULL(0x00050121), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL1_SET , RULL(0x00050121), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL2_FSI , RULL(0x00002812), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL2_FSI_BYTE , RULL(0x00002848), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL2_FSI_BYTE , RULL(0x00002848), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL2_SCOM , RULL(0x00050012), SH_UNT_PERV , SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( PERV_PIB_ROOT_CTRL2 , RULL(0x00050012), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL2_CLEAR_FSI , RULL(0x00002932), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL2_CLEAR_FSI_BYTE , RULL(0x00002CC8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL2_CLEAR_FSI_BYTE , RULL(0x00002CC8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL2_CLEAR_SCOM , RULL(0x00050132), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL2_CLEAR , RULL(0x00050132), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL2_COPY_FSI , RULL(0x00002912), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL2_COPY_FSI_BYTE , RULL(0x00002C48), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL2_COPY_FSI_BYTE , RULL(0x00002C48), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL2_COPY_SCOM , RULL(0x00050112), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL2_COPY , RULL(0x00050112), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL2_SET_FSI , RULL(0x00002922), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL2_SET_FSI_BYTE , RULL(0x00002C88), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL2_SET_FSI_BYTE , RULL(0x00002C88), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL2_SET_SCOM , RULL(0x00050122), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL2_SET , RULL(0x00050122), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL3_FSI , RULL(0x00002813), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL3_FSI_BYTE , RULL(0x0000284C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL3_FSI_BYTE , RULL(0x0000284C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL3_SCOM , RULL(0x00050013), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL3 , RULL(0x00050013), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL3_CLEAR_FSI , RULL(0x00002933), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL3_CLEAR_FSI_BYTE , RULL(0x00002CCC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL3_CLEAR_FSI_BYTE , RULL(0x00002CCC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL3_CLEAR_SCOM , RULL(0x00050133), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL3_CLEAR , RULL(0x00050133), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL3_COPY_FSI , RULL(0x00002913), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL3_COPY_FSI_BYTE , RULL(0x00002C4C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL3_COPY_FSI_BYTE , RULL(0x00002C4C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL3_COPY_SCOM , RULL(0x00050113), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL3_COPY , RULL(0x00050113), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL3_SET_FSI , RULL(0x00002923), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL3_SET_FSI_BYTE , RULL(0x00002C8C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL3_SET_FSI_BYTE , RULL(0x00002C8C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL3_SET_SCOM , RULL(0x00050123), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL3_SET , RULL(0x00050123), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL4_FSI , RULL(0x00002814), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL4_FSI_BYTE , RULL(0x00002850), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL4_FSI_BYTE , RULL(0x00002850), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL4_SCOM , RULL(0x00050014), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL4 , RULL(0x00050014), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL4_CLEAR_FSI , RULL(0x00002934), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL4_CLEAR_FSI_BYTE , RULL(0x00002CD0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL4_CLEAR_FSI_BYTE , RULL(0x00002CD0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL4_CLEAR_SCOM , RULL(0x00050134), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL4_CLEAR , RULL(0x00050134), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL4_COPY_FSI , RULL(0x00002914), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL4_COPY_FSI_BYTE , RULL(0x00002C50), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL4_COPY_FSI_BYTE , RULL(0x00002C50), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL4_COPY_SCOM , RULL(0x00050114), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL4_COPY , RULL(0x00050114), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL4_SET_FSI , RULL(0x00002924), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL4_SET_FSI_BYTE , RULL(0x00002C90), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL4_SET_FSI_BYTE , RULL(0x00002C90), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL4_SET_SCOM , RULL(0x00050124), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL4_SET , RULL(0x00050124), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL5_FSI , RULL(0x00002815), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL5_FSI_BYTE , RULL(0x00002854), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL5_FSI_BYTE , RULL(0x00002854), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL5_SCOM , RULL(0x00050015), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL5 , RULL(0x00050015), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL5_CLEAR_FSI , RULL(0x00002935), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL5_CLEAR_FSI_BYTE , RULL(0x00002CD4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL5_CLEAR_FSI_BYTE , RULL(0x00002CD4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL5_CLEAR_SCOM , RULL(0x00050135), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL5_CLEAR , RULL(0x00050135), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL5_COPY_FSI , RULL(0x00002915), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL5_COPY_FSI_BYTE , RULL(0x00002C54), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL5_COPY_FSI_BYTE , RULL(0x00002C54), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL5_COPY_SCOM , RULL(0x00050115), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL5_COPY , RULL(0x00050115), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL5_SET_FSI , RULL(0x00002925), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL5_SET_FSI_BYTE , RULL(0x00002C94), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL5_SET_FSI_BYTE , RULL(0x00002C94), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL5_SET_SCOM , RULL(0x00050125), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL5_SET , RULL(0x00050125), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL6_FSI , RULL(0x00002816), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL6_FSI_BYTE , RULL(0x00002858), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL6_FSI_BYTE , RULL(0x00002858), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL6_SCOM , RULL(0x00050016), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL6 , RULL(0x00050016), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL6_CLEAR_FSI , RULL(0x00002936), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL6_CLEAR_FSI_BYTE , RULL(0x00002CD8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL6_CLEAR_FSI_BYTE , RULL(0x00002CD8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL6_CLEAR_SCOM , RULL(0x00050136), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL6_CLEAR , RULL(0x00050136), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL6_COPY_FSI , RULL(0x00002916), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL6_COPY_FSI_BYTE , RULL(0x00002C58), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL6_COPY_FSI_BYTE , RULL(0x00002C58), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL6_COPY_SCOM , RULL(0x00050116), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL6_COPY , RULL(0x00050116), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL6_SET_FSI , RULL(0x00002926), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL6_SET_FSI_BYTE , RULL(0x00002C98), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL6_SET_FSI_BYTE , RULL(0x00002C98), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL6_SET_SCOM , RULL(0x00050126), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL6_SET , RULL(0x00050126), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL7_FSI , RULL(0x00002817), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL7_FSI_BYTE , RULL(0x0000285C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL7_FSI_BYTE , RULL(0x0000285C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL7_SCOM , RULL(0x00050017), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL7 , RULL(0x00050017), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL7_CLEAR_FSI , RULL(0x00002937), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL7_CLEAR_FSI_BYTE , RULL(0x00002CDC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL7_CLEAR_FSI_BYTE , RULL(0x00002CDC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL7_CLEAR_SCOM , RULL(0x00050137), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL7_CLEAR , RULL(0x00050137), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL7_COPY_FSI , RULL(0x00002917), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL7_COPY_FSI_BYTE , RULL(0x00002C5C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL7_COPY_FSI_BYTE , RULL(0x00002C5C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL7_COPY_SCOM , RULL(0x00050117), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL7_COPY , RULL(0x00050117), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL7_SET_FSI , RULL(0x00002927), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL7_SET_FSI_BYTE , RULL(0x00002C9C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL7_SET_FSI_BYTE , RULL(0x00002C9C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL7_SET_SCOM , RULL(0x00050127), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL7_SET , RULL(0x00050127), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL8_FSI , RULL(0x00002818), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL8_FSI_BYTE , RULL(0x00002860), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL8_FSI_BYTE , RULL(0x00002860), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL8_SCOM , RULL(0x00050018), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL8 , RULL(0x00050018), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL8_CLEAR_FSI , RULL(0x00002938), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL8_CLEAR_FSI_BYTE , RULL(0x00002CE0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL8_CLEAR_FSI_BYTE , RULL(0x00002CE0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL8_CLEAR_SCOM , RULL(0x00050138), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL8_CLEAR , RULL(0x00050138), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL8_COPY_FSI , RULL(0x00002918), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL8_COPY_FSI_BYTE , RULL(0x00002C60), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL8_COPY_FSI_BYTE , RULL(0x00002C60), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL8_COPY_SCOM , RULL(0x00050118), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL8_COPY , RULL(0x00050118), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL8_SET_FSI , RULL(0x00002928), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_ROOT_CTRL8_SET_FSI_BYTE , RULL(0x00002CA0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_ROOT_CTRL8_SET_FSI_BYTE , RULL(0x00002CA0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL8_SET_SCOM , RULL(0x00050128), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL8_SET , RULL(0x00050128), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -8907,15 +8960,324 @@ REG64( PERV_SBE_LCL_TBR_PPE , RULL(0x00000140 REG64( PERV_SBE_LCL_TSEL_PPE , RULL(0x00000100), SH_UNT_PERV , SH_ACS_PPE ); REG32( PERV_SB_CS_FSI , RULL(0x00002808), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SB_CS_FSI_BYTE , RULL(0x00002820), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SB_CS_FSI_BYTE , RULL(0x00002820), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SB_CS_SCOM , RULL(0x00050008), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SB_CS , RULL(0x00050008), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SB_MSG_FSI , RULL(0x00002809), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SB_MSG_FSI_BYTE , RULL(0x00002824), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SB_MSG_FSI_BYTE , RULL(0x00002824), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SB_MSG_SCOM , RULL(0x00050009), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SB_MSG , RULL(0x00050009), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG64( PERV_SCAN32 , RULL(0x00038000), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_TP_SCAN32 , RULL(0x01038000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_SCAN32 , RULL(0x02038000), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_SCAN32 , RULL(0x03038000), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_SCAN32 , RULL(0x04038000), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_SCAN32 , RULL(0x05038000), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_SCAN32 , RULL(0x06038000), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_SCAN32 , RULL(0x07038000), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_SCAN32 , RULL(0x08038000), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_SCAN32 , RULL(0x09038000), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_SCAN32 , RULL(0x0C038000), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_SCAN32 , RULL(0x0D038000), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_SCAN32 , RULL(0x0E038000), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_SCAN32 , RULL(0x0F038000), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_SCAN32 , RULL(0x10038000), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_SCAN32 , RULL(0x11038000), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_SCAN32 , RULL(0x12038000), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_SCAN32 , RULL(0x13038000), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_SCAN32 , RULL(0x14038000), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_SCAN32 , RULL(0x15038000), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_SCAN32 , RULL(0x20038000), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_SCAN32 , RULL(0x21038000), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_SCAN32 , RULL(0x22038000), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_SCAN32 , RULL(0x23038000), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_SCAN32 , RULL(0x24038000), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_SCAN32 , RULL(0x25038000), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_SCAN32 , RULL(0x26038000), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_SCAN32 , RULL(0x27038000), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_SCAN32 , RULL(0x28038000), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_SCAN32 , RULL(0x29038000), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_SCAN32 , RULL(0x2A038000), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_SCAN32 , RULL(0x2B038000), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_SCAN32 , RULL(0x2C038000), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_SCAN32 , RULL(0x2D038000), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_SCAN32 , RULL(0x2E038000), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_SCAN32 , RULL(0x2F038000), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_SCAN32 , RULL(0x30038000), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_SCAN32 , RULL(0x31038000), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_SCAN32 , RULL(0x32038000), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_SCAN32 , RULL(0x33038000), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_SCAN32 , RULL(0x34038000), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_SCAN32 , RULL(0x35038000), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_SCAN32 , RULL(0x36038000), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_SCAN32 , RULL(0x37038000), SH_UNT_PERV_55 , SH_ACS_SCOM ); + +REG64( PERV_SCAN64 , RULL(0x0003E000), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_TP_SCAN64 , RULL(0x0103E000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_SCAN64 , RULL(0x0203E000), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_SCAN64 , RULL(0x0303E000), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_SCAN64 , RULL(0x0403E000), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_SCAN64 , RULL(0x0503E000), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_SCAN64 , RULL(0x0603E000), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_SCAN64 , RULL(0x0703E000), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_SCAN64 , RULL(0x0803E000), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_SCAN64 , RULL(0x0903E000), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_SCAN64 , RULL(0x0C03E000), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_SCAN64 , RULL(0x0D03E000), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_SCAN64 , RULL(0x0E03E000), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_SCAN64 , RULL(0x0F03E000), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_SCAN64 , RULL(0x1003E000), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_SCAN64 , RULL(0x1103E000), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_SCAN64 , RULL(0x1203E000), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_SCAN64 , RULL(0x1303E000), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_SCAN64 , RULL(0x1403E000), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_SCAN64 , RULL(0x1503E000), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_SCAN64 , RULL(0x2003E000), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_SCAN64 , RULL(0x2103E000), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_SCAN64 , RULL(0x2203E000), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_SCAN64 , RULL(0x2303E000), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_SCAN64 , RULL(0x2403E000), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_SCAN64 , RULL(0x2503E000), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_SCAN64 , RULL(0x2603E000), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_SCAN64 , RULL(0x2703E000), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_SCAN64 , RULL(0x2803E000), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_SCAN64 , RULL(0x2903E000), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_SCAN64 , RULL(0x2A03E000), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_SCAN64 , RULL(0x2B03E000), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_SCAN64 , RULL(0x2C03E000), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_SCAN64 , RULL(0x2D03E000), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_SCAN64 , RULL(0x2E03E000), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_SCAN64 , RULL(0x2F03E000), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_SCAN64 , RULL(0x3003E000), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_SCAN64 , RULL(0x3103E000), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_SCAN64 , RULL(0x3203E000), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_SCAN64 , RULL(0x3303E000), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_SCAN64 , RULL(0x3403E000), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_SCAN64 , RULL(0x3503E000), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_SCAN64 , RULL(0x3603E000), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_SCAN64 , RULL(0x3703E000), SH_UNT_PERV_55 , SH_ACS_SCOM ); + +REG64( PERV_SCAN_CAPTUREDR , RULL(0x0003C000), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_TP_SCAN_CAPTUREDR , RULL(0x0103C000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_SCAN_CAPTUREDR , RULL(0x0203C000), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_SCAN_CAPTUREDR , RULL(0x0303C000), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_SCAN_CAPTUREDR , RULL(0x0403C000), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_SCAN_CAPTUREDR , RULL(0x0503C000), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_SCAN_CAPTUREDR , RULL(0x0603C000), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_SCAN_CAPTUREDR , RULL(0x0703C000), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_SCAN_CAPTUREDR , RULL(0x0803C000), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_SCAN_CAPTUREDR , RULL(0x0903C000), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_SCAN_CAPTUREDR , RULL(0x0C03C000), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_SCAN_CAPTUREDR , RULL(0x0D03C000), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_SCAN_CAPTUREDR , RULL(0x0E03C000), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_SCAN_CAPTUREDR , RULL(0x0F03C000), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_SCAN_CAPTUREDR , RULL(0x1003C000), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_SCAN_CAPTUREDR , RULL(0x1103C000), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_SCAN_CAPTUREDR , RULL(0x1203C000), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_SCAN_CAPTUREDR , RULL(0x1303C000), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_SCAN_CAPTUREDR , RULL(0x1403C000), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_SCAN_CAPTUREDR , RULL(0x1503C000), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_SCAN_CAPTUREDR , RULL(0x2003C000), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_SCAN_CAPTUREDR , RULL(0x2103C000), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_SCAN_CAPTUREDR , RULL(0x2203C000), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_SCAN_CAPTUREDR , RULL(0x2303C000), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_SCAN_CAPTUREDR , RULL(0x2403C000), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_SCAN_CAPTUREDR , RULL(0x2503C000), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_SCAN_CAPTUREDR , RULL(0x2603C000), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_SCAN_CAPTUREDR , RULL(0x2703C000), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_SCAN_CAPTUREDR , RULL(0x2803C000), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_SCAN_CAPTUREDR , RULL(0x2903C000), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_SCAN_CAPTUREDR , RULL(0x2A03C000), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_SCAN_CAPTUREDR , RULL(0x2B03C000), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_SCAN_CAPTUREDR , RULL(0x2C03C000), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_SCAN_CAPTUREDR , RULL(0x2D03C000), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_SCAN_CAPTUREDR , RULL(0x2E03C000), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_SCAN_CAPTUREDR , RULL(0x2F03C000), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_SCAN_CAPTUREDR , RULL(0x3003C000), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_SCAN_CAPTUREDR , RULL(0x3103C000), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_SCAN_CAPTUREDR , RULL(0x3203C000), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_SCAN_CAPTUREDR , RULL(0x3303C000), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_SCAN_CAPTUREDR , RULL(0x3403C000), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_SCAN_CAPTUREDR , RULL(0x3503C000), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_SCAN_CAPTUREDR , RULL(0x3603C000), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_SCAN_CAPTUREDR , RULL(0x3703C000), SH_UNT_PERV_55 , SH_ACS_SCOM ); + +REG64( PERV_12_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0C03D000), SH_UNT_PERV_12_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_13_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0D03D000), SH_UNT_PERV_13_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_14_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0E03D000), SH_UNT_PERV_14_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_15_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0F03D000), SH_UNT_PERV_15_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_16_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x1003D000), SH_UNT_PERV_16_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_17_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x1103D000), SH_UNT_PERV_17_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_18_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x1203D000), SH_UNT_PERV_18_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_19_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x1303D000), SH_UNT_PERV_19_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_1_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0103D000), SH_UNT_PERV_1_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_20_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x1403D000), SH_UNT_PERV_20_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_21_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x1503D000), SH_UNT_PERV_21_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_2_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0203D000), SH_UNT_PERV_2_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_32_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2003D000), SH_UNT_PERV_32_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_33_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2103D000), SH_UNT_PERV_33_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_34_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2203D000), SH_UNT_PERV_34_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_35_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2303D000), SH_UNT_PERV_35_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_36_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2403D000), SH_UNT_PERV_36_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_37_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2503D000), SH_UNT_PERV_37_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_38_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2603D000), SH_UNT_PERV_38_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_39_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2703D000), SH_UNT_PERV_39_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_3_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0303D000), SH_UNT_PERV_3_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_40_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2803D000), SH_UNT_PERV_40_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_41_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2903D000), SH_UNT_PERV_41_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_42_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2A03D000), SH_UNT_PERV_42_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_43_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2B03D000), SH_UNT_PERV_43_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_44_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2C03D000), SH_UNT_PERV_44_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_45_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2D03D000), SH_UNT_PERV_45_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_46_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2E03D000), SH_UNT_PERV_46_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_47_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x2F03D000), SH_UNT_PERV_47_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_48_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3003D000), SH_UNT_PERV_48_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_49_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3103D000), SH_UNT_PERV_49_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_4_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0403D000), SH_UNT_PERV_4_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_50_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3203D000), SH_UNT_PERV_50_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_51_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3303D000), SH_UNT_PERV_51_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_52_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3403D000), SH_UNT_PERV_52_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_53_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3503D000), SH_UNT_PERV_53_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_54_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3603D000), SH_UNT_PERV_54_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_55_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x3703D000), SH_UNT_PERV_55_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_5_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0503D000), SH_UNT_PERV_5_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_6_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0603D000), SH_UNT_PERV_6_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_7_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0703D000), SH_UNT_PERV_7_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_8_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0803D000), SH_UNT_PERV_8_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_9_FSI2PIB_SCAN_CAPTUREDR_LONG , RULL(0x0903D000), SH_UNT_PERV_9_FSI2PIB, + SH_ACS_SCOM ); + +REG64( PERV_12_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x0C039000), SH_UNT_PERV_12_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_13_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x0D039000), SH_UNT_PERV_13_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_14_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x0E039000), SH_UNT_PERV_14_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_15_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x0F039000), SH_UNT_PERV_15_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_16_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x10039000), SH_UNT_PERV_16_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_17_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x11039000), SH_UNT_PERV_17_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_18_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x12039000), SH_UNT_PERV_18_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_19_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x13039000), SH_UNT_PERV_19_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_1_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x01039000), SH_UNT_PERV_1_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_20_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x14039000), SH_UNT_PERV_20_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_21_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x15039000), SH_UNT_PERV_21_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_2_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x02039000), SH_UNT_PERV_2_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_32_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x20039000), SH_UNT_PERV_32_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_33_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x21039000), SH_UNT_PERV_33_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_34_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x22039000), SH_UNT_PERV_34_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_35_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x23039000), SH_UNT_PERV_35_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_36_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x24039000), SH_UNT_PERV_36_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_37_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x25039000), SH_UNT_PERV_37_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_38_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x26039000), SH_UNT_PERV_38_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_39_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x27039000), SH_UNT_PERV_39_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_3_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x03039000), SH_UNT_PERV_3_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_40_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x28039000), SH_UNT_PERV_40_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_41_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x29039000), SH_UNT_PERV_41_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_42_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x2A039000), SH_UNT_PERV_42_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_43_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x2B039000), SH_UNT_PERV_43_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_44_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x2C039000), SH_UNT_PERV_44_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_45_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x2D039000), SH_UNT_PERV_45_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_46_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x2E039000), SH_UNT_PERV_46_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_47_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x2F039000), SH_UNT_PERV_47_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_48_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x30039000), SH_UNT_PERV_48_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_49_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x31039000), SH_UNT_PERV_49_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_4_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x04039000), SH_UNT_PERV_4_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_50_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x32039000), SH_UNT_PERV_50_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_51_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x33039000), SH_UNT_PERV_51_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_52_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x34039000), SH_UNT_PERV_52_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_53_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x35039000), SH_UNT_PERV_53_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_54_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x36039000), SH_UNT_PERV_54_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_55_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x37039000), SH_UNT_PERV_55_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_5_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x05039000), SH_UNT_PERV_5_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_6_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x06039000), SH_UNT_PERV_6_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_7_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x07039000), SH_UNT_PERV_7_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_8_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x08039000), SH_UNT_PERV_8_FSI2PIB, + SH_ACS_SCOM ); +REG64( PERV_9_FSI2PIB_SCAN_LONG_ROTATE , RULL(0x09039000), SH_UNT_PERV_9_FSI2PIB, + SH_ACS_SCOM ); + REG64( PERV_SCAN_REGION_TYPE , RULL(0x00030005), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_TP_SCAN_REGION_TYPE , RULL(0x01030005), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_N0_SCAN_REGION_TYPE , RULL(0x02030005), SH_UNT_PERV_2 , SH_ACS_SCOM ); @@ -8961,45 +9323,135 @@ REG64( PERV_EC21_SCAN_REGION_TYPE , RULL(0x35030005 REG64( PERV_EC22_SCAN_REGION_TYPE , RULL(0x36030005), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_SCAN_REGION_TYPE , RULL(0x37030005), SH_UNT_PERV_55 , SH_ACS_SCOM ); +REG64( PERV_SCAN_UPDATEDR , RULL(0x0003A000), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_TP_SCAN_UPDATEDR , RULL(0x0103A000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_SCAN_UPDATEDR , RULL(0x0203A000), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_SCAN_UPDATEDR , RULL(0x0303A000), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_SCAN_UPDATEDR , RULL(0x0403A000), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_SCAN_UPDATEDR , RULL(0x0503A000), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_SCAN_UPDATEDR , RULL(0x0603A000), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_SCAN_UPDATEDR , RULL(0x0703A000), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_SCAN_UPDATEDR , RULL(0x0803A000), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_SCAN_UPDATEDR , RULL(0x0903A000), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_SCAN_UPDATEDR , RULL(0x0C03A000), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_SCAN_UPDATEDR , RULL(0x0D03A000), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_SCAN_UPDATEDR , RULL(0x0E03A000), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_SCAN_UPDATEDR , RULL(0x0F03A000), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_SCAN_UPDATEDR , RULL(0x1003A000), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_SCAN_UPDATEDR , RULL(0x1103A000), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_SCAN_UPDATEDR , RULL(0x1203A000), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_SCAN_UPDATEDR , RULL(0x1303A000), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_SCAN_UPDATEDR , RULL(0x1403A000), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_SCAN_UPDATEDR , RULL(0x1503A000), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_SCAN_UPDATEDR , RULL(0x2003A000), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_SCAN_UPDATEDR , RULL(0x2103A000), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_SCAN_UPDATEDR , RULL(0x2203A000), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_SCAN_UPDATEDR , RULL(0x2303A000), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_SCAN_UPDATEDR , RULL(0x2403A000), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_SCAN_UPDATEDR , RULL(0x2503A000), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_SCAN_UPDATEDR , RULL(0x2603A000), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_SCAN_UPDATEDR , RULL(0x2703A000), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_SCAN_UPDATEDR , RULL(0x2803A000), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_SCAN_UPDATEDR , RULL(0x2903A000), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_SCAN_UPDATEDR , RULL(0x2A03A000), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_SCAN_UPDATEDR , RULL(0x2B03A000), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_SCAN_UPDATEDR , RULL(0x2C03A000), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_SCAN_UPDATEDR , RULL(0x2D03A000), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_SCAN_UPDATEDR , RULL(0x2E03A000), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_SCAN_UPDATEDR , RULL(0x2F03A000), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_SCAN_UPDATEDR , RULL(0x3003A000), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_SCAN_UPDATEDR , RULL(0x3103A000), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_SCAN_UPDATEDR , RULL(0x3203A000), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_SCAN_UPDATEDR , RULL(0x3303A000), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_SCAN_UPDATEDR , RULL(0x3403A000), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_SCAN_UPDATEDR , RULL(0x3503A000), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_SCAN_UPDATEDR , RULL(0x3603A000), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_SCAN_UPDATEDR , RULL(0x3703A000), SH_UNT_PERV_55 , SH_ACS_SCOM ); + +REG64( PERV_SCAN_UPDATEDR_LONG , RULL(0x0003B000), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_TP_SCAN_UPDATEDR_LONG , RULL(0x0103B000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_SCAN_UPDATEDR_LONG , RULL(0x0203B000), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_SCAN_UPDATEDR_LONG , RULL(0x0303B000), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_SCAN_UPDATEDR_LONG , RULL(0x0403B000), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_SCAN_UPDATEDR_LONG , RULL(0x0503B000), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_SCAN_UPDATEDR_LONG , RULL(0x0603B000), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_SCAN_UPDATEDR_LONG , RULL(0x0703B000), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_SCAN_UPDATEDR_LONG , RULL(0x0803B000), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_SCAN_UPDATEDR_LONG , RULL(0x0903B000), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_SCAN_UPDATEDR_LONG , RULL(0x0C03B000), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_SCAN_UPDATEDR_LONG , RULL(0x0D03B000), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_SCAN_UPDATEDR_LONG , RULL(0x0E03B000), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_SCAN_UPDATEDR_LONG , RULL(0x0F03B000), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_SCAN_UPDATEDR_LONG , RULL(0x1003B000), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_SCAN_UPDATEDR_LONG , RULL(0x1103B000), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_SCAN_UPDATEDR_LONG , RULL(0x1203B000), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_SCAN_UPDATEDR_LONG , RULL(0x1303B000), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_SCAN_UPDATEDR_LONG , RULL(0x1403B000), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_SCAN_UPDATEDR_LONG , RULL(0x1503B000), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_SCAN_UPDATEDR_LONG , RULL(0x2003B000), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_SCAN_UPDATEDR_LONG , RULL(0x2103B000), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_SCAN_UPDATEDR_LONG , RULL(0x2203B000), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_SCAN_UPDATEDR_LONG , RULL(0x2303B000), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_SCAN_UPDATEDR_LONG , RULL(0x2403B000), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_SCAN_UPDATEDR_LONG , RULL(0x2503B000), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_SCAN_UPDATEDR_LONG , RULL(0x2603B000), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_SCAN_UPDATEDR_LONG , RULL(0x2703B000), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_SCAN_UPDATEDR_LONG , RULL(0x2803B000), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_SCAN_UPDATEDR_LONG , RULL(0x2903B000), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_SCAN_UPDATEDR_LONG , RULL(0x2A03B000), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_SCAN_UPDATEDR_LONG , RULL(0x2B03B000), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_SCAN_UPDATEDR_LONG , RULL(0x2C03B000), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_SCAN_UPDATEDR_LONG , RULL(0x2D03B000), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_SCAN_UPDATEDR_LONG , RULL(0x2E03B000), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_SCAN_UPDATEDR_LONG , RULL(0x2F03B000), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_SCAN_UPDATEDR_LONG , RULL(0x3003B000), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_SCAN_UPDATEDR_LONG , RULL(0x3103B000), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_SCAN_UPDATEDR_LONG , RULL(0x3203B000), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_SCAN_UPDATEDR_LONG , RULL(0x3303B000), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_SCAN_UPDATEDR_LONG , RULL(0x3403B000), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_SCAN_UPDATEDR_LONG , RULL(0x3503B000), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_SCAN_UPDATEDR_LONG , RULL(0x3603B000), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_SCAN_UPDATEDR_LONG , RULL(0x3703B000), SH_UNT_PERV_55 , SH_ACS_SCOM ); + REG32( PERV_SCPSIZE_FSI , RULL(0x00001400), SH_UNT_PERV , SH_ACS_FSI ); REG32( PERV_SCRATCH_REGISTER_1_FSI , RULL(0x00002838), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_1_FSI_BYTE , RULL(0x000028E0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_1_FSI_BYTE , RULL(0x000028E0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_1_SCOM , RULL(0x00050038), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_1 , RULL(0x00050038), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_2_FSI , RULL(0x00002839), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_2_FSI_BYTE , RULL(0x000028E4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_2_FSI_BYTE , RULL(0x000028E4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_2_SCOM , RULL(0x00050039), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_2 , RULL(0x00050039), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_3_FSI , RULL(0x0000283A), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_3_FSI_BYTE , RULL(0x000028E8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_3_FSI_BYTE , RULL(0x000028E8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_3_SCOM , RULL(0x0005003A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_3 , RULL(0x0005003A), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_4_FSI , RULL(0x0000283B), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_4_FSI_BYTE , RULL(0x000028EC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_4_FSI_BYTE , RULL(0x000028EC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_4_SCOM , RULL(0x0005003B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_4 , RULL(0x0005003B), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_5_FSI , RULL(0x0000283C), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_5_FSI_BYTE , RULL(0x000028F0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_5_FSI_BYTE , RULL(0x000028F0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_5_SCOM , RULL(0x0005003C), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_5 , RULL(0x0005003C), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_6_FSI , RULL(0x0000283D), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_6_FSI_BYTE , RULL(0x000028F4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_6_FSI_BYTE , RULL(0x000028F4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_6_SCOM , RULL(0x0005003D), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_6 , RULL(0x0005003D), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_7_FSI , RULL(0x0000283E), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_7_FSI_BYTE , RULL(0x000028F8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_7_FSI_BYTE , RULL(0x000028F8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_7_SCOM , RULL(0x0005003E), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_7 , RULL(0x0005003E), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SCRATCH_REGISTER_8_FSI , RULL(0x0000283F), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SCRATCH_REGISTER_8_FSI_BYTE , RULL(0x000028FC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SCRATCH_REGISTER_8_FSI_BYTE , RULL(0x000028FC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_8_SCOM , RULL(0x0005003F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_8 , RULL(0x0005003F), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -9333,12 +9785,12 @@ REG64( PERV_EC22_SLAVE_CONFIG_REG , RULL(0x360F001E REG64( PERV_EC23_SLAVE_CONFIG_REG , RULL(0x370F001E), SH_UNT_PERV_55 , SH_ACS_SCOM ); REG32( PERV_SNS1LTH_FSI , RULL(0x0000281D), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SNS1LTH_FSI_BYTE , RULL(0x00002874), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SNS1LTH_FSI_BYTE , RULL(0x00002874), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SNS1LTH_SCOM , RULL(0x0005001D), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SNS1LTH , RULL(0x0005001D), SH_UNT_PERV_0 , SH_ACS_SCOM ); REG32( PERV_SNS2LTH_FSI , RULL(0x0000281E), SH_UNT_PERV , SH_ACS_FSI ); -REG64( PERV_SNS2LTH_FSI_BYTE , RULL(0x00002878), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG32( PERV_SNS2LTH_FSI_BYTE , RULL(0x00002878), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SNS2LTH_SCOM , RULL(0x0005001E), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SNS2LTH , RULL(0x0005001E), SH_UNT_PERV_0 , SH_ACS_SCOM ); diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H index 4e7af7a1..ccb91a9c 100644 --- a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H +++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H @@ -68,8 +68,5 @@ REG64( PERV_OB2_CPLT_CONF1_OR, REG64( PERV_OB2_CPLT_CONF1_CLEAR, RULL(0x0B000029), SH_UNT_PERV_11, SH_ACS_SCOM2_CLEAR); -REG32( PERV_CBS_ENVSTAT_FSI, RULL(0x00002804), SH_UNT_PERV_CBS_ENVSTAT, SH_ACS_FSI); -REG64( PERV_CBS_ENVSTAT_FSI_BYTE, RULL(0x00002810), SH_UNT_PERV_CBS_ENVSTAT, SH_ACS_FSI_BYTE); -REG64( PERV_CBS_ENVSTAT_SCOM, RULL(0x00050004), SH_UNT_PERV_CBS_ENVSTAT, SH_ACS_SCOM); #endif diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H index 7ecb0c94..26860c30 100644 --- a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H @@ -62,6 +62,13 @@ REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); +REG64_FLD( PERV_1_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ATTN ); +REG64_FLD( PERV_1_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RECOV ); +REG64_FLD( PERV_1_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -78,6 +85,9 @@ REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UN REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); +REG64_FLD( PERV_1_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ATTN ); + REG64_FLD( PERV_1_BIST_TC_START_TEST_DC , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TC_START_TEST_DC ); REG64_FLD( PERV_1_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -137,6 +147,19 @@ REG64_FLD( PERV_CBS_CS_INTERNAL_STATE_VECTOR , 16 , SH_UN REG64_FLD( PERV_CBS_CS_INTERNAL_STATE_VECTOR_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_INTERNAL_STATE_VECTOR_LEN ); +REG64_FLD( PERV_CBS_ENVSTAT_C4_TEST_ENABLE , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_C4_TEST_ENABLE ); +REG64_FLD( PERV_CBS_ENVSTAT_C4_CARD_TEST_BSC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_C4_CARD_TEST_BSC ); +REG64_FLD( PERV_CBS_ENVSTAT_C4_VDN_GPOOD , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_C4_VDN_GPOOD ); +REG64_FLD( PERV_CBS_ENVSTAT_C4_FSI_IN_ENA , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_C4_FSI_IN_ENA ); +REG64_FLD( PERV_CBS_ENVSTAT_C4_CHIP_MASTER , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_C4_CHIP_MASTER ); +REG64_FLD( PERV_CBS_ENVSTAT_C4_SMD , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_C4_SMD ); + REG64_FLD( PERV_CBS_STAT_DBG_RESET_EP , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_DBG_RESET_EP ); REG64_FLD( PERV_CBS_STAT_DBG_OPCG_IP , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -325,12 +348,36 @@ REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT10 , 14 , SH_UN REG64_FLD( PERV_PIB2OPB1_CMD_WRDAT_WRITE_NOT_READ , 0 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM , SH_FLD_WRITE_NOT_READ ); +REG64_FLD( PERV_PIB2OPB1_CMD_WRDAT_CMD , 1 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM , + SH_FLD_CMD ); +REG64_FLD( PERV_PIB2OPB1_CMD_WRDAT_CMD_LEN , 31 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM , + SH_FLD_CMD_LEN ); +REG64_FLD( PERV_PIB2OPB1_CMD_WRDAT_WDATA , 32 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM , + SH_FLD_WDATA ); +REG64_FLD( PERV_PIB2OPB1_CMD_WRDAT_WDATA_LEN , 32 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM , + SH_FLD_WDATA_LEN ); REG64_FLD( PERV_CMD_WRDAT_WRITE_NOT_READ , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_WRITE_NOT_READ ); +REG64_FLD( PERV_CMD_WRDAT_CMD , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_CMD ); +REG64_FLD( PERV_CMD_WRDAT_CMD_LEN , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_CMD_LEN ); +REG64_FLD( PERV_CMD_WRDAT_WDATA , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_WDATA ); +REG64_FLD( PERV_CMD_WRDAT_WDATA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_WDATA_LEN ); REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_WRITE_NOT_READ , 0 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM , SH_FLD_WRITE_NOT_READ ); +REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_CMD , 1 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM , + SH_FLD_CMD ); +REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_CMD_LEN , 31 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM , + SH_FLD_CMD_LEN ); +REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_WDATA , 32 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM , + SH_FLD_WDATA ); +REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_WDATA_LEN , 32 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM , + SH_FLD_WDATA_LEN ); REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_CMD_REG ); @@ -387,6 +434,33 @@ REG32_FLD( PERV_FSISHIFT_COMPLEMENT_MASK_REG , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_COMPLEMENT_MASK_REG_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN ); +REG64_FLD( PERV_1_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_TRIP_HISTORY ); +REG64_FLD( PERV_1_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_PULSE_CNT ); +REG64_FLD( PERV_1_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_RD ); +REG64_FLD( PERV_1_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_WR ); +REG64_FLD( PERV_1_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_DTS ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L1RESULTS ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L2RESULTS ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L3RESULTS ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_MEASURE_VOLT ); +REG64_FLD( PERV_1_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_SHIFT_SENSOR ); + REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, @@ -474,8 +548,10 @@ REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UN REG64_FLD( PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, SH_FLD_TCPERV_AMUX_VSELECT_CHIP ); -REG64_FLD( PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, +REG64_FLD( PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN ); +REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_3D , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_3D ); REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_4D , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_4D ); REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM2_CLEAR, @@ -1034,10 +1110,14 @@ REG64_FLD( PERV_1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( PERV_1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PERV_1_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PERV_1_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PERV_1_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -1046,6 +1126,10 @@ REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PERV_1_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( PERV_1_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( PERV_1_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); @@ -1194,6 +1278,13 @@ REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UN REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PERV_1_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( PERV_1_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( PERV_1_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + REG64_FLD( PERV_DEVICE_ID_REG_SOCKET , 36 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_SOCKET ); REG64_FLD( PERV_DEVICE_ID_REG_SOCKET_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , @@ -1345,6 +1436,11 @@ REG64_FLD( PERV_1_DTS_TRC_RESULT_1 , 48 , SH_UN REG64_FLD( PERV_1_DTS_TRC_RESULT_1_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); +REG64_FLD( PERV_1_EDRAM_STATUS_STAT , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STAT ); +REG64_FLD( PERV_1_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STAT_LEN ); + REG64_FLD( PERV_ERROR_REG_TIMEOUT_ACTIVE , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TIMEOUT_ACTIVE ); REG64_FLD( PERV_ERROR_REG_PARITY_ERR , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -1362,11 +1458,103 @@ REG64_FLD( PERV_ERROR_REG_PIB_ADDR_P_ERR , 6 , SH_UN REG64_FLD( PERV_ERROR_REG_PIB_DATA_P_ERR , 7 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_PIB_DATA_P_ERR ); -REG64_FLD( PERV_1_ERROR_STATUS_ERRORS , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_ERRORS ); -REG64_FLD( PERV_1_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_ERRORS_LEN ); - +REG64_FLD( PERV_1_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_CMD_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_ADDR_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_DATA_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_CONFLICT_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCAN_COLLISION_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_OPCG_TRIGGER_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PHASE_CNT_CORRUPTION_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_PREVENTED_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_SM_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_REG_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_XSTOP_REG_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_GPIO_REG_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CLKCMD_REQUEST_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CBS_PROTOCOL_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_VITL_ALIGN_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNIT_SYNC_LVL_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); +REG64_FLD( PERV_1_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR27 ); +REG64_FLD( PERV_1_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR28 ); +REG64_FLD( PERV_1_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR29 ); +REG64_FLD( PERV_1_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR30 ); +REG64_FLD( PERV_1_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR31 ); + +REG64_FLD( PERV_1_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_STATE_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_ERR_HOLD ); +REG64_FLD( PERV_1_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( PERV_1_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( PERV_1_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , @@ -1397,6 +1585,36 @@ REG64_FLD( PERV_1_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( PERV_1_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); +REG64_FLD( PERV_1_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT_LEN ); +REG64_FLD( PERV_1_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT_LEN ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_DTS_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_VOLT_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT_LEN ); +REG64_FLD( PERV_1_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT_LEN ); +REG64_FLD( PERV_1_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_SAMPLE_DTS_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_MEASURE_VOLT_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_READ_CPM_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CPM_LT ); +REG64_FLD( PERV_1_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0 , 11 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_0 ); @@ -1481,15 +1699,35 @@ REG64_FLD( PERV_1_FIR_MASK_IN21_LEN , 5 , SH_UN REG64_FLD( PERV_1_FIR_MASK_IN26 , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN26 ); -REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_FMU_FORCE_OP_REG_FORCE_MEASURE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE ); +REG64_FLD( PERV_1_FMU_FORCE_OP_REG_FORCE_FMU_SM_RESET , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_FMU_SM_RESET ); + +REG64_FLD( PERV_1_FMU_KVREF_DATAREG_FMU_KVREF_DATAREG , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_FMU_KVREF_DATAREG ); +REG64_FLD( PERV_1_FMU_KVREF_DATAREG_FMU_KVREF_DATAREG_LEN , 64 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_FMU_KVREF_DATAREG_LEN ); + +REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TOD_CNTR_REF ); -REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TOD_CNTR_REF_LEN ); +REG64_FLD( PERV_1_FMU_MODE_REG_UNUSED1 , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED1 ); REG64_FLD( PERV_1_FMU_MODE_REG_POWER_UP_CNTR_REF , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_POWER_UP_CNTR_REF ); REG64_FLD( PERV_1_FMU_MODE_REG_POWER_UP_CNTR_REF_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_POWER_UP_CNTR_REF_LEN ); +REG64_FLD( PERV_1_FMU_MODE_REG_UNUSED2 , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED2 ); +REG64_FLD( PERV_1_FMU_MODE_REG_UNUSED2_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED2_LEN ); +REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_FMU_PULSE_GEN_REG_ERR , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FMU_PULSE_GEN_REG_ERR ); +REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_FMU_MODEREG_P_ERR , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FMU_MODEREG_P_ERR ); REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_RESULT_AVAILABLE , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_RESULT_AVAILABLE ); REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -1497,6 +1735,10 @@ REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR , 4 , SH_UN REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_PULSE1_CNTR_LEN ); +REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_FMU_PULSE_GEN_REG_ERR , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FMU_PULSE_GEN_REG_ERR ); +REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_FMU_MODEREG_P_ERR , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FMU_MODEREG_P_ERR ); REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_RESULT_AVAILABLE , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_RESULT_AVAILABLE ); REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_PULSE2_CNTR , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -1506,55 +1748,94 @@ REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_PULSE2_CNTR_LEN , 24 , SH_UN REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_INT_ENA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_INT_ENA ); +REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_UNUSED3 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED3 ); REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_INT_CNTR_REF , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_INT_CNTR_REF ); REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_INT_CNTR_REF_LEN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_INT_CNTR_REF_LEN ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG64_FLD( PERV_1_FMU_VMEAS_MAX_RESULT_VMEAS_MAX_RESULT , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_VMEAS_MAX_RESULT ); +REG64_FLD( PERV_1_FMU_VMEAS_MAX_RESULT_VMEAS_MAX_RESULT_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_VMEAS_MAX_RESULT_LEN ); + +REG64_FLD( PERV_1_FMU_VMEAS_MIN_RESULT_VMEAS_MIN_RESULT , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_VMEAS_MIN_RESULT ); +REG64_FLD( PERV_1_FMU_VMEAS_MIN_RESULT_VMEAS_MIN_RESULT_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_VMEAS_MIN_RESULT_LEN ); + +REG32_FLD( PERV_FSB_FSB_DNFIFO_DATA_OUT_DNFIFO_DATA_OUT_PORT , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_DNFIFO_DATA_OUT_PORT ); +REG32_FLD( PERV_FSB_FSB_DNFIFO_DATA_OUT_DNFIFO_DATA_OUT_PORT_LEN , 32 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_DNFIFO_DATA_OUT_PORT_LEN ); + +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_DNFIFO_ACK , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_DNFIFO_ACK ); + +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_MTC_DNFIFO_MCT , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_DNFIFO_MCT ); +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_MTC_DNFIFO_MCT_LEN , 32 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_DNFIFO_MCT_LEN ); + +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_RESET_DNFIFO_RESET , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_DNFIFO_RESET ); + +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_REQ_RESET_FR_SBE ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_REQ_RESET_FR_SP ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_FULL ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_EMPTY ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_VALID_FLAGS ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_EOT_FLAGS ); -REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_DATA_IN_UPFIFO_DATA_IN_PORT , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI , + SH_FLD_UPFIFO_DATA_IN_PORT ); +REG32_FLD( PERV_FSB_FSB_UPFIFO_DATA_IN_UPFIFO_DATA_IN_PORT_LEN , 32 , SH_UNT_PERV_FSB , SH_ACS_FSI , + SH_FLD_UPFIFO_DATA_IN_PORT_LEN ); + +REG32_FLD( PERV_FSB_FSB_UPFIFO_REQ_RESET_UPFIFO_REQ_RESET , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_UPFIFO_REQ_RESET ); + +REG32_FLD( PERV_FSB_FSB_UPFIFO_SIG_EOT_UPFIFO_SIGNAL , 0 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , + SH_FLD_UPFIFO_SIGNAL ); + +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_REQ_RESET_FR_SP ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_REQ_RESET_FR_SBE ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_DEQUEUED_EOT_FLAG ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_FULL ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_EMPTY ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_ENTRY_COUNT ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_ENTRY_COUNT_LEN ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_VALID_FLAGS ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_VALID_FLAGS_LEN ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_EOT_FLAGS ); -REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , +REG32_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE , SH_FLD_FIFO_EOT_FLAGS_LEN ); REG32_FLD( PERV_FSISCRPD1_FSI_SCRATCH_PAD1 , 0 , SH_UNT_PERV , SH_ACS_FSI_BYTE , @@ -1572,9 +1853,74 @@ REG32_FLD( PERV_FSISCRPD3_FSI_SCRATCH_PAD3 , 0 , SH_UN REG32_FLD( PERV_FSISCRPD3_FSI_SCRATCH_PAD3_LEN , 32 , SH_UNT_PERV , SH_ACS_FSI_BYTE , SH_FLD_FSI_SCRATCH_PAD3_LEN ); +REG32_FLD( PERV_FSI_A_LLMOD_EXTEND_TIMO , 29 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_EXTEND_TIMO ); +REG32_FLD( PERV_FSI_A_LLMOD_DISABLE_GAP , 30 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_DISABLE_GAP ); REG32_FLD( PERV_FSI_A_LLMOD_ASYNC_MODE , 31 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_ASYNC_MODE ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_0 , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_0 ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_0_LEN , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_0_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_NO_CLK , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_NO_CLK ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_2 , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_2 ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_2_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_2_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_BAD_HANDSHAKE_AT_START , 10 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BAD_HANDSHAKE_AT_START ); +REG32_FLD( PERV_FSI_A_LLSTAT_TIMEOUT , 11 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_TIMEOUT ); +REG32_FLD( PERV_FSI_A_LLSTAT_LBUS_BUSY , 12 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LBUS_BUSY ); +REG32_FLD( PERV_FSI_A_LLSTAT_OPB_BUSY , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_OPB_BUSY ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_3 , 14 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_3 ); +REG32_FLD( PERV_FSI_A_LLSTAT_BREAK_PENDING , 15 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BREAK_PENDING ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_4 , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_4 ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_4_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_4_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_HANDSHAKE_STATE , 18 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HANDSHAKE_STATE ); +REG32_FLD( PERV_FSI_A_LLSTAT_HANDSHAKE_STATE_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HANDSHAKE_STATE_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_CFAM_CYCLE_TIME , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CFAM_CYCLE_TIME ); +REG32_FLD( PERV_FSI_A_LLSTAT_CFAM_CYCLE_TIME_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CFAM_CYCLE_TIME_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_REFCLOCK_STATUS , 24 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_REFCLOCK_STATUS ); +REG32_FLD( PERV_FSI_A_LLSTAT_REFCLOCK_STATUS_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_REFCLOCK_STATUS_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_5 , 28 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_5 ); +REG32_FLD( PERV_FSI_A_LLSTAT_RESERVED_5_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESERVED_5_LEN ); +REG32_FLD( PERV_FSI_A_LLSTAT_ASYNC_MODE , 31 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_ASYNC_MODE ); + +REG32_FLD( PERV_FSI_A_MST_0_MAEB_BRIDGE_ERROR , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIDGE_ERROR ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MAEB_BRIDGE_ERROR , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_BRIDGE_ERROR ); + +REG32_FLD( PERV_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CLR_PORT_ENABLE ); +REG32_FLD( PERV_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE_LEN , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CLR_PORT_ENABLE_LEN ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CLR_PORT_ENABLE ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE_LEN , 8 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CLR_PORT_ENABLE_LEN ); + REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT_ENABLE ); REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_1_ENABLE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , @@ -1613,6 +1959,28 @@ REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR , 0 , SH_UN SH_FLD_FIRST_ERROR ); REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_FIRST_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_MMODE_PARITY_CHECK , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MMODE_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_MDLYR_PARITY_CHECK , 9 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MDLYR_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_MCRSP0_PARITY_CHECK , 10 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MCRSP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_MENP0_PARITY_CHECK , 11 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MENP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_MSIEP0_PARITY_CHECK , 12 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_MSSIEP0_PARITY_CHECK , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MSSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK , 14 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_REGISTER_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK , 15 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_OPB_BUS_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_ERROR , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_REGISTER_ACCESS_ERROR ); REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_FAILING_OPB_MASTER_FRST ); REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , @@ -1621,6 +1989,10 @@ REG32_FLD( PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR , 20 , SH_UN SH_FLD_ACTUAL_ERROR ); REG32_FLD( PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_ACTUAL_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_SELECTED_ERROR , 24 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_SELECTED_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MESRB0_SELECTED_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_SELECTED_ERROR_LEN ); REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_FAILING_OPB_MASTER_ACT ); REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , @@ -1630,6 +2002,28 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR , 0 , SH_UN SH_FLD_FIRST_ERROR ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FIRST_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MMODE_PARITY_CHECK , 8 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_MMODE_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MDLYR_PARITY_CHECK , 9 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_MDLYR_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MCRSP0_PARITY_CHECK , 10 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_MCRSP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MENP0_PARITY_CHECK , 11 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_MENP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MSIEP0_PARITY_CHECK , 12 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_MSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MSSIEP0_PARITY_CHECK , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_MSSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK , 14 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_REGISTER_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK , 15 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_OPB_BUS_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_ERROR , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_REGISTER_ACCESS_ERROR ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_FRST ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , @@ -1638,11 +2032,83 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR , 20 , SH_UN SH_FLD_ACTUAL_ERROR ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_ACTUAL_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_SELECTED_ERROR , 24 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_SELECTED_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_SELECTED_ERROR_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_SELECTED_ERROR_LEN ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_1 , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_2 , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_3 , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_4 , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_5 , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_6 , 6 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_7 , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_1 , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_2 , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_3 , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_4 , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_5 , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_6 , 6 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_7 , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_7 ); + REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA , 0 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_ENABLE_IPOLL_AND_DMA ); REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY , 1 , SH_UNT_PERV , SH_ACS_FSI0 , @@ -1697,6 +2163,122 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE , 29 , SH_UN REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_RECEIVER_MODE_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSI_A_MST_0_MRESB0_BRIDGE_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESB0_BRIDGE_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIDGE_ERROR_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_SET_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSI_A_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE , 6 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CLEAR_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSI_A_MST_0_MRESB0_SET_DLY_MEASUREMENT , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_SET_DLY_MEASUREMENT ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESB0_BRIDGE_GENERAL_RESET , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESB0_BRIDGE_ERROR_RESET , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_BRIDGE_ERROR_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_SET_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CLEAR_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESB0_SET_DLY_MEASUREMENT , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_SET_DLY_MEASUREMENT ); + +REG32_FLD( PERV_FSI_A_MST_0_MRESP0_PORT_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESP0_PORT_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PORT_ERROR_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_ALL_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESP0_ALL_PORT_GENERAL_RESET , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_ALL_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESP0_CONTROL_REGISTER_RESET , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CONTROL_REGISTER_RESET ); +REG32_FLD( PERV_FSI_A_MST_0_MRESP0_PARITY_ERROR_RESET , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_PARITY_ERROR_RESET ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP0_PORT_GENERAL_RESET , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP0_PORT_ERROR_RESET , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_PORT_ERROR_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_ALL_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP0_ALL_PORT_GENERAL_RESET , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_ALL_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP0_CONTROL_REGISTER_RESET , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CONTROL_REGISTER_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP0_PARITY_ERROR_RESET , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_PARITY_ERROR_RESET ); + REG32_FLD( PERV_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1 , 0 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT_GENERAL_RESET_1 ); REG32_FLD( PERV_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1 , 1 , SH_UNT_PERV , SH_ACS_FSI0 , @@ -1767,6 +2349,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7 , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_7 ); +REG32_FLD( PERV_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_SET_PORT_ENABLE ); +REG32_FLD( PERV_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE_LEN , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_SET_PORT_ENABLE_LEN ); + +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_SET_PORT_ENABLE ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE_LEN , 8 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_SET_PORT_ENABLE_LEN ); + REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT0_ERROR_CODE ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , @@ -1779,6 +2371,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT0_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT0_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE ); @@ -1792,6 +2394,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT0_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT1_ERROR_CODE ); @@ -1805,6 +2417,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT1_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT1_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE ); @@ -1818,6 +2440,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT1_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT2_ERROR_CODE ); @@ -1831,6 +2463,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT2_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT2_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE ); @@ -1844,6 +2486,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT2_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT3_ERROR_CODE ); @@ -1857,6 +2509,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT3_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT3_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE ); @@ -1870,6 +2532,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT3_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT4_ERROR_CODE ); @@ -1883,6 +2555,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT4_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT4_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE ); @@ -1896,6 +2578,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT4_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT5_ERROR_CODE ); @@ -1909,6 +2601,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT5_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT5_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE ); @@ -1922,6 +2624,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT5_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT6_ERROR_CODE ); @@ -1935,6 +2647,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT6_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT6_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE ); @@ -1948,6 +2670,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT6_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT7_ERROR_CODE ); @@ -1961,6 +2693,16 @@ REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT7_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_PORT7_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE ); @@ -1974,6 +2716,24 @@ REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT7_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); + +REG32_FLD( PERV_FSI_A_MST_1_MAEB_BRIDGE_ERROR , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_BRIDGE_ERROR ); + +REG32_FLD( PERV_FSI_A_MST_1_MCENP0_CLR_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CLR_PORT_ENABLE ); +REG32_FLD( PERV_FSI_A_MST_1_MCENP0_CLR_PORT_ENABLE_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CLR_PORT_ENABLE_LEN ); REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_0_ENABLE , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT_0_ENABLE ); @@ -1996,6 +2756,28 @@ REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR , 0 , SH_UN SH_FLD_FIRST_ERROR ); REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_FIRST_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_CRC_ERROR_COUNT , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_MMODE_PARITY_CHECK , 8 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_MMODE_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_MDLYR_PARITY_CHECK , 9 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_MDLYR_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_MCRSP0_PARITY_CHECK , 10 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_MCRSP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_MENP0_PARITY_CHECK , 11 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_MENP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_MSIEP0_PARITY_CHECK , 12 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_MSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_MSSIEP0_PARITY_CHECK , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_MSSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_REGISTER_ACCESS_FSM_CHECK , 14 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_REGISTER_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_OPB_BUS_ACCESS_FSM_CHECK , 15 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_OPB_BUS_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_REGISTER_ACCESS_ERROR , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_REGISTER_ACCESS_ERROR ); REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST , 17 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_FRST ); REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , @@ -2004,11 +2786,49 @@ REG32_FLD( PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR , 20 , SH_UN SH_FLD_ACTUAL_ERROR ); REG32_FLD( PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_ACTUAL_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_SELECTED_ERROR , 24 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_SELECTED_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MESRB0_SELECTED_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_SELECTED_ERROR_LEN ); REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT , 29 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT ); REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_FAILING_OPB_MASTER_ACT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_0 , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_0 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_2 , 2 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_3 , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_4 , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_5 , 5 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_6 , 6 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_7 , 7 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_0 , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_0 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_2 , 2 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_3 , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_4 , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_5 , 5 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_6 , 6 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_7 , 7 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_LEVEL_7 ); + REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_IPOLL_AND_DMA , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_ENABLE_IPOLL_AND_DMA ); REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_HW_ERROR_RECOVERY , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , @@ -2036,6 +2856,64 @@ REG32_FLD( PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE , 29 , SH_UN REG32_FLD( PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_RECEIVER_MODE_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_0 , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_0 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_0 , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_0 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV , SH_ACS_SCOMFSI0_RO, + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSI_A_MST_1_MRESB0_BRIDGE_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESB0_BRIDGE_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_BRIDGE_ERROR_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESB0_SET_DMA_IRQ_SUSPEND_MODE , 5 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_SET_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSI_A_MST_1_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE , 6 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CLEAR_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSI_A_MST_1_MRESB0_SET_DLY_MEASUREMENT , 7 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_SET_DLY_MEASUREMENT ); + +REG32_FLD( PERV_FSI_A_MST_1_MRESP0_PORT_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESP0_PORT_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_PORT_ERROR_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESP0_ALL_BRIDGE_GENERAL_RESET , 2 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_ALL_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESP0_ALL_PORT_GENERAL_RESET , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_ALL_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESP0_CONTROL_REGISTER_RESET , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CONTROL_REGISTER_RESET ); +REG32_FLD( PERV_FSI_A_MST_1_MRESP0_PARITY_ERROR_RESET , 5 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_PARITY_ERROR_RESET ); + REG32_FLD( PERV_FSI_A_MST_1_MRESP1_PORT_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT_GENERAL_RESET ); REG32_FLD( PERV_FSI_A_MST_1_MRESP1_PORT_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , @@ -2071,6 +2949,11 @@ REG32_FLD( PERV_FSI_A_MST_1_MRESP7_PORT_GENERAL_RESET_7 , 0 , SH_UN REG32_FLD( PERV_FSI_A_MST_1_MRESP7_PORT_ERROR_RESET_7 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT_ERROR_RESET_7 ); +REG32_FLD( PERV_FSI_A_MST_1_MSENP0_SET_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_SET_PORT_ENABLE ); +REG32_FLD( PERV_FSI_A_MST_1_MSENP0_SET_PORT_ENABLE_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_SET_PORT_ENABLE_LEN ); + REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_0 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , @@ -2083,6 +2966,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT0_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT0_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_0 ); @@ -2096,6 +2989,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT1_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT1_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_0 ); @@ -2109,6 +3012,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT2_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT2_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_0 ); @@ -2122,6 +3035,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT3_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT3_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_0 ); @@ -2135,6 +3058,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT4_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT4_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_0 ); @@ -2148,6 +3081,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT5_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT5_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_0 ); @@ -2161,6 +3104,16 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT6_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT6_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0 , 1 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_0 ); @@ -2174,6 +3127,56 @@ REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT7_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , SH_FLD_PORT7_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_SCOMFSI0 , + SH_FLD_HOT_PLUG_FLAG ); + +REG32_FLD( PERV_FSI_A_SDMA_DMA_REQUEST_1_SELECT , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_DMA_REQUEST_1_SELECT ); +REG32_FLD( PERV_FSI_A_SDMA_DMA_REQUEST_1_SELECT_LEN , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_DMA_REQUEST_1_SELECT_LEN ); +REG32_FLD( PERV_FSI_A_SDMA_DMA_REQUEST_2_SELECT , 11 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_DMA_REQUEST_2_SELECT ); +REG32_FLD( PERV_FSI_A_SDMA_DMA_REQUEST_2_SELECT_LEN , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_DMA_REQUEST_2_SELECT_LEN ); +REG32_FLD( PERV_FSI_A_SDMA_CMFSI_PORT_ID_SELECT , 19 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CMFSI_PORT_ID_SELECT ); +REG32_FLD( PERV_FSI_A_SDMA_CMFSI_PORT_ID_SELECT_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CMFSI_PORT_ID_SELECT_LEN ); +REG32_FLD( PERV_FSI_A_SDMA_CMFSI_SLAVE_ID_SELECT , 22 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CMFSI_SLAVE_ID_SELECT ); +REG32_FLD( PERV_FSI_A_SDMA_CMFSI_SLAVE_ID_SELECT_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CMFSI_SLAVE_ID_SELECT_LEN ); +REG32_FLD( PERV_FSI_A_SDMA_MFSI_PORT_ID_SELECT , 27 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MFSI_PORT_ID_SELECT ); +REG32_FLD( PERV_FSI_A_SDMA_MFSI_PORT_ID_SELECT_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MFSI_PORT_ID_SELECT_LEN ); +REG32_FLD( PERV_FSI_A_SDMA_MFSI_SLAVE_ID_SELECT , 30 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MFSI_SLAVE_ID_SELECT ); +REG32_FLD( PERV_FSI_A_SDMA_MFSI_SLAVE_ID_SELECT_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MFSI_SLAVE_ID_SELECT_LEN ); + +REG32_FLD( PERV_FSI_A_SLBUS_FORCE_LBUS_OWNERSHIP , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_FORCE_LBUS_OWNERSHIP ); +REG32_FLD( PERV_FSI_A_SLBUS_REQUEST_LBUS_OWNERSHIP , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_REQUEST_LBUS_OWNERSHIP ); +REG32_FLD( PERV_FSI_A_SLBUS_RELEASE_LBUS_OWNERSHIP , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RELEASE_LBUS_OWNERSHIP ); +REG32_FLD( PERV_FSI_A_SLBUS_RELEASE_LBUS_OWNERSHIP_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RELEASE_LBUS_OWNERSHIP_LEN ); +REG32_FLD( PERV_FSI_A_SLBUS_RESET_LBUS_REQUEST , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_RESET_LBUS_REQUEST ); +REG32_FLD( PERV_FSI_A_SLBUS_LOCK_LBUS_ACCESS , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LOCK_LBUS_ACCESS ); +REG32_FLD( PERV_FSI_A_SLBUS_LOCK_LBUS_ACCESS_LEN , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LOCK_LBUS_ACCESS_LEN ); REG32_FLD( PERV_FSI_A_SMODE_WARM_START_COMPLETED , 0 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_WARM_START_COMPLETED ); @@ -2197,10 +3200,132 @@ REG32_FLD( PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER , 20 , SH_UN SH_FLD_LBUS_CLOCK_DIVIDER ); REG32_FLD( PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , SH_FLD_LBUS_CLOCK_DIVIDER_LEN ); - +REG32_FLD( PERV_FSI_A_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_1 , 28 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_1 ); +REG32_FLD( PERV_FSI_A_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_1_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_1_LEN ); + +REG32_FLD( PERV_FSI_A_SSTAT_ANY_SLV_ERROR , 0 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_ANY_SLV_ERROR ); +REG32_FLD( PERV_FSI_A_SSTAT_ID_DIRTY , 1 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_ID_DIRTY ); +REG32_FLD( PERV_FSI_A_SSTAT_WARM_START_SYNC_FR_LEFT , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_WARM_START_SYNC_FR_LEFT ); +REG32_FLD( PERV_FSI_A_SSTAT_WARM_START_SYNC_FR_RIGHT , 3 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_WARM_START_SYNC_FR_RIGHT ); +REG32_FLD( PERV_FSI_A_SSTAT_MAIL_DELIVERED_TO_LEFT , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MAIL_DELIVERED_TO_LEFT ); +REG32_FLD( PERV_FSI_A_SSTAT_MAIL_DELIVERED_TO_RIGHT , 5 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MAIL_DELIVERED_TO_RIGHT ); +REG32_FLD( PERV_FSI_A_SSTAT_MAIL_RECEIVED_FR_LEFT , 6 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MAIL_RECEIVED_FR_LEFT ); +REG32_FLD( PERV_FSI_A_SSTAT_MAIL_RECEIVED_FR_RIGHT , 7 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_MAIL_RECEIVED_FR_RIGHT ); +REG32_FLD( PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT , 8 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIEFING_DATA_SYNC_FR_LEFT ); +REG32_FLD( PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIEFING_DATA_SYNC_FR_LEFT_LEN ); +REG32_FLD( PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT , 12 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIEFING_DATA_SYNC_FR_RIGHT ); +REG32_FLD( PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_BRIEFING_DATA_SYNC_FR_RIGHT_LEN ); +REG32_FLD( PERV_FSI_A_SSTAT_LBUS_REQ_SYNC_FR_LEFT , 16 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LBUS_REQ_SYNC_FR_LEFT ); +REG32_FLD( PERV_FSI_A_SSTAT_LBUS_REQ_SYNC_FR_RIGHT , 17 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LBUS_REQ_SYNC_FR_RIGHT ); +REG32_FLD( PERV_FSI_A_SSTAT_THIS_LBUS_REQ , 18 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_THIS_LBUS_REQ ); +REG32_FLD( PERV_FSI_A_SSTAT_LBUS_LOCK , 19 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LBUS_LOCK ); +REG32_FLD( PERV_FSI_A_SSTAT_LBUS_GNT , 20 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LBUS_GNT ); +REG32_FLD( PERV_FSI_A_SSTAT_LBUS_GNT_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_LBUS_GNT_LEN ); +REG32_FLD( PERV_FSI_A_SSTAT_THIS_SIDE , 22 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_THIS_SIDE ); +REG32_FLD( PERV_FSI_A_SSTAT_THIS_SIDE_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_THIS_SIDE_LEN ); +REG32_FLD( PERV_FSI_A_SSTAT_OWNERSHIP_FF1 , 24 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_OWNERSHIP_FF1 ); +REG32_FLD( PERV_FSI_A_SSTAT_OWNERSHIP_FF2 , 25 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_OWNERSHIP_FF2 ); +REG32_FLD( PERV_FSI_A_SSTAT_AUX_DI_LEVEL , 26 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_AUX_DI_LEVEL ); +REG32_FLD( PERV_FSI_A_SSTAT_AUX_DI_REFERENCE , 27 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_AUX_DI_REFERENCE ); +REG32_FLD( PERV_FSI_A_SSTAT_CRC_ERR_CTR , 28 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERR_CTR ); +REG32_FLD( PERV_FSI_A_SSTAT_CRC_ERR_CTR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI0 , + SH_FLD_CRC_ERR_CTR_LEN ); + +REG32_FLD( PERV_FSI_B_LLMOD_EXTEND_TIMO , 29 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_EXTEND_TIMO ); +REG32_FLD( PERV_FSI_B_LLMOD_DISABLE_GAP , 30 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_DISABLE_GAP ); REG32_FLD( PERV_FSI_B_LLMOD_ASYNC_MODE , 31 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_ASYNC_MODE ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_0 , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_0 ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_0_LEN , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_0_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_NO_CLK , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_NO_CLK ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_2 , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_2 ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_2_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_2_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_BAD_HANDSHAKE_AT_START , 10 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BAD_HANDSHAKE_AT_START ); +REG32_FLD( PERV_FSI_B_LLSTAT_TIMEOUT , 11 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_TIMEOUT ); +REG32_FLD( PERV_FSI_B_LLSTAT_LBUS_BUSY , 12 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LBUS_BUSY ); +REG32_FLD( PERV_FSI_B_LLSTAT_OPB_BUSY , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_OPB_BUSY ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_3 , 14 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_3 ); +REG32_FLD( PERV_FSI_B_LLSTAT_BREAK_PENDING , 15 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BREAK_PENDING ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_4 , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_4 ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_4_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_4_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_HANDSHAKE_STATE , 18 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HANDSHAKE_STATE ); +REG32_FLD( PERV_FSI_B_LLSTAT_HANDSHAKE_STATE_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HANDSHAKE_STATE_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_CFAM_CYCLE_TIME , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CFAM_CYCLE_TIME ); +REG32_FLD( PERV_FSI_B_LLSTAT_CFAM_CYCLE_TIME_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CFAM_CYCLE_TIME_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_REFCLOCK_STATUS , 24 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_REFCLOCK_STATUS ); +REG32_FLD( PERV_FSI_B_LLSTAT_REFCLOCK_STATUS_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_REFCLOCK_STATUS_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_5 , 28 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_5 ); +REG32_FLD( PERV_FSI_B_LLSTAT_RESERVED_5_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESERVED_5_LEN ); +REG32_FLD( PERV_FSI_B_LLSTAT_ASYNC_MODE , 31 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_ASYNC_MODE ); + +REG32_FLD( PERV_FSI_B_MST_0_MAEB_BRIDGE_ERROR , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIDGE_ERROR ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MAEB_BRIDGE_ERROR , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_BRIDGE_ERROR ); + +REG32_FLD( PERV_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CLR_PORT_ENABLE ); +REG32_FLD( PERV_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE_LEN , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CLR_PORT_ENABLE_LEN ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CLR_PORT_ENABLE ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE_LEN , 8 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CLR_PORT_ENABLE_LEN ); + REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT_ENABLE ); REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_1_ENABLE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , @@ -2239,6 +3364,28 @@ REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR , 0 , SH_UN SH_FLD_FIRST_ERROR ); REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_FIRST_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_MMODE_PARITY_CHECK , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MMODE_PARITY_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_MDLYR_PARITY_CHECK , 9 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MDLYR_PARITY_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_MCRSP0_PARITY_CHECK , 10 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MCRSP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_MENP0_PARITY_CHECK , 11 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MENP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_MSIEP0_PARITY_CHECK , 12 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_MSSIEP0_PARITY_CHECK , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MSSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK , 14 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_REGISTER_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK , 15 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_OPB_BUS_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_ERROR , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_REGISTER_ACCESS_ERROR ); REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_FAILING_OPB_MASTER_FRST ); REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , @@ -2247,6 +3394,10 @@ REG32_FLD( PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR , 20 , SH_UN SH_FLD_ACTUAL_ERROR ); REG32_FLD( PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_ACTUAL_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_SELECTED_ERROR , 24 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_SELECTED_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MESRB0_SELECTED_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_SELECTED_ERROR_LEN ); REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_FAILING_OPB_MASTER_ACT ); REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , @@ -2256,6 +3407,28 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR , 0 , SH_UN SH_FLD_FIRST_ERROR ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FIRST_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MMODE_PARITY_CHECK , 8 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_MMODE_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MDLYR_PARITY_CHECK , 9 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_MDLYR_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MCRSP0_PARITY_CHECK , 10 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_MCRSP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MENP0_PARITY_CHECK , 11 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_MENP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MSIEP0_PARITY_CHECK , 12 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_MSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MSSIEP0_PARITY_CHECK , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_MSSIEP0_PARITY_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK , 14 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_REGISTER_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK , 15 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_OPB_BUS_ACCESS_FSM_CHECK ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_ERROR , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_REGISTER_ACCESS_ERROR ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_FRST ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , @@ -2264,11 +3437,83 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR , 20 , SH_UN SH_FLD_ACTUAL_ERROR ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_ACTUAL_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_SELECTED_ERROR , 24 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_SELECTED_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_SELECTED_ERROR_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_SELECTED_ERROR_LEN ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_ACT ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_FAILING_OPB_MASTER_ACT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_1 , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_2 , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_3 , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_4 , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_5 , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_6 , 6 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_7 , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_1 , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_2 , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_3 , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_4 , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_5 , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_6 , 6 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_7 , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_LEVEL_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_LEVEL_7 ); + REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA , 0 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_ENABLE_IPOLL_AND_DMA ); REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY , 1 , SH_UNT_PERV , SH_ACS_FSI1 , @@ -2323,6 +3568,122 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE , 29 , SH_UN REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_RECEIVER_MODE_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_1 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_1 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_2 , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_2 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_3 , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_3 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_4 , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_4 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_5 , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_5 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_6 , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_6 ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_7 , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1_RO, + SH_FLD_PORT_HOT_PLUG_7 ); + +REG32_FLD( PERV_FSI_B_MST_0_MRESB0_BRIDGE_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESB0_BRIDGE_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIDGE_ERROR_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_SET_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSI_B_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE , 6 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CLEAR_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSI_B_MST_0_MRESB0_SET_DLY_MEASUREMENT , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_SET_DLY_MEASUREMENT ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESB0_BRIDGE_GENERAL_RESET , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESB0_BRIDGE_ERROR_RESET , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_BRIDGE_ERROR_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_SET_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE , 6 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CLEAR_DMA_IRQ_SUSPEND_MODE ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESB0_SET_DLY_MEASUREMENT , 7 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_SET_DLY_MEASUREMENT ); + +REG32_FLD( PERV_FSI_B_MST_0_MRESP0_PORT_GENERAL_RESET , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESP0_PORT_ERROR_RESET , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PORT_ERROR_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_ALL_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESP0_ALL_PORT_GENERAL_RESET , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_ALL_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESP0_CONTROL_REGISTER_RESET , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CONTROL_REGISTER_RESET ); +REG32_FLD( PERV_FSI_B_MST_0_MRESP0_PARITY_ERROR_RESET , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_PARITY_ERROR_RESET ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP0_PORT_GENERAL_RESET , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP0_PORT_ERROR_RESET , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_PORT_ERROR_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET , 2 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_ALL_BRIDGE_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP0_ALL_PORT_GENERAL_RESET , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_ALL_PORT_GENERAL_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP0_CONTROL_REGISTER_RESET , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CONTROL_REGISTER_RESET ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP0_PARITY_ERROR_RESET , 5 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_PARITY_ERROR_RESET ); + REG32_FLD( PERV_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1 , 0 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT_GENERAL_RESET_1 ); REG32_FLD( PERV_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1 , 1 , SH_UNT_PERV , SH_ACS_FSI1 , @@ -2393,6 +3754,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7 , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7 , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT_ERROR_RESET_7 ); +REG32_FLD( PERV_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_SET_PORT_ENABLE ); +REG32_FLD( PERV_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE_LEN , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_SET_PORT_ENABLE_LEN ); + +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_SET_PORT_ENABLE ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE_LEN , 8 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_SET_PORT_ENABLE_LEN ); + REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT0_ERROR_CODE ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , @@ -2405,6 +3776,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT0_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT0_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE ); @@ -2418,6 +3799,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT0_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT0_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT1_ERROR_CODE ); @@ -2431,6 +3822,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT1_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT1_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE ); @@ -2444,6 +3845,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT1_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT1_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT2_ERROR_CODE ); @@ -2457,6 +3868,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT2_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT2_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE ); @@ -2470,6 +3891,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT2_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT2_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT3_ERROR_CODE ); @@ -2483,6 +3914,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT3_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT3_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE ); @@ -2496,6 +3937,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT3_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT3_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT4_ERROR_CODE ); @@ -2509,6 +3960,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT4_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT4_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE ); @@ -2522,6 +3983,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT4_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT4_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT5_ERROR_CODE ); @@ -2535,6 +4006,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT5_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT5_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE ); @@ -2548,6 +4029,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT5_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT5_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT6_ERROR_CODE ); @@ -2561,6 +4052,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT6_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT6_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE ); @@ -2574,6 +4075,16 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT6_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT6_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE , 1 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT7_ERROR_CODE ); @@ -2587,6 +4098,16 @@ REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT7_ERROR_CODE_2 ); REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_PORT7_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_FOURTH_ERROR , 13 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_HOT_PLUG_FLAG , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_HOT_PLUG_FLAG ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE , 1 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE ); @@ -2600,6 +4121,56 @@ REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2 , 9 , SH_UN SH_FLD_PORT7_ERROR_CODE_2 ); REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , SH_FLD_PORT7_ERROR_CODE_2_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_FOURTH_ERROR , 13 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_FOURTH_ERROR_LEN , 3 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_FOURTH_ERROR_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT , 16 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_CRC_ERROR_COUNT_LEN ); +REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_HOT_PLUG_FLAG , 20 , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 , + SH_FLD_HOT_PLUG_FLAG ); + +REG32_FLD( PERV_FSI_B_SDMA_DMA_REQUEST_1_SELECT , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_DMA_REQUEST_1_SELECT ); +REG32_FLD( PERV_FSI_B_SDMA_DMA_REQUEST_1_SELECT_LEN , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_DMA_REQUEST_1_SELECT_LEN ); +REG32_FLD( PERV_FSI_B_SDMA_DMA_REQUEST_2_SELECT , 11 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_DMA_REQUEST_2_SELECT ); +REG32_FLD( PERV_FSI_B_SDMA_DMA_REQUEST_2_SELECT_LEN , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_DMA_REQUEST_2_SELECT_LEN ); +REG32_FLD( PERV_FSI_B_SDMA_CMFSI_PORT_ID_SELECT , 19 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CMFSI_PORT_ID_SELECT ); +REG32_FLD( PERV_FSI_B_SDMA_CMFSI_PORT_ID_SELECT_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CMFSI_PORT_ID_SELECT_LEN ); +REG32_FLD( PERV_FSI_B_SDMA_CMFSI_SLAVE_ID_SELECT , 22 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CMFSI_SLAVE_ID_SELECT ); +REG32_FLD( PERV_FSI_B_SDMA_CMFSI_SLAVE_ID_SELECT_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CMFSI_SLAVE_ID_SELECT_LEN ); +REG32_FLD( PERV_FSI_B_SDMA_MFSI_PORT_ID_SELECT , 27 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MFSI_PORT_ID_SELECT ); +REG32_FLD( PERV_FSI_B_SDMA_MFSI_PORT_ID_SELECT_LEN , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MFSI_PORT_ID_SELECT_LEN ); +REG32_FLD( PERV_FSI_B_SDMA_MFSI_SLAVE_ID_SELECT , 30 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MFSI_SLAVE_ID_SELECT ); +REG32_FLD( PERV_FSI_B_SDMA_MFSI_SLAVE_ID_SELECT_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MFSI_SLAVE_ID_SELECT_LEN ); + +REG32_FLD( PERV_FSI_B_SLBUS_FORCE_LBUS_OWNERSHIP , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_FORCE_LBUS_OWNERSHIP ); +REG32_FLD( PERV_FSI_B_SLBUS_REQUEST_LBUS_OWNERSHIP , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_REQUEST_LBUS_OWNERSHIP ); +REG32_FLD( PERV_FSI_B_SLBUS_RELEASE_LBUS_OWNERSHIP , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RELEASE_LBUS_OWNERSHIP ); +REG32_FLD( PERV_FSI_B_SLBUS_RELEASE_LBUS_OWNERSHIP_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RELEASE_LBUS_OWNERSHIP_LEN ); +REG32_FLD( PERV_FSI_B_SLBUS_RESET_LBUS_REQUEST , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_RESET_LBUS_REQUEST ); +REG32_FLD( PERV_FSI_B_SLBUS_LOCK_LBUS_ACCESS , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LOCK_LBUS_ACCESS ); +REG32_FLD( PERV_FSI_B_SLBUS_LOCK_LBUS_ACCESS_LEN , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LOCK_LBUS_ACCESS_LEN ); REG32_FLD( PERV_FSI_B_SMODE_WARM_START_COMPLETED , 0 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_WARM_START_COMPLETED ); @@ -2623,6 +4194,63 @@ REG32_FLD( PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER , 20 , SH_UN SH_FLD_LBUS_CLOCK_DIVIDER ); REG32_FLD( PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , SH_FLD_LBUS_CLOCK_DIVIDER_LEN ); +REG32_FLD( PERV_FSI_B_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_0 , 24 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_0 ); +REG32_FLD( PERV_FSI_B_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_0_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_0_LEN ); + +REG32_FLD( PERV_FSI_B_SSTAT_ANY_SLV_ERROR , 0 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_ANY_SLV_ERROR ); +REG32_FLD( PERV_FSI_B_SSTAT_ID_DIRTY , 1 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_ID_DIRTY ); +REG32_FLD( PERV_FSI_B_SSTAT_WARM_START_SYNC_FR_LEFT , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_WARM_START_SYNC_FR_LEFT ); +REG32_FLD( PERV_FSI_B_SSTAT_WARM_START_SYNC_FR_RIGHT , 3 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_WARM_START_SYNC_FR_RIGHT ); +REG32_FLD( PERV_FSI_B_SSTAT_MAIL_DELIVERED_TO_LEFT , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MAIL_DELIVERED_TO_LEFT ); +REG32_FLD( PERV_FSI_B_SSTAT_MAIL_DELIVERED_TO_RIGHT , 5 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MAIL_DELIVERED_TO_RIGHT ); +REG32_FLD( PERV_FSI_B_SSTAT_MAIL_RECEIVED_FR_LEFT , 6 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MAIL_RECEIVED_FR_LEFT ); +REG32_FLD( PERV_FSI_B_SSTAT_MAIL_RECEIVED_FR_RIGHT , 7 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_MAIL_RECEIVED_FR_RIGHT ); +REG32_FLD( PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT , 8 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIEFING_DATA_SYNC_FR_LEFT ); +REG32_FLD( PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIEFING_DATA_SYNC_FR_LEFT_LEN ); +REG32_FLD( PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT , 12 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIEFING_DATA_SYNC_FR_RIGHT ); +REG32_FLD( PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_BRIEFING_DATA_SYNC_FR_RIGHT_LEN ); +REG32_FLD( PERV_FSI_B_SSTAT_LBUS_REQ_SYNC_FR_LEFT , 16 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LBUS_REQ_SYNC_FR_LEFT ); +REG32_FLD( PERV_FSI_B_SSTAT_LBUS_REQ_SYNC_FR_RIGHT , 17 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LBUS_REQ_SYNC_FR_RIGHT ); +REG32_FLD( PERV_FSI_B_SSTAT_THIS_LBUS_REQ , 18 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_THIS_LBUS_REQ ); +REG32_FLD( PERV_FSI_B_SSTAT_LBUS_LOCK , 19 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LBUS_LOCK ); +REG32_FLD( PERV_FSI_B_SSTAT_LBUS_GNT , 20 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LBUS_GNT ); +REG32_FLD( PERV_FSI_B_SSTAT_LBUS_GNT_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_LBUS_GNT_LEN ); +REG32_FLD( PERV_FSI_B_SSTAT_THIS_SIDE , 22 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_THIS_SIDE ); +REG32_FLD( PERV_FSI_B_SSTAT_THIS_SIDE_LEN , 2 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_THIS_SIDE_LEN ); +REG32_FLD( PERV_FSI_B_SSTAT_OWNERSHIP_FF1 , 24 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_OWNERSHIP_FF1 ); +REG32_FLD( PERV_FSI_B_SSTAT_OWNERSHIP_FF2 , 25 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_OWNERSHIP_FF2 ); +REG32_FLD( PERV_FSI_B_SSTAT_AUX_DI_LEVEL , 26 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_AUX_DI_LEVEL ); +REG32_FLD( PERV_FSI_B_SSTAT_AUX_DI_REFERENCE , 27 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_AUX_DI_REFERENCE ); +REG32_FLD( PERV_FSI_B_SSTAT_CRC_ERR_CTR , 28 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERR_CTR ); +REG32_FLD( PERV_FSI_B_SSTAT_CRC_ERR_CTR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI1 , + SH_FLD_CRC_ERR_CTR_LEN ); REG64_FLD( PERV_GPWRP_MAGIC_COOKIE , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MAGIC_COOKIE ); @@ -3067,6 +4695,30 @@ REG64_FLD( PERV_IODA_XLT_EA_IDIAL_RSVD0 , 50 , SH_UN REG64_FLD( PERV_IODA_XLT_EA_IDIAL_RSVD0_LEN , 14 , SH_UNT_PERV , SH_ACS_IODA , SH_FLD_IDIAL_RSVD0_LEN ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_START_CAL , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_START_CAL ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_DATA_SEL , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_DATA_SEL ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_BYPASS , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_BYPASS ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_MEASURE , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MEASURE ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_MAX , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MAX ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_MIN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MIN ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_CAL_DONE , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CAL_DONE ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_TIMEOUT , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT ); +REG64_FLD( PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_RESULT_VALID , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESULT_VALID ); + +REG64_FLD( PERV_1_KVREF_TUNE_DATA_FMU_KVREF_TUNE_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_FMU_KVREF_TUNE_DATA ); +REG64_FLD( PERV_1_KVREF_TUNE_DATA_FMU_KVREF_TUNE_DATA_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_FMU_KVREF_TUNE_DATA_LEN ); + REG64_FLD( PERV_1_LOCAL_FIR_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN0 ); REG64_FLD( PERV_1_LOCAL_FIR_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , @@ -3219,6 +4871,326 @@ REG64_FLD( PERV_1_LOCAL_XSTOP_MASK_IN , 0 , SH_UN REG64_FLD( PERV_1_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN_LEN ); +REG64_FLD( PERV_M1A_DATA_AREA_0_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_0_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_1_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_1_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_10_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_10_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_11_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_11_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_12_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_12_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_13_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_13_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_14_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_14_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_15_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_15_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_2_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_2_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_3_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_3_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_4_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_4_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_5_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_5_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_6_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_6_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_7_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_7_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_8_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_8_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1A_DATA_AREA_9_MDA_M1A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA ); +REG64_FLD( PERV_M1A_DATA_AREA_9_MDA_M1A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_0_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_0_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_1_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_1_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_10_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_10_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_11_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_11_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_12_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_12_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_13_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_13_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_14_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_14_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_15_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_15_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_2_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_2_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_3_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_3_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_4_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_4_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_5_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_5_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_6_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_6_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_7_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_7_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_8_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_8_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M1B_DATA_AREA_9_MDA_M1B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA ); +REG64_FLD( PERV_M1B_DATA_AREA_9_MDA_M1B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M1B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_0_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_0_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_1_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_1_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_10_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_10_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_11_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_11_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_12_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_12_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_13_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_13_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_14_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_14_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_15_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_15_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_2_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_2_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_3_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_3_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_4_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_4_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_5_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_5_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_6_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_6_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_7_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_7_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_8_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_8_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2A_DATA_AREA_9_MDA_M2A_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA ); +REG64_FLD( PERV_M2A_DATA_AREA_9_MDA_M2A_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2A_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_0_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_0_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_1_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_1_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_10_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_10_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_11_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_11_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_12_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_12_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_13_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_13_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_14_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_14_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_15_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_15_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_2_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_2_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_3_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_3_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_4_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_4_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_5_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_5_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_6_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_6_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_7_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_7_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_8_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_8_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + +REG64_FLD( PERV_M2B_DATA_AREA_9_MDA_M2B_DATA_AREA , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA ); +REG64_FLD( PERV_M2B_DATA_AREA_9_MDA_M2B_DATA_AREA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MDA_M2B_DATA_AREA_LEN ); + REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A , 0 , SH_UNT_PERV , SH_ACS_SCOM_RW , SH_FLD_M1HC0A ); REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM_RW , @@ -3381,6 +5353,10 @@ REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARI REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_2 , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDES_CLEAR_2 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_ABORT_MAILBOX_2 , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_ABORT_MAILBOX_2 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_ABORT_MAILBOX_1 , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_ABORT_MAILBOX_1 ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_2 , 26 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDI_LBUS_ERROR_2 ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_1 , 27 , SH_UNT_PERV , SH_ACS_SCOM , @@ -3571,10 +5547,8 @@ REG64_FLD( PERV_1_NET_CTRL0_CPLT_RCTRL , 19 , SH_UN SH_FLD_CPLT_RCTRL ); REG64_FLD( PERV_1_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); -REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE0 ); -REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( PERV_1_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( PERV_1_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( PERV_1_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, @@ -3585,6 +5559,8 @@ REG64_FLD( PERV_1_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( PERV_1_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( PERV_1_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_PM_ACCESS ); REG64_FLD( PERV_1_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); @@ -3626,6 +5602,10 @@ REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UN SH_FLD_CLK_PULSE_MODE ); REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); +REG64_FLD( PERV_1_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS ); +REG64_FLD( PERV_1_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, SH_FLD_SRAM_CERRRPT ); @@ -4189,8 +6169,8 @@ REG64_FLD( PERV_1_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UN SH_FLD_MISR_INIT_WAIT ); REG64_FLD( PERV_1_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); -REG64_FLD( PERV_1_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( PERV_1_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( PERV_1_OPCG_REG1_UNUSED2 , 50 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -4400,8 +6380,8 @@ REG64_FLD( PERV_PERV_CTRL0_29_RESERVED_FOR_HTB , 29 , SH_UN SH_FLD_29_RESERVED_FOR_HTB ); REG64_FLD( PERV_PERV_CTRL0_30_RESERVED_FOR_HTB , 30 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_30_RESERVED_FOR_HTB ); -REG64_FLD( PERV_PERV_CTRL0_31_RESERVED_FOR_HTB , 31 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_31_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_TP_PLLCHIPLET_FORCE_OUT_EN_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLCHIPLET_FORCE_OUT_EN_DC ); REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_CHIPLET_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_CHIPLET_EN_DC ); @@ -4465,8 +6445,13 @@ REG64_FLD( PERV_PERV_CTRL0_CLEAR_29_RESERVED_FOR_HTB , 29 , SH_UN SH_FLD_29_RESERVED_FOR_HTB ); REG64_FLD( PERV_PERV_CTRL0_CLEAR_30_RESERVED_FOR_HTB , 30 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_30_RESERVED_FOR_HTB ); -REG64_FLD( PERV_PERV_CTRL0_CLEAR_31_RESERVED_FOR_HTB , 31 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_31_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLLCHIPLET_FORCE_OUT_EN_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLCHIPLET_FORCE_OUT_EN_DC ); + +REG64_FLD( PERV_PERV_CTRL0_COPY_PERV_CTRL0_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PERV_CTRL0_COPY_REG ); +REG64_FLD( PERV_PERV_CTRL0_COPY_PERV_CTRL0_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PERV_CTRL0_COPY_REG_LEN ); REG64_FLD( PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_CHIPLET_EN_DC ); @@ -4530,15 +6515,15 @@ REG64_FLD( PERV_PERV_CTRL0_SET_29_RESERVED_FOR_HTB , 29 , SH_UN SH_FLD_29_RESERVED_FOR_HTB ); REG64_FLD( PERV_PERV_CTRL0_SET_30_RESERVED_FOR_HTB , 30 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_30_RESERVED_FOR_HTB ); -REG64_FLD( PERV_PERV_CTRL0_SET_31_RESERVED_FOR_HTB , 31 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_31_RESERVED_FOR_HTB ); - -REG64_FLD( PERV_PERV_CTRL1_UNUSED1 , 0 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED1 ); -REG64_FLD( PERV_PERV_CTRL1_UNUSED2 , 1 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED2 ); -REG64_FLD( PERV_PERV_CTRL1_UNUSED3 , 2 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED3 ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLLCHIPLET_FORCE_OUT_EN_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLCHIPLET_FORCE_OUT_EN_DC ); + +REG64_FLD( PERV_PERV_CTRL1_TP_CHIPLET_PLL_CLKIN_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_PLL_CLKIN_SEL_DC ); +REG64_FLD( PERV_PERV_CTRL1_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC ); +REG64_FLD( PERV_PERV_CTRL1_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC ); REG64_FLD( PERV_PERV_CTRL1_3_RESERVED , 3 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_3_RESERVED ); REG64_FLD( PERV_PERV_CTRL1_4_RESERVED , 4 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4594,12 +6579,12 @@ REG64_FLD( PERV_PERV_CTRL1_30_RESERVED , 30 , SH_UN REG64_FLD( PERV_PERV_CTRL1_TP_PCB_PM_MUX_SEL_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PCB_PM_MUX_SEL_DC ); -REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED1 , 0 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED1 ); -REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED2 , 1 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED2 ); -REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED3 , 2 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED3 ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CHIPLET_PLL_CLKIN_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_PLL_CLKIN_SEL_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC ); REG64_FLD( PERV_PERV_CTRL1_CLEAR_3_RESERVED , 3 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_3_RESERVED ); REG64_FLD( PERV_PERV_CTRL1_CLEAR_4_RESERVED , 4 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4655,12 +6640,17 @@ REG64_FLD( PERV_PERV_CTRL1_CLEAR_30_RESERVED , 30 , SH_UN REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_PCB_PM_MUX_SEL_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PCB_PM_MUX_SEL_DC ); -REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED1 , 0 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED1 ); -REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED2 , 1 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED2 ); -REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED3 , 2 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_UNUSED3 ); +REG64_FLD( PERV_PERV_CTRL1_COPY_PERV_CTRL1_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PERV_CTRL1_COPY_REG ); +REG64_FLD( PERV_PERV_CTRL1_COPY_PERV_CTRL1_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PERV_CTRL1_COPY_REG_LEN ); + +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CHIPLET_PLL_CLKIN_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_PLL_CLKIN_SEL_DC ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC ); REG64_FLD( PERV_PERV_CTRL1_SET_3_RESERVED , 3 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_3_RESERVED ); REG64_FLD( PERV_PERV_CTRL1_SET_4_RESERVED , 4 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4716,11 +6706,21 @@ REG64_FLD( PERV_PERV_CTRL1_SET_30_RESERVED , 30 , SH_UN REG64_FLD( PERV_PERV_CTRL1_SET_TP_PCB_PM_MUX_SEL_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PCB_PM_MUX_SEL_DC ); +REG64_FLD( PERV_1_PLL_LOCK_REG_LOCK , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_LOCK ); +REG64_FLD( PERV_1_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_LOCK_LEN ); + REG64_FLD( PERV_1_PRE_COUNTER_REG_COUNTER , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_COUNTER ); REG64_FLD( PERV_1_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_COUNTER_LEN ); +REG64_FLD( PERV_1_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS ); +REG64_FLD( PERV_1_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS_LEN ); + REG64_FLD( PERV_1_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( PERV_1_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -4864,6 +6864,9 @@ REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN ); +REG64_FLD( PERV_1_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RECOV ); + REG64_FLD( PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER ); REG64_FLD( PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER_LEN , 64 , SH_UNT_PERV , SH_ACS_SCOM , @@ -5312,8 +7315,6 @@ REG64_FLD( PERV_1_RFIR_IN21 , 19 , SH_UN REG64_FLD( PERV_1_RFIR_IN21_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN21_LEN ); -REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -5441,6 +7442,11 @@ REG64_FLD( PERV_ROOT_CTRL0_CLEAR_PCB_RESET_DC , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL0_CLEAR_GLOBAL_EP_RESET_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_GLOBAL_EP_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL0_COPY_ROOT_CTRL0_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL0_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL0_COPY_ROOT_CTRL0_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL0_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_FENCE0_DC ); REG64_FLD( PERV_ROOT_CTRL0_SET_TPFSI_TP_FENCE_VTLIO_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -5616,6 +7622,11 @@ REG64_FLD( PERV_ROOT_CTRL1_CLEAR_30_SPARE_TEST_CONTROL , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL1_CLEAR_31_SPARE_TEST_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_COPY_ROOT_CTRL1_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL1_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL1_COPY_ROOT_CTRL1_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL1_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PROBE0_SEL_DC ); REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , @@ -5799,6 +7810,11 @@ REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP3A_V1P8_EN , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP3B_V1P8_EN , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_IO_VSB_OP3B_V1P8_EN ); +REG64_FLD( PERV_ROOT_CTRL2_COPY_ROOT_CTRL2_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL2_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL2_COPY_ROOT_CTRL2_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL2_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC ); REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -5896,6 +7912,11 @@ REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC , 24 , SH_UN REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_OSCSWITCH_CNTL1_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_COPY_ROOT_CTRL3_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL3_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL3_COPY_ROOT_CTRL3_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL3_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_OSCSWITCH_CNTL0_DC ); REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM , @@ -5923,6 +7944,11 @@ REG64_FLD( PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB , 0 , SH_UN REG64_FLD( PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_OSCSWITCH_VSB_LEN ); +REG64_FLD( PERV_ROOT_CTRL4_COPY_ROOT_CTRL4_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL4_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL4_COPY_ROOT_CTRL4_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL4_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_OSCSWITCH_VSB ); REG64_FLD( PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , @@ -6038,6 +8064,11 @@ REG64_FLD( PERV_ROOT_CTRL5_CLEAR_30_SPARE_OSC , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL5_CLEAR_31_SPARE_OSC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_COPY_ROOT_CTRL5_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL5_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL5_COPY_ROOT_CTRL5_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL5_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_OSCSW_ERRINJ0_DC ); REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , @@ -6183,6 +8214,11 @@ REG64_FLD( PERV_ROOT_CTRL6_CLEAR_30_SPARE_REFCLOCK_CONTROL , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL6_CLEAR_31_SPARE_REFCLOCK_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_COPY_ROOT_CTRL6_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL6_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL6_COPY_ROOT_CTRL6_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL6_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC ); REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , @@ -6358,6 +8394,11 @@ REG64_FLD( PERV_ROOT_CTRL7_CLEAR_30_SPARE_RESONANT_CLOCKING_CONTROL , 30 , SH_U REG64_FLD( PERV_ROOT_CTRL7_CLEAR_31_SPARE_RESONANT_CLOCKING_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_COPY_ROOT_CTRL7_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL7_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL7_COPY_ROOT_CTRL7_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL7_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL7_SET_0_SPARE_SECTOR_BUFFER_CONTROL , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL ); REG64_FLD( PERV_ROOT_CTRL7_SET_1_SPARE_SECTOR_BUFFER_CONTROL , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -6553,6 +8594,11 @@ REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL3_DC , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL4_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PLL_CLKIN_SEL4_DC ); +REG64_FLD( PERV_ROOT_CTRL8_COPY_ROOT_CTRL8_COPY_REG , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL8_COPY_REG ); +REG64_FLD( PERV_ROOT_CTRL8_COPY_ROOT_CTRL8_COPY_REG_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_ROOT_CTRL8_COPY_REG_LEN ); + REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_SS0_PLL_RESET ); REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -6624,27 +8670,35 @@ REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PERV , SH_ACS_PPE , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PERV_SBE_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PERV_SBE_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PERV_SBE_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PERV_SBE_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PERV_SBE_LCL_DBG_HTM_TRACE_MODE , 7 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_HTM_TRACE_MODE ); -REG64_FLD( PERV_SBE_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PERV_SBE_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PERV_SBE_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PERV , SH_ACS_PPE , +REG64_FLD( PERV_SBE_LCL_DBG_RESERVED3 , 3 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_RESERVED3 ); +REG64_FLD( PERV_SBE_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PERV_SBE_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PERV_SBE_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PERV_SBE_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PERV_SBE_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PERV_SBE_LCL_DBG_RESERVED9 , 9 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_RESERVED9 ); +REG64_FLD( PERV_SBE_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PERV_SBE_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PERV_SBE_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PERV , SH_ACS_PPE , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PERV , SH_ACS_PPE , +REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PERV , SH_ACS_PPE , SH_FLD_MIB_GPIO ); REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PERV , SH_ACS_PPE , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PERV_SBE_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PERV , SH_ACS_PPE , +REG64_FLD( PERV_SBE_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PERV_SBE_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( PERV_SBE_LCL_DBG_HALT_INPUT , 24 , SH_UNT_PERV , SH_ACS_PPE , SH_FLD_HALT_INPUT ); REG64_FLD( PERV_SBE_LCL_EIMR_START0 , 0 , SH_UNT_PERV , SH_ACS_PPE2 , @@ -6731,6 +8785,11 @@ REG64_FLD( PERV_SBE_LCL_EISR_TRIG , 8 , SH_UN REG64_FLD( PERV_SBE_LCL_EISR_XSTOP , 9 , SH_UNT_PERV , SH_ACS_PPE2 , SH_FLD_XSTOP ); +REG64_FLD( PERV_SBE_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( PERV_SBE_LCL_EISTR_INTERRUPT_STATUS_LEN , 10 , SH_UNT_PERV , SH_ACS_PPE , + SH_FLD_INTERRUPT_STATUS_LEN ); + REG64_FLD( PERV_SBE_LCL_EITR_START0 , 0 , SH_UNT_PERV , SH_ACS_PPE2 , SH_FLD_START0 ); REG64_FLD( PERV_SBE_LCL_EITR_START1 , 1 , SH_UNT_PERV , SH_ACS_PPE2 , @@ -6941,13 +9000,13 @@ REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UN SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); -REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); -REG64_FLD( PERV_SNS1LTH_SNS1_UNUSED_0_31 , 0 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_SNS1_UNUSED_0_31 ); -REG64_FLD( PERV_SNS1LTH_SNS1_UNUSED_0_31_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_SNS1_UNUSED_0_31_LEN ); +REG64_FLD( PERV_SNS1LTH_SNS1_0_31 , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SNS1_0_31 ); +REG64_FLD( PERV_SNS1LTH_SNS1_0_31_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SNS1_0_31_LEN ); REG64_FLD( PERV_SNS2LTH_SNS2_UNUSED_0_31 , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_SNS2_UNUSED_0_31 ); @@ -7065,6 +9124,8 @@ REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0 , 28 , SH_UN REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0_LEN , 4 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_0_LEN ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_ANY_ERROR , 0 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_ANY_ERROR ); REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CMD_PARITY_ERROR , 1 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , SH_FLD_CMD_PARITY_ERROR ); REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR , 2 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , @@ -7075,9 +9136,55 @@ REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR , 4 , SH_UN SH_FLD_LCK_STATUS_PARITY_ERROR ); REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_FSM_PARITY_ERROR , 5 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , SH_FLD_FSM_PARITY_ERROR ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_COMMAND_OVERRUN_ERROR , 7 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_OPB_COMMAND_OVERRUN_ERROR ); REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_PARITY_ERROR , 8 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , SH_FLD_OPB_PARITY_ERROR ); - +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_PROTOCOL_ERROR , 9 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_OPB_PROTOCOL_ERROR ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_TIMEOUT_BIT , 10 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_OPB_TIMEOUT_BIT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_ERRACK , 11 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_OPB_ERRACK ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_INVALID_ADDRESS , 12 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_INVALID_ADDRESS ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_PORT_IS_FENCED , 13 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_PORT_IS_FENCED ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_READ_DATA_VALID , 14 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_READ_DATA_VALID ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_BUSY_FLAG , 15 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_OPB_BUSY_FLAG ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_MASTER_ERROR , 16 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_MASTER_ERROR ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_PORT_INTERRUPT , 17 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_PORT_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_HOT_PLUG_EVENT , 18 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_CM_HOT_PLUG_EVENT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_CONTROL_REGISTER_PARITY_INTERRUPT , 19 , SH_UNT_PERV_PIB2OPB1, + SH_ACS_SCOM_RO , SH_FLD_CM_CONTROL_REGISTER_PARITY_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT , 20 , SH_UNT_PERV_PIB2OPB1, + SH_ACS_SCOM_RO , SH_FLD_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT , 21 , SH_UNT_PERV_PIB2OPB1, + SH_ACS_SCOM_RO , SH_FLD_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_MASTER_ERROR , 24 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_M_ANY_MASTER_ERROR ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_PORT_INTERRUPT , 25 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_M_ANY_PORT_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_HOT_PLUG_EVENT , 26 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_M_HOT_PLUG_EVENT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_CONTROL_REGISTER_PARITY_INTERRUPT , 27 , SH_UNT_PERV_PIB2OPB1, + SH_ACS_SCOM_RO , SH_FLD_M_CONTROL_REGISTER_PARITY_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT , 28 , SH_UNT_PERV_PIB2OPB1, + SH_ACS_SCOM_RO , SH_FLD_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT , 29 , SH_UNT_PERV_PIB2OPB1, + SH_ACS_SCOM_RO , SH_FLD_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_READ_DATA , 32 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_READ_DATA ); +REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_READ_DATA_LEN , 32 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , + SH_FLD_READ_DATA_LEN ); + +REG64_FLD( PERV_STAT_RDDAT_ERRES_ANY_ERROR , 0 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_ANY_ERROR ); REG64_FLD( PERV_STAT_RDDAT_ERRES_CMD_PARITY_ERROR , 1 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_CMD_PARITY_ERROR ); REG64_FLD( PERV_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR , 2 , SH_UNT_PERV , SH_ACS_SCOM_RO , @@ -7088,9 +9195,55 @@ REG64_FLD( PERV_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR , 4 , SH_UN SH_FLD_LCK_STATUS_PARITY_ERROR ); REG64_FLD( PERV_STAT_RDDAT_ERRES_FSM_PARITY_ERROR , 5 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_FSM_PARITY_ERROR ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_COMMAND_OVERRUN_ERROR , 7 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_OPB_COMMAND_OVERRUN_ERROR ); REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_PARITY_ERROR , 8 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_OPB_PARITY_ERROR ); - +REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_PROTOCOL_ERROR , 9 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_OPB_PROTOCOL_ERROR ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_TIMEOUT_BIT , 10 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_OPB_TIMEOUT_BIT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_ERRACK , 11 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_OPB_ERRACK ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_INVALID_ADDRESS , 12 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_INVALID_ADDRESS ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_PORT_IS_FENCED , 13 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_PORT_IS_FENCED ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_READ_DATA_VALID , 14 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_READ_DATA_VALID ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_BUSY_FLAG , 15 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_OPB_BUSY_FLAG ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_CM_ANY_MASTER_ERROR , 16 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_MASTER_ERROR ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_CM_ANY_PORT_INTERRUPT , 17 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_PORT_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_CM_HOT_PLUG_EVENT , 18 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_CM_HOT_PLUG_EVENT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_CM_CONTROL_REGISTER_PARITY_INTERRUPT , 19 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_CM_CONTROL_REGISTER_PARITY_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT , 20 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT , 21 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_M_ANY_MASTER_ERROR , 24 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_M_ANY_MASTER_ERROR ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_M_ANY_PORT_INTERRUPT , 25 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_M_ANY_PORT_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_M_HOT_PLUG_EVENT , 26 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_M_HOT_PLUG_EVENT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_M_CONTROL_REGISTER_PARITY_INTERRUPT , 27 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_M_CONTROL_REGISTER_PARITY_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT , 28 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT , 29 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_READ_DATA , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_READ_DATA ); +REG64_FLD( PERV_STAT_RDDAT_ERRES_READ_DATA_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_READ_DATA_LEN ); + +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_ANY_ERROR , 0 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_ANY_ERROR ); REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CMD_PARITY_ERROR , 1 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , SH_FLD_CMD_PARITY_ERROR ); REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR , 2 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , @@ -7101,8 +9254,52 @@ REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR , 4 , SH_UN SH_FLD_LCK_STATUS_PARITY_ERROR ); REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_FSM_PARITY_ERROR , 5 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , SH_FLD_FSM_PARITY_ERROR ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_COMMAND_OVERRUN_ERROR , 7 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_OPB_COMMAND_OVERRUN_ERROR ); REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PARITY_ERROR , 8 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , SH_FLD_OPB_PARITY_ERROR ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PROTOCOL_ERROR , 9 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_OPB_PROTOCOL_ERROR ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_TIMEOUT_BIT , 10 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_OPB_TIMEOUT_BIT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_ERRACK , 11 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_OPB_ERRACK ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_INVALID_ADDRESS , 12 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_INVALID_ADDRESS ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_PORT_IS_FENCED , 13 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_PORT_IS_FENCED ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_READ_DATA_VALID , 14 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_READ_DATA_VALID ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_BUSY_FLAG , 15 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_OPB_BUSY_FLAG ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_MASTER_ERROR , 16 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_MASTER_ERROR ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_PORT_INTERRUPT , 17 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_CM_ANY_PORT_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_HOT_PLUG_EVENT , 18 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_CM_HOT_PLUG_EVENT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_CONTROL_REGISTER_PARITY_INTERRUPT , 19 , SH_UNT_PERV_PIB2OPB0, + SH_ACS_SCOM_RO , SH_FLD_CM_CONTROL_REGISTER_PARITY_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT , 20 , SH_UNT_PERV_PIB2OPB0, + SH_ACS_SCOM_RO , SH_FLD_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT , 21 , SH_UNT_PERV_PIB2OPB0, + SH_ACS_SCOM_RO , SH_FLD_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_MASTER_ERROR , 24 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_M_ANY_MASTER_ERROR ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_PORT_INTERRUPT , 25 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_M_ANY_PORT_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_HOT_PLUG_EVENT , 26 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_M_HOT_PLUG_EVENT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_CONTROL_REGISTER_PARITY_INTERRUPT , 27 , SH_UNT_PERV_PIB2OPB0, + SH_ACS_SCOM_RO , SH_FLD_M_CONTROL_REGISTER_PARITY_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT , 28 , SH_UNT_PERV_PIB2OPB0, + SH_ACS_SCOM_RO , SH_FLD_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT , 29 , SH_UNT_PERV_PIB2OPB0, + SH_ACS_SCOM_RO , SH_FLD_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_READ_DATA , 32 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_READ_DATA ); +REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_READ_DATA_LEN , 32 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , + SH_FLD_READ_DATA_LEN ); REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_SMASK_IN0 ); @@ -7127,16 +9324,18 @@ REG64_FLD( PERV_1_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( PERV_1_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); +REG64_FLD( PERV_1_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( PERV_1_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( PERV_1_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); -REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED1119 ); -REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED1119_LEN ); +REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PULSE_OUT_DIS ); +REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED1219 ); +REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED1219_LEN ); REG64_FLD( PERV_1_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -7172,6 +9371,10 @@ REG64_FLD( PERV_1_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UN SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( PERV_1_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); +REG64_FLD( PERV_1_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1 ); +REG64_FLD( PERV_1_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1_LEN ); REG64_FLD( PERV_TIMEOUT_REG_REGISTER , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_REGISTER ); @@ -8548,8 +10751,28 @@ REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_ REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -8641,6 +10864,14 @@ REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , S SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -8672,8 +10903,28 @@ REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_ REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -8765,6 +11016,14 @@ REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , S SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG ); @@ -8776,6 +11035,11 @@ REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN ); +REG64_FLD( PERV_1_VMEAS_RESULT_REG_RESULT , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RESULT ); +REG64_FLD( PERV_1_VMEAS_RESULT_REG_RESULT_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RESULT_LEN ); + REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , SH_FLD_WATERMARK_REG_0 ); REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , @@ -8945,6 +11209,9 @@ REG64_FLD( PERV_1_XSTOP3_WAIT_CYCLES , 48 , SH_UN REG64_FLD( PERV_1_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); +REG64_FLD( PERV_1_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( PERV_1_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PERV_1_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM , diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H index 01cc0b47..82a589f8 100644 --- a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H +++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H @@ -49,13 +49,6 @@ //FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE, // 12); -//static const uint64_t SH_UNT_PERV_CBS_ENVSTAT = 514; -static const uint64_t SH_FLD_C4_TEST_ENABLE = 32000; -static const uint64_t SH_FLD_C4_CARD_TEST_BSC = 32001; -static const uint64_t SH_FLD_C4_VDN_GPOOD = 32002; -static const uint64_t SH_FLD_C4_FSI_IN_ENA = 32003; -static const uint64_t SH_FLD_C4_CHIP_MASTER = 32004; -static const uint64_t SH_FLD_C4_SMD = 32005; static const uint64_t SH_FLD_CLOCK_REGION_ALL_UNITS = 32006; static const uint64_t SH_FLD_CLOCK_REGION_ALL_UNITS_LEN = 32007; static const uint64_t SH_FLD_SEL_THOLD_ALL = 32008; @@ -69,24 +62,6 @@ static const uint64_t SH_FLD_SCAN_REGION_ALL_UNITS_LEN = 32015; static const uint64_t SH_FLD_SCAN_ALL_TYPES = 32016; static const uint64_t SH_FLD_SCAN_ALL_TYPES_LEN = 32017; -REG64_FLD( PERV_CBS_ENVSTAT_C4_TEST_ENABLE , 0 , SH_UNT_PERV_CBS_ENVSTAT , - SH_ACS_SCOM , - SH_FLD_C4_TEST_ENABLE ); -REG64_FLD( PERV_CBS_ENVSTAT_C4_CARD_TEST_BSC , 1 , SH_UNT_PERV_CBS_ENVSTAT , - SH_ACS_SCOM , - SH_FLD_C4_CARD_TEST_BSC ); -REG64_FLD( PERV_CBS_ENVSTAT_C4_VDN_GPOOD , 2 , SH_UNT_PERV_CBS_ENVSTAT , - SH_ACS_SCOM , - SH_FLD_C4_VDN_GPOOD ); -REG64_FLD( PERV_CBS_ENVSTAT_C4_FSI_IN_ENA , 3 , SH_UNT_PERV_CBS_ENVSTAT , - SH_ACS_SCOM , - SH_FLD_C4_FSI_IN_ENA ); -REG64_FLD( PERV_CBS_ENVSTAT_C4_CHIP_MASTER , 4 , SH_UNT_PERV_CBS_ENVSTAT , - SH_ACS_SCOM , - SH_FLD_C4_CHIP_MASTER ); -REG64_FLD( PERV_CBS_ENVSTAT_C4_SMD , 5 , SH_UNT_PERV_CBS_ENVSTAT , - SH_ACS_SCOM , - SH_FLD_C4_SMD ); REG64_FLD( PERV_1_CLK_REGION_CLOCK_REGION_ALL_UNITS , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CLOCK_REGION_ALL_UNITS ); diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses.H index 17215825..a0b124d2 100644 --- a/src/import/chips/p9/common/include/p9_quad_scom_addresses.H +++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses.H @@ -287,7 +287,7 @@ REG64( EX_5_ADDR_TRAP_REG , RULL(0x2A010003 SH_ACS_SCOM ); //DUPS: 2B010003, REG64( EX_6_ADDR_TRAP_REG , RULL(0x2C010003), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010003, -REG64( EX_7_ADDR_TRAP_REG , RULL(0x2E010003), SH_UNT_EX_7 , +REG64( EX_7_ADDR_TRAP_REG , RULL(0x2F010003), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010003, REG64( EX_8_ADDR_TRAP_REG , RULL(0x30010003), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010003, @@ -334,7 +334,7 @@ REG64( EX_ASSIST_INTERRUPT_REG , RULL(0x200F0011 SH_ACS_SCOM ); //DUPS: 210F0011, REG64( EX_0_ASSIST_INTERRUPT_REG , RULL(0x200F0011), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0011, -REG64( EX_1_ASSIST_INTERRUPT_REG , RULL(0x230F0011), SH_UNT_EX_1 , +REG64( EX_1_ASSIST_INTERRUPT_REG , RULL(0x220F0011), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0011, REG64( EX_2_ASSIST_INTERRUPT_REG , RULL(0x240F0011), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0011, @@ -405,7 +405,7 @@ REG64( EX_5_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x2A010007 SH_ACS_SCOM ); //DUPS: 2B010007, REG64( EX_6_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x2C010007), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010007, -REG64( EX_7_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x2E010007), SH_UNT_EX_7 , +REG64( EX_7_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x2F010007), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010007, REG64( EX_8_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x30010007), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010007, @@ -452,7 +452,7 @@ REG64( EX_ATOMIC_LOCK_REG , RULL(0x200F03FF SH_ACS_SCOM ); //DUPS: 210F03FF, REG64( EX_0_ATOMIC_LOCK_REG , RULL(0x200F03FF), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F03FF, -REG64( EX_1_ATOMIC_LOCK_REG , RULL(0x230F03FF), SH_UNT_EX_1 , +REG64( EX_1_ATOMIC_LOCK_REG , RULL(0x220F03FF), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F03FF, REG64( EX_2_ATOMIC_LOCK_REG , RULL(0x240F03FF), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F03FF, @@ -511,7 +511,7 @@ REG64( EX_ATTN_INTERRUPT_REG , RULL(0x200F001A SH_ACS_SCOM ); //DUPS: 210F001A, REG64( EX_0_ATTN_INTERRUPT_REG , RULL(0x200F001A), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F001A, -REG64( EX_1_ATTN_INTERRUPT_REG , RULL(0x230F001A), SH_UNT_EX_1 , +REG64( EX_1_ATTN_INTERRUPT_REG , RULL(0x220F001A), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F001A, REG64( EX_2_ATTN_INTERRUPT_REG , RULL(0x240F001A), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F001A, @@ -582,7 +582,7 @@ REG64( EX_5_BIST , RULL(0x2A03000B SH_ACS_SCOM ); //DUPS: 2B03000B, REG64( EX_6_BIST , RULL(0x2C03000B), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D03000B, -REG64( EX_7_BIST , RULL(0x2E03000B), SH_UNT_EX_7 , +REG64( EX_7_BIST , RULL(0x2F03000B), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F03000B, REG64( EX_8_BIST , RULL(0x3003000B), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3103000B, @@ -641,7 +641,7 @@ REG64( EX_5_CC_ATOMIC_LOCK_REG , RULL(0x2A0303FF SH_ACS_SCOM ); //DUPS: 2B0303FF, REG64( EX_6_CC_ATOMIC_LOCK_REG , RULL(0x2C0303FF), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0303FF, -REG64( EX_7_CC_ATOMIC_LOCK_REG , RULL(0x2E0303FF), SH_UNT_EX_7 , +REG64( EX_7_CC_ATOMIC_LOCK_REG , RULL(0x2F0303FF), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0303FF, REG64( EX_8_CC_ATOMIC_LOCK_REG , RULL(0x300303FF), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310303FF, @@ -700,7 +700,7 @@ REG64( EX_5_CC_PROTECT_MODE_REG , RULL(0x2A0303FE SH_ACS_SCOM ); //DUPS: 2B0303FE, REG64( EX_6_CC_PROTECT_MODE_REG , RULL(0x2C0303FE), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0303FE, -REG64( EX_7_CC_PROTECT_MODE_REG , RULL(0x2E0303FE), SH_UNT_EX_7 , +REG64( EX_7_CC_PROTECT_MODE_REG , RULL(0x2F0303FE), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0303FE, REG64( EX_8_CC_PROTECT_MODE_REG , RULL(0x300303FE), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310303FE, @@ -759,7 +759,7 @@ REG64( EX_5_CLK_REGION , RULL(0x2A030006 SH_ACS_SCOM ); //DUPS: 2B030006, REG64( EX_6_CLK_REGION , RULL(0x2C030006), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030006, -REG64( EX_7_CLK_REGION , RULL(0x2E030006), SH_UNT_EX_7 , +REG64( EX_7_CLK_REGION , RULL(0x2F030006), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030006, REG64( EX_8_CLK_REGION , RULL(0x30030006), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030006, @@ -818,7 +818,7 @@ REG64( EX_5_CLOCK_STAT_ARY , RULL(0x2A03000A SH_ACS_SCOM ); //DUPS: 2B03000A, REG64( EX_6_CLOCK_STAT_ARY , RULL(0x2C03000A), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D03000A, -REG64( EX_7_CLOCK_STAT_ARY , RULL(0x2E03000A), SH_UNT_EX_7 , +REG64( EX_7_CLOCK_STAT_ARY , RULL(0x2F03000A), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F03000A, REG64( EX_8_CLOCK_STAT_ARY , RULL(0x3003000A), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3103000A, @@ -877,7 +877,7 @@ REG64( EX_5_CLOCK_STAT_NSL , RULL(0x2A030009 SH_ACS_SCOM ); //DUPS: 2B030009, REG64( EX_6_CLOCK_STAT_NSL , RULL(0x2C030009), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030009, -REG64( EX_7_CLOCK_STAT_NSL , RULL(0x2E030009), SH_UNT_EX_7 , +REG64( EX_7_CLOCK_STAT_NSL , RULL(0x2F030009), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030009, REG64( EX_8_CLOCK_STAT_NSL , RULL(0x30030009), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030009, @@ -936,7 +936,7 @@ REG64( EX_5_CLOCK_STAT_SL , RULL(0x2A030008 SH_ACS_SCOM ); //DUPS: 2B030008, REG64( EX_6_CLOCK_STAT_SL , RULL(0x2C030008), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030008, -REG64( EX_7_CLOCK_STAT_SL , RULL(0x2E030008), SH_UNT_EX_7 , +REG64( EX_7_CLOCK_STAT_SL , RULL(0x2F030008), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030008, REG64( EX_8_CLOCK_STAT_SL , RULL(0x30030008), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030008, @@ -1026,19 +1026,19 @@ REG64( EX_11_CME_LCL_DBG_PPE1 , RULL(0x10E02013 REG64( EX_11_CME_LCL_DBG_PPE2 , RULL(0x10E020130), SH_UNT_EX_11 , SH_ACS_PPE2 ); -REG64( EQ_CME_LCL_EIMR , RULL(0x10012426), SH_UNT_EQ , +REG64( EQ_CME_LCL_EIMR , RULL(0x10012026), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012026, -REG64( EQ_0_CME_LCL_EIMR , RULL(0x10012426), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_EIMR , RULL(0x10012026), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012026, -REG64( EQ_1_CME_LCL_EIMR , RULL(0x11012426), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_EIMR , RULL(0x11012026), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012026, -REG64( EQ_2_CME_LCL_EIMR , RULL(0x12012426), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_EIMR , RULL(0x12012026), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012026, -REG64( EQ_3_CME_LCL_EIMR , RULL(0x13012426), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_EIMR , RULL(0x13012026), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012026, -REG64( EQ_4_CME_LCL_EIMR , RULL(0x14012426), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_EIMR , RULL(0x14012026), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012026, -REG64( EQ_5_CME_LCL_EIMR , RULL(0x15012426), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_EIMR , RULL(0x15012026), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012026, REG64( EX_CME_LCL_EIMR_PPE , RULL(0x109010020), SH_UNT_EX , SH_ACS_PPE ); @@ -1132,19 +1132,19 @@ REG64( EX_11_CME_LCL_EIMR_PPE2 , RULL(0x10E02003 SH_ACS_PPE2 ); REG64( EX_11_CME_LCL_EIMR_SCOM , RULL(0x15012426), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_LCL_EINR , RULL(0x1001242A), SH_UNT_EQ , +REG64( EQ_CME_LCL_EINR , RULL(0x1001202A), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001202A, -REG64( EQ_0_CME_LCL_EINR , RULL(0x1001242A), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_EINR , RULL(0x1001202A), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001202A, -REG64( EQ_1_CME_LCL_EINR , RULL(0x1101242A), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_EINR , RULL(0x1101202A), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101202A, -REG64( EQ_2_CME_LCL_EINR , RULL(0x1201242A), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_EINR , RULL(0x1201202A), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201202A, -REG64( EQ_3_CME_LCL_EINR , RULL(0x1301242A), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_EINR , RULL(0x1301202A), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301202A, -REG64( EQ_4_CME_LCL_EINR , RULL(0x1401242A), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_EINR , RULL(0x1401202A), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401202A, -REG64( EQ_5_CME_LCL_EINR , RULL(0x1501242A), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_EINR , RULL(0x1501202A), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501202A, REG64( EX_CME_LCL_EINR_PPE , RULL(0x1090100A0), SH_UNT_EX , SH_ACS_PPE ); @@ -1186,19 +1186,19 @@ REG64( EX_11_CME_LCL_EINR_PPE , RULL(0x10E0200A SH_ACS_PPE ); REG64( EX_11_CME_LCL_EINR_SCOM , RULL(0x1501242A), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_LCL_EIPR , RULL(0x10012427), SH_UNT_EQ , +REG64( EQ_CME_LCL_EIPR , RULL(0x10012027), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012027, -REG64( EQ_0_CME_LCL_EIPR , RULL(0x10012427), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_EIPR , RULL(0x10012027), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012027, -REG64( EQ_1_CME_LCL_EIPR , RULL(0x11012427), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_EIPR , RULL(0x11012027), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012027, -REG64( EQ_2_CME_LCL_EIPR , RULL(0x12012427), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_EIPR , RULL(0x12012027), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012027, -REG64( EQ_3_CME_LCL_EIPR , RULL(0x13012427), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_EIPR , RULL(0x13012027), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012027, -REG64( EQ_4_CME_LCL_EIPR , RULL(0x14012427), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_EIPR , RULL(0x14012027), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012027, -REG64( EQ_5_CME_LCL_EIPR , RULL(0x15012427), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_EIPR , RULL(0x15012027), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012027, REG64( EX_CME_LCL_EIPR_PPE , RULL(0x109010040), SH_UNT_EX , SH_ACS_PPE ); @@ -1292,19 +1292,19 @@ REG64( EX_11_CME_LCL_EIPR_PPE2 , RULL(0x10E02005 SH_ACS_PPE2 ); REG64( EX_11_CME_LCL_EIPR_SCOM , RULL(0x15012427), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_LCL_EISR , RULL(0x10012425), SH_UNT_EQ , +REG64( EQ_CME_LCL_EISR , RULL(0x10012025), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012025, -REG64( EQ_0_CME_LCL_EISR , RULL(0x10012425), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_EISR , RULL(0x10012025), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012025, -REG64( EQ_1_CME_LCL_EISR , RULL(0x11012425), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_EISR , RULL(0x11012025), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012025, -REG64( EQ_2_CME_LCL_EISR , RULL(0x12012425), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_EISR , RULL(0x12012025), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012025, -REG64( EQ_3_CME_LCL_EISR , RULL(0x13012425), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_EISR , RULL(0x13012025), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012025, -REG64( EQ_4_CME_LCL_EISR , RULL(0x14012425), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_EISR , RULL(0x14012025), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012025, -REG64( EQ_5_CME_LCL_EISR , RULL(0x15012425), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_EISR , RULL(0x15012025), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012025, REG64( EX_CME_LCL_EISR_PPE , RULL(0x109010000), SH_UNT_EX , SH_ACS_PPE ); @@ -1398,19 +1398,19 @@ REG64( EX_11_CME_LCL_EISR_PPE2 , RULL(0x10E02001 SH_ACS_PPE2 ); REG64( EX_11_CME_LCL_EISR_SCOM , RULL(0x15012425), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_LCL_EISTR , RULL(0x10012429), SH_UNT_EQ , +REG64( EQ_CME_LCL_EISTR , RULL(0x10012029), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012029, -REG64( EQ_0_CME_LCL_EISTR , RULL(0x10012429), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_EISTR , RULL(0x10012029), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012029, -REG64( EQ_1_CME_LCL_EISTR , RULL(0x11012429), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_EISTR , RULL(0x11012029), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012029, -REG64( EQ_2_CME_LCL_EISTR , RULL(0x12012429), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_EISTR , RULL(0x12012029), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012029, -REG64( EQ_3_CME_LCL_EISTR , RULL(0x13012429), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_EISTR , RULL(0x13012029), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012029, -REG64( EQ_4_CME_LCL_EISTR , RULL(0x14012429), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_EISTR , RULL(0x14012029), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012029, -REG64( EQ_5_CME_LCL_EISTR , RULL(0x15012429), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_EISTR , RULL(0x15012029), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012029, REG64( EX_CME_LCL_EISTR_PPE , RULL(0x109010080), SH_UNT_EX , SH_ACS_PPE ); @@ -1452,19 +1452,19 @@ REG64( EX_11_CME_LCL_EISTR_PPE , RULL(0x10E02008 SH_ACS_PPE ); REG64( EX_11_CME_LCL_EISTR_SCOM , RULL(0x15012429), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_LCL_EITR , RULL(0x10012428), SH_UNT_EQ , +REG64( EQ_CME_LCL_EITR , RULL(0x10012028), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012028, -REG64( EQ_0_CME_LCL_EITR , RULL(0x10012428), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_EITR , RULL(0x10012028), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012028, -REG64( EQ_1_CME_LCL_EITR , RULL(0x11012428), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_EITR , RULL(0x11012028), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012028, -REG64( EQ_2_CME_LCL_EITR , RULL(0x12012428), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_EITR , RULL(0x12012028), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012028, -REG64( EQ_3_CME_LCL_EITR , RULL(0x13012428), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_EITR , RULL(0x13012028), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012028, -REG64( EQ_4_CME_LCL_EITR , RULL(0x14012428), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_EITR , RULL(0x14012028), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012028, -REG64( EQ_5_CME_LCL_EITR , RULL(0x15012428), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_EITR , RULL(0x15012028), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012028, REG64( EX_CME_LCL_EITR_PPE , RULL(0x109010060), SH_UNT_EX , SH_ACS_PPE ); @@ -1637,19 +1637,19 @@ REG64( EX_11_CME_LCL_ICCR_PPE1 , RULL(0x10E02071 REG64( EX_11_CME_LCL_ICCR_PPE2 , RULL(0x10E020710), SH_UNT_EX_11 , SH_ACS_PPE2 ); -REG64( EQ_CME_LCL_ICRR , RULL(0x1001244D), SH_UNT_EQ , +REG64( EQ_CME_LCL_ICRR , RULL(0x1001204D), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001204D, -REG64( EQ_0_CME_LCL_ICRR , RULL(0x1001244D), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_ICRR , RULL(0x1001204D), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001204D, -REG64( EQ_1_CME_LCL_ICRR , RULL(0x1101244D), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_ICRR , RULL(0x1101204D), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101204D, -REG64( EQ_2_CME_LCL_ICRR , RULL(0x1201244D), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_ICRR , RULL(0x1201204D), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201204D, -REG64( EQ_3_CME_LCL_ICRR , RULL(0x1301244D), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_ICRR , RULL(0x1301204D), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301204D, -REG64( EQ_4_CME_LCL_ICRR , RULL(0x1401244D), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_ICRR , RULL(0x1401204D), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401204D, -REG64( EQ_5_CME_LCL_ICRR , RULL(0x1501244D), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_ICRR , RULL(0x1501204D), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501204D, REG64( EX_CME_LCL_ICRR_PPE , RULL(0x109010740), SH_UNT_EX , SH_ACS_PPE ); @@ -1718,33 +1718,6 @@ REG64( EX_10_CME_LCL_ICSR_PPE , RULL(0x10E01072 REG64( EX_11_CME_LCL_ICSR_PPE , RULL(0x10E020720), SH_UNT_EX_11 , SH_ACS_PPE ); -REG64( EX_CME_LCL_LMCR_PPE , RULL(0x1090101A0), SH_UNT_EX , - SH_ACS_PPE ); -REG64( EX_0_CME_LCL_LMCR_PPE , RULL(0x1090101A0), SH_UNT_EX_0 , - SH_ACS_PPE ); -REG64( EX_1_CME_LCL_LMCR_PPE , RULL(0x1090201A0), SH_UNT_EX_1 , - SH_ACS_PPE ); -REG64( EX_2_CME_LCL_LMCR_PPE , RULL(0x10A0101A0), SH_UNT_EX_2 , - SH_ACS_PPE ); -REG64( EX_3_CME_LCL_LMCR_PPE , RULL(0x10A0201A0), SH_UNT_EX_3 , - SH_ACS_PPE ); -REG64( EX_4_CME_LCL_LMCR_PPE , RULL(0x10B0101A0), SH_UNT_EX_4 , - SH_ACS_PPE ); -REG64( EX_5_CME_LCL_LMCR_PPE , RULL(0x10B0201A0), SH_UNT_EX_5 , - SH_ACS_PPE ); -REG64( EX_6_CME_LCL_LMCR_PPE , RULL(0x10C0101A0), SH_UNT_EX_6 , - SH_ACS_PPE ); -REG64( EX_7_CME_LCL_LMCR_PPE , RULL(0x10C0201A0), SH_UNT_EX_7 , - SH_ACS_PPE ); -REG64( EX_8_CME_LCL_LMCR_PPE , RULL(0x10D0101A0), SH_UNT_EX_8 , - SH_ACS_PPE ); -REG64( EX_9_CME_LCL_LMCR_PPE , RULL(0x10D0201A0), SH_UNT_EX_9 , - SH_ACS_PPE ); -REG64( EX_10_CME_LCL_LMCR_PPE , RULL(0x10E0101A0), SH_UNT_EX_10 , - SH_ACS_PPE ); -REG64( EX_11_CME_LCL_LMCR_PPE , RULL(0x10E0201A0), SH_UNT_EX_11 , - SH_ACS_PPE ); - REG64( EX_CME_LCL_PECESR0_PPE , RULL(0x109010280), SH_UNT_EX , SH_ACS_PPE ); REG64( EX_0_CME_LCL_PECESR0_PPE , RULL(0x109010280), SH_UNT_EX_0 , @@ -1799,19 +1772,19 @@ REG64( EX_10_CME_LCL_PECESR1_PPE , RULL(0x10E0102A REG64( EX_11_CME_LCL_PECESR1_PPE , RULL(0x10E0202A0), SH_UNT_EX_11 , SH_ACS_PPE ); -REG64( EQ_CME_LCL_SISR , RULL(0x1001244C), SH_UNT_EQ , +REG64( EQ_CME_LCL_SISR , RULL(0x1001204C), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001204C, -REG64( EQ_0_CME_LCL_SISR , RULL(0x1001244C), SH_UNT_EQ_0 , +REG64( EQ_0_CME_LCL_SISR , RULL(0x1001204C), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001204C, -REG64( EQ_1_CME_LCL_SISR , RULL(0x1101244C), SH_UNT_EQ_1 , +REG64( EQ_1_CME_LCL_SISR , RULL(0x1101204C), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101204C, -REG64( EQ_2_CME_LCL_SISR , RULL(0x1201244C), SH_UNT_EQ_2 , +REG64( EQ_2_CME_LCL_SISR , RULL(0x1201204C), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201204C, -REG64( EQ_3_CME_LCL_SISR , RULL(0x1301244C), SH_UNT_EQ_3 , +REG64( EQ_3_CME_LCL_SISR , RULL(0x1301204C), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301204C, -REG64( EQ_4_CME_LCL_SISR , RULL(0x1401244C), SH_UNT_EQ_4 , +REG64( EQ_4_CME_LCL_SISR , RULL(0x1401204C), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401204C, -REG64( EQ_5_CME_LCL_SISR , RULL(0x1501244C), SH_UNT_EQ_5 , +REG64( EQ_5_CME_LCL_SISR , RULL(0x1501204C), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501204C, REG64( EX_CME_LCL_SISR_PPE , RULL(0x109010520), SH_UNT_EX , SH_ACS_PPE ); @@ -1880,19 +1853,19 @@ REG64( EX_10_CME_LCL_TSEL_PPE , RULL(0x10E01010 REG64( EX_11_CME_LCL_TSEL_PPE , RULL(0x10E020100), SH_UNT_EX_11 , SH_ACS_PPE ); -REG64( EQ_CME_SCOM_AFSR , RULL(0x10012433), SH_UNT_EQ , +REG64( EQ_CME_SCOM_AFSR , RULL(0x10012033), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10012033, -REG64( EQ_0_CME_SCOM_AFSR , RULL(0x10012433), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_AFSR , RULL(0x10012033), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10012033, -REG64( EQ_1_CME_SCOM_AFSR , RULL(0x11012433), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_AFSR , RULL(0x11012033), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11012033, -REG64( EQ_2_CME_SCOM_AFSR , RULL(0x12012433), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_AFSR , RULL(0x12012033), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12012033, -REG64( EQ_3_CME_SCOM_AFSR , RULL(0x13012433), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_AFSR , RULL(0x13012033), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13012033, -REG64( EQ_4_CME_SCOM_AFSR , RULL(0x14012433), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_AFSR , RULL(0x14012033), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14012033, -REG64( EQ_5_CME_SCOM_AFSR , RULL(0x15012433), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_AFSR , RULL(0x15012033), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15012033, REG64( EX_CME_SCOM_AFSR_PPE , RULL(0x109010160), SH_UNT_EX , SH_ACS_PPE ); @@ -1934,19 +1907,19 @@ REG64( EX_11_CME_SCOM_AFSR_PPE , RULL(0x10E02016 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_AFSR_SCOM , RULL(0x15012433), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_CME_SCOM_AFTR , RULL(0x10012434), SH_UNT_EQ , +REG64( EQ_CME_SCOM_AFTR , RULL(0x10012034), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012034, -REG64( EQ_0_CME_SCOM_AFTR , RULL(0x10012434), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_AFTR , RULL(0x10012034), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012034, -REG64( EQ_1_CME_SCOM_AFTR , RULL(0x11012434), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_AFTR , RULL(0x11012034), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012034, -REG64( EQ_2_CME_SCOM_AFTR , RULL(0x12012434), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_AFTR , RULL(0x12012034), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012034, -REG64( EQ_3_CME_SCOM_AFTR , RULL(0x13012434), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_AFTR , RULL(0x13012034), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012034, -REG64( EQ_4_CME_SCOM_AFTR , RULL(0x14012434), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_AFTR , RULL(0x14012034), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012034, -REG64( EQ_5_CME_SCOM_AFTR , RULL(0x15012434), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_AFTR , RULL(0x15012034), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012034, REG64( EX_CME_SCOM_AFTR_PPE , RULL(0x109010180), SH_UNT_EX , SH_ACS_PPE ); @@ -1988,19 +1961,19 @@ REG64( EX_11_CME_SCOM_AFTR_PPE , RULL(0x10E02018 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_AFTR_SCOM , RULL(0x15012434), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_BCEBAR0 , RULL(0x10012430), SH_UNT_EQ , +REG64( EQ_CME_SCOM_BCEBAR0 , RULL(0x10012030), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012030, -REG64( EQ_0_CME_SCOM_BCEBAR0 , RULL(0x10012430), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_BCEBAR0 , RULL(0x10012030), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012030, -REG64( EQ_1_CME_SCOM_BCEBAR0 , RULL(0x11012430), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_BCEBAR0 , RULL(0x11012030), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012030, -REG64( EQ_2_CME_SCOM_BCEBAR0 , RULL(0x12012430), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_BCEBAR0 , RULL(0x12012030), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012030, -REG64( EQ_3_CME_SCOM_BCEBAR0 , RULL(0x13012430), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_BCEBAR0 , RULL(0x13012030), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012030, -REG64( EQ_4_CME_SCOM_BCEBAR0 , RULL(0x14012430), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_BCEBAR0 , RULL(0x14012030), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012030, -REG64( EQ_5_CME_SCOM_BCEBAR0 , RULL(0x15012430), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_BCEBAR0 , RULL(0x15012030), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012030, REG64( EX_CME_SCOM_BCEBAR0 , RULL(0x10012030), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CME_SCOM_BCEBAR0 , RULL(0x10012030), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -2016,19 +1989,19 @@ REG64( EX_9_CME_SCOM_BCEBAR0 , RULL(0x14012430 REG64( EX_10_CME_SCOM_BCEBAR0 , RULL(0x15012030), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); REG64( EX_11_CME_SCOM_BCEBAR0 , RULL(0x15012430), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_BCEBAR1 , RULL(0x10012431), SH_UNT_EQ , +REG64( EQ_CME_SCOM_BCEBAR1 , RULL(0x10012031), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012031, -REG64( EQ_0_CME_SCOM_BCEBAR1 , RULL(0x10012431), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_BCEBAR1 , RULL(0x10012031), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012031, -REG64( EQ_1_CME_SCOM_BCEBAR1 , RULL(0x11012431), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_BCEBAR1 , RULL(0x11012031), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012031, -REG64( EQ_2_CME_SCOM_BCEBAR1 , RULL(0x12012431), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_BCEBAR1 , RULL(0x12012031), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012031, -REG64( EQ_3_CME_SCOM_BCEBAR1 , RULL(0x13012431), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_BCEBAR1 , RULL(0x13012031), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012031, -REG64( EQ_4_CME_SCOM_BCEBAR1 , RULL(0x14012431), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_BCEBAR1 , RULL(0x14012031), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012031, -REG64( EQ_5_CME_SCOM_BCEBAR1 , RULL(0x15012431), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_BCEBAR1 , RULL(0x15012031), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012031, REG64( EX_CME_SCOM_BCEBAR1 , RULL(0x10012031), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CME_SCOM_BCEBAR1 , RULL(0x10012031), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -2044,19 +2017,19 @@ REG64( EX_9_CME_SCOM_BCEBAR1 , RULL(0x14012431 REG64( EX_10_CME_SCOM_BCEBAR1 , RULL(0x15012031), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); REG64( EX_11_CME_SCOM_BCEBAR1 , RULL(0x15012431), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_BCECSR , RULL(0x1001240F), SH_UNT_EQ , +REG64( EQ_CME_SCOM_BCECSR , RULL(0x1001200F), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 1001200F, -REG64( EQ_0_CME_SCOM_BCECSR , RULL(0x1001240F), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_BCECSR , RULL(0x1001200F), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 1001200F, -REG64( EQ_1_CME_SCOM_BCECSR , RULL(0x1101240F), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_BCECSR , RULL(0x1101200F), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 1101200F, -REG64( EQ_2_CME_SCOM_BCECSR , RULL(0x1201240F), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_BCECSR , RULL(0x1201200F), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 1201200F, -REG64( EQ_3_CME_SCOM_BCECSR , RULL(0x1301240F), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_BCECSR , RULL(0x1301200F), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 1301200F, -REG64( EQ_4_CME_SCOM_BCECSR , RULL(0x1401240F), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_BCECSR , RULL(0x1401200F), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 1401200F, -REG64( EQ_5_CME_SCOM_BCECSR , RULL(0x1501240F), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_BCECSR , RULL(0x1501200F), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 1501200F, REG64( EX_CME_SCOM_BCECSR_PPE , RULL(0x1090101E0), SH_UNT_EX , SH_ACS_PPE ); @@ -2098,19 +2071,19 @@ REG64( EX_11_CME_SCOM_BCECSR_PPE , RULL(0x10E0201E SH_ACS_PPE ); REG64( EX_11_CME_SCOM_BCECSR_SCOM , RULL(0x1501240F), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_CME_SCOM_CIDSR , RULL(0x1001242E), SH_UNT_EQ , +REG64( EQ_CME_SCOM_CIDSR , RULL(0x1001202E), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001202E, -REG64( EQ_0_CME_SCOM_CIDSR , RULL(0x1001242E), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_CIDSR , RULL(0x1001202E), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001202E, -REG64( EQ_1_CME_SCOM_CIDSR , RULL(0x1101242E), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_CIDSR , RULL(0x1101202E), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101202E, -REG64( EQ_2_CME_SCOM_CIDSR , RULL(0x1201242E), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_CIDSR , RULL(0x1201202E), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201202E, -REG64( EQ_3_CME_SCOM_CIDSR , RULL(0x1301242E), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_CIDSR , RULL(0x1301202E), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301202E, -REG64( EQ_4_CME_SCOM_CIDSR , RULL(0x1401242E), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_CIDSR , RULL(0x1401202E), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401202E, -REG64( EQ_5_CME_SCOM_CIDSR , RULL(0x1501242E), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_CIDSR , RULL(0x1501202E), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501202E, REG64( EX_CME_SCOM_CIDSR_PPE , RULL(0x1090106C0), SH_UNT_EX , SH_ACS_PPE ); @@ -2152,19 +2125,19 @@ REG64( EX_11_CME_SCOM_CIDSR_PPE , RULL(0x10E0206C SH_ACS_PPE ); REG64( EX_11_CME_SCOM_CIDSR_SCOM , RULL(0x1501242E), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_EIIR , RULL(0x1001242B), SH_UNT_EQ , +REG64( EQ_CME_SCOM_EIIR , RULL(0x1001202B), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 1001202B, -REG64( EQ_0_CME_SCOM_EIIR , RULL(0x1001242B), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_EIIR , RULL(0x1001202B), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 1001202B, -REG64( EQ_1_CME_SCOM_EIIR , RULL(0x1101242B), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_EIIR , RULL(0x1101202B), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 1101202B, -REG64( EQ_2_CME_SCOM_EIIR , RULL(0x1201242B), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_EIIR , RULL(0x1201202B), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 1201202B, -REG64( EQ_3_CME_SCOM_EIIR , RULL(0x1301242B), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_EIIR , RULL(0x1301202B), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 1301202B, -REG64( EQ_4_CME_SCOM_EIIR , RULL(0x1401242B), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_EIIR , RULL(0x1401202B), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 1401202B, -REG64( EQ_5_CME_SCOM_EIIR , RULL(0x1501242B), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_EIIR , RULL(0x1501202B), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 1501202B, REG64( EX_CME_SCOM_EIIR , RULL(0x1001202B), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_CME_SCOM_EIIR , RULL(0x1001202B), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -2180,47 +2153,47 @@ REG64( EX_9_CME_SCOM_EIIR , RULL(0x1401242B REG64( EX_10_CME_SCOM_EIIR , RULL(0x1501202B), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_CME_SCOM_EIIR , RULL(0x1501242B), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_CME_SCOM_FLAGS , RULL(0x10012420), SH_UNT_EQ , +REG64( EQ_CME_SCOM_FLAGS , RULL(0x10012020), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012020, -REG64( EQ_CME_SCOM_FLAGS_CLEAR , RULL(0x10012421), SH_UNT_EQ , +REG64( EQ_CME_SCOM_FLAGS_CLEAR , RULL(0x10012021), SH_UNT_EQ , SH_ACS_SCOM1_CLEAR ); //DUPS: 10012021, -REG64( EQ_CME_SCOM_FLAGS_OR , RULL(0x10012422), SH_UNT_EQ , +REG64( EQ_CME_SCOM_FLAGS_OR , RULL(0x10012022), SH_UNT_EQ , SH_ACS_SCOM2_OR ); //DUPS: 10012022, -REG64( EQ_0_CME_SCOM_FLAGS , RULL(0x10012420), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_FLAGS , RULL(0x10012020), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012020, -REG64( EQ_0_CME_SCOM_FLAGS_CLEAR , RULL(0x10012421), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_FLAGS_CLEAR , RULL(0x10012021), SH_UNT_EQ_0 , SH_ACS_SCOM1_CLEAR ); //DUPS: 10012021, -REG64( EQ_0_CME_SCOM_FLAGS_OR , RULL(0x10012422), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_FLAGS_OR , RULL(0x10012022), SH_UNT_EQ_0 , SH_ACS_SCOM2_OR ); //DUPS: 10012022, -REG64( EQ_1_CME_SCOM_FLAGS , RULL(0x11012420), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_FLAGS , RULL(0x11012020), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012020, -REG64( EQ_1_CME_SCOM_FLAGS_CLEAR , RULL(0x11012421), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_FLAGS_CLEAR , RULL(0x11012021), SH_UNT_EQ_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 11012021, -REG64( EQ_1_CME_SCOM_FLAGS_OR , RULL(0x11012422), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_FLAGS_OR , RULL(0x11012022), SH_UNT_EQ_1 , SH_ACS_SCOM2_OR ); //DUPS: 11012022, -REG64( EQ_2_CME_SCOM_FLAGS , RULL(0x12012420), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_FLAGS , RULL(0x12012020), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012020, -REG64( EQ_2_CME_SCOM_FLAGS_CLEAR , RULL(0x12012421), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_FLAGS_CLEAR , RULL(0x12012021), SH_UNT_EQ_2 , SH_ACS_SCOM1_CLEAR ); //DUPS: 12012021, -REG64( EQ_2_CME_SCOM_FLAGS_OR , RULL(0x12012422), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_FLAGS_OR , RULL(0x12012022), SH_UNT_EQ_2 , SH_ACS_SCOM2_OR ); //DUPS: 12012022, -REG64( EQ_3_CME_SCOM_FLAGS , RULL(0x13012420), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_FLAGS , RULL(0x13012020), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012020, -REG64( EQ_3_CME_SCOM_FLAGS_CLEAR , RULL(0x13012421), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_FLAGS_CLEAR , RULL(0x13012021), SH_UNT_EQ_3 , SH_ACS_SCOM1_CLEAR ); //DUPS: 13012021, -REG64( EQ_3_CME_SCOM_FLAGS_OR , RULL(0x13012422), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_FLAGS_OR , RULL(0x13012022), SH_UNT_EQ_3 , SH_ACS_SCOM2_OR ); //DUPS: 13012022, -REG64( EQ_4_CME_SCOM_FLAGS , RULL(0x14012420), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_FLAGS , RULL(0x14012020), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012020, -REG64( EQ_4_CME_SCOM_FLAGS_CLEAR , RULL(0x14012421), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_FLAGS_CLEAR , RULL(0x14012021), SH_UNT_EQ_4 , SH_ACS_SCOM1_CLEAR ); //DUPS: 14012021, -REG64( EQ_4_CME_SCOM_FLAGS_OR , RULL(0x14012422), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_FLAGS_OR , RULL(0x14012022), SH_UNT_EQ_4 , SH_ACS_SCOM2_OR ); //DUPS: 14012022, -REG64( EQ_5_CME_SCOM_FLAGS , RULL(0x15012420), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_FLAGS , RULL(0x15012020), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012020, -REG64( EQ_5_CME_SCOM_FLAGS_CLEAR , RULL(0x15012421), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_FLAGS_CLEAR , RULL(0x15012021), SH_UNT_EQ_5 , SH_ACS_SCOM1_CLEAR ); //DUPS: 15012021, -REG64( EQ_5_CME_SCOM_FLAGS_OR , RULL(0x15012422), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_FLAGS_OR , RULL(0x15012022), SH_UNT_EQ_5 , SH_ACS_SCOM2_OR ); //DUPS: 15012022, REG64( EX_CME_SCOM_FLAGS_PPE , RULL(0x109010400), SH_UNT_EX , SH_ACS_PPE ); @@ -2353,114 +2326,19 @@ REG64( EX_11_CME_SCOM_FLAGS_SCOM1 , RULL(0x15012421 SH_ACS_SCOM1_CLEAR ); REG64( EX_11_CME_SCOM_FLAGS_SCOM2 , RULL(0x15012422), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); -REG64( EQ_CME_SCOM_FWMR , RULL(0x1001243A), SH_UNT_EQ , - SH_ACS_SCOM_RW ); //DUPS: 1001203A, -REG64( EQ_CME_SCOM_FWMR_CLEAR , RULL(0x1001243B), SH_UNT_EQ , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1001203B, -REG64( EQ_CME_SCOM_FWMR_OR , RULL(0x1001243C), SH_UNT_EQ , - SH_ACS_SCOM2_OR ); //DUPS: 1001203C, -REG64( EQ_0_CME_SCOM_FWMR , RULL(0x1001243A), SH_UNT_EQ_0 , - SH_ACS_SCOM_RW ); //DUPS: 1001203A, -REG64( EQ_0_CME_SCOM_FWMR_CLEAR , RULL(0x1001243B), SH_UNT_EQ_0 , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1001203B, -REG64( EQ_0_CME_SCOM_FWMR_OR , RULL(0x1001243C), SH_UNT_EQ_0 , - SH_ACS_SCOM2_OR ); //DUPS: 1001203C, -REG64( EQ_1_CME_SCOM_FWMR , RULL(0x1101243A), SH_UNT_EQ_1 , - SH_ACS_SCOM_RW ); //DUPS: 1101203A, -REG64( EQ_1_CME_SCOM_FWMR_CLEAR , RULL(0x1101243B), SH_UNT_EQ_1 , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1101203B, -REG64( EQ_1_CME_SCOM_FWMR_OR , RULL(0x1101243C), SH_UNT_EQ_1 , - SH_ACS_SCOM2_OR ); //DUPS: 1101203C, -REG64( EQ_2_CME_SCOM_FWMR , RULL(0x1201243A), SH_UNT_EQ_2 , - SH_ACS_SCOM_RW ); //DUPS: 1201203A, -REG64( EQ_2_CME_SCOM_FWMR_CLEAR , RULL(0x1201243B), SH_UNT_EQ_2 , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1201203B, -REG64( EQ_2_CME_SCOM_FWMR_OR , RULL(0x1201243C), SH_UNT_EQ_2 , - SH_ACS_SCOM2_OR ); //DUPS: 1201203C, -REG64( EQ_3_CME_SCOM_FWMR , RULL(0x1301243A), SH_UNT_EQ_3 , - SH_ACS_SCOM_RW ); //DUPS: 1301203A, -REG64( EQ_3_CME_SCOM_FWMR_CLEAR , RULL(0x1301243B), SH_UNT_EQ_3 , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1301203B, -REG64( EQ_3_CME_SCOM_FWMR_OR , RULL(0x1301243C), SH_UNT_EQ_3 , - SH_ACS_SCOM2_OR ); //DUPS: 1301203C, -REG64( EQ_4_CME_SCOM_FWMR , RULL(0x1401243A), SH_UNT_EQ_4 , - SH_ACS_SCOM_RW ); //DUPS: 1401203A, -REG64( EQ_4_CME_SCOM_FWMR_CLEAR , RULL(0x1401243B), SH_UNT_EQ_4 , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1401203B, -REG64( EQ_4_CME_SCOM_FWMR_OR , RULL(0x1401243C), SH_UNT_EQ_4 , - SH_ACS_SCOM2_OR ); //DUPS: 1401203C, -REG64( EQ_5_CME_SCOM_FWMR , RULL(0x1501243A), SH_UNT_EQ_5 , - SH_ACS_SCOM_RW ); //DUPS: 1501203A, -REG64( EQ_5_CME_SCOM_FWMR_CLEAR , RULL(0x1501243B), SH_UNT_EQ_5 , - SH_ACS_SCOM1_CLEAR ); //DUPS: 1501203B, -REG64( EQ_5_CME_SCOM_FWMR_OR , RULL(0x1501243C), SH_UNT_EQ_5 , - SH_ACS_SCOM2_OR ); //DUPS: 1501203C, -REG64( EX_CME_SCOM_FWMR , RULL(0x1001203A), SH_UNT_EX , SH_ACS_SCOM_RW ); -REG64( EX_CME_SCOM_FWMR_CLEAR , RULL(0x1001203B), SH_UNT_EX , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_CME_SCOM_FWMR_OR , RULL(0x1001203C), SH_UNT_EX , SH_ACS_SCOM2_OR ); -REG64( EX_0_CME_SCOM_FWMR , RULL(0x1001203A), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); -REG64( EX_0_CME_SCOM_FWMR_CLEAR , RULL(0x1001203B), SH_UNT_EX_0 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_0_CME_SCOM_FWMR_OR , RULL(0x1001203C), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); -REG64( EX_1_CME_SCOM_FWMR , RULL(0x1001243A), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); -REG64( EX_1_CME_SCOM_FWMR_CLEAR , RULL(0x1001243B), SH_UNT_EX_1 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_1_CME_SCOM_FWMR_OR , RULL(0x1001243C), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); -REG64( EX_2_CME_SCOM_FWMR , RULL(0x1101203A), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); -REG64( EX_2_CME_SCOM_FWMR_CLEAR , RULL(0x1101203B), SH_UNT_EX_2 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_2_CME_SCOM_FWMR_OR , RULL(0x1101203C), SH_UNT_EX_2 , SH_ACS_SCOM2_OR ); -REG64( EX_3_CME_SCOM_FWMR , RULL(0x1101243A), SH_UNT_EX_3 , SH_ACS_SCOM_RW ); -REG64( EX_3_CME_SCOM_FWMR_CLEAR , RULL(0x1101243B), SH_UNT_EX_3 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_3_CME_SCOM_FWMR_OR , RULL(0x1101243C), SH_UNT_EX_3 , SH_ACS_SCOM2_OR ); -REG64( EX_4_CME_SCOM_FWMR , RULL(0x1201203A), SH_UNT_EX_4 , SH_ACS_SCOM_RW ); -REG64( EX_4_CME_SCOM_FWMR_CLEAR , RULL(0x1201203B), SH_UNT_EX_4 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_4_CME_SCOM_FWMR_OR , RULL(0x1201203C), SH_UNT_EX_4 , SH_ACS_SCOM2_OR ); -REG64( EX_5_CME_SCOM_FWMR , RULL(0x1201243A), SH_UNT_EX_5 , SH_ACS_SCOM_RW ); -REG64( EX_5_CME_SCOM_FWMR_CLEAR , RULL(0x1201243B), SH_UNT_EX_5 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_5_CME_SCOM_FWMR_OR , RULL(0x1201243C), SH_UNT_EX_5 , SH_ACS_SCOM2_OR ); -REG64( EX_6_CME_SCOM_FWMR , RULL(0x1301203A), SH_UNT_EX_6 , SH_ACS_SCOM_RW ); -REG64( EX_6_CME_SCOM_FWMR_CLEAR , RULL(0x1301203B), SH_UNT_EX_6 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_6_CME_SCOM_FWMR_OR , RULL(0x1301203C), SH_UNT_EX_6 , SH_ACS_SCOM2_OR ); -REG64( EX_7_CME_SCOM_FWMR , RULL(0x1301243A), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); -REG64( EX_7_CME_SCOM_FWMR_CLEAR , RULL(0x1301243B), SH_UNT_EX_7 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_7_CME_SCOM_FWMR_OR , RULL(0x1301243C), SH_UNT_EX_7 , SH_ACS_SCOM2_OR ); -REG64( EX_8_CME_SCOM_FWMR , RULL(0x1401203A), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); -REG64( EX_8_CME_SCOM_FWMR_CLEAR , RULL(0x1401203B), SH_UNT_EX_8 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_8_CME_SCOM_FWMR_OR , RULL(0x1401203C), SH_UNT_EX_8 , SH_ACS_SCOM2_OR ); -REG64( EX_9_CME_SCOM_FWMR , RULL(0x1401243A), SH_UNT_EX_9 , SH_ACS_SCOM_RW ); -REG64( EX_9_CME_SCOM_FWMR_CLEAR , RULL(0x1401243B), SH_UNT_EX_9 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_9_CME_SCOM_FWMR_OR , RULL(0x1401243C), SH_UNT_EX_9 , SH_ACS_SCOM2_OR ); -REG64( EX_10_CME_SCOM_FWMR , RULL(0x1501203A), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); -REG64( EX_10_CME_SCOM_FWMR_CLEAR , RULL(0x1501203B), SH_UNT_EX_10 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_10_CME_SCOM_FWMR_OR , RULL(0x1501203C), SH_UNT_EX_10 , SH_ACS_SCOM2_OR ); -REG64( EX_11_CME_SCOM_FWMR , RULL(0x1501243A), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EX_11_CME_SCOM_FWMR_CLEAR , RULL(0x1501243B), SH_UNT_EX_11 , - SH_ACS_SCOM1_CLEAR ); -REG64( EX_11_CME_SCOM_FWMR_OR , RULL(0x1501243C), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); - -REG64( EQ_CME_SCOM_IDCR , RULL(0x1001242D), SH_UNT_EQ , +REG64( EQ_CME_SCOM_IDCR , RULL(0x1001202D), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001202D, -REG64( EQ_0_CME_SCOM_IDCR , RULL(0x1001242D), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_IDCR , RULL(0x1001202D), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001202D, -REG64( EQ_1_CME_SCOM_IDCR , RULL(0x1101242D), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_IDCR , RULL(0x1101202D), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101202D, -REG64( EQ_2_CME_SCOM_IDCR , RULL(0x1201242D), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_IDCR , RULL(0x1201202D), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201202D, -REG64( EQ_3_CME_SCOM_IDCR , RULL(0x1301242D), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_IDCR , RULL(0x1301202D), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301202D, -REG64( EQ_4_CME_SCOM_IDCR , RULL(0x1401242D), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_IDCR , RULL(0x1401202D), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401202D, -REG64( EQ_5_CME_SCOM_IDCR , RULL(0x1501242D), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_IDCR , RULL(0x1501202D), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501202D, REG64( EX_CME_SCOM_IDCR_PPE , RULL(0x1090106A0), SH_UNT_EX , SH_ACS_PPE ); @@ -2502,47 +2380,47 @@ REG64( EX_11_CME_SCOM_IDCR_PPE , RULL(0x10E0206A SH_ACS_PPE ); REG64( EX_11_CME_SCOM_IDCR_SCOM , RULL(0x1501242D), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_LFIR , RULL(0x10012400), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIR , RULL(0x10012000), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012000, -REG64( EQ_CME_SCOM_LFIR_AND , RULL(0x10012401), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIR_AND , RULL(0x10012001), SH_UNT_EQ , SH_ACS_SCOM1_AND ); //DUPS: 10012001, -REG64( EQ_CME_SCOM_LFIR_OR , RULL(0x10012402), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIR_OR , RULL(0x10012002), SH_UNT_EQ , SH_ACS_SCOM2_OR ); //DUPS: 10012002, -REG64( EQ_0_CME_SCOM_LFIR , RULL(0x10012400), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIR , RULL(0x10012000), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012000, -REG64( EQ_0_CME_SCOM_LFIR_AND , RULL(0x10012401), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIR_AND , RULL(0x10012001), SH_UNT_EQ_0 , SH_ACS_SCOM1_AND ); //DUPS: 10012001, -REG64( EQ_0_CME_SCOM_LFIR_OR , RULL(0x10012402), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIR_OR , RULL(0x10012002), SH_UNT_EQ_0 , SH_ACS_SCOM2_OR ); //DUPS: 10012002, -REG64( EQ_1_CME_SCOM_LFIR , RULL(0x11012400), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIR , RULL(0x11012000), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012000, -REG64( EQ_1_CME_SCOM_LFIR_AND , RULL(0x11012401), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIR_AND , RULL(0x11012001), SH_UNT_EQ_1 , SH_ACS_SCOM1_AND ); //DUPS: 11012001, -REG64( EQ_1_CME_SCOM_LFIR_OR , RULL(0x11012402), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIR_OR , RULL(0x11012002), SH_UNT_EQ_1 , SH_ACS_SCOM2_OR ); //DUPS: 11012002, -REG64( EQ_2_CME_SCOM_LFIR , RULL(0x12012400), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIR , RULL(0x12012000), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012000, -REG64( EQ_2_CME_SCOM_LFIR_AND , RULL(0x12012401), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIR_AND , RULL(0x12012001), SH_UNT_EQ_2 , SH_ACS_SCOM1_AND ); //DUPS: 12012001, -REG64( EQ_2_CME_SCOM_LFIR_OR , RULL(0x12012402), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIR_OR , RULL(0x12012002), SH_UNT_EQ_2 , SH_ACS_SCOM2_OR ); //DUPS: 12012002, -REG64( EQ_3_CME_SCOM_LFIR , RULL(0x13012400), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIR , RULL(0x13012000), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012000, -REG64( EQ_3_CME_SCOM_LFIR_AND , RULL(0x13012401), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIR_AND , RULL(0x13012001), SH_UNT_EQ_3 , SH_ACS_SCOM1_AND ); //DUPS: 13012001, -REG64( EQ_3_CME_SCOM_LFIR_OR , RULL(0x13012402), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIR_OR , RULL(0x13012002), SH_UNT_EQ_3 , SH_ACS_SCOM2_OR ); //DUPS: 13012002, -REG64( EQ_4_CME_SCOM_LFIR , RULL(0x14012400), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIR , RULL(0x14012000), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012000, -REG64( EQ_4_CME_SCOM_LFIR_AND , RULL(0x14012401), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIR_AND , RULL(0x14012001), SH_UNT_EQ_4 , SH_ACS_SCOM1_AND ); //DUPS: 14012001, -REG64( EQ_4_CME_SCOM_LFIR_OR , RULL(0x14012402), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIR_OR , RULL(0x14012002), SH_UNT_EQ_4 , SH_ACS_SCOM2_OR ); //DUPS: 14012002, -REG64( EQ_5_CME_SCOM_LFIR , RULL(0x15012400), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIR , RULL(0x15012000), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012000, -REG64( EQ_5_CME_SCOM_LFIR_AND , RULL(0x15012401), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIR_AND , RULL(0x15012001), SH_UNT_EQ_5 , SH_ACS_SCOM1_AND ); //DUPS: 15012001, -REG64( EQ_5_CME_SCOM_LFIR_OR , RULL(0x15012402), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIR_OR , RULL(0x15012002), SH_UNT_EQ_5 , SH_ACS_SCOM2_OR ); //DUPS: 15012002, REG64( EX_CME_SCOM_LFIR , RULL(0x10012000), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_CME_SCOM_LFIR_AND , RULL(0x10012001), SH_UNT_EX , SH_ACS_SCOM1_AND ); @@ -2584,19 +2462,19 @@ REG64( EX_11_CME_SCOM_LFIR , RULL(0x15012400 REG64( EX_11_CME_SCOM_LFIR_AND , RULL(0x15012401), SH_UNT_EX_11 , SH_ACS_SCOM1_AND ); REG64( EX_11_CME_SCOM_LFIR_OR , RULL(0x15012402), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); -REG64( EQ_CME_SCOM_LFIRACT0 , RULL(0x10012406), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIRACT0 , RULL(0x10012006), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012006, -REG64( EQ_0_CME_SCOM_LFIRACT0 , RULL(0x10012406), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIRACT0 , RULL(0x10012006), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012006, -REG64( EQ_1_CME_SCOM_LFIRACT0 , RULL(0x11012406), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIRACT0 , RULL(0x11012006), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012006, -REG64( EQ_2_CME_SCOM_LFIRACT0 , RULL(0x12012406), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIRACT0 , RULL(0x12012006), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012006, -REG64( EQ_3_CME_SCOM_LFIRACT0 , RULL(0x13012406), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIRACT0 , RULL(0x13012006), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012006, -REG64( EQ_4_CME_SCOM_LFIRACT0 , RULL(0x14012406), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIRACT0 , RULL(0x14012006), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012006, -REG64( EQ_5_CME_SCOM_LFIRACT0 , RULL(0x15012406), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIRACT0 , RULL(0x15012006), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012006, REG64( EX_CME_SCOM_LFIRACT0 , RULL(0x10012006), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CME_SCOM_LFIRACT0 , RULL(0x10012006), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -2612,19 +2490,19 @@ REG64( EX_9_CME_SCOM_LFIRACT0 , RULL(0x14012406 REG64( EX_10_CME_SCOM_LFIRACT0 , RULL(0x15012006), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); REG64( EX_11_CME_SCOM_LFIRACT0 , RULL(0x15012406), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_LFIRACT1 , RULL(0x10012407), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIRACT1 , RULL(0x10012007), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012007, -REG64( EQ_0_CME_SCOM_LFIRACT1 , RULL(0x10012407), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIRACT1 , RULL(0x10012007), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012007, -REG64( EQ_1_CME_SCOM_LFIRACT1 , RULL(0x11012407), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIRACT1 , RULL(0x11012007), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012007, -REG64( EQ_2_CME_SCOM_LFIRACT1 , RULL(0x12012407), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIRACT1 , RULL(0x12012007), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012007, -REG64( EQ_3_CME_SCOM_LFIRACT1 , RULL(0x13012407), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIRACT1 , RULL(0x13012007), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012007, -REG64( EQ_4_CME_SCOM_LFIRACT1 , RULL(0x14012407), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIRACT1 , RULL(0x14012007), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012007, -REG64( EQ_5_CME_SCOM_LFIRACT1 , RULL(0x15012407), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIRACT1 , RULL(0x15012007), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012007, REG64( EX_CME_SCOM_LFIRACT1 , RULL(0x10012007), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CME_SCOM_LFIRACT1 , RULL(0x10012007), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -2640,47 +2518,47 @@ REG64( EX_9_CME_SCOM_LFIRACT1 , RULL(0x14012407 REG64( EX_10_CME_SCOM_LFIRACT1 , RULL(0x15012007), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); REG64( EX_11_CME_SCOM_LFIRACT1 , RULL(0x15012407), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_LFIRMASK , RULL(0x10012403), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIRMASK , RULL(0x10012003), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012003, -REG64( EQ_CME_SCOM_LFIRMASK_AND , RULL(0x10012404), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIRMASK_AND , RULL(0x10012004), SH_UNT_EQ , SH_ACS_SCOM1_AND ); //DUPS: 10012004, -REG64( EQ_CME_SCOM_LFIRMASK_OR , RULL(0x10012405), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LFIRMASK_OR , RULL(0x10012005), SH_UNT_EQ , SH_ACS_SCOM2_OR ); //DUPS: 10012005, -REG64( EQ_0_CME_SCOM_LFIRMASK , RULL(0x10012403), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIRMASK , RULL(0x10012003), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012003, -REG64( EQ_0_CME_SCOM_LFIRMASK_AND , RULL(0x10012404), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIRMASK_AND , RULL(0x10012004), SH_UNT_EQ_0 , SH_ACS_SCOM1_AND ); //DUPS: 10012004, -REG64( EQ_0_CME_SCOM_LFIRMASK_OR , RULL(0x10012405), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_LFIRMASK_OR , RULL(0x10012005), SH_UNT_EQ_0 , SH_ACS_SCOM2_OR ); //DUPS: 10012005, -REG64( EQ_1_CME_SCOM_LFIRMASK , RULL(0x11012403), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIRMASK , RULL(0x11012003), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012003, -REG64( EQ_1_CME_SCOM_LFIRMASK_AND , RULL(0x11012404), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIRMASK_AND , RULL(0x11012004), SH_UNT_EQ_1 , SH_ACS_SCOM1_AND ); //DUPS: 11012004, -REG64( EQ_1_CME_SCOM_LFIRMASK_OR , RULL(0x11012405), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_LFIRMASK_OR , RULL(0x11012005), SH_UNT_EQ_1 , SH_ACS_SCOM2_OR ); //DUPS: 11012005, -REG64( EQ_2_CME_SCOM_LFIRMASK , RULL(0x12012403), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIRMASK , RULL(0x12012003), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012003, -REG64( EQ_2_CME_SCOM_LFIRMASK_AND , RULL(0x12012404), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIRMASK_AND , RULL(0x12012004), SH_UNT_EQ_2 , SH_ACS_SCOM1_AND ); //DUPS: 12012004, -REG64( EQ_2_CME_SCOM_LFIRMASK_OR , RULL(0x12012405), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_LFIRMASK_OR , RULL(0x12012005), SH_UNT_EQ_2 , SH_ACS_SCOM2_OR ); //DUPS: 12012005, -REG64( EQ_3_CME_SCOM_LFIRMASK , RULL(0x13012403), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIRMASK , RULL(0x13012003), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012003, -REG64( EQ_3_CME_SCOM_LFIRMASK_AND , RULL(0x13012404), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIRMASK_AND , RULL(0x13012004), SH_UNT_EQ_3 , SH_ACS_SCOM1_AND ); //DUPS: 13012004, -REG64( EQ_3_CME_SCOM_LFIRMASK_OR , RULL(0x13012405), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_LFIRMASK_OR , RULL(0x13012005), SH_UNT_EQ_3 , SH_ACS_SCOM2_OR ); //DUPS: 13012005, -REG64( EQ_4_CME_SCOM_LFIRMASK , RULL(0x14012403), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIRMASK , RULL(0x14012003), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012003, -REG64( EQ_4_CME_SCOM_LFIRMASK_AND , RULL(0x14012404), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIRMASK_AND , RULL(0x14012004), SH_UNT_EQ_4 , SH_ACS_SCOM1_AND ); //DUPS: 14012004, -REG64( EQ_4_CME_SCOM_LFIRMASK_OR , RULL(0x14012405), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_LFIRMASK_OR , RULL(0x14012005), SH_UNT_EQ_4 , SH_ACS_SCOM2_OR ); //DUPS: 14012005, -REG64( EQ_5_CME_SCOM_LFIRMASK , RULL(0x15012403), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIRMASK , RULL(0x15012003), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012003, -REG64( EQ_5_CME_SCOM_LFIRMASK_AND , RULL(0x15012404), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIRMASK_AND , RULL(0x15012004), SH_UNT_EQ_5 , SH_ACS_SCOM1_AND ); //DUPS: 15012004, -REG64( EQ_5_CME_SCOM_LFIRMASK_OR , RULL(0x15012405), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_LFIRMASK_OR , RULL(0x15012005), SH_UNT_EQ_5 , SH_ACS_SCOM2_OR ); //DUPS: 15012005, REG64( EX_CME_SCOM_LFIRMASK , RULL(0x10012003), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_CME_SCOM_LFIRMASK_AND , RULL(0x10012004), SH_UNT_EX , SH_ACS_SCOM1_AND ); @@ -2722,19 +2600,179 @@ REG64( EX_11_CME_SCOM_LFIRMASK , RULL(0x15012403 REG64( EX_11_CME_SCOM_LFIRMASK_AND , RULL(0x15012404), SH_UNT_EX_11 , SH_ACS_SCOM1_AND ); REG64( EX_11_CME_SCOM_LFIRMASK_OR , RULL(0x15012405), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); -REG64( EQ_CME_SCOM_PMCRS0 , RULL(0x10012442), SH_UNT_EQ , +REG64( EQ_CME_SCOM_LMCR_SCOM , RULL(0x1001203A), SH_UNT_EQ , + SH_ACS_SCOM ); //DUPS: 1001203A, +REG64( EQ_CME_SCOM_LMCR_SCOM1 , RULL(0x1001203B), SH_UNT_EQ , + SH_ACS_SCOM1 ); //DUPS: 1001203B, +REG64( EQ_CME_SCOM_LMCR_SCOM2 , RULL(0x1001203C), SH_UNT_EQ , + SH_ACS_SCOM2 ); //DUPS: 1001203C, +REG64( EQ_0_CME_SCOM_LMCR_SCOM , RULL(0x1001203A), SH_UNT_EQ_0 , + SH_ACS_SCOM ); //DUPS: 1001203A, +REG64( EQ_0_CME_SCOM_LMCR_SCOM1 , RULL(0x1001203B), SH_UNT_EQ_0 , + SH_ACS_SCOM1 ); //DUPS: 1001203B, +REG64( EQ_0_CME_SCOM_LMCR_SCOM2 , RULL(0x1001203C), SH_UNT_EQ_0 , + SH_ACS_SCOM2 ); //DUPS: 1001203C, +REG64( EQ_1_CME_SCOM_LMCR_SCOM , RULL(0x1101203A), SH_UNT_EQ_1 , + SH_ACS_SCOM ); //DUPS: 1101203A, +REG64( EQ_1_CME_SCOM_LMCR_SCOM1 , RULL(0x1101203B), SH_UNT_EQ_1 , + SH_ACS_SCOM1 ); //DUPS: 1101203B, +REG64( EQ_1_CME_SCOM_LMCR_SCOM2 , RULL(0x1101203C), SH_UNT_EQ_1 , + SH_ACS_SCOM2 ); //DUPS: 1101203C, +REG64( EQ_2_CME_SCOM_LMCR_SCOM , RULL(0x1201203A), SH_UNT_EQ_2 , + SH_ACS_SCOM ); //DUPS: 1201203A, +REG64( EQ_2_CME_SCOM_LMCR_SCOM1 , RULL(0x1201203B), SH_UNT_EQ_2 , + SH_ACS_SCOM1 ); //DUPS: 1201203B, +REG64( EQ_2_CME_SCOM_LMCR_SCOM2 , RULL(0x1201203C), SH_UNT_EQ_2 , + SH_ACS_SCOM2 ); //DUPS: 1201203C, +REG64( EQ_3_CME_SCOM_LMCR_SCOM , RULL(0x1301203A), SH_UNT_EQ_3 , + SH_ACS_SCOM ); //DUPS: 1301203A, +REG64( EQ_3_CME_SCOM_LMCR_SCOM1 , RULL(0x1301203B), SH_UNT_EQ_3 , + SH_ACS_SCOM1 ); //DUPS: 1301203B, +REG64( EQ_3_CME_SCOM_LMCR_SCOM2 , RULL(0x1301203C), SH_UNT_EQ_3 , + SH_ACS_SCOM2 ); //DUPS: 1301203C, +REG64( EQ_4_CME_SCOM_LMCR_SCOM , RULL(0x1401203A), SH_UNT_EQ_4 , + SH_ACS_SCOM ); //DUPS: 1401203A, +REG64( EQ_4_CME_SCOM_LMCR_SCOM1 , RULL(0x1401203B), SH_UNT_EQ_4 , + SH_ACS_SCOM1 ); //DUPS: 1401203B, +REG64( EQ_4_CME_SCOM_LMCR_SCOM2 , RULL(0x1401203C), SH_UNT_EQ_4 , + SH_ACS_SCOM2 ); //DUPS: 1401203C, +REG64( EQ_5_CME_SCOM_LMCR_SCOM , RULL(0x1501203A), SH_UNT_EQ_5 , + SH_ACS_SCOM ); //DUPS: 1501203A, +REG64( EQ_5_CME_SCOM_LMCR_SCOM1 , RULL(0x1501203B), SH_UNT_EQ_5 , + SH_ACS_SCOM1 ); //DUPS: 1501203B, +REG64( EQ_5_CME_SCOM_LMCR_SCOM2 , RULL(0x1501203C), SH_UNT_EQ_5 , + SH_ACS_SCOM2 ); //DUPS: 1501203C, +REG64( EX_CME_SCOM_LMCR_PPE , RULL(0x1090101A0), SH_UNT_EX , + SH_ACS_PPE ); +REG64( EX_CME_SCOM_LMCR_PPE1 , RULL(0x1090101B8), SH_UNT_EX , + SH_ACS_PPE1 ); +REG64( EX_CME_SCOM_LMCR_PPE2 , RULL(0x1090101B0), SH_UNT_EX , + SH_ACS_PPE2 ); +REG64( EX_CME_SCOM_LMCR_SCOM , RULL(0x1001203A), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_CME_SCOM_LMCR_SCOM1 , RULL(0x1001203B), SH_UNT_EX , SH_ACS_SCOM1 ); +REG64( EX_CME_SCOM_LMCR_SCOM2 , RULL(0x1001203C), SH_UNT_EX , SH_ACS_SCOM2 ); +REG64( EX_0_CME_SCOM_LMCR_PPE , RULL(0x1090101A0), SH_UNT_EX_0 , + SH_ACS_PPE ); +REG64( EX_0_CME_SCOM_LMCR_PPE1 , RULL(0x1090101B8), SH_UNT_EX_0 , + SH_ACS_PPE1 ); +REG64( EX_0_CME_SCOM_LMCR_PPE2 , RULL(0x1090101B0), SH_UNT_EX_0 , + SH_ACS_PPE2 ); +REG64( EX_0_CME_SCOM_LMCR_SCOM , RULL(0x1001203A), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_0_CME_SCOM_LMCR_SCOM1 , RULL(0x1001203B), SH_UNT_EX_0 , SH_ACS_SCOM1 ); +REG64( EX_0_CME_SCOM_LMCR_SCOM2 , RULL(0x1001203C), SH_UNT_EX_0 , SH_ACS_SCOM2 ); +REG64( EX_1_CME_SCOM_LMCR_PPE , RULL(0x1090201A0), SH_UNT_EX_1 , + SH_ACS_PPE ); +REG64( EX_1_CME_SCOM_LMCR_PPE1 , RULL(0x1090201B8), SH_UNT_EX_1 , + SH_ACS_PPE1 ); +REG64( EX_1_CME_SCOM_LMCR_PPE2 , RULL(0x1090201B0), SH_UNT_EX_1 , + SH_ACS_PPE2 ); +REG64( EX_1_CME_SCOM_LMCR_SCOM , RULL(0x1001243A), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_1_CME_SCOM_LMCR_SCOM1 , RULL(0x1001243B), SH_UNT_EX_1 , SH_ACS_SCOM1 ); +REG64( EX_1_CME_SCOM_LMCR_SCOM2 , RULL(0x1001243C), SH_UNT_EX_1 , SH_ACS_SCOM2 ); +REG64( EX_2_CME_SCOM_LMCR_PPE , RULL(0x10A0101A0), SH_UNT_EX_2 , + SH_ACS_PPE ); +REG64( EX_2_CME_SCOM_LMCR_PPE1 , RULL(0x10A0101B8), SH_UNT_EX_2 , + SH_ACS_PPE1 ); +REG64( EX_2_CME_SCOM_LMCR_PPE2 , RULL(0x10A0101B0), SH_UNT_EX_2 , + SH_ACS_PPE2 ); +REG64( EX_2_CME_SCOM_LMCR_SCOM , RULL(0x1101203A), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_2_CME_SCOM_LMCR_SCOM1 , RULL(0x1101203B), SH_UNT_EX_2 , SH_ACS_SCOM1 ); +REG64( EX_2_CME_SCOM_LMCR_SCOM2 , RULL(0x1101203C), SH_UNT_EX_2 , SH_ACS_SCOM2 ); +REG64( EX_3_CME_SCOM_LMCR_PPE , RULL(0x10A0201A0), SH_UNT_EX_3 , + SH_ACS_PPE ); +REG64( EX_3_CME_SCOM_LMCR_PPE1 , RULL(0x10A0201B8), SH_UNT_EX_3 , + SH_ACS_PPE1 ); +REG64( EX_3_CME_SCOM_LMCR_PPE2 , RULL(0x10A0201B0), SH_UNT_EX_3 , + SH_ACS_PPE2 ); +REG64( EX_3_CME_SCOM_LMCR_SCOM , RULL(0x1101243A), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_3_CME_SCOM_LMCR_SCOM1 , RULL(0x1101243B), SH_UNT_EX_3 , SH_ACS_SCOM1 ); +REG64( EX_3_CME_SCOM_LMCR_SCOM2 , RULL(0x1101243C), SH_UNT_EX_3 , SH_ACS_SCOM2 ); +REG64( EX_4_CME_SCOM_LMCR_PPE , RULL(0x10B0101A0), SH_UNT_EX_4 , + SH_ACS_PPE ); +REG64( EX_4_CME_SCOM_LMCR_PPE1 , RULL(0x10B0101B8), SH_UNT_EX_4 , + SH_ACS_PPE1 ); +REG64( EX_4_CME_SCOM_LMCR_PPE2 , RULL(0x10B0101B0), SH_UNT_EX_4 , + SH_ACS_PPE2 ); +REG64( EX_4_CME_SCOM_LMCR_SCOM , RULL(0x1201203A), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_4_CME_SCOM_LMCR_SCOM1 , RULL(0x1201203B), SH_UNT_EX_4 , SH_ACS_SCOM1 ); +REG64( EX_4_CME_SCOM_LMCR_SCOM2 , RULL(0x1201203C), SH_UNT_EX_4 , SH_ACS_SCOM2 ); +REG64( EX_5_CME_SCOM_LMCR_PPE , RULL(0x10B0201A0), SH_UNT_EX_5 , + SH_ACS_PPE ); +REG64( EX_5_CME_SCOM_LMCR_PPE1 , RULL(0x10B0201B8), SH_UNT_EX_5 , + SH_ACS_PPE1 ); +REG64( EX_5_CME_SCOM_LMCR_PPE2 , RULL(0x10B0201B0), SH_UNT_EX_5 , + SH_ACS_PPE2 ); +REG64( EX_5_CME_SCOM_LMCR_SCOM , RULL(0x1201243A), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_5_CME_SCOM_LMCR_SCOM1 , RULL(0x1201243B), SH_UNT_EX_5 , SH_ACS_SCOM1 ); +REG64( EX_5_CME_SCOM_LMCR_SCOM2 , RULL(0x1201243C), SH_UNT_EX_5 , SH_ACS_SCOM2 ); +REG64( EX_6_CME_SCOM_LMCR_PPE , RULL(0x10C0101A0), SH_UNT_EX_6 , + SH_ACS_PPE ); +REG64( EX_6_CME_SCOM_LMCR_PPE1 , RULL(0x10C0101B8), SH_UNT_EX_6 , + SH_ACS_PPE1 ); +REG64( EX_6_CME_SCOM_LMCR_PPE2 , RULL(0x10C0101B0), SH_UNT_EX_6 , + SH_ACS_PPE2 ); +REG64( EX_6_CME_SCOM_LMCR_SCOM , RULL(0x1301203A), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_6_CME_SCOM_LMCR_SCOM1 , RULL(0x1301203B), SH_UNT_EX_6 , SH_ACS_SCOM1 ); +REG64( EX_6_CME_SCOM_LMCR_SCOM2 , RULL(0x1301203C), SH_UNT_EX_6 , SH_ACS_SCOM2 ); +REG64( EX_7_CME_SCOM_LMCR_PPE , RULL(0x10C0201A0), SH_UNT_EX_7 , + SH_ACS_PPE ); +REG64( EX_7_CME_SCOM_LMCR_PPE1 , RULL(0x10C0201B8), SH_UNT_EX_7 , + SH_ACS_PPE1 ); +REG64( EX_7_CME_SCOM_LMCR_PPE2 , RULL(0x10C0201B0), SH_UNT_EX_7 , + SH_ACS_PPE2 ); +REG64( EX_7_CME_SCOM_LMCR_SCOM , RULL(0x1301243A), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_7_CME_SCOM_LMCR_SCOM1 , RULL(0x1301243B), SH_UNT_EX_7 , SH_ACS_SCOM1 ); +REG64( EX_7_CME_SCOM_LMCR_SCOM2 , RULL(0x1301243C), SH_UNT_EX_7 , SH_ACS_SCOM2 ); +REG64( EX_8_CME_SCOM_LMCR_PPE , RULL(0x10D0101A0), SH_UNT_EX_8 , + SH_ACS_PPE ); +REG64( EX_8_CME_SCOM_LMCR_PPE1 , RULL(0x10D0101B8), SH_UNT_EX_8 , + SH_ACS_PPE1 ); +REG64( EX_8_CME_SCOM_LMCR_PPE2 , RULL(0x10D0101B0), SH_UNT_EX_8 , + SH_ACS_PPE2 ); +REG64( EX_8_CME_SCOM_LMCR_SCOM , RULL(0x1401203A), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_8_CME_SCOM_LMCR_SCOM1 , RULL(0x1401203B), SH_UNT_EX_8 , SH_ACS_SCOM1 ); +REG64( EX_8_CME_SCOM_LMCR_SCOM2 , RULL(0x1401203C), SH_UNT_EX_8 , SH_ACS_SCOM2 ); +REG64( EX_9_CME_SCOM_LMCR_PPE , RULL(0x10D0201A0), SH_UNT_EX_9 , + SH_ACS_PPE ); +REG64( EX_9_CME_SCOM_LMCR_PPE1 , RULL(0x10D0201B8), SH_UNT_EX_9 , + SH_ACS_PPE1 ); +REG64( EX_9_CME_SCOM_LMCR_PPE2 , RULL(0x10D0201B0), SH_UNT_EX_9 , + SH_ACS_PPE2 ); +REG64( EX_9_CME_SCOM_LMCR_SCOM , RULL(0x1401243A), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_9_CME_SCOM_LMCR_SCOM1 , RULL(0x1401243B), SH_UNT_EX_9 , SH_ACS_SCOM1 ); +REG64( EX_9_CME_SCOM_LMCR_SCOM2 , RULL(0x1401243C), SH_UNT_EX_9 , SH_ACS_SCOM2 ); +REG64( EX_10_CME_SCOM_LMCR_PPE , RULL(0x10E0101A0), SH_UNT_EX_10 , + SH_ACS_PPE ); +REG64( EX_10_CME_SCOM_LMCR_PPE1 , RULL(0x10E0101B8), SH_UNT_EX_10 , + SH_ACS_PPE1 ); +REG64( EX_10_CME_SCOM_LMCR_PPE2 , RULL(0x10E0101B0), SH_UNT_EX_10 , + SH_ACS_PPE2 ); +REG64( EX_10_CME_SCOM_LMCR_SCOM , RULL(0x1501203A), SH_UNT_EX_10 , SH_ACS_SCOM ); +REG64( EX_10_CME_SCOM_LMCR_SCOM1 , RULL(0x1501203B), SH_UNT_EX_10 , SH_ACS_SCOM1 ); +REG64( EX_10_CME_SCOM_LMCR_SCOM2 , RULL(0x1501203C), SH_UNT_EX_10 , SH_ACS_SCOM2 ); +REG64( EX_11_CME_SCOM_LMCR_PPE , RULL(0x10E0201A0), SH_UNT_EX_11 , + SH_ACS_PPE ); +REG64( EX_11_CME_SCOM_LMCR_PPE1 , RULL(0x10E0201B8), SH_UNT_EX_11 , + SH_ACS_PPE1 ); +REG64( EX_11_CME_SCOM_LMCR_PPE2 , RULL(0x10E0201B0), SH_UNT_EX_11 , + SH_ACS_PPE2 ); +REG64( EX_11_CME_SCOM_LMCR_SCOM , RULL(0x1501243A), SH_UNT_EX_11 , SH_ACS_SCOM ); +REG64( EX_11_CME_SCOM_LMCR_SCOM1 , RULL(0x1501243B), SH_UNT_EX_11 , SH_ACS_SCOM1 ); +REG64( EX_11_CME_SCOM_LMCR_SCOM2 , RULL(0x1501243C), SH_UNT_EX_11 , SH_ACS_SCOM2 ); + +REG64( EQ_CME_SCOM_PMCRS0 , RULL(0x10012042), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012042, -REG64( EQ_0_CME_SCOM_PMCRS0 , RULL(0x10012442), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PMCRS0 , RULL(0x10012042), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012042, -REG64( EQ_1_CME_SCOM_PMCRS0 , RULL(0x11012442), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PMCRS0 , RULL(0x11012042), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012042, -REG64( EQ_2_CME_SCOM_PMCRS0 , RULL(0x12012442), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PMCRS0 , RULL(0x12012042), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012042, -REG64( EQ_3_CME_SCOM_PMCRS0 , RULL(0x13012442), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PMCRS0 , RULL(0x13012042), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012042, -REG64( EQ_4_CME_SCOM_PMCRS0 , RULL(0x14012442), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PMCRS0 , RULL(0x14012042), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012042, -REG64( EQ_5_CME_SCOM_PMCRS0 , RULL(0x15012442), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PMCRS0 , RULL(0x15012042), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012042, REG64( EX_CME_SCOM_PMCRS0_PPE , RULL(0x109010240), SH_UNT_EX , SH_ACS_PPE ); @@ -2776,19 +2814,19 @@ REG64( EX_11_CME_SCOM_PMCRS0_PPE , RULL(0x10E02024 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PMCRS0_SCOM , RULL(0x15012442), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PMCRS1 , RULL(0x10012443), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PMCRS1 , RULL(0x10012043), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012043, -REG64( EQ_0_CME_SCOM_PMCRS1 , RULL(0x10012443), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PMCRS1 , RULL(0x10012043), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012043, -REG64( EQ_1_CME_SCOM_PMCRS1 , RULL(0x11012443), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PMCRS1 , RULL(0x11012043), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012043, -REG64( EQ_2_CME_SCOM_PMCRS1 , RULL(0x12012443), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PMCRS1 , RULL(0x12012043), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012043, -REG64( EQ_3_CME_SCOM_PMCRS1 , RULL(0x13012443), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PMCRS1 , RULL(0x13012043), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012043, -REG64( EQ_4_CME_SCOM_PMCRS1 , RULL(0x14012443), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PMCRS1 , RULL(0x14012043), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012043, -REG64( EQ_5_CME_SCOM_PMCRS1 , RULL(0x15012443), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PMCRS1 , RULL(0x15012043), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012043, REG64( EX_CME_SCOM_PMCRS1_PPE , RULL(0x109010260), SH_UNT_EX , SH_ACS_PPE ); @@ -2830,19 +2868,19 @@ REG64( EX_11_CME_SCOM_PMCRS1_PPE , RULL(0x10E02026 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PMCRS1_SCOM , RULL(0x15012443), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PMSRS0 , RULL(0x10012440), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PMSRS0 , RULL(0x10012040), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012040, -REG64( EQ_0_CME_SCOM_PMSRS0 , RULL(0x10012440), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PMSRS0 , RULL(0x10012040), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012040, -REG64( EQ_1_CME_SCOM_PMSRS0 , RULL(0x11012440), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PMSRS0 , RULL(0x11012040), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012040, -REG64( EQ_2_CME_SCOM_PMSRS0 , RULL(0x12012440), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PMSRS0 , RULL(0x12012040), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012040, -REG64( EQ_3_CME_SCOM_PMSRS0 , RULL(0x13012440), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PMSRS0 , RULL(0x13012040), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012040, -REG64( EQ_4_CME_SCOM_PMSRS0 , RULL(0x14012440), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PMSRS0 , RULL(0x14012040), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012040, -REG64( EQ_5_CME_SCOM_PMSRS0 , RULL(0x15012440), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PMSRS0 , RULL(0x15012040), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012040, REG64( EX_CME_SCOM_PMSRS0_PPE , RULL(0x109010200), SH_UNT_EX , SH_ACS_PPE ); @@ -2884,19 +2922,19 @@ REG64( EX_11_CME_SCOM_PMSRS0_PPE , RULL(0x10E02020 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PMSRS0_SCOM , RULL(0x15012440), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PMSRS1 , RULL(0x10012441), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PMSRS1 , RULL(0x10012041), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012041, -REG64( EQ_0_CME_SCOM_PMSRS1 , RULL(0x10012441), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PMSRS1 , RULL(0x10012041), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012041, -REG64( EQ_1_CME_SCOM_PMSRS1 , RULL(0x11012441), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PMSRS1 , RULL(0x11012041), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012041, -REG64( EQ_2_CME_SCOM_PMSRS1 , RULL(0x12012441), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PMSRS1 , RULL(0x12012041), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012041, -REG64( EQ_3_CME_SCOM_PMSRS1 , RULL(0x13012441), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PMSRS1 , RULL(0x13012041), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012041, -REG64( EQ_4_CME_SCOM_PMSRS1 , RULL(0x14012441), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PMSRS1 , RULL(0x14012041), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012041, -REG64( EQ_5_CME_SCOM_PMSRS1 , RULL(0x15012441), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PMSRS1 , RULL(0x15012041), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012041, REG64( EX_CME_SCOM_PMSRS1_PPE , RULL(0x109010220), SH_UNT_EX , SH_ACS_PPE ); @@ -2938,19 +2976,19 @@ REG64( EX_11_CME_SCOM_PMSRS1_PPE , RULL(0x10E02022 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PMSRS1_SCOM , RULL(0x15012441), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS00 , RULL(0x10012444), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS00 , RULL(0x10012044), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012044, -REG64( EQ_0_CME_SCOM_PSCRS00 , RULL(0x10012444), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS00 , RULL(0x10012044), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012044, -REG64( EQ_1_CME_SCOM_PSCRS00 , RULL(0x11012444), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS00 , RULL(0x11012044), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012044, -REG64( EQ_2_CME_SCOM_PSCRS00 , RULL(0x12012444), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS00 , RULL(0x12012044), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012044, -REG64( EQ_3_CME_SCOM_PSCRS00 , RULL(0x13012444), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS00 , RULL(0x13012044), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012044, -REG64( EQ_4_CME_SCOM_PSCRS00 , RULL(0x14012444), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS00 , RULL(0x14012044), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012044, -REG64( EQ_5_CME_SCOM_PSCRS00 , RULL(0x15012444), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS00 , RULL(0x15012044), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012044, REG64( EX_CME_SCOM_PSCRS00_PPE , RULL(0x109010300), SH_UNT_EX , SH_ACS_PPE ); @@ -2992,19 +3030,19 @@ REG64( EX_11_CME_SCOM_PSCRS00_PPE , RULL(0x10E02030 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS00_SCOM , RULL(0x15012444), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS01 , RULL(0x10012445), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS01 , RULL(0x10012045), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012045, -REG64( EQ_0_CME_SCOM_PSCRS01 , RULL(0x10012445), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS01 , RULL(0x10012045), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012045, -REG64( EQ_1_CME_SCOM_PSCRS01 , RULL(0x11012445), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS01 , RULL(0x11012045), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012045, -REG64( EQ_2_CME_SCOM_PSCRS01 , RULL(0x12012445), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS01 , RULL(0x12012045), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012045, -REG64( EQ_3_CME_SCOM_PSCRS01 , RULL(0x13012445), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS01 , RULL(0x13012045), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012045, -REG64( EQ_4_CME_SCOM_PSCRS01 , RULL(0x14012445), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS01 , RULL(0x14012045), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012045, -REG64( EQ_5_CME_SCOM_PSCRS01 , RULL(0x15012445), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS01 , RULL(0x15012045), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012045, REG64( EX_CME_SCOM_PSCRS01_PPE , RULL(0x109010320), SH_UNT_EX , SH_ACS_PPE ); @@ -3046,19 +3084,19 @@ REG64( EX_11_CME_SCOM_PSCRS01_PPE , RULL(0x10E02032 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS01_SCOM , RULL(0x15012445), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS02 , RULL(0x10012446), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS02 , RULL(0x10012046), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012046, -REG64( EQ_0_CME_SCOM_PSCRS02 , RULL(0x10012446), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS02 , RULL(0x10012046), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012046, -REG64( EQ_1_CME_SCOM_PSCRS02 , RULL(0x11012446), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS02 , RULL(0x11012046), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012046, -REG64( EQ_2_CME_SCOM_PSCRS02 , RULL(0x12012446), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS02 , RULL(0x12012046), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012046, -REG64( EQ_3_CME_SCOM_PSCRS02 , RULL(0x13012446), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS02 , RULL(0x13012046), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012046, -REG64( EQ_4_CME_SCOM_PSCRS02 , RULL(0x14012446), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS02 , RULL(0x14012046), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012046, -REG64( EQ_5_CME_SCOM_PSCRS02 , RULL(0x15012446), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS02 , RULL(0x15012046), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012046, REG64( EX_CME_SCOM_PSCRS02_PPE , RULL(0x109010340), SH_UNT_EX , SH_ACS_PPE ); @@ -3100,19 +3138,19 @@ REG64( EX_11_CME_SCOM_PSCRS02_PPE , RULL(0x10E02034 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS02_SCOM , RULL(0x15012446), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS03 , RULL(0x10012447), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS03 , RULL(0x10012047), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012047, -REG64( EQ_0_CME_SCOM_PSCRS03 , RULL(0x10012447), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS03 , RULL(0x10012047), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012047, -REG64( EQ_1_CME_SCOM_PSCRS03 , RULL(0x11012447), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS03 , RULL(0x11012047), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012047, -REG64( EQ_2_CME_SCOM_PSCRS03 , RULL(0x12012447), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS03 , RULL(0x12012047), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012047, -REG64( EQ_3_CME_SCOM_PSCRS03 , RULL(0x13012447), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS03 , RULL(0x13012047), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012047, -REG64( EQ_4_CME_SCOM_PSCRS03 , RULL(0x14012447), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS03 , RULL(0x14012047), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012047, -REG64( EQ_5_CME_SCOM_PSCRS03 , RULL(0x15012447), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS03 , RULL(0x15012047), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012047, REG64( EX_CME_SCOM_PSCRS03_PPE , RULL(0x109010360), SH_UNT_EX , SH_ACS_PPE ); @@ -3154,19 +3192,19 @@ REG64( EX_11_CME_SCOM_PSCRS03_PPE , RULL(0x10E02036 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS03_SCOM , RULL(0x15012447), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS10 , RULL(0x10012448), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS10 , RULL(0x10012048), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012048, -REG64( EQ_0_CME_SCOM_PSCRS10 , RULL(0x10012448), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS10 , RULL(0x10012048), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012048, -REG64( EQ_1_CME_SCOM_PSCRS10 , RULL(0x11012448), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS10 , RULL(0x11012048), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012048, -REG64( EQ_2_CME_SCOM_PSCRS10 , RULL(0x12012448), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS10 , RULL(0x12012048), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012048, -REG64( EQ_3_CME_SCOM_PSCRS10 , RULL(0x13012448), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS10 , RULL(0x13012048), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012048, -REG64( EQ_4_CME_SCOM_PSCRS10 , RULL(0x14012448), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS10 , RULL(0x14012048), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012048, -REG64( EQ_5_CME_SCOM_PSCRS10 , RULL(0x15012448), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS10 , RULL(0x15012048), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012048, REG64( EX_CME_SCOM_PSCRS10_PPE , RULL(0x109010380), SH_UNT_EX , SH_ACS_PPE ); @@ -3208,19 +3246,19 @@ REG64( EX_11_CME_SCOM_PSCRS10_PPE , RULL(0x10E02038 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS10_SCOM , RULL(0x15012448), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS11 , RULL(0x10012449), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS11 , RULL(0x10012049), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012049, -REG64( EQ_0_CME_SCOM_PSCRS11 , RULL(0x10012449), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS11 , RULL(0x10012049), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012049, -REG64( EQ_1_CME_SCOM_PSCRS11 , RULL(0x11012449), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS11 , RULL(0x11012049), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012049, -REG64( EQ_2_CME_SCOM_PSCRS11 , RULL(0x12012449), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS11 , RULL(0x12012049), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012049, -REG64( EQ_3_CME_SCOM_PSCRS11 , RULL(0x13012449), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS11 , RULL(0x13012049), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012049, -REG64( EQ_4_CME_SCOM_PSCRS11 , RULL(0x14012449), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS11 , RULL(0x14012049), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012049, -REG64( EQ_5_CME_SCOM_PSCRS11 , RULL(0x15012449), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS11 , RULL(0x15012049), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012049, REG64( EX_CME_SCOM_PSCRS11_PPE , RULL(0x1090103A0), SH_UNT_EX , SH_ACS_PPE ); @@ -3262,19 +3300,19 @@ REG64( EX_11_CME_SCOM_PSCRS11_PPE , RULL(0x10E0203A SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS11_SCOM , RULL(0x15012449), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS12 , RULL(0x1001244A), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS12 , RULL(0x1001204A), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001204A, -REG64( EQ_0_CME_SCOM_PSCRS12 , RULL(0x1001244A), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS12 , RULL(0x1001204A), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001204A, -REG64( EQ_1_CME_SCOM_PSCRS12 , RULL(0x1101244A), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS12 , RULL(0x1101204A), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101204A, -REG64( EQ_2_CME_SCOM_PSCRS12 , RULL(0x1201244A), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS12 , RULL(0x1201204A), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201204A, -REG64( EQ_3_CME_SCOM_PSCRS12 , RULL(0x1301244A), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS12 , RULL(0x1301204A), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301204A, -REG64( EQ_4_CME_SCOM_PSCRS12 , RULL(0x1401244A), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS12 , RULL(0x1401204A), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401204A, -REG64( EQ_5_CME_SCOM_PSCRS12 , RULL(0x1501244A), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS12 , RULL(0x1501204A), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501204A, REG64( EX_CME_SCOM_PSCRS12_PPE , RULL(0x1090103C0), SH_UNT_EX , SH_ACS_PPE ); @@ -3316,19 +3354,19 @@ REG64( EX_11_CME_SCOM_PSCRS12_PPE , RULL(0x10E0203C SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS12_SCOM , RULL(0x1501244A), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_PSCRS13 , RULL(0x1001244B), SH_UNT_EQ , +REG64( EQ_CME_SCOM_PSCRS13 , RULL(0x1001204B), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001204B, -REG64( EQ_0_CME_SCOM_PSCRS13 , RULL(0x1001244B), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_PSCRS13 , RULL(0x1001204B), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001204B, -REG64( EQ_1_CME_SCOM_PSCRS13 , RULL(0x1101244B), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_PSCRS13 , RULL(0x1101204B), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101204B, -REG64( EQ_2_CME_SCOM_PSCRS13 , RULL(0x1201244B), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_PSCRS13 , RULL(0x1201204B), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201204B, -REG64( EQ_3_CME_SCOM_PSCRS13 , RULL(0x1301244B), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_PSCRS13 , RULL(0x1301204B), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301204B, -REG64( EQ_4_CME_SCOM_PSCRS13 , RULL(0x1401244B), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_PSCRS13 , RULL(0x1401204B), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401204B, -REG64( EQ_5_CME_SCOM_PSCRS13 , RULL(0x1501244B), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_PSCRS13 , RULL(0x1501204B), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501204B, REG64( EX_CME_SCOM_PSCRS13_PPE , RULL(0x1090103E0), SH_UNT_EX , SH_ACS_PPE ); @@ -3370,19 +3408,19 @@ REG64( EX_11_CME_SCOM_PSCRS13_PPE , RULL(0x10E0203E SH_ACS_PPE ); REG64( EX_11_CME_SCOM_PSCRS13_SCOM , RULL(0x1501244B), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_QFMR , RULL(0x10012432), SH_UNT_EQ , +REG64( EQ_CME_SCOM_QFMR , RULL(0x10012032), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012032, -REG64( EQ_0_CME_SCOM_QFMR , RULL(0x10012432), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_QFMR , RULL(0x10012032), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012032, -REG64( EQ_1_CME_SCOM_QFMR , RULL(0x11012432), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_QFMR , RULL(0x11012032), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012032, -REG64( EQ_2_CME_SCOM_QFMR , RULL(0x12012432), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_QFMR , RULL(0x12012032), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012032, -REG64( EQ_3_CME_SCOM_QFMR , RULL(0x13012432), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_QFMR , RULL(0x13012032), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012032, -REG64( EQ_4_CME_SCOM_QFMR , RULL(0x14012432), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_QFMR , RULL(0x14012032), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012032, -REG64( EQ_5_CME_SCOM_QFMR , RULL(0x15012432), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_QFMR , RULL(0x15012032), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012032, REG64( EX_CME_SCOM_QFMR_PPE , RULL(0x109010140), SH_UNT_EX , SH_ACS_PPE ); @@ -3424,19 +3462,19 @@ REG64( EX_11_CME_SCOM_QFMR_PPE , RULL(0x10E02014 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_QFMR_SCOM , RULL(0x15012432), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_QIDSR , RULL(0x1001242F), SH_UNT_EQ , +REG64( EQ_CME_SCOM_QIDSR , RULL(0x1001202F), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001202F, -REG64( EQ_0_CME_SCOM_QIDSR , RULL(0x1001242F), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_QIDSR , RULL(0x1001202F), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001202F, -REG64( EQ_1_CME_SCOM_QIDSR , RULL(0x1101242F), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_QIDSR , RULL(0x1101202F), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101202F, -REG64( EQ_2_CME_SCOM_QIDSR , RULL(0x1201242F), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_QIDSR , RULL(0x1201202F), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201202F, -REG64( EQ_3_CME_SCOM_QIDSR , RULL(0x1301242F), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_QIDSR , RULL(0x1301202F), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301202F, -REG64( EQ_4_CME_SCOM_QIDSR , RULL(0x1401242F), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_QIDSR , RULL(0x1401202F), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401202F, -REG64( EQ_5_CME_SCOM_QIDSR , RULL(0x1501242F), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_QIDSR , RULL(0x1501202F), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501202F, REG64( EX_CME_SCOM_QIDSR_PPE , RULL(0x1090106E0), SH_UNT_EX , SH_ACS_PPE ); @@ -3478,47 +3516,47 @@ REG64( EX_11_CME_SCOM_QIDSR_PPE , RULL(0x10E0206E SH_ACS_PPE ); REG64( EX_11_CME_SCOM_QIDSR_SCOM , RULL(0x1501242F), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_SICR_SCOM , RULL(0x1001243D), SH_UNT_EQ , +REG64( EQ_CME_SCOM_SICR_SCOM , RULL(0x1001203D), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 1001203D, -REG64( EQ_CME_SCOM_SICR_SCOM1 , RULL(0x1001243E), SH_UNT_EQ , +REG64( EQ_CME_SCOM_SICR_SCOM1 , RULL(0x1001203E), SH_UNT_EQ , SH_ACS_SCOM1 ); //DUPS: 1001203E, -REG64( EQ_CME_SCOM_SICR_SCOM2 , RULL(0x1001243F), SH_UNT_EQ , +REG64( EQ_CME_SCOM_SICR_SCOM2 , RULL(0x1001203F), SH_UNT_EQ , SH_ACS_SCOM2 ); //DUPS: 1001203F, -REG64( EQ_0_CME_SCOM_SICR_SCOM , RULL(0x1001243D), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_SICR_SCOM , RULL(0x1001203D), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 1001203D, -REG64( EQ_0_CME_SCOM_SICR_SCOM1 , RULL(0x1001243E), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_SICR_SCOM1 , RULL(0x1001203E), SH_UNT_EQ_0 , SH_ACS_SCOM1 ); //DUPS: 1001203E, -REG64( EQ_0_CME_SCOM_SICR_SCOM2 , RULL(0x1001243F), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_SICR_SCOM2 , RULL(0x1001203F), SH_UNT_EQ_0 , SH_ACS_SCOM2 ); //DUPS: 1001203F, -REG64( EQ_1_CME_SCOM_SICR_SCOM , RULL(0x1101243D), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_SICR_SCOM , RULL(0x1101203D), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 1101203D, -REG64( EQ_1_CME_SCOM_SICR_SCOM1 , RULL(0x1101243E), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_SICR_SCOM1 , RULL(0x1101203E), SH_UNT_EQ_1 , SH_ACS_SCOM1 ); //DUPS: 1101203E, -REG64( EQ_1_CME_SCOM_SICR_SCOM2 , RULL(0x1101243F), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_SICR_SCOM2 , RULL(0x1101203F), SH_UNT_EQ_1 , SH_ACS_SCOM2 ); //DUPS: 1101203F, -REG64( EQ_2_CME_SCOM_SICR_SCOM , RULL(0x1201243D), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_SICR_SCOM , RULL(0x1201203D), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 1201203D, -REG64( EQ_2_CME_SCOM_SICR_SCOM1 , RULL(0x1201243E), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_SICR_SCOM1 , RULL(0x1201203E), SH_UNT_EQ_2 , SH_ACS_SCOM1 ); //DUPS: 1201203E, -REG64( EQ_2_CME_SCOM_SICR_SCOM2 , RULL(0x1201243F), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_SICR_SCOM2 , RULL(0x1201203F), SH_UNT_EQ_2 , SH_ACS_SCOM2 ); //DUPS: 1201203F, -REG64( EQ_3_CME_SCOM_SICR_SCOM , RULL(0x1301243D), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_SICR_SCOM , RULL(0x1301203D), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 1301203D, -REG64( EQ_3_CME_SCOM_SICR_SCOM1 , RULL(0x1301243E), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_SICR_SCOM1 , RULL(0x1301203E), SH_UNT_EQ_3 , SH_ACS_SCOM1 ); //DUPS: 1301203E, -REG64( EQ_3_CME_SCOM_SICR_SCOM2 , RULL(0x1301243F), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_SICR_SCOM2 , RULL(0x1301203F), SH_UNT_EQ_3 , SH_ACS_SCOM2 ); //DUPS: 1301203F, -REG64( EQ_4_CME_SCOM_SICR_SCOM , RULL(0x1401243D), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_SICR_SCOM , RULL(0x1401203D), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 1401203D, -REG64( EQ_4_CME_SCOM_SICR_SCOM1 , RULL(0x1401243E), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_SICR_SCOM1 , RULL(0x1401203E), SH_UNT_EQ_4 , SH_ACS_SCOM1 ); //DUPS: 1401203E, -REG64( EQ_4_CME_SCOM_SICR_SCOM2 , RULL(0x1401243F), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_SICR_SCOM2 , RULL(0x1401203F), SH_UNT_EQ_4 , SH_ACS_SCOM2 ); //DUPS: 1401203F, -REG64( EQ_5_CME_SCOM_SICR_SCOM , RULL(0x1501243D), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_SICR_SCOM , RULL(0x1501203D), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 1501203D, -REG64( EQ_5_CME_SCOM_SICR_SCOM1 , RULL(0x1501243E), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_SICR_SCOM1 , RULL(0x1501203E), SH_UNT_EQ_5 , SH_ACS_SCOM1 ); //DUPS: 1501203E, -REG64( EQ_5_CME_SCOM_SICR_SCOM2 , RULL(0x1501243F), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_SICR_SCOM2 , RULL(0x1501203F), SH_UNT_EQ_5 , SH_ACS_SCOM2 ); //DUPS: 1501203F, REG64( EX_CME_SCOM_SICR_PPE , RULL(0x109010500), SH_UNT_EX , SH_ACS_PPE ); @@ -3638,19 +3676,19 @@ REG64( EX_11_CME_SCOM_SICR_SCOM , RULL(0x1501243D REG64( EX_11_CME_SCOM_SICR_SCOM1 , RULL(0x1501243E), SH_UNT_EX_11 , SH_ACS_SCOM1 ); REG64( EX_11_CME_SCOM_SICR_SCOM2 , RULL(0x1501243F), SH_UNT_EX_11 , SH_ACS_SCOM2 ); -REG64( EQ_CME_SCOM_SRTCH0 , RULL(0x10012423), SH_UNT_EQ , +REG64( EQ_CME_SCOM_SRTCH0 , RULL(0x10012023), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012023, -REG64( EQ_0_CME_SCOM_SRTCH0 , RULL(0x10012423), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_SRTCH0 , RULL(0x10012023), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012023, -REG64( EQ_1_CME_SCOM_SRTCH0 , RULL(0x11012423), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_SRTCH0 , RULL(0x11012023), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012023, -REG64( EQ_2_CME_SCOM_SRTCH0 , RULL(0x12012423), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_SRTCH0 , RULL(0x12012023), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012023, -REG64( EQ_3_CME_SCOM_SRTCH0 , RULL(0x13012423), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_SRTCH0 , RULL(0x13012023), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012023, -REG64( EQ_4_CME_SCOM_SRTCH0 , RULL(0x14012423), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_SRTCH0 , RULL(0x14012023), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012023, -REG64( EQ_5_CME_SCOM_SRTCH0 , RULL(0x15012423), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_SRTCH0 , RULL(0x15012023), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012023, REG64( EX_CME_SCOM_SRTCH0_PPE , RULL(0x109010420), SH_UNT_EX , SH_ACS_PPE ); @@ -3692,19 +3730,19 @@ REG64( EX_11_CME_SCOM_SRTCH0_PPE , RULL(0x10E02042 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_SRTCH0_SCOM , RULL(0x15012423), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_SRTCH1 , RULL(0x10012424), SH_UNT_EQ , +REG64( EQ_CME_SCOM_SRTCH1 , RULL(0x10012024), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012024, -REG64( EQ_0_CME_SCOM_SRTCH1 , RULL(0x10012424), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_SRTCH1 , RULL(0x10012024), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012024, -REG64( EQ_1_CME_SCOM_SRTCH1 , RULL(0x11012424), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_SRTCH1 , RULL(0x11012024), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012024, -REG64( EQ_2_CME_SCOM_SRTCH1 , RULL(0x12012424), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_SRTCH1 , RULL(0x12012024), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012024, -REG64( EQ_3_CME_SCOM_SRTCH1 , RULL(0x13012424), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_SRTCH1 , RULL(0x13012024), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012024, -REG64( EQ_4_CME_SCOM_SRTCH1 , RULL(0x14012424), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_SRTCH1 , RULL(0x14012024), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012024, -REG64( EQ_5_CME_SCOM_SRTCH1 , RULL(0x15012424), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_SRTCH1 , RULL(0x15012024), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012024, REG64( EX_CME_SCOM_SRTCH1_PPE , RULL(0x109010440), SH_UNT_EX , SH_ACS_PPE ); @@ -3746,19 +3784,19 @@ REG64( EX_11_CME_SCOM_SRTCH1_PPE , RULL(0x10E02044 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_SRTCH1_SCOM , RULL(0x15012424), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_VCCR , RULL(0x1001242C), SH_UNT_EQ , +REG64( EQ_CME_SCOM_VCCR , RULL(0x1001202C), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001202C, -REG64( EQ_0_CME_SCOM_VCCR , RULL(0x1001242C), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_VCCR , RULL(0x1001202C), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001202C, -REG64( EQ_1_CME_SCOM_VCCR , RULL(0x1101242C), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_VCCR , RULL(0x1101202C), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101202C, -REG64( EQ_2_CME_SCOM_VCCR , RULL(0x1201242C), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_VCCR , RULL(0x1201202C), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201202C, -REG64( EQ_3_CME_SCOM_VCCR , RULL(0x1301242C), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_VCCR , RULL(0x1301202C), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301202C, -REG64( EQ_4_CME_SCOM_VCCR , RULL(0x1401242C), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_VCCR , RULL(0x1401202C), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401202C, -REG64( EQ_5_CME_SCOM_VCCR , RULL(0x1501242C), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_VCCR , RULL(0x1501202C), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501202C, REG64( EX_CME_SCOM_VCCR_PPE , RULL(0x109010680), SH_UNT_EX , SH_ACS_PPE ); @@ -3800,19 +3838,19 @@ REG64( EX_11_CME_SCOM_VCCR_PPE , RULL(0x10E02068 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_VCCR_SCOM , RULL(0x1501242C), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_VCTR , RULL(0x10012439), SH_UNT_EQ , +REG64( EQ_CME_SCOM_VCTR , RULL(0x10012039), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012039, -REG64( EQ_0_CME_SCOM_VCTR , RULL(0x10012439), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_VCTR , RULL(0x10012039), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012039, -REG64( EQ_1_CME_SCOM_VCTR , RULL(0x11012439), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_VCTR , RULL(0x11012039), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012039, -REG64( EQ_2_CME_SCOM_VCTR , RULL(0x12012439), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_VCTR , RULL(0x12012039), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012039, -REG64( EQ_3_CME_SCOM_VCTR , RULL(0x13012439), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_VCTR , RULL(0x13012039), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012039, -REG64( EQ_4_CME_SCOM_VCTR , RULL(0x14012439), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_VCTR , RULL(0x14012039), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012039, -REG64( EQ_5_CME_SCOM_VCTR , RULL(0x15012439), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_VCTR , RULL(0x15012039), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012039, REG64( EX_CME_SCOM_VCTR , RULL(0x10012039), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CME_SCOM_VCTR , RULL(0x10012039), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -3828,19 +3866,19 @@ REG64( EX_9_CME_SCOM_VCTR , RULL(0x14012439 REG64( EX_10_CME_SCOM_VCTR , RULL(0x15012039), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); REG64( EX_11_CME_SCOM_VCTR , RULL(0x15012439), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CME_SCOM_VDCR , RULL(0x10012435), SH_UNT_EQ , +REG64( EQ_CME_SCOM_VDCR , RULL(0x10012035), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012035, -REG64( EQ_0_CME_SCOM_VDCR , RULL(0x10012435), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_VDCR , RULL(0x10012035), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012035, -REG64( EQ_1_CME_SCOM_VDCR , RULL(0x11012435), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_VDCR , RULL(0x11012035), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012035, -REG64( EQ_2_CME_SCOM_VDCR , RULL(0x12012435), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_VDCR , RULL(0x12012035), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012035, -REG64( EQ_3_CME_SCOM_VDCR , RULL(0x13012435), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_VDCR , RULL(0x13012035), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012035, -REG64( EQ_4_CME_SCOM_VDCR , RULL(0x14012435), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_VDCR , RULL(0x14012035), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012035, -REG64( EQ_5_CME_SCOM_VDCR , RULL(0x15012435), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_VDCR , RULL(0x15012035), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012035, REG64( EX_CME_SCOM_VDCR_PPE , RULL(0x109010600), SH_UNT_EX , SH_ACS_PPE ); @@ -3882,19 +3920,19 @@ REG64( EX_11_CME_SCOM_VDCR_PPE , RULL(0x10E02060 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_VDCR_SCOM , RULL(0x15012435), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_VDSR , RULL(0x10012437), SH_UNT_EQ , +REG64( EQ_CME_SCOM_VDSR , RULL(0x10012037), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012037, -REG64( EQ_0_CME_SCOM_VDSR , RULL(0x10012437), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_VDSR , RULL(0x10012037), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012037, -REG64( EQ_1_CME_SCOM_VDSR , RULL(0x11012437), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_VDSR , RULL(0x11012037), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012037, -REG64( EQ_2_CME_SCOM_VDSR , RULL(0x12012437), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_VDSR , RULL(0x12012037), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012037, -REG64( EQ_3_CME_SCOM_VDSR , RULL(0x13012437), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_VDSR , RULL(0x13012037), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012037, -REG64( EQ_4_CME_SCOM_VDSR , RULL(0x14012437), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_VDSR , RULL(0x14012037), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012037, -REG64( EQ_5_CME_SCOM_VDSR , RULL(0x15012437), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_VDSR , RULL(0x15012037), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012037, REG64( EX_CME_SCOM_VDSR_PPE , RULL(0x109010640), SH_UNT_EX , SH_ACS_PPE ); @@ -3936,19 +3974,19 @@ REG64( EX_11_CME_SCOM_VDSR_PPE , RULL(0x10E02064 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_VDSR_SCOM , RULL(0x15012437), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_VECR , RULL(0x10012438), SH_UNT_EQ , +REG64( EQ_CME_SCOM_VECR , RULL(0x10012038), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012038, -REG64( EQ_0_CME_SCOM_VECR , RULL(0x10012438), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_VECR , RULL(0x10012038), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012038, -REG64( EQ_1_CME_SCOM_VECR , RULL(0x11012438), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_VECR , RULL(0x11012038), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012038, -REG64( EQ_2_CME_SCOM_VECR , RULL(0x12012438), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_VECR , RULL(0x12012038), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012038, -REG64( EQ_3_CME_SCOM_VECR , RULL(0x13012438), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_VECR , RULL(0x13012038), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012038, -REG64( EQ_4_CME_SCOM_VECR , RULL(0x14012438), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_VECR , RULL(0x14012038), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012038, -REG64( EQ_5_CME_SCOM_VECR , RULL(0x15012438), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_VECR , RULL(0x15012038), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012038, REG64( EX_CME_SCOM_VECR_PPE , RULL(0x109010660), SH_UNT_EX , SH_ACS_PPE ); @@ -3990,19 +4028,19 @@ REG64( EX_11_CME_SCOM_VECR_PPE , RULL(0x10E02066 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_VECR_SCOM , RULL(0x15012438), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_VNCR , RULL(0x10012436), SH_UNT_EQ , +REG64( EQ_CME_SCOM_VNCR , RULL(0x10012036), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012036, -REG64( EQ_0_CME_SCOM_VNCR , RULL(0x10012436), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_VNCR , RULL(0x10012036), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012036, -REG64( EQ_1_CME_SCOM_VNCR , RULL(0x11012436), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_VNCR , RULL(0x11012036), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012036, -REG64( EQ_2_CME_SCOM_VNCR , RULL(0x12012436), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_VNCR , RULL(0x12012036), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012036, -REG64( EQ_3_CME_SCOM_VNCR , RULL(0x13012436), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_VNCR , RULL(0x13012036), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012036, -REG64( EQ_4_CME_SCOM_VNCR , RULL(0x14012436), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_VNCR , RULL(0x14012036), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012036, -REG64( EQ_5_CME_SCOM_VNCR , RULL(0x15012436), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_VNCR , RULL(0x15012036), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012036, REG64( EX_CME_SCOM_VNCR_PPE , RULL(0x109010620), SH_UNT_EX , SH_ACS_PPE ); @@ -4044,19 +4082,19 @@ REG64( EX_11_CME_SCOM_VNCR_PPE , RULL(0x10E02062 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_VNCR_SCOM , RULL(0x15012436), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_XIPCBMD0 , RULL(0x1001241C), SH_UNT_EQ , +REG64( EQ_CME_SCOM_XIPCBMD0 , RULL(0x1001201C), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001201C, -REG64( EQ_0_CME_SCOM_XIPCBMD0 , RULL(0x1001241C), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_XIPCBMD0 , RULL(0x1001201C), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001201C, -REG64( EQ_1_CME_SCOM_XIPCBMD0 , RULL(0x1101241C), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_XIPCBMD0 , RULL(0x1101201C), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101201C, -REG64( EQ_2_CME_SCOM_XIPCBMD0 , RULL(0x1201241C), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_XIPCBMD0 , RULL(0x1201201C), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201201C, -REG64( EQ_3_CME_SCOM_XIPCBMD0 , RULL(0x1301241C), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_XIPCBMD0 , RULL(0x1301201C), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301201C, -REG64( EQ_4_CME_SCOM_XIPCBMD0 , RULL(0x1401241C), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_XIPCBMD0 , RULL(0x1401201C), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401201C, -REG64( EQ_5_CME_SCOM_XIPCBMD0 , RULL(0x1501241C), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_XIPCBMD0 , RULL(0x1501201C), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501201C, REG64( EX_CME_SCOM_XIPCBMD0_PPE , RULL(0x109010580), SH_UNT_EX , SH_ACS_PPE ); @@ -4098,19 +4136,19 @@ REG64( EX_11_CME_SCOM_XIPCBMD0_PPE , RULL(0x10E02058 SH_ACS_PPE ); REG64( EX_11_CME_SCOM_XIPCBMD0_SCOM , RULL(0x1501241C), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_XIPCBMD1 , RULL(0x1001241D), SH_UNT_EQ , +REG64( EQ_CME_SCOM_XIPCBMD1 , RULL(0x1001201D), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001201D, -REG64( EQ_0_CME_SCOM_XIPCBMD1 , RULL(0x1001241D), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_XIPCBMD1 , RULL(0x1001201D), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001201D, -REG64( EQ_1_CME_SCOM_XIPCBMD1 , RULL(0x1101241D), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_XIPCBMD1 , RULL(0x1101201D), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101201D, -REG64( EQ_2_CME_SCOM_XIPCBMD1 , RULL(0x1201241D), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_XIPCBMD1 , RULL(0x1201201D), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201201D, -REG64( EQ_3_CME_SCOM_XIPCBMD1 , RULL(0x1301241D), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_XIPCBMD1 , RULL(0x1301201D), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301201D, -REG64( EQ_4_CME_SCOM_XIPCBMD1 , RULL(0x1401241D), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_XIPCBMD1 , RULL(0x1401201D), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401201D, -REG64( EQ_5_CME_SCOM_XIPCBMD1 , RULL(0x1501241D), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_XIPCBMD1 , RULL(0x1501201D), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501201D, REG64( EX_CME_SCOM_XIPCBMD1_PPE , RULL(0x1090105A0), SH_UNT_EX , SH_ACS_PPE ); @@ -4152,19 +4190,19 @@ REG64( EX_11_CME_SCOM_XIPCBMD1_PPE , RULL(0x10E0205A SH_ACS_PPE ); REG64( EX_11_CME_SCOM_XIPCBMD1_SCOM , RULL(0x1501241D), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_XIPCBMI0 , RULL(0x1001241E), SH_UNT_EQ , +REG64( EQ_CME_SCOM_XIPCBMI0 , RULL(0x1001201E), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001201E, -REG64( EQ_0_CME_SCOM_XIPCBMI0 , RULL(0x1001241E), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_XIPCBMI0 , RULL(0x1001201E), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001201E, -REG64( EQ_1_CME_SCOM_XIPCBMI0 , RULL(0x1101241E), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_XIPCBMI0 , RULL(0x1101201E), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101201E, -REG64( EQ_2_CME_SCOM_XIPCBMI0 , RULL(0x1201241E), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_XIPCBMI0 , RULL(0x1201201E), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201201E, -REG64( EQ_3_CME_SCOM_XIPCBMI0 , RULL(0x1301241E), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_XIPCBMI0 , RULL(0x1301201E), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301201E, -REG64( EQ_4_CME_SCOM_XIPCBMI0 , RULL(0x1401241E), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_XIPCBMI0 , RULL(0x1401201E), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401201E, -REG64( EQ_5_CME_SCOM_XIPCBMI0 , RULL(0x1501241E), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_XIPCBMI0 , RULL(0x1501201E), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501201E, REG64( EX_CME_SCOM_XIPCBMI0_PPE , RULL(0x1090105C0), SH_UNT_EX , SH_ACS_PPE ); @@ -4206,19 +4244,19 @@ REG64( EX_11_CME_SCOM_XIPCBMI0_PPE , RULL(0x10E0205C SH_ACS_PPE ); REG64( EX_11_CME_SCOM_XIPCBMI0_SCOM , RULL(0x1501241E), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_XIPCBMI1 , RULL(0x1001241F), SH_UNT_EQ , +REG64( EQ_CME_SCOM_XIPCBMI1 , RULL(0x1001201F), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001201F, -REG64( EQ_0_CME_SCOM_XIPCBMI1 , RULL(0x1001241F), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_XIPCBMI1 , RULL(0x1001201F), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001201F, -REG64( EQ_1_CME_SCOM_XIPCBMI1 , RULL(0x1101241F), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_XIPCBMI1 , RULL(0x1101201F), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101201F, -REG64( EQ_2_CME_SCOM_XIPCBMI1 , RULL(0x1201241F), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_XIPCBMI1 , RULL(0x1201201F), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201201F, -REG64( EQ_3_CME_SCOM_XIPCBMI1 , RULL(0x1301241F), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_XIPCBMI1 , RULL(0x1301201F), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301201F, -REG64( EQ_4_CME_SCOM_XIPCBMI1 , RULL(0x1401241F), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_XIPCBMI1 , RULL(0x1401201F), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401201F, -REG64( EQ_5_CME_SCOM_XIPCBMI1 , RULL(0x1501241F), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_XIPCBMI1 , RULL(0x1501201F), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501201F, REG64( EX_CME_SCOM_XIPCBMI1_PPE , RULL(0x1090105E0), SH_UNT_EX , SH_ACS_PPE ); @@ -4260,19 +4298,19 @@ REG64( EX_11_CME_SCOM_XIPCBMI1_PPE , RULL(0x10E0205E SH_ACS_PPE ); REG64( EX_11_CME_SCOM_XIPCBMI1_SCOM , RULL(0x1501241F), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_XIPCBQ0 , RULL(0x1001241A), SH_UNT_EQ , +REG64( EQ_CME_SCOM_XIPCBQ0 , RULL(0x1001201A), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001201A, -REG64( EQ_0_CME_SCOM_XIPCBQ0 , RULL(0x1001241A), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_XIPCBQ0 , RULL(0x1001201A), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001201A, -REG64( EQ_1_CME_SCOM_XIPCBQ0 , RULL(0x1101241A), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_XIPCBQ0 , RULL(0x1101201A), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101201A, -REG64( EQ_2_CME_SCOM_XIPCBQ0 , RULL(0x1201241A), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_XIPCBQ0 , RULL(0x1201201A), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201201A, -REG64( EQ_3_CME_SCOM_XIPCBQ0 , RULL(0x1301241A), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_XIPCBQ0 , RULL(0x1301201A), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301201A, -REG64( EQ_4_CME_SCOM_XIPCBQ0 , RULL(0x1401241A), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_XIPCBQ0 , RULL(0x1401201A), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401201A, -REG64( EQ_5_CME_SCOM_XIPCBQ0 , RULL(0x1501241A), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_XIPCBQ0 , RULL(0x1501201A), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501201A, REG64( EX_CME_SCOM_XIPCBQ0 , RULL(0x1001201A), SH_UNT_EX , SH_ACS_SCOM_RO ); REG64( EX_0_CME_SCOM_XIPCBQ0 , RULL(0x1001201A), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); @@ -4288,19 +4326,19 @@ REG64( EX_9_CME_SCOM_XIPCBQ0 , RULL(0x1401241A REG64( EX_10_CME_SCOM_XIPCBQ0 , RULL(0x1501201A), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); REG64( EX_11_CME_SCOM_XIPCBQ0 , RULL(0x1501241A), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_CME_SCOM_XIPCBQ1 , RULL(0x1001241B), SH_UNT_EQ , +REG64( EQ_CME_SCOM_XIPCBQ1 , RULL(0x1001201B), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001201B, -REG64( EQ_0_CME_SCOM_XIPCBQ1 , RULL(0x1001241B), SH_UNT_EQ_0 , +REG64( EQ_0_CME_SCOM_XIPCBQ1 , RULL(0x1001201B), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001201B, -REG64( EQ_1_CME_SCOM_XIPCBQ1 , RULL(0x1101241B), SH_UNT_EQ_1 , +REG64( EQ_1_CME_SCOM_XIPCBQ1 , RULL(0x1101201B), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101201B, -REG64( EQ_2_CME_SCOM_XIPCBQ1 , RULL(0x1201241B), SH_UNT_EQ_2 , +REG64( EQ_2_CME_SCOM_XIPCBQ1 , RULL(0x1201201B), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201201B, -REG64( EQ_3_CME_SCOM_XIPCBQ1 , RULL(0x1301241B), SH_UNT_EQ_3 , +REG64( EQ_3_CME_SCOM_XIPCBQ1 , RULL(0x1301201B), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301201B, -REG64( EQ_4_CME_SCOM_XIPCBQ1 , RULL(0x1401241B), SH_UNT_EQ_4 , +REG64( EQ_4_CME_SCOM_XIPCBQ1 , RULL(0x1401201B), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401201B, -REG64( EQ_5_CME_SCOM_XIPCBQ1 , RULL(0x1501241B), SH_UNT_EQ_5 , +REG64( EQ_5_CME_SCOM_XIPCBQ1 , RULL(0x1501201B), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501201B, REG64( EX_CME_SCOM_XIPCBQ1 , RULL(0x1001201B), SH_UNT_EX , SH_ACS_SCOM_RO ); REG64( EX_0_CME_SCOM_XIPCBQ1 , RULL(0x1001201B), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); @@ -4316,6 +4354,34 @@ REG64( EX_9_CME_SCOM_XIPCBQ1 , RULL(0x1401241B REG64( EX_10_CME_SCOM_XIPCBQ1 , RULL(0x1501201B), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); REG64( EX_11_CME_SCOM_XIPCBQ1 , RULL(0x1501241B), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); +REG64( EQ_CME_SCOM_XISIB , RULL(0x10012016), SH_UNT_EQ , + SH_ACS_SCOM_RO ); //DUPS: 10012016, +REG64( EQ_0_CME_SCOM_XISIB , RULL(0x10012016), SH_UNT_EQ_0 , + SH_ACS_SCOM_RO ); //DUPS: 10012016, +REG64( EQ_1_CME_SCOM_XISIB , RULL(0x11012016), SH_UNT_EQ_1 , + SH_ACS_SCOM_RO ); //DUPS: 11012016, +REG64( EQ_2_CME_SCOM_XISIB , RULL(0x12012016), SH_UNT_EQ_2 , + SH_ACS_SCOM_RO ); //DUPS: 12012016, +REG64( EQ_3_CME_SCOM_XISIB , RULL(0x13012016), SH_UNT_EQ_3 , + SH_ACS_SCOM_RO ); //DUPS: 13012016, +REG64( EQ_4_CME_SCOM_XISIB , RULL(0x14012016), SH_UNT_EQ_4 , + SH_ACS_SCOM_RO ); //DUPS: 14012016, +REG64( EQ_5_CME_SCOM_XISIB , RULL(0x15012016), SH_UNT_EQ_5 , + SH_ACS_SCOM_RO ); //DUPS: 15012016, +REG64( EX_CME_SCOM_XISIB , RULL(0x10012016), SH_UNT_EX , SH_ACS_SCOM_RO ); +REG64( EX_0_CME_SCOM_XISIB , RULL(0x10012016), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); +REG64( EX_1_CME_SCOM_XISIB , RULL(0x10012416), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); +REG64( EX_2_CME_SCOM_XISIB , RULL(0x11012016), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); +REG64( EX_3_CME_SCOM_XISIB , RULL(0x11012416), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); +REG64( EX_4_CME_SCOM_XISIB , RULL(0x12012016), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); +REG64( EX_5_CME_SCOM_XISIB , RULL(0x12012416), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); +REG64( EX_6_CME_SCOM_XISIB , RULL(0x13012016), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); +REG64( EX_7_CME_SCOM_XISIB , RULL(0x13012416), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); +REG64( EX_8_CME_SCOM_XISIB , RULL(0x14012016), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); +REG64( EX_9_CME_SCOM_XISIB , RULL(0x14012416), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); +REG64( EX_10_CME_SCOM_XISIB , RULL(0x15012016), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); +REG64( EX_11_CME_SCOM_XISIB , RULL(0x15012416), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); + REG64( C_CONTROL_REG , RULL(0x20050012), SH_UNT_C , SH_ACS_SCOM ); REG64( C_0_CONTROL_REG , RULL(0x20050012), SH_UNT_C_0 , SH_ACS_SCOM ); REG64( C_1_CONTROL_REG , RULL(0x21050012), SH_UNT_C_1 , SH_ACS_SCOM ); @@ -4364,7 +4430,7 @@ REG64( EX_5_CONTROL_REG , RULL(0x2A050012 SH_ACS_SCOM ); //DUPS: 2B050012, REG64( EX_6_CONTROL_REG , RULL(0x2C050012), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D050012, -REG64( EX_7_CONTROL_REG , RULL(0x2E050012), SH_UNT_EX_7 , +REG64( EX_7_CONTROL_REG , RULL(0x2F050012), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F050012, REG64( EX_8_CONTROL_REG , RULL(0x30050012), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31050012, @@ -4418,7 +4484,7 @@ REG64( EX_5_L2_CORE_ACTION0 , RULL(0x2A010A46 SH_ACS_SCOM_RW ); //DUPS: 2B010A46, REG64( EX_6_L2_CORE_ACTION0 , RULL(0x2C010A46), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010A46, -REG64( EX_7_L2_CORE_ACTION0 , RULL(0x2E010A46), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_ACTION0 , RULL(0x2F010A46), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A46, REG64( EX_8_L2_CORE_ACTION0 , RULL(0x30010A46), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A46, @@ -4470,7 +4536,7 @@ REG64( EX_5_L2_CORE_ACTION1 , RULL(0x2A010A47 SH_ACS_SCOM_RW ); //DUPS: 2B010A47, REG64( EX_6_L2_CORE_ACTION1 , RULL(0x2C010A47), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010A47, -REG64( EX_7_L2_CORE_ACTION1 , RULL(0x2E010A47), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_ACTION1 , RULL(0x2F010A47), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A47, REG64( EX_8_L2_CORE_ACTION1 , RULL(0x30010A47), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A47, @@ -4608,11 +4674,11 @@ REG64( EX_6_L2_CORE_FIR_AND , RULL(0x2C010A41 SH_ACS_SCOM1_AND ); //DUPS: 2D010A41, REG64( EX_6_L2_CORE_FIR_OR , RULL(0x2C010A42), SH_UNT_EX_6_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2D010A42, -REG64( EX_7_L2_CORE_FIR , RULL(0x2E010A40), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FIR , RULL(0x2F010A40), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A40, -REG64( EX_7_L2_CORE_FIR_AND , RULL(0x2E010A41), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FIR_AND , RULL(0x2F010A41), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_AND ); //DUPS: 2F010A41, -REG64( EX_7_L2_CORE_FIR_OR , RULL(0x2E010A42), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FIR_OR , RULL(0x2F010A42), SH_UNT_EX_7_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2F010A42, REG64( EX_8_L2_CORE_FIR , RULL(0x30010A40), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A40, @@ -4762,11 +4828,11 @@ REG64( EX_6_L2_CORE_FIRMASK_AND , RULL(0x2C010A44 SH_ACS_SCOM1_AND ); //DUPS: 2D010A44, REG64( EX_6_L2_CORE_FIRMASK_OR , RULL(0x2C010A45), SH_UNT_EX_6_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2D010A45, -REG64( EX_7_L2_CORE_FIRMASK , RULL(0x2E010A43), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FIRMASK , RULL(0x2F010A43), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A43, -REG64( EX_7_L2_CORE_FIRMASK_AND , RULL(0x2E010A44), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FIRMASK_AND , RULL(0x2F010A44), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_AND ); //DUPS: 2F010A44, -REG64( EX_7_L2_CORE_FIRMASK_OR , RULL(0x2E010A45), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FIRMASK_OR , RULL(0x2F010A45), SH_UNT_EX_7_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2F010A45, REG64( EX_8_L2_CORE_FIRMASK , RULL(0x30010A43), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A43, @@ -4830,7 +4896,7 @@ REG64( EX_5_L2_CORE_FUSES , RULL(0x2A010AA7 SH_ACS_SCOM_RO ); //DUPS: 2B010AA7, REG64( EX_6_L2_CORE_FUSES , RULL(0x2C010AA7), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010AA7, -REG64( EX_7_L2_CORE_FUSES , RULL(0x2E010AA7), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_CORE_FUSES , RULL(0x2F010AA7), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010AA7, REG64( EX_8_L2_CORE_FUSES , RULL(0x30010AA7), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010AA7, @@ -4864,19 +4930,19 @@ REG64( C_20_CORE_THREAD_STATE , RULL(0x34010AB3 REG64( C_21_CORE_THREAD_STATE , RULL(0x35010AB3), SH_UNT_C_21 , SH_ACS_SCOM_RO ); REG64( C_22_CORE_THREAD_STATE , RULL(0x36010AB3), SH_UNT_C_22 , SH_ACS_SCOM_RO ); REG64( C_23_CORE_THREAD_STATE , RULL(0x37010AB3), SH_UNT_C_23 , SH_ACS_SCOM_RO ); -REG64( EX_0_L2_CORE_THREAD_STATE , RULL(0x21010AB3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_CORE_THREAD_STATE , RULL(0x20010AB3), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RO ); //DUPS: 20010AB3, -REG64( EX_10_L2_CORE_THREAD_STATE , RULL(0x35010AB3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_CORE_THREAD_STATE , RULL(0x34010AB3), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RO ); //DUPS: 34010AB3, -REG64( EX_11_L2_CORE_THREAD_STATE , RULL(0x37010AB3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_CORE_THREAD_STATE , RULL(0x36010AB3), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RO ); //DUPS: 36010AB3, -REG64( EX_1_L2_CORE_THREAD_STATE , RULL(0x23010AB3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_CORE_THREAD_STATE , RULL(0x22010AB3), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RO ); //DUPS: 22010AB3, -REG64( EX_2_L2_CORE_THREAD_STATE , RULL(0x25010AB3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_CORE_THREAD_STATE , RULL(0x24010AB3), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RO ); //DUPS: 24010AB3, -REG64( EX_3_L2_CORE_THREAD_STATE , RULL(0x27010AB3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_CORE_THREAD_STATE , RULL(0x26010AB3), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RO ); //DUPS: 26010AB3, -REG64( EX_4_L2_CORE_THREAD_STATE , RULL(0x29010AB3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_CORE_THREAD_STATE , RULL(0x28010AB3), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RO ); //DUPS: 28010AB3, REG64( EX_5_L2_CORE_THREAD_STATE , RULL(0x2B010AB3), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RO ); //DUPS: 2A010AB3, @@ -4884,11 +4950,11 @@ REG64( EX_6_L2_CORE_THREAD_STATE , RULL(0x2D010AB3 SH_ACS_SCOM_RO ); //DUPS: 2C010AB3, REG64( EX_7_L2_CORE_THREAD_STATE , RULL(0x2F010AB3), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2E010AB3, -REG64( EX_8_L2_CORE_THREAD_STATE , RULL(0x31010AB3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_CORE_THREAD_STATE , RULL(0x30010AB3), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 30010AB3, -REG64( EX_9_L2_CORE_THREAD_STATE , RULL(0x33010AB3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_CORE_THREAD_STATE , RULL(0x32010AB3), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RO ); //DUPS: 32010AB3, -REG64( EX_L2_CORE_THREAD_STATE , RULL(0x21010AB3), SH_UNT_EX_L2 , +REG64( EX_L2_CORE_THREAD_STATE , RULL(0x20010AB3), SH_UNT_EX_L2 , SH_ACS_SCOM_RO ); //DUPS: 20010AB3, REG64( C_CORE_WOF , RULL(0x20010A48), SH_UNT_C , @@ -4957,7 +5023,7 @@ REG64( EX_5_CORE_WOF , RULL(0x2A010A48 SH_ACS_SCOM_WCLRREG ); //DUPS: 2B010A48, REG64( EX_6_CORE_WOF , RULL(0x2C010A48), SH_UNT_EX_6 , SH_ACS_SCOM_WCLRREG ); //DUPS: 2D010A48, -REG64( EX_7_CORE_WOF , RULL(0x2E010A48), SH_UNT_EX_7 , +REG64( EX_7_CORE_WOF , RULL(0x2F010A48), SH_UNT_EX_7 , SH_ACS_SCOM_WCLRREG ); //DUPS: 2F010A48, REG64( EX_8_CORE_WOF , RULL(0x30010A48), SH_UNT_EX_8 , SH_ACS_SCOM_WCLRREG ); //DUPS: 31010A48, @@ -5144,11 +5210,11 @@ REG64( EX_6_CPLT_CONF0_OR , RULL(0x2C000018 SH_ACS_SCOM1_OR ); //DUPS: 2D000018, REG64( EX_6_CPLT_CONF0_CLEAR , RULL(0x2C000028), SH_UNT_EX_6 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000028, -REG64( EX_7_CPLT_CONF0 , RULL(0x2E000008), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CONF0 , RULL(0x2F000008), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F000008, -REG64( EX_7_CPLT_CONF0_OR , RULL(0x2E000018), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CONF0_OR , RULL(0x2F000018), SH_UNT_EX_7 , SH_ACS_SCOM1_OR ); //DUPS: 2F000018, -REG64( EX_7_CPLT_CONF0_CLEAR , RULL(0x2E000028), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CONF0_CLEAR , RULL(0x2F000028), SH_UNT_EX_7 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000028, REG64( EX_8_CPLT_CONF0 , RULL(0x30000008), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31000008, @@ -5351,11 +5417,11 @@ REG64( EX_6_CPLT_CONF1_OR , RULL(0x2C000019 SH_ACS_SCOM1_OR ); //DUPS: 2D000019, REG64( EX_6_CPLT_CONF1_CLEAR , RULL(0x2C000029), SH_UNT_EX_6 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000029, -REG64( EX_7_CPLT_CONF1 , RULL(0x2E000009), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CONF1 , RULL(0x2F000009), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F000009, -REG64( EX_7_CPLT_CONF1_OR , RULL(0x2E000019), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CONF1_OR , RULL(0x2F000019), SH_UNT_EX_7 , SH_ACS_SCOM1_OR ); //DUPS: 2F000019, -REG64( EX_7_CPLT_CONF1_CLEAR , RULL(0x2E000029), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CONF1_CLEAR , RULL(0x2F000029), SH_UNT_EX_7 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000029, REG64( EX_8_CPLT_CONF1 , RULL(0x30000009), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31000009, @@ -5560,9 +5626,9 @@ REG64( EX_6_CPLT_CTRL0_CLEAR , RULL(0x2C000020 SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000020, REG64( EX_7_CPLT_CTRL0 , RULL(0x2E000000), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F000000, -REG64( EX_7_CPLT_CTRL0_OR , RULL(0x2E000010), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CTRL0_OR , RULL(0x2F000010), SH_UNT_EX_7 , SH_ACS_SCOM1_OR ); //DUPS: 2F000010, -REG64( EX_7_CPLT_CTRL0_CLEAR , RULL(0x2E000020), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CTRL0_CLEAR , RULL(0x2F000020), SH_UNT_EX_7 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000020, REG64( EX_8_CPLT_CTRL0 , RULL(0x30000000), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31000000, @@ -5765,11 +5831,11 @@ REG64( EX_6_CPLT_CTRL1_OR , RULL(0x2C000011 SH_ACS_SCOM1_OR ); //DUPS: 2D000011, REG64( EX_6_CPLT_CTRL1_CLEAR , RULL(0x2C000021), SH_UNT_EX_6 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000021, -REG64( EX_7_CPLT_CTRL1 , RULL(0x2E000001), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CTRL1 , RULL(0x2F000001), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F000001, -REG64( EX_7_CPLT_CTRL1_OR , RULL(0x2E000011), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CTRL1_OR , RULL(0x2F000011), SH_UNT_EX_7 , SH_ACS_SCOM1_OR ); //DUPS: 2F000011, -REG64( EX_7_CPLT_CTRL1_CLEAR , RULL(0x2E000021), SH_UNT_EX_7 , +REG64( EX_7_CPLT_CTRL1_CLEAR , RULL(0x2F000021), SH_UNT_EX_7 , SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000021, REG64( EX_8_CPLT_CTRL1 , RULL(0x30000001), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31000001, @@ -5844,7 +5910,7 @@ REG64( EX_5_CPLT_MASK0 , RULL(0x2A000101 SH_ACS_SCOM ); //DUPS: 2B000101, REG64( EX_6_CPLT_MASK0 , RULL(0x2C000101), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D000101, -REG64( EX_7_CPLT_MASK0 , RULL(0x2E000101), SH_UNT_EX_7 , +REG64( EX_7_CPLT_MASK0 , RULL(0x2F000101), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F000101, REG64( EX_8_CPLT_MASK0 , RULL(0x30000101), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31000101, @@ -5903,7 +5969,7 @@ REG64( EX_5_CPLT_STAT0 , RULL(0x2A000100 SH_ACS_SCOM ); //DUPS: 2B000100, REG64( EX_6_CPLT_STAT0 , RULL(0x2C000100), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D000100, -REG64( EX_7_CPLT_STAT0 , RULL(0x2E000100), SH_UNT_EX_7 , +REG64( EX_7_CPLT_STAT0 , RULL(0x2F000100), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F000100, REG64( EX_8_CPLT_STAT0 , RULL(0x30000100), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31000100, @@ -6026,11 +6092,11 @@ REG64( EX_0_CPPM_CACCR_CLEAR , RULL(0x200F0169 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0169, REG64( EX_0_CPPM_CACCR_OR , RULL(0x200F016A), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F016A, -REG64( EX_1_CPPM_CACCR , RULL(0x230F0168), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CACCR , RULL(0x220F0168), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0168, -REG64( EX_1_CPPM_CACCR_CLEAR , RULL(0x230F0169), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CACCR_CLEAR , RULL(0x220F0169), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0169, -REG64( EX_1_CPPM_CACCR_OR , RULL(0x230F016A), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CACCR_OR , RULL(0x220F016A), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F016A, REG64( EX_2_CPPM_CACCR , RULL(0x240F0168), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0168, @@ -6122,7 +6188,7 @@ REG64( EX_CPPM_CACSR , RULL(0x200F016B SH_ACS_SCOM_RO ); //DUPS: 210F016B, REG64( EX_0_CPPM_CACSR , RULL(0x200F016B), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F016B, -REG64( EX_1_CPPM_CACSR , RULL(0x230F016B), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CACSR , RULL(0x220F016B), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F016B, REG64( EX_2_CPPM_CACSR , RULL(0x240F016B), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F016B, @@ -6174,7 +6240,7 @@ REG64( EX_CPPM_CIIR , RULL(0x200F01AD SH_ACS_SCOM_4P ); //DUPS: 210F01AD, REG64( EX_0_CPPM_CIIR , RULL(0x200F01AD), SH_UNT_EX_0 , SH_ACS_SCOM_4P ); //DUPS: 210F01AD, -REG64( EX_1_CPPM_CIIR , RULL(0x230F01AD), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CIIR , RULL(0x220F01AD), SH_UNT_EX_1 , SH_ACS_SCOM_4P ); //DUPS: 220F01AD, REG64( EX_2_CPPM_CIIR , RULL(0x240F01AD), SH_UNT_EX_2 , SH_ACS_SCOM_4P ); //DUPS: 250F01AD, @@ -6226,7 +6292,7 @@ REG64( EX_CPPM_CISR , RULL(0x200F01AE SH_ACS_SCOM_RO ); //DUPS: 210F01AE, REG64( EX_0_CPPM_CISR , RULL(0x200F01AE), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F01AE, -REG64( EX_1_CPPM_CISR , RULL(0x230F01AE), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CISR , RULL(0x220F01AE), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F01AE, REG64( EX_2_CPPM_CISR , RULL(0x240F01AE), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F01AE, @@ -6278,7 +6344,7 @@ REG64( EX_CPPM_CIVRMLCR , RULL(0x200F01B7 SH_ACS_SCOM_RW ); //DUPS: 210F01B7, REG64( EX_0_CPPM_CIVRMLCR , RULL(0x200F01B7), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01B7, -REG64( EX_1_CPPM_CIVRMLCR , RULL(0x230F01B7), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CIVRMLCR , RULL(0x220F01B7), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01B7, REG64( EX_2_CPPM_CIVRMLCR , RULL(0x240F01B7), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01B7, @@ -6413,11 +6479,11 @@ REG64( EX_0_CPPM_CMEDATA_CLEAR , RULL(0x200F01A9 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01A9, REG64( EX_0_CPPM_CMEDATA_OR , RULL(0x200F01AA), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F01AA, -REG64( EX_1_CPPM_CMEDATA , RULL(0x230F01A8), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDATA , RULL(0x220F01A8), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01A8, -REG64( EX_1_CPPM_CMEDATA_CLEAR , RULL(0x230F01A9), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDATA_CLEAR , RULL(0x220F01A9), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F01A9, -REG64( EX_1_CPPM_CMEDATA_OR , RULL(0x230F01AA), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDATA_OR , RULL(0x220F01AA), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F01AA, REG64( EX_2_CPPM_CMEDATA , RULL(0x240F01A8), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01A8, @@ -6592,11 +6658,11 @@ REG64( EX_0_CPPM_CMEDB0_CLEAR , RULL(0x200F0191 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0191, REG64( EX_0_CPPM_CMEDB0_OR , RULL(0x200F0192), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F0192, -REG64( EX_1_CPPM_CMEDB0 , RULL(0x230F0190), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB0 , RULL(0x220F0190), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0190, -REG64( EX_1_CPPM_CMEDB0_CLEAR , RULL(0x230F0191), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB0_CLEAR , RULL(0x220F0191), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0191, -REG64( EX_1_CPPM_CMEDB0_OR , RULL(0x230F0192), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB0_OR , RULL(0x220F0192), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F0192, REG64( EX_2_CPPM_CMEDB0 , RULL(0x240F0190), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0190, @@ -6771,11 +6837,11 @@ REG64( EX_0_CPPM_CMEDB1_CLEAR , RULL(0x200F0195 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0195, REG64( EX_0_CPPM_CMEDB1_OR , RULL(0x200F0196), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F0196, -REG64( EX_1_CPPM_CMEDB1 , RULL(0x230F0194), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB1 , RULL(0x220F0194), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0194, -REG64( EX_1_CPPM_CMEDB1_CLEAR , RULL(0x230F0195), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB1_CLEAR , RULL(0x220F0195), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0195, -REG64( EX_1_CPPM_CMEDB1_OR , RULL(0x230F0196), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB1_OR , RULL(0x220F0196), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F0196, REG64( EX_2_CPPM_CMEDB1 , RULL(0x240F0194), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0194, @@ -6950,11 +7016,11 @@ REG64( EX_0_CPPM_CMEDB2_CLEAR , RULL(0x200F0199 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0199, REG64( EX_0_CPPM_CMEDB2_OR , RULL(0x200F019A), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F019A, -REG64( EX_1_CPPM_CMEDB2 , RULL(0x230F0198), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB2 , RULL(0x220F0198), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0198, -REG64( EX_1_CPPM_CMEDB2_CLEAR , RULL(0x230F0199), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB2_CLEAR , RULL(0x220F0199), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0199, -REG64( EX_1_CPPM_CMEDB2_OR , RULL(0x230F019A), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB2_OR , RULL(0x220F019A), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F019A, REG64( EX_2_CPPM_CMEDB2 , RULL(0x240F0198), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0198, @@ -7129,11 +7195,11 @@ REG64( EX_0_CPPM_CMEDB3_CLEAR , RULL(0x200F019D SH_ACS_SCOM1_CLEAR ); //DUPS: 210F019D, REG64( EX_0_CPPM_CMEDB3_OR , RULL(0x200F019E), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F019E, -REG64( EX_1_CPPM_CMEDB3 , RULL(0x230F019C), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB3 , RULL(0x220F019C), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F019C, -REG64( EX_1_CPPM_CMEDB3_CLEAR , RULL(0x230F019D), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB3_CLEAR , RULL(0x220F019D), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F019D, -REG64( EX_1_CPPM_CMEDB3_OR , RULL(0x230F019E), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEDB3_OR , RULL(0x220F019E), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F019E, REG64( EX_2_CPPM_CMEDB3 , RULL(0x240F019C), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F019C, @@ -7225,7 +7291,7 @@ REG64( EX_CPPM_CMEMSG , RULL(0x200F01AB SH_ACS_SCOM_RW ); //DUPS: 210F01AB, REG64( EX_0_CPPM_CMEMSG , RULL(0x200F01AB), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01AB, -REG64( EX_1_CPPM_CMEMSG , RULL(0x230F01AB), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CMEMSG , RULL(0x220F01AB), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01AB, REG64( EX_2_CPPM_CMEMSG , RULL(0x240F01AB), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01AB, @@ -7360,11 +7426,11 @@ REG64( EX_0_CPPM_CPMMR_CLEAR , RULL(0x200F0107 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0107, REG64( EX_0_CPPM_CPMMR_OR , RULL(0x200F0108), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F0108, -REG64( EX_1_CPPM_CPMMR , RULL(0x230F0106), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CPMMR , RULL(0x220F0106), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0106, -REG64( EX_1_CPPM_CPMMR_CLEAR , RULL(0x230F0107), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CPMMR_CLEAR , RULL(0x220F0107), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0107, -REG64( EX_1_CPPM_CPMMR_OR , RULL(0x230F0108), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CPMMR_OR , RULL(0x220F0108), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F0108, REG64( EX_2_CPPM_CPMMR , RULL(0x240F0106), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0106, @@ -7539,11 +7605,11 @@ REG64( EX_0_CPPM_CSAR_CLEAR , RULL(0x200F0139 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0139, REG64( EX_0_CPPM_CSAR_OR , RULL(0x200F013A), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F013A, -REG64( EX_1_CPPM_CSAR , RULL(0x230F0138), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CSAR , RULL(0x220F0138), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0138, -REG64( EX_1_CPPM_CSAR_CLEAR , RULL(0x230F0139), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CSAR_CLEAR , RULL(0x220F0139), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0139, -REG64( EX_1_CPPM_CSAR_OR , RULL(0x230F013A), SH_UNT_EX_1 , +REG64( EX_1_CPPM_CSAR_OR , RULL(0x220F013A), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F013A, REG64( EX_2_CPPM_CSAR , RULL(0x240F0138), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0138, @@ -7635,7 +7701,7 @@ REG64( EX_CPPM_ERR , RULL(0x200F0121 SH_ACS_SCOM ); //DUPS: 210F0121, REG64( EX_0_CPPM_ERR , RULL(0x200F0121), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0121, -REG64( EX_1_CPPM_ERR , RULL(0x230F0121), SH_UNT_EX_1 , +REG64( EX_1_CPPM_ERR , RULL(0x220F0121), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0121, REG64( EX_2_CPPM_ERR , RULL(0x240F0121), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0121, @@ -7687,7 +7753,7 @@ REG64( EX_CPPM_ERRMSK , RULL(0x200F0122 SH_ACS_SCOM_RW ); //DUPS: 210F0122, REG64( EX_0_CPPM_ERRMSK , RULL(0x200F0122), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0122, -REG64( EX_1_CPPM_ERRMSK , RULL(0x230F0122), SH_UNT_EX_1 , +REG64( EX_1_CPPM_ERRMSK , RULL(0x220F0122), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0122, REG64( EX_2_CPPM_ERRMSK , RULL(0x240F0122), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0122, @@ -7739,7 +7805,7 @@ REG64( EX_CPPM_IPPMCMD , RULL(0x200F01C0 SH_ACS_SCOM_RW ); //DUPS: 210F01C0, REG64( EX_0_CPPM_IPPMCMD , RULL(0x200F01C0), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01C0, -REG64( EX_1_CPPM_IPPMCMD , RULL(0x230F01C0), SH_UNT_EX_1 , +REG64( EX_1_CPPM_IPPMCMD , RULL(0x220F01C0), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01C0, REG64( EX_2_CPPM_IPPMCMD , RULL(0x240F01C0), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01C0, @@ -7791,7 +7857,7 @@ REG64( EX_CPPM_IPPMRDATA , RULL(0x200F01C3 SH_ACS_SCOM_RW ); //DUPS: 210F01C3, REG64( EX_0_CPPM_IPPMRDATA , RULL(0x200F01C3), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01C3, -REG64( EX_1_CPPM_IPPMRDATA , RULL(0x230F01C3), SH_UNT_EX_1 , +REG64( EX_1_CPPM_IPPMRDATA , RULL(0x220F01C3), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01C3, REG64( EX_2_CPPM_IPPMRDATA , RULL(0x240F01C3), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01C3, @@ -7843,7 +7909,7 @@ REG64( EX_CPPM_IPPMSTAT , RULL(0x200F01C1 SH_ACS_SCOM_RO ); //DUPS: 210F01C1, REG64( EX_0_CPPM_IPPMSTAT , RULL(0x200F01C1), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F01C1, -REG64( EX_1_CPPM_IPPMSTAT , RULL(0x230F01C1), SH_UNT_EX_1 , +REG64( EX_1_CPPM_IPPMSTAT , RULL(0x220F01C1), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F01C1, REG64( EX_2_CPPM_IPPMSTAT , RULL(0x240F01C1), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F01C1, @@ -7895,7 +7961,7 @@ REG64( EX_CPPM_IPPMWDATA , RULL(0x200F01C2 SH_ACS_SCOM_RW ); //DUPS: 210F01C2, REG64( EX_0_CPPM_IPPMWDATA , RULL(0x200F01C2), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01C2, -REG64( EX_1_CPPM_IPPMWDATA , RULL(0x230F01C2), SH_UNT_EX_1 , +REG64( EX_1_CPPM_IPPMWDATA , RULL(0x220F01C2), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01C2, REG64( EX_2_CPPM_IPPMWDATA , RULL(0x240F01C2), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01C2, @@ -8005,11 +8071,11 @@ REG64( EX_0_CPPM_NC0INDIR_SCOM1 , RULL(0x200F0131 SH_ACS_SCOM1_NC ); //DUPS: 210F0131, REG64( EX_0_CPPM_NC0INDIR_SCOM2 , RULL(0x200F0132), SH_UNT_EX_0 , SH_ACS_SCOM2_NC ); //DUPS: 210F0132, -REG64( EX_1_CPPM_NC0INDIR_SCOM , RULL(0x230F0130), SH_UNT_EX_1 , +REG64( EX_1_CPPM_NC0INDIR_SCOM , RULL(0x220F0130), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F0130, -REG64( EX_1_CPPM_NC0INDIR_SCOM1 , RULL(0x230F0131), SH_UNT_EX_1 , +REG64( EX_1_CPPM_NC0INDIR_SCOM1 , RULL(0x220F0131), SH_UNT_EX_1 , SH_ACS_SCOM1_NC ); //DUPS: 220F0131, -REG64( EX_1_CPPM_NC0INDIR_SCOM2 , RULL(0x230F0132), SH_UNT_EX_1 , +REG64( EX_1_CPPM_NC0INDIR_SCOM2 , RULL(0x220F0132), SH_UNT_EX_1 , SH_ACS_SCOM2_NC ); //DUPS: 220F0132, REG64( EX_2_CPPM_NC0INDIR_SCOM , RULL(0x240F0130), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F0130, @@ -8159,11 +8225,11 @@ REG64( EX_0_CPPM_NC1INDIR_SCOM1 , RULL(0x200F0134 SH_ACS_SCOM1_NC ); //DUPS: 210F0134, REG64( EX_0_CPPM_NC1INDIR_SCOM2 , RULL(0x200F0135), SH_UNT_EX_0 , SH_ACS_SCOM2_NC ); //DUPS: 210F0135, -REG64( EX_1_CPPM_NC1INDIR_SCOM , RULL(0x230F0133), SH_UNT_EX_1 , +REG64( EX_1_CPPM_NC1INDIR_SCOM , RULL(0x220F0133), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F0133, -REG64( EX_1_CPPM_NC1INDIR_SCOM1 , RULL(0x230F0134), SH_UNT_EX_1 , +REG64( EX_1_CPPM_NC1INDIR_SCOM1 , RULL(0x220F0134), SH_UNT_EX_1 , SH_ACS_SCOM1_NC ); //DUPS: 220F0134, -REG64( EX_1_CPPM_NC1INDIR_SCOM2 , RULL(0x230F0135), SH_UNT_EX_1 , +REG64( EX_1_CPPM_NC1INDIR_SCOM2 , RULL(0x220F0135), SH_UNT_EX_1 , SH_ACS_SCOM2_NC ); //DUPS: 220F0135, REG64( EX_2_CPPM_NC1INDIR_SCOM , RULL(0x240F0133), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F0133, @@ -8255,7 +8321,7 @@ REG64( EX_CPPM_PECES , RULL(0x200F01AF SH_ACS_SCOM_RW ); //DUPS: 210F01AF, REG64( EX_0_CPPM_PECES , RULL(0x200F01AF), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01AF, -REG64( EX_1_CPPM_PECES , RULL(0x230F01AF), SH_UNT_EX_1 , +REG64( EX_1_CPPM_PECES , RULL(0x220F01AF), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01AF, REG64( EX_2_CPPM_PECES , RULL(0x240F01AF), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01AF, @@ -8332,7 +8398,7 @@ REG64( EX_CPPM_PERRSUM , RULL(0x200F0120 SH_ACS_SCOM_WCLEAR ); //DUPS: 210F0120, REG64( EX_0_CPPM_PERRSUM , RULL(0x200F0120), SH_UNT_EX_0 , SH_ACS_SCOM_WCLEAR ); //DUPS: 210F0120, -REG64( EX_1_CPPM_PERRSUM , RULL(0x230F0120), SH_UNT_EX_1 , +REG64( EX_1_CPPM_PERRSUM , RULL(0x220F0120), SH_UNT_EX_1 , SH_ACS_SCOM_WCLEAR ); //DUPS: 220F0120, REG64( EX_2_CPPM_PERRSUM , RULL(0x240F0120), SH_UNT_EX_2 , SH_ACS_SCOM_WCLEAR ); //DUPS: 250F0120, @@ -8355,19 +8421,19 @@ REG64( EX_10_CPPM_PERRSUM , RULL(0x340F0120 REG64( EX_11_CPPM_PERRSUM , RULL(0x360F0120), SH_UNT_EX_11 , SH_ACS_SCOM_WCLEAR ); //DUPS: 370F0120, -REG64( EQ_CSAR , RULL(0x1001240D), SH_UNT_EQ , +REG64( EQ_CSAR , RULL(0x1001200D), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001200D, -REG64( EQ_0_CSAR , RULL(0x1001240D), SH_UNT_EQ_0 , +REG64( EQ_0_CSAR , RULL(0x1001200D), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001200D, -REG64( EQ_1_CSAR , RULL(0x1101240D), SH_UNT_EQ_1 , +REG64( EQ_1_CSAR , RULL(0x1101200D), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101200D, -REG64( EQ_2_CSAR , RULL(0x1201240D), SH_UNT_EQ_2 , +REG64( EQ_2_CSAR , RULL(0x1201200D), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201200D, -REG64( EQ_3_CSAR , RULL(0x1301240D), SH_UNT_EQ_3 , +REG64( EQ_3_CSAR , RULL(0x1301200D), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301200D, -REG64( EQ_4_CSAR , RULL(0x1401240D), SH_UNT_EQ_4 , +REG64( EQ_4_CSAR , RULL(0x1401200D), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401200D, -REG64( EQ_5_CSAR , RULL(0x1501240D), SH_UNT_EQ_5 , +REG64( EQ_5_CSAR , RULL(0x1501200D), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501200D, REG64( EX_CSAR , RULL(0x1001200D), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CSAR , RULL(0x1001200D), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -8383,47 +8449,47 @@ REG64( EX_9_CSAR , RULL(0x1401240D REG64( EX_10_CSAR , RULL(0x1501200D), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); REG64( EX_11_CSAR , RULL(0x1501240D), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); -REG64( EQ_CSCR , RULL(0x1001240A), SH_UNT_EQ , +REG64( EQ_CSCR , RULL(0x1001200A), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001200A, -REG64( EQ_CSCR_CLEAR , RULL(0x1001240B), SH_UNT_EQ , +REG64( EQ_CSCR_CLEAR , RULL(0x1001200B), SH_UNT_EQ , SH_ACS_SCOM1_CLEAR ); //DUPS: 1001200B, -REG64( EQ_CSCR_OR , RULL(0x1001240C), SH_UNT_EQ , +REG64( EQ_CSCR_OR , RULL(0x1001200C), SH_UNT_EQ , SH_ACS_SCOM2_OR ); //DUPS: 1001200C, -REG64( EQ_0_CSCR , RULL(0x1001240A), SH_UNT_EQ_0 , +REG64( EQ_0_CSCR , RULL(0x1001200A), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001200A, -REG64( EQ_0_CSCR_CLEAR , RULL(0x1001240B), SH_UNT_EQ_0 , +REG64( EQ_0_CSCR_CLEAR , RULL(0x1001200B), SH_UNT_EQ_0 , SH_ACS_SCOM1_CLEAR ); //DUPS: 1001200B, -REG64( EQ_0_CSCR_OR , RULL(0x1001240C), SH_UNT_EQ_0 , +REG64( EQ_0_CSCR_OR , RULL(0x1001200C), SH_UNT_EQ_0 , SH_ACS_SCOM2_OR ); //DUPS: 1001200C, -REG64( EQ_1_CSCR , RULL(0x1101240A), SH_UNT_EQ_1 , +REG64( EQ_1_CSCR , RULL(0x1101200A), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101200A, -REG64( EQ_1_CSCR_CLEAR , RULL(0x1101240B), SH_UNT_EQ_1 , +REG64( EQ_1_CSCR_CLEAR , RULL(0x1101200B), SH_UNT_EQ_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 1101200B, -REG64( EQ_1_CSCR_OR , RULL(0x1101240C), SH_UNT_EQ_1 , +REG64( EQ_1_CSCR_OR , RULL(0x1101200C), SH_UNT_EQ_1 , SH_ACS_SCOM2_OR ); //DUPS: 1101200C, -REG64( EQ_2_CSCR , RULL(0x1201240A), SH_UNT_EQ_2 , +REG64( EQ_2_CSCR , RULL(0x1201200A), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201200A, -REG64( EQ_2_CSCR_CLEAR , RULL(0x1201240B), SH_UNT_EQ_2 , +REG64( EQ_2_CSCR_CLEAR , RULL(0x1201200B), SH_UNT_EQ_2 , SH_ACS_SCOM1_CLEAR ); //DUPS: 1201200B, -REG64( EQ_2_CSCR_OR , RULL(0x1201240C), SH_UNT_EQ_2 , +REG64( EQ_2_CSCR_OR , RULL(0x1201200C), SH_UNT_EQ_2 , SH_ACS_SCOM2_OR ); //DUPS: 1201200C, -REG64( EQ_3_CSCR , RULL(0x1301240A), SH_UNT_EQ_3 , +REG64( EQ_3_CSCR , RULL(0x1301200A), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301200A, -REG64( EQ_3_CSCR_CLEAR , RULL(0x1301240B), SH_UNT_EQ_3 , +REG64( EQ_3_CSCR_CLEAR , RULL(0x1301200B), SH_UNT_EQ_3 , SH_ACS_SCOM1_CLEAR ); //DUPS: 1301200B, -REG64( EQ_3_CSCR_OR , RULL(0x1301240C), SH_UNT_EQ_3 , +REG64( EQ_3_CSCR_OR , RULL(0x1301200C), SH_UNT_EQ_3 , SH_ACS_SCOM2_OR ); //DUPS: 1301200C, -REG64( EQ_4_CSCR , RULL(0x1401240A), SH_UNT_EQ_4 , +REG64( EQ_4_CSCR , RULL(0x1401200A), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401200A, -REG64( EQ_4_CSCR_CLEAR , RULL(0x1401240B), SH_UNT_EQ_4 , +REG64( EQ_4_CSCR_CLEAR , RULL(0x1401200B), SH_UNT_EQ_4 , SH_ACS_SCOM1_CLEAR ); //DUPS: 1401200B, -REG64( EQ_4_CSCR_OR , RULL(0x1401240C), SH_UNT_EQ_4 , +REG64( EQ_4_CSCR_OR , RULL(0x1401200C), SH_UNT_EQ_4 , SH_ACS_SCOM2_OR ); //DUPS: 1401200C, -REG64( EQ_5_CSCR , RULL(0x1501240A), SH_UNT_EQ_5 , +REG64( EQ_5_CSCR , RULL(0x1501200A), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501200A, -REG64( EQ_5_CSCR_CLEAR , RULL(0x1501240B), SH_UNT_EQ_5 , +REG64( EQ_5_CSCR_CLEAR , RULL(0x1501200B), SH_UNT_EQ_5 , SH_ACS_SCOM1_CLEAR ); //DUPS: 1501200B, -REG64( EQ_5_CSCR_OR , RULL(0x1501240C), SH_UNT_EQ_5 , +REG64( EQ_5_CSCR_OR , RULL(0x1501200C), SH_UNT_EQ_5 , SH_ACS_SCOM2_OR ); //DUPS: 1501200C, REG64( EX_CSCR , RULL(0x1001200A), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_CSCR_CLEAR , RULL(0x1001200B), SH_UNT_EX , @@ -8478,19 +8544,19 @@ REG64( EX_11_CSCR_CLEAR , RULL(0x1501240B SH_ACS_SCOM1_CLEAR ); REG64( EX_11_CSCR_OR , RULL(0x1501240C), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); -REG64( EQ_CSDR , RULL(0x1001240E), SH_UNT_EQ , +REG64( EQ_CSDR , RULL(0x1001200E), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001200E, -REG64( EQ_0_CSDR , RULL(0x1001240E), SH_UNT_EQ_0 , +REG64( EQ_0_CSDR , RULL(0x1001200E), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001200E, -REG64( EQ_1_CSDR , RULL(0x1101240E), SH_UNT_EQ_1 , +REG64( EQ_1_CSDR , RULL(0x1101200E), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101200E, -REG64( EQ_2_CSDR , RULL(0x1201240E), SH_UNT_EQ_2 , +REG64( EQ_2_CSDR , RULL(0x1201200E), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201200E, -REG64( EQ_3_CSDR , RULL(0x1301240E), SH_UNT_EQ_3 , +REG64( EQ_3_CSDR , RULL(0x1301200E), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301200E, -REG64( EQ_4_CSDR , RULL(0x1401240E), SH_UNT_EQ_4 , +REG64( EQ_4_CSDR , RULL(0x1401200E), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401200E, -REG64( EQ_5_CSDR , RULL(0x1501240E), SH_UNT_EQ_5 , +REG64( EQ_5_CSDR , RULL(0x1501200E), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501200E, REG64( EX_CSDR , RULL(0x1001200E), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_CSDR , RULL(0x1001200E), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -8531,19 +8597,19 @@ REG64( C_20_CTRL , RULL(0x34010A85 REG64( C_21_CTRL , RULL(0x35010A85), SH_UNT_C_21 , SH_ACS_SCOM_NC ); REG64( C_22_CTRL , RULL(0x36010A85), SH_UNT_C_22 , SH_ACS_SCOM_NC ); REG64( C_23_CTRL , RULL(0x37010A85), SH_UNT_C_23 , SH_ACS_SCOM_NC ); -REG64( EX_0_L2_CTRL , RULL(0x21010A85), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_CTRL , RULL(0x20010A85), SH_UNT_EX_0_L2 , SH_ACS_SCOM_NC ); //DUPS: 20010A85, -REG64( EX_10_L2_CTRL , RULL(0x35010A85), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_CTRL , RULL(0x34010A85), SH_UNT_EX_10_L2 , SH_ACS_SCOM_NC ); //DUPS: 34010A85, -REG64( EX_11_L2_CTRL , RULL(0x37010A85), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_CTRL , RULL(0x36010A85), SH_UNT_EX_11_L2 , SH_ACS_SCOM_NC ); //DUPS: 36010A85, -REG64( EX_1_L2_CTRL , RULL(0x23010A85), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_CTRL , RULL(0x22010A85), SH_UNT_EX_1_L2 , SH_ACS_SCOM_NC ); //DUPS: 22010A85, -REG64( EX_2_L2_CTRL , RULL(0x25010A85), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_CTRL , RULL(0x24010A85), SH_UNT_EX_2_L2 , SH_ACS_SCOM_NC ); //DUPS: 24010A85, -REG64( EX_3_L2_CTRL , RULL(0x27010A85), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_CTRL , RULL(0x26010A85), SH_UNT_EX_3_L2 , SH_ACS_SCOM_NC ); //DUPS: 26010A85, -REG64( EX_4_L2_CTRL , RULL(0x29010A85), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_CTRL , RULL(0x28010A85), SH_UNT_EX_4_L2 , SH_ACS_SCOM_NC ); //DUPS: 28010A85, REG64( EX_5_L2_CTRL , RULL(0x2B010A85), SH_UNT_EX_5_L2 , SH_ACS_SCOM_NC ); //DUPS: 2A010A85, @@ -8551,11 +8617,11 @@ REG64( EX_6_L2_CTRL , RULL(0x2D010A85 SH_ACS_SCOM_NC ); //DUPS: 2C010A85, REG64( EX_7_L2_CTRL , RULL(0x2F010A85), SH_UNT_EX_7_L2 , SH_ACS_SCOM_NC ); //DUPS: 2E010A85, -REG64( EX_8_L2_CTRL , RULL(0x31010A85), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_CTRL , RULL(0x30010A85), SH_UNT_EX_8_L2 , SH_ACS_SCOM_NC ); //DUPS: 30010A85, -REG64( EX_9_L2_CTRL , RULL(0x33010A85), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_CTRL , RULL(0x32010A85), SH_UNT_EX_9_L2 , SH_ACS_SCOM_NC ); //DUPS: 32010A85, -REG64( EX_L2_CTRL , RULL(0x21010A85), SH_UNT_EX_L2 , +REG64( EX_L2_CTRL , RULL(0x20010A85), SH_UNT_EX_L2 , SH_ACS_SCOM_NC ); //DUPS: 20010A85, REG64( C_CTRL_ATOMIC_LOCK_REG , RULL(0x200003FF), SH_UNT_C , SH_ACS_SCOM ); @@ -8606,7 +8672,7 @@ REG64( EX_5_CTRL_ATOMIC_LOCK_REG , RULL(0x2A0003FF SH_ACS_SCOM ); //DUPS: 2B0003FF, REG64( EX_6_CTRL_ATOMIC_LOCK_REG , RULL(0x2C0003FF), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0003FF, -REG64( EX_7_CTRL_ATOMIC_LOCK_REG , RULL(0x2E0003FF), SH_UNT_EX_7 , +REG64( EX_7_CTRL_ATOMIC_LOCK_REG , RULL(0x2F0003FF), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0003FF, REG64( EX_8_CTRL_ATOMIC_LOCK_REG , RULL(0x300003FF), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310003FF, @@ -8665,7 +8731,7 @@ REG64( EX_5_CTRL_PROTECT_MODE_REG , RULL(0x2A0003FE SH_ACS_SCOM ); //DUPS: 2B0003FE, REG64( EX_6_CTRL_PROTECT_MODE_REG , RULL(0x2C0003FE), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0003FE, -REG64( EX_7_CTRL_PROTECT_MODE_REG , RULL(0x2E0003FE), SH_UNT_EX_7 , +REG64( EX_7_CTRL_PROTECT_MODE_REG , RULL(0x2F0003FE), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0003FE, REG64( EX_8_CTRL_PROTECT_MODE_REG , RULL(0x300003FE), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310003FE, @@ -8724,7 +8790,7 @@ REG64( EX_5_DBG_CBS_CC , RULL(0x2A030013 SH_ACS_SCOM ); //DUPS: 2B030013, REG64( EX_6_DBG_CBS_CC , RULL(0x2C030013), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030013, -REG64( EX_7_DBG_CBS_CC , RULL(0x2E030013), SH_UNT_EX_7 , +REG64( EX_7_DBG_CBS_CC , RULL(0x2F030013), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030013, REG64( EX_8_DBG_CBS_CC , RULL(0x30030013), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030013, @@ -8783,7 +8849,7 @@ REG64( EX_5_DBG_INST1_COND_REG_1 , RULL(0x2A0107C1 SH_ACS_SCOM ); //DUPS: 2B0107C1, REG64( EX_6_DBG_INST1_COND_REG_1 , RULL(0x2C0107C1), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C1, -REG64( EX_7_DBG_INST1_COND_REG_1 , RULL(0x2E0107C1), SH_UNT_EX_7 , +REG64( EX_7_DBG_INST1_COND_REG_1 , RULL(0x2F0107C1), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C1, REG64( EX_8_DBG_INST1_COND_REG_1 , RULL(0x300107C1), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C1, @@ -8842,7 +8908,7 @@ REG64( EX_5_DBG_INST1_COND_REG_2 , RULL(0x2A0107C2 SH_ACS_SCOM ); //DUPS: 2B0107C2, REG64( EX_6_DBG_INST1_COND_REG_2 , RULL(0x2C0107C2), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C2, -REG64( EX_7_DBG_INST1_COND_REG_2 , RULL(0x2E0107C2), SH_UNT_EX_7 , +REG64( EX_7_DBG_INST1_COND_REG_2 , RULL(0x2F0107C2), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C2, REG64( EX_8_DBG_INST1_COND_REG_2 , RULL(0x300107C2), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C2, @@ -8901,7 +8967,7 @@ REG64( EX_5_DBG_INST1_COND_REG_3 , RULL(0x2A0107C3 SH_ACS_SCOM ); //DUPS: 2B0107C3, REG64( EX_6_DBG_INST1_COND_REG_3 , RULL(0x2C0107C3), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C3, -REG64( EX_7_DBG_INST1_COND_REG_3 , RULL(0x2E0107C3), SH_UNT_EX_7 , +REG64( EX_7_DBG_INST1_COND_REG_3 , RULL(0x2F0107C3), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C3, REG64( EX_8_DBG_INST1_COND_REG_3 , RULL(0x300107C3), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C3, @@ -8960,7 +9026,7 @@ REG64( EX_5_DBG_INST2_COND_REG_1 , RULL(0x2A0107C4 SH_ACS_SCOM ); //DUPS: 2B0107C4, REG64( EX_6_DBG_INST2_COND_REG_1 , RULL(0x2C0107C4), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C4, -REG64( EX_7_DBG_INST2_COND_REG_1 , RULL(0x2E0107C4), SH_UNT_EX_7 , +REG64( EX_7_DBG_INST2_COND_REG_1 , RULL(0x2F0107C4), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C4, REG64( EX_8_DBG_INST2_COND_REG_1 , RULL(0x300107C4), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C4, @@ -9019,7 +9085,7 @@ REG64( EX_5_DBG_INST2_COND_REG_2 , RULL(0x2A0107C5 SH_ACS_SCOM ); //DUPS: 2B0107C5, REG64( EX_6_DBG_INST2_COND_REG_2 , RULL(0x2C0107C5), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C5, -REG64( EX_7_DBG_INST2_COND_REG_2 , RULL(0x2E0107C5), SH_UNT_EX_7 , +REG64( EX_7_DBG_INST2_COND_REG_2 , RULL(0x2F0107C5), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C5, REG64( EX_8_DBG_INST2_COND_REG_2 , RULL(0x300107C5), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C5, @@ -9078,7 +9144,7 @@ REG64( EX_5_DBG_INST2_COND_REG_3 , RULL(0x2A0107C6 SH_ACS_SCOM ); //DUPS: 2B0107C6, REG64( EX_6_DBG_INST2_COND_REG_3 , RULL(0x2C0107C6), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C6, -REG64( EX_7_DBG_INST2_COND_REG_3 , RULL(0x2E0107C6), SH_UNT_EX_7 , +REG64( EX_7_DBG_INST2_COND_REG_3 , RULL(0x2F0107C6), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C6, REG64( EX_8_DBG_INST2_COND_REG_3 , RULL(0x300107C6), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C6, @@ -9137,7 +9203,7 @@ REG64( EX_5_DBG_MODE_REG , RULL(0x2A0107C0 SH_ACS_SCOM ); //DUPS: 2B0107C0, REG64( EX_6_DBG_MODE_REG , RULL(0x2C0107C0), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107C0, -REG64( EX_7_DBG_MODE_REG , RULL(0x2E0107C0), SH_UNT_EX_7 , +REG64( EX_7_DBG_MODE_REG , RULL(0x2F0107C0), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107C0, REG64( EX_8_DBG_MODE_REG , RULL(0x300107C0), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107C0, @@ -9196,7 +9262,7 @@ REG64( EX_5_DBG_TRACE_MODE_REG_2 , RULL(0x2A0107CF SH_ACS_SCOM ); //DUPS: 2B0107CF, REG64( EX_6_DBG_TRACE_MODE_REG_2 , RULL(0x2C0107CF), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107CF, -REG64( EX_7_DBG_TRACE_MODE_REG_2 , RULL(0x2E0107CF), SH_UNT_EX_7 , +REG64( EX_7_DBG_TRACE_MODE_REG_2 , RULL(0x2F0107CF), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107CF, REG64( EX_8_DBG_TRACE_MODE_REG_2 , RULL(0x300107CF), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107CF, @@ -9255,7 +9321,7 @@ REG64( EX_5_DBG_TRACE_REG_0 , RULL(0x2A0107CD SH_ACS_SCOM ); //DUPS: 2B0107CD, REG64( EX_6_DBG_TRACE_REG_0 , RULL(0x2C0107CD), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107CD, -REG64( EX_7_DBG_TRACE_REG_0 , RULL(0x2E0107CD), SH_UNT_EX_7 , +REG64( EX_7_DBG_TRACE_REG_0 , RULL(0x2F0107CD), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107CD, REG64( EX_8_DBG_TRACE_REG_0 , RULL(0x300107CD), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107CD, @@ -9314,7 +9380,7 @@ REG64( EX_5_DBG_TRACE_REG_1 , RULL(0x2A0107CE SH_ACS_SCOM ); //DUPS: 2B0107CE, REG64( EX_6_DBG_TRACE_REG_1 , RULL(0x2C0107CE), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107CE, -REG64( EX_7_DBG_TRACE_REG_1 , RULL(0x2E0107CE), SH_UNT_EX_7 , +REG64( EX_7_DBG_TRACE_REG_1 , RULL(0x2F0107CE), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107CE, REG64( EX_8_DBG_TRACE_REG_1 , RULL(0x300107CE), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107CE, @@ -9373,7 +9439,7 @@ REG64( EX_5_DEBUG_TRACE_CONTROL , RULL(0x2A0107D0 SH_ACS_SCOM ); //DUPS: 2B0107D0, REG64( EX_6_DEBUG_TRACE_CONTROL , RULL(0x2C0107D0), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107D0, -REG64( EX_7_DEBUG_TRACE_CONTROL , RULL(0x2E0107D0), SH_UNT_EX_7 , +REG64( EX_7_DEBUG_TRACE_CONTROL , RULL(0x2F0107D0), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107D0, REG64( EX_8_DEBUG_TRACE_CONTROL , RULL(0x300107D0), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107D0, @@ -9409,19 +9475,19 @@ REG64( C_20_DIRECT_CONTROLS , RULL(0x34010A9C REG64( C_21_DIRECT_CONTROLS , RULL(0x35010A9C), SH_UNT_C_21 , SH_ACS_SCOM ); REG64( C_22_DIRECT_CONTROLS , RULL(0x36010A9C), SH_UNT_C_22 , SH_ACS_SCOM ); REG64( C_23_DIRECT_CONTROLS , RULL(0x37010A9C), SH_UNT_C_23 , SH_ACS_SCOM ); -REG64( EX_0_L2_DIRECT_CONTROLS , RULL(0x21010A9C), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_DIRECT_CONTROLS , RULL(0x20010A9C), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); //DUPS: 20010A9C, -REG64( EX_10_L2_DIRECT_CONTROLS , RULL(0x35010A9C), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_DIRECT_CONTROLS , RULL(0x34010A9C), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); //DUPS: 34010A9C, -REG64( EX_11_L2_DIRECT_CONTROLS , RULL(0x37010A9C), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_DIRECT_CONTROLS , RULL(0x36010A9C), SH_UNT_EX_11_L2 , SH_ACS_SCOM ); //DUPS: 36010A9C, -REG64( EX_1_L2_DIRECT_CONTROLS , RULL(0x23010A9C), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_DIRECT_CONTROLS , RULL(0x22010A9C), SH_UNT_EX_1_L2 , SH_ACS_SCOM ); //DUPS: 22010A9C, -REG64( EX_2_L2_DIRECT_CONTROLS , RULL(0x25010A9C), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_DIRECT_CONTROLS , RULL(0x24010A9C), SH_UNT_EX_2_L2 , SH_ACS_SCOM ); //DUPS: 24010A9C, -REG64( EX_3_L2_DIRECT_CONTROLS , RULL(0x27010A9C), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_DIRECT_CONTROLS , RULL(0x26010A9C), SH_UNT_EX_3_L2 , SH_ACS_SCOM ); //DUPS: 26010A9C, -REG64( EX_4_L2_DIRECT_CONTROLS , RULL(0x29010A9C), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_DIRECT_CONTROLS , RULL(0x28010A9C), SH_UNT_EX_4_L2 , SH_ACS_SCOM ); //DUPS: 28010A9C, REG64( EX_5_L2_DIRECT_CONTROLS , RULL(0x2B010A9C), SH_UNT_EX_5_L2 , SH_ACS_SCOM ); //DUPS: 2A010A9C, @@ -9429,26 +9495,26 @@ REG64( EX_6_L2_DIRECT_CONTROLS , RULL(0x2D010A9C SH_ACS_SCOM ); //DUPS: 2C010A9C, REG64( EX_7_L2_DIRECT_CONTROLS , RULL(0x2F010A9C), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2E010A9C, -REG64( EX_8_L2_DIRECT_CONTROLS , RULL(0x31010A9C), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_DIRECT_CONTROLS , RULL(0x30010A9C), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 30010A9C, -REG64( EX_9_L2_DIRECT_CONTROLS , RULL(0x33010A9C), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_DIRECT_CONTROLS , RULL(0x32010A9C), SH_UNT_EX_9_L2 , SH_ACS_SCOM ); //DUPS: 32010A9C, -REG64( EX_L2_DIRECT_CONTROLS , RULL(0x21010A9C), SH_UNT_EX_L2 , +REG64( EX_L2_DIRECT_CONTROLS , RULL(0x20010A9C), SH_UNT_EX_L2 , SH_ACS_SCOM ); //DUPS: 20010A9C, -REG64( EQ_DRAM_REF_REG , RULL(0x1001180F), SH_UNT_EQ , +REG64( EQ_DRAM_REF_REG , RULL(0x10011C0F), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C0F, -REG64( EQ_0_DRAM_REF_REG , RULL(0x1001180F), SH_UNT_EQ_0 , +REG64( EQ_0_DRAM_REF_REG , RULL(0x10011C0F), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C0F, -REG64( EQ_1_DRAM_REF_REG , RULL(0x1101180F), SH_UNT_EQ_1 , +REG64( EQ_1_DRAM_REF_REG , RULL(0x11011C0F), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C0F, -REG64( EQ_2_DRAM_REF_REG , RULL(0x1201180F), SH_UNT_EQ_2 , +REG64( EQ_2_DRAM_REF_REG , RULL(0x12011C0F), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C0F, -REG64( EQ_3_DRAM_REF_REG , RULL(0x1301180F), SH_UNT_EQ_3 , +REG64( EQ_3_DRAM_REF_REG , RULL(0x13011C0F), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C0F, -REG64( EQ_4_DRAM_REF_REG , RULL(0x1401180F), SH_UNT_EQ_4 , +REG64( EQ_4_DRAM_REF_REG , RULL(0x14011C0F), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C0F, -REG64( EQ_5_DRAM_REF_REG , RULL(0x1501180F), SH_UNT_EQ_5 , +REG64( EQ_5_DRAM_REF_REG , RULL(0x15011C0F), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C0F, REG64( EX_DRAM_REF_REG , RULL(0x1001180F), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_DRAM_REF_REG , RULL(0x1001180F), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -9512,7 +9578,7 @@ REG64( EX_5_DTS_RESULT0 , RULL(0x2A050000 SH_ACS_SCOM_RO ); //DUPS: 2B050000, REG64( EX_6_DTS_RESULT0 , RULL(0x2C050000), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D050000, -REG64( EX_7_DTS_RESULT0 , RULL(0x2E050000), SH_UNT_EX_7 , +REG64( EX_7_DTS_RESULT0 , RULL(0x2F050000), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F050000, REG64( EX_8_DTS_RESULT0 , RULL(0x30050000), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31050000, @@ -9571,7 +9637,7 @@ REG64( EX_5_DTS_TRC_RESULT , RULL(0x2A050003 SH_ACS_SCOM_RO ); //DUPS: 2B050003, REG64( EX_6_DTS_TRC_RESULT , RULL(0x2C050003), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D050003, -REG64( EX_7_DTS_TRC_RESULT , RULL(0x2E050003), SH_UNT_EX_7 , +REG64( EX_7_DTS_TRC_RESULT , RULL(0x2F050003), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F050003, REG64( EX_8_DTS_TRC_RESULT , RULL(0x30050003), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31050003, @@ -9582,19 +9648,19 @@ REG64( EX_10_DTS_TRC_RESULT , RULL(0x34050003 REG64( EX_11_DTS_TRC_RESULT , RULL(0x36050003), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); //DUPS: 37050003, -REG64( EQ_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1001181B), SH_UNT_EQ , +REG64( EQ_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x10011C1B), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C1B, -REG64( EQ_0_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1001181B), SH_UNT_EQ_0 , +REG64( EQ_0_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x10011C1B), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C1B, -REG64( EQ_1_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1101181B), SH_UNT_EQ_1 , +REG64( EQ_1_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x11011C1B), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C1B, -REG64( EQ_2_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1201181B), SH_UNT_EQ_2 , +REG64( EQ_2_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x12011C1B), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C1B, -REG64( EQ_3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1301181B), SH_UNT_EQ_3 , +REG64( EQ_3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x13011C1B), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C1B, -REG64( EQ_4_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1401181B), SH_UNT_EQ_4 , +REG64( EQ_4_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x14011C1B), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C1B, -REG64( EQ_5_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1501181B), SH_UNT_EQ_5 , +REG64( EQ_5_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x15011C1B), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C1B, REG64( EX_0_L3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1001181B), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1501181B), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -9610,19 +9676,19 @@ REG64( EX_8_L3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1401181B REG64( EX_9_L3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x14011C1B), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_EDRAM_BANK_FAIL_SCOM_RD , RULL(0x1001181B), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_EDRAM_BANK_SOFT_DIS , RULL(0x1001180B), SH_UNT_EQ , +REG64( EQ_EDRAM_BANK_SOFT_DIS , RULL(0x10011C0B), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C0B, -REG64( EQ_0_EDRAM_BANK_SOFT_DIS , RULL(0x1001180B), SH_UNT_EQ_0 , +REG64( EQ_0_EDRAM_BANK_SOFT_DIS , RULL(0x10011C0B), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C0B, -REG64( EQ_1_EDRAM_BANK_SOFT_DIS , RULL(0x1101180B), SH_UNT_EQ_1 , +REG64( EQ_1_EDRAM_BANK_SOFT_DIS , RULL(0x11011C0B), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C0B, -REG64( EQ_2_EDRAM_BANK_SOFT_DIS , RULL(0x1201180B), SH_UNT_EQ_2 , +REG64( EQ_2_EDRAM_BANK_SOFT_DIS , RULL(0x12011C0B), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C0B, -REG64( EQ_3_EDRAM_BANK_SOFT_DIS , RULL(0x1301180B), SH_UNT_EQ_3 , +REG64( EQ_3_EDRAM_BANK_SOFT_DIS , RULL(0x13011C0B), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C0B, -REG64( EQ_4_EDRAM_BANK_SOFT_DIS , RULL(0x1401180B), SH_UNT_EQ_4 , +REG64( EQ_4_EDRAM_BANK_SOFT_DIS , RULL(0x14011C0B), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C0B, -REG64( EQ_5_EDRAM_BANK_SOFT_DIS , RULL(0x1501180B), SH_UNT_EQ_5 , +REG64( EQ_5_EDRAM_BANK_SOFT_DIS , RULL(0x15011C0B), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C0B, REG64( EX_0_L3_EDRAM_BANK_SOFT_DIS , RULL(0x1001180B), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_EDRAM_BANK_SOFT_DIS , RULL(0x1501180B), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -9638,19 +9704,19 @@ REG64( EX_8_L3_EDRAM_BANK_SOFT_DIS , RULL(0x1401180B REG64( EX_9_L3_EDRAM_BANK_SOFT_DIS , RULL(0x14011C0B), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_EDRAM_BANK_SOFT_DIS , RULL(0x1001180B), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_EDRAM_REG , RULL(0x1001180C), SH_UNT_EQ , +REG64( EQ_EDRAM_REG , RULL(0x10011C0C), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C0C, -REG64( EQ_0_EDRAM_REG , RULL(0x1001180C), SH_UNT_EQ_0 , +REG64( EQ_0_EDRAM_REG , RULL(0x10011C0C), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C0C, -REG64( EQ_1_EDRAM_REG , RULL(0x1101180C), SH_UNT_EQ_1 , +REG64( EQ_1_EDRAM_REG , RULL(0x11011C0C), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C0C, -REG64( EQ_2_EDRAM_REG , RULL(0x1201180C), SH_UNT_EQ_2 , +REG64( EQ_2_EDRAM_REG , RULL(0x12011C0C), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C0C, -REG64( EQ_3_EDRAM_REG , RULL(0x1301180C), SH_UNT_EQ_3 , +REG64( EQ_3_EDRAM_REG , RULL(0x13011C0C), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C0C, -REG64( EQ_4_EDRAM_REG , RULL(0x1401180C), SH_UNT_EQ_4 , +REG64( EQ_4_EDRAM_REG , RULL(0x14011C0C), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C0C, -REG64( EQ_5_EDRAM_REG , RULL(0x1501180C), SH_UNT_EQ_5 , +REG64( EQ_5_EDRAM_REG , RULL(0x15011C0C), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C0C, REG64( EX_0_L3_EDRAM_REG , RULL(0x1001180C), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_EDRAM_REG , RULL(0x1501180C), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -9666,19 +9732,78 @@ REG64( EX_8_L3_EDRAM_REG , RULL(0x1401180C REG64( EX_9_L3_EDRAM_REG , RULL(0x14011C0C), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_EDRAM_REG , RULL(0x1001180C), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_ED_RD_ERR_STAT_REG0 , RULL(0x10011819), SH_UNT_EQ , +REG64( C_EDRAM_STATUS , RULL(0x200F0029), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_EDRAM_STATUS , RULL(0x200F0029), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_EDRAM_STATUS , RULL(0x210F0029), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_EDRAM_STATUS , RULL(0x220F0029), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_EDRAM_STATUS , RULL(0x230F0029), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_EDRAM_STATUS , RULL(0x240F0029), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_EDRAM_STATUS , RULL(0x250F0029), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_EDRAM_STATUS , RULL(0x260F0029), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_EDRAM_STATUS , RULL(0x270F0029), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_EDRAM_STATUS , RULL(0x280F0029), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_EDRAM_STATUS , RULL(0x290F0029), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_EDRAM_STATUS , RULL(0x2A0F0029), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_EDRAM_STATUS , RULL(0x2B0F0029), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_EDRAM_STATUS , RULL(0x2C0F0029), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_EDRAM_STATUS , RULL(0x2D0F0029), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_EDRAM_STATUS , RULL(0x2E0F0029), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_EDRAM_STATUS , RULL(0x2F0F0029), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_EDRAM_STATUS , RULL(0x300F0029), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_EDRAM_STATUS , RULL(0x310F0029), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_EDRAM_STATUS , RULL(0x320F0029), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_EDRAM_STATUS , RULL(0x330F0029), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_EDRAM_STATUS , RULL(0x340F0029), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_EDRAM_STATUS , RULL(0x350F0029), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_EDRAM_STATUS , RULL(0x360F0029), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_EDRAM_STATUS , RULL(0x370F0029), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_EDRAM_STATUS , RULL(0x100F0029), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_EDRAM_STATUS , RULL(0x100F0029), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_EDRAM_STATUS , RULL(0x110F0029), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_EDRAM_STATUS , RULL(0x120F0029), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_EDRAM_STATUS , RULL(0x130F0029), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_EDRAM_STATUS , RULL(0x140F0029), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_EDRAM_STATUS , RULL(0x150F0029), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_EDRAM_STATUS , RULL(0x200F0029), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 210F0029, +REG64( EX_0_EDRAM_STATUS , RULL(0x200F0029), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 210F0029, +REG64( EX_1_EDRAM_STATUS , RULL(0x220F0029), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 220F0029, +REG64( EX_2_EDRAM_STATUS , RULL(0x240F0029), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 250F0029, +REG64( EX_3_EDRAM_STATUS , RULL(0x260F0029), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 270F0029, +REG64( EX_4_EDRAM_STATUS , RULL(0x280F0029), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 290F0029, +REG64( EX_5_EDRAM_STATUS , RULL(0x2A0F0029), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B0F0029, +REG64( EX_6_EDRAM_STATUS , RULL(0x2C0F0029), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D0F0029, +REG64( EX_7_EDRAM_STATUS , RULL(0x2E0F0029), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F0F0029, +REG64( EX_8_EDRAM_STATUS , RULL(0x300F0029), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 310F0029, +REG64( EX_9_EDRAM_STATUS , RULL(0x320F0029), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 330F0029, +REG64( EX_10_EDRAM_STATUS , RULL(0x340F0029), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 350F0029, +REG64( EX_11_EDRAM_STATUS , RULL(0x360F0029), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 370F0029, + +REG64( EQ_ED_RD_ERR_STAT_REG0 , RULL(0x10011C19), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C19, -REG64( EQ_0_ED_RD_ERR_STAT_REG0 , RULL(0x10011819), SH_UNT_EQ_0 , +REG64( EQ_0_ED_RD_ERR_STAT_REG0 , RULL(0x10011C19), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C19, -REG64( EQ_1_ED_RD_ERR_STAT_REG0 , RULL(0x11011819), SH_UNT_EQ_1 , +REG64( EQ_1_ED_RD_ERR_STAT_REG0 , RULL(0x11011C19), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C19, -REG64( EQ_2_ED_RD_ERR_STAT_REG0 , RULL(0x12011819), SH_UNT_EQ_2 , +REG64( EQ_2_ED_RD_ERR_STAT_REG0 , RULL(0x12011C19), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C19, -REG64( EQ_3_ED_RD_ERR_STAT_REG0 , RULL(0x13011819), SH_UNT_EQ_3 , +REG64( EQ_3_ED_RD_ERR_STAT_REG0 , RULL(0x13011C19), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C19, -REG64( EQ_4_ED_RD_ERR_STAT_REG0 , RULL(0x14011819), SH_UNT_EQ_4 , +REG64( EQ_4_ED_RD_ERR_STAT_REG0 , RULL(0x14011C19), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C19, -REG64( EQ_5_ED_RD_ERR_STAT_REG0 , RULL(0x15011819), SH_UNT_EQ_5 , +REG64( EQ_5_ED_RD_ERR_STAT_REG0 , RULL(0x15011C19), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C19, REG64( EX_ED_RD_ERR_STAT_REG0 , RULL(0x10011819), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_ED_RD_ERR_STAT_REG0 , RULL(0x10011819), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -9694,19 +9819,19 @@ REG64( EX_9_ED_RD_ERR_STAT_REG0 , RULL(0x14011C19 REG64( EX_10_ED_RD_ERR_STAT_REG0 , RULL(0x15011819), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_ED_RD_ERR_STAT_REG0 , RULL(0x15011C19), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_ED_RD_ERR_STAT_REG1 , RULL(0x1001181A), SH_UNT_EQ , +REG64( EQ_ED_RD_ERR_STAT_REG1 , RULL(0x10011C1A), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C1A, -REG64( EQ_0_ED_RD_ERR_STAT_REG1 , RULL(0x1001181A), SH_UNT_EQ_0 , +REG64( EQ_0_ED_RD_ERR_STAT_REG1 , RULL(0x10011C1A), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C1A, -REG64( EQ_1_ED_RD_ERR_STAT_REG1 , RULL(0x1101181A), SH_UNT_EQ_1 , +REG64( EQ_1_ED_RD_ERR_STAT_REG1 , RULL(0x11011C1A), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C1A, -REG64( EQ_2_ED_RD_ERR_STAT_REG1 , RULL(0x1201181A), SH_UNT_EQ_2 , +REG64( EQ_2_ED_RD_ERR_STAT_REG1 , RULL(0x12011C1A), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C1A, -REG64( EQ_3_ED_RD_ERR_STAT_REG1 , RULL(0x1301181A), SH_UNT_EQ_3 , +REG64( EQ_3_ED_RD_ERR_STAT_REG1 , RULL(0x13011C1A), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C1A, -REG64( EQ_4_ED_RD_ERR_STAT_REG1 , RULL(0x1401181A), SH_UNT_EQ_4 , +REG64( EQ_4_ED_RD_ERR_STAT_REG1 , RULL(0x14011C1A), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C1A, -REG64( EQ_5_ED_RD_ERR_STAT_REG1 , RULL(0x1501181A), SH_UNT_EQ_5 , +REG64( EQ_5_ED_RD_ERR_STAT_REG1 , RULL(0x15011C1A), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C1A, REG64( EX_0_L3_ED_RD_ERR_STAT_REG1 , RULL(0x1001181A), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_ED_RD_ERR_STAT_REG1 , RULL(0x1501181A), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -9758,7 +9883,7 @@ REG64( EX_ERROR_REG , RULL(0x200F001F SH_ACS_SCOM ); //DUPS: 210F001F, REG64( EX_0_ERROR_REG , RULL(0x200F001F), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F001F, -REG64( EX_1_ERROR_REG , RULL(0x230F001F), SH_UNT_EX_1 , +REG64( EX_1_ERROR_REG , RULL(0x220F001F), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F001F, REG64( EX_2_ERROR_REG , RULL(0x240F001F), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F001F, @@ -9829,7 +9954,7 @@ REG64( EX_5_ERROR_STATUS , RULL(0x2A03000F SH_ACS_SCOM ); //DUPS: 2B03000F, REG64( EX_6_ERROR_STATUS , RULL(0x2C03000F), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D03000F, -REG64( EX_7_ERROR_STATUS , RULL(0x2E03000F), SH_UNT_EX_7 , +REG64( EX_7_ERROR_STATUS , RULL(0x2F03000F), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F03000F, REG64( EX_8_ERROR_STATUS , RULL(0x3003000F), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3103000F, @@ -9890,19 +10015,19 @@ REG64( C_22_ERR_INJ_REG , RULL(0x36010C04 SH_ACS_SCOM_RW ); //DUPS: 36010CBF, REG64( C_23_ERR_INJ_REG , RULL(0x37010C04), SH_UNT_C_23 , SH_ACS_SCOM_RW ); //DUPS: 37010CBF, -REG64( EQ_ERR_INJ_REG , RULL(0x1001080C), SH_UNT_EQ , +REG64( EQ_ERR_INJ_REG , RULL(0x10010C0C), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 1001180D, 10010C0C, 10011C0D, -REG64( EQ_0_ERR_INJ_REG , RULL(0x1001080C), SH_UNT_EQ_0 , +REG64( EQ_0_ERR_INJ_REG , RULL(0x10010C0C), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 1001180D, 10010C0C, 10011C0D, -REG64( EQ_1_ERR_INJ_REG , RULL(0x1101080C), SH_UNT_EQ_1 , +REG64( EQ_1_ERR_INJ_REG , RULL(0x11010C0C), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 1101180D, 11010C0C, 11011C0D, -REG64( EQ_2_ERR_INJ_REG , RULL(0x1201080C), SH_UNT_EQ_2 , +REG64( EQ_2_ERR_INJ_REG , RULL(0x12010C0C), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 1201180D, 12010C0C, 12011C0D, -REG64( EQ_3_ERR_INJ_REG , RULL(0x1301080C), SH_UNT_EQ_3 , +REG64( EQ_3_ERR_INJ_REG , RULL(0x13010C0C), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 1301180D, 13010C0C, 13011C0D, -REG64( EQ_4_ERR_INJ_REG , RULL(0x1401080C), SH_UNT_EQ_4 , +REG64( EQ_4_ERR_INJ_REG , RULL(0x14010C0C), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 1401180D, 14010C0C, 14011C0D, -REG64( EQ_5_ERR_INJ_REG , RULL(0x1501080C), SH_UNT_EQ_5 , +REG64( EQ_5_ERR_INJ_REG , RULL(0x15010C0C), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 1501180D, 15010C0C, 15011C0D, REG64( EX_ERR_INJ_REG , RULL(0x20010CBF), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 21010CBF, @@ -9920,7 +10045,7 @@ REG64( EX_5_ERR_INJ_REG , RULL(0x2A010CBF SH_ACS_SCOM_RW ); //DUPS: 2B010CBF, REG64( EX_6_ERR_INJ_REG , RULL(0x2C010CBF), SH_UNT_EX_6 , SH_ACS_SCOM_RW ); //DUPS: 2D010CBF, -REG64( EX_7_ERR_INJ_REG , RULL(0x2E010CBF), SH_UNT_EX_7 , +REG64( EX_7_ERR_INJ_REG , RULL(0x2F010CBF), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F010CBF, REG64( EX_8_ERR_INJ_REG , RULL(0x30010CBF), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31010CBF, @@ -9936,16 +10061,16 @@ REG64( EX_11_ERR_INJ_REG , RULL(0x36010CBF REG64( EX_10_L2_ERR_INJ_REG , RULL(0x34010C04), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 35010C04, 1501080C, REG64( EX_10_L3_ERR_INJ_REG , RULL(0x1501180D), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); -REG64( EX_11_L2_ERR_INJ_REG , RULL(0x36010C04), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_ERR_INJ_REG , RULL(0x15010C0C), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 37010C04, 15010C0C, REG64( EX_11_L3_ERR_INJ_REG , RULL(0x15011C0D), SH_UNT_EX_11_L3 , SH_ACS_SCOM ); -REG64( EX_1_L2_ERR_INJ_REG , RULL(0x22010C04), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_ERR_INJ_REG , RULL(0x10010C0C), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 23010C04, 10010C0C, REG64( EX_1_L3_ERR_INJ_REG , RULL(0x10011C0D), SH_UNT_EX_1_L3 , SH_ACS_SCOM ); REG64( EX_2_L2_ERR_INJ_REG , RULL(0x24010C04), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 25010C04, 1101080C, REG64( EX_2_L3_ERR_INJ_REG , RULL(0x1101180D), SH_UNT_EX_2_L3 , SH_ACS_SCOM ); -REG64( EX_3_L2_ERR_INJ_REG , RULL(0x26010C04), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_ERR_INJ_REG , RULL(0x11010C0C), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 27010C04, 11010C0C, REG64( EX_3_L3_ERR_INJ_REG , RULL(0x11011C0D), SH_UNT_EX_3_L3 , SH_ACS_SCOM ); REG64( EX_4_L2_ERR_INJ_REG , RULL(0x28010C04), SH_UNT_EX_4_L2 , @@ -9957,32 +10082,32 @@ REG64( EX_5_L3_ERR_INJ_REG , RULL(0x12011C0D REG64( EX_6_L2_ERR_INJ_REG , RULL(0x2C010C04), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010C04, 1301080C, REG64( EX_6_L3_ERR_INJ_REG , RULL(0x1301180D), SH_UNT_EX_6_L3 , SH_ACS_SCOM ); -REG64( EX_7_L2_ERR_INJ_REG , RULL(0x2E010C04), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ERR_INJ_REG , RULL(0x2F010C04), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010C04, 13010C0C, REG64( EX_7_L3_ERR_INJ_REG , RULL(0x13011C0D), SH_UNT_EX_7_L3 , SH_ACS_SCOM ); REG64( EX_8_L2_ERR_INJ_REG , RULL(0x30010C04), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010C04, 1401080C, REG64( EX_8_L3_ERR_INJ_REG , RULL(0x1401180D), SH_UNT_EX_8_L3 , SH_ACS_SCOM ); -REG64( EX_9_L2_ERR_INJ_REG , RULL(0x32010C04), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_ERR_INJ_REG , RULL(0x14010C0C), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 33010C04, 14010C0C, REG64( EX_9_L3_ERR_INJ_REG , RULL(0x14011C0D), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L2_ERR_INJ_REG , RULL(0x20010C04), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 21010C04, 1001080C, REG64( EX_L3_ERR_INJ_REG , RULL(0x1001180D), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_ERR_RPT0 , RULL(0x10010812), SH_UNT_EQ , +REG64( EQ_ERR_RPT0 , RULL(0x10010C12), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C12, -REG64( EQ_0_ERR_RPT0 , RULL(0x10010812), SH_UNT_EQ_0 , +REG64( EQ_0_ERR_RPT0 , RULL(0x10010C12), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C12, -REG64( EQ_1_ERR_RPT0 , RULL(0x11010812), SH_UNT_EQ_1 , +REG64( EQ_1_ERR_RPT0 , RULL(0x11010C12), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C12, -REG64( EQ_2_ERR_RPT0 , RULL(0x12010812), SH_UNT_EQ_2 , +REG64( EQ_2_ERR_RPT0 , RULL(0x12010C12), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C12, -REG64( EQ_3_ERR_RPT0 , RULL(0x13010812), SH_UNT_EQ_3 , +REG64( EQ_3_ERR_RPT0 , RULL(0x13010C12), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C12, -REG64( EQ_4_ERR_RPT0 , RULL(0x14010812), SH_UNT_EQ_4 , +REG64( EQ_4_ERR_RPT0 , RULL(0x14010C12), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C12, -REG64( EQ_5_ERR_RPT0 , RULL(0x15010812), SH_UNT_EQ_5 , +REG64( EQ_5_ERR_RPT0 , RULL(0x15010C12), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C12, REG64( EX_0_L2_ERR_RPT0 , RULL(0x10010812), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_10_L2_ERR_RPT0 , RULL(0x15010812), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); @@ -9998,19 +10123,19 @@ REG64( EX_8_L2_ERR_RPT0 , RULL(0x14010812 REG64( EX_9_L2_ERR_RPT0 , RULL(0x14010C12), SH_UNT_EX_9_L2 , SH_ACS_SCOM ); REG64( EX_L2_ERR_RPT0 , RULL(0x10010812), SH_UNT_EX_L2 , SH_ACS_SCOM ); -REG64( EQ_ERR_RPT1 , RULL(0x10010813), SH_UNT_EQ , +REG64( EQ_ERR_RPT1 , RULL(0x10010C13), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C13, -REG64( EQ_0_ERR_RPT1 , RULL(0x10010813), SH_UNT_EQ_0 , +REG64( EQ_0_ERR_RPT1 , RULL(0x10010C13), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C13, -REG64( EQ_1_ERR_RPT1 , RULL(0x11010813), SH_UNT_EQ_1 , +REG64( EQ_1_ERR_RPT1 , RULL(0x11010C13), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C13, -REG64( EQ_2_ERR_RPT1 , RULL(0x12010813), SH_UNT_EQ_2 , +REG64( EQ_2_ERR_RPT1 , RULL(0x12010C13), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C13, -REG64( EQ_3_ERR_RPT1 , RULL(0x13010813), SH_UNT_EQ_3 , +REG64( EQ_3_ERR_RPT1 , RULL(0x13010C13), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C13, -REG64( EQ_4_ERR_RPT1 , RULL(0x14010813), SH_UNT_EQ_4 , +REG64( EQ_4_ERR_RPT1 , RULL(0x14010C13), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C13, -REG64( EQ_5_ERR_RPT1 , RULL(0x15010813), SH_UNT_EQ_5 , +REG64( EQ_5_ERR_RPT1 , RULL(0x15010C13), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C13, REG64( EX_0_L2_ERR_RPT1 , RULL(0x10010813), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_10_L2_ERR_RPT1 , RULL(0x15010813), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); @@ -10102,7 +10227,7 @@ REG64( EX_5_ERR_STATUS_REG , RULL(0x2A050013 SH_ACS_SCOM_RO ); //DUPS: 2B050013, REG64( EX_6_ERR_STATUS_REG , RULL(0x2C050013), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D050013, -REG64( EX_7_ERR_STATUS_REG , RULL(0x2E050013), SH_UNT_EX_7 , +REG64( EX_7_ERR_STATUS_REG , RULL(0x2F050013), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F050013, REG64( EX_8_ERR_STATUS_REG , RULL(0x30050013), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31050013, @@ -10113,19 +10238,19 @@ REG64( EX_10_ERR_STATUS_REG , RULL(0x34050013 REG64( EX_11_ERR_STATUS_REG , RULL(0x36050013), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); //DUPS: 37050013, -REG64( EQ_FIR_ACTION0_REG , RULL(0x10010806), SH_UNT_EQ , +REG64( EQ_FIR_ACTION0_REG , RULL(0x10010C06), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10011806, 10011006, 10010C06, 10011C06, 10011406, -REG64( EQ_0_FIR_ACTION0_REG , RULL(0x10010806), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_ACTION0_REG , RULL(0x10010C06), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10011806, 10011006, 10010C06, 10011C06, 10011406, -REG64( EQ_1_FIR_ACTION0_REG , RULL(0x11010806), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_ACTION0_REG , RULL(0x11010C06), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11011806, 11011006, 11010C06, 11011C06, 11011406, -REG64( EQ_2_FIR_ACTION0_REG , RULL(0x12010806), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_ACTION0_REG , RULL(0x12010C06), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12011806, 12011006, 12010C06, 12011C06, 12011406, -REG64( EQ_3_FIR_ACTION0_REG , RULL(0x13010806), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_ACTION0_REG , RULL(0x13010C06), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13011806, 13011006, 13010C06, 13011C06, 13011406, -REG64( EQ_4_FIR_ACTION0_REG , RULL(0x14010806), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_ACTION0_REG , RULL(0x14010C06), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14011806, 14011006, 14010C06, 14011C06, 14011406, -REG64( EQ_5_FIR_ACTION0_REG , RULL(0x15010806), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_ACTION0_REG , RULL(0x15010C06), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15011806, 15011006, 15010C06, 15011C06, 15011406, REG64( EX_FIR_ACTION0_REG , RULL(0x10011006), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_FIR_ACTION0_REG , RULL(0x10011006), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -10167,19 +10292,19 @@ REG64( EX_9_L3_FIR_ACTION0_REG , RULL(0x14011C06 REG64( EX_L2_FIR_ACTION0_REG , RULL(0x10010806), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); REG64( EX_L3_FIR_ACTION0_REG , RULL(0x10011806), SH_UNT_EX_L3 , SH_ACS_SCOM_RW ); -REG64( EQ_FIR_ACTION1_REG , RULL(0x10010807), SH_UNT_EQ , +REG64( EQ_FIR_ACTION1_REG , RULL(0x10010C07), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10011807, 10011007, 10010C07, 10011C07, 10011407, -REG64( EQ_0_FIR_ACTION1_REG , RULL(0x10010807), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_ACTION1_REG , RULL(0x10010C07), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10011807, 10011007, 10010C07, 10011C07, 10011407, -REG64( EQ_1_FIR_ACTION1_REG , RULL(0x11010807), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_ACTION1_REG , RULL(0x11010C07), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11011807, 11011007, 11010C07, 11011C07, 11011407, -REG64( EQ_2_FIR_ACTION1_REG , RULL(0x12010807), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_ACTION1_REG , RULL(0x12010C07), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12011807, 12011007, 12010C07, 12011C07, 12011407, -REG64( EQ_3_FIR_ACTION1_REG , RULL(0x13010807), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_ACTION1_REG , RULL(0x13010C07), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13011807, 13011007, 13010C07, 13011C07, 13011407, -REG64( EQ_4_FIR_ACTION1_REG , RULL(0x14010807), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_ACTION1_REG , RULL(0x14010C07), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14011807, 14011007, 14010C07, 14011C07, 14011407, -REG64( EQ_5_FIR_ACTION1_REG , RULL(0x15010807), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_ACTION1_REG , RULL(0x15010C07), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15011807, 15011007, 15010C07, 15011C07, 15011407, REG64( EX_FIR_ACTION1_REG , RULL(0x10011007), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_0_FIR_ACTION1_REG , RULL(0x10011007), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); @@ -10264,7 +10389,7 @@ REG64( EX_5_L2_FIR_ERR_INJ , RULL(0x2A010A4D SH_ACS_SCOM_RW ); //DUPS: 2B010A4D, REG64( EX_6_L2_FIR_ERR_INJ , RULL(0x2C010A4D), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010A4D, -REG64( EX_7_L2_FIR_ERR_INJ , RULL(0x2E010A4D), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_FIR_ERR_INJ , RULL(0x2F010A4D), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A4D, REG64( EX_8_L2_FIR_ERR_INJ , RULL(0x30010A4D), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A4D, @@ -10316,7 +10441,7 @@ REG64( EX_5_L2_FIR_HOLD_OUT , RULL(0x2A010A51 SH_ACS_SCOM_RO ); //DUPS: 2B010A51, REG64( EX_6_L2_FIR_HOLD_OUT , RULL(0x2C010A51), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010A51, -REG64( EX_7_L2_FIR_HOLD_OUT , RULL(0x2E010A51), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_FIR_HOLD_OUT , RULL(0x2F010A51), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010A51, REG64( EX_8_L2_FIR_HOLD_OUT , RULL(0x30010A51), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010A51, @@ -10373,7 +10498,7 @@ REG64( EX_5_FIR_MASK , RULL(0x2A040002 SH_ACS_SCOM ); //DUPS: 2B040002, REG64( EX_6_FIR_MASK , RULL(0x2C040002), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040002, -REG64( EX_7_FIR_MASK , RULL(0x2E040002), SH_UNT_EX_7 , +REG64( EX_7_FIR_MASK , RULL(0x2F040002), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040002, REG64( EX_8_FIR_MASK , RULL(0x30040002), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040002, @@ -10384,47 +10509,47 @@ REG64( EX_10_FIR_MASK , RULL(0x34040002 REG64( EX_11_FIR_MASK , RULL(0x36040002), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37040002, -REG64( EQ_FIR_MASK_REG , RULL(0x10010803), SH_UNT_EQ , +REG64( EQ_FIR_MASK_REG , RULL(0x10010C03), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10011803, 10011003, 10010C03, 10011C03, 10011403, -REG64( EQ_FIR_MASK_REG_AND , RULL(0x10010804), SH_UNT_EQ , +REG64( EQ_FIR_MASK_REG_AND , RULL(0x10010C04), SH_UNT_EQ , SH_ACS_SCOM1_AND ); //DUPS: 10011804, 10011004, 10010C04, 10011C04, 10011404, -REG64( EQ_FIR_MASK_REG_OR , RULL(0x10010805), SH_UNT_EQ , +REG64( EQ_FIR_MASK_REG_OR , RULL(0x10010C05), SH_UNT_EQ , SH_ACS_SCOM2_OR ); //DUPS: 10011805, 10011005, 10010C05, 10011C05, 10011405, -REG64( EQ_0_FIR_MASK_REG , RULL(0x10010803), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_MASK_REG , RULL(0x10010C03), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10011803, 10011003, 10010C03, 10011C03, 10011403, -REG64( EQ_0_FIR_MASK_REG_AND , RULL(0x10010804), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_MASK_REG_AND , RULL(0x10010C04), SH_UNT_EQ_0 , SH_ACS_SCOM1_AND ); //DUPS: 10011804, 10011004, 10010C04, 10011C04, 10011404, -REG64( EQ_0_FIR_MASK_REG_OR , RULL(0x10010805), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_MASK_REG_OR , RULL(0x10010C05), SH_UNT_EQ_0 , SH_ACS_SCOM2_OR ); //DUPS: 10011805, 10011005, 10010C05, 10011C05, 10011405, -REG64( EQ_1_FIR_MASK_REG , RULL(0x11010803), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_MASK_REG , RULL(0x11010C03), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11011803, 11011003, 11010C03, 11011C03, 11011403, -REG64( EQ_1_FIR_MASK_REG_AND , RULL(0x11010804), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_MASK_REG_AND , RULL(0x11010C04), SH_UNT_EQ_1 , SH_ACS_SCOM1_AND ); //DUPS: 11011804, 11011004, 11010C04, 11011C04, 11011404, -REG64( EQ_1_FIR_MASK_REG_OR , RULL(0x11010805), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_MASK_REG_OR , RULL(0x11010C05), SH_UNT_EQ_1 , SH_ACS_SCOM2_OR ); //DUPS: 11011805, 11011005, 11010C05, 11011C05, 11011405, -REG64( EQ_2_FIR_MASK_REG , RULL(0x12010803), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_MASK_REG , RULL(0x12010C03), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12011803, 12011003, 12010C03, 12011C03, 12011403, -REG64( EQ_2_FIR_MASK_REG_AND , RULL(0x12010804), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_MASK_REG_AND , RULL(0x12010C04), SH_UNT_EQ_2 , SH_ACS_SCOM1_AND ); //DUPS: 12011804, 12011004, 12010C04, 12011C04, 12011404, -REG64( EQ_2_FIR_MASK_REG_OR , RULL(0x12010805), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_MASK_REG_OR , RULL(0x12010C05), SH_UNT_EQ_2 , SH_ACS_SCOM2_OR ); //DUPS: 12011805, 12011005, 12010C05, 12011C05, 12011405, -REG64( EQ_3_FIR_MASK_REG , RULL(0x13010803), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_MASK_REG , RULL(0x13010C03), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13011803, 13011003, 13010C03, 13011C03, 13011403, -REG64( EQ_3_FIR_MASK_REG_AND , RULL(0x13010804), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_MASK_REG_AND , RULL(0x13010C04), SH_UNT_EQ_3 , SH_ACS_SCOM1_AND ); //DUPS: 13011804, 13011004, 13010C04, 13011C04, 13011404, -REG64( EQ_3_FIR_MASK_REG_OR , RULL(0x13010805), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_MASK_REG_OR , RULL(0x13010C05), SH_UNT_EQ_3 , SH_ACS_SCOM2_OR ); //DUPS: 13011805, 13011005, 13010C05, 13011C05, 13011405, -REG64( EQ_4_FIR_MASK_REG , RULL(0x14010803), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_MASK_REG , RULL(0x14010C03), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14011803, 14011003, 14010C03, 14011C03, 14011403, -REG64( EQ_4_FIR_MASK_REG_AND , RULL(0x14010804), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_MASK_REG_AND , RULL(0x14010C04), SH_UNT_EQ_4 , SH_ACS_SCOM1_AND ); //DUPS: 14011804, 14011004, 14010C04, 14011C04, 14011404, -REG64( EQ_4_FIR_MASK_REG_OR , RULL(0x14010805), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_MASK_REG_OR , RULL(0x14010C05), SH_UNT_EQ_4 , SH_ACS_SCOM2_OR ); //DUPS: 14011805, 14011005, 14010C05, 14011C05, 14011405, -REG64( EQ_5_FIR_MASK_REG , RULL(0x15010803), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_MASK_REG , RULL(0x15010C03), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15011803, 15011003, 15010C03, 15011C03, 15011403, -REG64( EQ_5_FIR_MASK_REG_AND , RULL(0x15010804), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_MASK_REG_AND , RULL(0x15010C04), SH_UNT_EQ_5 , SH_ACS_SCOM1_AND ); //DUPS: 15011804, 15011004, 15010C04, 15011C04, 15011404, -REG64( EQ_5_FIR_MASK_REG_OR , RULL(0x15010805), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_MASK_REG_OR , RULL(0x15010C05), SH_UNT_EQ_5 , SH_ACS_SCOM2_OR ); //DUPS: 15011805, 15011005, 15010C05, 15011C05, 15011405, REG64( EX_FIR_MASK_REG , RULL(0x10011003), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_FIR_MASK_REG_AND , RULL(0x10011004), SH_UNT_EX , SH_ACS_SCOM1_AND ); @@ -10544,47 +10669,47 @@ REG64( EX_L3_FIR_MASK_REG , RULL(0x10011803 REG64( EX_L3_FIR_MASK_REG_AND , RULL(0x10011804), SH_UNT_EX_L3 , SH_ACS_SCOM1_AND ); REG64( EX_L3_FIR_MASK_REG_OR , RULL(0x10011805), SH_UNT_EX_L3 , SH_ACS_SCOM2_OR ); -REG64( EQ_FIR_REG , RULL(0x10010800), SH_UNT_EQ , +REG64( EQ_FIR_REG , RULL(0x10010C00), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10011800, 10011000, 10010C00, 10011C00, 10011400, -REG64( EQ_FIR_REG_AND , RULL(0x10010801), SH_UNT_EQ , +REG64( EQ_FIR_REG_AND , RULL(0x10010C01), SH_UNT_EQ , SH_ACS_SCOM1_AND ); //DUPS: 10011801, 10011001, 10010C01, 10011C01, 10011401, -REG64( EQ_FIR_REG_OR , RULL(0x10010802), SH_UNT_EQ , +REG64( EQ_FIR_REG_OR , RULL(0x10010C02), SH_UNT_EQ , SH_ACS_SCOM2_OR ); //DUPS: 10011802, 10011002, 10010C02, 10011C02, 10011402, -REG64( EQ_0_FIR_REG , RULL(0x10010800), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_REG , RULL(0x10010C00), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10011800, 10011000, 10010C00, 10011C00, 10011400, -REG64( EQ_0_FIR_REG_AND , RULL(0x10010801), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_REG_AND , RULL(0x10010C01), SH_UNT_EQ_0 , SH_ACS_SCOM1_AND ); //DUPS: 10011801, 10011001, 10010C01, 10011C01, 10011401, -REG64( EQ_0_FIR_REG_OR , RULL(0x10010802), SH_UNT_EQ_0 , +REG64( EQ_0_FIR_REG_OR , RULL(0x10010C02), SH_UNT_EQ_0 , SH_ACS_SCOM2_OR ); //DUPS: 10011802, 10011002, 10010C02, 10011C02, 10011402, -REG64( EQ_1_FIR_REG , RULL(0x11010800), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_REG , RULL(0x11010C00), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11011800, 11011000, 11010C00, 11011C00, 11011400, -REG64( EQ_1_FIR_REG_AND , RULL(0x11010801), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_REG_AND , RULL(0x11010C01), SH_UNT_EQ_1 , SH_ACS_SCOM1_AND ); //DUPS: 11011801, 11011001, 11010C01, 11011C01, 11011401, -REG64( EQ_1_FIR_REG_OR , RULL(0x11010802), SH_UNT_EQ_1 , +REG64( EQ_1_FIR_REG_OR , RULL(0x11010C02), SH_UNT_EQ_1 , SH_ACS_SCOM2_OR ); //DUPS: 11011802, 11011002, 11010C02, 11011C02, 11011402, -REG64( EQ_2_FIR_REG , RULL(0x12010800), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_REG , RULL(0x12010C00), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12011800, 12011000, 12010C00, 12011C00, 12011400, -REG64( EQ_2_FIR_REG_AND , RULL(0x12010801), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_REG_AND , RULL(0x12010C01), SH_UNT_EQ_2 , SH_ACS_SCOM1_AND ); //DUPS: 12011801, 12011001, 12010C01, 12011C01, 12011401, -REG64( EQ_2_FIR_REG_OR , RULL(0x12010802), SH_UNT_EQ_2 , +REG64( EQ_2_FIR_REG_OR , RULL(0x12010C02), SH_UNT_EQ_2 , SH_ACS_SCOM2_OR ); //DUPS: 12011802, 12011002, 12010C02, 12011C02, 12011402, -REG64( EQ_3_FIR_REG , RULL(0x13010800), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_REG , RULL(0x13010C00), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13011800, 13011000, 13010C00, 13011C00, 13011400, -REG64( EQ_3_FIR_REG_AND , RULL(0x13010801), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_REG_AND , RULL(0x13010C01), SH_UNT_EQ_3 , SH_ACS_SCOM1_AND ); //DUPS: 13011801, 13011001, 13010C01, 13011C01, 13011401, -REG64( EQ_3_FIR_REG_OR , RULL(0x13010802), SH_UNT_EQ_3 , +REG64( EQ_3_FIR_REG_OR , RULL(0x13010C02), SH_UNT_EQ_3 , SH_ACS_SCOM2_OR ); //DUPS: 13011802, 13011002, 13010C02, 13011C02, 13011402, -REG64( EQ_4_FIR_REG , RULL(0x14010800), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_REG , RULL(0x14010C00), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14011800, 14011000, 14010C00, 14011C00, 14011400, -REG64( EQ_4_FIR_REG_AND , RULL(0x14010801), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_REG_AND , RULL(0x14010C01), SH_UNT_EQ_4 , SH_ACS_SCOM1_AND ); //DUPS: 14011801, 14011001, 14010C01, 14011C01, 14011401, -REG64( EQ_4_FIR_REG_OR , RULL(0x14010802), SH_UNT_EQ_4 , +REG64( EQ_4_FIR_REG_OR , RULL(0x14010C02), SH_UNT_EQ_4 , SH_ACS_SCOM2_OR ); //DUPS: 14011802, 14011002, 14010C02, 14011C02, 14011402, -REG64( EQ_5_FIR_REG , RULL(0x15010800), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_REG , RULL(0x15010C00), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15011800, 15011000, 15010C00, 15011C00, 15011400, -REG64( EQ_5_FIR_REG_AND , RULL(0x15010801), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_REG_AND , RULL(0x15010C01), SH_UNT_EQ_5 , SH_ACS_SCOM1_AND ); //DUPS: 15011801, 15011001, 15010C01, 15011C01, 15011401, -REG64( EQ_5_FIR_REG_OR , RULL(0x15010802), SH_UNT_EQ_5 , +REG64( EQ_5_FIR_REG_OR , RULL(0x15010C02), SH_UNT_EQ_5 , SH_ACS_SCOM2_OR ); //DUPS: 15011802, 15011002, 15010C02, 15011C02, 15011402, REG64( EX_FIR_REG , RULL(0x10011000), SH_UNT_EX , SH_ACS_SCOM_RW ); REG64( EX_FIR_REG_AND , RULL(0x10011001), SH_UNT_EX , SH_ACS_SCOM1_AND ); @@ -10752,7 +10877,7 @@ REG64( EX_5_GXSTOP0_MASK_REG , RULL(0x2A040014 SH_ACS_SCOM ); //DUPS: 2B040014, REG64( EX_6_GXSTOP0_MASK_REG , RULL(0x2C040014), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040014, -REG64( EX_7_GXSTOP0_MASK_REG , RULL(0x2E040014), SH_UNT_EX_7 , +REG64( EX_7_GXSTOP0_MASK_REG , RULL(0x2F040014), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040014, REG64( EX_8_GXSTOP0_MASK_REG , RULL(0x30040014), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040014, @@ -10811,7 +10936,7 @@ REG64( EX_5_GXSTOP1_MASK_REG , RULL(0x2A040015 SH_ACS_SCOM ); //DUPS: 2B040015, REG64( EX_6_GXSTOP1_MASK_REG , RULL(0x2C040015), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040015, -REG64( EX_7_GXSTOP1_MASK_REG , RULL(0x2E040015), SH_UNT_EX_7 , +REG64( EX_7_GXSTOP1_MASK_REG , RULL(0x2F040015), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040015, REG64( EX_8_GXSTOP1_MASK_REG , RULL(0x30040015), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040015, @@ -10870,7 +10995,7 @@ REG64( EX_5_GXSTOP2_MASK_REG , RULL(0x2A040016 SH_ACS_SCOM ); //DUPS: 2B040016, REG64( EX_6_GXSTOP2_MASK_REG , RULL(0x2C040016), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040016, -REG64( EX_7_GXSTOP2_MASK_REG , RULL(0x2E040016), SH_UNT_EX_7 , +REG64( EX_7_GXSTOP2_MASK_REG , RULL(0x2F040016), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040016, REG64( EX_8_GXSTOP2_MASK_REG , RULL(0x30040016), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040016, @@ -10929,7 +11054,7 @@ REG64( EX_5_GXSTOP_TRIG_REG , RULL(0x2A040013 SH_ACS_SCOM ); //DUPS: 2B040013, REG64( EX_6_GXSTOP_TRIG_REG , RULL(0x2C040013), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040013, -REG64( EX_7_GXSTOP_TRIG_REG , RULL(0x2E040013), SH_UNT_EX_7 , +REG64( EX_7_GXSTOP_TRIG_REG , RULL(0x2F040013), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040013, REG64( EX_8_GXSTOP_TRIG_REG , RULL(0x30040013), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040013, @@ -10983,7 +11108,7 @@ REG64( EX_5_L2_HANG_CONTROL , RULL(0x2A010A00 SH_ACS_SCOM_RW ); //DUPS: 2B010A00, REG64( EX_6_L2_HANG_CONTROL , RULL(0x2C010A00), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010A00, -REG64( EX_7_L2_HANG_CONTROL , RULL(0x2E010A00), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_HANG_CONTROL , RULL(0x2F010A00), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A00, REG64( EX_8_L2_HANG_CONTROL , RULL(0x30010A00), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A00, @@ -11028,7 +11153,7 @@ REG64( EX_HANG_PULSE_0_REG , RULL(0x200F0020 SH_ACS_SCOM_RW ); //DUPS: 210F0020, REG64( EX_0_HANG_PULSE_0_REG , RULL(0x200F0020), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0020, -REG64( EX_1_HANG_PULSE_0_REG , RULL(0x230F0020), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_0_REG , RULL(0x220F0020), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0020, REG64( EX_2_HANG_PULSE_0_REG , RULL(0x240F0020), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0020, @@ -11087,7 +11212,7 @@ REG64( EX_HANG_PULSE_1_REG , RULL(0x200F0021 SH_ACS_SCOM_RW ); //DUPS: 210F0021, REG64( EX_0_HANG_PULSE_1_REG , RULL(0x200F0021), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0021, -REG64( EX_1_HANG_PULSE_1_REG , RULL(0x230F0021), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_1_REG , RULL(0x220F0021), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0021, REG64( EX_2_HANG_PULSE_1_REG , RULL(0x240F0021), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0021, @@ -11146,7 +11271,7 @@ REG64( EX_HANG_PULSE_2_REG , RULL(0x200F0022 SH_ACS_SCOM_RW ); //DUPS: 210F0022, REG64( EX_0_HANG_PULSE_2_REG , RULL(0x200F0022), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0022, -REG64( EX_1_HANG_PULSE_2_REG , RULL(0x230F0022), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_2_REG , RULL(0x220F0022), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0022, REG64( EX_2_HANG_PULSE_2_REG , RULL(0x240F0022), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0022, @@ -11205,7 +11330,7 @@ REG64( EX_HANG_PULSE_3_REG , RULL(0x200F0023 SH_ACS_SCOM_RW ); //DUPS: 210F0023, REG64( EX_0_HANG_PULSE_3_REG , RULL(0x200F0023), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0023, -REG64( EX_1_HANG_PULSE_3_REG , RULL(0x230F0023), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_3_REG , RULL(0x220F0023), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0023, REG64( EX_2_HANG_PULSE_3_REG , RULL(0x240F0023), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0023, @@ -11264,7 +11389,7 @@ REG64( EX_HANG_PULSE_4_REG , RULL(0x200F0024 SH_ACS_SCOM_RW ); //DUPS: 210F0024, REG64( EX_0_HANG_PULSE_4_REG , RULL(0x200F0024), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0024, -REG64( EX_1_HANG_PULSE_4_REG , RULL(0x230F0024), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_4_REG , RULL(0x220F0024), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0024, REG64( EX_2_HANG_PULSE_4_REG , RULL(0x240F0024), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0024, @@ -11323,7 +11448,7 @@ REG64( EX_HANG_PULSE_5_REG , RULL(0x200F0025 SH_ACS_SCOM_RW ); //DUPS: 210F0025, REG64( EX_0_HANG_PULSE_5_REG , RULL(0x200F0025), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0025, -REG64( EX_1_HANG_PULSE_5_REG , RULL(0x230F0025), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_5_REG , RULL(0x220F0025), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0025, REG64( EX_2_HANG_PULSE_5_REG , RULL(0x240F0025), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0025, @@ -11382,7 +11507,7 @@ REG64( EX_HANG_PULSE_6_REG , RULL(0x200F0026 SH_ACS_SCOM_RW ); //DUPS: 210F0026, REG64( EX_0_HANG_PULSE_6_REG , RULL(0x200F0026), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0026, -REG64( EX_1_HANG_PULSE_6_REG , RULL(0x230F0026), SH_UNT_EX_1 , +REG64( EX_1_HANG_PULSE_6_REG , RULL(0x220F0026), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0026, REG64( EX_2_HANG_PULSE_6_REG , RULL(0x240F0026), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0026, @@ -11441,7 +11566,7 @@ REG64( EX_HEARTBEAT_REG , RULL(0x200F0018 SH_ACS_SCOM ); //DUPS: 210F0018, REG64( EX_0_HEARTBEAT_REG , RULL(0x200F0018), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0018, -REG64( EX_1_HEARTBEAT_REG , RULL(0x230F0018), SH_UNT_EX_1 , +REG64( EX_1_HEARTBEAT_REG , RULL(0x220F0018), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0018, REG64( EX_2_HEARTBEAT_REG , RULL(0x240F0018), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0018, @@ -11464,57 +11589,57 @@ REG64( EX_10_HEARTBEAT_REG , RULL(0x340F0018 REG64( EX_11_HEARTBEAT_REG , RULL(0x360F0018), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 370F0018, -REG64( C_HID , RULL(0x20010A01), SH_UNT_C , SH_ACS_SCOM ); -REG64( C_0_HID , RULL(0x20010A01), SH_UNT_C_0 , SH_ACS_SCOM ); -REG64( C_1_HID , RULL(0x21010A01), SH_UNT_C_1 , SH_ACS_SCOM ); -REG64( C_2_HID , RULL(0x22010A01), SH_UNT_C_2 , SH_ACS_SCOM ); -REG64( C_3_HID , RULL(0x23010A01), SH_UNT_C_3 , SH_ACS_SCOM ); -REG64( C_4_HID , RULL(0x24010A01), SH_UNT_C_4 , SH_ACS_SCOM ); -REG64( C_5_HID , RULL(0x25010A01), SH_UNT_C_5 , SH_ACS_SCOM ); -REG64( C_6_HID , RULL(0x26010A01), SH_UNT_C_6 , SH_ACS_SCOM ); -REG64( C_7_HID , RULL(0x27010A01), SH_UNT_C_7 , SH_ACS_SCOM ); -REG64( C_8_HID , RULL(0x28010A01), SH_UNT_C_8 , SH_ACS_SCOM ); -REG64( C_9_HID , RULL(0x29010A01), SH_UNT_C_9 , SH_ACS_SCOM ); -REG64( C_10_HID , RULL(0x2A010A01), SH_UNT_C_10 , SH_ACS_SCOM ); -REG64( C_11_HID , RULL(0x2B010A01), SH_UNT_C_11 , SH_ACS_SCOM ); -REG64( C_12_HID , RULL(0x2C010A01), SH_UNT_C_12 , SH_ACS_SCOM ); -REG64( C_13_HID , RULL(0x2D010A01), SH_UNT_C_13 , SH_ACS_SCOM ); -REG64( C_14_HID , RULL(0x2E010A01), SH_UNT_C_14 , SH_ACS_SCOM ); -REG64( C_15_HID , RULL(0x2F010A01), SH_UNT_C_15 , SH_ACS_SCOM ); -REG64( C_16_HID , RULL(0x30010A01), SH_UNT_C_16 , SH_ACS_SCOM ); -REG64( C_17_HID , RULL(0x31010A01), SH_UNT_C_17 , SH_ACS_SCOM ); -REG64( C_18_HID , RULL(0x32010A01), SH_UNT_C_18 , SH_ACS_SCOM ); -REG64( C_19_HID , RULL(0x33010A01), SH_UNT_C_19 , SH_ACS_SCOM ); -REG64( C_20_HID , RULL(0x34010A01), SH_UNT_C_20 , SH_ACS_SCOM ); -REG64( C_21_HID , RULL(0x35010A01), SH_UNT_C_21 , SH_ACS_SCOM ); -REG64( C_22_HID , RULL(0x36010A01), SH_UNT_C_22 , SH_ACS_SCOM ); -REG64( C_23_HID , RULL(0x37010A01), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( C_HID , RULL(0x20010A01), SH_UNT_C , SH_ACS_SCOM_RW ); +REG64( C_0_HID , RULL(0x20010A01), SH_UNT_C_0 , SH_ACS_SCOM_RW ); +REG64( C_1_HID , RULL(0x21010A01), SH_UNT_C_1 , SH_ACS_SCOM_RW ); +REG64( C_2_HID , RULL(0x22010A01), SH_UNT_C_2 , SH_ACS_SCOM_RW ); +REG64( C_3_HID , RULL(0x23010A01), SH_UNT_C_3 , SH_ACS_SCOM_RW ); +REG64( C_4_HID , RULL(0x24010A01), SH_UNT_C_4 , SH_ACS_SCOM_RW ); +REG64( C_5_HID , RULL(0x25010A01), SH_UNT_C_5 , SH_ACS_SCOM_RW ); +REG64( C_6_HID , RULL(0x26010A01), SH_UNT_C_6 , SH_ACS_SCOM_RW ); +REG64( C_7_HID , RULL(0x27010A01), SH_UNT_C_7 , SH_ACS_SCOM_RW ); +REG64( C_8_HID , RULL(0x28010A01), SH_UNT_C_8 , SH_ACS_SCOM_RW ); +REG64( C_9_HID , RULL(0x29010A01), SH_UNT_C_9 , SH_ACS_SCOM_RW ); +REG64( C_10_HID , RULL(0x2A010A01), SH_UNT_C_10 , SH_ACS_SCOM_RW ); +REG64( C_11_HID , RULL(0x2B010A01), SH_UNT_C_11 , SH_ACS_SCOM_RW ); +REG64( C_12_HID , RULL(0x2C010A01), SH_UNT_C_12 , SH_ACS_SCOM_RW ); +REG64( C_13_HID , RULL(0x2D010A01), SH_UNT_C_13 , SH_ACS_SCOM_RW ); +REG64( C_14_HID , RULL(0x2E010A01), SH_UNT_C_14 , SH_ACS_SCOM_RW ); +REG64( C_15_HID , RULL(0x2F010A01), SH_UNT_C_15 , SH_ACS_SCOM_RW ); +REG64( C_16_HID , RULL(0x30010A01), SH_UNT_C_16 , SH_ACS_SCOM_RW ); +REG64( C_17_HID , RULL(0x31010A01), SH_UNT_C_17 , SH_ACS_SCOM_RW ); +REG64( C_18_HID , RULL(0x32010A01), SH_UNT_C_18 , SH_ACS_SCOM_RW ); +REG64( C_19_HID , RULL(0x33010A01), SH_UNT_C_19 , SH_ACS_SCOM_RW ); +REG64( C_20_HID , RULL(0x34010A01), SH_UNT_C_20 , SH_ACS_SCOM_RW ); +REG64( C_21_HID , RULL(0x35010A01), SH_UNT_C_21 , SH_ACS_SCOM_RW ); +REG64( C_22_HID , RULL(0x36010A01), SH_UNT_C_22 , SH_ACS_SCOM_RW ); +REG64( C_23_HID , RULL(0x37010A01), SH_UNT_C_23 , SH_ACS_SCOM_RW ); REG64( EX_0_L2_HID , RULL(0x20010A01), SH_UNT_EX_0_L2 , - SH_ACS_SCOM ); //DUPS: 21010A01, + SH_ACS_SCOM_RW ); //DUPS: 21010A01, REG64( EX_10_L2_HID , RULL(0x34010A01), SH_UNT_EX_10_L2 , - SH_ACS_SCOM ); //DUPS: 35010A01, + SH_ACS_SCOM_RW ); //DUPS: 35010A01, REG64( EX_11_L2_HID , RULL(0x36010A01), SH_UNT_EX_11_L2 , - SH_ACS_SCOM ); //DUPS: 37010A01, + SH_ACS_SCOM_RW ); //DUPS: 37010A01, REG64( EX_1_L2_HID , RULL(0x22010A01), SH_UNT_EX_1_L2 , - SH_ACS_SCOM ); //DUPS: 23010A01, + SH_ACS_SCOM_RW ); //DUPS: 23010A01, REG64( EX_2_L2_HID , RULL(0x24010A01), SH_UNT_EX_2_L2 , - SH_ACS_SCOM ); //DUPS: 25010A01, + SH_ACS_SCOM_RW ); //DUPS: 25010A01, REG64( EX_3_L2_HID , RULL(0x26010A01), SH_UNT_EX_3_L2 , - SH_ACS_SCOM ); //DUPS: 27010A01, + SH_ACS_SCOM_RW ); //DUPS: 27010A01, REG64( EX_4_L2_HID , RULL(0x28010A01), SH_UNT_EX_4_L2 , - SH_ACS_SCOM ); //DUPS: 29010A01, + SH_ACS_SCOM_RW ); //DUPS: 29010A01, REG64( EX_5_L2_HID , RULL(0x2A010A01), SH_UNT_EX_5_L2 , - SH_ACS_SCOM ); //DUPS: 2B010A01, + SH_ACS_SCOM_RW ); //DUPS: 2B010A01, REG64( EX_6_L2_HID , RULL(0x2C010A01), SH_UNT_EX_6_L2 , - SH_ACS_SCOM ); //DUPS: 2D010A01, -REG64( EX_7_L2_HID , RULL(0x2E010A01), SH_UNT_EX_7_L2 , - SH_ACS_SCOM ); //DUPS: 2F010A01, + SH_ACS_SCOM_RW ); //DUPS: 2D010A01, +REG64( EX_7_L2_HID , RULL(0x2F010A01), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2F010A01, REG64( EX_8_L2_HID , RULL(0x30010A01), SH_UNT_EX_8_L2 , - SH_ACS_SCOM ); //DUPS: 31010A01, + SH_ACS_SCOM_RW ); //DUPS: 31010A01, REG64( EX_9_L2_HID , RULL(0x32010A01), SH_UNT_EX_9_L2 , - SH_ACS_SCOM ); //DUPS: 33010A01, + SH_ACS_SCOM_RW ); //DUPS: 33010A01, REG64( EX_L2_HID , RULL(0x20010A01), SH_UNT_EX_L2 , - SH_ACS_SCOM ); //DUPS: 21010A01, + SH_ACS_SCOM_RW ); //DUPS: 21010A01, REG64( C_HMEER , RULL(0x20010A96), SH_UNT_C , SH_ACS_SCOM_RW ); REG64( C_0_HMEER , RULL(0x20010A96), SH_UNT_C_0 , SH_ACS_SCOM_RW ); @@ -11541,19 +11666,19 @@ REG64( C_20_HMEER , RULL(0x34010A96 REG64( C_21_HMEER , RULL(0x35010A96), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_HMEER , RULL(0x36010A96), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_HMEER , RULL(0x37010A96), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_HMEER , RULL(0x21010A96), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_HMEER , RULL(0x20010A96), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A96, -REG64( EX_10_L2_HMEER , RULL(0x35010A96), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_HMEER , RULL(0x34010A96), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010A96, -REG64( EX_11_L2_HMEER , RULL(0x37010A96), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_HMEER , RULL(0x36010A96), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010A96, -REG64( EX_1_L2_HMEER , RULL(0x23010A96), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_HMEER , RULL(0x22010A96), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010A96, -REG64( EX_2_L2_HMEER , RULL(0x25010A96), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_HMEER , RULL(0x24010A96), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010A96, -REG64( EX_3_L2_HMEER , RULL(0x27010A96), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_HMEER , RULL(0x26010A96), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010A96, -REG64( EX_4_L2_HMEER , RULL(0x29010A96), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_HMEER , RULL(0x28010A96), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010A96, REG64( EX_5_L2_HMEER , RULL(0x2B010A96), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010A96, @@ -11561,11 +11686,11 @@ REG64( EX_6_L2_HMEER , RULL(0x2D010A96 SH_ACS_SCOM_RW ); //DUPS: 2C010A96, REG64( EX_7_L2_HMEER , RULL(0x2F010A96), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010A96, -REG64( EX_8_L2_HMEER , RULL(0x31010A96), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_HMEER , RULL(0x30010A96), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010A96, -REG64( EX_9_L2_HMEER , RULL(0x33010A96), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_HMEER , RULL(0x32010A96), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010A96, -REG64( EX_L2_HMEER , RULL(0x21010A96), SH_UNT_EX_L2 , +REG64( EX_L2_HMEER , RULL(0x20010A96), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A96, REG64( C_HOSTATTN , RULL(0x20040009), SH_UNT_C , SH_ACS_SCOM_RO ); @@ -11616,7 +11741,7 @@ REG64( EX_5_HOSTATTN , RULL(0x2A040009 SH_ACS_SCOM_RO ); //DUPS: 2B040009, REG64( EX_6_HOSTATTN , RULL(0x2C040009), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D040009, -REG64( EX_7_HOSTATTN , RULL(0x2E040009), SH_UNT_EX_7 , +REG64( EX_7_HOSTATTN , RULL(0x2F040009), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F040009, REG64( EX_8_HOSTATTN , RULL(0x30040009), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31040009, @@ -11675,7 +11800,7 @@ REG64( EX_5_HOSTATTN_MASK , RULL(0x2A04001A SH_ACS_SCOM ); //DUPS: 2B04001A, REG64( EX_6_HOSTATTN_MASK , RULL(0x2C04001A), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D04001A, -REG64( EX_7_HOSTATTN_MASK , RULL(0x2E04001A), SH_UNT_EX_7 , +REG64( EX_7_HOSTATTN_MASK , RULL(0x2F04001A), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F04001A, REG64( EX_8_HOSTATTN_MASK , RULL(0x3004001A), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3104001A, @@ -11686,19 +11811,72 @@ REG64( EX_10_HOSTATTN_MASK , RULL(0x3404001A REG64( EX_11_HOSTATTN_MASK , RULL(0x3604001A), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 3704001A, -REG64( EQ_HTM_CTRL , RULL(0x10012605), SH_UNT_EQ , +REG64( EQ_HTM_CSEL , RULL(0x10012207), SH_UNT_EQ , + SH_ACS_SCOM_R0 ); //DUPS: 10012707, 10012207, 10012307, +REG64( EQ_0_HTM_CSEL , RULL(0x10012207), SH_UNT_EQ_0 , + SH_ACS_SCOM_R0 ); //DUPS: 10012707, 10012207, 10012307, +REG64( EQ_1_HTM_CSEL , RULL(0x11012207), SH_UNT_EQ_1 , + SH_ACS_SCOM_R0 ); //DUPS: 11012707, 11012207, 11012307, +REG64( EQ_2_HTM_CSEL , RULL(0x12012207), SH_UNT_EQ_2 , + SH_ACS_SCOM_R0 ); //DUPS: 12012707, 12012207, 12012307, +REG64( EQ_3_HTM_CSEL , RULL(0x13012207), SH_UNT_EQ_3 , + SH_ACS_SCOM_R0 ); //DUPS: 13012707, 13012207, 13012307, +REG64( EQ_4_HTM_CSEL , RULL(0x14012207), SH_UNT_EQ_4 , + SH_ACS_SCOM_R0 ); //DUPS: 14012707, 14012207, 14012307, +REG64( EQ_5_HTM_CSEL , RULL(0x15012207), SH_UNT_EQ_5 , + SH_ACS_SCOM_R0 ); //DUPS: 15012707, 15012207, 15012307, +REG64( EX_HTM_CSEL , RULL(0x10012207), SH_UNT_EX , + SH_ACS_SCOM_R0 ); //DUPS: 10012307, +REG64( EX_0_HTM_CSEL , RULL(0x10012207), SH_UNT_EX_0 , + SH_ACS_SCOM_R0 ); //DUPS: 10012307, +REG64( EX_2_HTM_CSEL , RULL(0x11012207), SH_UNT_EX_2 , + SH_ACS_SCOM_R0 ); //DUPS: 11012307, +REG64( EX_4_HTM_CSEL , RULL(0x12012207), SH_UNT_EX_4 , + SH_ACS_SCOM_R0 ); //DUPS: 12012307, +REG64( EX_6_HTM_CSEL , RULL(0x13012207), SH_UNT_EX_6 , + SH_ACS_SCOM_R0 ); //DUPS: 13012307, +REG64( EX_8_HTM_CSEL , RULL(0x14012207), SH_UNT_EX_8 , + SH_ACS_SCOM_R0 ); //DUPS: 14012307, +REG64( EX_10_HTM_CSEL , RULL(0x15012207), SH_UNT_EX_10 , + SH_ACS_SCOM_R0 ); //DUPS: 15012307, +REG64( EX_11_CHTMLBS0_HTM_CSEL , RULL(0x15012607), SH_UNT_EX_11_CHTMLBS0, + SH_ACS_SCOM_R0 ); +REG64( EX_11_CHTMLBS1_HTM_CSEL , RULL(0x15012707), SH_UNT_EX_11_CHTMLBS1, + SH_ACS_SCOM_R0 ); +REG64( EX_1_CHTMLBS0_HTM_CSEL , RULL(0x10012607), SH_UNT_EX_1_CHTMLBS0, + SH_ACS_SCOM_R0 ); +REG64( EX_1_CHTMLBS1_HTM_CSEL , RULL(0x10012707), SH_UNT_EX_1_CHTMLBS1, + SH_ACS_SCOM_R0 ); +REG64( EX_3_CHTMLBS0_HTM_CSEL , RULL(0x11012607), SH_UNT_EX_3_CHTMLBS0, + SH_ACS_SCOM_R0 ); +REG64( EX_3_CHTMLBS1_HTM_CSEL , RULL(0x11012707), SH_UNT_EX_3_CHTMLBS1, + SH_ACS_SCOM_R0 ); +REG64( EX_5_CHTMLBS0_HTM_CSEL , RULL(0x12012607), SH_UNT_EX_5_CHTMLBS0, + SH_ACS_SCOM_R0 ); +REG64( EX_5_CHTMLBS1_HTM_CSEL , RULL(0x12012707), SH_UNT_EX_5_CHTMLBS1, + SH_ACS_SCOM_R0 ); +REG64( EX_7_CHTMLBS0_HTM_CSEL , RULL(0x13012607), SH_UNT_EX_7_CHTMLBS0, + SH_ACS_SCOM_R0 ); +REG64( EX_7_CHTMLBS1_HTM_CSEL , RULL(0x13012707), SH_UNT_EX_7_CHTMLBS1, + SH_ACS_SCOM_R0 ); +REG64( EX_9_CHTMLBS0_HTM_CSEL , RULL(0x14012607), SH_UNT_EX_9_CHTMLBS0, + SH_ACS_SCOM_R0 ); +REG64( EX_9_CHTMLBS1_HTM_CSEL , RULL(0x14012707), SH_UNT_EX_9_CHTMLBS1, + SH_ACS_SCOM_R0 ); + +REG64( EQ_HTM_CTRL , RULL(0x10012205), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012705, 10012205, 10012305, -REG64( EQ_0_HTM_CTRL , RULL(0x10012605), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_CTRL , RULL(0x10012205), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012705, 10012205, 10012305, -REG64( EQ_1_HTM_CTRL , RULL(0x11012605), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_CTRL , RULL(0x11012205), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012705, 11012205, 11012305, -REG64( EQ_2_HTM_CTRL , RULL(0x12012605), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_CTRL , RULL(0x12012205), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012705, 12012205, 12012305, -REG64( EQ_3_HTM_CTRL , RULL(0x13012605), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_CTRL , RULL(0x13012205), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012705, 13012205, 13012305, -REG64( EQ_4_HTM_CTRL , RULL(0x14012605), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_CTRL , RULL(0x14012205), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012705, 14012205, 14012305, -REG64( EQ_5_HTM_CTRL , RULL(0x15012605), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_CTRL , RULL(0x15012205), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012705, 15012205, 15012305, REG64( EX_HTM_CTRL , RULL(0x10012205), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 10012305, @@ -11739,19 +11917,19 @@ REG64( EX_9_CHTMLBS0_HTM_CTRL , RULL(0x14012605 REG64( EX_9_CHTMLBS1_HTM_CTRL , RULL(0x14012705), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RW ); -REG64( EQ_HTM_IMA_PDBAR , RULL(0x1001260B), SH_UNT_EQ , +REG64( EQ_HTM_IMA_PDBAR , RULL(0x1001220B), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 1001270B, 1001220B, 1001230B, -REG64( EQ_0_HTM_IMA_PDBAR , RULL(0x1001260B), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_IMA_PDBAR , RULL(0x1001220B), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 1001270B, 1001220B, 1001230B, -REG64( EQ_1_HTM_IMA_PDBAR , RULL(0x1101260B), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_IMA_PDBAR , RULL(0x1101220B), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 1101270B, 1101220B, 1101230B, -REG64( EQ_2_HTM_IMA_PDBAR , RULL(0x1201260B), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_IMA_PDBAR , RULL(0x1201220B), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 1201270B, 1201220B, 1201230B, -REG64( EQ_3_HTM_IMA_PDBAR , RULL(0x1301260B), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_IMA_PDBAR , RULL(0x1301220B), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 1301270B, 1301220B, 1301230B, -REG64( EQ_4_HTM_IMA_PDBAR , RULL(0x1401260B), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_IMA_PDBAR , RULL(0x1401220B), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 1401270B, 1401220B, 1401230B, -REG64( EQ_5_HTM_IMA_PDBAR , RULL(0x1501260B), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_IMA_PDBAR , RULL(0x1501220B), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 1501270B, 1501220B, 1501230B, REG64( EX_HTM_IMA_PDBAR , RULL(0x1001220B), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 1001230B, @@ -11792,19 +11970,19 @@ REG64( EX_9_CHTMLBS0_HTM_IMA_PDBAR , RULL(0x1401260B REG64( EX_9_CHTMLBS1_HTM_IMA_PDBAR , RULL(0x1401270B), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RW ); -REG64( EQ_HTM_IMA_STATUS , RULL(0x1001260A), SH_UNT_EQ , +REG64( EQ_HTM_IMA_STATUS , RULL(0x1001220A), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 1001270A, 1001220A, 1001230A, -REG64( EQ_0_HTM_IMA_STATUS , RULL(0x1001260A), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_IMA_STATUS , RULL(0x1001220A), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 1001270A, 1001220A, 1001230A, -REG64( EQ_1_HTM_IMA_STATUS , RULL(0x1101260A), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_IMA_STATUS , RULL(0x1101220A), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 1101270A, 1101220A, 1101230A, -REG64( EQ_2_HTM_IMA_STATUS , RULL(0x1201260A), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_IMA_STATUS , RULL(0x1201220A), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 1201270A, 1201220A, 1201230A, -REG64( EQ_3_HTM_IMA_STATUS , RULL(0x1301260A), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_IMA_STATUS , RULL(0x1301220A), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 1301270A, 1301220A, 1301230A, -REG64( EQ_4_HTM_IMA_STATUS , RULL(0x1401260A), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_IMA_STATUS , RULL(0x1401220A), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 1401270A, 1401220A, 1401230A, -REG64( EQ_5_HTM_IMA_STATUS , RULL(0x1501260A), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_IMA_STATUS , RULL(0x1501220A), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 1501270A, 1501220A, 1501230A, REG64( EX_HTM_IMA_STATUS , RULL(0x1001220A), SH_UNT_EX , SH_ACS_SCOM_RO ); //DUPS: 1001230A, @@ -11845,19 +12023,19 @@ REG64( EX_9_CHTMLBS0_HTM_IMA_STATUS , RULL(0x1401260A REG64( EX_9_CHTMLBS1_HTM_IMA_STATUS , RULL(0x1401270A), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RO ); -REG64( EQ_HTM_LAST , RULL(0x10012603), SH_UNT_EQ , +REG64( EQ_HTM_LAST , RULL(0x10012203), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012703, 10012203, 10012303, -REG64( EQ_0_HTM_LAST , RULL(0x10012603), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_LAST , RULL(0x10012203), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012703, 10012203, 10012303, -REG64( EQ_1_HTM_LAST , RULL(0x11012603), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_LAST , RULL(0x11012203), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012703, 11012203, 11012303, -REG64( EQ_2_HTM_LAST , RULL(0x12012603), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_LAST , RULL(0x12012203), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012703, 12012203, 12012303, -REG64( EQ_3_HTM_LAST , RULL(0x13012603), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_LAST , RULL(0x13012203), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012703, 13012203, 13012303, -REG64( EQ_4_HTM_LAST , RULL(0x14012603), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_LAST , RULL(0x14012203), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012703, 14012203, 14012303, -REG64( EQ_5_HTM_LAST , RULL(0x15012603), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_LAST , RULL(0x15012203), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012703, 15012203, 15012303, REG64( EX_HTM_LAST , RULL(0x10012203), SH_UNT_EX , SH_ACS_SCOM_RO ); //DUPS: 10012303, @@ -11898,19 +12076,19 @@ REG64( EX_9_CHTMLBS0_HTM_LAST , RULL(0x14012603 REG64( EX_9_CHTMLBS1_HTM_LAST , RULL(0x14012703), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RO ); -REG64( EQ_HTM_MEM , RULL(0x10012601), SH_UNT_EQ , +REG64( EQ_HTM_MEM , RULL(0x10012201), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012701, 10012201, 10012301, -REG64( EQ_0_HTM_MEM , RULL(0x10012601), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_MEM , RULL(0x10012201), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012701, 10012201, 10012301, -REG64( EQ_1_HTM_MEM , RULL(0x11012601), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_MEM , RULL(0x11012201), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012701, 11012201, 11012301, -REG64( EQ_2_HTM_MEM , RULL(0x12012601), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_MEM , RULL(0x12012201), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012701, 12012201, 12012301, -REG64( EQ_3_HTM_MEM , RULL(0x13012601), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_MEM , RULL(0x13012201), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012701, 13012201, 13012301, -REG64( EQ_4_HTM_MEM , RULL(0x14012601), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_MEM , RULL(0x14012201), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012701, 14012201, 14012301, -REG64( EQ_5_HTM_MEM , RULL(0x15012601), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_MEM , RULL(0x15012201), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012701, 15012201, 15012301, REG64( EX_HTM_MEM , RULL(0x10012201), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 10012301, @@ -11951,19 +12129,19 @@ REG64( EX_9_CHTMLBS0_HTM_MEM , RULL(0x14012601 REG64( EX_9_CHTMLBS1_HTM_MEM , RULL(0x14012701), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RW ); -REG64( EQ_HTM_MODE , RULL(0x10012600), SH_UNT_EQ , +REG64( EQ_HTM_MODE , RULL(0x10012200), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012700, 10012200, 10012300, -REG64( EQ_0_HTM_MODE , RULL(0x10012600), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_MODE , RULL(0x10012200), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012700, 10012200, 10012300, -REG64( EQ_1_HTM_MODE , RULL(0x11012600), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_MODE , RULL(0x11012200), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012700, 11012200, 11012300, -REG64( EQ_2_HTM_MODE , RULL(0x12012600), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_MODE , RULL(0x12012200), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012700, 12012200, 12012300, -REG64( EQ_3_HTM_MODE , RULL(0x13012600), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_MODE , RULL(0x13012200), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012700, 13012200, 13012300, -REG64( EQ_4_HTM_MODE , RULL(0x14012600), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_MODE , RULL(0x14012200), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012700, 14012200, 14012300, -REG64( EQ_5_HTM_MODE , RULL(0x15012600), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_MODE , RULL(0x15012200), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012700, 15012200, 15012300, REG64( EX_HTM_MODE , RULL(0x10012200), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 10012300, @@ -12004,19 +12182,72 @@ REG64( EX_9_CHTMLBS0_HTM_MODE , RULL(0x14012600 REG64( EX_9_CHTMLBS1_HTM_MODE , RULL(0x14012700), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RW ); -REG64( EQ_HTM_STAT , RULL(0x10012602), SH_UNT_EQ , +REG64( EQ_HTM_PTRC , RULL(0x10012206), SH_UNT_EQ , + SH_ACS_SCOM_RO ); //DUPS: 10012706, 10012206, 10012306, +REG64( EQ_0_HTM_PTRC , RULL(0x10012206), SH_UNT_EQ_0 , + SH_ACS_SCOM_RO ); //DUPS: 10012706, 10012206, 10012306, +REG64( EQ_1_HTM_PTRC , RULL(0x11012206), SH_UNT_EQ_1 , + SH_ACS_SCOM_RO ); //DUPS: 11012706, 11012206, 11012306, +REG64( EQ_2_HTM_PTRC , RULL(0x12012206), SH_UNT_EQ_2 , + SH_ACS_SCOM_RO ); //DUPS: 12012706, 12012206, 12012306, +REG64( EQ_3_HTM_PTRC , RULL(0x13012206), SH_UNT_EQ_3 , + SH_ACS_SCOM_RO ); //DUPS: 13012706, 13012206, 13012306, +REG64( EQ_4_HTM_PTRC , RULL(0x14012206), SH_UNT_EQ_4 , + SH_ACS_SCOM_RO ); //DUPS: 14012706, 14012206, 14012306, +REG64( EQ_5_HTM_PTRC , RULL(0x15012206), SH_UNT_EQ_5 , + SH_ACS_SCOM_RO ); //DUPS: 15012706, 15012206, 15012306, +REG64( EX_HTM_PTRC , RULL(0x10012206), SH_UNT_EX , + SH_ACS_SCOM_RO ); //DUPS: 10012306, +REG64( EX_0_HTM_PTRC , RULL(0x10012206), SH_UNT_EX_0 , + SH_ACS_SCOM_RO ); //DUPS: 10012306, +REG64( EX_2_HTM_PTRC , RULL(0x11012206), SH_UNT_EX_2 , + SH_ACS_SCOM_RO ); //DUPS: 11012306, +REG64( EX_4_HTM_PTRC , RULL(0x12012206), SH_UNT_EX_4 , + SH_ACS_SCOM_RO ); //DUPS: 12012306, +REG64( EX_6_HTM_PTRC , RULL(0x13012206), SH_UNT_EX_6 , + SH_ACS_SCOM_RO ); //DUPS: 13012306, +REG64( EX_8_HTM_PTRC , RULL(0x14012206), SH_UNT_EX_8 , + SH_ACS_SCOM_RO ); //DUPS: 14012306, +REG64( EX_10_HTM_PTRC , RULL(0x15012206), SH_UNT_EX_10 , + SH_ACS_SCOM_RO ); //DUPS: 15012306, +REG64( EX_11_CHTMLBS0_HTM_PTRC , RULL(0x15012606), SH_UNT_EX_11_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_11_CHTMLBS1_HTM_PTRC , RULL(0x15012706), SH_UNT_EX_11_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_1_CHTMLBS0_HTM_PTRC , RULL(0x10012606), SH_UNT_EX_1_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_1_CHTMLBS1_HTM_PTRC , RULL(0x10012706), SH_UNT_EX_1_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_3_CHTMLBS0_HTM_PTRC , RULL(0x11012606), SH_UNT_EX_3_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_3_CHTMLBS1_HTM_PTRC , RULL(0x11012706), SH_UNT_EX_3_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_5_CHTMLBS0_HTM_PTRC , RULL(0x12012606), SH_UNT_EX_5_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_5_CHTMLBS1_HTM_PTRC , RULL(0x12012706), SH_UNT_EX_5_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_7_CHTMLBS0_HTM_PTRC , RULL(0x13012606), SH_UNT_EX_7_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_7_CHTMLBS1_HTM_PTRC , RULL(0x13012706), SH_UNT_EX_7_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_9_CHTMLBS0_HTM_PTRC , RULL(0x14012606), SH_UNT_EX_9_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_9_CHTMLBS1_HTM_PTRC , RULL(0x14012706), SH_UNT_EX_9_CHTMLBS1, + SH_ACS_SCOM_RO ); + +REG64( EQ_HTM_STAT , RULL(0x10012202), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012702, 10012202, 10012302, -REG64( EQ_0_HTM_STAT , RULL(0x10012602), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_STAT , RULL(0x10012202), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012702, 10012202, 10012302, -REG64( EQ_1_HTM_STAT , RULL(0x11012602), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_STAT , RULL(0x11012202), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012702, 11012202, 11012302, -REG64( EQ_2_HTM_STAT , RULL(0x12012602), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_STAT , RULL(0x12012202), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012702, 12012202, 12012302, -REG64( EQ_3_HTM_STAT , RULL(0x13012602), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_STAT , RULL(0x13012202), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012702, 13012202, 13012302, -REG64( EQ_4_HTM_STAT , RULL(0x14012602), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_STAT , RULL(0x14012202), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012702, 14012202, 14012302, -REG64( EQ_5_HTM_STAT , RULL(0x15012602), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_STAT , RULL(0x15012202), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012702, 15012202, 15012302, REG64( EX_HTM_STAT , RULL(0x10012202), SH_UNT_EX , SH_ACS_SCOM_RO ); //DUPS: 10012302, @@ -12057,19 +12288,19 @@ REG64( EX_9_CHTMLBS0_HTM_STAT , RULL(0x14012602 REG64( EX_9_CHTMLBS1_HTM_STAT , RULL(0x14012702), SH_UNT_EX_9_CHTMLBS1, SH_ACS_SCOM_RO ); -REG64( EQ_HTM_TRIG , RULL(0x10012604), SH_UNT_EQ , +REG64( EQ_HTM_TRIG , RULL(0x10012204), SH_UNT_EQ , SH_ACS_SCOM_RW ); //DUPS: 10012704, 10012204, 10012304, -REG64( EQ_0_HTM_TRIG , RULL(0x10012604), SH_UNT_EQ_0 , +REG64( EQ_0_HTM_TRIG , RULL(0x10012204), SH_UNT_EQ_0 , SH_ACS_SCOM_RW ); //DUPS: 10012704, 10012204, 10012304, -REG64( EQ_1_HTM_TRIG , RULL(0x11012604), SH_UNT_EQ_1 , +REG64( EQ_1_HTM_TRIG , RULL(0x11012204), SH_UNT_EQ_1 , SH_ACS_SCOM_RW ); //DUPS: 11012704, 11012204, 11012304, -REG64( EQ_2_HTM_TRIG , RULL(0x12012604), SH_UNT_EQ_2 , +REG64( EQ_2_HTM_TRIG , RULL(0x12012204), SH_UNT_EQ_2 , SH_ACS_SCOM_RW ); //DUPS: 12012704, 12012204, 12012304, -REG64( EQ_3_HTM_TRIG , RULL(0x13012604), SH_UNT_EQ_3 , +REG64( EQ_3_HTM_TRIG , RULL(0x13012204), SH_UNT_EQ_3 , SH_ACS_SCOM_RW ); //DUPS: 13012704, 13012204, 13012304, -REG64( EQ_4_HTM_TRIG , RULL(0x14012604), SH_UNT_EQ_4 , +REG64( EQ_4_HTM_TRIG , RULL(0x14012204), SH_UNT_EQ_4 , SH_ACS_SCOM_RW ); //DUPS: 14012704, 14012204, 14012304, -REG64( EQ_5_HTM_TRIG , RULL(0x15012604), SH_UNT_EQ_5 , +REG64( EQ_5_HTM_TRIG , RULL(0x15012204), SH_UNT_EQ_5 , SH_ACS_SCOM_RW ); //DUPS: 15012704, 15012204, 15012304, REG64( EX_HTM_TRIG , RULL(0x10012204), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 10012304, @@ -12153,7 +12384,7 @@ REG64( EX_5_L2_HV_STATE , RULL(0x2A010AA6 SH_ACS_SCOM_RO ); //DUPS: 2B010AA6, REG64( EX_6_L2_HV_STATE , RULL(0x2C010AA6), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010AA6, -REG64( EX_7_L2_HV_STATE , RULL(0x2E010AA6), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_HV_STATE , RULL(0x2F010AA6), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010AA6, REG64( EX_8_L2_HV_STATE , RULL(0x30010AA6), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010AA6, @@ -12162,6 +12393,214 @@ REG64( EX_9_L2_HV_STATE , RULL(0x32010AA6 REG64( EX_L2_HV_STATE , RULL(0x20010AA6), SH_UNT_EX_L2 , SH_ACS_SCOM_RO ); //DUPS: 21010AA6, +REG64( C_IFU_HOLD_OUT_0 , RULL(0x20010C00), SH_UNT_C , SH_ACS_SCOM_RO ); +REG64( C_0_IFU_HOLD_OUT_0 , RULL(0x20010C00), SH_UNT_C_0 , SH_ACS_SCOM_RO ); +REG64( C_1_IFU_HOLD_OUT_0 , RULL(0x21010C00), SH_UNT_C_1 , SH_ACS_SCOM_RO ); +REG64( C_2_IFU_HOLD_OUT_0 , RULL(0x22010C00), SH_UNT_C_2 , SH_ACS_SCOM_RO ); +REG64( C_3_IFU_HOLD_OUT_0 , RULL(0x23010C00), SH_UNT_C_3 , SH_ACS_SCOM_RO ); +REG64( C_4_IFU_HOLD_OUT_0 , RULL(0x24010C00), SH_UNT_C_4 , SH_ACS_SCOM_RO ); +REG64( C_5_IFU_HOLD_OUT_0 , RULL(0x25010C00), SH_UNT_C_5 , SH_ACS_SCOM_RO ); +REG64( C_6_IFU_HOLD_OUT_0 , RULL(0x26010C00), SH_UNT_C_6 , SH_ACS_SCOM_RO ); +REG64( C_7_IFU_HOLD_OUT_0 , RULL(0x27010C00), SH_UNT_C_7 , SH_ACS_SCOM_RO ); +REG64( C_8_IFU_HOLD_OUT_0 , RULL(0x28010C00), SH_UNT_C_8 , SH_ACS_SCOM_RO ); +REG64( C_9_IFU_HOLD_OUT_0 , RULL(0x29010C00), SH_UNT_C_9 , SH_ACS_SCOM_RO ); +REG64( C_10_IFU_HOLD_OUT_0 , RULL(0x2A010C00), SH_UNT_C_10 , SH_ACS_SCOM_RO ); +REG64( C_11_IFU_HOLD_OUT_0 , RULL(0x2B010C00), SH_UNT_C_11 , SH_ACS_SCOM_RO ); +REG64( C_12_IFU_HOLD_OUT_0 , RULL(0x2C010C00), SH_UNT_C_12 , SH_ACS_SCOM_RO ); +REG64( C_13_IFU_HOLD_OUT_0 , RULL(0x2D010C00), SH_UNT_C_13 , SH_ACS_SCOM_RO ); +REG64( C_14_IFU_HOLD_OUT_0 , RULL(0x2E010C00), SH_UNT_C_14 , SH_ACS_SCOM_RO ); +REG64( C_15_IFU_HOLD_OUT_0 , RULL(0x2F010C00), SH_UNT_C_15 , SH_ACS_SCOM_RO ); +REG64( C_16_IFU_HOLD_OUT_0 , RULL(0x30010C00), SH_UNT_C_16 , SH_ACS_SCOM_RO ); +REG64( C_17_IFU_HOLD_OUT_0 , RULL(0x31010C00), SH_UNT_C_17 , SH_ACS_SCOM_RO ); +REG64( C_18_IFU_HOLD_OUT_0 , RULL(0x32010C00), SH_UNT_C_18 , SH_ACS_SCOM_RO ); +REG64( C_19_IFU_HOLD_OUT_0 , RULL(0x33010C00), SH_UNT_C_19 , SH_ACS_SCOM_RO ); +REG64( C_20_IFU_HOLD_OUT_0 , RULL(0x34010C00), SH_UNT_C_20 , SH_ACS_SCOM_RO ); +REG64( C_21_IFU_HOLD_OUT_0 , RULL(0x35010C00), SH_UNT_C_21 , SH_ACS_SCOM_RO ); +REG64( C_22_IFU_HOLD_OUT_0 , RULL(0x36010C00), SH_UNT_C_22 , SH_ACS_SCOM_RO ); +REG64( C_23_IFU_HOLD_OUT_0 , RULL(0x37010C00), SH_UNT_C_23 , SH_ACS_SCOM_RO ); +REG64( EX_0_L2_IFU_HOLD_OUT_0 , RULL(0x20010C00), SH_UNT_EX_0_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C00, +REG64( EX_10_L2_IFU_HOLD_OUT_0 , RULL(0x34010C00), SH_UNT_EX_10_L2 , + SH_ACS_SCOM_RO ); //DUPS: 35010C00, +REG64( EX_11_L2_IFU_HOLD_OUT_0 , RULL(0x36010C00), SH_UNT_EX_11_L2 , + SH_ACS_SCOM_RO ); //DUPS: 37010C00, +REG64( EX_1_L2_IFU_HOLD_OUT_0 , RULL(0x22010C00), SH_UNT_EX_1_L2 , + SH_ACS_SCOM_RO ); //DUPS: 23010C00, +REG64( EX_2_L2_IFU_HOLD_OUT_0 , RULL(0x24010C00), SH_UNT_EX_2_L2 , + SH_ACS_SCOM_RO ); //DUPS: 25010C00, +REG64( EX_3_L2_IFU_HOLD_OUT_0 , RULL(0x26010C00), SH_UNT_EX_3_L2 , + SH_ACS_SCOM_RO ); //DUPS: 27010C00, +REG64( EX_4_L2_IFU_HOLD_OUT_0 , RULL(0x28010C00), SH_UNT_EX_4_L2 , + SH_ACS_SCOM_RO ); //DUPS: 29010C00, +REG64( EX_5_L2_IFU_HOLD_OUT_0 , RULL(0x2A010C00), SH_UNT_EX_5_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2B010C00, +REG64( EX_6_L2_IFU_HOLD_OUT_0 , RULL(0x2C010C00), SH_UNT_EX_6_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2D010C00, +REG64( EX_7_L2_IFU_HOLD_OUT_0 , RULL(0x2F010C00), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2F010C00, +REG64( EX_8_L2_IFU_HOLD_OUT_0 , RULL(0x30010C00), SH_UNT_EX_8_L2 , + SH_ACS_SCOM_RO ); //DUPS: 31010C00, +REG64( EX_9_L2_IFU_HOLD_OUT_0 , RULL(0x32010C00), SH_UNT_EX_9_L2 , + SH_ACS_SCOM_RO ); //DUPS: 33010C00, +REG64( EX_L2_IFU_HOLD_OUT_0 , RULL(0x20010C00), SH_UNT_EX_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C00, + +REG64( C_IFU_HOLD_OUT_1 , RULL(0x20010C01), SH_UNT_C , SH_ACS_SCOM_RO ); +REG64( C_0_IFU_HOLD_OUT_1 , RULL(0x20010C01), SH_UNT_C_0 , SH_ACS_SCOM_RO ); +REG64( C_1_IFU_HOLD_OUT_1 , RULL(0x21010C01), SH_UNT_C_1 , SH_ACS_SCOM_RO ); +REG64( C_2_IFU_HOLD_OUT_1 , RULL(0x22010C01), SH_UNT_C_2 , SH_ACS_SCOM_RO ); +REG64( C_3_IFU_HOLD_OUT_1 , RULL(0x23010C01), SH_UNT_C_3 , SH_ACS_SCOM_RO ); +REG64( C_4_IFU_HOLD_OUT_1 , RULL(0x24010C01), SH_UNT_C_4 , SH_ACS_SCOM_RO ); +REG64( C_5_IFU_HOLD_OUT_1 , RULL(0x25010C01), SH_UNT_C_5 , SH_ACS_SCOM_RO ); +REG64( C_6_IFU_HOLD_OUT_1 , RULL(0x26010C01), SH_UNT_C_6 , SH_ACS_SCOM_RO ); +REG64( C_7_IFU_HOLD_OUT_1 , RULL(0x27010C01), SH_UNT_C_7 , SH_ACS_SCOM_RO ); +REG64( C_8_IFU_HOLD_OUT_1 , RULL(0x28010C01), SH_UNT_C_8 , SH_ACS_SCOM_RO ); +REG64( C_9_IFU_HOLD_OUT_1 , RULL(0x29010C01), SH_UNT_C_9 , SH_ACS_SCOM_RO ); +REG64( C_10_IFU_HOLD_OUT_1 , RULL(0x2A010C01), SH_UNT_C_10 , SH_ACS_SCOM_RO ); +REG64( C_11_IFU_HOLD_OUT_1 , RULL(0x2B010C01), SH_UNT_C_11 , SH_ACS_SCOM_RO ); +REG64( C_12_IFU_HOLD_OUT_1 , RULL(0x2C010C01), SH_UNT_C_12 , SH_ACS_SCOM_RO ); +REG64( C_13_IFU_HOLD_OUT_1 , RULL(0x2D010C01), SH_UNT_C_13 , SH_ACS_SCOM_RO ); +REG64( C_14_IFU_HOLD_OUT_1 , RULL(0x2E010C01), SH_UNT_C_14 , SH_ACS_SCOM_RO ); +REG64( C_15_IFU_HOLD_OUT_1 , RULL(0x2F010C01), SH_UNT_C_15 , SH_ACS_SCOM_RO ); +REG64( C_16_IFU_HOLD_OUT_1 , RULL(0x30010C01), SH_UNT_C_16 , SH_ACS_SCOM_RO ); +REG64( C_17_IFU_HOLD_OUT_1 , RULL(0x31010C01), SH_UNT_C_17 , SH_ACS_SCOM_RO ); +REG64( C_18_IFU_HOLD_OUT_1 , RULL(0x32010C01), SH_UNT_C_18 , SH_ACS_SCOM_RO ); +REG64( C_19_IFU_HOLD_OUT_1 , RULL(0x33010C01), SH_UNT_C_19 , SH_ACS_SCOM_RO ); +REG64( C_20_IFU_HOLD_OUT_1 , RULL(0x34010C01), SH_UNT_C_20 , SH_ACS_SCOM_RO ); +REG64( C_21_IFU_HOLD_OUT_1 , RULL(0x35010C01), SH_UNT_C_21 , SH_ACS_SCOM_RO ); +REG64( C_22_IFU_HOLD_OUT_1 , RULL(0x36010C01), SH_UNT_C_22 , SH_ACS_SCOM_RO ); +REG64( C_23_IFU_HOLD_OUT_1 , RULL(0x37010C01), SH_UNT_C_23 , SH_ACS_SCOM_RO ); +REG64( EX_0_L2_IFU_HOLD_OUT_1 , RULL(0x20010C01), SH_UNT_EX_0_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C01, +REG64( EX_10_L2_IFU_HOLD_OUT_1 , RULL(0x34010C01), SH_UNT_EX_10_L2 , + SH_ACS_SCOM_RO ); //DUPS: 35010C01, +REG64( EX_11_L2_IFU_HOLD_OUT_1 , RULL(0x36010C01), SH_UNT_EX_11_L2 , + SH_ACS_SCOM_RO ); //DUPS: 37010C01, +REG64( EX_1_L2_IFU_HOLD_OUT_1 , RULL(0x22010C01), SH_UNT_EX_1_L2 , + SH_ACS_SCOM_RO ); //DUPS: 23010C01, +REG64( EX_2_L2_IFU_HOLD_OUT_1 , RULL(0x24010C01), SH_UNT_EX_2_L2 , + SH_ACS_SCOM_RO ); //DUPS: 25010C01, +REG64( EX_3_L2_IFU_HOLD_OUT_1 , RULL(0x26010C01), SH_UNT_EX_3_L2 , + SH_ACS_SCOM_RO ); //DUPS: 27010C01, +REG64( EX_4_L2_IFU_HOLD_OUT_1 , RULL(0x28010C01), SH_UNT_EX_4_L2 , + SH_ACS_SCOM_RO ); //DUPS: 29010C01, +REG64( EX_5_L2_IFU_HOLD_OUT_1 , RULL(0x2A010C01), SH_UNT_EX_5_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2B010C01, +REG64( EX_6_L2_IFU_HOLD_OUT_1 , RULL(0x2C010C01), SH_UNT_EX_6_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2D010C01, +REG64( EX_7_L2_IFU_HOLD_OUT_1 , RULL(0x2F010C01), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2F010C01, +REG64( EX_8_L2_IFU_HOLD_OUT_1 , RULL(0x30010C01), SH_UNT_EX_8_L2 , + SH_ACS_SCOM_RO ); //DUPS: 31010C01, +REG64( EX_9_L2_IFU_HOLD_OUT_1 , RULL(0x32010C01), SH_UNT_EX_9_L2 , + SH_ACS_SCOM_RO ); //DUPS: 33010C01, +REG64( EX_L2_IFU_HOLD_OUT_1 , RULL(0x20010C01), SH_UNT_EX_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C01, + +REG64( C_IFU_HOLD_OUT_2 , RULL(0x20010C02), SH_UNT_C , SH_ACS_SCOM_RO ); +REG64( C_0_IFU_HOLD_OUT_2 , RULL(0x20010C02), SH_UNT_C_0 , SH_ACS_SCOM_RO ); +REG64( C_1_IFU_HOLD_OUT_2 , RULL(0x21010C02), SH_UNT_C_1 , SH_ACS_SCOM_RO ); +REG64( C_2_IFU_HOLD_OUT_2 , RULL(0x22010C02), SH_UNT_C_2 , SH_ACS_SCOM_RO ); +REG64( C_3_IFU_HOLD_OUT_2 , RULL(0x23010C02), SH_UNT_C_3 , SH_ACS_SCOM_RO ); +REG64( C_4_IFU_HOLD_OUT_2 , RULL(0x24010C02), SH_UNT_C_4 , SH_ACS_SCOM_RO ); +REG64( C_5_IFU_HOLD_OUT_2 , RULL(0x25010C02), SH_UNT_C_5 , SH_ACS_SCOM_RO ); +REG64( C_6_IFU_HOLD_OUT_2 , RULL(0x26010C02), SH_UNT_C_6 , SH_ACS_SCOM_RO ); +REG64( C_7_IFU_HOLD_OUT_2 , RULL(0x27010C02), SH_UNT_C_7 , SH_ACS_SCOM_RO ); +REG64( C_8_IFU_HOLD_OUT_2 , RULL(0x28010C02), SH_UNT_C_8 , SH_ACS_SCOM_RO ); +REG64( C_9_IFU_HOLD_OUT_2 , RULL(0x29010C02), SH_UNT_C_9 , SH_ACS_SCOM_RO ); +REG64( C_10_IFU_HOLD_OUT_2 , RULL(0x2A010C02), SH_UNT_C_10 , SH_ACS_SCOM_RO ); +REG64( C_11_IFU_HOLD_OUT_2 , RULL(0x2B010C02), SH_UNT_C_11 , SH_ACS_SCOM_RO ); +REG64( C_12_IFU_HOLD_OUT_2 , RULL(0x2C010C02), SH_UNT_C_12 , SH_ACS_SCOM_RO ); +REG64( C_13_IFU_HOLD_OUT_2 , RULL(0x2D010C02), SH_UNT_C_13 , SH_ACS_SCOM_RO ); +REG64( C_14_IFU_HOLD_OUT_2 , RULL(0x2E010C02), SH_UNT_C_14 , SH_ACS_SCOM_RO ); +REG64( C_15_IFU_HOLD_OUT_2 , RULL(0x2F010C02), SH_UNT_C_15 , SH_ACS_SCOM_RO ); +REG64( C_16_IFU_HOLD_OUT_2 , RULL(0x30010C02), SH_UNT_C_16 , SH_ACS_SCOM_RO ); +REG64( C_17_IFU_HOLD_OUT_2 , RULL(0x31010C02), SH_UNT_C_17 , SH_ACS_SCOM_RO ); +REG64( C_18_IFU_HOLD_OUT_2 , RULL(0x32010C02), SH_UNT_C_18 , SH_ACS_SCOM_RO ); +REG64( C_19_IFU_HOLD_OUT_2 , RULL(0x33010C02), SH_UNT_C_19 , SH_ACS_SCOM_RO ); +REG64( C_20_IFU_HOLD_OUT_2 , RULL(0x34010C02), SH_UNT_C_20 , SH_ACS_SCOM_RO ); +REG64( C_21_IFU_HOLD_OUT_2 , RULL(0x35010C02), SH_UNT_C_21 , SH_ACS_SCOM_RO ); +REG64( C_22_IFU_HOLD_OUT_2 , RULL(0x36010C02), SH_UNT_C_22 , SH_ACS_SCOM_RO ); +REG64( C_23_IFU_HOLD_OUT_2 , RULL(0x37010C02), SH_UNT_C_23 , SH_ACS_SCOM_RO ); +REG64( EX_0_L2_IFU_HOLD_OUT_2 , RULL(0x20010C02), SH_UNT_EX_0_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C02, +REG64( EX_10_L2_IFU_HOLD_OUT_2 , RULL(0x34010C02), SH_UNT_EX_10_L2 , + SH_ACS_SCOM_RO ); //DUPS: 35010C02, +REG64( EX_11_L2_IFU_HOLD_OUT_2 , RULL(0x36010C02), SH_UNT_EX_11_L2 , + SH_ACS_SCOM_RO ); //DUPS: 37010C02, +REG64( EX_1_L2_IFU_HOLD_OUT_2 , RULL(0x22010C02), SH_UNT_EX_1_L2 , + SH_ACS_SCOM_RO ); //DUPS: 23010C02, +REG64( EX_2_L2_IFU_HOLD_OUT_2 , RULL(0x24010C02), SH_UNT_EX_2_L2 , + SH_ACS_SCOM_RO ); //DUPS: 25010C02, +REG64( EX_3_L2_IFU_HOLD_OUT_2 , RULL(0x26010C02), SH_UNT_EX_3_L2 , + SH_ACS_SCOM_RO ); //DUPS: 27010C02, +REG64( EX_4_L2_IFU_HOLD_OUT_2 , RULL(0x28010C02), SH_UNT_EX_4_L2 , + SH_ACS_SCOM_RO ); //DUPS: 29010C02, +REG64( EX_5_L2_IFU_HOLD_OUT_2 , RULL(0x2A010C02), SH_UNT_EX_5_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2B010C02, +REG64( EX_6_L2_IFU_HOLD_OUT_2 , RULL(0x2C010C02), SH_UNT_EX_6_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2D010C02, +REG64( EX_7_L2_IFU_HOLD_OUT_2 , RULL(0x2F010C02), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2F010C02, +REG64( EX_8_L2_IFU_HOLD_OUT_2 , RULL(0x30010C02), SH_UNT_EX_8_L2 , + SH_ACS_SCOM_RO ); //DUPS: 31010C02, +REG64( EX_9_L2_IFU_HOLD_OUT_2 , RULL(0x32010C02), SH_UNT_EX_9_L2 , + SH_ACS_SCOM_RO ); //DUPS: 33010C02, +REG64( EX_L2_IFU_HOLD_OUT_2 , RULL(0x20010C02), SH_UNT_EX_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C02, + +REG64( C_IFU_HOLD_OUT_3 , RULL(0x20010C03), SH_UNT_C , SH_ACS_SCOM_RO ); +REG64( C_0_IFU_HOLD_OUT_3 , RULL(0x20010C03), SH_UNT_C_0 , SH_ACS_SCOM_RO ); +REG64( C_1_IFU_HOLD_OUT_3 , RULL(0x21010C03), SH_UNT_C_1 , SH_ACS_SCOM_RO ); +REG64( C_2_IFU_HOLD_OUT_3 , RULL(0x22010C03), SH_UNT_C_2 , SH_ACS_SCOM_RO ); +REG64( C_3_IFU_HOLD_OUT_3 , RULL(0x23010C03), SH_UNT_C_3 , SH_ACS_SCOM_RO ); +REG64( C_4_IFU_HOLD_OUT_3 , RULL(0x24010C03), SH_UNT_C_4 , SH_ACS_SCOM_RO ); +REG64( C_5_IFU_HOLD_OUT_3 , RULL(0x25010C03), SH_UNT_C_5 , SH_ACS_SCOM_RO ); +REG64( C_6_IFU_HOLD_OUT_3 , RULL(0x26010C03), SH_UNT_C_6 , SH_ACS_SCOM_RO ); +REG64( C_7_IFU_HOLD_OUT_3 , RULL(0x27010C03), SH_UNT_C_7 , SH_ACS_SCOM_RO ); +REG64( C_8_IFU_HOLD_OUT_3 , RULL(0x28010C03), SH_UNT_C_8 , SH_ACS_SCOM_RO ); +REG64( C_9_IFU_HOLD_OUT_3 , RULL(0x29010C03), SH_UNT_C_9 , SH_ACS_SCOM_RO ); +REG64( C_10_IFU_HOLD_OUT_3 , RULL(0x2A010C03), SH_UNT_C_10 , SH_ACS_SCOM_RO ); +REG64( C_11_IFU_HOLD_OUT_3 , RULL(0x2B010C03), SH_UNT_C_11 , SH_ACS_SCOM_RO ); +REG64( C_12_IFU_HOLD_OUT_3 , RULL(0x2C010C03), SH_UNT_C_12 , SH_ACS_SCOM_RO ); +REG64( C_13_IFU_HOLD_OUT_3 , RULL(0x2D010C03), SH_UNT_C_13 , SH_ACS_SCOM_RO ); +REG64( C_14_IFU_HOLD_OUT_3 , RULL(0x2E010C03), SH_UNT_C_14 , SH_ACS_SCOM_RO ); +REG64( C_15_IFU_HOLD_OUT_3 , RULL(0x2F010C03), SH_UNT_C_15 , SH_ACS_SCOM_RO ); +REG64( C_16_IFU_HOLD_OUT_3 , RULL(0x30010C03), SH_UNT_C_16 , SH_ACS_SCOM_RO ); +REG64( C_17_IFU_HOLD_OUT_3 , RULL(0x31010C03), SH_UNT_C_17 , SH_ACS_SCOM_RO ); +REG64( C_18_IFU_HOLD_OUT_3 , RULL(0x32010C03), SH_UNT_C_18 , SH_ACS_SCOM_RO ); +REG64( C_19_IFU_HOLD_OUT_3 , RULL(0x33010C03), SH_UNT_C_19 , SH_ACS_SCOM_RO ); +REG64( C_20_IFU_HOLD_OUT_3 , RULL(0x34010C03), SH_UNT_C_20 , SH_ACS_SCOM_RO ); +REG64( C_21_IFU_HOLD_OUT_3 , RULL(0x35010C03), SH_UNT_C_21 , SH_ACS_SCOM_RO ); +REG64( C_22_IFU_HOLD_OUT_3 , RULL(0x36010C03), SH_UNT_C_22 , SH_ACS_SCOM_RO ); +REG64( C_23_IFU_HOLD_OUT_3 , RULL(0x37010C03), SH_UNT_C_23 , SH_ACS_SCOM_RO ); +REG64( EX_0_L2_IFU_HOLD_OUT_3 , RULL(0x20010C03), SH_UNT_EX_0_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C03, +REG64( EX_10_L2_IFU_HOLD_OUT_3 , RULL(0x34010C03), SH_UNT_EX_10_L2 , + SH_ACS_SCOM_RO ); //DUPS: 35010C03, +REG64( EX_11_L2_IFU_HOLD_OUT_3 , RULL(0x36010C03), SH_UNT_EX_11_L2 , + SH_ACS_SCOM_RO ); //DUPS: 37010C03, +REG64( EX_1_L2_IFU_HOLD_OUT_3 , RULL(0x22010C03), SH_UNT_EX_1_L2 , + SH_ACS_SCOM_RO ); //DUPS: 23010C03, +REG64( EX_2_L2_IFU_HOLD_OUT_3 , RULL(0x24010C03), SH_UNT_EX_2_L2 , + SH_ACS_SCOM_RO ); //DUPS: 25010C03, +REG64( EX_3_L2_IFU_HOLD_OUT_3 , RULL(0x26010C03), SH_UNT_EX_3_L2 , + SH_ACS_SCOM_RO ); //DUPS: 27010C03, +REG64( EX_4_L2_IFU_HOLD_OUT_3 , RULL(0x28010C03), SH_UNT_EX_4_L2 , + SH_ACS_SCOM_RO ); //DUPS: 29010C03, +REG64( EX_5_L2_IFU_HOLD_OUT_3 , RULL(0x2A010C03), SH_UNT_EX_5_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2B010C03, +REG64( EX_6_L2_IFU_HOLD_OUT_3 , RULL(0x2C010C03), SH_UNT_EX_6_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2D010C03, +REG64( EX_7_L2_IFU_HOLD_OUT_3 , RULL(0x2F010C03), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RO ); //DUPS: 2F010C03, +REG64( EX_8_L2_IFU_HOLD_OUT_3 , RULL(0x30010C03), SH_UNT_EX_8_L2 , + SH_ACS_SCOM_RO ); //DUPS: 31010C03, +REG64( EX_9_L2_IFU_HOLD_OUT_3 , RULL(0x32010C03), SH_UNT_EX_9_L2 , + SH_ACS_SCOM_RO ); //DUPS: 33010C03, +REG64( EX_L2_IFU_HOLD_OUT_3 , RULL(0x20010C03), SH_UNT_EX_L2 , + SH_ACS_SCOM_RO ); //DUPS: 21010C03, + REG64( C_IMA_EVENT_MASK , RULL(0x20010AA8), SH_UNT_C , SH_ACS_SCOM_RW ); REG64( C_0_IMA_EVENT_MASK , RULL(0x20010AA8), SH_UNT_C_0 , SH_ACS_SCOM_RW ); REG64( C_1_IMA_EVENT_MASK , RULL(0x21010AA8), SH_UNT_C_1 , SH_ACS_SCOM_RW ); @@ -12203,7 +12642,7 @@ REG64( EX_5_IMA_EVENT_MASK , RULL(0x2A010AA8 SH_ACS_SCOM_RW ); //DUPS: 2B010AA8, REG64( EX_6_IMA_EVENT_MASK , RULL(0x2C010AA8), SH_UNT_EX_6 , SH_ACS_SCOM_RW ); //DUPS: 2D010AA8, -REG64( EX_7_IMA_EVENT_MASK , RULL(0x2E010AA8), SH_UNT_EX_7 , +REG64( EX_7_IMA_EVENT_MASK , RULL(0x2F010AA8), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F010AA8, REG64( EX_8_IMA_EVENT_MASK , RULL(0x30010AA8), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31010AA8, @@ -12255,7 +12694,7 @@ REG64( EX_5_IMA_TRACE , RULL(0x2A010AA9 SH_ACS_SCOM_RW ); //DUPS: 2B010AA9, REG64( EX_6_IMA_TRACE , RULL(0x2C010AA9), SH_UNT_EX_6 , SH_ACS_SCOM_RW ); //DUPS: 2D010AA9, -REG64( EX_7_IMA_TRACE , RULL(0x2E010AA9), SH_UNT_EX_7 , +REG64( EX_7_IMA_TRACE , RULL(0x2F010AA9), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F010AA9, REG64( EX_8_IMA_TRACE , RULL(0x30010AA9), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31010AA9, @@ -12314,7 +12753,7 @@ REG64( EX_5_INJECT_REG , RULL(0x2A050011 SH_ACS_SCOM ); //DUPS: 2B050011, REG64( EX_6_INJECT_REG , RULL(0x2C050011), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D050011, -REG64( EX_7_INJECT_REG , RULL(0x2E050011), SH_UNT_EX_7 , +REG64( EX_7_INJECT_REG , RULL(0x2F050011), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F050011, REG64( EX_8_INJECT_REG , RULL(0x30050011), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31050011, @@ -12396,7 +12835,7 @@ REG64( EX_5_L2_INV_ERATE , RULL(0x2A010AB4 SH_ACS_SCOM ); //DUPS: 2B010AB4, REG64( EX_6_L2_INV_ERATE , RULL(0x2C010AB4), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010AB4, -REG64( EX_7_L2_INV_ERATE , RULL(0x2E010AB4), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_INV_ERATE , RULL(0x2F010AB4), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010AB4, REG64( EX_8_L2_INV_ERATE , RULL(0x30010AB4), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010AB4, @@ -12448,7 +12887,7 @@ REG64( EX_5_L2_ISU_DEBUG_CTRL , RULL(0x2A010C46 SH_ACS_SCOM_RW ); //DUPS: 2B010C46, REG64( EX_6_L2_ISU_DEBUG_CTRL , RULL(0x2C010C46), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010C46, -REG64( EX_7_L2_ISU_DEBUG_CTRL , RULL(0x2E010C46), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_DEBUG_CTRL , RULL(0x2F010C46), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010C46, REG64( EX_8_L2_ISU_DEBUG_CTRL , RULL(0x30010C46), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010C46, @@ -12500,7 +12939,7 @@ REG64( EX_5_L2_ISU_REG0_HOLD_OUT , RULL(0x2A010C40 SH_ACS_SCOM ); //DUPS: 2B010C40, REG64( EX_6_L2_ISU_REG0_HOLD_OUT , RULL(0x2C010C40), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010C40, -REG64( EX_7_L2_ISU_REG0_HOLD_OUT , RULL(0x2E010C40), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_REG0_HOLD_OUT , RULL(0x2F010C40), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010C40, REG64( EX_8_L2_ISU_REG0_HOLD_OUT , RULL(0x30010C40), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010C40, @@ -12552,7 +12991,7 @@ REG64( EX_5_L2_ISU_REG1_HOLD_OUT , RULL(0x2A010C41 SH_ACS_SCOM ); //DUPS: 2B010C41, REG64( EX_6_L2_ISU_REG1_HOLD_OUT , RULL(0x2C010C41), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010C41, -REG64( EX_7_L2_ISU_REG1_HOLD_OUT , RULL(0x2E010C41), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_REG1_HOLD_OUT , RULL(0x2F010C41), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010C41, REG64( EX_8_L2_ISU_REG1_HOLD_OUT , RULL(0x30010C41), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010C41, @@ -12604,7 +13043,7 @@ REG64( EX_5_L2_ISU_REG2_HOLD_OUT , RULL(0x2A010C42 SH_ACS_SCOM ); //DUPS: 2B010C42, REG64( EX_6_L2_ISU_REG2_HOLD_OUT , RULL(0x2C010C42), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010C42, -REG64( EX_7_L2_ISU_REG2_HOLD_OUT , RULL(0x2E010C42), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_REG2_HOLD_OUT , RULL(0x2F010C42), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010C42, REG64( EX_8_L2_ISU_REG2_HOLD_OUT , RULL(0x30010C42), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010C42, @@ -12656,7 +13095,7 @@ REG64( EX_5_L2_ISU_REG3_HOLD_OUT , RULL(0x2A010C43 SH_ACS_SCOM ); //DUPS: 2B010C43, REG64( EX_6_L2_ISU_REG3_HOLD_OUT , RULL(0x2C010C43), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010C43, -REG64( EX_7_L2_ISU_REG3_HOLD_OUT , RULL(0x2E010C43), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_REG3_HOLD_OUT , RULL(0x2F010C43), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010C43, REG64( EX_8_L2_ISU_REG3_HOLD_OUT , RULL(0x30010C43), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010C43, @@ -12708,7 +13147,7 @@ REG64( EX_5_L2_ISU_REG4_HOLD_OUT , RULL(0x2A010C44 SH_ACS_SCOM ); //DUPS: 2B010C44, REG64( EX_6_L2_ISU_REG4_HOLD_OUT , RULL(0x2C010C44), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010C44, -REG64( EX_7_L2_ISU_REG4_HOLD_OUT , RULL(0x2E010C44), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_REG4_HOLD_OUT , RULL(0x2F010C44), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010C44, REG64( EX_8_L2_ISU_REG4_HOLD_OUT , RULL(0x30010C44), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010C44, @@ -12760,7 +13199,7 @@ REG64( EX_5_L2_ISU_REG5_HOLD_OUT , RULL(0x2A010C45 SH_ACS_SCOM ); //DUPS: 2B010C45, REG64( EX_6_L2_ISU_REG5_HOLD_OUT , RULL(0x2C010C45), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010C45, -REG64( EX_7_L2_ISU_REG5_HOLD_OUT , RULL(0x2E010C45), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_ISU_REG5_HOLD_OUT , RULL(0x2F010C45), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010C45, REG64( EX_8_L2_ISU_REG5_HOLD_OUT , RULL(0x30010C45), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010C45, @@ -13089,19 +13528,19 @@ REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x130104C9 REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x140104C9), SH_UNT_EQ_4 , SH_ACS_SCOM ); REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x150104C9), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EQ_L3_ERR_RPT0_REG , RULL(0x10011810), SH_UNT_EQ , +REG64( EQ_L3_ERR_RPT0_REG , RULL(0x10011C10), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C10, -REG64( EQ_0_L3_ERR_RPT0_REG , RULL(0x10011810), SH_UNT_EQ_0 , +REG64( EQ_0_L3_ERR_RPT0_REG , RULL(0x10011C10), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C10, -REG64( EQ_1_L3_ERR_RPT0_REG , RULL(0x11011810), SH_UNT_EQ_1 , +REG64( EQ_1_L3_ERR_RPT0_REG , RULL(0x11011C10), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C10, -REG64( EQ_2_L3_ERR_RPT0_REG , RULL(0x12011810), SH_UNT_EQ_2 , +REG64( EQ_2_L3_ERR_RPT0_REG , RULL(0x12011C10), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C10, -REG64( EQ_3_L3_ERR_RPT0_REG , RULL(0x13011810), SH_UNT_EQ_3 , +REG64( EQ_3_L3_ERR_RPT0_REG , RULL(0x13011C10), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C10, -REG64( EQ_4_L3_ERR_RPT0_REG , RULL(0x14011810), SH_UNT_EQ_4 , +REG64( EQ_4_L3_ERR_RPT0_REG , RULL(0x14011C10), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C10, -REG64( EQ_5_L3_ERR_RPT0_REG , RULL(0x15011810), SH_UNT_EQ_5 , +REG64( EQ_5_L3_ERR_RPT0_REG , RULL(0x15011C10), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C10, REG64( EX_0_L3_L3_ERR_RPT0_REG , RULL(0x10011810), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_L3_ERR_RPT0_REG , RULL(0x15011810), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -13117,19 +13556,19 @@ REG64( EX_8_L3_L3_ERR_RPT0_REG , RULL(0x14011810 REG64( EX_9_L3_L3_ERR_RPT0_REG , RULL(0x14011C10), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_L3_ERR_RPT0_REG , RULL(0x10011810), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_L3_ERR_RPT1_REG , RULL(0x10011817), SH_UNT_EQ , +REG64( EQ_L3_ERR_RPT1_REG , RULL(0x10011C17), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C17, -REG64( EQ_0_L3_ERR_RPT1_REG , RULL(0x10011817), SH_UNT_EQ_0 , +REG64( EQ_0_L3_ERR_RPT1_REG , RULL(0x10011C17), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C17, -REG64( EQ_1_L3_ERR_RPT1_REG , RULL(0x11011817), SH_UNT_EQ_1 , +REG64( EQ_1_L3_ERR_RPT1_REG , RULL(0x11011C17), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C17, -REG64( EQ_2_L3_ERR_RPT1_REG , RULL(0x12011817), SH_UNT_EQ_2 , +REG64( EQ_2_L3_ERR_RPT1_REG , RULL(0x12011C17), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C17, -REG64( EQ_3_L3_ERR_RPT1_REG , RULL(0x13011817), SH_UNT_EQ_3 , +REG64( EQ_3_L3_ERR_RPT1_REG , RULL(0x13011C17), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C17, -REG64( EQ_4_L3_ERR_RPT1_REG , RULL(0x14011817), SH_UNT_EQ_4 , +REG64( EQ_4_L3_ERR_RPT1_REG , RULL(0x14011C17), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C17, -REG64( EQ_5_L3_ERR_RPT1_REG , RULL(0x15011817), SH_UNT_EQ_5 , +REG64( EQ_5_L3_ERR_RPT1_REG , RULL(0x15011C17), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C17, REG64( EX_0_L3_L3_ERR_RPT1_REG , RULL(0x10011817), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_L3_ERR_RPT1_REG , RULL(0x15011817), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -13145,19 +13584,19 @@ REG64( EX_8_L3_L3_ERR_RPT1_REG , RULL(0x14011817 REG64( EX_9_L3_L3_ERR_RPT1_REG , RULL(0x14011C17), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_L3_ERR_RPT1_REG , RULL(0x10011817), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_L3_RD_EPSILON_CFG_REG , RULL(0x10011829), SH_UNT_EQ , +REG64( EQ_L3_RD_EPSILON_CFG_REG , RULL(0x10011C29), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C29, -REG64( EQ_0_L3_RD_EPSILON_CFG_REG , RULL(0x10011829), SH_UNT_EQ_0 , +REG64( EQ_0_L3_RD_EPSILON_CFG_REG , RULL(0x10011C29), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C29, -REG64( EQ_1_L3_RD_EPSILON_CFG_REG , RULL(0x11011829), SH_UNT_EQ_1 , +REG64( EQ_1_L3_RD_EPSILON_CFG_REG , RULL(0x11011C29), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C29, -REG64( EQ_2_L3_RD_EPSILON_CFG_REG , RULL(0x12011829), SH_UNT_EQ_2 , +REG64( EQ_2_L3_RD_EPSILON_CFG_REG , RULL(0x12011C29), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C29, -REG64( EQ_3_L3_RD_EPSILON_CFG_REG , RULL(0x13011829), SH_UNT_EQ_3 , +REG64( EQ_3_L3_RD_EPSILON_CFG_REG , RULL(0x13011C29), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C29, -REG64( EQ_4_L3_RD_EPSILON_CFG_REG , RULL(0x14011829), SH_UNT_EQ_4 , +REG64( EQ_4_L3_RD_EPSILON_CFG_REG , RULL(0x14011C29), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C29, -REG64( EQ_5_L3_RD_EPSILON_CFG_REG , RULL(0x15011829), SH_UNT_EQ_5 , +REG64( EQ_5_L3_RD_EPSILON_CFG_REG , RULL(0x15011C29), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C29, REG64( EX_L3_RD_EPSILON_CFG_REG , RULL(0x10011829), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_L3_RD_EPSILON_CFG_REG , RULL(0x10011829), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -13173,19 +13612,19 @@ REG64( EX_9_L3_RD_EPSILON_CFG_REG , RULL(0x14011C29 REG64( EX_10_L3_RD_EPSILON_CFG_REG , RULL(0x15011829), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_L3_RD_EPSILON_CFG_REG , RULL(0x15011C29), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_L3_RTIM_PERIOD_MONITOR , RULL(0x10011812), SH_UNT_EQ , +REG64( EQ_L3_RTIM_PERIOD_MONITOR , RULL(0x10011C12), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C12, -REG64( EQ_0_L3_RTIM_PERIOD_MONITOR , RULL(0x10011812), SH_UNT_EQ_0 , +REG64( EQ_0_L3_RTIM_PERIOD_MONITOR , RULL(0x10011C12), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C12, -REG64( EQ_1_L3_RTIM_PERIOD_MONITOR , RULL(0x11011812), SH_UNT_EQ_1 , +REG64( EQ_1_L3_RTIM_PERIOD_MONITOR , RULL(0x11011C12), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C12, -REG64( EQ_2_L3_RTIM_PERIOD_MONITOR , RULL(0x12011812), SH_UNT_EQ_2 , +REG64( EQ_2_L3_RTIM_PERIOD_MONITOR , RULL(0x12011C12), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C12, -REG64( EQ_3_L3_RTIM_PERIOD_MONITOR , RULL(0x13011812), SH_UNT_EQ_3 , +REG64( EQ_3_L3_RTIM_PERIOD_MONITOR , RULL(0x13011C12), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C12, -REG64( EQ_4_L3_RTIM_PERIOD_MONITOR , RULL(0x14011812), SH_UNT_EQ_4 , +REG64( EQ_4_L3_RTIM_PERIOD_MONITOR , RULL(0x14011C12), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C12, -REG64( EQ_5_L3_RTIM_PERIOD_MONITOR , RULL(0x15011812), SH_UNT_EQ_5 , +REG64( EQ_5_L3_RTIM_PERIOD_MONITOR , RULL(0x15011C12), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C12, REG64( EX_0_L3_L3_RTIM_PERIOD_MONITOR , RULL(0x10011812), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_L3_RTIM_PERIOD_MONITOR , RULL(0x15011812), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -13201,19 +13640,19 @@ REG64( EX_8_L3_L3_RTIM_PERIOD_MONITOR , RULL(0x14011812 REG64( EX_9_L3_L3_RTIM_PERIOD_MONITOR , RULL(0x14011C12), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_L3_RTIM_PERIOD_MONITOR , RULL(0x10011812), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_L3_WR_EPSILON_CFG_REG , RULL(0x1001182A), SH_UNT_EQ , +REG64( EQ_L3_WR_EPSILON_CFG_REG , RULL(0x10011C2A), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C2A, -REG64( EQ_0_L3_WR_EPSILON_CFG_REG , RULL(0x1001182A), SH_UNT_EQ_0 , +REG64( EQ_0_L3_WR_EPSILON_CFG_REG , RULL(0x10011C2A), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C2A, -REG64( EQ_1_L3_WR_EPSILON_CFG_REG , RULL(0x1101182A), SH_UNT_EQ_1 , +REG64( EQ_1_L3_WR_EPSILON_CFG_REG , RULL(0x11011C2A), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C2A, -REG64( EQ_2_L3_WR_EPSILON_CFG_REG , RULL(0x1201182A), SH_UNT_EQ_2 , +REG64( EQ_2_L3_WR_EPSILON_CFG_REG , RULL(0x12011C2A), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C2A, -REG64( EQ_3_L3_WR_EPSILON_CFG_REG , RULL(0x1301182A), SH_UNT_EQ_3 , +REG64( EQ_3_L3_WR_EPSILON_CFG_REG , RULL(0x13011C2A), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C2A, -REG64( EQ_4_L3_WR_EPSILON_CFG_REG , RULL(0x1401182A), SH_UNT_EQ_4 , +REG64( EQ_4_L3_WR_EPSILON_CFG_REG , RULL(0x14011C2A), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C2A, -REG64( EQ_5_L3_WR_EPSILON_CFG_REG , RULL(0x1501182A), SH_UNT_EQ_5 , +REG64( EQ_5_L3_WR_EPSILON_CFG_REG , RULL(0x15011C2A), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C2A, REG64( EX_0_L3_L3_WR_EPSILON_CFG_REG , RULL(0x1001182A), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_L3_WR_EPSILON_CFG_REG , RULL(0x1501182A), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -13229,19 +13668,19 @@ REG64( EX_8_L3_L3_WR_EPSILON_CFG_REG , RULL(0x1401182A REG64( EX_9_L3_L3_WR_EPSILON_CFG_REG , RULL(0x14011C2A), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_L3_WR_EPSILON_CFG_REG , RULL(0x1001182A), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_LINEDEL_TRIG_REG , RULL(0x1001080D), SH_UNT_EQ , +REG64( EQ_LINEDEL_TRIG_REG , RULL(0x10010C0D), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C0D, -REG64( EQ_0_LINEDEL_TRIG_REG , RULL(0x1001080D), SH_UNT_EQ_0 , +REG64( EQ_0_LINEDEL_TRIG_REG , RULL(0x10010C0D), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C0D, -REG64( EQ_1_LINEDEL_TRIG_REG , RULL(0x1101080D), SH_UNT_EQ_1 , +REG64( EQ_1_LINEDEL_TRIG_REG , RULL(0x11010C0D), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C0D, -REG64( EQ_2_LINEDEL_TRIG_REG , RULL(0x1201080D), SH_UNT_EQ_2 , +REG64( EQ_2_LINEDEL_TRIG_REG , RULL(0x12010C0D), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C0D, -REG64( EQ_3_LINEDEL_TRIG_REG , RULL(0x1301080D), SH_UNT_EQ_3 , +REG64( EQ_3_LINEDEL_TRIG_REG , RULL(0x13010C0D), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C0D, -REG64( EQ_4_LINEDEL_TRIG_REG , RULL(0x1401080D), SH_UNT_EQ_4 , +REG64( EQ_4_LINEDEL_TRIG_REG , RULL(0x14010C0D), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C0D, -REG64( EQ_5_LINEDEL_TRIG_REG , RULL(0x1501080D), SH_UNT_EQ_5 , +REG64( EQ_5_LINEDEL_TRIG_REG , RULL(0x15010C0D), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C0D, REG64( EX_0_L2_LINEDEL_TRIG_REG , RULL(0x1001080D), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_10_L2_LINEDEL_TRIG_REG , RULL(0x1501080D), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); @@ -13257,19 +13696,19 @@ REG64( EX_8_L2_LINEDEL_TRIG_REG , RULL(0x1401080D REG64( EX_9_L2_LINEDEL_TRIG_REG , RULL(0x14010C0D), SH_UNT_EX_9_L2 , SH_ACS_SCOM ); REG64( EX_L2_LINEDEL_TRIG_REG , RULL(0x1001080D), SH_UNT_EX_L2 , SH_ACS_SCOM ); -REG64( EQ_LINE_DELETED_MEMBERS_REG , RULL(0x10011815), SH_UNT_EQ , +REG64( EQ_LINE_DELETED_MEMBERS_REG , RULL(0x10011C15), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C15, -REG64( EQ_0_LINE_DELETED_MEMBERS_REG , RULL(0x10011815), SH_UNT_EQ_0 , +REG64( EQ_0_LINE_DELETED_MEMBERS_REG , RULL(0x10011C15), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C15, -REG64( EQ_1_LINE_DELETED_MEMBERS_REG , RULL(0x11011815), SH_UNT_EQ_1 , +REG64( EQ_1_LINE_DELETED_MEMBERS_REG , RULL(0x11011C15), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C15, -REG64( EQ_2_LINE_DELETED_MEMBERS_REG , RULL(0x12011815), SH_UNT_EQ_2 , +REG64( EQ_2_LINE_DELETED_MEMBERS_REG , RULL(0x12011C15), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C15, -REG64( EQ_3_LINE_DELETED_MEMBERS_REG , RULL(0x13011815), SH_UNT_EQ_3 , +REG64( EQ_3_LINE_DELETED_MEMBERS_REG , RULL(0x13011C15), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C15, -REG64( EQ_4_LINE_DELETED_MEMBERS_REG , RULL(0x14011815), SH_UNT_EQ_4 , +REG64( EQ_4_LINE_DELETED_MEMBERS_REG , RULL(0x14011C15), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C15, -REG64( EQ_5_LINE_DELETED_MEMBERS_REG , RULL(0x15011815), SH_UNT_EQ_5 , +REG64( EQ_5_LINE_DELETED_MEMBERS_REG , RULL(0x15011C15), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C15, REG64( EX_0_L3_LINE_DELETED_MEMBERS_REG , RULL(0x10011815), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_LINE_DELETED_MEMBERS_REG , RULL(0x15011815), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -13429,11 +13868,11 @@ REG64( EX_6_LOCAL_FIR_AND , RULL(0x2C04000B SH_ACS_SCOM1_AND ); //DUPS: 2D04000B, REG64( EX_6_LOCAL_FIR_OR , RULL(0x2C04000C), SH_UNT_EX_6 , SH_ACS_SCOM2_OR ); //DUPS: 2D04000C, -REG64( EX_7_LOCAL_FIR , RULL(0x2E04000A), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR , RULL(0x2F04000A), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F04000A, -REG64( EX_7_LOCAL_FIR_AND , RULL(0x2E04000B), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_AND , RULL(0x2F04000B), SH_UNT_EX_7 , SH_ACS_SCOM1_AND ); //DUPS: 2F04000B, -REG64( EX_7_LOCAL_FIR_OR , RULL(0x2E04000C), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_OR , RULL(0x2F04000C), SH_UNT_EX_7 , SH_ACS_SCOM2_OR ); //DUPS: 2F04000C, REG64( EX_8_LOCAL_FIR , RULL(0x3004000A), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 3104000A, @@ -13508,7 +13947,7 @@ REG64( EX_5_LOCAL_FIR_ACTION0 , RULL(0x2A040010 SH_ACS_SCOM ); //DUPS: 2B040010, REG64( EX_6_LOCAL_FIR_ACTION0 , RULL(0x2C040010), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040010, -REG64( EX_7_LOCAL_FIR_ACTION0 , RULL(0x2E040010), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_ACTION0 , RULL(0x2F040010), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040010, REG64( EX_8_LOCAL_FIR_ACTION0 , RULL(0x30040010), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040010, @@ -13567,7 +14006,7 @@ REG64( EX_5_LOCAL_FIR_ACTION1 , RULL(0x2A040011 SH_ACS_SCOM ); //DUPS: 2B040011, REG64( EX_6_LOCAL_FIR_ACTION1 , RULL(0x2C040011), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040011, -REG64( EX_7_LOCAL_FIR_ACTION1 , RULL(0x2E040011), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_ACTION1 , RULL(0x2F040011), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040011, REG64( EX_8_LOCAL_FIR_ACTION1 , RULL(0x30040011), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040011, @@ -13722,11 +14161,11 @@ REG64( EX_6_LOCAL_FIR_MASK_AND , RULL(0x2C04000E SH_ACS_SCOM1_AND ); //DUPS: 2D04000E, REG64( EX_6_LOCAL_FIR_MASK_OR , RULL(0x2C04000F), SH_UNT_EX_6 , SH_ACS_SCOM2_OR ); //DUPS: 2D04000F, -REG64( EX_7_LOCAL_FIR_MASK , RULL(0x2E04000D), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_MASK , RULL(0x2F04000D), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F04000D, -REG64( EX_7_LOCAL_FIR_MASK_AND , RULL(0x2E04000E), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_MASK_AND , RULL(0x2F04000E), SH_UNT_EX_7 , SH_ACS_SCOM1_AND ); //DUPS: 2F04000E, -REG64( EX_7_LOCAL_FIR_MASK_OR , RULL(0x2E04000F), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_FIR_MASK_OR , RULL(0x2F04000F), SH_UNT_EX_7 , SH_ACS_SCOM2_OR ); //DUPS: 2F04000F, REG64( EX_8_LOCAL_FIR_MASK , RULL(0x3004000D), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 3104000D, @@ -13801,7 +14240,7 @@ REG64( EX_5_LOCAL_XSTOP_ERR , RULL(0x2A040018 SH_ACS_SCOM_RO ); //DUPS: 2B040018, REG64( EX_6_LOCAL_XSTOP_ERR , RULL(0x2C040018), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D040018, -REG64( EX_7_LOCAL_XSTOP_ERR , RULL(0x2E040018), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_XSTOP_ERR , RULL(0x2F040018), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F040018, REG64( EX_8_LOCAL_XSTOP_ERR , RULL(0x30040018), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31040018, @@ -13860,7 +14299,7 @@ REG64( EX_5_LOCAL_XSTOP_MASK , RULL(0x2A040019 SH_ACS_SCOM ); //DUPS: 2B040019, REG64( EX_6_LOCAL_XSTOP_MASK , RULL(0x2C040019), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040019, -REG64( EX_7_LOCAL_XSTOP_MASK , RULL(0x2E040019), SH_UNT_EX_7 , +REG64( EX_7_LOCAL_XSTOP_MASK , RULL(0x2F040019), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040019, REG64( EX_8_LOCAL_XSTOP_MASK , RULL(0x30040019), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040019, @@ -13871,19 +14310,19 @@ REG64( EX_10_LOCAL_XSTOP_MASK , RULL(0x34040019 REG64( EX_11_LOCAL_XSTOP_MASK , RULL(0x36040019), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37040019, -REG64( EQ_LRU_VIC_ALLOC_REG , RULL(0x10011811), SH_UNT_EQ , +REG64( EQ_LRU_VIC_ALLOC_REG , RULL(0x10011C11), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C11, -REG64( EQ_0_LRU_VIC_ALLOC_REG , RULL(0x10011811), SH_UNT_EQ_0 , +REG64( EQ_0_LRU_VIC_ALLOC_REG , RULL(0x10011C11), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C11, -REG64( EQ_1_LRU_VIC_ALLOC_REG , RULL(0x11011811), SH_UNT_EQ_1 , +REG64( EQ_1_LRU_VIC_ALLOC_REG , RULL(0x11011C11), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C11, -REG64( EQ_2_LRU_VIC_ALLOC_REG , RULL(0x12011811), SH_UNT_EQ_2 , +REG64( EQ_2_LRU_VIC_ALLOC_REG , RULL(0x12011C11), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C11, -REG64( EQ_3_LRU_VIC_ALLOC_REG , RULL(0x13011811), SH_UNT_EQ_3 , +REG64( EQ_3_LRU_VIC_ALLOC_REG , RULL(0x13011C11), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C11, -REG64( EQ_4_LRU_VIC_ALLOC_REG , RULL(0x14011811), SH_UNT_EQ_4 , +REG64( EQ_4_LRU_VIC_ALLOC_REG , RULL(0x14011C11), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C11, -REG64( EQ_5_LRU_VIC_ALLOC_REG , RULL(0x15011811), SH_UNT_EQ_5 , +REG64( EQ_5_LRU_VIC_ALLOC_REG , RULL(0x15011C11), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C11, REG64( EX_0_L3_LRU_VIC_ALLOC_REG , RULL(0x10011811), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_LRU_VIC_ALLOC_REG , RULL(0x15011811), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -13942,7 +14381,7 @@ REG64( EX_5_L2_LSU_HOLD_OUT_REG0 , RULL(0x2A010C80 SH_ACS_SCOM_RO ); //DUPS: 2B010C80, REG64( EX_6_L2_LSU_HOLD_OUT_REG0 , RULL(0x2C010C80), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010C80, -REG64( EX_7_L2_LSU_HOLD_OUT_REG0 , RULL(0x2E010C80), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_LSU_HOLD_OUT_REG0 , RULL(0x2F010C80), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010C80, REG64( EX_8_L2_LSU_HOLD_OUT_REG0 , RULL(0x30010C80), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010C80, @@ -13994,7 +14433,7 @@ REG64( EX_5_L2_LSU_HOLD_OUT_REG1 , RULL(0x2A010C81 SH_ACS_SCOM_RO ); //DUPS: 2B010C81, REG64( EX_6_L2_LSU_HOLD_OUT_REG1 , RULL(0x2C010C81), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010C81, -REG64( EX_7_L2_LSU_HOLD_OUT_REG1 , RULL(0x2E010C81), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_LSU_HOLD_OUT_REG1 , RULL(0x2F010C81), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010C81, REG64( EX_8_L2_LSU_HOLD_OUT_REG1 , RULL(0x30010C81), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010C81, @@ -14046,7 +14485,7 @@ REG64( EX_5_L2_LSU_HOLD_OUT_REG2 , RULL(0x2A010C82 SH_ACS_SCOM_RO ); //DUPS: 2B010C82, REG64( EX_6_L2_LSU_HOLD_OUT_REG2 , RULL(0x2C010C82), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010C82, -REG64( EX_7_L2_LSU_HOLD_OUT_REG2 , RULL(0x2E010C82), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_LSU_HOLD_OUT_REG2 , RULL(0x2F010C82), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010C82, REG64( EX_8_L2_LSU_HOLD_OUT_REG2 , RULL(0x30010C82), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010C82, @@ -14098,7 +14537,7 @@ REG64( EX_5_L2_LSU_HOLD_OUT_REG3 , RULL(0x2A010C83 SH_ACS_SCOM_RO ); //DUPS: 2B010C83, REG64( EX_6_L2_LSU_HOLD_OUT_REG3 , RULL(0x2C010C83), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010C83, -REG64( EX_7_L2_LSU_HOLD_OUT_REG3 , RULL(0x2E010C83), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_LSU_HOLD_OUT_REG3 , RULL(0x2F010C83), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010C83, REG64( EX_8_L2_LSU_HOLD_OUT_REG3 , RULL(0x30010C83), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010C83, @@ -14107,19 +14546,72 @@ REG64( EX_9_L2_LSU_HOLD_OUT_REG3 , RULL(0x32010C83 REG64( EX_L2_LSU_HOLD_OUT_REG3 , RULL(0x20010C83), SH_UNT_EX_L2 , SH_ACS_SCOM_RO ); //DUPS: 21010C83, -REG64( EQ_MIB_XIICAC , RULL(0x10012419), SH_UNT_EQ , +REG64( EQ_MEM_OP_CTR , RULL(0x10012208), SH_UNT_EQ , + SH_ACS_SCOM_RO ); //DUPS: 10012708, 10012208, 10012308, +REG64( EQ_0_MEM_OP_CTR , RULL(0x10012208), SH_UNT_EQ_0 , + SH_ACS_SCOM_RO ); //DUPS: 10012708, 10012208, 10012308, +REG64( EQ_1_MEM_OP_CTR , RULL(0x11012208), SH_UNT_EQ_1 , + SH_ACS_SCOM_RO ); //DUPS: 11012708, 11012208, 11012308, +REG64( EQ_2_MEM_OP_CTR , RULL(0x12012208), SH_UNT_EQ_2 , + SH_ACS_SCOM_RO ); //DUPS: 12012708, 12012208, 12012308, +REG64( EQ_3_MEM_OP_CTR , RULL(0x13012208), SH_UNT_EQ_3 , + SH_ACS_SCOM_RO ); //DUPS: 13012708, 13012208, 13012308, +REG64( EQ_4_MEM_OP_CTR , RULL(0x14012208), SH_UNT_EQ_4 , + SH_ACS_SCOM_RO ); //DUPS: 14012708, 14012208, 14012308, +REG64( EQ_5_MEM_OP_CTR , RULL(0x15012208), SH_UNT_EQ_5 , + SH_ACS_SCOM_RO ); //DUPS: 15012708, 15012208, 15012308, +REG64( EX_MEM_OP_CTR , RULL(0x10012208), SH_UNT_EX , + SH_ACS_SCOM_RO ); //DUPS: 10012308, +REG64( EX_0_MEM_OP_CTR , RULL(0x10012208), SH_UNT_EX_0 , + SH_ACS_SCOM_RO ); //DUPS: 10012308, +REG64( EX_2_MEM_OP_CTR , RULL(0x11012208), SH_UNT_EX_2 , + SH_ACS_SCOM_RO ); //DUPS: 11012308, +REG64( EX_4_MEM_OP_CTR , RULL(0x12012208), SH_UNT_EX_4 , + SH_ACS_SCOM_RO ); //DUPS: 12012308, +REG64( EX_6_MEM_OP_CTR , RULL(0x13012208), SH_UNT_EX_6 , + SH_ACS_SCOM_RO ); //DUPS: 13012308, +REG64( EX_8_MEM_OP_CTR , RULL(0x14012208), SH_UNT_EX_8 , + SH_ACS_SCOM_RO ); //DUPS: 14012308, +REG64( EX_10_MEM_OP_CTR , RULL(0x15012208), SH_UNT_EX_10 , + SH_ACS_SCOM_RO ); //DUPS: 15012308, +REG64( EX_11_CHTMLBS0_MEM_OP_CTR , RULL(0x15012608), SH_UNT_EX_11_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_11_CHTMLBS1_MEM_OP_CTR , RULL(0x15012708), SH_UNT_EX_11_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_1_CHTMLBS0_MEM_OP_CTR , RULL(0x10012608), SH_UNT_EX_1_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_1_CHTMLBS1_MEM_OP_CTR , RULL(0x10012708), SH_UNT_EX_1_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_3_CHTMLBS0_MEM_OP_CTR , RULL(0x11012608), SH_UNT_EX_3_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_3_CHTMLBS1_MEM_OP_CTR , RULL(0x11012708), SH_UNT_EX_3_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_5_CHTMLBS0_MEM_OP_CTR , RULL(0x12012608), SH_UNT_EX_5_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_5_CHTMLBS1_MEM_OP_CTR , RULL(0x12012708), SH_UNT_EX_5_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_7_CHTMLBS0_MEM_OP_CTR , RULL(0x13012608), SH_UNT_EX_7_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_7_CHTMLBS1_MEM_OP_CTR , RULL(0x13012708), SH_UNT_EX_7_CHTMLBS1, + SH_ACS_SCOM_RO ); +REG64( EX_9_CHTMLBS0_MEM_OP_CTR , RULL(0x14012608), SH_UNT_EX_9_CHTMLBS0, + SH_ACS_SCOM_RO ); +REG64( EX_9_CHTMLBS1_MEM_OP_CTR , RULL(0x14012708), SH_UNT_EX_9_CHTMLBS1, + SH_ACS_SCOM_RO ); + +REG64( EQ_MIB_XIICAC , RULL(0x10012019), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012019, -REG64( EQ_0_MIB_XIICAC , RULL(0x10012419), SH_UNT_EQ_0 , +REG64( EQ_0_MIB_XIICAC , RULL(0x10012019), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012019, -REG64( EQ_1_MIB_XIICAC , RULL(0x11012419), SH_UNT_EQ_1 , +REG64( EQ_1_MIB_XIICAC , RULL(0x11012019), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012019, -REG64( EQ_2_MIB_XIICAC , RULL(0x12012419), SH_UNT_EQ_2 , +REG64( EQ_2_MIB_XIICAC , RULL(0x12012019), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012019, -REG64( EQ_3_MIB_XIICAC , RULL(0x13012419), SH_UNT_EQ_3 , +REG64( EQ_3_MIB_XIICAC , RULL(0x13012019), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012019, -REG64( EQ_4_MIB_XIICAC , RULL(0x14012419), SH_UNT_EQ_4 , +REG64( EQ_4_MIB_XIICAC , RULL(0x14012019), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012019, -REG64( EQ_5_MIB_XIICAC , RULL(0x15012419), SH_UNT_EQ_5 , +REG64( EQ_5_MIB_XIICAC , RULL(0x15012019), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012019, REG64( EX_MIB_XIICAC , RULL(0x10012019), SH_UNT_EX , SH_ACS_SCOM_RO ); REG64( EX_0_MIB_XIICAC , RULL(0x10012019), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); @@ -14135,19 +14627,19 @@ REG64( EX_9_MIB_XIICAC , RULL(0x14012419 REG64( EX_10_MIB_XIICAC , RULL(0x15012019), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); REG64( EX_11_MIB_XIICAC , RULL(0x15012419), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_MIB_XIMEM , RULL(0x10012417), SH_UNT_EQ , +REG64( EQ_MIB_XIMEM , RULL(0x10012017), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012017, -REG64( EQ_0_MIB_XIMEM , RULL(0x10012417), SH_UNT_EQ_0 , +REG64( EQ_0_MIB_XIMEM , RULL(0x10012017), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012017, -REG64( EQ_1_MIB_XIMEM , RULL(0x11012417), SH_UNT_EQ_1 , +REG64( EQ_1_MIB_XIMEM , RULL(0x11012017), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012017, -REG64( EQ_2_MIB_XIMEM , RULL(0x12012417), SH_UNT_EQ_2 , +REG64( EQ_2_MIB_XIMEM , RULL(0x12012017), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012017, -REG64( EQ_3_MIB_XIMEM , RULL(0x13012417), SH_UNT_EQ_3 , +REG64( EQ_3_MIB_XIMEM , RULL(0x13012017), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012017, -REG64( EQ_4_MIB_XIMEM , RULL(0x14012417), SH_UNT_EQ_4 , +REG64( EQ_4_MIB_XIMEM , RULL(0x14012017), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012017, -REG64( EQ_5_MIB_XIMEM , RULL(0x15012417), SH_UNT_EQ_5 , +REG64( EQ_5_MIB_XIMEM , RULL(0x15012017), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012017, REG64( EX_MIB_XIMEM , RULL(0x10012017), SH_UNT_EX , SH_ACS_SCOM_RO ); REG64( EX_0_MIB_XIMEM , RULL(0x10012017), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); @@ -14163,19 +14655,19 @@ REG64( EX_9_MIB_XIMEM , RULL(0x14012417 REG64( EX_10_MIB_XIMEM , RULL(0x15012017), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); REG64( EX_11_MIB_XIMEM , RULL(0x15012417), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); -REG64( EQ_MIB_XISGB , RULL(0x10012418), SH_UNT_EQ , +REG64( EQ_MIB_XISGB , RULL(0x10012018), SH_UNT_EQ , SH_ACS_SCOM_RO ); //DUPS: 10012018, -REG64( EQ_0_MIB_XISGB , RULL(0x10012418), SH_UNT_EQ_0 , +REG64( EQ_0_MIB_XISGB , RULL(0x10012018), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); //DUPS: 10012018, -REG64( EQ_1_MIB_XISGB , RULL(0x11012418), SH_UNT_EQ_1 , +REG64( EQ_1_MIB_XISGB , RULL(0x11012018), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); //DUPS: 11012018, -REG64( EQ_2_MIB_XISGB , RULL(0x12012418), SH_UNT_EQ_2 , +REG64( EQ_2_MIB_XISGB , RULL(0x12012018), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); //DUPS: 12012018, -REG64( EQ_3_MIB_XISGB , RULL(0x13012418), SH_UNT_EQ_3 , +REG64( EQ_3_MIB_XISGB , RULL(0x13012018), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); //DUPS: 13012018, -REG64( EQ_4_MIB_XISGB , RULL(0x14012418), SH_UNT_EQ_4 , +REG64( EQ_4_MIB_XISGB , RULL(0x14012018), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); //DUPS: 14012018, -REG64( EQ_5_MIB_XISGB , RULL(0x15012418), SH_UNT_EQ_5 , +REG64( EQ_5_MIB_XISGB , RULL(0x15012018), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); //DUPS: 15012018, REG64( EX_MIB_XISGB , RULL(0x10012018), SH_UNT_EX , SH_ACS_SCOM_RO ); REG64( EX_0_MIB_XISGB , RULL(0x10012018), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); @@ -14239,7 +14731,7 @@ REG64( EX_5_MODE_REG , RULL(0x2A040008 SH_ACS_SCOM ); //DUPS: 2B040008, REG64( EX_6_MODE_REG , RULL(0x2C040008), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040008, -REG64( EX_7_MODE_REG , RULL(0x2E040008), SH_UNT_EX_7 , +REG64( EX_7_MODE_REG , RULL(0x2F040008), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040008, REG64( EX_8_MODE_REG , RULL(0x30040008), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040008, @@ -14250,19 +14742,19 @@ REG64( EX_10_MODE_REG , RULL(0x34040008 REG64( EX_11_MODE_REG , RULL(0x36040008), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37040008, -REG64( EQ_MODE_REG0 , RULL(0x1001080A), SH_UNT_EQ , +REG64( EQ_MODE_REG0 , RULL(0x10010C0A), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 1001182B, 10010C0A, 10011C2B, -REG64( EQ_0_MODE_REG0 , RULL(0x1001080A), SH_UNT_EQ_0 , +REG64( EQ_0_MODE_REG0 , RULL(0x10010C0A), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 1001182B, 10010C0A, 10011C2B, -REG64( EQ_1_MODE_REG0 , RULL(0x1101080A), SH_UNT_EQ_1 , +REG64( EQ_1_MODE_REG0 , RULL(0x11010C0A), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 1101182B, 11010C0A, 11011C2B, -REG64( EQ_2_MODE_REG0 , RULL(0x1201080A), SH_UNT_EQ_2 , +REG64( EQ_2_MODE_REG0 , RULL(0x12010C0A), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 1201182B, 12010C0A, 12011C2B, -REG64( EQ_3_MODE_REG0 , RULL(0x1301080A), SH_UNT_EQ_3 , +REG64( EQ_3_MODE_REG0 , RULL(0x13010C0A), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 1301182B, 13010C0A, 13011C2B, -REG64( EQ_4_MODE_REG0 , RULL(0x1401080A), SH_UNT_EQ_4 , +REG64( EQ_4_MODE_REG0 , RULL(0x14010C0A), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 1401182B, 14010C0A, 14011C2B, -REG64( EQ_5_MODE_REG0 , RULL(0x1501080A), SH_UNT_EQ_5 , +REG64( EQ_5_MODE_REG0 , RULL(0x15010C0A), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 1501182B, 15010C0A, 15011C2B, REG64( EX_0_L2_MODE_REG0 , RULL(0x1001080A), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_0_L3_MODE_REG0 , RULL(0x1001182B), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); @@ -14291,19 +14783,19 @@ REG64( EX_9_L3_MODE_REG0 , RULL(0x14011C2B REG64( EX_L2_MODE_REG0 , RULL(0x1001080A), SH_UNT_EX_L2 , SH_ACS_SCOM ); REG64( EX_L3_MODE_REG0 , RULL(0x1001182B), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_MODE_REG1 , RULL(0x1001080B), SH_UNT_EQ , +REG64( EQ_MODE_REG1 , RULL(0x10010C0B), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 1001180A, 10010C0B, 10011C0A, -REG64( EQ_0_MODE_REG1 , RULL(0x1001080B), SH_UNT_EQ_0 , +REG64( EQ_0_MODE_REG1 , RULL(0x10010C0B), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 1001180A, 10010C0B, 10011C0A, -REG64( EQ_1_MODE_REG1 , RULL(0x1101080B), SH_UNT_EQ_1 , +REG64( EQ_1_MODE_REG1 , RULL(0x11010C0B), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 1101180A, 11010C0B, 11011C0A, -REG64( EQ_2_MODE_REG1 , RULL(0x1201080B), SH_UNT_EQ_2 , +REG64( EQ_2_MODE_REG1 , RULL(0x12010C0B), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 1201180A, 12010C0B, 12011C0A, -REG64( EQ_3_MODE_REG1 , RULL(0x1301080B), SH_UNT_EQ_3 , +REG64( EQ_3_MODE_REG1 , RULL(0x13010C0B), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 1301180A, 13010C0B, 13011C0A, -REG64( EQ_4_MODE_REG1 , RULL(0x1401080B), SH_UNT_EQ_4 , +REG64( EQ_4_MODE_REG1 , RULL(0x14010C0B), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 1401180A, 14010C0B, 14011C0A, -REG64( EQ_5_MODE_REG1 , RULL(0x1501080B), SH_UNT_EQ_5 , +REG64( EQ_5_MODE_REG1 , RULL(0x15010C0B), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 1501180A, 15010C0B, 15011C0A, REG64( EX_0_L2_MODE_REG1 , RULL(0x1001080B), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_0_L3_MODE_REG1 , RULL(0x1001180A), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); @@ -14368,7 +14860,7 @@ REG64( EX_MULTICAST_GROUP_1 , RULL(0x200F0001 SH_ACS_SCOM ); //DUPS: 210F0001, REG64( EX_0_MULTICAST_GROUP_1 , RULL(0x200F0001), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0001, -REG64( EX_1_MULTICAST_GROUP_1 , RULL(0x230F0001), SH_UNT_EX_1 , +REG64( EX_1_MULTICAST_GROUP_1 , RULL(0x220F0001), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0001, REG64( EX_2_MULTICAST_GROUP_1 , RULL(0x240F0001), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0001, @@ -14427,7 +14919,7 @@ REG64( EX_MULTICAST_GROUP_2 , RULL(0x200F0002 SH_ACS_SCOM ); //DUPS: 210F0002, REG64( EX_0_MULTICAST_GROUP_2 , RULL(0x200F0002), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0002, -REG64( EX_1_MULTICAST_GROUP_2 , RULL(0x230F0002), SH_UNT_EX_1 , +REG64( EX_1_MULTICAST_GROUP_2 , RULL(0x220F0002), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0002, REG64( EX_2_MULTICAST_GROUP_2 , RULL(0x240F0002), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0002, @@ -14486,7 +14978,7 @@ REG64( EX_MULTICAST_GROUP_3 , RULL(0x200F0003 SH_ACS_SCOM ); //DUPS: 210F0003, REG64( EX_0_MULTICAST_GROUP_3 , RULL(0x200F0003), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0003, -REG64( EX_1_MULTICAST_GROUP_3 , RULL(0x230F0003), SH_UNT_EX_1 , +REG64( EX_1_MULTICAST_GROUP_3 , RULL(0x220F0003), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0003, REG64( EX_2_MULTICAST_GROUP_3 , RULL(0x240F0003), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0003, @@ -14545,7 +15037,7 @@ REG64( EX_MULTICAST_GROUP_4 , RULL(0x200F0004 SH_ACS_SCOM ); //DUPS: 210F0004, REG64( EX_0_MULTICAST_GROUP_4 , RULL(0x200F0004), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0004, -REG64( EX_1_MULTICAST_GROUP_4 , RULL(0x230F0004), SH_UNT_EX_1 , +REG64( EX_1_MULTICAST_GROUP_4 , RULL(0x220F0004), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0004, REG64( EX_2_MULTICAST_GROUP_4 , RULL(0x240F0004), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0004, @@ -14932,11 +15424,11 @@ REG64( EX_0_NET_CTRL0_WAND , RULL(0x200F0041 SH_ACS_SCOM1_WAND ); //DUPS: 210F0041, REG64( EX_0_NET_CTRL0_WOR , RULL(0x200F0042), SH_UNT_EX_0 , SH_ACS_SCOM2_WOR ); //DUPS: 210F0042, -REG64( EX_1_NET_CTRL0 , RULL(0x230F0040), SH_UNT_EX_1 , +REG64( EX_1_NET_CTRL0 , RULL(0x220F0040), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0040, -REG64( EX_1_NET_CTRL0_WAND , RULL(0x230F0041), SH_UNT_EX_1 , +REG64( EX_1_NET_CTRL0_WAND , RULL(0x220F0041), SH_UNT_EX_1 , SH_ACS_SCOM1_WAND ); //DUPS: 220F0041, -REG64( EX_1_NET_CTRL0_WOR , RULL(0x230F0042), SH_UNT_EX_1 , +REG64( EX_1_NET_CTRL0_WOR , RULL(0x220F0042), SH_UNT_EX_1 , SH_ACS_SCOM2_WOR ); //DUPS: 220F0042, REG64( EX_2_NET_CTRL0 , RULL(0x240F0040), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0040, @@ -15139,11 +15631,11 @@ REG64( EX_0_NET_CTRL1_WAND , RULL(0x200F0045 SH_ACS_SCOM1_WAND ); //DUPS: 210F0045, REG64( EX_0_NET_CTRL1_WOR , RULL(0x200F0046), SH_UNT_EX_0 , SH_ACS_SCOM2_WOR ); //DUPS: 210F0046, -REG64( EX_1_NET_CTRL1 , RULL(0x230F0044), SH_UNT_EX_1 , +REG64( EX_1_NET_CTRL1 , RULL(0x220F0044), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0044, -REG64( EX_1_NET_CTRL1_WAND , RULL(0x230F0045), SH_UNT_EX_1 , +REG64( EX_1_NET_CTRL1_WAND , RULL(0x220F0045), SH_UNT_EX_1 , SH_ACS_SCOM1_WAND ); //DUPS: 220F0045, -REG64( EX_1_NET_CTRL1_WOR , RULL(0x230F0046), SH_UNT_EX_1 , +REG64( EX_1_NET_CTRL1_WOR , RULL(0x220F0046), SH_UNT_EX_1 , SH_ACS_SCOM2_WOR ); //DUPS: 220F0046, REG64( EX_2_NET_CTRL1 , RULL(0x240F0044), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0044, @@ -15231,19 +15723,19 @@ REG64( C_20_OCC_SCOMC , RULL(0x34010A82 REG64( C_21_OCC_SCOMC , RULL(0x35010A82), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_OCC_SCOMC , RULL(0x36010A82), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_OCC_SCOMC , RULL(0x37010A82), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_OCC_SCOMC , RULL(0x21010A82), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_OCC_SCOMC , RULL(0x20010A82), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A82, -REG64( EX_10_L2_OCC_SCOMC , RULL(0x35010A82), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_OCC_SCOMC , RULL(0x34010A82), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010A82, -REG64( EX_11_L2_OCC_SCOMC , RULL(0x37010A82), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_OCC_SCOMC , RULL(0x36010A82), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010A82, -REG64( EX_1_L2_OCC_SCOMC , RULL(0x23010A82), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_OCC_SCOMC , RULL(0x22010A82), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010A82, -REG64( EX_2_L2_OCC_SCOMC , RULL(0x25010A82), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_OCC_SCOMC , RULL(0x24010A82), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010A82, -REG64( EX_3_L2_OCC_SCOMC , RULL(0x27010A82), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_OCC_SCOMC , RULL(0x26010A82), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010A82, -REG64( EX_4_L2_OCC_SCOMC , RULL(0x29010A82), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_OCC_SCOMC , RULL(0x28010A82), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010A82, REG64( EX_5_L2_OCC_SCOMC , RULL(0x2B010A82), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010A82, @@ -15251,13 +15743,65 @@ REG64( EX_6_L2_OCC_SCOMC , RULL(0x2D010A82 SH_ACS_SCOM_RW ); //DUPS: 2C010A82, REG64( EX_7_L2_OCC_SCOMC , RULL(0x2F010A82), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010A82, -REG64( EX_8_L2_OCC_SCOMC , RULL(0x31010A82), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_OCC_SCOMC , RULL(0x30010A82), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010A82, -REG64( EX_9_L2_OCC_SCOMC , RULL(0x33010A82), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_OCC_SCOMC , RULL(0x32010A82), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010A82, -REG64( EX_L2_OCC_SCOMC , RULL(0x21010A82), SH_UNT_EX_L2 , +REG64( EX_L2_OCC_SCOMC , RULL(0x20010A82), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A82, +REG64( C_OCC_SCOMD , RULL(0x20010A83), SH_UNT_C , SH_ACS_SCOM_RW ); +REG64( C_0_OCC_SCOMD , RULL(0x20010A83), SH_UNT_C_0 , SH_ACS_SCOM_RW ); +REG64( C_1_OCC_SCOMD , RULL(0x21010A83), SH_UNT_C_1 , SH_ACS_SCOM_RW ); +REG64( C_2_OCC_SCOMD , RULL(0x22010A83), SH_UNT_C_2 , SH_ACS_SCOM_RW ); +REG64( C_3_OCC_SCOMD , RULL(0x23010A83), SH_UNT_C_3 , SH_ACS_SCOM_RW ); +REG64( C_4_OCC_SCOMD , RULL(0x24010A83), SH_UNT_C_4 , SH_ACS_SCOM_RW ); +REG64( C_5_OCC_SCOMD , RULL(0x25010A83), SH_UNT_C_5 , SH_ACS_SCOM_RW ); +REG64( C_6_OCC_SCOMD , RULL(0x26010A83), SH_UNT_C_6 , SH_ACS_SCOM_RW ); +REG64( C_7_OCC_SCOMD , RULL(0x27010A83), SH_UNT_C_7 , SH_ACS_SCOM_RW ); +REG64( C_8_OCC_SCOMD , RULL(0x28010A83), SH_UNT_C_8 , SH_ACS_SCOM_RW ); +REG64( C_9_OCC_SCOMD , RULL(0x29010A83), SH_UNT_C_9 , SH_ACS_SCOM_RW ); +REG64( C_10_OCC_SCOMD , RULL(0x2A010A83), SH_UNT_C_10 , SH_ACS_SCOM_RW ); +REG64( C_11_OCC_SCOMD , RULL(0x2B010A83), SH_UNT_C_11 , SH_ACS_SCOM_RW ); +REG64( C_12_OCC_SCOMD , RULL(0x2C010A83), SH_UNT_C_12 , SH_ACS_SCOM_RW ); +REG64( C_13_OCC_SCOMD , RULL(0x2D010A83), SH_UNT_C_13 , SH_ACS_SCOM_RW ); +REG64( C_14_OCC_SCOMD , RULL(0x2E010A83), SH_UNT_C_14 , SH_ACS_SCOM_RW ); +REG64( C_15_OCC_SCOMD , RULL(0x2F010A83), SH_UNT_C_15 , SH_ACS_SCOM_RW ); +REG64( C_16_OCC_SCOMD , RULL(0x30010A83), SH_UNT_C_16 , SH_ACS_SCOM_RW ); +REG64( C_17_OCC_SCOMD , RULL(0x31010A83), SH_UNT_C_17 , SH_ACS_SCOM_RW ); +REG64( C_18_OCC_SCOMD , RULL(0x32010A83), SH_UNT_C_18 , SH_ACS_SCOM_RW ); +REG64( C_19_OCC_SCOMD , RULL(0x33010A83), SH_UNT_C_19 , SH_ACS_SCOM_RW ); +REG64( C_20_OCC_SCOMD , RULL(0x34010A83), SH_UNT_C_20 , SH_ACS_SCOM_RW ); +REG64( C_21_OCC_SCOMD , RULL(0x35010A83), SH_UNT_C_21 , SH_ACS_SCOM_RW ); +REG64( C_22_OCC_SCOMD , RULL(0x36010A83), SH_UNT_C_22 , SH_ACS_SCOM_RW ); +REG64( C_23_OCC_SCOMD , RULL(0x37010A83), SH_UNT_C_23 , SH_ACS_SCOM_RW ); +REG64( EX_0_L2_OCC_SCOMD , RULL(0x20010A83), SH_UNT_EX_0_L2 , + SH_ACS_SCOM_RW ); //DUPS: 20010A83, +REG64( EX_10_L2_OCC_SCOMD , RULL(0x34010A83), SH_UNT_EX_10_L2 , + SH_ACS_SCOM_RW ); //DUPS: 34010A83, +REG64( EX_11_L2_OCC_SCOMD , RULL(0x36010A83), SH_UNT_EX_11_L2 , + SH_ACS_SCOM_RW ); //DUPS: 36010A83, +REG64( EX_1_L2_OCC_SCOMD , RULL(0x22010A83), SH_UNT_EX_1_L2 , + SH_ACS_SCOM_RW ); //DUPS: 22010A83, +REG64( EX_2_L2_OCC_SCOMD , RULL(0x24010A83), SH_UNT_EX_2_L2 , + SH_ACS_SCOM_RW ); //DUPS: 24010A83, +REG64( EX_3_L2_OCC_SCOMD , RULL(0x26010A83), SH_UNT_EX_3_L2 , + SH_ACS_SCOM_RW ); //DUPS: 26010A83, +REG64( EX_4_L2_OCC_SCOMD , RULL(0x28010A83), SH_UNT_EX_4_L2 , + SH_ACS_SCOM_RW ); //DUPS: 28010A83, +REG64( EX_5_L2_OCC_SCOMD , RULL(0x2B010A83), SH_UNT_EX_5_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2A010A83, +REG64( EX_6_L2_OCC_SCOMD , RULL(0x2D010A83), SH_UNT_EX_6_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2C010A83, +REG64( EX_7_L2_OCC_SCOMD , RULL(0x2F010A83), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2E010A83, +REG64( EX_8_L2_OCC_SCOMD , RULL(0x30010A83), SH_UNT_EX_8_L2 , + SH_ACS_SCOM_RW ); //DUPS: 30010A83, +REG64( EX_9_L2_OCC_SCOMD , RULL(0x32010A83), SH_UNT_EX_9_L2 , + SH_ACS_SCOM_RW ); //DUPS: 32010A83, +REG64( EX_L2_OCC_SCOMD , RULL(0x20010A83), SH_UNT_EX_L2 , + SH_ACS_SCOM_RW ); //DUPS: 20010A83, + REG64( C_OPCG_ALIGN , RULL(0x20030001), SH_UNT_C , SH_ACS_SCOM ); REG64( C_0_OPCG_ALIGN , RULL(0x20030001), SH_UNT_C_0 , SH_ACS_SCOM ); REG64( C_1_OPCG_ALIGN , RULL(0x21030001), SH_UNT_C_1 , SH_ACS_SCOM ); @@ -15306,7 +15850,7 @@ REG64( EX_5_OPCG_ALIGN , RULL(0x2A030001 SH_ACS_SCOM ); //DUPS: 2B030001, REG64( EX_6_OPCG_ALIGN , RULL(0x2C030001), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030001, -REG64( EX_7_OPCG_ALIGN , RULL(0x2E030001), SH_UNT_EX_7 , +REG64( EX_7_OPCG_ALIGN , RULL(0x2F030001), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030001, REG64( EX_8_OPCG_ALIGN , RULL(0x30030001), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030001, @@ -15365,7 +15909,7 @@ REG64( EX_5_OPCG_CAPT1 , RULL(0x2A030010 SH_ACS_SCOM ); //DUPS: 2B030010, REG64( EX_6_OPCG_CAPT1 , RULL(0x2C030010), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030010, -REG64( EX_7_OPCG_CAPT1 , RULL(0x2E030010), SH_UNT_EX_7 , +REG64( EX_7_OPCG_CAPT1 , RULL(0x2F030010), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030010, REG64( EX_8_OPCG_CAPT1 , RULL(0x30030010), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030010, @@ -15424,7 +15968,7 @@ REG64( EX_5_OPCG_CAPT2 , RULL(0x2A030011 SH_ACS_SCOM ); //DUPS: 2B030011, REG64( EX_6_OPCG_CAPT2 , RULL(0x2C030011), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030011, -REG64( EX_7_OPCG_CAPT2 , RULL(0x2E030011), SH_UNT_EX_7 , +REG64( EX_7_OPCG_CAPT2 , RULL(0x2F030011), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030011, REG64( EX_8_OPCG_CAPT2 , RULL(0x30030011), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030011, @@ -15483,7 +16027,7 @@ REG64( EX_5_OPCG_CAPT3 , RULL(0x2A030012 SH_ACS_SCOM ); //DUPS: 2B030012, REG64( EX_6_OPCG_CAPT3 , RULL(0x2C030012), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030012, -REG64( EX_7_OPCG_CAPT3 , RULL(0x2E030012), SH_UNT_EX_7 , +REG64( EX_7_OPCG_CAPT3 , RULL(0x2F030012), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030012, REG64( EX_8_OPCG_CAPT3 , RULL(0x30030012), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030012, @@ -15542,7 +16086,7 @@ REG64( EX_5_OPCG_REG0 , RULL(0x2A030002 SH_ACS_SCOM ); //DUPS: 2B030002, REG64( EX_6_OPCG_REG0 , RULL(0x2C030002), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030002, -REG64( EX_7_OPCG_REG0 , RULL(0x2E030002), SH_UNT_EX_7 , +REG64( EX_7_OPCG_REG0 , RULL(0x2F030002), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030002, REG64( EX_8_OPCG_REG0 , RULL(0x30030002), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030002, @@ -15601,7 +16145,7 @@ REG64( EX_5_OPCG_REG1 , RULL(0x2A030003 SH_ACS_SCOM ); //DUPS: 2B030003, REG64( EX_6_OPCG_REG1 , RULL(0x2C030003), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030003, -REG64( EX_7_OPCG_REG1 , RULL(0x2E030003), SH_UNT_EX_7 , +REG64( EX_7_OPCG_REG1 , RULL(0x2F030003), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030003, REG64( EX_8_OPCG_REG1 , RULL(0x30030003), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030003, @@ -15660,7 +16204,7 @@ REG64( EX_5_OPCG_REG2 , RULL(0x2A030004 SH_ACS_SCOM ); //DUPS: 2B030004, REG64( EX_6_OPCG_REG2 , RULL(0x2C030004), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030004, -REG64( EX_7_OPCG_REG2 , RULL(0x2E030004), SH_UNT_EX_7 , +REG64( EX_7_OPCG_REG2 , RULL(0x2F030004), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030004, REG64( EX_8_OPCG_REG2 , RULL(0x30030004), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030004, @@ -15671,19 +16215,19 @@ REG64( EX_10_OPCG_REG2 , RULL(0x34030004 REG64( EX_11_OPCG_REG2 , RULL(0x36030004), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37030004, -REG64( EQ_PHYP_PURGE_CMD_REG , RULL(0x1001080F), SH_UNT_EQ , +REG64( EQ_PHYP_PURGE_CMD_REG , RULL(0x10010C0F), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C0F, -REG64( EQ_0_PHYP_PURGE_CMD_REG , RULL(0x1001080F), SH_UNT_EQ_0 , +REG64( EQ_0_PHYP_PURGE_CMD_REG , RULL(0x10010C0F), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C0F, -REG64( EQ_1_PHYP_PURGE_CMD_REG , RULL(0x1101080F), SH_UNT_EQ_1 , +REG64( EQ_1_PHYP_PURGE_CMD_REG , RULL(0x11010C0F), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C0F, -REG64( EQ_2_PHYP_PURGE_CMD_REG , RULL(0x1201080F), SH_UNT_EQ_2 , +REG64( EQ_2_PHYP_PURGE_CMD_REG , RULL(0x12010C0F), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C0F, -REG64( EQ_3_PHYP_PURGE_CMD_REG , RULL(0x1301080F), SH_UNT_EQ_3 , +REG64( EQ_3_PHYP_PURGE_CMD_REG , RULL(0x13010C0F), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C0F, -REG64( EQ_4_PHYP_PURGE_CMD_REG , RULL(0x1401080F), SH_UNT_EQ_4 , +REG64( EQ_4_PHYP_PURGE_CMD_REG , RULL(0x14010C0F), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C0F, -REG64( EQ_5_PHYP_PURGE_CMD_REG , RULL(0x1501080F), SH_UNT_EQ_5 , +REG64( EQ_5_PHYP_PURGE_CMD_REG , RULL(0x15010C0F), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C0F, REG64( EX_PHYP_PURGE_CMD_REG , RULL(0x1001080F), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PHYP_PURGE_CMD_REG , RULL(0x1001080F), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -15699,19 +16243,19 @@ REG64( EX_9_PHYP_PURGE_CMD_REG , RULL(0x14010C0F REG64( EX_10_PHYP_PURGE_CMD_REG , RULL(0x1501080F), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_PHYP_PURGE_CMD_REG , RULL(0x15010C0F), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_PHYP_PURGE_REG , RULL(0x10011814), SH_UNT_EQ , +REG64( EQ_PHYP_PURGE_REG , RULL(0x10011C14), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C14, -REG64( EQ_0_PHYP_PURGE_REG , RULL(0x10011814), SH_UNT_EQ_0 , +REG64( EQ_0_PHYP_PURGE_REG , RULL(0x10011C14), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C14, -REG64( EQ_1_PHYP_PURGE_REG , RULL(0x11011814), SH_UNT_EQ_1 , +REG64( EQ_1_PHYP_PURGE_REG , RULL(0x11011C14), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C14, -REG64( EQ_2_PHYP_PURGE_REG , RULL(0x12011814), SH_UNT_EQ_2 , +REG64( EQ_2_PHYP_PURGE_REG , RULL(0x12011C14), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C14, -REG64( EQ_3_PHYP_PURGE_REG , RULL(0x13011814), SH_UNT_EQ_3 , +REG64( EQ_3_PHYP_PURGE_REG , RULL(0x13011C14), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C14, -REG64( EQ_4_PHYP_PURGE_REG , RULL(0x14011814), SH_UNT_EQ_4 , +REG64( EQ_4_PHYP_PURGE_REG , RULL(0x14011C14), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C14, -REG64( EQ_5_PHYP_PURGE_REG , RULL(0x15011814), SH_UNT_EQ_5 , +REG64( EQ_5_PHYP_PURGE_REG , RULL(0x15011C14), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C14, REG64( EX_0_L3_PHYP_PURGE_REG , RULL(0x10011814), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_PHYP_PURGE_REG , RULL(0x15011814), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -15763,7 +16307,7 @@ REG64( EX_PLL_LOCK_REG , RULL(0x200F0019 SH_ACS_SCOM ); //DUPS: 210F0019, REG64( EX_0_PLL_LOCK_REG , RULL(0x200F0019), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0019, -REG64( EX_1_PLL_LOCK_REG , RULL(0x230F0019), SH_UNT_EX_1 , +REG64( EX_1_PLL_LOCK_REG , RULL(0x220F0019), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0019, REG64( EX_2_PLL_LOCK_REG , RULL(0x240F0019), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0019, @@ -15829,7 +16373,7 @@ REG64( EX_5_L2_PMU_HOLD_OUT , RULL(0x2A010AB6 SH_ACS_SCOM ); //DUPS: 2B010AB6, REG64( EX_6_L2_PMU_HOLD_OUT , RULL(0x2C010AB6), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010AB6, -REG64( EX_7_L2_PMU_HOLD_OUT , RULL(0x2E010AB6), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_PMU_HOLD_OUT , RULL(0x2F010AB6), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010AB6, REG64( EX_8_L2_PMU_HOLD_OUT , RULL(0x30010AB6), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010AB6, @@ -15881,7 +16425,7 @@ REG64( EX_5_L2_PMU_SCOMC , RULL(0x2A010AB0 SH_ACS_SCOM_RW ); //DUPS: 2B010AB0, REG64( EX_6_L2_PMU_SCOMC , RULL(0x2C010AB0), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010AB0, -REG64( EX_7_L2_PMU_SCOMC , RULL(0x2E010AB0), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_PMU_SCOMC , RULL(0x2F010AB0), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010AB0, REG64( EX_8_L2_PMU_SCOMC , RULL(0x30010AB0), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010AB0, @@ -15933,7 +16477,7 @@ REG64( EX_5_L2_PMU_SCOMC_EN , RULL(0x2A010AB2 SH_ACS_SCOM_RW ); //DUPS: 2B010AB2, REG64( EX_6_L2_PMU_SCOMC_EN , RULL(0x2C010AB2), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010AB2, -REG64( EX_7_L2_PMU_SCOMC_EN , RULL(0x2E010AB2), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_PMU_SCOMC_EN , RULL(0x2F010AB2), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010AB2, REG64( EX_8_L2_PMU_SCOMC_EN , RULL(0x30010AB2), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010AB2, @@ -15942,19 +16486,19 @@ REG64( EX_9_L2_PMU_SCOMC_EN , RULL(0x32010AB2 REG64( EX_L2_PMU_SCOMC_EN , RULL(0x20010AB2), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 21010AB2, -REG64( EQ_PM_L2_RCMD_DIS_REG , RULL(0x10011818), SH_UNT_EQ , +REG64( EQ_PM_L2_RCMD_DIS_REG , RULL(0x10011C18), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C18, -REG64( EQ_0_PM_L2_RCMD_DIS_REG , RULL(0x10011818), SH_UNT_EQ_0 , +REG64( EQ_0_PM_L2_RCMD_DIS_REG , RULL(0x10011C18), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C18, -REG64( EQ_1_PM_L2_RCMD_DIS_REG , RULL(0x11011818), SH_UNT_EQ_1 , +REG64( EQ_1_PM_L2_RCMD_DIS_REG , RULL(0x11011C18), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C18, -REG64( EQ_2_PM_L2_RCMD_DIS_REG , RULL(0x12011818), SH_UNT_EQ_2 , +REG64( EQ_2_PM_L2_RCMD_DIS_REG , RULL(0x12011C18), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C18, -REG64( EQ_3_PM_L2_RCMD_DIS_REG , RULL(0x13011818), SH_UNT_EQ_3 , +REG64( EQ_3_PM_L2_RCMD_DIS_REG , RULL(0x13011C18), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C18, -REG64( EQ_4_PM_L2_RCMD_DIS_REG , RULL(0x14011818), SH_UNT_EQ_4 , +REG64( EQ_4_PM_L2_RCMD_DIS_REG , RULL(0x14011C18), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C18, -REG64( EQ_5_PM_L2_RCMD_DIS_REG , RULL(0x15011818), SH_UNT_EQ_5 , +REG64( EQ_5_PM_L2_RCMD_DIS_REG , RULL(0x15011C18), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C18, REG64( EX_PM_L2_RCMD_DIS_REG , RULL(0x10011818), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PM_L2_RCMD_DIS_REG , RULL(0x10011818), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -15970,19 +16514,19 @@ REG64( EX_9_PM_L2_RCMD_DIS_REG , RULL(0x14011C18 REG64( EX_10_PM_L2_RCMD_DIS_REG , RULL(0x15011818), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_PM_L2_RCMD_DIS_REG , RULL(0x15011C18), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_PM_LCO_DIS_REG , RULL(0x10011816), SH_UNT_EQ , +REG64( EQ_PM_LCO_DIS_REG , RULL(0x10011C16), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C16, -REG64( EQ_0_PM_LCO_DIS_REG , RULL(0x10011816), SH_UNT_EQ_0 , +REG64( EQ_0_PM_LCO_DIS_REG , RULL(0x10011C16), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C16, -REG64( EQ_1_PM_LCO_DIS_REG , RULL(0x11011816), SH_UNT_EQ_1 , +REG64( EQ_1_PM_LCO_DIS_REG , RULL(0x11011C16), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C16, -REG64( EQ_2_PM_LCO_DIS_REG , RULL(0x12011816), SH_UNT_EQ_2 , +REG64( EQ_2_PM_LCO_DIS_REG , RULL(0x12011C16), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C16, -REG64( EQ_3_PM_LCO_DIS_REG , RULL(0x13011816), SH_UNT_EQ_3 , +REG64( EQ_3_PM_LCO_DIS_REG , RULL(0x13011C16), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C16, -REG64( EQ_4_PM_LCO_DIS_REG , RULL(0x14011816), SH_UNT_EQ_4 , +REG64( EQ_4_PM_LCO_DIS_REG , RULL(0x14011C16), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C16, -REG64( EQ_5_PM_LCO_DIS_REG , RULL(0x15011816), SH_UNT_EQ_5 , +REG64( EQ_5_PM_LCO_DIS_REG , RULL(0x15011C16), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C16, REG64( EX_0_L3_PM_LCO_DIS_REG , RULL(0x10011816), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_PM_LCO_DIS_REG , RULL(0x15011816), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -15998,19 +16542,19 @@ REG64( EX_8_L3_PM_LCO_DIS_REG , RULL(0x14011816 REG64( EX_9_L3_PM_LCO_DIS_REG , RULL(0x14011C16), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_PM_LCO_DIS_REG , RULL(0x10011816), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_PM_PURGE_REG , RULL(0x10011813), SH_UNT_EQ , +REG64( EQ_PM_PURGE_REG , RULL(0x10011C13), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C13, -REG64( EQ_0_PM_PURGE_REG , RULL(0x10011813), SH_UNT_EQ_0 , +REG64( EQ_0_PM_PURGE_REG , RULL(0x10011C13), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C13, -REG64( EQ_1_PM_PURGE_REG , RULL(0x11011813), SH_UNT_EQ_1 , +REG64( EQ_1_PM_PURGE_REG , RULL(0x11011C13), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C13, -REG64( EQ_2_PM_PURGE_REG , RULL(0x12011813), SH_UNT_EQ_2 , +REG64( EQ_2_PM_PURGE_REG , RULL(0x12011C13), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C13, -REG64( EQ_3_PM_PURGE_REG , RULL(0x13011813), SH_UNT_EQ_3 , +REG64( EQ_3_PM_PURGE_REG , RULL(0x13011C13), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C13, -REG64( EQ_4_PM_PURGE_REG , RULL(0x14011813), SH_UNT_EQ_4 , +REG64( EQ_4_PM_PURGE_REG , RULL(0x14011C13), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C13, -REG64( EQ_5_PM_PURGE_REG , RULL(0x15011813), SH_UNT_EQ_5 , +REG64( EQ_5_PM_PURGE_REG , RULL(0x15011C13), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C13, REG64( EX_0_L3_PM_PURGE_REG , RULL(0x10011813), SH_UNT_EX_0_L3 , SH_ACS_SCOM ); REG64( EX_10_L3_PM_PURGE_REG , RULL(0x15011813), SH_UNT_EX_10_L3 , SH_ACS_SCOM ); @@ -16026,19 +16570,19 @@ REG64( EX_8_L3_PM_PURGE_REG , RULL(0x14011813 REG64( EX_9_L3_PM_PURGE_REG , RULL(0x14011C13), SH_UNT_EX_9_L3 , SH_ACS_SCOM ); REG64( EX_L3_PM_PURGE_REG , RULL(0x10011813), SH_UNT_EX_L3 , SH_ACS_SCOM ); -REG64( EQ_PPE_XIDBGPRO , RULL(0x10012415), SH_UNT_EQ , +REG64( EQ_PPE_XIDBGPRO , RULL(0x10012015), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10012015, -REG64( EQ_0_PPE_XIDBGPRO , RULL(0x10012415), SH_UNT_EQ_0 , +REG64( EQ_0_PPE_XIDBGPRO , RULL(0x10012015), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10012015, -REG64( EQ_1_PPE_XIDBGPRO , RULL(0x11012415), SH_UNT_EQ_1 , +REG64( EQ_1_PPE_XIDBGPRO , RULL(0x11012015), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11012015, -REG64( EQ_2_PPE_XIDBGPRO , RULL(0x12012415), SH_UNT_EQ_2 , +REG64( EQ_2_PPE_XIDBGPRO , RULL(0x12012015), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12012015, -REG64( EQ_3_PPE_XIDBGPRO , RULL(0x13012415), SH_UNT_EQ_3 , +REG64( EQ_3_PPE_XIDBGPRO , RULL(0x13012015), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13012015, -REG64( EQ_4_PPE_XIDBGPRO , RULL(0x14012415), SH_UNT_EQ_4 , +REG64( EQ_4_PPE_XIDBGPRO , RULL(0x14012015), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14012015, -REG64( EQ_5_PPE_XIDBGPRO , RULL(0x15012415), SH_UNT_EQ_5 , +REG64( EQ_5_PPE_XIDBGPRO , RULL(0x15012015), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15012015, REG64( EX_PPE_XIDBGPRO , RULL(0x10012015), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PPE_XIDBGPRO , RULL(0x10012015), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -16054,19 +16598,19 @@ REG64( EX_9_PPE_XIDBGPRO , RULL(0x14012415 REG64( EX_10_PPE_XIDBGPRO , RULL(0x15012015), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_PPE_XIDBGPRO , RULL(0x15012415), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_PPE_XIRAMDBG , RULL(0x10012413), SH_UNT_EQ , +REG64( EQ_PPE_XIRAMDBG , RULL(0x10012013), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10012013, -REG64( EQ_0_PPE_XIRAMDBG , RULL(0x10012413), SH_UNT_EQ_0 , +REG64( EQ_0_PPE_XIRAMDBG , RULL(0x10012013), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10012013, -REG64( EQ_1_PPE_XIRAMDBG , RULL(0x11012413), SH_UNT_EQ_1 , +REG64( EQ_1_PPE_XIRAMDBG , RULL(0x11012013), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11012013, -REG64( EQ_2_PPE_XIRAMDBG , RULL(0x12012413), SH_UNT_EQ_2 , +REG64( EQ_2_PPE_XIRAMDBG , RULL(0x12012013), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12012013, -REG64( EQ_3_PPE_XIRAMDBG , RULL(0x13012413), SH_UNT_EQ_3 , +REG64( EQ_3_PPE_XIRAMDBG , RULL(0x13012013), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13012013, -REG64( EQ_4_PPE_XIRAMDBG , RULL(0x14012413), SH_UNT_EQ_4 , +REG64( EQ_4_PPE_XIRAMDBG , RULL(0x14012013), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14012013, -REG64( EQ_5_PPE_XIRAMDBG , RULL(0x15012413), SH_UNT_EQ_5 , +REG64( EQ_5_PPE_XIRAMDBG , RULL(0x15012013), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15012013, REG64( EX_PPE_XIRAMDBG , RULL(0x10012013), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PPE_XIRAMDBG , RULL(0x10012013), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -16082,19 +16626,19 @@ REG64( EX_9_PPE_XIRAMDBG , RULL(0x14012413 REG64( EX_10_PPE_XIRAMDBG , RULL(0x15012013), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_PPE_XIRAMDBG , RULL(0x15012413), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_PPE_XIRAMEDR , RULL(0x10012414), SH_UNT_EQ , +REG64( EQ_PPE_XIRAMEDR , RULL(0x10012014), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10012014, -REG64( EQ_0_PPE_XIRAMEDR , RULL(0x10012414), SH_UNT_EQ_0 , +REG64( EQ_0_PPE_XIRAMEDR , RULL(0x10012014), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10012014, -REG64( EQ_1_PPE_XIRAMEDR , RULL(0x11012414), SH_UNT_EQ_1 , +REG64( EQ_1_PPE_XIRAMEDR , RULL(0x11012014), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11012014, -REG64( EQ_2_PPE_XIRAMEDR , RULL(0x12012414), SH_UNT_EQ_2 , +REG64( EQ_2_PPE_XIRAMEDR , RULL(0x12012014), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12012014, -REG64( EQ_3_PPE_XIRAMEDR , RULL(0x13012414), SH_UNT_EQ_3 , +REG64( EQ_3_PPE_XIRAMEDR , RULL(0x13012014), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13012014, -REG64( EQ_4_PPE_XIRAMEDR , RULL(0x14012414), SH_UNT_EQ_4 , +REG64( EQ_4_PPE_XIRAMEDR , RULL(0x14012014), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14012014, -REG64( EQ_5_PPE_XIRAMEDR , RULL(0x15012414), SH_UNT_EQ_5 , +REG64( EQ_5_PPE_XIRAMEDR , RULL(0x15012014), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15012014, REG64( EX_PPE_XIRAMEDR , RULL(0x10012014), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PPE_XIRAMEDR , RULL(0x10012014), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -16110,19 +16654,19 @@ REG64( EX_9_PPE_XIRAMEDR , RULL(0x14012414 REG64( EX_10_PPE_XIRAMEDR , RULL(0x15012014), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_PPE_XIRAMEDR , RULL(0x15012414), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_PPE_XIRAMGA , RULL(0x10012412), SH_UNT_EQ , +REG64( EQ_PPE_XIRAMGA , RULL(0x10012012), SH_UNT_EQ , SH_ACS_SCOM_WO ); //DUPS: 10012012, -REG64( EQ_0_PPE_XIRAMGA , RULL(0x10012412), SH_UNT_EQ_0 , +REG64( EQ_0_PPE_XIRAMGA , RULL(0x10012012), SH_UNT_EQ_0 , SH_ACS_SCOM_WO ); //DUPS: 10012012, -REG64( EQ_1_PPE_XIRAMGA , RULL(0x11012412), SH_UNT_EQ_1 , +REG64( EQ_1_PPE_XIRAMGA , RULL(0x11012012), SH_UNT_EQ_1 , SH_ACS_SCOM_WO ); //DUPS: 11012012, -REG64( EQ_2_PPE_XIRAMGA , RULL(0x12012412), SH_UNT_EQ_2 , +REG64( EQ_2_PPE_XIRAMGA , RULL(0x12012012), SH_UNT_EQ_2 , SH_ACS_SCOM_WO ); //DUPS: 12012012, -REG64( EQ_3_PPE_XIRAMGA , RULL(0x13012412), SH_UNT_EQ_3 , +REG64( EQ_3_PPE_XIRAMGA , RULL(0x13012012), SH_UNT_EQ_3 , SH_ACS_SCOM_WO ); //DUPS: 13012012, -REG64( EQ_4_PPE_XIRAMGA , RULL(0x14012412), SH_UNT_EQ_4 , +REG64( EQ_4_PPE_XIRAMGA , RULL(0x14012012), SH_UNT_EQ_4 , SH_ACS_SCOM_WO ); //DUPS: 14012012, -REG64( EQ_5_PPE_XIRAMGA , RULL(0x15012412), SH_UNT_EQ_5 , +REG64( EQ_5_PPE_XIRAMGA , RULL(0x15012012), SH_UNT_EQ_5 , SH_ACS_SCOM_WO ); //DUPS: 15012012, REG64( EX_PPE_XIRAMGA , RULL(0x10012012), SH_UNT_EX , SH_ACS_SCOM_WO ); REG64( EX_0_PPE_XIRAMGA , RULL(0x10012012), SH_UNT_EX_0 , SH_ACS_SCOM_WO ); @@ -16138,19 +16682,19 @@ REG64( EX_9_PPE_XIRAMGA , RULL(0x14012412 REG64( EX_10_PPE_XIRAMGA , RULL(0x15012012), SH_UNT_EX_10 , SH_ACS_SCOM_WO ); REG64( EX_11_PPE_XIRAMGA , RULL(0x15012412), SH_UNT_EX_11 , SH_ACS_SCOM_WO ); -REG64( EQ_PPE_XIRAMRA , RULL(0x10012411), SH_UNT_EQ , +REG64( EQ_PPE_XIRAMRA , RULL(0x10012011), SH_UNT_EQ , SH_ACS_SCOM_WO ); //DUPS: 10012011, -REG64( EQ_0_PPE_XIRAMRA , RULL(0x10012411), SH_UNT_EQ_0 , +REG64( EQ_0_PPE_XIRAMRA , RULL(0x10012011), SH_UNT_EQ_0 , SH_ACS_SCOM_WO ); //DUPS: 10012011, -REG64( EQ_1_PPE_XIRAMRA , RULL(0x11012411), SH_UNT_EQ_1 , +REG64( EQ_1_PPE_XIRAMRA , RULL(0x11012011), SH_UNT_EQ_1 , SH_ACS_SCOM_WO ); //DUPS: 11012011, -REG64( EQ_2_PPE_XIRAMRA , RULL(0x12012411), SH_UNT_EQ_2 , +REG64( EQ_2_PPE_XIRAMRA , RULL(0x12012011), SH_UNT_EQ_2 , SH_ACS_SCOM_WO ); //DUPS: 12012011, -REG64( EQ_3_PPE_XIRAMRA , RULL(0x13012411), SH_UNT_EQ_3 , +REG64( EQ_3_PPE_XIRAMRA , RULL(0x13012011), SH_UNT_EQ_3 , SH_ACS_SCOM_WO ); //DUPS: 13012011, -REG64( EQ_4_PPE_XIRAMRA , RULL(0x14012411), SH_UNT_EQ_4 , +REG64( EQ_4_PPE_XIRAMRA , RULL(0x14012011), SH_UNT_EQ_4 , SH_ACS_SCOM_WO ); //DUPS: 14012011, -REG64( EQ_5_PPE_XIRAMRA , RULL(0x15012411), SH_UNT_EQ_5 , +REG64( EQ_5_PPE_XIRAMRA , RULL(0x15012011), SH_UNT_EQ_5 , SH_ACS_SCOM_WO ); //DUPS: 15012011, REG64( EX_PPE_XIRAMRA , RULL(0x10012011), SH_UNT_EX , SH_ACS_SCOM_WO ); REG64( EX_0_PPE_XIRAMRA , RULL(0x10012011), SH_UNT_EX_0 , SH_ACS_SCOM_WO ); @@ -16166,19 +16710,19 @@ REG64( EX_9_PPE_XIRAMRA , RULL(0x14012411 REG64( EX_10_PPE_XIRAMRA , RULL(0x15012011), SH_UNT_EX_10 , SH_ACS_SCOM_WO ); REG64( EX_11_PPE_XIRAMRA , RULL(0x15012411), SH_UNT_EX_11 , SH_ACS_SCOM_WO ); -REG64( EQ_PPE_XIXCR , RULL(0x10012410), SH_UNT_EQ , +REG64( EQ_PPE_XIXCR , RULL(0x10012010), SH_UNT_EQ , SH_ACS_SCOM_WO ); //DUPS: 10012010, -REG64( EQ_0_PPE_XIXCR , RULL(0x10012410), SH_UNT_EQ_0 , +REG64( EQ_0_PPE_XIXCR , RULL(0x10012010), SH_UNT_EQ_0 , SH_ACS_SCOM_WO ); //DUPS: 10012010, -REG64( EQ_1_PPE_XIXCR , RULL(0x11012410), SH_UNT_EQ_1 , +REG64( EQ_1_PPE_XIXCR , RULL(0x11012010), SH_UNT_EQ_1 , SH_ACS_SCOM_WO ); //DUPS: 11012010, -REG64( EQ_2_PPE_XIXCR , RULL(0x12012410), SH_UNT_EQ_2 , +REG64( EQ_2_PPE_XIXCR , RULL(0x12012010), SH_UNT_EQ_2 , SH_ACS_SCOM_WO ); //DUPS: 12012010, -REG64( EQ_3_PPE_XIXCR , RULL(0x13012410), SH_UNT_EQ_3 , +REG64( EQ_3_PPE_XIXCR , RULL(0x13012010), SH_UNT_EQ_3 , SH_ACS_SCOM_WO ); //DUPS: 13012010, -REG64( EQ_4_PPE_XIXCR , RULL(0x14012410), SH_UNT_EQ_4 , +REG64( EQ_4_PPE_XIXCR , RULL(0x14012010), SH_UNT_EQ_4 , SH_ACS_SCOM_WO ); //DUPS: 14012010, -REG64( EQ_5_PPE_XIXCR , RULL(0x15012410), SH_UNT_EQ_5 , +REG64( EQ_5_PPE_XIXCR , RULL(0x15012010), SH_UNT_EQ_5 , SH_ACS_SCOM_WO ); //DUPS: 15012010, REG64( EX_PPE_XIXCR , RULL(0x10012010), SH_UNT_EX , SH_ACS_SCOM_WO ); REG64( EX_0_PPE_XIXCR , RULL(0x10012010), SH_UNT_EX_0 , SH_ACS_SCOM_WO ); @@ -16230,7 +16774,7 @@ REG64( EX_PPM_CGCR , RULL(0x200F0164 SH_ACS_SCOM_RW ); //DUPS: 210F0164, REG64( EX_0_PPM_CGCR , RULL(0x200F0164), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F0164, -REG64( EX_1_PPM_CGCR , RULL(0x230F0164), SH_UNT_EX_1 , +REG64( EX_1_PPM_CGCR , RULL(0x220F0164), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F0164, REG64( EX_2_PPM_CGCR , RULL(0x240F0164), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F0164, @@ -16361,11 +16905,11 @@ REG64( EX_0_PPM_GPMMR_SCOM1 , RULL(0x200F0101 SH_ACS_SCOM1 ); //DUPS: 210F0101, REG64( EX_0_PPM_GPMMR_SCOM2 , RULL(0x200F0102), SH_UNT_EX_0 , SH_ACS_SCOM2 ); //DUPS: 210F0102, -REG64( EX_1_PPM_GPMMR_SCOM , RULL(0x230F0100), SH_UNT_EX_1 , +REG64( EX_1_PPM_GPMMR_SCOM , RULL(0x220F0100), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0100, -REG64( EX_1_PPM_GPMMR_SCOM1 , RULL(0x230F0101), SH_UNT_EX_1 , +REG64( EX_1_PPM_GPMMR_SCOM1 , RULL(0x220F0101), SH_UNT_EX_1 , SH_ACS_SCOM1 ); //DUPS: 220F0101, -REG64( EX_1_PPM_GPMMR_SCOM2 , RULL(0x230F0102), SH_UNT_EX_1 , +REG64( EX_1_PPM_GPMMR_SCOM2 , RULL(0x220F0102), SH_UNT_EX_1 , SH_ACS_SCOM2 ); //DUPS: 220F0102, REG64( EX_2_PPM_GPMMR_SCOM , RULL(0x240F0100), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0100, @@ -16464,7 +17008,7 @@ REG64( EX_PPM_IVRMAVR , RULL(0x200F01B5 SH_ACS_SCOM_RO ); //DUPS: 210F01B5, REG64( EX_0_PPM_IVRMAVR , RULL(0x200F01B5), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F01B5, -REG64( EX_1_PPM_IVRMAVR , RULL(0x230F01B5), SH_UNT_EX_1 , +REG64( EX_1_PPM_IVRMAVR , RULL(0x220F01B5), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F01B5, REG64( EX_2_PPM_IVRMAVR , RULL(0x240F01B5), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F01B5, @@ -16627,11 +17171,11 @@ REG64( EX_0_PPM_IVRMCR_CLEAR , RULL(0x200F01B1 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01B1, REG64( EX_0_PPM_IVRMCR_OR , RULL(0x200F01B2), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F01B2, -REG64( EX_1_PPM_IVRMCR , RULL(0x230F01B0), SH_UNT_EX_1 , +REG64( EX_1_PPM_IVRMCR , RULL(0x220F01B0), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01B0, -REG64( EX_1_PPM_IVRMCR_CLEAR , RULL(0x230F01B1), SH_UNT_EX_1 , +REG64( EX_1_PPM_IVRMCR_CLEAR , RULL(0x220F01B1), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F01B1, -REG64( EX_1_PPM_IVRMCR_OR , RULL(0x230F01B2), SH_UNT_EX_1 , +REG64( EX_1_PPM_IVRMCR_OR , RULL(0x220F01B2), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F01B2, REG64( EX_2_PPM_IVRMCR , RULL(0x240F01B0), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01B0, @@ -16730,7 +17274,7 @@ REG64( EX_PPM_IVRMDVR , RULL(0x200F01B4 SH_ACS_SCOM_RW ); //DUPS: 210F01B4, REG64( EX_0_PPM_IVRMDVR , RULL(0x200F01B4), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F01B4, -REG64( EX_1_PPM_IVRMDVR , RULL(0x230F01B4), SH_UNT_EX_1 , +REG64( EX_1_PPM_IVRMDVR , RULL(0x220F01B4), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01B4, REG64( EX_2_PPM_IVRMDVR , RULL(0x240F01B4), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01B4, @@ -16789,7 +17333,7 @@ REG64( EX_PPM_IVRMST , RULL(0x200F01B3 SH_ACS_SCOM_RO ); //DUPS: 210F01B3, REG64( EX_0_PPM_IVRMST , RULL(0x200F01B3), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F01B3, -REG64( EX_1_PPM_IVRMST , RULL(0x230F01B3), SH_UNT_EX_1 , +REG64( EX_1_PPM_IVRMST , RULL(0x220F01B3), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F01B3, REG64( EX_2_PPM_IVRMST , RULL(0x240F01B3), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F01B3, @@ -16920,11 +17464,11 @@ REG64( EX_0_PPM_PFCS_SCOM1 , RULL(0x200F0119 SH_ACS_SCOM1 ); //DUPS: 210F0119, REG64( EX_0_PPM_PFCS_SCOM2 , RULL(0x200F011A), SH_UNT_EX_0 , SH_ACS_SCOM2 ); //DUPS: 210F011A, -REG64( EX_1_PPM_PFCS_SCOM , RULL(0x230F0118), SH_UNT_EX_1 , +REG64( EX_1_PPM_PFCS_SCOM , RULL(0x220F0118), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0118, -REG64( EX_1_PPM_PFCS_SCOM1 , RULL(0x230F0119), SH_UNT_EX_1 , +REG64( EX_1_PPM_PFCS_SCOM1 , RULL(0x220F0119), SH_UNT_EX_1 , SH_ACS_SCOM1 ); //DUPS: 220F0119, -REG64( EX_1_PPM_PFCS_SCOM2 , RULL(0x230F011A), SH_UNT_EX_1 , +REG64( EX_1_PPM_PFCS_SCOM2 , RULL(0x220F011A), SH_UNT_EX_1 , SH_ACS_SCOM2 ); //DUPS: 220F011A, REG64( EX_2_PPM_PFCS_SCOM , RULL(0x240F0118), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0118, @@ -17023,7 +17567,7 @@ REG64( EX_PPM_PFDLY , RULL(0x200F011B SH_ACS_SCOM_RW ); //DUPS: 210F011B, REG64( EX_0_PPM_PFDLY , RULL(0x200F011B), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F011B, -REG64( EX_1_PPM_PFDLY , RULL(0x230F011B), SH_UNT_EX_1 , +REG64( EX_1_PPM_PFDLY , RULL(0x220F011B), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F011B, REG64( EX_2_PPM_PFDLY , RULL(0x240F011B), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F011B, @@ -17082,7 +17626,7 @@ REG64( EX_PPM_PFOFF , RULL(0x200F011D SH_ACS_SCOM_RW ); //DUPS: 210F011D, REG64( EX_0_PPM_PFOFF , RULL(0x200F011D), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F011D, -REG64( EX_1_PPM_PFOFF , RULL(0x230F011D), SH_UNT_EX_1 , +REG64( EX_1_PPM_PFOFF , RULL(0x220F011D), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F011D, REG64( EX_2_PPM_PFOFF , RULL(0x240F011D), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F011D, @@ -17141,7 +17685,7 @@ REG64( EX_PPM_PFSNS , RULL(0x200F011C SH_ACS_SCOM_RO ); //DUPS: 210F011C, REG64( EX_0_PPM_PFSNS , RULL(0x200F011C), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F011C, -REG64( EX_1_PPM_PFSNS , RULL(0x230F011C), SH_UNT_EX_1 , +REG64( EX_1_PPM_PFSNS , RULL(0x220F011C), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F011C, REG64( EX_2_PPM_PFSNS , RULL(0x240F011C), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F011C, @@ -17200,7 +17744,7 @@ REG64( EX_PPM_PIG , RULL(0x200F0180 SH_ACS_SCOM ); //DUPS: 210F0180, REG64( EX_0_PPM_PIG , RULL(0x200F0180), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0180, -REG64( EX_1_PPM_PIG , RULL(0x230F0180), SH_UNT_EX_1 , +REG64( EX_1_PPM_PIG , RULL(0x220F0180), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0180, REG64( EX_2_PPM_PIG , RULL(0x240F0180), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0180, @@ -17259,7 +17803,7 @@ REG64( EX_PPM_SCRATCH0 , RULL(0x200F011E SH_ACS_SCOM_RW ); //DUPS: 210F011E, REG64( EX_0_PPM_SCRATCH0 , RULL(0x200F011E), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F011E, -REG64( EX_1_PPM_SCRATCH0 , RULL(0x230F011E), SH_UNT_EX_1 , +REG64( EX_1_PPM_SCRATCH0 , RULL(0x220F011E), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F011E, REG64( EX_2_PPM_SCRATCH0 , RULL(0x240F011E), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F011E, @@ -17318,7 +17862,7 @@ REG64( EX_PPM_SCRATCH1 , RULL(0x200F011F SH_ACS_SCOM_RW ); //DUPS: 210F011F, REG64( EX_0_PPM_SCRATCH1 , RULL(0x200F011F), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F011F, -REG64( EX_1_PPM_SCRATCH1 , RULL(0x230F011F), SH_UNT_EX_1 , +REG64( EX_1_PPM_SCRATCH1 , RULL(0x220F011F), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F011F, REG64( EX_2_PPM_SCRATCH1 , RULL(0x240F011F), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F011F, @@ -17377,7 +17921,7 @@ REG64( EX_PPM_SPWKUP_FSP , RULL(0x200F010B SH_ACS_SCOM_RW ); //DUPS: 210F010B, REG64( EX_0_PPM_SPWKUP_FSP , RULL(0x200F010B), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F010B, -REG64( EX_1_PPM_SPWKUP_FSP , RULL(0x230F010B), SH_UNT_EX_1 , +REG64( EX_1_PPM_SPWKUP_FSP , RULL(0x220F010B), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F010B, REG64( EX_2_PPM_SPWKUP_FSP , RULL(0x240F010B), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F010B, @@ -17436,7 +17980,7 @@ REG64( EX_PPM_SPWKUP_HYP , RULL(0x200F010D SH_ACS_SCOM_RW ); //DUPS: 210F010D, REG64( EX_0_PPM_SPWKUP_HYP , RULL(0x200F010D), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F010D, -REG64( EX_1_PPM_SPWKUP_HYP , RULL(0x230F010D), SH_UNT_EX_1 , +REG64( EX_1_PPM_SPWKUP_HYP , RULL(0x220F010D), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F010D, REG64( EX_2_PPM_SPWKUP_HYP , RULL(0x240F010D), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F010D, @@ -17495,7 +18039,7 @@ REG64( EX_PPM_SPWKUP_OCC , RULL(0x200F010C SH_ACS_SCOM_RW ); //DUPS: 210F010C, REG64( EX_0_PPM_SPWKUP_OCC , RULL(0x200F010C), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F010C, -REG64( EX_1_PPM_SPWKUP_OCC , RULL(0x230F010C), SH_UNT_EX_1 , +REG64( EX_1_PPM_SPWKUP_OCC , RULL(0x220F010C), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F010C, REG64( EX_2_PPM_SPWKUP_OCC , RULL(0x240F010C), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F010C, @@ -17554,7 +18098,7 @@ REG64( EX_PPM_SPWKUP_OTR , RULL(0x200F010A SH_ACS_SCOM_RW ); //DUPS: 210F010A, REG64( EX_0_PPM_SPWKUP_OTR , RULL(0x200F010A), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 210F010A, -REG64( EX_1_PPM_SPWKUP_OTR , RULL(0x230F010A), SH_UNT_EX_1 , +REG64( EX_1_PPM_SPWKUP_OTR , RULL(0x220F010A), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F010A, REG64( EX_2_PPM_SPWKUP_OTR , RULL(0x240F010A), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F010A, @@ -17613,7 +18157,7 @@ REG64( EX_PPM_SSHFSP , RULL(0x200F0111 SH_ACS_SCOM ); //DUPS: 210F0111, REG64( EX_0_PPM_SSHFSP , RULL(0x200F0111), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0111, -REG64( EX_1_PPM_SSHFSP , RULL(0x230F0111), SH_UNT_EX_1 , +REG64( EX_1_PPM_SSHFSP , RULL(0x220F0111), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0111, REG64( EX_2_PPM_SSHFSP , RULL(0x240F0111), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0111, @@ -17672,7 +18216,7 @@ REG64( EX_PPM_SSHHYP , RULL(0x200F0114 SH_ACS_SCOM ); //DUPS: 210F0114, REG64( EX_0_PPM_SSHHYP , RULL(0x200F0114), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0114, -REG64( EX_1_PPM_SSHHYP , RULL(0x230F0114), SH_UNT_EX_1 , +REG64( EX_1_PPM_SSHHYP , RULL(0x220F0114), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0114, REG64( EX_2_PPM_SSHHYP , RULL(0x240F0114), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0114, @@ -17731,7 +18275,7 @@ REG64( EX_PPM_SSHOCC , RULL(0x200F0112 SH_ACS_SCOM ); //DUPS: 210F0112, REG64( EX_0_PPM_SSHOCC , RULL(0x200F0112), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0112, -REG64( EX_1_PPM_SSHOCC , RULL(0x230F0112), SH_UNT_EX_1 , +REG64( EX_1_PPM_SSHOCC , RULL(0x220F0112), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0112, REG64( EX_2_PPM_SSHOCC , RULL(0x240F0112), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0112, @@ -17790,7 +18334,7 @@ REG64( EX_PPM_SSHOTR , RULL(0x200F0113 SH_ACS_SCOM ); //DUPS: 210F0113, REG64( EX_0_PPM_SSHOTR , RULL(0x200F0113), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0113, -REG64( EX_1_PPM_SSHOTR , RULL(0x230F0113), SH_UNT_EX_1 , +REG64( EX_1_PPM_SSHOTR , RULL(0x220F0113), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0113, REG64( EX_2_PPM_SSHOTR , RULL(0x240F0113), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0113, @@ -17849,7 +18393,7 @@ REG64( EX_PPM_SSHSRC , RULL(0x200F0110 SH_ACS_SCOM ); //DUPS: 210F0110, REG64( EX_0_PPM_SSHSRC , RULL(0x200F0110), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0110, -REG64( EX_1_PPM_SSHSRC , RULL(0x230F0110), SH_UNT_EX_1 , +REG64( EX_1_PPM_SSHSRC , RULL(0x220F0110), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0110, REG64( EX_2_PPM_SSHSRC , RULL(0x240F0110), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0110, @@ -18012,11 +18556,11 @@ REG64( EX_0_PPM_VDMCR_CLEAR , RULL(0x200F01B9 SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01B9, REG64( EX_0_PPM_VDMCR_OR , RULL(0x200F01BA), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 210F01BA, -REG64( EX_1_PPM_VDMCR , RULL(0x230F01B8), SH_UNT_EX_1 , +REG64( EX_1_PPM_VDMCR , RULL(0x220F01B8), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 220F01B8, -REG64( EX_1_PPM_VDMCR_CLEAR , RULL(0x230F01B9), SH_UNT_EX_1 , +REG64( EX_1_PPM_VDMCR_CLEAR , RULL(0x220F01B9), SH_UNT_EX_1 , SH_ACS_SCOM1_CLEAR ); //DUPS: 220F01B9, -REG64( EX_1_PPM_VDMCR_OR , RULL(0x230F01BA), SH_UNT_EX_1 , +REG64( EX_1_PPM_VDMCR_OR , RULL(0x220F01BA), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 220F01BA, REG64( EX_2_PPM_VDMCR , RULL(0x240F01B8), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 250F01B8, @@ -18079,19 +18623,19 @@ REG64( EX_11_PPM_VDMCR_CLEAR , RULL(0x360F01B9 REG64( EX_11_PPM_VDMCR_OR , RULL(0x360F01BA), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); //DUPS: 370F01BA, -REG64( EQ_PRD_PURGE_CMD_REG , RULL(0x1001080E), SH_UNT_EQ , +REG64( EQ_PRD_PURGE_CMD_REG , RULL(0x10010C0E), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C0E, -REG64( EQ_0_PRD_PURGE_CMD_REG , RULL(0x1001080E), SH_UNT_EQ_0 , +REG64( EQ_0_PRD_PURGE_CMD_REG , RULL(0x10010C0E), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C0E, -REG64( EQ_1_PRD_PURGE_CMD_REG , RULL(0x1101080E), SH_UNT_EQ_1 , +REG64( EQ_1_PRD_PURGE_CMD_REG , RULL(0x11010C0E), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C0E, -REG64( EQ_2_PRD_PURGE_CMD_REG , RULL(0x1201080E), SH_UNT_EQ_2 , +REG64( EQ_2_PRD_PURGE_CMD_REG , RULL(0x12010C0E), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C0E, -REG64( EQ_3_PRD_PURGE_CMD_REG , RULL(0x1301080E), SH_UNT_EQ_3 , +REG64( EQ_3_PRD_PURGE_CMD_REG , RULL(0x13010C0E), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C0E, -REG64( EQ_4_PRD_PURGE_CMD_REG , RULL(0x1401080E), SH_UNT_EQ_4 , +REG64( EQ_4_PRD_PURGE_CMD_REG , RULL(0x14010C0E), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C0E, -REG64( EQ_5_PRD_PURGE_CMD_REG , RULL(0x1501080E), SH_UNT_EQ_5 , +REG64( EQ_5_PRD_PURGE_CMD_REG , RULL(0x15010C0E), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C0E, REG64( EX_PRD_PURGE_CMD_REG , RULL(0x1001080E), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PRD_PURGE_CMD_REG , RULL(0x1001080E), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -18107,19 +18651,19 @@ REG64( EX_9_PRD_PURGE_CMD_REG , RULL(0x14010C0E REG64( EX_10_PRD_PURGE_CMD_REG , RULL(0x1501080E), SH_UNT_EX_10 , SH_ACS_SCOM ); REG64( EX_11_PRD_PURGE_CMD_REG , RULL(0x15010C0E), SH_UNT_EX_11 , SH_ACS_SCOM ); -REG64( EQ_PRD_PURGE_REG , RULL(0x1001180E), SH_UNT_EQ , +REG64( EQ_PRD_PURGE_REG , RULL(0x10011C0E), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10011C0E, -REG64( EQ_0_PRD_PURGE_REG , RULL(0x1001180E), SH_UNT_EQ_0 , +REG64( EQ_0_PRD_PURGE_REG , RULL(0x10011C0E), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10011C0E, -REG64( EQ_1_PRD_PURGE_REG , RULL(0x1101180E), SH_UNT_EQ_1 , +REG64( EQ_1_PRD_PURGE_REG , RULL(0x11011C0E), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11011C0E, -REG64( EQ_2_PRD_PURGE_REG , RULL(0x1201180E), SH_UNT_EQ_2 , +REG64( EQ_2_PRD_PURGE_REG , RULL(0x12011C0E), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12011C0E, -REG64( EQ_3_PRD_PURGE_REG , RULL(0x1301180E), SH_UNT_EQ_3 , +REG64( EQ_3_PRD_PURGE_REG , RULL(0x13011C0E), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13011C0E, -REG64( EQ_4_PRD_PURGE_REG , RULL(0x1401180E), SH_UNT_EQ_4 , +REG64( EQ_4_PRD_PURGE_REG , RULL(0x14011C0E), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14011C0E, -REG64( EQ_5_PRD_PURGE_REG , RULL(0x1501180E), SH_UNT_EQ_5 , +REG64( EQ_5_PRD_PURGE_REG , RULL(0x15011C0E), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15011C0E, REG64( EX_PRD_PURGE_REG , RULL(0x1001180E), SH_UNT_EX , SH_ACS_SCOM ); REG64( EX_0_PRD_PURGE_REG , RULL(0x1001180E), SH_UNT_EX_0 , SH_ACS_SCOM ); @@ -18171,7 +18715,7 @@ REG64( EX_PRE_COUNTER_REG , RULL(0x200F0028 SH_ACS_SCOM ); //DUPS: 210F0028, REG64( EX_0_PRE_COUNTER_REG , RULL(0x200F0028), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0028, -REG64( EX_1_PRE_COUNTER_REG , RULL(0x230F0028), SH_UNT_EX_1 , +REG64( EX_1_PRE_COUNTER_REG , RULL(0x220F0028), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0028, REG64( EX_2_PRE_COUNTER_REG , RULL(0x240F0028), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0028, @@ -18230,7 +18774,7 @@ REG64( EX_PRIMARY_ADDRESS_REG , RULL(0x200F0000 SH_ACS_SCOM ); //DUPS: 210F0000, REG64( EX_0_PRIMARY_ADDRESS_REG , RULL(0x200F0000), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0000, -REG64( EX_1_PRIMARY_ADDRESS_REG , RULL(0x230F0000), SH_UNT_EX_1 , +REG64( EX_1_PRIMARY_ADDRESS_REG , RULL(0x220F0000), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0000, REG64( EX_2_PRIMARY_ADDRESS_REG , RULL(0x240F0000), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0000, @@ -18289,7 +18833,7 @@ REG64( EX_PROTECT_MODE_REG , RULL(0x200F03FE SH_ACS_SCOM ); //DUPS: 210F03FE, REG64( EX_0_PROTECT_MODE_REG , RULL(0x200F03FE), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F03FE, -REG64( EX_1_PROTECT_MODE_REG , RULL(0x230F03FE), SH_UNT_EX_1 , +REG64( EX_1_PROTECT_MODE_REG , RULL(0x220F03FE), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F03FE, REG64( EX_2_PROTECT_MODE_REG , RULL(0x240F03FE), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F03FE, @@ -18360,7 +18904,7 @@ REG64( EX_5_PSCOM_ERROR_MASK , RULL(0x2A010002 SH_ACS_SCOM ); //DUPS: 2B010002, REG64( EX_6_PSCOM_ERROR_MASK , RULL(0x2C010002), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010002, -REG64( EX_7_PSCOM_ERROR_MASK , RULL(0x2E010002), SH_UNT_EX_7 , +REG64( EX_7_PSCOM_ERROR_MASK , RULL(0x2F010002), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010002, REG64( EX_8_PSCOM_ERROR_MASK , RULL(0x30010002), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010002, @@ -18419,7 +18963,7 @@ REG64( EX_5_PSCOM_MODE_REG , RULL(0x2A010000 SH_ACS_SCOM ); //DUPS: 2B010000, REG64( EX_6_PSCOM_MODE_REG , RULL(0x2C010000), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010000, -REG64( EX_7_PSCOM_MODE_REG , RULL(0x2E010000), SH_UNT_EX_7 , +REG64( EX_7_PSCOM_MODE_REG , RULL(0x2F010000), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010000, REG64( EX_8_PSCOM_MODE_REG , RULL(0x30010000), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010000, @@ -18478,7 +19022,7 @@ REG64( EX_5_PSCOM_STATUS_ERROR_REG , RULL(0x2A010001 SH_ACS_SCOM ); //DUPS: 2B010001, REG64( EX_6_PSCOM_STATUS_ERROR_REG , RULL(0x2C010001), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010001, -REG64( EX_7_PSCOM_STATUS_ERROR_REG , RULL(0x2E010001), SH_UNT_EX_7 , +REG64( EX_7_PSCOM_STATUS_ERROR_REG , RULL(0x2F010001), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010001, REG64( EX_8_PSCOM_STATUS_ERROR_REG , RULL(0x30010001), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010001, @@ -18514,19 +19058,19 @@ REG64( C_20_PWM_EVENTS , RULL(0x34010AA2 REG64( C_21_PWM_EVENTS , RULL(0x35010AA2), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_PWM_EVENTS , RULL(0x36010AA2), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_PWM_EVENTS , RULL(0x37010AA2), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_PWM_EVENTS , RULL(0x21010AA2), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_PWM_EVENTS , RULL(0x20010AA2), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA2, -REG64( EX_10_L2_PWM_EVENTS , RULL(0x35010AA2), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_PWM_EVENTS , RULL(0x34010AA2), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010AA2, -REG64( EX_11_L2_PWM_EVENTS , RULL(0x37010AA2), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_PWM_EVENTS , RULL(0x36010AA2), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010AA2, -REG64( EX_1_L2_PWM_EVENTS , RULL(0x23010AA2), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_PWM_EVENTS , RULL(0x22010AA2), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010AA2, -REG64( EX_2_L2_PWM_EVENTS , RULL(0x25010AA2), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_PWM_EVENTS , RULL(0x24010AA2), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010AA2, -REG64( EX_3_L2_PWM_EVENTS , RULL(0x27010AA2), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_PWM_EVENTS , RULL(0x26010AA2), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010AA2, -REG64( EX_4_L2_PWM_EVENTS , RULL(0x29010AA2), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_PWM_EVENTS , RULL(0x28010AA2), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010AA2, REG64( EX_5_L2_PWM_EVENTS , RULL(0x2B010AA2), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010AA2, @@ -18534,11 +19078,11 @@ REG64( EX_6_L2_PWM_EVENTS , RULL(0x2D010AA2 SH_ACS_SCOM_RW ); //DUPS: 2C010AA2, REG64( EX_7_L2_PWM_EVENTS , RULL(0x2F010AA2), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010AA2, -REG64( EX_8_L2_PWM_EVENTS , RULL(0x31010AA2), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_PWM_EVENTS , RULL(0x30010AA2), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010AA2, -REG64( EX_9_L2_PWM_EVENTS , RULL(0x33010AA2), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_PWM_EVENTS , RULL(0x32010AA2), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010AA2, -REG64( EX_L2_PWM_EVENTS , RULL(0x21010AA2), SH_UNT_EX_L2 , +REG64( EX_L2_PWM_EVENTS , RULL(0x20010AA2), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA2, REG64( EQ_QPPM_DPLL_CTRL , RULL(0x100F0152), SH_UNT_EQ , SH_ACS_SCOM_RW ); @@ -18822,7 +19366,7 @@ REG64( EX_5_RAM_CTRL , RULL(0x2A010A4F SH_ACS_SCOM_RW ); //DUPS: 2B010A4F, REG64( EX_6_RAM_CTRL , RULL(0x2C010A4F), SH_UNT_EX_6 , SH_ACS_SCOM_RW ); //DUPS: 2D010A4F, -REG64( EX_7_RAM_CTRL , RULL(0x2E010A4F), SH_UNT_EX_7 , +REG64( EX_7_RAM_CTRL , RULL(0x2F010A4F), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F010A4F, REG64( EX_8_RAM_CTRL , RULL(0x30010A4F), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31010A4F, @@ -18874,7 +19418,7 @@ REG64( EX_5_RAM_MODEREG , RULL(0x2A010A4E SH_ACS_SCOM_RW ); //DUPS: 2B010A4E, REG64( EX_6_RAM_MODEREG , RULL(0x2C010A4E), SH_UNT_EX_6 , SH_ACS_SCOM_RW ); //DUPS: 2D010A4E, -REG64( EX_7_RAM_MODEREG , RULL(0x2E010A4E), SH_UNT_EX_7 , +REG64( EX_7_RAM_MODEREG , RULL(0x2F010A4E), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2F010A4E, REG64( EX_8_RAM_MODEREG , RULL(0x30010A4E), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 31010A4E, @@ -18928,7 +19472,7 @@ REG64( EX_5_L2_RAM_STATUS , RULL(0x2A010A50 SH_ACS_SCOM ); //DUPS: 2B010A50, REG64( EX_6_L2_RAM_STATUS , RULL(0x2C010A50), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010A50, -REG64( EX_7_L2_RAM_STATUS , RULL(0x2E010A50), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_RAM_STATUS , RULL(0x2F010A50), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010A50, REG64( EX_8_L2_RAM_STATUS , RULL(0x30010A50), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010A50, @@ -18980,7 +19524,7 @@ REG64( EX_5_L2_RAS_MODEREG , RULL(0x2A010A9D SH_ACS_SCOM_RW ); //DUPS: 2B010A9D, REG64( EX_6_L2_RAS_MODEREG , RULL(0x2C010A9D), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010A9D, -REG64( EX_7_L2_RAS_MODEREG , RULL(0x2E010A9D), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_RAS_MODEREG , RULL(0x2F010A9D), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A9D, REG64( EX_8_L2_RAS_MODEREG , RULL(0x30010A9D), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A9D, @@ -19032,7 +19576,7 @@ REG64( EX_5_L2_RAS_STATUS , RULL(0x2A010A02 SH_ACS_SCOM ); //DUPS: 2B010A02, REG64( EX_6_L2_RAS_STATUS , RULL(0x2C010A02), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010A02, -REG64( EX_7_L2_RAS_STATUS , RULL(0x2E010A02), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_RAS_STATUS , RULL(0x2F010A02), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010A02, REG64( EX_8_L2_RAS_STATUS , RULL(0x30010A02), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010A02, @@ -19041,19 +19585,19 @@ REG64( EX_9_L2_RAS_STATUS , RULL(0x32010A02 REG64( EX_L2_RAS_STATUS , RULL(0x20010A02), SH_UNT_EX_L2 , SH_ACS_SCOM ); //DUPS: 21010A02, -REG64( EQ_RD_EPS_REG , RULL(0x10010810), SH_UNT_EQ , +REG64( EQ_RD_EPS_REG , RULL(0x10010C10), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C10, -REG64( EQ_0_RD_EPS_REG , RULL(0x10010810), SH_UNT_EQ_0 , +REG64( EQ_0_RD_EPS_REG , RULL(0x10010C10), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C10, -REG64( EQ_1_RD_EPS_REG , RULL(0x11010810), SH_UNT_EQ_1 , +REG64( EQ_1_RD_EPS_REG , RULL(0x11010C10), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C10, -REG64( EQ_2_RD_EPS_REG , RULL(0x12010810), SH_UNT_EQ_2 , +REG64( EQ_2_RD_EPS_REG , RULL(0x12010C10), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C10, -REG64( EQ_3_RD_EPS_REG , RULL(0x13010810), SH_UNT_EQ_3 , +REG64( EQ_3_RD_EPS_REG , RULL(0x13010C10), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C10, -REG64( EQ_4_RD_EPS_REG , RULL(0x14010810), SH_UNT_EQ_4 , +REG64( EQ_4_RD_EPS_REG , RULL(0x14010C10), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C10, -REG64( EQ_5_RD_EPS_REG , RULL(0x15010810), SH_UNT_EQ_5 , +REG64( EQ_5_RD_EPS_REG , RULL(0x15010C10), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C10, REG64( EX_0_L2_RD_EPS_REG , RULL(0x10010810), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_10_L2_RD_EPS_REG , RULL(0x15010810), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); @@ -19112,7 +19656,7 @@ REG64( EX_5_L2_RECOV_FWD_PROG_CTRL , RULL(0x2A010A4B SH_ACS_SCOM ); //DUPS: 2B010A4B, REG64( EX_6_L2_RECOV_FWD_PROG_CTRL , RULL(0x2C010A4B), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010A4B, -REG64( EX_7_L2_RECOV_FWD_PROG_CTRL , RULL(0x2E010A4B), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_RECOV_FWD_PROG_CTRL , RULL(0x2F010A4B), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010A4B, REG64( EX_8_L2_RECOV_FWD_PROG_CTRL , RULL(0x30010A4B), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010A4B, @@ -19157,7 +19701,7 @@ REG64( EX_RECOV_INTERRUPT_REG , RULL(0x200F001B SH_ACS_SCOM ); //DUPS: 210F001B, REG64( EX_0_RECOV_INTERRUPT_REG , RULL(0x200F001B), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F001B, -REG64( EX_1_RECOV_INTERRUPT_REG , RULL(0x230F001B), SH_UNT_EX_1 , +REG64( EX_1_RECOV_INTERRUPT_REG , RULL(0x220F001B), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F001B, REG64( EX_2_RECOV_INTERRUPT_REG , RULL(0x240F001B), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F001B, @@ -19223,7 +19767,7 @@ REG64( EX_5_L2_RECOV_THOLD , RULL(0x2A010A4C SH_ACS_SCOM_RW ); //DUPS: 2B010A4C, REG64( EX_6_L2_RECOV_THOLD , RULL(0x2C010A4C), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010A4C, -REG64( EX_7_L2_RECOV_THOLD , RULL(0x2E010A4C), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_RECOV_THOLD , RULL(0x2F010A4C), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010A4C, REG64( EX_8_L2_RECOV_THOLD , RULL(0x30010A4C), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010A4C, @@ -19275,7 +19819,7 @@ REG64( EX_5_L2_RESET_KEEPER , RULL(0x2A010A4A SH_ACS_SCOM ); //DUPS: 2B010A4A, REG64( EX_6_L2_RESET_KEEPER , RULL(0x2C010A4A), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010A4A, -REG64( EX_7_L2_RESET_KEEPER , RULL(0x2E010A4A), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_RESET_KEEPER , RULL(0x2F010A4A), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010A4A, REG64( EX_8_L2_RESET_KEEPER , RULL(0x30010A4A), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010A4A, @@ -19332,7 +19876,7 @@ REG64( EX_5_RFIR , RULL(0x2A040001 SH_ACS_SCOM ); //DUPS: 2B040001, REG64( EX_6_RFIR , RULL(0x2C040001), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040001, -REG64( EX_7_RFIR , RULL(0x2E040001), SH_UNT_EX_7 , +REG64( EX_7_RFIR , RULL(0x2F040001), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040001, REG64( EX_8_RFIR , RULL(0x30040001), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040001, @@ -19391,7 +19935,7 @@ REG64( EX_5_RING_FENCE_MASK_LATCH_REG , RULL(0x2A010008 SH_ACS_SCOM ); //DUPS: 2B010008, REG64( EX_6_RING_FENCE_MASK_LATCH_REG , RULL(0x2C010008), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010008, -REG64( EX_7_RING_FENCE_MASK_LATCH_REG , RULL(0x2E010008), SH_UNT_EX_7 , +REG64( EX_7_RING_FENCE_MASK_LATCH_REG , RULL(0x2F010008), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010008, REG64( EX_8_RING_FENCE_MASK_LATCH_REG , RULL(0x30010008), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010008, @@ -19402,6 +19946,301 @@ REG64( EX_10_RING_FENCE_MASK_LATCH_REG , RULL(0x34010008 REG64( EX_11_RING_FENCE_MASK_LATCH_REG , RULL(0x36010008), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37010008, +REG64( C_SCAN32 , RULL(0x20038000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN32 , RULL(0x20038000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN32 , RULL(0x21038000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN32 , RULL(0x22038000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN32 , RULL(0x23038000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN32 , RULL(0x24038000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN32 , RULL(0x25038000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN32 , RULL(0x26038000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN32 , RULL(0x27038000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN32 , RULL(0x28038000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN32 , RULL(0x29038000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN32 , RULL(0x2A038000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN32 , RULL(0x2B038000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN32 , RULL(0x2C038000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN32 , RULL(0x2D038000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN32 , RULL(0x2E038000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN32 , RULL(0x2F038000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN32 , RULL(0x30038000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN32 , RULL(0x31038000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN32 , RULL(0x32038000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN32 , RULL(0x33038000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN32 , RULL(0x34038000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN32 , RULL(0x35038000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN32 , RULL(0x36038000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN32 , RULL(0x37038000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN32 , RULL(0x10038000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN32 , RULL(0x10038000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN32 , RULL(0x11038000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN32 , RULL(0x12038000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN32 , RULL(0x13038000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN32 , RULL(0x14038000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN32 , RULL(0x15038000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN32 , RULL(0x20038000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 21038000, +REG64( EX_0_SCAN32 , RULL(0x20038000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 21038000, +REG64( EX_1_SCAN32 , RULL(0x22038000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 23038000, +REG64( EX_2_SCAN32 , RULL(0x24038000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 25038000, +REG64( EX_3_SCAN32 , RULL(0x26038000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 27038000, +REG64( EX_4_SCAN32 , RULL(0x28038000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 29038000, +REG64( EX_5_SCAN32 , RULL(0x2A038000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B038000, +REG64( EX_6_SCAN32 , RULL(0x2C038000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D038000, +REG64( EX_7_SCAN32 , RULL(0x2F038000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F038000, +REG64( EX_8_SCAN32 , RULL(0x30038000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 31038000, +REG64( EX_9_SCAN32 , RULL(0x32038000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 33038000, +REG64( EX_10_SCAN32 , RULL(0x34038000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 35038000, +REG64( EX_11_SCAN32 , RULL(0x36038000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 37038000, + +REG64( C_SCAN64 , RULL(0x2003E000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN64 , RULL(0x2003E000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN64 , RULL(0x2103E000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN64 , RULL(0x2203E000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN64 , RULL(0x2303E000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN64 , RULL(0x2403E000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN64 , RULL(0x2503E000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN64 , RULL(0x2603E000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN64 , RULL(0x2703E000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN64 , RULL(0x2803E000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN64 , RULL(0x2903E000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN64 , RULL(0x2A03E000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN64 , RULL(0x2B03E000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN64 , RULL(0x2C03E000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN64 , RULL(0x2D03E000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN64 , RULL(0x2E03E000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN64 , RULL(0x2F03E000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN64 , RULL(0x3003E000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN64 , RULL(0x3103E000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN64 , RULL(0x3203E000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN64 , RULL(0x3303E000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN64 , RULL(0x3403E000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN64 , RULL(0x3503E000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN64 , RULL(0x3603E000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN64 , RULL(0x3703E000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN64 , RULL(0x1003E000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN64 , RULL(0x1003E000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN64 , RULL(0x1103E000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN64 , RULL(0x1203E000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN64 , RULL(0x1303E000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN64 , RULL(0x1403E000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN64 , RULL(0x1503E000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN64 , RULL(0x2003E000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 2103E000, +REG64( EX_0_SCAN64 , RULL(0x2003E000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 2103E000, +REG64( EX_1_SCAN64 , RULL(0x2203E000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 2303E000, +REG64( EX_2_SCAN64 , RULL(0x2403E000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 2503E000, +REG64( EX_3_SCAN64 , RULL(0x2603E000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 2703E000, +REG64( EX_4_SCAN64 , RULL(0x2803E000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 2903E000, +REG64( EX_5_SCAN64 , RULL(0x2A03E000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B03E000, +REG64( EX_6_SCAN64 , RULL(0x2C03E000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D03E000, +REG64( EX_7_SCAN64 , RULL(0x2F03E000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F03E000, +REG64( EX_8_SCAN64 , RULL(0x3003E000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 3103E000, +REG64( EX_9_SCAN64 , RULL(0x3203E000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 3303E000, +REG64( EX_10_SCAN64 , RULL(0x3403E000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 3503E000, +REG64( EX_11_SCAN64 , RULL(0x3603E000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 3703E000, + +REG64( C_SCAN_CAPTUREDR , RULL(0x2003C000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN_CAPTUREDR , RULL(0x2003C000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN_CAPTUREDR , RULL(0x2103C000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN_CAPTUREDR , RULL(0x2203C000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN_CAPTUREDR , RULL(0x2303C000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN_CAPTUREDR , RULL(0x2403C000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN_CAPTUREDR , RULL(0x2503C000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN_CAPTUREDR , RULL(0x2603C000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN_CAPTUREDR , RULL(0x2703C000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN_CAPTUREDR , RULL(0x2803C000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN_CAPTUREDR , RULL(0x2903C000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN_CAPTUREDR , RULL(0x2A03C000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN_CAPTUREDR , RULL(0x2B03C000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN_CAPTUREDR , RULL(0x2C03C000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN_CAPTUREDR , RULL(0x2D03C000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN_CAPTUREDR , RULL(0x2E03C000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN_CAPTUREDR , RULL(0x2F03C000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN_CAPTUREDR , RULL(0x3003C000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN_CAPTUREDR , RULL(0x3103C000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN_CAPTUREDR , RULL(0x3203C000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN_CAPTUREDR , RULL(0x3303C000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN_CAPTUREDR , RULL(0x3403C000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN_CAPTUREDR , RULL(0x3503C000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN_CAPTUREDR , RULL(0x3603C000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN_CAPTUREDR , RULL(0x3703C000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN_CAPTUREDR , RULL(0x1003C000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN_CAPTUREDR , RULL(0x1003C000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN_CAPTUREDR , RULL(0x1103C000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN_CAPTUREDR , RULL(0x1203C000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN_CAPTUREDR , RULL(0x1303C000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN_CAPTUREDR , RULL(0x1403C000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN_CAPTUREDR , RULL(0x1503C000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN_CAPTUREDR , RULL(0x2003C000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 2103C000, +REG64( EX_0_SCAN_CAPTUREDR , RULL(0x2003C000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 2103C000, +REG64( EX_1_SCAN_CAPTUREDR , RULL(0x2203C000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 2303C000, +REG64( EX_2_SCAN_CAPTUREDR , RULL(0x2403C000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 2503C000, +REG64( EX_3_SCAN_CAPTUREDR , RULL(0x2603C000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 2703C000, +REG64( EX_4_SCAN_CAPTUREDR , RULL(0x2803C000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 2903C000, +REG64( EX_5_SCAN_CAPTUREDR , RULL(0x2A03C000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B03C000, +REG64( EX_6_SCAN_CAPTUREDR , RULL(0x2C03C000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D03C000, +REG64( EX_7_SCAN_CAPTUREDR , RULL(0x2F03C000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F03C000, +REG64( EX_8_SCAN_CAPTUREDR , RULL(0x3003C000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 3103C000, +REG64( EX_9_SCAN_CAPTUREDR , RULL(0x3203C000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 3303C000, +REG64( EX_10_SCAN_CAPTUREDR , RULL(0x3403C000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 3503C000, +REG64( EX_11_SCAN_CAPTUREDR , RULL(0x3603C000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 3703C000, + +REG64( C_SCAN_CAPTUREDR_LONG , RULL(0x2003D000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN_CAPTUREDR_LONG , RULL(0x2003D000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN_CAPTUREDR_LONG , RULL(0x2103D000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN_CAPTUREDR_LONG , RULL(0x2203D000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN_CAPTUREDR_LONG , RULL(0x2303D000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN_CAPTUREDR_LONG , RULL(0x2403D000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN_CAPTUREDR_LONG , RULL(0x2503D000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN_CAPTUREDR_LONG , RULL(0x2603D000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN_CAPTUREDR_LONG , RULL(0x2703D000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN_CAPTUREDR_LONG , RULL(0x2803D000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN_CAPTUREDR_LONG , RULL(0x2903D000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN_CAPTUREDR_LONG , RULL(0x2A03D000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN_CAPTUREDR_LONG , RULL(0x2B03D000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN_CAPTUREDR_LONG , RULL(0x2C03D000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN_CAPTUREDR_LONG , RULL(0x2D03D000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN_CAPTUREDR_LONG , RULL(0x2E03D000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN_CAPTUREDR_LONG , RULL(0x2F03D000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN_CAPTUREDR_LONG , RULL(0x3003D000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN_CAPTUREDR_LONG , RULL(0x3103D000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN_CAPTUREDR_LONG , RULL(0x3203D000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN_CAPTUREDR_LONG , RULL(0x3303D000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN_CAPTUREDR_LONG , RULL(0x3403D000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN_CAPTUREDR_LONG , RULL(0x3503D000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN_CAPTUREDR_LONG , RULL(0x3603D000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN_CAPTUREDR_LONG , RULL(0x3703D000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN_CAPTUREDR_LONG , RULL(0x1003D000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN_CAPTUREDR_LONG , RULL(0x1003D000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN_CAPTUREDR_LONG , RULL(0x1103D000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN_CAPTUREDR_LONG , RULL(0x1203D000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN_CAPTUREDR_LONG , RULL(0x1303D000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN_CAPTUREDR_LONG , RULL(0x1403D000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN_CAPTUREDR_LONG , RULL(0x1503D000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN_CAPTUREDR_LONG , RULL(0x2003D000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 2103D000, +REG64( EX_0_SCAN_CAPTUREDR_LONG , RULL(0x2003D000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 2103D000, +REG64( EX_1_SCAN_CAPTUREDR_LONG , RULL(0x2203D000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 2303D000, +REG64( EX_2_SCAN_CAPTUREDR_LONG , RULL(0x2403D000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 2503D000, +REG64( EX_3_SCAN_CAPTUREDR_LONG , RULL(0x2603D000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 2703D000, +REG64( EX_4_SCAN_CAPTUREDR_LONG , RULL(0x2803D000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 2903D000, +REG64( EX_5_SCAN_CAPTUREDR_LONG , RULL(0x2A03D000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B03D000, +REG64( EX_6_SCAN_CAPTUREDR_LONG , RULL(0x2C03D000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D03D000, +REG64( EX_7_SCAN_CAPTUREDR_LONG , RULL(0x2F03D000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F03D000, +REG64( EX_8_SCAN_CAPTUREDR_LONG , RULL(0x3003D000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 3103D000, +REG64( EX_9_SCAN_CAPTUREDR_LONG , RULL(0x3203D000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 3303D000, +REG64( EX_10_SCAN_CAPTUREDR_LONG , RULL(0x3403D000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 3503D000, +REG64( EX_11_SCAN_CAPTUREDR_LONG , RULL(0x3603D000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 3703D000, + +REG64( C_SCAN_LONG_ROTATE , RULL(0x20039000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN_LONG_ROTATE , RULL(0x20039000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN_LONG_ROTATE , RULL(0x21039000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN_LONG_ROTATE , RULL(0x22039000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN_LONG_ROTATE , RULL(0x23039000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN_LONG_ROTATE , RULL(0x24039000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN_LONG_ROTATE , RULL(0x25039000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN_LONG_ROTATE , RULL(0x26039000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN_LONG_ROTATE , RULL(0x27039000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN_LONG_ROTATE , RULL(0x28039000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN_LONG_ROTATE , RULL(0x29039000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN_LONG_ROTATE , RULL(0x2A039000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN_LONG_ROTATE , RULL(0x2B039000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN_LONG_ROTATE , RULL(0x2C039000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN_LONG_ROTATE , RULL(0x2D039000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN_LONG_ROTATE , RULL(0x2E039000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN_LONG_ROTATE , RULL(0x2F039000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN_LONG_ROTATE , RULL(0x30039000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN_LONG_ROTATE , RULL(0x31039000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN_LONG_ROTATE , RULL(0x32039000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN_LONG_ROTATE , RULL(0x33039000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN_LONG_ROTATE , RULL(0x34039000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN_LONG_ROTATE , RULL(0x35039000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN_LONG_ROTATE , RULL(0x36039000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN_LONG_ROTATE , RULL(0x37039000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN_LONG_ROTATE , RULL(0x10039000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN_LONG_ROTATE , RULL(0x10039000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN_LONG_ROTATE , RULL(0x11039000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN_LONG_ROTATE , RULL(0x12039000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN_LONG_ROTATE , RULL(0x13039000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN_LONG_ROTATE , RULL(0x14039000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN_LONG_ROTATE , RULL(0x15039000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN_LONG_ROTATE , RULL(0x20039000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 21039000, +REG64( EX_0_SCAN_LONG_ROTATE , RULL(0x20039000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 21039000, +REG64( EX_1_SCAN_LONG_ROTATE , RULL(0x22039000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 23039000, +REG64( EX_2_SCAN_LONG_ROTATE , RULL(0x24039000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 25039000, +REG64( EX_3_SCAN_LONG_ROTATE , RULL(0x26039000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 27039000, +REG64( EX_4_SCAN_LONG_ROTATE , RULL(0x28039000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 29039000, +REG64( EX_5_SCAN_LONG_ROTATE , RULL(0x2A039000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B039000, +REG64( EX_6_SCAN_LONG_ROTATE , RULL(0x2C039000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D039000, +REG64( EX_7_SCAN_LONG_ROTATE , RULL(0x2F039000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F039000, +REG64( EX_8_SCAN_LONG_ROTATE , RULL(0x30039000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 31039000, +REG64( EX_9_SCAN_LONG_ROTATE , RULL(0x32039000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 33039000, +REG64( EX_10_SCAN_LONG_ROTATE , RULL(0x34039000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 35039000, +REG64( EX_11_SCAN_LONG_ROTATE , RULL(0x36039000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 37039000, + REG64( C_SCAN_REGION_TYPE , RULL(0x20030005), SH_UNT_C , SH_ACS_SCOM ); REG64( C_0_SCAN_REGION_TYPE , RULL(0x20030005), SH_UNT_C_0 , SH_ACS_SCOM ); REG64( C_1_SCAN_REGION_TYPE , RULL(0x21030005), SH_UNT_C_1 , SH_ACS_SCOM ); @@ -19450,7 +20289,7 @@ REG64( EX_5_SCAN_REGION_TYPE , RULL(0x2A030005 SH_ACS_SCOM ); //DUPS: 2B030005, REG64( EX_6_SCAN_REGION_TYPE , RULL(0x2C030005), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030005, -REG64( EX_7_SCAN_REGION_TYPE , RULL(0x2E030005), SH_UNT_EX_7 , +REG64( EX_7_SCAN_REGION_TYPE , RULL(0x2F030005), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030005, REG64( EX_8_SCAN_REGION_TYPE , RULL(0x30030005), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030005, @@ -19461,6 +20300,124 @@ REG64( EX_10_SCAN_REGION_TYPE , RULL(0x34030005 REG64( EX_11_SCAN_REGION_TYPE , RULL(0x36030005), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37030005, +REG64( C_SCAN_UPDATEDR , RULL(0x2003A000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN_UPDATEDR , RULL(0x2003A000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN_UPDATEDR , RULL(0x2103A000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN_UPDATEDR , RULL(0x2203A000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN_UPDATEDR , RULL(0x2303A000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN_UPDATEDR , RULL(0x2403A000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN_UPDATEDR , RULL(0x2503A000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN_UPDATEDR , RULL(0x2603A000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN_UPDATEDR , RULL(0x2703A000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN_UPDATEDR , RULL(0x2803A000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN_UPDATEDR , RULL(0x2903A000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN_UPDATEDR , RULL(0x2A03A000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN_UPDATEDR , RULL(0x2B03A000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN_UPDATEDR , RULL(0x2C03A000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN_UPDATEDR , RULL(0x2D03A000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN_UPDATEDR , RULL(0x2E03A000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN_UPDATEDR , RULL(0x2F03A000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN_UPDATEDR , RULL(0x3003A000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN_UPDATEDR , RULL(0x3103A000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN_UPDATEDR , RULL(0x3203A000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN_UPDATEDR , RULL(0x3303A000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN_UPDATEDR , RULL(0x3403A000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN_UPDATEDR , RULL(0x3503A000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN_UPDATEDR , RULL(0x3603A000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN_UPDATEDR , RULL(0x3703A000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN_UPDATEDR , RULL(0x1003A000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN_UPDATEDR , RULL(0x1003A000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN_UPDATEDR , RULL(0x1103A000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN_UPDATEDR , RULL(0x1203A000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN_UPDATEDR , RULL(0x1303A000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN_UPDATEDR , RULL(0x1403A000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN_UPDATEDR , RULL(0x1503A000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN_UPDATEDR , RULL(0x2003A000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 2103A000, +REG64( EX_0_SCAN_UPDATEDR , RULL(0x2003A000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 2103A000, +REG64( EX_1_SCAN_UPDATEDR , RULL(0x2203A000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 2303A000, +REG64( EX_2_SCAN_UPDATEDR , RULL(0x2403A000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 2503A000, +REG64( EX_3_SCAN_UPDATEDR , RULL(0x2603A000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 2703A000, +REG64( EX_4_SCAN_UPDATEDR , RULL(0x2803A000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 2903A000, +REG64( EX_5_SCAN_UPDATEDR , RULL(0x2A03A000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B03A000, +REG64( EX_6_SCAN_UPDATEDR , RULL(0x2C03A000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D03A000, +REG64( EX_7_SCAN_UPDATEDR , RULL(0x2F03A000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F03A000, +REG64( EX_8_SCAN_UPDATEDR , RULL(0x3003A000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 3103A000, +REG64( EX_9_SCAN_UPDATEDR , RULL(0x3203A000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 3303A000, +REG64( EX_10_SCAN_UPDATEDR , RULL(0x3403A000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 3503A000, +REG64( EX_11_SCAN_UPDATEDR , RULL(0x3603A000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 3703A000, + +REG64( C_SCAN_UPDATEDR_LONG , RULL(0x2003B000), SH_UNT_C , SH_ACS_SCOM ); +REG64( C_0_SCAN_UPDATEDR_LONG , RULL(0x2003B000), SH_UNT_C_0 , SH_ACS_SCOM ); +REG64( C_1_SCAN_UPDATEDR_LONG , RULL(0x2103B000), SH_UNT_C_1 , SH_ACS_SCOM ); +REG64( C_2_SCAN_UPDATEDR_LONG , RULL(0x2203B000), SH_UNT_C_2 , SH_ACS_SCOM ); +REG64( C_3_SCAN_UPDATEDR_LONG , RULL(0x2303B000), SH_UNT_C_3 , SH_ACS_SCOM ); +REG64( C_4_SCAN_UPDATEDR_LONG , RULL(0x2403B000), SH_UNT_C_4 , SH_ACS_SCOM ); +REG64( C_5_SCAN_UPDATEDR_LONG , RULL(0x2503B000), SH_UNT_C_5 , SH_ACS_SCOM ); +REG64( C_6_SCAN_UPDATEDR_LONG , RULL(0x2603B000), SH_UNT_C_6 , SH_ACS_SCOM ); +REG64( C_7_SCAN_UPDATEDR_LONG , RULL(0x2703B000), SH_UNT_C_7 , SH_ACS_SCOM ); +REG64( C_8_SCAN_UPDATEDR_LONG , RULL(0x2803B000), SH_UNT_C_8 , SH_ACS_SCOM ); +REG64( C_9_SCAN_UPDATEDR_LONG , RULL(0x2903B000), SH_UNT_C_9 , SH_ACS_SCOM ); +REG64( C_10_SCAN_UPDATEDR_LONG , RULL(0x2A03B000), SH_UNT_C_10 , SH_ACS_SCOM ); +REG64( C_11_SCAN_UPDATEDR_LONG , RULL(0x2B03B000), SH_UNT_C_11 , SH_ACS_SCOM ); +REG64( C_12_SCAN_UPDATEDR_LONG , RULL(0x2C03B000), SH_UNT_C_12 , SH_ACS_SCOM ); +REG64( C_13_SCAN_UPDATEDR_LONG , RULL(0x2D03B000), SH_UNT_C_13 , SH_ACS_SCOM ); +REG64( C_14_SCAN_UPDATEDR_LONG , RULL(0x2E03B000), SH_UNT_C_14 , SH_ACS_SCOM ); +REG64( C_15_SCAN_UPDATEDR_LONG , RULL(0x2F03B000), SH_UNT_C_15 , SH_ACS_SCOM ); +REG64( C_16_SCAN_UPDATEDR_LONG , RULL(0x3003B000), SH_UNT_C_16 , SH_ACS_SCOM ); +REG64( C_17_SCAN_UPDATEDR_LONG , RULL(0x3103B000), SH_UNT_C_17 , SH_ACS_SCOM ); +REG64( C_18_SCAN_UPDATEDR_LONG , RULL(0x3203B000), SH_UNT_C_18 , SH_ACS_SCOM ); +REG64( C_19_SCAN_UPDATEDR_LONG , RULL(0x3303B000), SH_UNT_C_19 , SH_ACS_SCOM ); +REG64( C_20_SCAN_UPDATEDR_LONG , RULL(0x3403B000), SH_UNT_C_20 , SH_ACS_SCOM ); +REG64( C_21_SCAN_UPDATEDR_LONG , RULL(0x3503B000), SH_UNT_C_21 , SH_ACS_SCOM ); +REG64( C_22_SCAN_UPDATEDR_LONG , RULL(0x3603B000), SH_UNT_C_22 , SH_ACS_SCOM ); +REG64( C_23_SCAN_UPDATEDR_LONG , RULL(0x3703B000), SH_UNT_C_23 , SH_ACS_SCOM ); +REG64( EQ_SCAN_UPDATEDR_LONG , RULL(0x1003B000), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_SCAN_UPDATEDR_LONG , RULL(0x1003B000), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_SCAN_UPDATEDR_LONG , RULL(0x1103B000), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_SCAN_UPDATEDR_LONG , RULL(0x1203B000), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_SCAN_UPDATEDR_LONG , RULL(0x1303B000), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_SCAN_UPDATEDR_LONG , RULL(0x1403B000), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_SCAN_UPDATEDR_LONG , RULL(0x1503B000), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_SCAN_UPDATEDR_LONG , RULL(0x2003B000), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 2103B000, +REG64( EX_0_SCAN_UPDATEDR_LONG , RULL(0x2003B000), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 2103B000, +REG64( EX_1_SCAN_UPDATEDR_LONG , RULL(0x2203B000), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 2303B000, +REG64( EX_2_SCAN_UPDATEDR_LONG , RULL(0x2403B000), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 2503B000, +REG64( EX_3_SCAN_UPDATEDR_LONG , RULL(0x2603B000), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 2703B000, +REG64( EX_4_SCAN_UPDATEDR_LONG , RULL(0x2803B000), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 2903B000, +REG64( EX_5_SCAN_UPDATEDR_LONG , RULL(0x2A03B000), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2B03B000, +REG64( EX_6_SCAN_UPDATEDR_LONG , RULL(0x2C03B000), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2D03B000, +REG64( EX_7_SCAN_UPDATEDR_LONG , RULL(0x2F03B000), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2F03B000, +REG64( EX_8_SCAN_UPDATEDR_LONG , RULL(0x3003B000), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 3103B000, +REG64( EX_9_SCAN_UPDATEDR_LONG , RULL(0x3203B000), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 3303B000, +REG64( EX_10_SCAN_UPDATEDR_LONG , RULL(0x3403B000), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 3503B000, +REG64( EX_11_SCAN_UPDATEDR_LONG , RULL(0x3603B000), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 3703B000, + REG64( C_SCOMC , RULL(0x20010A80), SH_UNT_C , SH_ACS_SCOM_RW ); REG64( C_0_SCOMC , RULL(0x20010A80), SH_UNT_C_0 , SH_ACS_SCOM_RW ); REG64( C_1_SCOMC , RULL(0x21010A80), SH_UNT_C_1 , SH_ACS_SCOM_RW ); @@ -19486,19 +20443,19 @@ REG64( C_20_SCOMC , RULL(0x34010A80 REG64( C_21_SCOMC , RULL(0x35010A80), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SCOMC , RULL(0x36010A80), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SCOMC , RULL(0x37010A80), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_SCOMC , RULL(0x21010A80), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SCOMC , RULL(0x20010A80), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A80, -REG64( EX_10_L2_SCOMC , RULL(0x35010A80), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SCOMC , RULL(0x34010A80), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010A80, -REG64( EX_11_L2_SCOMC , RULL(0x37010A80), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SCOMC , RULL(0x36010A80), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010A80, -REG64( EX_1_L2_SCOMC , RULL(0x23010A80), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SCOMC , RULL(0x22010A80), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010A80, -REG64( EX_2_L2_SCOMC , RULL(0x25010A80), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SCOMC , RULL(0x24010A80), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010A80, -REG64( EX_3_L2_SCOMC , RULL(0x27010A80), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SCOMC , RULL(0x26010A80), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010A80, -REG64( EX_4_L2_SCOMC , RULL(0x29010A80), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SCOMC , RULL(0x28010A80), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010A80, REG64( EX_5_L2_SCOMC , RULL(0x2B010A80), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010A80, @@ -19506,13 +20463,65 @@ REG64( EX_6_L2_SCOMC , RULL(0x2D010A80 SH_ACS_SCOM_RW ); //DUPS: 2C010A80, REG64( EX_7_L2_SCOMC , RULL(0x2F010A80), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010A80, -REG64( EX_8_L2_SCOMC , RULL(0x31010A80), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SCOMC , RULL(0x30010A80), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010A80, -REG64( EX_9_L2_SCOMC , RULL(0x33010A80), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SCOMC , RULL(0x32010A80), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010A80, -REG64( EX_L2_SCOMC , RULL(0x21010A80), SH_UNT_EX_L2 , +REG64( EX_L2_SCOMC , RULL(0x20010A80), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A80, +REG64( C_SCOMD , RULL(0x20010A81), SH_UNT_C , SH_ACS_SCOM_RW ); +REG64( C_0_SCOMD , RULL(0x20010A81), SH_UNT_C_0 , SH_ACS_SCOM_RW ); +REG64( C_1_SCOMD , RULL(0x21010A81), SH_UNT_C_1 , SH_ACS_SCOM_RW ); +REG64( C_2_SCOMD , RULL(0x22010A81), SH_UNT_C_2 , SH_ACS_SCOM_RW ); +REG64( C_3_SCOMD , RULL(0x23010A81), SH_UNT_C_3 , SH_ACS_SCOM_RW ); +REG64( C_4_SCOMD , RULL(0x24010A81), SH_UNT_C_4 , SH_ACS_SCOM_RW ); +REG64( C_5_SCOMD , RULL(0x25010A81), SH_UNT_C_5 , SH_ACS_SCOM_RW ); +REG64( C_6_SCOMD , RULL(0x26010A81), SH_UNT_C_6 , SH_ACS_SCOM_RW ); +REG64( C_7_SCOMD , RULL(0x27010A81), SH_UNT_C_7 , SH_ACS_SCOM_RW ); +REG64( C_8_SCOMD , RULL(0x28010A81), SH_UNT_C_8 , SH_ACS_SCOM_RW ); +REG64( C_9_SCOMD , RULL(0x29010A81), SH_UNT_C_9 , SH_ACS_SCOM_RW ); +REG64( C_10_SCOMD , RULL(0x2A010A81), SH_UNT_C_10 , SH_ACS_SCOM_RW ); +REG64( C_11_SCOMD , RULL(0x2B010A81), SH_UNT_C_11 , SH_ACS_SCOM_RW ); +REG64( C_12_SCOMD , RULL(0x2C010A81), SH_UNT_C_12 , SH_ACS_SCOM_RW ); +REG64( C_13_SCOMD , RULL(0x2D010A81), SH_UNT_C_13 , SH_ACS_SCOM_RW ); +REG64( C_14_SCOMD , RULL(0x2E010A81), SH_UNT_C_14 , SH_ACS_SCOM_RW ); +REG64( C_15_SCOMD , RULL(0x2F010A81), SH_UNT_C_15 , SH_ACS_SCOM_RW ); +REG64( C_16_SCOMD , RULL(0x30010A81), SH_UNT_C_16 , SH_ACS_SCOM_RW ); +REG64( C_17_SCOMD , RULL(0x31010A81), SH_UNT_C_17 , SH_ACS_SCOM_RW ); +REG64( C_18_SCOMD , RULL(0x32010A81), SH_UNT_C_18 , SH_ACS_SCOM_RW ); +REG64( C_19_SCOMD , RULL(0x33010A81), SH_UNT_C_19 , SH_ACS_SCOM_RW ); +REG64( C_20_SCOMD , RULL(0x34010A81), SH_UNT_C_20 , SH_ACS_SCOM_RW ); +REG64( C_21_SCOMD , RULL(0x35010A81), SH_UNT_C_21 , SH_ACS_SCOM_RW ); +REG64( C_22_SCOMD , RULL(0x36010A81), SH_UNT_C_22 , SH_ACS_SCOM_RW ); +REG64( C_23_SCOMD , RULL(0x37010A81), SH_UNT_C_23 , SH_ACS_SCOM_RW ); +REG64( EX_0_L2_SCOMD , RULL(0x20010A81), SH_UNT_EX_0_L2 , + SH_ACS_SCOM_RW ); //DUPS: 20010A81, +REG64( EX_10_L2_SCOMD , RULL(0x34010A81), SH_UNT_EX_10_L2 , + SH_ACS_SCOM_RW ); //DUPS: 34010A81, +REG64( EX_11_L2_SCOMD , RULL(0x36010A81), SH_UNT_EX_11_L2 , + SH_ACS_SCOM_RW ); //DUPS: 36010A81, +REG64( EX_1_L2_SCOMD , RULL(0x22010A81), SH_UNT_EX_1_L2 , + SH_ACS_SCOM_RW ); //DUPS: 22010A81, +REG64( EX_2_L2_SCOMD , RULL(0x24010A81), SH_UNT_EX_2_L2 , + SH_ACS_SCOM_RW ); //DUPS: 24010A81, +REG64( EX_3_L2_SCOMD , RULL(0x26010A81), SH_UNT_EX_3_L2 , + SH_ACS_SCOM_RW ); //DUPS: 26010A81, +REG64( EX_4_L2_SCOMD , RULL(0x28010A81), SH_UNT_EX_4_L2 , + SH_ACS_SCOM_RW ); //DUPS: 28010A81, +REG64( EX_5_L2_SCOMD , RULL(0x2B010A81), SH_UNT_EX_5_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2A010A81, +REG64( EX_6_L2_SCOMD , RULL(0x2D010A81), SH_UNT_EX_6_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2C010A81, +REG64( EX_7_L2_SCOMD , RULL(0x2F010A81), SH_UNT_EX_7_L2 , + SH_ACS_SCOM_RW ); //DUPS: 2E010A81, +REG64( EX_8_L2_SCOMD , RULL(0x30010A81), SH_UNT_EX_8_L2 , + SH_ACS_SCOM_RW ); //DUPS: 30010A81, +REG64( EX_9_L2_SCOMD , RULL(0x32010A81), SH_UNT_EX_9_L2 , + SH_ACS_SCOM_RW ); //DUPS: 32010A81, +REG64( EX_L2_SCOMD , RULL(0x20010A81), SH_UNT_EX_L2 , + SH_ACS_SCOM_RW ); //DUPS: 20010A81, + REG64( C_SCR0 , RULL(0x20010A86), SH_UNT_C , SH_ACS_SCOM_RW ); REG64( C_0_SCR0 , RULL(0x20010A86), SH_UNT_C_0 , SH_ACS_SCOM_RW ); REG64( C_1_SCR0 , RULL(0x21010A86), SH_UNT_C_1 , SH_ACS_SCOM_RW ); @@ -19538,19 +20547,19 @@ REG64( C_20_SCR0 , RULL(0x34010A86 REG64( C_21_SCR0 , RULL(0x35010A86), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SCR0 , RULL(0x36010A86), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SCR0 , RULL(0x37010A86), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_SCR0 , RULL(0x21010A86), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SCR0 , RULL(0x20010A86), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A86, -REG64( EX_10_L2_SCR0 , RULL(0x35010A86), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SCR0 , RULL(0x34010A86), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010A86, -REG64( EX_11_L2_SCR0 , RULL(0x37010A86), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SCR0 , RULL(0x36010A86), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010A86, -REG64( EX_1_L2_SCR0 , RULL(0x23010A86), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SCR0 , RULL(0x22010A86), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010A86, -REG64( EX_2_L2_SCR0 , RULL(0x25010A86), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SCR0 , RULL(0x24010A86), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010A86, -REG64( EX_3_L2_SCR0 , RULL(0x27010A86), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SCR0 , RULL(0x26010A86), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010A86, -REG64( EX_4_L2_SCR0 , RULL(0x29010A86), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SCR0 , RULL(0x28010A86), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010A86, REG64( EX_5_L2_SCR0 , RULL(0x2B010A86), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010A86, @@ -19558,11 +20567,11 @@ REG64( EX_6_L2_SCR0 , RULL(0x2D010A86 SH_ACS_SCOM_RW ); //DUPS: 2C010A86, REG64( EX_7_L2_SCR0 , RULL(0x2F010A86), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010A86, -REG64( EX_8_L2_SCR0 , RULL(0x31010A86), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SCR0 , RULL(0x30010A86), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010A86, -REG64( EX_9_L2_SCR0 , RULL(0x33010A86), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SCR0 , RULL(0x32010A86), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010A86, -REG64( EX_L2_SCR0 , RULL(0x21010A86), SH_UNT_EX_L2 , +REG64( EX_L2_SCR0 , RULL(0x20010A86), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A86, REG64( C_SCR1 , RULL(0x20010A87), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -19590,19 +20599,19 @@ REG64( C_20_SCR1 , RULL(0x34010A87 REG64( C_21_SCR1 , RULL(0x35010A87), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SCR1 , RULL(0x36010A87), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SCR1 , RULL(0x37010A87), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_SCR1 , RULL(0x21010A87), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SCR1 , RULL(0x20010A87), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A87, -REG64( EX_10_L2_SCR1 , RULL(0x35010A87), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SCR1 , RULL(0x34010A87), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010A87, -REG64( EX_11_L2_SCR1 , RULL(0x37010A87), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SCR1 , RULL(0x36010A87), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010A87, -REG64( EX_1_L2_SCR1 , RULL(0x23010A87), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SCR1 , RULL(0x22010A87), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010A87, -REG64( EX_2_L2_SCR1 , RULL(0x25010A87), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SCR1 , RULL(0x24010A87), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010A87, -REG64( EX_3_L2_SCR1 , RULL(0x27010A87), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SCR1 , RULL(0x26010A87), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010A87, -REG64( EX_4_L2_SCR1 , RULL(0x29010A87), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SCR1 , RULL(0x28010A87), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010A87, REG64( EX_5_L2_SCR1 , RULL(0x2B010A87), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010A87, @@ -19610,11 +20619,11 @@ REG64( EX_6_L2_SCR1 , RULL(0x2D010A87 SH_ACS_SCOM_RW ); //DUPS: 2C010A87, REG64( EX_7_L2_SCR1 , RULL(0x2F010A87), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010A87, -REG64( EX_8_L2_SCR1 , RULL(0x31010A87), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SCR1 , RULL(0x30010A87), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010A87, -REG64( EX_9_L2_SCR1 , RULL(0x33010A87), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SCR1 , RULL(0x32010A87), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010A87, -REG64( EX_L2_SCR1 , RULL(0x21010A87), SH_UNT_EX_L2 , +REG64( EX_L2_SCR1 , RULL(0x20010A87), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010A87, REG64( C_SCR2 , RULL(0x20010A88), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -19642,17 +20651,17 @@ REG64( C_20_SCR2 , RULL(0x34010A88 REG64( C_21_SCR2 , RULL(0x35010A88), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SCR2 , RULL(0x36010A88), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SCR2 , RULL(0x37010A88), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_SCR2 , RULL(0x21010A88), SH_UNT_EX , +REG64( EX_SCR2 , RULL(0x20010A88), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 20010A88, -REG64( EX_0_SCR2 , RULL(0x21010A88), SH_UNT_EX_0 , +REG64( EX_0_SCR2 , RULL(0x20010A88), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 20010A88, -REG64( EX_1_SCR2 , RULL(0x23010A88), SH_UNT_EX_1 , +REG64( EX_1_SCR2 , RULL(0x22010A88), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 22010A88, -REG64( EX_2_SCR2 , RULL(0x25010A88), SH_UNT_EX_2 , +REG64( EX_2_SCR2 , RULL(0x24010A88), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 24010A88, -REG64( EX_3_SCR2 , RULL(0x27010A88), SH_UNT_EX_3 , +REG64( EX_3_SCR2 , RULL(0x26010A88), SH_UNT_EX_3 , SH_ACS_SCOM_RW ); //DUPS: 26010A88, -REG64( EX_4_SCR2 , RULL(0x29010A88), SH_UNT_EX_4 , +REG64( EX_4_SCR2 , RULL(0x28010A88), SH_UNT_EX_4 , SH_ACS_SCOM_RW ); //DUPS: 28010A88, REG64( EX_5_SCR2 , RULL(0x2B010A88), SH_UNT_EX_5 , SH_ACS_SCOM_RW ); //DUPS: 2A010A88, @@ -19660,13 +20669,13 @@ REG64( EX_6_SCR2 , RULL(0x2D010A88 SH_ACS_SCOM_RW ); //DUPS: 2C010A88, REG64( EX_7_SCR2 , RULL(0x2F010A88), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2E010A88, -REG64( EX_8_SCR2 , RULL(0x31010A88), SH_UNT_EX_8 , +REG64( EX_8_SCR2 , RULL(0x30010A88), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 30010A88, -REG64( EX_9_SCR2 , RULL(0x33010A88), SH_UNT_EX_9 , +REG64( EX_9_SCR2 , RULL(0x32010A88), SH_UNT_EX_9 , SH_ACS_SCOM_RW ); //DUPS: 32010A88, -REG64( EX_10_SCR2 , RULL(0x35010A88), SH_UNT_EX_10 , +REG64( EX_10_SCR2 , RULL(0x34010A88), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); //DUPS: 34010A88, -REG64( EX_11_SCR2 , RULL(0x37010A88), SH_UNT_EX_11 , +REG64( EX_11_SCR2 , RULL(0x36010A88), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); //DUPS: 36010A88, REG64( C_SCR3 , RULL(0x20010A89), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -19694,17 +20703,17 @@ REG64( C_20_SCR3 , RULL(0x34010A89 REG64( C_21_SCR3 , RULL(0x35010A89), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SCR3 , RULL(0x36010A89), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SCR3 , RULL(0x37010A89), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_SCR3 , RULL(0x21010A89), SH_UNT_EX , +REG64( EX_SCR3 , RULL(0x20010A89), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 20010A89, -REG64( EX_0_SCR3 , RULL(0x21010A89), SH_UNT_EX_0 , +REG64( EX_0_SCR3 , RULL(0x20010A89), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 20010A89, -REG64( EX_1_SCR3 , RULL(0x23010A89), SH_UNT_EX_1 , +REG64( EX_1_SCR3 , RULL(0x22010A89), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 22010A89, -REG64( EX_2_SCR3 , RULL(0x25010A89), SH_UNT_EX_2 , +REG64( EX_2_SCR3 , RULL(0x24010A89), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 24010A89, -REG64( EX_3_SCR3 , RULL(0x27010A89), SH_UNT_EX_3 , +REG64( EX_3_SCR3 , RULL(0x26010A89), SH_UNT_EX_3 , SH_ACS_SCOM_RW ); //DUPS: 26010A89, -REG64( EX_4_SCR3 , RULL(0x29010A89), SH_UNT_EX_4 , +REG64( EX_4_SCR3 , RULL(0x28010A89), SH_UNT_EX_4 , SH_ACS_SCOM_RW ); //DUPS: 28010A89, REG64( EX_5_SCR3 , RULL(0x2B010A89), SH_UNT_EX_5 , SH_ACS_SCOM_RW ); //DUPS: 2A010A89, @@ -19712,13 +20721,13 @@ REG64( EX_6_SCR3 , RULL(0x2D010A89 SH_ACS_SCOM_RW ); //DUPS: 2C010A89, REG64( EX_7_SCR3 , RULL(0x2F010A89), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2E010A89, -REG64( EX_8_SCR3 , RULL(0x31010A89), SH_UNT_EX_8 , +REG64( EX_8_SCR3 , RULL(0x30010A89), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 30010A89, -REG64( EX_9_SCR3 , RULL(0x33010A89), SH_UNT_EX_9 , +REG64( EX_9_SCR3 , RULL(0x32010A89), SH_UNT_EX_9 , SH_ACS_SCOM_RW ); //DUPS: 32010A89, -REG64( EX_10_SCR3 , RULL(0x35010A89), SH_UNT_EX_10 , +REG64( EX_10_SCR3 , RULL(0x34010A89), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); //DUPS: 34010A89, -REG64( EX_11_SCR3 , RULL(0x37010A89), SH_UNT_EX_11 , +REG64( EX_11_SCR3 , RULL(0x36010A89), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); //DUPS: 36010A89, REG64( C_SHID0 , RULL(0x20010AA5), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -19764,7 +20773,7 @@ REG64( EX_5_L2_SHID0 , RULL(0x2A010AA5 SH_ACS_SCOM_RW ); //DUPS: 2B010AA5, REG64( EX_6_L2_SHID0 , RULL(0x2C010AA5), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RW ); //DUPS: 2D010AA5, -REG64( EX_7_L2_SHID0 , RULL(0x2E010AA5), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_SHID0 , RULL(0x2F010AA5), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2F010AA5, REG64( EX_8_L2_SHID0 , RULL(0x30010AA5), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 31010AA5, @@ -19814,7 +20823,7 @@ REG64( EX_5_SIER_MASK , RULL(0x2A010AAE SH_ACS_SCOM ); //DUPS: 2B010AAE, REG64( EX_6_SIER_MASK , RULL(0x2C010AAE), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010AAE, -REG64( EX_7_SIER_MASK , RULL(0x2E010AAE), SH_UNT_EX_7 , +REG64( EX_7_SIER_MASK , RULL(0x2F010AAE), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010AAE, REG64( EX_8_SIER_MASK , RULL(0x30010AAE), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010AAE, @@ -19873,7 +20882,7 @@ REG64( EX_5_SKITTER_CLKSRC_REG , RULL(0x2A050016 SH_ACS_SCOM ); //DUPS: 2B050016, REG64( EX_6_SKITTER_CLKSRC_REG , RULL(0x2C050016), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D050016, -REG64( EX_7_SKITTER_CLKSRC_REG , RULL(0x2E050016), SH_UNT_EX_7 , +REG64( EX_7_SKITTER_CLKSRC_REG , RULL(0x2F050016), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F050016, REG64( EX_8_SKITTER_CLKSRC_REG , RULL(0x30050016), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31050016, @@ -19932,7 +20941,7 @@ REG64( EX_5_SKITTER_DATA0 , RULL(0x2A050019 SH_ACS_SCOM_RO ); //DUPS: 2B050019, REG64( EX_6_SKITTER_DATA0 , RULL(0x2C050019), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D050019, -REG64( EX_7_SKITTER_DATA0 , RULL(0x2E050019), SH_UNT_EX_7 , +REG64( EX_7_SKITTER_DATA0 , RULL(0x2F050019), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F050019, REG64( EX_8_SKITTER_DATA0 , RULL(0x30050019), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31050019, @@ -19991,7 +21000,7 @@ REG64( EX_5_SKITTER_DATA1 , RULL(0x2A05001A SH_ACS_SCOM_RO ); //DUPS: 2B05001A, REG64( EX_6_SKITTER_DATA1 , RULL(0x2C05001A), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D05001A, -REG64( EX_7_SKITTER_DATA1 , RULL(0x2E05001A), SH_UNT_EX_7 , +REG64( EX_7_SKITTER_DATA1 , RULL(0x2F05001A), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F05001A, REG64( EX_8_SKITTER_DATA1 , RULL(0x3005001A), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 3105001A, @@ -20050,7 +21059,7 @@ REG64( EX_5_SKITTER_DATA2 , RULL(0x2A05001B SH_ACS_SCOM_RO ); //DUPS: 2B05001B, REG64( EX_6_SKITTER_DATA2 , RULL(0x2C05001B), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D05001B, -REG64( EX_7_SKITTER_DATA2 , RULL(0x2E05001B), SH_UNT_EX_7 , +REG64( EX_7_SKITTER_DATA2 , RULL(0x2F05001B), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F05001B, REG64( EX_8_SKITTER_DATA2 , RULL(0x3005001B), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 3105001B, @@ -20109,7 +21118,7 @@ REG64( EX_5_SKITTER_FORCE_REG , RULL(0x2A050014 SH_ACS_SCOM ); //DUPS: 2B050014, REG64( EX_6_SKITTER_FORCE_REG , RULL(0x2C050014), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D050014, -REG64( EX_7_SKITTER_FORCE_REG , RULL(0x2E050014), SH_UNT_EX_7 , +REG64( EX_7_SKITTER_FORCE_REG , RULL(0x2F050014), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F050014, REG64( EX_8_SKITTER_FORCE_REG , RULL(0x30050014), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31050014, @@ -20168,7 +21177,7 @@ REG64( EX_5_SKITTER_MODE_REG , RULL(0x2A050010 SH_ACS_SCOM ); //DUPS: 2B050010, REG64( EX_6_SKITTER_MODE_REG , RULL(0x2C050010), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D050010, -REG64( EX_7_SKITTER_MODE_REG , RULL(0x2E050010), SH_UNT_EX_7 , +REG64( EX_7_SKITTER_MODE_REG , RULL(0x2F050010), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F050010, REG64( EX_8_SKITTER_MODE_REG , RULL(0x30050010), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31050010, @@ -20215,7 +21224,7 @@ REG64( EX_SLAVE_CONFIG_REG , RULL(0x200F001E SH_ACS_SCOM ); //DUPS: 210F001E, REG64( EX_0_SLAVE_CONFIG_REG , RULL(0x200F001E), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F001E, -REG64( EX_1_SLAVE_CONFIG_REG , RULL(0x230F001E), SH_UNT_EX_1 , +REG64( EX_1_SLAVE_CONFIG_REG , RULL(0x220F001E), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F001E, REG64( EX_2_SLAVE_CONFIG_REG , RULL(0x240F001E), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F001E, @@ -20238,71 +21247,71 @@ REG64( EX_10_SLAVE_CONFIG_REG , RULL(0x340F001E REG64( EX_11_SLAVE_CONFIG_REG , RULL(0x360F001E), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 370F001E, -REG64( C_SPATTN_SCOM , RULL(0x20040004), SH_UNT_C , +REG64( C_SPATTN_SCOM , RULL(0x20010A99), SH_UNT_C , SH_ACS_SCOM_RO ); //DUPS: 20010A99, -REG64( C_SPATTN_SCOM1 , RULL(0x20040005), SH_UNT_C , +REG64( C_SPATTN_SCOM1 , RULL(0x20010A98), SH_UNT_C , SH_ACS_SCOM1_NC ); //DUPS: 20010A98, -REG64( C_SPATTN_SCOM2 , RULL(0x20040006), SH_UNT_C , +REG64( C_SPATTN_SCOM2 , RULL(0x20010A97), SH_UNT_C , SH_ACS_SCOM2_NC ); //DUPS: 20010A97, -REG64( C_0_SPATTN_SCOM , RULL(0x20040004), SH_UNT_C_0 , +REG64( C_0_SPATTN_SCOM , RULL(0x20010A99), SH_UNT_C_0 , SH_ACS_SCOM_RO ); //DUPS: 20010A99, -REG64( C_0_SPATTN_SCOM1 , RULL(0x20040005), SH_UNT_C_0 , +REG64( C_0_SPATTN_SCOM1 , RULL(0x20010A98), SH_UNT_C_0 , SH_ACS_SCOM1_NC ); //DUPS: 20010A98, -REG64( C_0_SPATTN_SCOM2 , RULL(0x20040006), SH_UNT_C_0 , +REG64( C_0_SPATTN_SCOM2 , RULL(0x20010A97), SH_UNT_C_0 , SH_ACS_SCOM2_NC ); //DUPS: 20010A97, -REG64( C_1_SPATTN_SCOM , RULL(0x21040004), SH_UNT_C_1 , +REG64( C_1_SPATTN_SCOM , RULL(0x21010A99), SH_UNT_C_1 , SH_ACS_SCOM_RO ); //DUPS: 21010A99, -REG64( C_1_SPATTN_SCOM1 , RULL(0x21040005), SH_UNT_C_1 , +REG64( C_1_SPATTN_SCOM1 , RULL(0x21010A98), SH_UNT_C_1 , SH_ACS_SCOM1_NC ); //DUPS: 21010A98, -REG64( C_1_SPATTN_SCOM2 , RULL(0x21040006), SH_UNT_C_1 , +REG64( C_1_SPATTN_SCOM2 , RULL(0x21010A97), SH_UNT_C_1 , SH_ACS_SCOM2_NC ); //DUPS: 21010A97, -REG64( C_2_SPATTN_SCOM , RULL(0x22040004), SH_UNT_C_2 , +REG64( C_2_SPATTN_SCOM , RULL(0x22010A99), SH_UNT_C_2 , SH_ACS_SCOM_RO ); //DUPS: 22010A99, -REG64( C_2_SPATTN_SCOM1 , RULL(0x22040005), SH_UNT_C_2 , +REG64( C_2_SPATTN_SCOM1 , RULL(0x22010A98), SH_UNT_C_2 , SH_ACS_SCOM1_NC ); //DUPS: 22010A98, -REG64( C_2_SPATTN_SCOM2 , RULL(0x22040006), SH_UNT_C_2 , +REG64( C_2_SPATTN_SCOM2 , RULL(0x22010A97), SH_UNT_C_2 , SH_ACS_SCOM2_NC ); //DUPS: 22010A97, -REG64( C_3_SPATTN_SCOM , RULL(0x23040004), SH_UNT_C_3 , +REG64( C_3_SPATTN_SCOM , RULL(0x23010A99), SH_UNT_C_3 , SH_ACS_SCOM_RO ); //DUPS: 23010A99, -REG64( C_3_SPATTN_SCOM1 , RULL(0x23040005), SH_UNT_C_3 , +REG64( C_3_SPATTN_SCOM1 , RULL(0x23010A98), SH_UNT_C_3 , SH_ACS_SCOM1_NC ); //DUPS: 23010A98, -REG64( C_3_SPATTN_SCOM2 , RULL(0x23040006), SH_UNT_C_3 , +REG64( C_3_SPATTN_SCOM2 , RULL(0x23010A97), SH_UNT_C_3 , SH_ACS_SCOM2_NC ); //DUPS: 23010A97, -REG64( C_4_SPATTN_SCOM , RULL(0x24040004), SH_UNT_C_4 , +REG64( C_4_SPATTN_SCOM , RULL(0x24010A99), SH_UNT_C_4 , SH_ACS_SCOM_RO ); //DUPS: 24010A99, -REG64( C_4_SPATTN_SCOM1 , RULL(0x24040005), SH_UNT_C_4 , +REG64( C_4_SPATTN_SCOM1 , RULL(0x24010A98), SH_UNT_C_4 , SH_ACS_SCOM1_NC ); //DUPS: 24010A98, -REG64( C_4_SPATTN_SCOM2 , RULL(0x24040006), SH_UNT_C_4 , +REG64( C_4_SPATTN_SCOM2 , RULL(0x24010A97), SH_UNT_C_4 , SH_ACS_SCOM2_NC ); //DUPS: 24010A97, -REG64( C_5_SPATTN_SCOM , RULL(0x25040004), SH_UNT_C_5 , +REG64( C_5_SPATTN_SCOM , RULL(0x25010A99), SH_UNT_C_5 , SH_ACS_SCOM_RO ); //DUPS: 25010A99, -REG64( C_5_SPATTN_SCOM1 , RULL(0x25040005), SH_UNT_C_5 , +REG64( C_5_SPATTN_SCOM1 , RULL(0x25010A98), SH_UNT_C_5 , SH_ACS_SCOM1_NC ); //DUPS: 25010A98, -REG64( C_5_SPATTN_SCOM2 , RULL(0x25040006), SH_UNT_C_5 , +REG64( C_5_SPATTN_SCOM2 , RULL(0x25010A97), SH_UNT_C_5 , SH_ACS_SCOM2_NC ); //DUPS: 25010A97, -REG64( C_6_SPATTN_SCOM , RULL(0x26040004), SH_UNT_C_6 , +REG64( C_6_SPATTN_SCOM , RULL(0x26010A99), SH_UNT_C_6 , SH_ACS_SCOM_RO ); //DUPS: 26010A99, -REG64( C_6_SPATTN_SCOM1 , RULL(0x26040005), SH_UNT_C_6 , +REG64( C_6_SPATTN_SCOM1 , RULL(0x26010A98), SH_UNT_C_6 , SH_ACS_SCOM1_NC ); //DUPS: 26010A98, -REG64( C_6_SPATTN_SCOM2 , RULL(0x26040006), SH_UNT_C_6 , +REG64( C_6_SPATTN_SCOM2 , RULL(0x26010A97), SH_UNT_C_6 , SH_ACS_SCOM2_NC ); //DUPS: 26010A97, -REG64( C_7_SPATTN_SCOM , RULL(0x27040004), SH_UNT_C_7 , +REG64( C_7_SPATTN_SCOM , RULL(0x27010A99), SH_UNT_C_7 , SH_ACS_SCOM_RO ); //DUPS: 27010A99, -REG64( C_7_SPATTN_SCOM1 , RULL(0x27040005), SH_UNT_C_7 , +REG64( C_7_SPATTN_SCOM1 , RULL(0x27010A98), SH_UNT_C_7 , SH_ACS_SCOM1_NC ); //DUPS: 27010A98, -REG64( C_7_SPATTN_SCOM2 , RULL(0x27040006), SH_UNT_C_7 , +REG64( C_7_SPATTN_SCOM2 , RULL(0x27010A97), SH_UNT_C_7 , SH_ACS_SCOM2_NC ); //DUPS: 27010A97, -REG64( C_8_SPATTN_SCOM , RULL(0x28040004), SH_UNT_C_8 , +REG64( C_8_SPATTN_SCOM , RULL(0x28010A99), SH_UNT_C_8 , SH_ACS_SCOM_RO ); //DUPS: 28010A99, -REG64( C_8_SPATTN_SCOM1 , RULL(0x28040005), SH_UNT_C_8 , +REG64( C_8_SPATTN_SCOM1 , RULL(0x28010A98), SH_UNT_C_8 , SH_ACS_SCOM1_NC ); //DUPS: 28010A98, -REG64( C_8_SPATTN_SCOM2 , RULL(0x28040006), SH_UNT_C_8 , +REG64( C_8_SPATTN_SCOM2 , RULL(0x28010A97), SH_UNT_C_8 , SH_ACS_SCOM2_NC ); //DUPS: 28010A97, -REG64( C_9_SPATTN_SCOM , RULL(0x29040004), SH_UNT_C_9 , +REG64( C_9_SPATTN_SCOM , RULL(0x29010A99), SH_UNT_C_9 , SH_ACS_SCOM_RO ); //DUPS: 29010A99, -REG64( C_9_SPATTN_SCOM1 , RULL(0x29040005), SH_UNT_C_9 , +REG64( C_9_SPATTN_SCOM1 , RULL(0x29010A98), SH_UNT_C_9 , SH_ACS_SCOM1_NC ); //DUPS: 29010A98, -REG64( C_9_SPATTN_SCOM2 , RULL(0x29040006), SH_UNT_C_9 , +REG64( C_9_SPATTN_SCOM2 , RULL(0x29010A97), SH_UNT_C_9 , SH_ACS_SCOM2_NC ); //DUPS: 29010A97, REG64( C_10_SPATTN_SCOM , RULL(0x2A040004), SH_UNT_C_10 , SH_ACS_SCOM_RO ); //DUPS: 2A010A99, @@ -20328,11 +21337,11 @@ REG64( C_13_SPATTN_SCOM1 , RULL(0x2D040005 SH_ACS_SCOM1_NC ); //DUPS: 2D010A98, REG64( C_13_SPATTN_SCOM2 , RULL(0x2D040006), SH_UNT_C_13 , SH_ACS_SCOM2_NC ); //DUPS: 2D010A97, -REG64( C_14_SPATTN_SCOM , RULL(0x2E040004), SH_UNT_C_14 , +REG64( C_14_SPATTN_SCOM , RULL(0x2E010A99), SH_UNT_C_14 , SH_ACS_SCOM_RO ); //DUPS: 2E010A99, -REG64( C_14_SPATTN_SCOM1 , RULL(0x2E040005), SH_UNT_C_14 , +REG64( C_14_SPATTN_SCOM1 , RULL(0x2E010A98), SH_UNT_C_14 , SH_ACS_SCOM1_NC ); //DUPS: 2E010A98, -REG64( C_14_SPATTN_SCOM2 , RULL(0x2E040006), SH_UNT_C_14 , +REG64( C_14_SPATTN_SCOM2 , RULL(0x2E010A97), SH_UNT_C_14 , SH_ACS_SCOM2_NC ); //DUPS: 2E010A97, REG64( C_15_SPATTN_SCOM , RULL(0x2F040004), SH_UNT_C_15 , SH_ACS_SCOM_RO ); //DUPS: 2F010A99, @@ -20340,53 +21349,53 @@ REG64( C_15_SPATTN_SCOM1 , RULL(0x2F040005 SH_ACS_SCOM1_NC ); //DUPS: 2F010A98, REG64( C_15_SPATTN_SCOM2 , RULL(0x2F040006), SH_UNT_C_15 , SH_ACS_SCOM2_NC ); //DUPS: 2F010A97, -REG64( C_16_SPATTN_SCOM , RULL(0x30040004), SH_UNT_C_16 , +REG64( C_16_SPATTN_SCOM , RULL(0x30010A99), SH_UNT_C_16 , SH_ACS_SCOM_RO ); //DUPS: 30010A99, -REG64( C_16_SPATTN_SCOM1 , RULL(0x30040005), SH_UNT_C_16 , +REG64( C_16_SPATTN_SCOM1 , RULL(0x30010A98), SH_UNT_C_16 , SH_ACS_SCOM1_NC ); //DUPS: 30010A98, -REG64( C_16_SPATTN_SCOM2 , RULL(0x30040006), SH_UNT_C_16 , +REG64( C_16_SPATTN_SCOM2 , RULL(0x30010A97), SH_UNT_C_16 , SH_ACS_SCOM2_NC ); //DUPS: 30010A97, -REG64( C_17_SPATTN_SCOM , RULL(0x31040004), SH_UNT_C_17 , +REG64( C_17_SPATTN_SCOM , RULL(0x31010A99), SH_UNT_C_17 , SH_ACS_SCOM_RO ); //DUPS: 31010A99, -REG64( C_17_SPATTN_SCOM1 , RULL(0x31040005), SH_UNT_C_17 , +REG64( C_17_SPATTN_SCOM1 , RULL(0x31010A98), SH_UNT_C_17 , SH_ACS_SCOM1_NC ); //DUPS: 31010A98, -REG64( C_17_SPATTN_SCOM2 , RULL(0x31040006), SH_UNT_C_17 , +REG64( C_17_SPATTN_SCOM2 , RULL(0x31010A97), SH_UNT_C_17 , SH_ACS_SCOM2_NC ); //DUPS: 31010A97, -REG64( C_18_SPATTN_SCOM , RULL(0x32040004), SH_UNT_C_18 , +REG64( C_18_SPATTN_SCOM , RULL(0x32010A99), SH_UNT_C_18 , SH_ACS_SCOM_RO ); //DUPS: 32010A99, -REG64( C_18_SPATTN_SCOM1 , RULL(0x32040005), SH_UNT_C_18 , +REG64( C_18_SPATTN_SCOM1 , RULL(0x32010A98), SH_UNT_C_18 , SH_ACS_SCOM1_NC ); //DUPS: 32010A98, -REG64( C_18_SPATTN_SCOM2 , RULL(0x32040006), SH_UNT_C_18 , +REG64( C_18_SPATTN_SCOM2 , RULL(0x32010A97), SH_UNT_C_18 , SH_ACS_SCOM2_NC ); //DUPS: 32010A97, -REG64( C_19_SPATTN_SCOM , RULL(0x33040004), SH_UNT_C_19 , +REG64( C_19_SPATTN_SCOM , RULL(0x33010A99), SH_UNT_C_19 , SH_ACS_SCOM_RO ); //DUPS: 33010A99, -REG64( C_19_SPATTN_SCOM1 , RULL(0x33040005), SH_UNT_C_19 , +REG64( C_19_SPATTN_SCOM1 , RULL(0x33010A98), SH_UNT_C_19 , SH_ACS_SCOM1_NC ); //DUPS: 33010A98, -REG64( C_19_SPATTN_SCOM2 , RULL(0x33040006), SH_UNT_C_19 , +REG64( C_19_SPATTN_SCOM2 , RULL(0x33010A97), SH_UNT_C_19 , SH_ACS_SCOM2_NC ); //DUPS: 33010A97, -REG64( C_20_SPATTN_SCOM , RULL(0x34040004), SH_UNT_C_20 , +REG64( C_20_SPATTN_SCOM , RULL(0x34010A99), SH_UNT_C_20 , SH_ACS_SCOM_RO ); //DUPS: 34010A99, -REG64( C_20_SPATTN_SCOM1 , RULL(0x34040005), SH_UNT_C_20 , +REG64( C_20_SPATTN_SCOM1 , RULL(0x34010A98), SH_UNT_C_20 , SH_ACS_SCOM1_NC ); //DUPS: 34010A98, -REG64( C_20_SPATTN_SCOM2 , RULL(0x34040006), SH_UNT_C_20 , +REG64( C_20_SPATTN_SCOM2 , RULL(0x34010A97), SH_UNT_C_20 , SH_ACS_SCOM2_NC ); //DUPS: 34010A97, -REG64( C_21_SPATTN_SCOM , RULL(0x35040004), SH_UNT_C_21 , +REG64( C_21_SPATTN_SCOM , RULL(0x35010A99), SH_UNT_C_21 , SH_ACS_SCOM_RO ); //DUPS: 35010A99, -REG64( C_21_SPATTN_SCOM1 , RULL(0x35040005), SH_UNT_C_21 , +REG64( C_21_SPATTN_SCOM1 , RULL(0x35010A98), SH_UNT_C_21 , SH_ACS_SCOM1_NC ); //DUPS: 35010A98, -REG64( C_21_SPATTN_SCOM2 , RULL(0x35040006), SH_UNT_C_21 , +REG64( C_21_SPATTN_SCOM2 , RULL(0x35010A97), SH_UNT_C_21 , SH_ACS_SCOM2_NC ); //DUPS: 35010A97, -REG64( C_22_SPATTN_SCOM , RULL(0x36040004), SH_UNT_C_22 , +REG64( C_22_SPATTN_SCOM , RULL(0x36010A99), SH_UNT_C_22 , SH_ACS_SCOM_RO ); //DUPS: 36010A99, -REG64( C_22_SPATTN_SCOM1 , RULL(0x36040005), SH_UNT_C_22 , +REG64( C_22_SPATTN_SCOM1 , RULL(0x36010A98), SH_UNT_C_22 , SH_ACS_SCOM1_NC ); //DUPS: 36010A98, -REG64( C_22_SPATTN_SCOM2 , RULL(0x36040006), SH_UNT_C_22 , +REG64( C_22_SPATTN_SCOM2 , RULL(0x36010A97), SH_UNT_C_22 , SH_ACS_SCOM2_NC ); //DUPS: 36010A97, -REG64( C_23_SPATTN_SCOM , RULL(0x37040004), SH_UNT_C_23 , +REG64( C_23_SPATTN_SCOM , RULL(0x37010A99), SH_UNT_C_23 , SH_ACS_SCOM_RO ); //DUPS: 37010A99, -REG64( C_23_SPATTN_SCOM1 , RULL(0x37040005), SH_UNT_C_23 , +REG64( C_23_SPATTN_SCOM1 , RULL(0x37010A98), SH_UNT_C_23 , SH_ACS_SCOM1_NC ); //DUPS: 37010A98, -REG64( C_23_SPATTN_SCOM2 , RULL(0x37040006), SH_UNT_C_23 , +REG64( C_23_SPATTN_SCOM2 , RULL(0x37010A97), SH_UNT_C_23 , SH_ACS_SCOM2_NC ); //DUPS: 37010A97, REG64( EQ_SPATTN_SCOM , RULL(0x10040004), SH_UNT_EQ , SH_ACS_SCOM_RO ); REG64( EQ_SPATTN_SCOM1 , RULL(0x10040005), SH_UNT_EQ , SH_ACS_SCOM1_NC ); @@ -20409,39 +21418,39 @@ REG64( EQ_4_SPATTN_SCOM2 , RULL(0x14040006 REG64( EQ_5_SPATTN_SCOM , RULL(0x15040004), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); REG64( EQ_5_SPATTN_SCOM1 , RULL(0x15040005), SH_UNT_EQ_5 , SH_ACS_SCOM1_NC ); REG64( EQ_5_SPATTN_SCOM2 , RULL(0x15040006), SH_UNT_EQ_5 , SH_ACS_SCOM2_NC ); -REG64( EX_SPATTN_SCOM , RULL(0x20040004), SH_UNT_EX , +REG64( EX_SPATTN_SCOM , RULL(0x20010A99), SH_UNT_EX , SH_ACS_SCOM_RO ); //DUPS: 21040004, 21010A99, 20010A99, -REG64( EX_SPATTN_SCOM1 , RULL(0x20040005), SH_UNT_EX , +REG64( EX_SPATTN_SCOM1 , RULL(0x20010A98), SH_UNT_EX , SH_ACS_SCOM1_NC ); //DUPS: 21040005, 21010A98, 20010A98, REG64( EX_SPATTN_SCOM2 , RULL(0x20040006), SH_UNT_EX , SH_ACS_SCOM2_NC ); //DUPS: 21040006, -REG64( EX_0_SPATTN_SCOM , RULL(0x20040004), SH_UNT_EX_0 , +REG64( EX_0_SPATTN_SCOM , RULL(0x20010A99), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 21040004, 21010A99, 20010A99, -REG64( EX_0_SPATTN_SCOM1 , RULL(0x20040005), SH_UNT_EX_0 , +REG64( EX_0_SPATTN_SCOM1 , RULL(0x20010A98), SH_UNT_EX_0 , SH_ACS_SCOM1_NC ); //DUPS: 21040005, 21010A98, 20010A98, REG64( EX_0_SPATTN_SCOM2 , RULL(0x20040006), SH_UNT_EX_0 , SH_ACS_SCOM2_NC ); //DUPS: 21040006, -REG64( EX_1_SPATTN_SCOM , RULL(0x22040004), SH_UNT_EX_1 , +REG64( EX_1_SPATTN_SCOM , RULL(0x22010A99), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 23040004, 23010A99, 22010A99, -REG64( EX_1_SPATTN_SCOM1 , RULL(0x22040005), SH_UNT_EX_1 , +REG64( EX_1_SPATTN_SCOM1 , RULL(0x22010A98), SH_UNT_EX_1 , SH_ACS_SCOM1_NC ); //DUPS: 23040005, 23010A98, 22010A98, REG64( EX_1_SPATTN_SCOM2 , RULL(0x22040006), SH_UNT_EX_1 , SH_ACS_SCOM2_NC ); //DUPS: 23040006, -REG64( EX_2_SPATTN_SCOM , RULL(0x24040004), SH_UNT_EX_2 , +REG64( EX_2_SPATTN_SCOM , RULL(0x24010A99), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 25040004, 25010A99, 24010A99, -REG64( EX_2_SPATTN_SCOM1 , RULL(0x24040005), SH_UNT_EX_2 , +REG64( EX_2_SPATTN_SCOM1 , RULL(0x24010A98), SH_UNT_EX_2 , SH_ACS_SCOM1_NC ); //DUPS: 25040005, 25010A98, 24010A98, REG64( EX_2_SPATTN_SCOM2 , RULL(0x24040006), SH_UNT_EX_2 , SH_ACS_SCOM2_NC ); //DUPS: 25040006, -REG64( EX_3_SPATTN_SCOM , RULL(0x26040004), SH_UNT_EX_3 , +REG64( EX_3_SPATTN_SCOM , RULL(0x26010A99), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); //DUPS: 27040004, 27010A99, 26010A99, -REG64( EX_3_SPATTN_SCOM1 , RULL(0x26040005), SH_UNT_EX_3 , +REG64( EX_3_SPATTN_SCOM1 , RULL(0x26010A98), SH_UNT_EX_3 , SH_ACS_SCOM1_NC ); //DUPS: 27040005, 27010A98, 26010A98, REG64( EX_3_SPATTN_SCOM2 , RULL(0x26040006), SH_UNT_EX_3 , SH_ACS_SCOM2_NC ); //DUPS: 27040006, -REG64( EX_4_SPATTN_SCOM , RULL(0x28040004), SH_UNT_EX_4 , +REG64( EX_4_SPATTN_SCOM , RULL(0x28010A99), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); //DUPS: 29040004, 29010A99, 28010A99, -REG64( EX_4_SPATTN_SCOM1 , RULL(0x28040005), SH_UNT_EX_4 , +REG64( EX_4_SPATTN_SCOM1 , RULL(0x28010A98), SH_UNT_EX_4 , SH_ACS_SCOM1_NC ); //DUPS: 29040005, 29010A98, 28010A98, REG64( EX_4_SPATTN_SCOM2 , RULL(0x28040006), SH_UNT_EX_4 , SH_ACS_SCOM2_NC ); //DUPS: 29040006, @@ -20457,49 +21466,49 @@ REG64( EX_6_SPATTN_SCOM1 , RULL(0x2C040005 SH_ACS_SCOM1_NC ); //DUPS: 2D040005, 2D010A98, 2C010A98, REG64( EX_6_SPATTN_SCOM2 , RULL(0x2C040006), SH_UNT_EX_6 , SH_ACS_SCOM2_NC ); //DUPS: 2D040006, -REG64( EX_7_SPATTN_SCOM , RULL(0x2E040004), SH_UNT_EX_7 , +REG64( EX_7_SPATTN_SCOM , RULL(0x2F040004), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F040004, 2F010A99, 2E010A99, -REG64( EX_7_SPATTN_SCOM1 , RULL(0x2E040005), SH_UNT_EX_7 , +REG64( EX_7_SPATTN_SCOM1 , RULL(0x2F040005), SH_UNT_EX_7 , SH_ACS_SCOM1_NC ); //DUPS: 2F040005, 2F010A98, 2E010A98, -REG64( EX_7_SPATTN_SCOM2 , RULL(0x2E040006), SH_UNT_EX_7 , +REG64( EX_7_SPATTN_SCOM2 , RULL(0x2F040006), SH_UNT_EX_7 , SH_ACS_SCOM2_NC ); //DUPS: 2F040006, -REG64( EX_8_SPATTN_SCOM , RULL(0x30040004), SH_UNT_EX_8 , +REG64( EX_8_SPATTN_SCOM , RULL(0x30010A99), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 31040004, 31010A99, 30010A99, -REG64( EX_8_SPATTN_SCOM1 , RULL(0x30040005), SH_UNT_EX_8 , +REG64( EX_8_SPATTN_SCOM1 , RULL(0x30010A98), SH_UNT_EX_8 , SH_ACS_SCOM1_NC ); //DUPS: 31040005, 31010A98, 30010A98, REG64( EX_8_SPATTN_SCOM2 , RULL(0x30040006), SH_UNT_EX_8 , SH_ACS_SCOM2_NC ); //DUPS: 31040006, -REG64( EX_9_SPATTN_SCOM , RULL(0x32040004), SH_UNT_EX_9 , +REG64( EX_9_SPATTN_SCOM , RULL(0x32010A99), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); //DUPS: 33040004, 33010A99, 32010A99, -REG64( EX_9_SPATTN_SCOM1 , RULL(0x32040005), SH_UNT_EX_9 , +REG64( EX_9_SPATTN_SCOM1 , RULL(0x32010A98), SH_UNT_EX_9 , SH_ACS_SCOM1_NC ); //DUPS: 33040005, 33010A98, 32010A98, REG64( EX_9_SPATTN_SCOM2 , RULL(0x32040006), SH_UNT_EX_9 , SH_ACS_SCOM2_NC ); //DUPS: 33040006, -REG64( EX_0_L2_SPATTN , RULL(0x21010A97), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SPATTN , RULL(0x20010A97), SH_UNT_EX_0_L2 , SH_ACS_SCOM2_OR ); //DUPS: 20010A97, -REG64( EX_10_SPATTN_SCOM , RULL(0x34040004), SH_UNT_EX_10 , +REG64( EX_10_SPATTN_SCOM , RULL(0x34010A99), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); //DUPS: 35040004, 35010A99, 34010A99, -REG64( EX_10_SPATTN_SCOM1 , RULL(0x34040005), SH_UNT_EX_10 , +REG64( EX_10_SPATTN_SCOM1 , RULL(0x34010A98), SH_UNT_EX_10 , SH_ACS_SCOM1_NC ); //DUPS: 35040005, 35010A98, 34010A98, REG64( EX_10_SPATTN_SCOM2 , RULL(0x34040006), SH_UNT_EX_10 , SH_ACS_SCOM2_NC ); //DUPS: 35040006, -REG64( EX_11_SPATTN_SCOM , RULL(0x36040004), SH_UNT_EX_11 , +REG64( EX_11_SPATTN_SCOM , RULL(0x36010A99), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); //DUPS: 37040004, 37010A99, 36010A99, -REG64( EX_11_SPATTN_SCOM1 , RULL(0x36040005), SH_UNT_EX_11 , +REG64( EX_11_SPATTN_SCOM1 , RULL(0x36010A98), SH_UNT_EX_11 , SH_ACS_SCOM1_NC ); //DUPS: 37040005, 37010A98, 36010A98, REG64( EX_11_SPATTN_SCOM2 , RULL(0x36040006), SH_UNT_EX_11 , SH_ACS_SCOM2_NC ); //DUPS: 37040006, -REG64( EX_10_L2_SPATTN , RULL(0x35010A97), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SPATTN , RULL(0x34010A97), SH_UNT_EX_10_L2 , SH_ACS_SCOM2_OR ); //DUPS: 34010A97, -REG64( EX_11_L2_SPATTN , RULL(0x37010A97), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SPATTN , RULL(0x36010A97), SH_UNT_EX_11_L2 , SH_ACS_SCOM2_OR ); //DUPS: 36010A97, -REG64( EX_1_L2_SPATTN , RULL(0x23010A97), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SPATTN , RULL(0x22010A97), SH_UNT_EX_1_L2 , SH_ACS_SCOM2_OR ); //DUPS: 22010A97, -REG64( EX_2_L2_SPATTN , RULL(0x25010A97), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SPATTN , RULL(0x24010A97), SH_UNT_EX_2_L2 , SH_ACS_SCOM2_OR ); //DUPS: 24010A97, -REG64( EX_3_L2_SPATTN , RULL(0x27010A97), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SPATTN , RULL(0x26010A97), SH_UNT_EX_3_L2 , SH_ACS_SCOM2_OR ); //DUPS: 26010A97, -REG64( EX_4_L2_SPATTN , RULL(0x29010A97), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SPATTN , RULL(0x28010A97), SH_UNT_EX_4_L2 , SH_ACS_SCOM2_OR ); //DUPS: 28010A97, REG64( EX_5_L2_SPATTN , RULL(0x2B010A97), SH_UNT_EX_5_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2A010A97, @@ -20507,11 +21516,11 @@ REG64( EX_6_L2_SPATTN , RULL(0x2D010A97 SH_ACS_SCOM2_OR ); //DUPS: 2C010A97, REG64( EX_7_L2_SPATTN , RULL(0x2F010A97), SH_UNT_EX_7_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2E010A97, -REG64( EX_8_L2_SPATTN , RULL(0x31010A97), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SPATTN , RULL(0x30010A97), SH_UNT_EX_8_L2 , SH_ACS_SCOM2_OR ); //DUPS: 30010A97, -REG64( EX_9_L2_SPATTN , RULL(0x33010A97), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SPATTN , RULL(0x32010A97), SH_UNT_EX_9_L2 , SH_ACS_SCOM2_OR ); //DUPS: 32010A97, -REG64( EX_L2_SPATTN , RULL(0x21010A97), SH_UNT_EX_L2 , +REG64( EX_L2_SPATTN , RULL(0x20010A97), SH_UNT_EX_L2 , SH_ACS_SCOM2_OR ); //DUPS: 20010A97, REG64( C_SPATTN_MASK , RULL(0x20010A9A), SH_UNT_C , SH_ACS_SCOM ); @@ -20539,19 +21548,19 @@ REG64( C_20_SPATTN_MASK , RULL(0x34010A9A REG64( C_21_SPATTN_MASK , RULL(0x35010A9A), SH_UNT_C_21 , SH_ACS_SCOM ); REG64( C_22_SPATTN_MASK , RULL(0x36010A9A), SH_UNT_C_22 , SH_ACS_SCOM ); REG64( C_23_SPATTN_MASK , RULL(0x37010A9A), SH_UNT_C_23 , SH_ACS_SCOM ); -REG64( EX_0_L2_SPATTN_MASK , RULL(0x21010A9A), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SPATTN_MASK , RULL(0x20010A9A), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); //DUPS: 20010A9A, -REG64( EX_10_L2_SPATTN_MASK , RULL(0x35010A9A), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SPATTN_MASK , RULL(0x34010A9A), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); //DUPS: 34010A9A, -REG64( EX_11_L2_SPATTN_MASK , RULL(0x37010A9A), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SPATTN_MASK , RULL(0x36010A9A), SH_UNT_EX_11_L2 , SH_ACS_SCOM ); //DUPS: 36010A9A, -REG64( EX_1_L2_SPATTN_MASK , RULL(0x23010A9A), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SPATTN_MASK , RULL(0x22010A9A), SH_UNT_EX_1_L2 , SH_ACS_SCOM ); //DUPS: 22010A9A, -REG64( EX_2_L2_SPATTN_MASK , RULL(0x25010A9A), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SPATTN_MASK , RULL(0x24010A9A), SH_UNT_EX_2_L2 , SH_ACS_SCOM ); //DUPS: 24010A9A, -REG64( EX_3_L2_SPATTN_MASK , RULL(0x27010A9A), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SPATTN_MASK , RULL(0x26010A9A), SH_UNT_EX_3_L2 , SH_ACS_SCOM ); //DUPS: 26010A9A, -REG64( EX_4_L2_SPATTN_MASK , RULL(0x29010A9A), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SPATTN_MASK , RULL(0x28010A9A), SH_UNT_EX_4_L2 , SH_ACS_SCOM ); //DUPS: 28010A9A, REG64( EX_5_L2_SPATTN_MASK , RULL(0x2B010A9A), SH_UNT_EX_5_L2 , SH_ACS_SCOM ); //DUPS: 2A010A9A, @@ -20559,11 +21568,11 @@ REG64( EX_6_L2_SPATTN_MASK , RULL(0x2D010A9A SH_ACS_SCOM ); //DUPS: 2C010A9A, REG64( EX_7_L2_SPATTN_MASK , RULL(0x2F010A9A), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2E010A9A, -REG64( EX_8_L2_SPATTN_MASK , RULL(0x31010A9A), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SPATTN_MASK , RULL(0x30010A9A), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 30010A9A, -REG64( EX_9_L2_SPATTN_MASK , RULL(0x33010A9A), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SPATTN_MASK , RULL(0x32010A9A), SH_UNT_EX_9_L2 , SH_ACS_SCOM ); //DUPS: 32010A9A, -REG64( EX_L2_SPATTN_MASK , RULL(0x21010A9A), SH_UNT_EX_L2 , +REG64( EX_L2_SPATTN_MASK , RULL(0x20010A9A), SH_UNT_EX_L2 , SH_ACS_SCOM ); //DUPS: 20010A9A, REG64( C_SPA_MASK , RULL(0x20040007), SH_UNT_C , SH_ACS_SCOM ); @@ -20614,7 +21623,7 @@ REG64( EX_5_SPA_MASK , RULL(0x2A040007 SH_ACS_SCOM ); //DUPS: 2B040007, REG64( EX_6_SPA_MASK , RULL(0x2C040007), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040007, -REG64( EX_7_SPA_MASK , RULL(0x2E040007), SH_UNT_EX_7 , +REG64( EX_7_SPA_MASK , RULL(0x2F040007), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040007, REG64( EX_8_SPA_MASK , RULL(0x30040007), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040007, @@ -20650,17 +21659,17 @@ REG64( C_20_SPR_COMMON_HOLD_OUT , RULL(0x34010AB8 REG64( C_21_SPR_COMMON_HOLD_OUT , RULL(0x35010AB8), SH_UNT_C_21 , SH_ACS_SCOM_RO ); REG64( C_22_SPR_COMMON_HOLD_OUT , RULL(0x36010AB8), SH_UNT_C_22 , SH_ACS_SCOM_RO ); REG64( C_23_SPR_COMMON_HOLD_OUT , RULL(0x37010AB8), SH_UNT_C_23 , SH_ACS_SCOM_RO ); -REG64( EX_SPR_COMMON_HOLD_OUT , RULL(0x21010AB8), SH_UNT_EX , +REG64( EX_SPR_COMMON_HOLD_OUT , RULL(0x20010AB8), SH_UNT_EX , SH_ACS_SCOM_RO ); //DUPS: 20010AB8, -REG64( EX_0_SPR_COMMON_HOLD_OUT , RULL(0x21010AB8), SH_UNT_EX_0 , +REG64( EX_0_SPR_COMMON_HOLD_OUT , RULL(0x20010AB8), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 20010AB8, -REG64( EX_1_SPR_COMMON_HOLD_OUT , RULL(0x23010AB8), SH_UNT_EX_1 , +REG64( EX_1_SPR_COMMON_HOLD_OUT , RULL(0x22010AB8), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 22010AB8, -REG64( EX_2_SPR_COMMON_HOLD_OUT , RULL(0x25010AB8), SH_UNT_EX_2 , +REG64( EX_2_SPR_COMMON_HOLD_OUT , RULL(0x24010AB8), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 24010AB8, -REG64( EX_3_SPR_COMMON_HOLD_OUT , RULL(0x27010AB8), SH_UNT_EX_3 , +REG64( EX_3_SPR_COMMON_HOLD_OUT , RULL(0x26010AB8), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); //DUPS: 26010AB8, -REG64( EX_4_SPR_COMMON_HOLD_OUT , RULL(0x29010AB8), SH_UNT_EX_4 , +REG64( EX_4_SPR_COMMON_HOLD_OUT , RULL(0x28010AB8), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); //DUPS: 28010AB8, REG64( EX_5_SPR_COMMON_HOLD_OUT , RULL(0x2B010AB8), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); //DUPS: 2A010AB8, @@ -20668,13 +21677,13 @@ REG64( EX_6_SPR_COMMON_HOLD_OUT , RULL(0x2D010AB8 SH_ACS_SCOM_RO ); //DUPS: 2C010AB8, REG64( EX_7_SPR_COMMON_HOLD_OUT , RULL(0x2F010AB8), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2E010AB8, -REG64( EX_8_SPR_COMMON_HOLD_OUT , RULL(0x31010AB8), SH_UNT_EX_8 , +REG64( EX_8_SPR_COMMON_HOLD_OUT , RULL(0x30010AB8), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 30010AB8, -REG64( EX_9_SPR_COMMON_HOLD_OUT , RULL(0x33010AB8), SH_UNT_EX_9 , +REG64( EX_9_SPR_COMMON_HOLD_OUT , RULL(0x32010AB8), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); //DUPS: 32010AB8, -REG64( EX_10_SPR_COMMON_HOLD_OUT , RULL(0x35010AB8), SH_UNT_EX_10 , +REG64( EX_10_SPR_COMMON_HOLD_OUT , RULL(0x34010AB8), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); //DUPS: 34010AB8, -REG64( EX_11_SPR_COMMON_HOLD_OUT , RULL(0x37010AB8), SH_UNT_EX_11 , +REG64( EX_11_SPR_COMMON_HOLD_OUT , RULL(0x36010AB8), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); //DUPS: 36010AB8, REG64( C_SPR_CORE_HOLD_OUT , RULL(0x20010AB5), SH_UNT_C , SH_ACS_SCOM_RO ); @@ -20720,7 +21729,7 @@ REG64( EX_5_L2_SPR_CORE_HOLD_OUT , RULL(0x2A010AB5 SH_ACS_SCOM_RO ); //DUPS: 2B010AB5, REG64( EX_6_L2_SPR_CORE_HOLD_OUT , RULL(0x2C010AB5), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010AB5, -REG64( EX_7_L2_SPR_CORE_HOLD_OUT , RULL(0x2E010AB5), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_SPR_CORE_HOLD_OUT , RULL(0x2F010AB5), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010AB5, REG64( EX_8_L2_SPR_CORE_HOLD_OUT , RULL(0x30010AB5), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010AB5, @@ -20754,19 +21763,19 @@ REG64( C_20_SPR_MODE , RULL(0x34010A84 REG64( C_21_SPR_MODE , RULL(0x35010A84), SH_UNT_C_21 , SH_ACS_SCOM ); REG64( C_22_SPR_MODE , RULL(0x36010A84), SH_UNT_C_22 , SH_ACS_SCOM ); REG64( C_23_SPR_MODE , RULL(0x37010A84), SH_UNT_C_23 , SH_ACS_SCOM ); -REG64( EX_0_L2_SPR_MODE , RULL(0x21010A84), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SPR_MODE , RULL(0x20010A84), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); //DUPS: 20010A84, -REG64( EX_10_L2_SPR_MODE , RULL(0x35010A84), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SPR_MODE , RULL(0x34010A84), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); //DUPS: 34010A84, -REG64( EX_11_L2_SPR_MODE , RULL(0x37010A84), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SPR_MODE , RULL(0x36010A84), SH_UNT_EX_11_L2 , SH_ACS_SCOM ); //DUPS: 36010A84, -REG64( EX_1_L2_SPR_MODE , RULL(0x23010A84), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SPR_MODE , RULL(0x22010A84), SH_UNT_EX_1_L2 , SH_ACS_SCOM ); //DUPS: 22010A84, -REG64( EX_2_L2_SPR_MODE , RULL(0x25010A84), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SPR_MODE , RULL(0x24010A84), SH_UNT_EX_2_L2 , SH_ACS_SCOM ); //DUPS: 24010A84, -REG64( EX_3_L2_SPR_MODE , RULL(0x27010A84), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SPR_MODE , RULL(0x26010A84), SH_UNT_EX_3_L2 , SH_ACS_SCOM ); //DUPS: 26010A84, -REG64( EX_4_L2_SPR_MODE , RULL(0x29010A84), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SPR_MODE , RULL(0x28010A84), SH_UNT_EX_4_L2 , SH_ACS_SCOM ); //DUPS: 28010A84, REG64( EX_5_L2_SPR_MODE , RULL(0x2B010A84), SH_UNT_EX_5_L2 , SH_ACS_SCOM ); //DUPS: 2A010A84, @@ -20774,11 +21783,11 @@ REG64( EX_6_L2_SPR_MODE , RULL(0x2D010A84 SH_ACS_SCOM ); //DUPS: 2C010A84, REG64( EX_7_L2_SPR_MODE , RULL(0x2F010A84), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2E010A84, -REG64( EX_8_L2_SPR_MODE , RULL(0x31010A84), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SPR_MODE , RULL(0x30010A84), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 30010A84, -REG64( EX_9_L2_SPR_MODE , RULL(0x33010A84), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SPR_MODE , RULL(0x32010A84), SH_UNT_EX_9_L2 , SH_ACS_SCOM ); //DUPS: 32010A84, -REG64( EX_L2_SPR_MODE , RULL(0x21010A84), SH_UNT_EX_L2 , +REG64( EX_L2_SPR_MODE , RULL(0x20010A84), SH_UNT_EX_L2 , SH_ACS_SCOM ); //DUPS: 20010A84, REG64( C_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x20010A9F), SH_UNT_C , SH_ACS_SCOM_RO ); @@ -20806,17 +21815,17 @@ REG64( C_20_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x34010A9F REG64( C_21_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x35010A9F), SH_UNT_C_21 , SH_ACS_SCOM_RO ); REG64( C_22_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x36010A9F), SH_UNT_C_22 , SH_ACS_SCOM_RO ); REG64( C_23_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x37010A9F), SH_UNT_C_23 , SH_ACS_SCOM_RO ); -REG64( EX_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x21010A9F), SH_UNT_EX , +REG64( EX_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x20010A9F), SH_UNT_EX , SH_ACS_SCOM_RO ); //DUPS: 20010A9F, -REG64( EX_0_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x21010A9F), SH_UNT_EX_0 , +REG64( EX_0_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x20010A9F), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 20010A9F, -REG64( EX_1_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x23010A9F), SH_UNT_EX_1 , +REG64( EX_1_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x22010A9F), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 22010A9F, -REG64( EX_2_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x25010A9F), SH_UNT_EX_2 , +REG64( EX_2_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x24010A9F), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 24010A9F, -REG64( EX_3_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x27010A9F), SH_UNT_EX_3 , +REG64( EX_3_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x26010A9F), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); //DUPS: 26010A9F, -REG64( EX_4_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x29010A9F), SH_UNT_EX_4 , +REG64( EX_4_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x28010A9F), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); //DUPS: 28010A9F, REG64( EX_5_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x2B010A9F), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); //DUPS: 2A010A9F, @@ -20824,13 +21833,13 @@ REG64( EX_6_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x2D010A9F SH_ACS_SCOM_RO ); //DUPS: 2C010A9F, REG64( EX_7_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x2F010A9F), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2E010A9F, -REG64( EX_8_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x31010A9F), SH_UNT_EX_8 , +REG64( EX_8_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x30010A9F), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 30010A9F, -REG64( EX_9_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x33010A9F), SH_UNT_EX_9 , +REG64( EX_9_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x32010A9F), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); //DUPS: 32010A9F, -REG64( EX_10_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x35010A9F), SH_UNT_EX_10 , +REG64( EX_10_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x34010A9F), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); //DUPS: 34010A9F, -REG64( EX_11_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x37010A9F), SH_UNT_EX_11 , +REG64( EX_11_SPURR_FREQ_DETECT_CYC_CNT , RULL(0x36010A9F), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); //DUPS: 36010A9F, REG64( C_SPURR_FREQ_REF , RULL(0x20010AA1), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -20858,19 +21867,19 @@ REG64( C_20_SPURR_FREQ_REF , RULL(0x34010AA1 REG64( C_21_SPURR_FREQ_REF , RULL(0x35010AA1), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SPURR_FREQ_REF , RULL(0x36010AA1), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SPURR_FREQ_REF , RULL(0x37010AA1), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_SPURR_FREQ_REF , RULL(0x21010AA1), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SPURR_FREQ_REF , RULL(0x20010AA1), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA1, -REG64( EX_10_L2_SPURR_FREQ_REF , RULL(0x35010AA1), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SPURR_FREQ_REF , RULL(0x34010AA1), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010AA1, -REG64( EX_11_L2_SPURR_FREQ_REF , RULL(0x37010AA1), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SPURR_FREQ_REF , RULL(0x36010AA1), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010AA1, -REG64( EX_1_L2_SPURR_FREQ_REF , RULL(0x23010AA1), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SPURR_FREQ_REF , RULL(0x22010AA1), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010AA1, -REG64( EX_2_L2_SPURR_FREQ_REF , RULL(0x25010AA1), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SPURR_FREQ_REF , RULL(0x24010AA1), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010AA1, -REG64( EX_3_L2_SPURR_FREQ_REF , RULL(0x27010AA1), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SPURR_FREQ_REF , RULL(0x26010AA1), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010AA1, -REG64( EX_4_L2_SPURR_FREQ_REF , RULL(0x29010AA1), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SPURR_FREQ_REF , RULL(0x28010AA1), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010AA1, REG64( EX_5_L2_SPURR_FREQ_REF , RULL(0x2B010AA1), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010AA1, @@ -20878,11 +21887,11 @@ REG64( EX_6_L2_SPURR_FREQ_REF , RULL(0x2D010AA1 SH_ACS_SCOM_RW ); //DUPS: 2C010AA1, REG64( EX_7_L2_SPURR_FREQ_REF , RULL(0x2F010AA1), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010AA1, -REG64( EX_8_L2_SPURR_FREQ_REF , RULL(0x31010AA1), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SPURR_FREQ_REF , RULL(0x30010AA1), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010AA1, -REG64( EX_9_L2_SPURR_FREQ_REF , RULL(0x33010AA1), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SPURR_FREQ_REF , RULL(0x32010AA1), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010AA1, -REG64( EX_L2_SPURR_FREQ_REF , RULL(0x21010AA1), SH_UNT_EX_L2 , +REG64( EX_L2_SPURR_FREQ_REF , RULL(0x20010AA1), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA1, REG64( C_SPURR_FREQ_SCALE , RULL(0x20010AA0), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -20910,19 +21919,19 @@ REG64( C_20_SPURR_FREQ_SCALE , RULL(0x34010AA0 REG64( C_21_SPURR_FREQ_SCALE , RULL(0x35010AA0), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_SPURR_FREQ_SCALE , RULL(0x36010AA0), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_SPURR_FREQ_SCALE , RULL(0x37010AA0), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_SPURR_FREQ_SCALE , RULL(0x21010AA0), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_SPURR_FREQ_SCALE , RULL(0x20010AA0), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA0, -REG64( EX_10_L2_SPURR_FREQ_SCALE , RULL(0x35010AA0), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_SPURR_FREQ_SCALE , RULL(0x34010AA0), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010AA0, -REG64( EX_11_L2_SPURR_FREQ_SCALE , RULL(0x37010AA0), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_SPURR_FREQ_SCALE , RULL(0x36010AA0), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010AA0, -REG64( EX_1_L2_SPURR_FREQ_SCALE , RULL(0x23010AA0), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_SPURR_FREQ_SCALE , RULL(0x22010AA0), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010AA0, -REG64( EX_2_L2_SPURR_FREQ_SCALE , RULL(0x25010AA0), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_SPURR_FREQ_SCALE , RULL(0x24010AA0), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010AA0, -REG64( EX_3_L2_SPURR_FREQ_SCALE , RULL(0x27010AA0), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_SPURR_FREQ_SCALE , RULL(0x26010AA0), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010AA0, -REG64( EX_4_L2_SPURR_FREQ_SCALE , RULL(0x29010AA0), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_SPURR_FREQ_SCALE , RULL(0x28010AA0), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010AA0, REG64( EX_5_L2_SPURR_FREQ_SCALE , RULL(0x2B010AA0), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010AA0, @@ -20930,11 +21939,11 @@ REG64( EX_6_L2_SPURR_FREQ_SCALE , RULL(0x2D010AA0 SH_ACS_SCOM_RW ); //DUPS: 2C010AA0, REG64( EX_7_L2_SPURR_FREQ_SCALE , RULL(0x2F010AA0), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010AA0, -REG64( EX_8_L2_SPURR_FREQ_SCALE , RULL(0x31010AA0), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_SPURR_FREQ_SCALE , RULL(0x30010AA0), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010AA0, -REG64( EX_9_L2_SPURR_FREQ_SCALE , RULL(0x33010AA0), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_SPURR_FREQ_SCALE , RULL(0x32010AA0), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010AA0, -REG64( EX_L2_SPURR_FREQ_SCALE , RULL(0x21010AA0), SH_UNT_EX_L2 , +REG64( EX_L2_SPURR_FREQ_SCALE , RULL(0x20010AA0), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA0, REG64( C_SRC_MASK , RULL(0x20010AAF), SH_UNT_C , SH_ACS_SCOM ); @@ -20978,7 +21987,7 @@ REG64( EX_5_SRC_MASK , RULL(0x2A010AAF SH_ACS_SCOM ); //DUPS: 2B010AAF, REG64( EX_6_SRC_MASK , RULL(0x2C010AAF), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010AAF, -REG64( EX_7_SRC_MASK , RULL(0x2E010AAF), SH_UNT_EX_7 , +REG64( EX_7_SRC_MASK , RULL(0x2F010AAF), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010AAF, REG64( EX_8_SRC_MASK , RULL(0x30010AAF), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010AAF, @@ -21037,7 +22046,7 @@ REG64( EX_5_SUM_MASK_REG , RULL(0x2A040017 SH_ACS_SCOM ); //DUPS: 2B040017, REG64( EX_6_SUM_MASK_REG , RULL(0x2C040017), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040017, -REG64( EX_7_SUM_MASK_REG , RULL(0x2E040017), SH_UNT_EX_7 , +REG64( EX_7_SUM_MASK_REG , RULL(0x2F040017), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040017, REG64( EX_8_SUM_MASK_REG , RULL(0x30040017), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040017, @@ -21096,7 +22105,7 @@ REG64( EX_5_SYNC_CONFIG , RULL(0x2A030000 SH_ACS_SCOM ); //DUPS: 2B030000, REG64( EX_6_SYNC_CONFIG , RULL(0x2C030000), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D030000, -REG64( EX_7_SYNC_CONFIG , RULL(0x2E030000), SH_UNT_EX_7 , +REG64( EX_7_SYNC_CONFIG , RULL(0x2F030000), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F030000, REG64( EX_8_SYNC_CONFIG , RULL(0x30030000), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31030000, @@ -21150,7 +22159,7 @@ REG64( EX_5_L2_T0_PMU_SCOM , RULL(0x2A010AAA SH_ACS_SCOM ); //DUPS: 2B010AAA, REG64( EX_6_L2_T0_PMU_SCOM , RULL(0x2C010AAA), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010AAA, -REG64( EX_7_L2_T0_PMU_SCOM , RULL(0x2E010AAA), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_T0_PMU_SCOM , RULL(0x2F010AAA), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010AAA, REG64( EX_8_L2_T0_PMU_SCOM , RULL(0x30010AAA), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010AAA, @@ -21202,7 +22211,7 @@ REG64( EX_5_L2_T1_PMU_SCOM , RULL(0x2A010AAB SH_ACS_SCOM ); //DUPS: 2B010AAB, REG64( EX_6_L2_T1_PMU_SCOM , RULL(0x2C010AAB), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010AAB, -REG64( EX_7_L2_T1_PMU_SCOM , RULL(0x2E010AAB), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_T1_PMU_SCOM , RULL(0x2F010AAB), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010AAB, REG64( EX_8_L2_T1_PMU_SCOM , RULL(0x30010AAB), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010AAB, @@ -21254,7 +22263,7 @@ REG64( EX_5_L2_T2_PMU_SCOM , RULL(0x2A010AAC SH_ACS_SCOM ); //DUPS: 2B010AAC, REG64( EX_6_L2_T2_PMU_SCOM , RULL(0x2C010AAC), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010AAC, -REG64( EX_7_L2_T2_PMU_SCOM , RULL(0x2E010AAC), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_T2_PMU_SCOM , RULL(0x2F010AAC), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010AAC, REG64( EX_8_L2_T2_PMU_SCOM , RULL(0x30010AAC), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010AAC, @@ -21306,7 +22315,7 @@ REG64( EX_5_L2_T3_PMU_SCOM , RULL(0x2A010AAD SH_ACS_SCOM ); //DUPS: 2B010AAD, REG64( EX_6_L2_T3_PMU_SCOM , RULL(0x2C010AAD), SH_UNT_EX_6_L2 , SH_ACS_SCOM ); //DUPS: 2D010AAD, -REG64( EX_7_L2_T3_PMU_SCOM , RULL(0x2E010AAD), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_T3_PMU_SCOM , RULL(0x2F010AAD), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2F010AAD, REG64( EX_8_L2_T3_PMU_SCOM , RULL(0x30010AAD), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 31010AAD, @@ -21340,19 +22349,19 @@ REG64( C_20_TFAC_HOLD_OUT , RULL(0x34010AB7 REG64( C_21_TFAC_HOLD_OUT , RULL(0x35010AB7), SH_UNT_C_21 , SH_ACS_SCOM_RO ); REG64( C_22_TFAC_HOLD_OUT , RULL(0x36010AB7), SH_UNT_C_22 , SH_ACS_SCOM_RO ); REG64( C_23_TFAC_HOLD_OUT , RULL(0x37010AB7), SH_UNT_C_23 , SH_ACS_SCOM_RO ); -REG64( EX_0_L2_TFAC_HOLD_OUT , RULL(0x21010AB7), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TFAC_HOLD_OUT , RULL(0x20010AB7), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RO ); //DUPS: 20010AB7, -REG64( EX_10_L2_TFAC_HOLD_OUT , RULL(0x35010AB7), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TFAC_HOLD_OUT , RULL(0x34010AB7), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RO ); //DUPS: 34010AB7, -REG64( EX_11_L2_TFAC_HOLD_OUT , RULL(0x37010AB7), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TFAC_HOLD_OUT , RULL(0x36010AB7), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RO ); //DUPS: 36010AB7, -REG64( EX_1_L2_TFAC_HOLD_OUT , RULL(0x23010AB7), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TFAC_HOLD_OUT , RULL(0x22010AB7), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RO ); //DUPS: 22010AB7, -REG64( EX_2_L2_TFAC_HOLD_OUT , RULL(0x25010AB7), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TFAC_HOLD_OUT , RULL(0x24010AB7), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RO ); //DUPS: 24010AB7, -REG64( EX_3_L2_TFAC_HOLD_OUT , RULL(0x27010AB7), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TFAC_HOLD_OUT , RULL(0x26010AB7), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RO ); //DUPS: 26010AB7, -REG64( EX_4_L2_TFAC_HOLD_OUT , RULL(0x29010AB7), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TFAC_HOLD_OUT , RULL(0x28010AB7), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RO ); //DUPS: 28010AB7, REG64( EX_5_L2_TFAC_HOLD_OUT , RULL(0x2B010AB7), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RO ); //DUPS: 2A010AB7, @@ -21360,11 +22369,11 @@ REG64( EX_6_L2_TFAC_HOLD_OUT , RULL(0x2D010AB7 SH_ACS_SCOM_RO ); //DUPS: 2C010AB7, REG64( EX_7_L2_TFAC_HOLD_OUT , RULL(0x2F010AB7), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2E010AB7, -REG64( EX_8_L2_TFAC_HOLD_OUT , RULL(0x31010AB7), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TFAC_HOLD_OUT , RULL(0x30010AB7), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 30010AB7, -REG64( EX_9_L2_TFAC_HOLD_OUT , RULL(0x33010AB7), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TFAC_HOLD_OUT , RULL(0x32010AB7), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RO ); //DUPS: 32010AB7, -REG64( EX_L2_TFAC_HOLD_OUT , RULL(0x21010AB7), SH_UNT_EX_L2 , +REG64( EX_L2_TFAC_HOLD_OUT , RULL(0x20010AB7), SH_UNT_EX_L2 , SH_ACS_SCOM_RO ); //DUPS: 20010AB7, REG64( C_THERM_MODE_REG , RULL(0x2005000F), SH_UNT_C , SH_ACS_SCOM ); @@ -21415,7 +22424,7 @@ REG64( EX_5_THERM_MODE_REG , RULL(0x2A05000F SH_ACS_SCOM ); //DUPS: 2B05000F, REG64( EX_6_THERM_MODE_REG , RULL(0x2C05000F), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D05000F, -REG64( EX_7_THERM_MODE_REG , RULL(0x2E05000F), SH_UNT_EX_7 , +REG64( EX_7_THERM_MODE_REG , RULL(0x2F05000F), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F05000F, REG64( EX_8_THERM_MODE_REG , RULL(0x3005000F), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3105000F, @@ -21469,7 +22478,7 @@ REG64( EX_5_L2_THRCTL_HOLD_OUT , RULL(0x2A010A03 SH_ACS_SCOM_RO ); //DUPS: 2B010A03, REG64( EX_6_L2_THRCTL_HOLD_OUT , RULL(0x2C010A03), SH_UNT_EX_6_L2 , SH_ACS_SCOM_RO ); //DUPS: 2D010A03, -REG64( EX_7_L2_THRCTL_HOLD_OUT , RULL(0x2E010A03), SH_UNT_EX_7_L2 , +REG64( EX_7_L2_THRCTL_HOLD_OUT , RULL(0x2F010A03), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2F010A03, REG64( EX_8_L2_THRCTL_HOLD_OUT , RULL(0x30010A03), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 31010A03, @@ -21503,19 +22512,19 @@ REG64( C_20_THREAD_INFO , RULL(0x34010A9B REG64( C_21_THREAD_INFO , RULL(0x35010A9B), SH_UNT_C_21 , SH_ACS_SCOM ); REG64( C_22_THREAD_INFO , RULL(0x36010A9B), SH_UNT_C_22 , SH_ACS_SCOM ); REG64( C_23_THREAD_INFO , RULL(0x37010A9B), SH_UNT_C_23 , SH_ACS_SCOM ); -REG64( EX_0_L2_THREAD_INFO , RULL(0x21010A9B), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_THREAD_INFO , RULL(0x20010A9B), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); //DUPS: 20010A9B, -REG64( EX_10_L2_THREAD_INFO , RULL(0x35010A9B), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_THREAD_INFO , RULL(0x34010A9B), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); //DUPS: 34010A9B, -REG64( EX_11_L2_THREAD_INFO , RULL(0x37010A9B), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_THREAD_INFO , RULL(0x36010A9B), SH_UNT_EX_11_L2 , SH_ACS_SCOM ); //DUPS: 36010A9B, -REG64( EX_1_L2_THREAD_INFO , RULL(0x23010A9B), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_THREAD_INFO , RULL(0x22010A9B), SH_UNT_EX_1_L2 , SH_ACS_SCOM ); //DUPS: 22010A9B, -REG64( EX_2_L2_THREAD_INFO , RULL(0x25010A9B), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_THREAD_INFO , RULL(0x24010A9B), SH_UNT_EX_2_L2 , SH_ACS_SCOM ); //DUPS: 24010A9B, -REG64( EX_3_L2_THREAD_INFO , RULL(0x27010A9B), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_THREAD_INFO , RULL(0x26010A9B), SH_UNT_EX_3_L2 , SH_ACS_SCOM ); //DUPS: 26010A9B, -REG64( EX_4_L2_THREAD_INFO , RULL(0x29010A9B), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_THREAD_INFO , RULL(0x28010A9B), SH_UNT_EX_4_L2 , SH_ACS_SCOM ); //DUPS: 28010A9B, REG64( EX_5_L2_THREAD_INFO , RULL(0x2B010A9B), SH_UNT_EX_5_L2 , SH_ACS_SCOM ); //DUPS: 2A010A9B, @@ -21523,11 +22532,11 @@ REG64( EX_6_L2_THREAD_INFO , RULL(0x2D010A9B SH_ACS_SCOM ); //DUPS: 2C010A9B, REG64( EX_7_L2_THREAD_INFO , RULL(0x2F010A9B), SH_UNT_EX_7_L2 , SH_ACS_SCOM ); //DUPS: 2E010A9B, -REG64( EX_8_L2_THREAD_INFO , RULL(0x31010A9B), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_THREAD_INFO , RULL(0x30010A9B), SH_UNT_EX_8_L2 , SH_ACS_SCOM ); //DUPS: 30010A9B, -REG64( EX_9_L2_THREAD_INFO , RULL(0x33010A9B), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_THREAD_INFO , RULL(0x32010A9B), SH_UNT_EX_9_L2 , SH_ACS_SCOM ); //DUPS: 32010A9B, -REG64( EX_L2_THREAD_INFO , RULL(0x21010A9B), SH_UNT_EX_L2 , +REG64( EX_L2_THREAD_INFO , RULL(0x20010A9B), SH_UNT_EX_L2 , SH_ACS_SCOM ); //DUPS: 20010A9B, REG64( C_THROTTLE_CONTROL , RULL(0x20010A9E), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -21555,17 +22564,17 @@ REG64( C_20_THROTTLE_CONTROL , RULL(0x34010A9E REG64( C_21_THROTTLE_CONTROL , RULL(0x35010A9E), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_THROTTLE_CONTROL , RULL(0x36010A9E), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_THROTTLE_CONTROL , RULL(0x37010A9E), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_THROTTLE_CONTROL , RULL(0x21010A9E), SH_UNT_EX , +REG64( EX_THROTTLE_CONTROL , RULL(0x20010A9E), SH_UNT_EX , SH_ACS_SCOM_RW ); //DUPS: 20010A9E, -REG64( EX_0_THROTTLE_CONTROL , RULL(0x21010A9E), SH_UNT_EX_0 , +REG64( EX_0_THROTTLE_CONTROL , RULL(0x20010A9E), SH_UNT_EX_0 , SH_ACS_SCOM_RW ); //DUPS: 20010A9E, -REG64( EX_1_THROTTLE_CONTROL , RULL(0x23010A9E), SH_UNT_EX_1 , +REG64( EX_1_THROTTLE_CONTROL , RULL(0x22010A9E), SH_UNT_EX_1 , SH_ACS_SCOM_RW ); //DUPS: 22010A9E, -REG64( EX_2_THROTTLE_CONTROL , RULL(0x25010A9E), SH_UNT_EX_2 , +REG64( EX_2_THROTTLE_CONTROL , RULL(0x24010A9E), SH_UNT_EX_2 , SH_ACS_SCOM_RW ); //DUPS: 24010A9E, -REG64( EX_3_THROTTLE_CONTROL , RULL(0x27010A9E), SH_UNT_EX_3 , +REG64( EX_3_THROTTLE_CONTROL , RULL(0x26010A9E), SH_UNT_EX_3 , SH_ACS_SCOM_RW ); //DUPS: 26010A9E, -REG64( EX_4_THROTTLE_CONTROL , RULL(0x29010A9E), SH_UNT_EX_4 , +REG64( EX_4_THROTTLE_CONTROL , RULL(0x28010A9E), SH_UNT_EX_4 , SH_ACS_SCOM_RW ); //DUPS: 28010A9E, REG64( EX_5_THROTTLE_CONTROL , RULL(0x2B010A9E), SH_UNT_EX_5 , SH_ACS_SCOM_RW ); //DUPS: 2A010A9E, @@ -21573,13 +22582,13 @@ REG64( EX_6_THROTTLE_CONTROL , RULL(0x2D010A9E SH_ACS_SCOM_RW ); //DUPS: 2C010A9E, REG64( EX_7_THROTTLE_CONTROL , RULL(0x2F010A9E), SH_UNT_EX_7 , SH_ACS_SCOM_RW ); //DUPS: 2E010A9E, -REG64( EX_8_THROTTLE_CONTROL , RULL(0x31010A9E), SH_UNT_EX_8 , +REG64( EX_8_THROTTLE_CONTROL , RULL(0x30010A9E), SH_UNT_EX_8 , SH_ACS_SCOM_RW ); //DUPS: 30010A9E, -REG64( EX_9_THROTTLE_CONTROL , RULL(0x33010A9E), SH_UNT_EX_9 , +REG64( EX_9_THROTTLE_CONTROL , RULL(0x32010A9E), SH_UNT_EX_9 , SH_ACS_SCOM_RW ); //DUPS: 32010A9E, -REG64( EX_10_THROTTLE_CONTROL , RULL(0x35010A9E), SH_UNT_EX_10 , +REG64( EX_10_THROTTLE_CONTROL , RULL(0x34010A9E), SH_UNT_EX_10 , SH_ACS_SCOM_RW ); //DUPS: 34010A9E, -REG64( EX_11_THROTTLE_CONTROL , RULL(0x37010A9E), SH_UNT_EX_11 , +REG64( EX_11_THROTTLE_CONTROL , RULL(0x36010A9E), SH_UNT_EX_11 , SH_ACS_SCOM_RW ); //DUPS: 36010A9E, REG64( C_TIMEOUT_REG , RULL(0x200F0010), SH_UNT_C , SH_ACS_SCOM ); @@ -21618,7 +22627,7 @@ REG64( EX_TIMEOUT_REG , RULL(0x200F0010 SH_ACS_SCOM ); //DUPS: 210F0010, REG64( EX_0_TIMEOUT_REG , RULL(0x200F0010), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F0010, -REG64( EX_1_TIMEOUT_REG , RULL(0x230F0010), SH_UNT_EX_1 , +REG64( EX_1_TIMEOUT_REG , RULL(0x220F0010), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F0010, REG64( EX_2_TIMEOUT_REG , RULL(0x240F0010), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F0010, @@ -21689,7 +22698,7 @@ REG64( EX_5_TIMESTAMP_COUNTER_READ , RULL(0x2A05001C SH_ACS_SCOM_RO ); //DUPS: 2B05001C, REG64( EX_6_TIMESTAMP_COUNTER_READ , RULL(0x2C05001C), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); //DUPS: 2D05001C, -REG64( EX_7_TIMESTAMP_COUNTER_READ , RULL(0x2E05001C), SH_UNT_EX_7 , +REG64( EX_7_TIMESTAMP_COUNTER_READ , RULL(0x2F05001C), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); //DUPS: 2F05001C, REG64( EX_8_TIMESTAMP_COUNTER_READ , RULL(0x3005001C), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); //DUPS: 3105001C, @@ -21725,19 +22734,19 @@ REG64( C_20_TOD_READ , RULL(0x34010AA3 REG64( C_21_TOD_READ , RULL(0x35010AA3), SH_UNT_C_21 , SH_ACS_SCOM_RO ); REG64( C_22_TOD_READ , RULL(0x36010AA3), SH_UNT_C_22 , SH_ACS_SCOM_RO ); REG64( C_23_TOD_READ , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM_RO ); -REG64( EX_0_L2_TOD_READ , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_READ , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RO ); //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_READ , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_READ , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RO ); //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_READ , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_READ , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RO ); //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_READ , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_READ , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RO ); //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_READ , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_READ , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RO ); //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_READ , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_READ , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RO ); //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_READ , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_READ , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RO ); //DUPS: 28010AA3, REG64( EX_5_L2_TOD_READ , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RO ); //DUPS: 2A010AA3, @@ -21745,11 +22754,11 @@ REG64( EX_6_L2_TOD_READ , RULL(0x2D010AA3 SH_ACS_SCOM_RO ); //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_READ , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RO ); //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_READ , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_READ , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RO ); //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_READ , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_READ , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RO ); //DUPS: 32010AA3, -REG64( EX_L2_TOD_READ , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_READ , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM_RO ); //DUPS: 20010AA3, REG64( C_TOD_STEP_CHECK , RULL(0x20010AA4), SH_UNT_C , SH_ACS_SCOM_RW ); @@ -21777,19 +22786,19 @@ REG64( C_20_TOD_STEP_CHECK , RULL(0x34010AA4 REG64( C_21_TOD_STEP_CHECK , RULL(0x35010AA4), SH_UNT_C_21 , SH_ACS_SCOM_RW ); REG64( C_22_TOD_STEP_CHECK , RULL(0x36010AA4), SH_UNT_C_22 , SH_ACS_SCOM_RW ); REG64( C_23_TOD_STEP_CHECK , RULL(0x37010AA4), SH_UNT_C_23 , SH_ACS_SCOM_RW ); -REG64( EX_0_L2_TOD_STEP_CHECK , RULL(0x21010AA4), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_STEP_CHECK , RULL(0x20010AA4), SH_UNT_EX_0_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA4, -REG64( EX_10_L2_TOD_STEP_CHECK , RULL(0x35010AA4), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_STEP_CHECK , RULL(0x34010AA4), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW ); //DUPS: 34010AA4, -REG64( EX_11_L2_TOD_STEP_CHECK , RULL(0x37010AA4), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_STEP_CHECK , RULL(0x36010AA4), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW ); //DUPS: 36010AA4, -REG64( EX_1_L2_TOD_STEP_CHECK , RULL(0x23010AA4), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_STEP_CHECK , RULL(0x22010AA4), SH_UNT_EX_1_L2 , SH_ACS_SCOM_RW ); //DUPS: 22010AA4, -REG64( EX_2_L2_TOD_STEP_CHECK , RULL(0x25010AA4), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_STEP_CHECK , RULL(0x24010AA4), SH_UNT_EX_2_L2 , SH_ACS_SCOM_RW ); //DUPS: 24010AA4, -REG64( EX_3_L2_TOD_STEP_CHECK , RULL(0x27010AA4), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_STEP_CHECK , RULL(0x26010AA4), SH_UNT_EX_3_L2 , SH_ACS_SCOM_RW ); //DUPS: 26010AA4, -REG64( EX_4_L2_TOD_STEP_CHECK , RULL(0x29010AA4), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_STEP_CHECK , RULL(0x28010AA4), SH_UNT_EX_4_L2 , SH_ACS_SCOM_RW ); //DUPS: 28010AA4, REG64( EX_5_L2_TOD_STEP_CHECK , RULL(0x2B010AA4), SH_UNT_EX_5_L2 , SH_ACS_SCOM_RW ); //DUPS: 2A010AA4, @@ -21797,11 +22806,11 @@ REG64( EX_6_L2_TOD_STEP_CHECK , RULL(0x2D010AA4 SH_ACS_SCOM_RW ); //DUPS: 2C010AA4, REG64( EX_7_L2_TOD_STEP_CHECK , RULL(0x2F010AA4), SH_UNT_EX_7_L2 , SH_ACS_SCOM_RW ); //DUPS: 2E010AA4, -REG64( EX_8_L2_TOD_STEP_CHECK , RULL(0x31010AA4), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_STEP_CHECK , RULL(0x30010AA4), SH_UNT_EX_8_L2 , SH_ACS_SCOM_RW ); //DUPS: 30010AA4, -REG64( EX_9_L2_TOD_STEP_CHECK , RULL(0x33010AA4), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_STEP_CHECK , RULL(0x32010AA4), SH_UNT_EX_9_L2 , SH_ACS_SCOM_RW ); //DUPS: 32010AA4, -REG64( EX_L2_TOD_STEP_CHECK , RULL(0x21010AA4), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_STEP_CHECK , RULL(0x20010AA4), SH_UNT_EX_L2 , SH_ACS_SCOM_RW ); //DUPS: 20010AA4, REG64( C_TOD_SYNC000 , RULL(0x20010AA3), SH_UNT_C , SH_ACS_SCOM1_WO ); @@ -21830,19 +22839,19 @@ REG64( C_20_TOD_SYNC000 , RULL(0x34010AA3 REG64( C_21_TOD_SYNC000 , RULL(0x35010AA3), SH_UNT_C_21 , SH_ACS_SCOM1_WO ); REG64( C_22_TOD_SYNC000 , RULL(0x36010AA3), SH_UNT_C_22 , SH_ACS_SCOM1_WO ); REG64( C_23_TOD_SYNC000 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); -REG64( EX_0_L2_TOD_SYNC000 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC000 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC000 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC000 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC000 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC000 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC000 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC000 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC000 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC000 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC000 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC000 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC000 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC000 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC000 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //DUPS: 2A010AA3, @@ -21850,11 +22859,11 @@ REG64( EX_6_L2_TOD_SYNC000 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC000 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC000 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC000 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC000 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC000 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC000 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC000 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //DUPS: 20010AA3, REG64( C_TOD_SYNC001 , RULL(0x20010AA3), SH_UNT_C , @@ -21907,19 +22916,19 @@ REG64( C_22_TOD_SYNC001 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC001 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC001 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC001 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC001 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC001 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC001 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC001 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC001 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC001 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC001 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC001 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC001 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC001 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC001 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC001 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC001 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -21927,11 +22936,11 @@ REG64( EX_6_L2_TOD_SYNC001 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC001 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC001 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC001 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC001 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC001 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC001 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC001 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, REG64( C_TOD_SYNC010 , RULL(0x20010AA3), SH_UNT_C , @@ -21984,19 +22993,19 @@ REG64( C_22_TOD_SYNC010 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC010 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC010 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC010 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC010 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC010 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC010 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC010 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC010 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC010 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC010 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC010 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC010 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC010 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC010 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC010 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC010 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -22004,11 +23013,11 @@ REG64( EX_6_L2_TOD_SYNC010 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC010 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC010 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC010 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC010 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC010 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC010 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC010 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, REG64( C_TOD_SYNC011 , RULL(0x20010AA3), SH_UNT_C , @@ -22061,19 +23070,19 @@ REG64( C_22_TOD_SYNC011 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC011 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC011 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC011 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC011 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC011 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC011 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC011 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC011 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC011 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC011 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC011 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC011 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC011 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC011 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC011 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC011 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -22081,11 +23090,11 @@ REG64( EX_6_L2_TOD_SYNC011 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC011 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC011 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC011 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC011 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC011 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC011 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC011 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, REG64( C_TOD_SYNC100 , RULL(0x20010AA3), SH_UNT_C , @@ -22138,19 +23147,19 @@ REG64( C_22_TOD_SYNC100 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC100 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC100 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC100 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC100 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC100 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC100 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC100 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC100 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC100 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC100 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC100 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC100 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC100 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC100 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC100 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC100 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -22158,11 +23167,11 @@ REG64( EX_6_L2_TOD_SYNC100 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC100 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC100 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC100 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC100 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC100 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC100 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC100 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, REG64( C_TOD_SYNC101 , RULL(0x20010AA3), SH_UNT_C , @@ -22215,19 +23224,19 @@ REG64( C_22_TOD_SYNC101 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC101 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC101 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC101 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC101 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC101 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC101 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC101 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC101 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC101 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC101 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC101 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC101 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC101 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC101 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC101 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC101 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -22235,11 +23244,11 @@ REG64( EX_6_L2_TOD_SYNC101 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC101 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC101 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC101 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC101 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC101 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC101 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC101 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, REG64( C_TOD_SYNC110 , RULL(0x20010AA3), SH_UNT_C , @@ -22292,19 +23301,19 @@ REG64( C_22_TOD_SYNC110 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC110 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC110 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC110 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC110 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC110 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC110 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC110 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC110 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC110 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC110 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC110 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC110 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC110 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC110 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC110 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC110 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -22312,11 +23321,11 @@ REG64( EX_6_L2_TOD_SYNC110 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC110 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC110 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC110 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC110 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC110 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC110 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC110 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, REG64( C_TOD_SYNC111 , RULL(0x20010AA3), SH_UNT_C , @@ -22369,19 +23378,19 @@ REG64( C_22_TOD_SYNC111 , RULL(0x36010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( C_23_TOD_SYNC111 , RULL(0x37010AA3), SH_UNT_C_23 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( EX_0_L2_TOD_SYNC111 , RULL(0x21010AA3), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_TOD_SYNC111 , RULL(0x20010AA3), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EX_10_L2_TOD_SYNC111 , RULL(0x35010AA3), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_TOD_SYNC111 , RULL(0x34010AA3), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3, -REG64( EX_11_L2_TOD_SYNC111 , RULL(0x37010AA3), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_TOD_SYNC111 , RULL(0x36010AA3), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3, -REG64( EX_1_L2_TOD_SYNC111 , RULL(0x23010AA3), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_TOD_SYNC111 , RULL(0x22010AA3), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3, -REG64( EX_2_L2_TOD_SYNC111 , RULL(0x25010AA3), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_TOD_SYNC111 , RULL(0x24010AA3), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3, -REG64( EX_3_L2_TOD_SYNC111 , RULL(0x27010AA3), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_TOD_SYNC111 , RULL(0x26010AA3), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3, -REG64( EX_4_L2_TOD_SYNC111 , RULL(0x29010AA3), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_TOD_SYNC111 , RULL(0x28010AA3), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3, REG64( EX_5_L2_TOD_SYNC111 , RULL(0x2B010AA3), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3, @@ -22389,592 +23398,1570 @@ REG64( EX_6_L2_TOD_SYNC111 , RULL(0x2D010AA3 SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3, REG64( EX_7_L2_TOD_SYNC111 , RULL(0x2F010AA3), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3, -REG64( EX_8_L2_TOD_SYNC111 , RULL(0x31010AA3), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_TOD_SYNC111 , RULL(0x30010AA3), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3, -REG64( EX_9_L2_TOD_SYNC111 , RULL(0x33010AA3), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_TOD_SYNC111 , RULL(0x32010AA3), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3, -REG64( EX_L2_TOD_SYNC111 , RULL(0x21010AA3), SH_UNT_EX_L2 , +REG64( EX_L2_TOD_SYNC111 , RULL(0x20010AA3), SH_UNT_EX_L2 , SH_ACS_SCOM1_WO ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3, -REG64( EQ_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012800), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012800), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x11012800), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x12012800), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x13012800), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x14012800), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x15012800), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012800), SH_UNT_EX , SH_ACS_SCOM_RO ); -REG64( EX_0_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012800), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); -REG64( EX_2_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x11012800), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); -REG64( EX_4_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x12012800), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); -REG64( EX_6_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x13012800), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); -REG64( EX_8_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x14012800), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); -REG64( EX_10_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x15012800), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012801), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012801), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x11012801), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x12012801), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x13012801), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x14012801), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x15012801), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012801), SH_UNT_EX , SH_ACS_SCOM_RO ); -REG64( EX_0_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012801), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); -REG64( EX_2_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x11012801), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); -REG64( EX_4_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x12012801), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); -REG64( EX_6_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x13012801), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); -REG64( EX_8_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x14012801), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); -REG64( EX_10_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x15012801), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012802), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012802), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012802), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012802), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012802), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012802), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012802), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012802), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012802), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012802), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012802), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012802), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012802), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012802), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012803), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012803), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012803), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012803), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012803), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012803), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012803), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012803), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012803), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012803), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012803), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012803), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012803), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012803), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012804), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012804), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012804), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012804), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012804), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012804), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012804), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012804), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012804), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012804), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012804), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012804), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012804), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012804), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012805), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012805), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012805), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012805), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012805), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012805), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012805), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012805), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012805), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012805), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012805), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012805), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012805), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012805), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012806), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012806), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012806), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012806), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012806), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012806), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012806), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012806), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012806), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012806), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012806), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012806), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012806), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012806), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012807), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012807), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012807), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012807), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012807), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012807), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012807), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012807), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012807), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012807), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012807), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012807), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012807), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012807), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012808), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012808), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012808), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012808), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012808), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012808), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012808), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012808), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012808), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012808), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012808), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012808), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012808), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012808), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012809), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012809), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012809), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012809), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012809), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012809), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012809), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012809), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012809), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012809), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012809), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012809), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012809), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012809), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012840), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012840), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x11012840), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x12012840), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x13012840), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x14012840), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x15012840), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012840), SH_UNT_EX , SH_ACS_SCOM_RO ); -REG64( EX_0_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012840), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); -REG64( EX_2_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x11012840), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); -REG64( EX_4_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x12012840), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); -REG64( EX_6_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x13012840), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); -REG64( EX_8_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x14012840), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); -REG64( EX_10_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x15012840), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012841), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012841), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x11012841), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x12012841), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x13012841), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x14012841), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x15012841), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012841), SH_UNT_EX , SH_ACS_SCOM_RO ); -REG64( EX_0_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012841), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); -REG64( EX_2_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x11012841), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); -REG64( EX_4_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x12012841), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); -REG64( EX_6_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x13012841), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); -REG64( EX_8_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x14012841), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); -REG64( EX_10_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x15012841), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012842), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012842), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012842), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012842), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012842), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012842), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012842), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012842), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012842), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012842), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012842), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012842), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012842), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012842), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012843), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012843), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012843), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012843), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012843), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012843), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012843), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012843), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012843), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012843), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012843), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012843), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012843), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012843), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012844), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012844), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012844), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012844), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012844), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012844), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012844), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012844), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012844), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012844), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012844), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012844), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012844), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012844), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012845), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012845), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012845), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012845), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012845), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012845), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012845), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012845), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012845), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012845), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012845), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012845), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012845), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012845), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012846), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012846), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012846), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012846), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012846), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012846), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012846), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012846), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012846), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012846), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012846), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012846), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012846), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012846), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012847), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012847), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012847), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012847), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012847), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012847), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012847), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012847), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012847), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012847), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012847), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012847), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012847), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012847), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012848), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012848), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012848), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012848), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012848), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012848), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012848), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012848), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012848), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012848), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012848), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012848), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012848), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012848), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012849), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012849), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012849), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012849), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012849), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012849), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012849), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012849), SH_UNT_EX , SH_ACS_SCOM ); -REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012849), SH_UNT_EX_0 , SH_ACS_SCOM ); -REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012849), SH_UNT_EX_2 , SH_ACS_SCOM ); -REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012849), SH_UNT_EX_4 , SH_ACS_SCOM ); -REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012849), SH_UNT_EX_6 , SH_ACS_SCOM ); -REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012849), SH_UNT_EX_8 , SH_ACS_SCOM ); -REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012849), SH_UNT_EX_10 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x10012C00), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x10012C00), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x11012C00), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x12012C00), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x13012C00), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x14012C00), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x15012C00), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_1_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x10012C00), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); -REG64( EX_3_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x11012C00), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); -REG64( EX_5_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x12012C00), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); -REG64( EX_7_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x13012C00), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); -REG64( EX_9_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x14012C00), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); -REG64( EX_11_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x15012C00), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x10012C01), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x10012C01), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x11012C01), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x12012C01), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x13012C01), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x14012C01), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x15012C01), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_1_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x10012C01), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); -REG64( EX_3_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x11012C01), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); -REG64( EX_5_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x12012C01), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); -REG64( EX_7_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x13012C01), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); -REG64( EX_9_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x14012C01), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); -REG64( EX_11_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x15012C01), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012C02), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012C02), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012C02), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012C02), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012C02), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012C02), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012C02), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012C02), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012C02), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012C02), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012C02), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012C02), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012C02), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012C03), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012C03), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012C03), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012C03), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012C03), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012C03), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012C03), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012C03), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012C03), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012C03), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012C03), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012C03), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012C03), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012C04), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012C04), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012C04), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012C04), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012C04), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012C04), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012C04), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012C04), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012C04), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012C04), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012C04), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012C04), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012C04), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012C05), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012C05), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012C05), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012C05), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012C05), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012C05), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012C05), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012C05), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012C05), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012C05), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012C05), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012C05), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012C05), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012C06), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012C06), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012C06), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012C06), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012C06), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012C06), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012C06), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012C06), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012C06), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012C06), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012C06), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012C06), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012C06), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012C07), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012C07), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012C07), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012C07), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012C07), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012C07), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012C07), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012C07), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012C07), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012C07), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012C07), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012C07), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012C07), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012C08), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012C08), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012C08), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012C08), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012C08), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012C08), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012C08), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012C08), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012C08), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012C08), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012C08), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012C08), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012C08), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012C09), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012C09), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012C09), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012C09), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012C09), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012C09), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012C09), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012C09), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012C09), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012C09), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012C09), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012C09), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012C09), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x10012C40), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x10012C40), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x11012C40), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x12012C40), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x13012C40), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x14012C40), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x15012C40), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_1_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x10012C40), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); -REG64( EX_3_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x11012C40), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); -REG64( EX_5_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x12012C40), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); -REG64( EX_7_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x13012C40), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); -REG64( EX_9_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x14012C40), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); -REG64( EX_11_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x15012C40), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x10012C41), SH_UNT_EQ , SH_ACS_SCOM_RO ); -REG64( EQ_0_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x10012C41), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); -REG64( EQ_1_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x11012C41), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); -REG64( EQ_2_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x12012C41), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); -REG64( EQ_3_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x13012C41), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); -REG64( EQ_4_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x14012C41), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); -REG64( EQ_5_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x15012C41), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); -REG64( EX_1_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x10012C41), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); -REG64( EX_3_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x11012C41), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); -REG64( EX_5_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x12012C41), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); -REG64( EX_7_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x13012C41), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); -REG64( EX_9_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x14012C41), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); -REG64( EX_11_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x15012C41), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); - -REG64( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012C42), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012C42), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012C42), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012C42), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012C42), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012C42), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012C42), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012C42), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012C42), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012C42), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012C42), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012C42), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012C42), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012C43), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012C43), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012C43), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012C43), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012C43), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012C43), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012C43), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012C43), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012C43), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012C43), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012C43), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012C43), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012C43), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012C44), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012C44), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012C44), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012C44), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012C44), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012C44), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012C44), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012C44), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012C44), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012C44), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012C44), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012C44), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012C44), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012C45), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012C45), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012C45), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012C45), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012C45), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012C45), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012C45), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012C45), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012C45), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012C45), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012C45), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012C45), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012C45), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012C46), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012C46), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012C46), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012C46), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012C46), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012C46), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012C46), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012C46), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012C46), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012C46), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012C46), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012C46), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012C46), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012C47), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012C47), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012C47), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012C47), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012C47), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012C47), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012C47), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012C47), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012C47), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012C47), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012C47), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012C47), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012C47), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012C48), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012C48), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012C48), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012C48), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012C48), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012C48), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012C48), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012C48), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012C48), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012C48), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012C48), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012C48), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012C48), SH_UNT_EX_11 , SH_ACS_SCOM ); - -REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012C49), SH_UNT_EQ , SH_ACS_SCOM ); -REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012C49), SH_UNT_EQ_0 , SH_ACS_SCOM ); -REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012C49), SH_UNT_EQ_1 , SH_ACS_SCOM ); -REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012C49), SH_UNT_EQ_2 , SH_ACS_SCOM ); -REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012C49), SH_UNT_EQ_3 , SH_ACS_SCOM ); -REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012C49), SH_UNT_EQ_4 , SH_ACS_SCOM ); -REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012C49), SH_UNT_EQ_5 , SH_ACS_SCOM ); -REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012C49), SH_UNT_EX_1 , SH_ACS_SCOM ); -REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012C49), SH_UNT_EX_3 , SH_ACS_SCOM ); -REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012C49), SH_UNT_EX_5 , SH_ACS_SCOM ); -REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012C49), SH_UNT_EX_7 , SH_ACS_SCOM ); -REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012C49), SH_UNT_EX_9 , SH_ACS_SCOM ); -REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012C49), SH_UNT_EX_11 , SH_ACS_SCOM ); +REG64( EQ_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012900), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012900), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x11012900), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x12012900), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x13012900), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x14012900), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x15012900), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012900), SH_UNT_EX , SH_ACS_SCOM_RO ); +REG64( EX_0_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x10012900), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); +REG64( EX_2_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x11012900), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); +REG64( EX_4_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x12012900), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); +REG64( EX_6_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x13012900), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); +REG64( EX_8_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x14012900), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); +REG64( EX_10_TPLC20_TR0_TRACE_HI_DATA_REG , RULL(0x15012900), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012901), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012901), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x11012901), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x12012901), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x13012901), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x14012901), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x15012901), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012901), SH_UNT_EX , SH_ACS_SCOM_RO ); +REG64( EX_0_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x10012901), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); +REG64( EX_2_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x11012901), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); +REG64( EX_4_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x12012901), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); +REG64( EX_6_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x13012901), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); +REG64( EX_8_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x14012901), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); +REG64( EX_10_TPLC20_TR0_TRACE_LO_DATA_REG , RULL(0x15012901), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012902), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012902), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012902), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012902), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012902), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012902), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012902), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012902), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012902), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012902), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012902), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012902), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012902), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012902), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012903), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012903), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012903), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012903), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012903), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012903), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012903), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012903), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012903), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012903), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012903), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012903), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012903), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012903), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012904), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012904), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012904), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012904), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012904), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012904), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012904), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012904), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012904), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012904), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012904), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012904), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012904), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012904), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012905), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012905), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012905), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012905), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012905), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012905), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012905), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012905), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012905), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012905), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012905), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012905), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012905), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012905), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012906), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012906), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012906), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012906), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012906), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012906), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012906), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012906), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012906), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012906), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012906), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012906), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012906), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012906), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012907), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012907), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012907), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012907), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012907), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012907), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012907), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012907), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012907), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012907), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012907), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012907), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012907), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012907), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012908), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012908), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012908), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012908), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012908), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012908), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012908), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012908), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012908), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012908), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012908), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012908), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012908), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012908), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012909), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012909), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012909), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012909), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012909), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012909), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012909), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012909), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012909), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012909), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012909), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012909), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012909), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012909), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012940), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012940), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x11012940), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x12012940), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x13012940), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x14012940), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x15012940), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012940), SH_UNT_EX , SH_ACS_SCOM_RO ); +REG64( EX_0_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x10012940), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); +REG64( EX_2_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x11012940), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); +REG64( EX_4_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x12012940), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); +REG64( EX_6_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x13012940), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); +REG64( EX_8_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x14012940), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); +REG64( EX_10_TPLC20_TR1_TRACE_HI_DATA_REG , RULL(0x15012940), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012941), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012941), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x11012941), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x12012941), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x13012941), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x14012941), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x15012941), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012941), SH_UNT_EX , SH_ACS_SCOM_RO ); +REG64( EX_0_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x10012941), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); +REG64( EX_2_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x11012941), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); +REG64( EX_4_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x12012941), SH_UNT_EX_4 , SH_ACS_SCOM_RO ); +REG64( EX_6_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x13012941), SH_UNT_EX_6 , SH_ACS_SCOM_RO ); +REG64( EX_8_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x14012941), SH_UNT_EX_8 , SH_ACS_SCOM_RO ); +REG64( EX_10_TPLC20_TR1_TRACE_LO_DATA_REG , RULL(0x15012941), SH_UNT_EX_10 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012942), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012942), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012942), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012942), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012942), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012942), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012942), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012942), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012942), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012942), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012942), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012942), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012942), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012942), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012943), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012943), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012943), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012943), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012943), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012943), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012943), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012943), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012943), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012943), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012943), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012943), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012943), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012943), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012944), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012944), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012944), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012944), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012944), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012944), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012944), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012944), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012944), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012944), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012944), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012944), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012944), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012944), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012945), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012945), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012945), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012945), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012945), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012945), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012945), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012945), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012945), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012945), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012945), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012945), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012945), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012945), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012946), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012946), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012946), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012946), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012946), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012946), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012946), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012946), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012946), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012946), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012946), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012946), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012946), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012946), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012947), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012947), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012947), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012947), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012947), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012947), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012947), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012947), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012947), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012947), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012947), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012947), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012947), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012947), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012948), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012948), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012948), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012948), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012948), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012948), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012948), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012948), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012948), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012948), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012948), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012948), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012948), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012948), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012949), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012949), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012949), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012949), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012949), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012949), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012949), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012949), SH_UNT_EX , SH_ACS_SCOM ); +REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012949), SH_UNT_EX_0 , SH_ACS_SCOM ); +REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012949), SH_UNT_EX_2 , SH_ACS_SCOM ); +REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012949), SH_UNT_EX_4 , SH_ACS_SCOM ); +REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012949), SH_UNT_EX_6 , SH_ACS_SCOM ); +REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012949), SH_UNT_EX_8 , SH_ACS_SCOM ); +REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012949), SH_UNT_EX_10 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x10012D00), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x10012D00), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x11012D00), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x12012D00), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x13012D00), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x14012D00), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x15012D00), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_1_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x10012D00), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); +REG64( EX_3_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x11012D00), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); +REG64( EX_5_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x12012D00), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); +REG64( EX_7_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x13012D00), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); +REG64( EX_9_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x14012D00), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); +REG64( EX_11_TPLC21_TR0_TRACE_HI_DATA_REG , RULL(0x15012D00), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x10012D01), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x10012D01), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x11012D01), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x12012D01), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x13012D01), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x14012D01), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x15012D01), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_1_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x10012D01), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); +REG64( EX_3_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x11012D01), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); +REG64( EX_5_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x12012D01), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); +REG64( EX_7_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x13012D01), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); +REG64( EX_9_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x14012D01), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); +REG64( EX_11_TPLC21_TR0_TRACE_LO_DATA_REG , RULL(0x15012D01), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012D02), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012D02), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012D02), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012D02), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012D02), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012D02), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012D02), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x10012D02), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x11012D02), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x12012D02), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x13012D02), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x14012D02), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRCTRL_CONFIG , RULL(0x15012D02), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012D03), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012D03), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012D03), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012D03), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012D03), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012D03), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012D03), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x10012D03), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x11012D03), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x12012D03), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x13012D03), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x14012D03), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x15012D03), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012D04), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012D04), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012D04), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012D04), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012D04), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012D04), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012D04), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x10012D04), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x11012D04), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x12012D04), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x13012D04), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x14012D04), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x15012D04), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012D05), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012D05), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012D05), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012D05), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012D05), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012D05), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012D05), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x10012D05), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x11012D05), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x12012D05), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x13012D05), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x14012D05), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x15012D05), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012D06), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012D06), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012D06), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012D06), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012D06), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012D06), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012D06), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x10012D06), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x11012D06), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x12012D06), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x13012D06), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x14012D06), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x15012D06), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012D07), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012D07), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012D07), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012D07), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012D07), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012D07), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012D07), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x10012D07), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x11012D07), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x12012D07), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x13012D07), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x14012D07), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x15012D07), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012D08), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012D08), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012D08), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012D08), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012D08), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012D08), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012D08), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x10012D08), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x11012D08), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x12012D08), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x13012D08), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x14012D08), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x15012D08), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012D09), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012D09), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012D09), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012D09), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012D09), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012D09), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012D09), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x10012D09), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x11012D09), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x12012D09), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x13012D09), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x14012D09), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x15012D09), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x10012D40), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x10012D40), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x11012D40), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x12012D40), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x13012D40), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x14012D40), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x15012D40), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_1_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x10012D40), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); +REG64( EX_3_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x11012D40), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); +REG64( EX_5_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x12012D40), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); +REG64( EX_7_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x13012D40), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); +REG64( EX_9_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x14012D40), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); +REG64( EX_11_TPLC21_TR1_TRACE_HI_DATA_REG , RULL(0x15012D40), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x10012D41), SH_UNT_EQ , SH_ACS_SCOM_RO ); +REG64( EQ_0_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x10012D41), SH_UNT_EQ_0 , SH_ACS_SCOM_RO ); +REG64( EQ_1_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x11012D41), SH_UNT_EQ_1 , SH_ACS_SCOM_RO ); +REG64( EQ_2_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x12012D41), SH_UNT_EQ_2 , SH_ACS_SCOM_RO ); +REG64( EQ_3_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x13012D41), SH_UNT_EQ_3 , SH_ACS_SCOM_RO ); +REG64( EQ_4_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x14012D41), SH_UNT_EQ_4 , SH_ACS_SCOM_RO ); +REG64( EQ_5_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x15012D41), SH_UNT_EQ_5 , SH_ACS_SCOM_RO ); +REG64( EX_1_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x10012D41), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); +REG64( EX_3_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x11012D41), SH_UNT_EX_3 , SH_ACS_SCOM_RO ); +REG64( EX_5_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x12012D41), SH_UNT_EX_5 , SH_ACS_SCOM_RO ); +REG64( EX_7_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x13012D41), SH_UNT_EX_7 , SH_ACS_SCOM_RO ); +REG64( EX_9_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x14012D41), SH_UNT_EX_9 , SH_ACS_SCOM_RO ); +REG64( EX_11_TPLC21_TR1_TRACE_LO_DATA_REG , RULL(0x15012D41), SH_UNT_EX_11 , SH_ACS_SCOM_RO ); + +REG64( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012D42), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012D42), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012D42), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012D42), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012D42), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012D42), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012D42), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x10012D42), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x11012D42), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x12012D42), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x13012D42), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x14012D42), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRCTRL_CONFIG , RULL(0x15012D42), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012D43), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012D43), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012D43), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012D43), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012D43), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012D43), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012D43), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x10012D43), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x11012D43), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x12012D43), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x13012D43), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x14012D43), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x15012D43), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012D44), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012D44), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012D44), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012D44), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012D44), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012D44), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012D44), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x10012D44), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x11012D44), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x12012D44), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x13012D44), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x14012D44), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x15012D44), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012D45), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012D45), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012D45), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012D45), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012D45), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012D45), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012D45), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x10012D45), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x11012D45), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x12012D45), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x13012D45), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x14012D45), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x15012D45), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012D46), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012D46), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012D46), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012D46), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012D46), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012D46), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012D46), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x10012D46), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x11012D46), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x12012D46), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x13012D46), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x14012D46), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x15012D46), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012D47), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012D47), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012D47), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012D47), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012D47), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012D47), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012D47), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x10012D47), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x11012D47), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x12012D47), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x13012D47), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x14012D47), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x15012D47), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012D48), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012D48), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012D48), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012D48), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012D48), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012D48), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012D48), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x10012D48), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x11012D48), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x12012D48), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x13012D48), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x14012D48), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x15012D48), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012D49), SH_UNT_EQ , SH_ACS_SCOM ); +REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012D49), SH_UNT_EQ_0 , SH_ACS_SCOM ); +REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012D49), SH_UNT_EQ_1 , SH_ACS_SCOM ); +REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012D49), SH_UNT_EQ_2 , SH_ACS_SCOM ); +REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012D49), SH_UNT_EQ_3 , SH_ACS_SCOM ); +REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012D49), SH_UNT_EQ_4 , SH_ACS_SCOM ); +REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012D49), SH_UNT_EQ_5 , SH_ACS_SCOM ); +REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x10012D49), SH_UNT_EX_1 , SH_ACS_SCOM ); +REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x11012D49), SH_UNT_EX_3 , SH_ACS_SCOM ); +REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x12012D49), SH_UNT_EX_5 , SH_ACS_SCOM ); +REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x13012D49), SH_UNT_EX_7 , SH_ACS_SCOM ); +REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x14012D49), SH_UNT_EX_9 , SH_ACS_SCOM ); +REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x15012D49), SH_UNT_EX_11 , SH_ACS_SCOM ); + +REG64( C_TRACE_HI_DATA_REG , RULL(0x20011C00), SH_UNT_C , + SH_ACS_SCOM_RO ); //DUPS: 20011440, 20011C00, +REG64( C_0_TRACE_HI_DATA_REG , RULL(0x20011C00), SH_UNT_C_0 , + SH_ACS_SCOM_RO ); //DUPS: 20011440, 20011C00, +REG64( C_1_TRACE_HI_DATA_REG , RULL(0x21011C00), SH_UNT_C_1 , + SH_ACS_SCOM_RO ); //DUPS: 21011440, 21011C00, +REG64( C_2_TRACE_HI_DATA_REG , RULL(0x22011C00), SH_UNT_C_2 , + SH_ACS_SCOM_RO ); //DUPS: 22011440, 22011C00, +REG64( C_3_TRACE_HI_DATA_REG , RULL(0x23011C00), SH_UNT_C_3 , + SH_ACS_SCOM_RO ); //DUPS: 23011440, 23011C00, +REG64( C_4_TRACE_HI_DATA_REG , RULL(0x24011C00), SH_UNT_C_4 , + SH_ACS_SCOM_RO ); //DUPS: 24011440, 24011C00, +REG64( C_5_TRACE_HI_DATA_REG , RULL(0x25011C00), SH_UNT_C_5 , + SH_ACS_SCOM_RO ); //DUPS: 25011440, 25011C00, +REG64( C_6_TRACE_HI_DATA_REG , RULL(0x26011C00), SH_UNT_C_6 , + SH_ACS_SCOM_RO ); //DUPS: 26011440, 26011C00, +REG64( C_7_TRACE_HI_DATA_REG , RULL(0x27011C00), SH_UNT_C_7 , + SH_ACS_SCOM_RO ); //DUPS: 27011440, 27011C00, +REG64( C_8_TRACE_HI_DATA_REG , RULL(0x28011C00), SH_UNT_C_8 , + SH_ACS_SCOM_RO ); //DUPS: 28011440, 28011C00, +REG64( C_9_TRACE_HI_DATA_REG , RULL(0x29011C00), SH_UNT_C_9 , + SH_ACS_SCOM_RO ); //DUPS: 29011440, 29011C00, +REG64( C_10_TRACE_HI_DATA_REG , RULL(0x2A011480), SH_UNT_C_10 , + SH_ACS_SCOM_RO ); //DUPS: 2A011440, 2A011C00, +REG64( C_11_TRACE_HI_DATA_REG , RULL(0x2B011480), SH_UNT_C_11 , + SH_ACS_SCOM_RO ); //DUPS: 2B011440, 2B011C00, +REG64( C_12_TRACE_HI_DATA_REG , RULL(0x2C011480), SH_UNT_C_12 , + SH_ACS_SCOM_RO ); //DUPS: 2C011440, 2C011C00, +REG64( C_13_TRACE_HI_DATA_REG , RULL(0x2D011480), SH_UNT_C_13 , + SH_ACS_SCOM_RO ); //DUPS: 2D011440, 2D011C00, +REG64( C_14_TRACE_HI_DATA_REG , RULL(0x2E011C00), SH_UNT_C_14 , + SH_ACS_SCOM_RO ); //DUPS: 2E011440, 2E011C00, +REG64( C_15_TRACE_HI_DATA_REG , RULL(0x2F011480), SH_UNT_C_15 , + SH_ACS_SCOM_RO ); //DUPS: 2F011440, 2F011C00, +REG64( C_16_TRACE_HI_DATA_REG , RULL(0x30011C00), SH_UNT_C_16 , + SH_ACS_SCOM_RO ); //DUPS: 30011440, 30011C00, +REG64( C_17_TRACE_HI_DATA_REG , RULL(0x31011C00), SH_UNT_C_17 , + SH_ACS_SCOM_RO ); //DUPS: 31011440, 31011C00, +REG64( C_18_TRACE_HI_DATA_REG , RULL(0x32011C00), SH_UNT_C_18 , + SH_ACS_SCOM_RO ); //DUPS: 32011440, 32011C00, +REG64( C_19_TRACE_HI_DATA_REG , RULL(0x33011C00), SH_UNT_C_19 , + SH_ACS_SCOM_RO ); //DUPS: 33011440, 33011C00, +REG64( C_20_TRACE_HI_DATA_REG , RULL(0x34011C00), SH_UNT_C_20 , + SH_ACS_SCOM_RO ); //DUPS: 34011440, 34011C00, +REG64( C_21_TRACE_HI_DATA_REG , RULL(0x35011C00), SH_UNT_C_21 , + SH_ACS_SCOM_RO ); //DUPS: 35011440, 35011C00, +REG64( C_22_TRACE_HI_DATA_REG , RULL(0x36011C00), SH_UNT_C_22 , + SH_ACS_SCOM_RO ); //DUPS: 36011440, 36011C00, +REG64( C_23_TRACE_HI_DATA_REG , RULL(0x37011C00), SH_UNT_C_23 , + SH_ACS_SCOM_RO ); //DUPS: 37011440, 37011C00, +REG64( EX_TRACE_HI_DATA_REG , RULL(0x20011440), SH_UNT_EX , + SH_ACS_SCOM_RO ); //DUPS: 20011440, 21011480, 21011440, +REG64( EX_0_TRACE_HI_DATA_REG , RULL(0x20011440), SH_UNT_EX_0 , + SH_ACS_SCOM_RO ); //DUPS: 20011440, 21011480, 21011440, +REG64( EX_1_TRACE_HI_DATA_REG , RULL(0x22011440), SH_UNT_EX_1 , + SH_ACS_SCOM_RO ); //DUPS: 22011440, 23011480, 23011440, +REG64( EX_2_TRACE_HI_DATA_REG , RULL(0x24011440), SH_UNT_EX_2 , + SH_ACS_SCOM_RO ); //DUPS: 24011440, 25011480, 25011440, +REG64( EX_3_TRACE_HI_DATA_REG , RULL(0x26011440), SH_UNT_EX_3 , + SH_ACS_SCOM_RO ); //DUPS: 26011440, 27011480, 27011440, +REG64( EX_4_TRACE_HI_DATA_REG , RULL(0x28011440), SH_UNT_EX_4 , + SH_ACS_SCOM_RO ); //DUPS: 28011440, 29011480, 29011440, +REG64( EX_5_TRACE_HI_DATA_REG , RULL(0x2A011480), SH_UNT_EX_5 , + SH_ACS_SCOM_RO ); //DUPS: 2A011440, 2B011480, 2B011440, +REG64( EX_6_TRACE_HI_DATA_REG , RULL(0x2C011480), SH_UNT_EX_6 , + SH_ACS_SCOM_RO ); //DUPS: 2C011440, 2D011480, 2D011440, +REG64( EX_7_TRACE_HI_DATA_REG , RULL(0x2F011480), SH_UNT_EX_7 , + SH_ACS_SCOM_RO ); //DUPS: 2E011440, 2F011480, 2F011440, +REG64( EX_8_TRACE_HI_DATA_REG , RULL(0x30011440), SH_UNT_EX_8 , + SH_ACS_SCOM_RO ); //DUPS: 30011440, 31011480, 31011440, +REG64( EX_9_TRACE_HI_DATA_REG , RULL(0x32011440), SH_UNT_EX_9 , + SH_ACS_SCOM_RO ); //DUPS: 32011440, 33011480, 33011440, +REG64( EX_0_L3_TRACE_HI_DATA_REG , RULL(0x20011C00), SH_UNT_EX_0_L3 , + SH_ACS_SCOM_RO ); //DUPS: 21011C00, +REG64( EX_10_TRACE_HI_DATA_REG , RULL(0x34011440), SH_UNT_EX_10 , + SH_ACS_SCOM_RO ); //DUPS: 34011440, 35011480, 35011440, +REG64( EX_11_TRACE_HI_DATA_REG , RULL(0x36011440), SH_UNT_EX_11 , + SH_ACS_SCOM_RO ); //DUPS: 36011440, 37011480, 37011440, +REG64( EX_10_L3_TRACE_HI_DATA_REG , RULL(0x34011C00), SH_UNT_EX_10_L3 , + SH_ACS_SCOM_RO ); //DUPS: 35011C00, +REG64( EX_11_L3_TRACE_HI_DATA_REG , RULL(0x36011C00), SH_UNT_EX_11_L3 , + SH_ACS_SCOM_RO ); //DUPS: 37011C00, +REG64( EX_1_L3_TRACE_HI_DATA_REG , RULL(0x22011C00), SH_UNT_EX_1_L3 , + SH_ACS_SCOM_RO ); //DUPS: 23011C00, +REG64( EX_2_L3_TRACE_HI_DATA_REG , RULL(0x24011C00), SH_UNT_EX_2_L3 , + SH_ACS_SCOM_RO ); //DUPS: 25011C00, +REG64( EX_3_L3_TRACE_HI_DATA_REG , RULL(0x26011C00), SH_UNT_EX_3_L3 , + SH_ACS_SCOM_RO ); //DUPS: 27011C00, +REG64( EX_4_L3_TRACE_HI_DATA_REG , RULL(0x28011C00), SH_UNT_EX_4_L3 , + SH_ACS_SCOM_RO ); //DUPS: 29011C00, +REG64( EX_5_L3_TRACE_HI_DATA_REG , RULL(0x2A011C00), SH_UNT_EX_5_L3 , + SH_ACS_SCOM_RO ); //DUPS: 2B011C00, +REG64( EX_6_L3_TRACE_HI_DATA_REG , RULL(0x2C011C00), SH_UNT_EX_6_L3 , + SH_ACS_SCOM_RO ); //DUPS: 2D011C00, +REG64( EX_7_L3_TRACE_HI_DATA_REG , RULL(0x2F011C00), SH_UNT_EX_7_L3 , + SH_ACS_SCOM_RO ); //DUPS: 2F011C00, +REG64( EX_8_L3_TRACE_HI_DATA_REG , RULL(0x30011C00), SH_UNT_EX_8_L3 , + SH_ACS_SCOM_RO ); //DUPS: 31011C00, +REG64( EX_9_L3_TRACE_HI_DATA_REG , RULL(0x32011C00), SH_UNT_EX_9_L3 , + SH_ACS_SCOM_RO ); //DUPS: 33011C00, +REG64( EX_L3_TRACE_HI_DATA_REG , RULL(0x20011C00), SH_UNT_EX_L3 , + SH_ACS_SCOM_RO ); //DUPS: 21011C00, + +REG64( C_TRACE_LO_DATA_REG , RULL(0x20011C01), SH_UNT_C , + SH_ACS_SCOM_RO ); //DUPS: 20011441, 20011C01, +REG64( C_0_TRACE_LO_DATA_REG , RULL(0x20011C01), SH_UNT_C_0 , + SH_ACS_SCOM_RO ); //DUPS: 20011441, 20011C01, +REG64( C_1_TRACE_LO_DATA_REG , RULL(0x21011C01), SH_UNT_C_1 , + SH_ACS_SCOM_RO ); //DUPS: 21011441, 21011C01, +REG64( C_2_TRACE_LO_DATA_REG , RULL(0x22011C01), SH_UNT_C_2 , + SH_ACS_SCOM_RO ); //DUPS: 22011441, 22011C01, +REG64( C_3_TRACE_LO_DATA_REG , RULL(0x23011C01), SH_UNT_C_3 , + SH_ACS_SCOM_RO ); //DUPS: 23011441, 23011C01, +REG64( C_4_TRACE_LO_DATA_REG , RULL(0x24011C01), SH_UNT_C_4 , + SH_ACS_SCOM_RO ); //DUPS: 24011441, 24011C01, +REG64( C_5_TRACE_LO_DATA_REG , RULL(0x25011C01), SH_UNT_C_5 , + SH_ACS_SCOM_RO ); //DUPS: 25011441, 25011C01, +REG64( C_6_TRACE_LO_DATA_REG , RULL(0x26011C01), SH_UNT_C_6 , + SH_ACS_SCOM_RO ); //DUPS: 26011441, 26011C01, +REG64( C_7_TRACE_LO_DATA_REG , RULL(0x27011C01), SH_UNT_C_7 , + SH_ACS_SCOM_RO ); //DUPS: 27011441, 27011C01, +REG64( C_8_TRACE_LO_DATA_REG , RULL(0x28011C01), SH_UNT_C_8 , + SH_ACS_SCOM_RO ); //DUPS: 28011441, 28011C01, +REG64( C_9_TRACE_LO_DATA_REG , RULL(0x29011C01), SH_UNT_C_9 , + SH_ACS_SCOM_RO ); //DUPS: 29011441, 29011C01, +REG64( C_10_TRACE_LO_DATA_REG , RULL(0x2A011481), SH_UNT_C_10 , + SH_ACS_SCOM_RO ); //DUPS: 2A011441, 2A011C01, +REG64( C_11_TRACE_LO_DATA_REG , RULL(0x2B011481), SH_UNT_C_11 , + SH_ACS_SCOM_RO ); //DUPS: 2B011441, 2B011C01, +REG64( C_12_TRACE_LO_DATA_REG , RULL(0x2C011481), SH_UNT_C_12 , + SH_ACS_SCOM_RO ); //DUPS: 2C011441, 2C011C01, +REG64( C_13_TRACE_LO_DATA_REG , RULL(0x2D011481), SH_UNT_C_13 , + SH_ACS_SCOM_RO ); //DUPS: 2D011441, 2D011C01, +REG64( C_14_TRACE_LO_DATA_REG , RULL(0x2E011C01), SH_UNT_C_14 , + SH_ACS_SCOM_RO ); //DUPS: 2E011441, 2E011C01, +REG64( C_15_TRACE_LO_DATA_REG , RULL(0x2F011481), SH_UNT_C_15 , + SH_ACS_SCOM_RO ); //DUPS: 2F011441, 2F011C01, +REG64( C_16_TRACE_LO_DATA_REG , RULL(0x30011C01), SH_UNT_C_16 , + SH_ACS_SCOM_RO ); //DUPS: 30011441, 30011C01, +REG64( C_17_TRACE_LO_DATA_REG , RULL(0x31011C01), SH_UNT_C_17 , + SH_ACS_SCOM_RO ); //DUPS: 31011441, 31011C01, +REG64( C_18_TRACE_LO_DATA_REG , RULL(0x32011C01), SH_UNT_C_18 , + SH_ACS_SCOM_RO ); //DUPS: 32011441, 32011C01, +REG64( C_19_TRACE_LO_DATA_REG , RULL(0x33011C01), SH_UNT_C_19 , + SH_ACS_SCOM_RO ); //DUPS: 33011441, 33011C01, +REG64( C_20_TRACE_LO_DATA_REG , RULL(0x34011C01), SH_UNT_C_20 , + SH_ACS_SCOM_RO ); //DUPS: 34011441, 34011C01, +REG64( C_21_TRACE_LO_DATA_REG , RULL(0x35011C01), SH_UNT_C_21 , + SH_ACS_SCOM_RO ); //DUPS: 35011441, 35011C01, +REG64( C_22_TRACE_LO_DATA_REG , RULL(0x36011C01), SH_UNT_C_22 , + SH_ACS_SCOM_RO ); //DUPS: 36011441, 36011C01, +REG64( C_23_TRACE_LO_DATA_REG , RULL(0x37011C01), SH_UNT_C_23 , + SH_ACS_SCOM_RO ); //DUPS: 37011441, 37011C01, +REG64( EX_TRACE_LO_DATA_REG , RULL(0x20011441), SH_UNT_EX , + SH_ACS_SCOM_RO ); //DUPS: 20011441, 21011481, 21011441, +REG64( EX_0_TRACE_LO_DATA_REG , RULL(0x20011441), SH_UNT_EX_0 , + SH_ACS_SCOM_RO ); //DUPS: 20011441, 21011481, 21011441, +REG64( EX_1_TRACE_LO_DATA_REG , RULL(0x22011441), SH_UNT_EX_1 , + SH_ACS_SCOM_RO ); //DUPS: 22011441, 23011481, 23011441, +REG64( EX_2_TRACE_LO_DATA_REG , RULL(0x24011441), SH_UNT_EX_2 , + SH_ACS_SCOM_RO ); //DUPS: 24011441, 25011481, 25011441, +REG64( EX_3_TRACE_LO_DATA_REG , RULL(0x26011441), SH_UNT_EX_3 , + SH_ACS_SCOM_RO ); //DUPS: 26011441, 27011481, 27011441, +REG64( EX_4_TRACE_LO_DATA_REG , RULL(0x28011441), SH_UNT_EX_4 , + SH_ACS_SCOM_RO ); //DUPS: 28011441, 29011481, 29011441, +REG64( EX_5_TRACE_LO_DATA_REG , RULL(0x2A011481), SH_UNT_EX_5 , + SH_ACS_SCOM_RO ); //DUPS: 2A011441, 2B011481, 2B011441, +REG64( EX_6_TRACE_LO_DATA_REG , RULL(0x2C011481), SH_UNT_EX_6 , + SH_ACS_SCOM_RO ); //DUPS: 2C011441, 2D011481, 2D011441, +REG64( EX_7_TRACE_LO_DATA_REG , RULL(0x2F011481), SH_UNT_EX_7 , + SH_ACS_SCOM_RO ); //DUPS: 2E011441, 2F011481, 2F011441, +REG64( EX_8_TRACE_LO_DATA_REG , RULL(0x30011441), SH_UNT_EX_8 , + SH_ACS_SCOM_RO ); //DUPS: 30011441, 31011481, 31011441, +REG64( EX_9_TRACE_LO_DATA_REG , RULL(0x32011441), SH_UNT_EX_9 , + SH_ACS_SCOM_RO ); //DUPS: 32011441, 33011481, 33011441, +REG64( EX_0_L3_TRACE_LO_DATA_REG , RULL(0x20011C01), SH_UNT_EX_0_L3 , + SH_ACS_SCOM_RO ); //DUPS: 21011C01, +REG64( EX_10_TRACE_LO_DATA_REG , RULL(0x34011441), SH_UNT_EX_10 , + SH_ACS_SCOM_RO ); //DUPS: 34011441, 35011481, 35011441, +REG64( EX_11_TRACE_LO_DATA_REG , RULL(0x36011441), SH_UNT_EX_11 , + SH_ACS_SCOM_RO ); //DUPS: 36011441, 37011481, 37011441, +REG64( EX_10_L3_TRACE_LO_DATA_REG , RULL(0x34011C01), SH_UNT_EX_10_L3 , + SH_ACS_SCOM_RO ); //DUPS: 35011C01, +REG64( EX_11_L3_TRACE_LO_DATA_REG , RULL(0x36011C01), SH_UNT_EX_11_L3 , + SH_ACS_SCOM_RO ); //DUPS: 37011C01, +REG64( EX_1_L3_TRACE_LO_DATA_REG , RULL(0x22011C01), SH_UNT_EX_1_L3 , + SH_ACS_SCOM_RO ); //DUPS: 23011C01, +REG64( EX_2_L3_TRACE_LO_DATA_REG , RULL(0x24011C01), SH_UNT_EX_2_L3 , + SH_ACS_SCOM_RO ); //DUPS: 25011C01, +REG64( EX_3_L3_TRACE_LO_DATA_REG , RULL(0x26011C01), SH_UNT_EX_3_L3 , + SH_ACS_SCOM_RO ); //DUPS: 27011C01, +REG64( EX_4_L3_TRACE_LO_DATA_REG , RULL(0x28011C01), SH_UNT_EX_4_L3 , + SH_ACS_SCOM_RO ); //DUPS: 29011C01, +REG64( EX_5_L3_TRACE_LO_DATA_REG , RULL(0x2A011C01), SH_UNT_EX_5_L3 , + SH_ACS_SCOM_RO ); //DUPS: 2B011C01, +REG64( EX_6_L3_TRACE_LO_DATA_REG , RULL(0x2C011C01), SH_UNT_EX_6_L3 , + SH_ACS_SCOM_RO ); //DUPS: 2D011C01, +REG64( EX_7_L3_TRACE_LO_DATA_REG , RULL(0x2F011C01), SH_UNT_EX_7_L3 , + SH_ACS_SCOM_RO ); //DUPS: 2F011C01, +REG64( EX_8_L3_TRACE_LO_DATA_REG , RULL(0x30011C01), SH_UNT_EX_8_L3 , + SH_ACS_SCOM_RO ); //DUPS: 31011C01, +REG64( EX_9_L3_TRACE_LO_DATA_REG , RULL(0x32011C01), SH_UNT_EX_9_L3 , + SH_ACS_SCOM_RO ); //DUPS: 33011C01, +REG64( EX_L3_TRACE_LO_DATA_REG , RULL(0x20011C01), SH_UNT_EX_L3 , + SH_ACS_SCOM_RO ); //DUPS: 21011C01, + +REG64( C_TRACE_TRCTRL_CONFIG , RULL(0x20011C02), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011442, 20011C02, +REG64( C_0_TRACE_TRCTRL_CONFIG , RULL(0x20011C02), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011442, 20011C02, +REG64( C_1_TRACE_TRCTRL_CONFIG , RULL(0x21011C02), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011442, 21011C02, +REG64( C_2_TRACE_TRCTRL_CONFIG , RULL(0x22011C02), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011442, 22011C02, +REG64( C_3_TRACE_TRCTRL_CONFIG , RULL(0x23011C02), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011442, 23011C02, +REG64( C_4_TRACE_TRCTRL_CONFIG , RULL(0x24011C02), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011442, 24011C02, +REG64( C_5_TRACE_TRCTRL_CONFIG , RULL(0x25011C02), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011442, 25011C02, +REG64( C_6_TRACE_TRCTRL_CONFIG , RULL(0x26011C02), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011442, 26011C02, +REG64( C_7_TRACE_TRCTRL_CONFIG , RULL(0x27011C02), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011442, 27011C02, +REG64( C_8_TRACE_TRCTRL_CONFIG , RULL(0x28011C02), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011442, 28011C02, +REG64( C_9_TRACE_TRCTRL_CONFIG , RULL(0x29011C02), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011442, 29011C02, +REG64( C_10_TRACE_TRCTRL_CONFIG , RULL(0x2A011482), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011442, 2A011C02, +REG64( C_11_TRACE_TRCTRL_CONFIG , RULL(0x2B011482), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011442, 2B011C02, +REG64( C_12_TRACE_TRCTRL_CONFIG , RULL(0x2C011482), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011442, 2C011C02, +REG64( C_13_TRACE_TRCTRL_CONFIG , RULL(0x2D011482), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011442, 2D011C02, +REG64( C_14_TRACE_TRCTRL_CONFIG , RULL(0x2E011C02), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011442, 2E011C02, +REG64( C_15_TRACE_TRCTRL_CONFIG , RULL(0x2F011482), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011442, 2F011C02, +REG64( C_16_TRACE_TRCTRL_CONFIG , RULL(0x30011C02), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011442, 30011C02, +REG64( C_17_TRACE_TRCTRL_CONFIG , RULL(0x31011C02), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011442, 31011C02, +REG64( C_18_TRACE_TRCTRL_CONFIG , RULL(0x32011C02), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011442, 32011C02, +REG64( C_19_TRACE_TRCTRL_CONFIG , RULL(0x33011C02), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011442, 33011C02, +REG64( C_20_TRACE_TRCTRL_CONFIG , RULL(0x34011C02), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011442, 34011C02, +REG64( C_21_TRACE_TRCTRL_CONFIG , RULL(0x35011C02), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011442, 35011C02, +REG64( C_22_TRACE_TRCTRL_CONFIG , RULL(0x36011C02), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011442, 36011C02, +REG64( C_23_TRACE_TRCTRL_CONFIG , RULL(0x37011C02), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011442, 37011C02, +REG64( EX_TRACE_TRCTRL_CONFIG , RULL(0x20011442), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011442, 21011482, 21011442, +REG64( EX_0_TRACE_TRCTRL_CONFIG , RULL(0x20011442), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011442, 21011482, 21011442, +REG64( EX_1_TRACE_TRCTRL_CONFIG , RULL(0x22011442), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011442, 23011482, 23011442, +REG64( EX_2_TRACE_TRCTRL_CONFIG , RULL(0x24011442), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011442, 25011482, 25011442, +REG64( EX_3_TRACE_TRCTRL_CONFIG , RULL(0x26011442), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011442, 27011482, 27011442, +REG64( EX_4_TRACE_TRCTRL_CONFIG , RULL(0x28011442), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011442, 29011482, 29011442, +REG64( EX_5_TRACE_TRCTRL_CONFIG , RULL(0x2A011482), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011442, 2B011482, 2B011442, +REG64( EX_6_TRACE_TRCTRL_CONFIG , RULL(0x2C011482), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011442, 2D011482, 2D011442, +REG64( EX_7_TRACE_TRCTRL_CONFIG , RULL(0x2F011482), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011442, 2F011482, 2F011442, +REG64( EX_8_TRACE_TRCTRL_CONFIG , RULL(0x30011442), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011442, 31011482, 31011442, +REG64( EX_9_TRACE_TRCTRL_CONFIG , RULL(0x32011442), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011442, 33011482, 33011442, +REG64( EX_0_L3_TRACE_TRCTRL_CONFIG , RULL(0x20011C02), SH_UNT_EX_0_L3 , + SH_ACS_SCOM ); //DUPS: 21011C02, +REG64( EX_10_TRACE_TRCTRL_CONFIG , RULL(0x34011442), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011442, 35011482, 35011442, +REG64( EX_11_TRACE_TRCTRL_CONFIG , RULL(0x36011442), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011442, 37011482, 37011442, +REG64( EX_10_L3_TRACE_TRCTRL_CONFIG , RULL(0x34011C02), SH_UNT_EX_10_L3 , + SH_ACS_SCOM ); //DUPS: 35011C02, +REG64( EX_11_L3_TRACE_TRCTRL_CONFIG , RULL(0x36011C02), SH_UNT_EX_11_L3 , + SH_ACS_SCOM ); //DUPS: 37011C02, +REG64( EX_1_L3_TRACE_TRCTRL_CONFIG , RULL(0x22011C02), SH_UNT_EX_1_L3 , + SH_ACS_SCOM ); //DUPS: 23011C02, +REG64( EX_2_L3_TRACE_TRCTRL_CONFIG , RULL(0x24011C02), SH_UNT_EX_2_L3 , + SH_ACS_SCOM ); //DUPS: 25011C02, +REG64( EX_3_L3_TRACE_TRCTRL_CONFIG , RULL(0x26011C02), SH_UNT_EX_3_L3 , + SH_ACS_SCOM ); //DUPS: 27011C02, +REG64( EX_4_L3_TRACE_TRCTRL_CONFIG , RULL(0x28011C02), SH_UNT_EX_4_L3 , + SH_ACS_SCOM ); //DUPS: 29011C02, +REG64( EX_5_L3_TRACE_TRCTRL_CONFIG , RULL(0x2A011C02), SH_UNT_EX_5_L3 , + SH_ACS_SCOM ); //DUPS: 2B011C02, +REG64( EX_6_L3_TRACE_TRCTRL_CONFIG , RULL(0x2C011C02), SH_UNT_EX_6_L3 , + SH_ACS_SCOM ); //DUPS: 2D011C02, +REG64( EX_7_L3_TRACE_TRCTRL_CONFIG , RULL(0x2F011C02), SH_UNT_EX_7_L3 , + SH_ACS_SCOM ); //DUPS: 2F011C02, +REG64( EX_8_L3_TRACE_TRCTRL_CONFIG , RULL(0x30011C02), SH_UNT_EX_8_L3 , + SH_ACS_SCOM ); //DUPS: 31011C02, +REG64( EX_9_L3_TRACE_TRCTRL_CONFIG , RULL(0x32011C02), SH_UNT_EX_9_L3 , + SH_ACS_SCOM ); //DUPS: 33011C02, +REG64( EX_L3_TRACE_TRCTRL_CONFIG , RULL(0x20011C02), SH_UNT_EX_L3 , + SH_ACS_SCOM ); //DUPS: 21011C02, + +REG64( C_TRACE_TRDATA_CONFIG_0 , RULL(0x20011C03), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011443, 20011C03, +REG64( C_0_TRACE_TRDATA_CONFIG_0 , RULL(0x20011C03), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011443, 20011C03, +REG64( C_1_TRACE_TRDATA_CONFIG_0 , RULL(0x21011C03), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011443, 21011C03, +REG64( C_2_TRACE_TRDATA_CONFIG_0 , RULL(0x22011C03), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011443, 22011C03, +REG64( C_3_TRACE_TRDATA_CONFIG_0 , RULL(0x23011C03), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011443, 23011C03, +REG64( C_4_TRACE_TRDATA_CONFIG_0 , RULL(0x24011C03), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011443, 24011C03, +REG64( C_5_TRACE_TRDATA_CONFIG_0 , RULL(0x25011C03), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011443, 25011C03, +REG64( C_6_TRACE_TRDATA_CONFIG_0 , RULL(0x26011C03), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011443, 26011C03, +REG64( C_7_TRACE_TRDATA_CONFIG_0 , RULL(0x27011C03), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011443, 27011C03, +REG64( C_8_TRACE_TRDATA_CONFIG_0 , RULL(0x28011C03), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011443, 28011C03, +REG64( C_9_TRACE_TRDATA_CONFIG_0 , RULL(0x29011C03), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011443, 29011C03, +REG64( C_10_TRACE_TRDATA_CONFIG_0 , RULL(0x2A011483), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011443, 2A011C03, +REG64( C_11_TRACE_TRDATA_CONFIG_0 , RULL(0x2B011483), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011443, 2B011C03, +REG64( C_12_TRACE_TRDATA_CONFIG_0 , RULL(0x2C011483), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011443, 2C011C03, +REG64( C_13_TRACE_TRDATA_CONFIG_0 , RULL(0x2D011483), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011443, 2D011C03, +REG64( C_14_TRACE_TRDATA_CONFIG_0 , RULL(0x2E011C03), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011443, 2E011C03, +REG64( C_15_TRACE_TRDATA_CONFIG_0 , RULL(0x2F011483), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011443, 2F011C03, +REG64( C_16_TRACE_TRDATA_CONFIG_0 , RULL(0x30011C03), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011443, 30011C03, +REG64( C_17_TRACE_TRDATA_CONFIG_0 , RULL(0x31011C03), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011443, 31011C03, +REG64( C_18_TRACE_TRDATA_CONFIG_0 , RULL(0x32011C03), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011443, 32011C03, +REG64( C_19_TRACE_TRDATA_CONFIG_0 , RULL(0x33011C03), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011443, 33011C03, +REG64( C_20_TRACE_TRDATA_CONFIG_0 , RULL(0x34011C03), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011443, 34011C03, +REG64( C_21_TRACE_TRDATA_CONFIG_0 , RULL(0x35011C03), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011443, 35011C03, +REG64( C_22_TRACE_TRDATA_CONFIG_0 , RULL(0x36011C03), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011443, 36011C03, +REG64( C_23_TRACE_TRDATA_CONFIG_0 , RULL(0x37011C03), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011443, 37011C03, +REG64( EX_TRACE_TRDATA_CONFIG_0 , RULL(0x20011443), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011443, 21011483, 21011443, +REG64( EX_0_TRACE_TRDATA_CONFIG_0 , RULL(0x20011443), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011443, 21011483, 21011443, +REG64( EX_1_TRACE_TRDATA_CONFIG_0 , RULL(0x22011443), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011443, 23011483, 23011443, +REG64( EX_2_TRACE_TRDATA_CONFIG_0 , RULL(0x24011443), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011443, 25011483, 25011443, +REG64( EX_3_TRACE_TRDATA_CONFIG_0 , RULL(0x26011443), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011443, 27011483, 27011443, +REG64( EX_4_TRACE_TRDATA_CONFIG_0 , RULL(0x28011443), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011443, 29011483, 29011443, +REG64( EX_5_TRACE_TRDATA_CONFIG_0 , RULL(0x2A011483), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011443, 2B011483, 2B011443, +REG64( EX_6_TRACE_TRDATA_CONFIG_0 , RULL(0x2C011483), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011443, 2D011483, 2D011443, +REG64( EX_7_TRACE_TRDATA_CONFIG_0 , RULL(0x2F011483), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011443, 2F011483, 2F011443, +REG64( EX_8_TRACE_TRDATA_CONFIG_0 , RULL(0x30011443), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011443, 31011483, 31011443, +REG64( EX_9_TRACE_TRDATA_CONFIG_0 , RULL(0x32011443), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011443, 33011483, 33011443, +REG64( EX_0_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x20011C03), SH_UNT_EX_0_L3 , + SH_ACS_SCOM ); //DUPS: 21011C03, +REG64( EX_10_TRACE_TRDATA_CONFIG_0 , RULL(0x34011443), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011443, 35011483, 35011443, +REG64( EX_11_TRACE_TRDATA_CONFIG_0 , RULL(0x36011443), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011443, 37011483, 37011443, +REG64( EX_10_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x34011C03), SH_UNT_EX_10_L3 , + SH_ACS_SCOM ); //DUPS: 35011C03, +REG64( EX_11_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x36011C03), SH_UNT_EX_11_L3 , + SH_ACS_SCOM ); //DUPS: 37011C03, +REG64( EX_1_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x22011C03), SH_UNT_EX_1_L3 , + SH_ACS_SCOM ); //DUPS: 23011C03, +REG64( EX_2_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x24011C03), SH_UNT_EX_2_L3 , + SH_ACS_SCOM ); //DUPS: 25011C03, +REG64( EX_3_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x26011C03), SH_UNT_EX_3_L3 , + SH_ACS_SCOM ); //DUPS: 27011C03, +REG64( EX_4_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x28011C03), SH_UNT_EX_4_L3 , + SH_ACS_SCOM ); //DUPS: 29011C03, +REG64( EX_5_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x2A011C03), SH_UNT_EX_5_L3 , + SH_ACS_SCOM ); //DUPS: 2B011C03, +REG64( EX_6_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x2C011C03), SH_UNT_EX_6_L3 , + SH_ACS_SCOM ); //DUPS: 2D011C03, +REG64( EX_7_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x2F011C03), SH_UNT_EX_7_L3 , + SH_ACS_SCOM ); //DUPS: 2F011C03, +REG64( EX_8_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x30011C03), SH_UNT_EX_8_L3 , + SH_ACS_SCOM ); //DUPS: 31011C03, +REG64( EX_9_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x32011C03), SH_UNT_EX_9_L3 , + SH_ACS_SCOM ); //DUPS: 33011C03, +REG64( EX_L3_TRACE_TRDATA_CONFIG_0 , RULL(0x20011C03), SH_UNT_EX_L3 , + SH_ACS_SCOM ); //DUPS: 21011C03, + +REG64( C_TRACE_TRDATA_CONFIG_1 , RULL(0x20011C04), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011444, 20011C04, +REG64( C_0_TRACE_TRDATA_CONFIG_1 , RULL(0x20011C04), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011444, 20011C04, +REG64( C_1_TRACE_TRDATA_CONFIG_1 , RULL(0x21011C04), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011444, 21011C04, +REG64( C_2_TRACE_TRDATA_CONFIG_1 , RULL(0x22011C04), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011444, 22011C04, +REG64( C_3_TRACE_TRDATA_CONFIG_1 , RULL(0x23011C04), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011444, 23011C04, +REG64( C_4_TRACE_TRDATA_CONFIG_1 , RULL(0x24011C04), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011444, 24011C04, +REG64( C_5_TRACE_TRDATA_CONFIG_1 , RULL(0x25011C04), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011444, 25011C04, +REG64( C_6_TRACE_TRDATA_CONFIG_1 , RULL(0x26011C04), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011444, 26011C04, +REG64( C_7_TRACE_TRDATA_CONFIG_1 , RULL(0x27011C04), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011444, 27011C04, +REG64( C_8_TRACE_TRDATA_CONFIG_1 , RULL(0x28011C04), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011444, 28011C04, +REG64( C_9_TRACE_TRDATA_CONFIG_1 , RULL(0x29011C04), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011444, 29011C04, +REG64( C_10_TRACE_TRDATA_CONFIG_1 , RULL(0x2A011484), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011444, 2A011C04, +REG64( C_11_TRACE_TRDATA_CONFIG_1 , RULL(0x2B011484), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011444, 2B011C04, +REG64( C_12_TRACE_TRDATA_CONFIG_1 , RULL(0x2C011484), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011444, 2C011C04, +REG64( C_13_TRACE_TRDATA_CONFIG_1 , RULL(0x2D011484), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011444, 2D011C04, +REG64( C_14_TRACE_TRDATA_CONFIG_1 , RULL(0x2E011C04), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011444, 2E011C04, +REG64( C_15_TRACE_TRDATA_CONFIG_1 , RULL(0x2F011484), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011444, 2F011C04, +REG64( C_16_TRACE_TRDATA_CONFIG_1 , RULL(0x30011C04), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011444, 30011C04, +REG64( C_17_TRACE_TRDATA_CONFIG_1 , RULL(0x31011C04), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011444, 31011C04, +REG64( C_18_TRACE_TRDATA_CONFIG_1 , RULL(0x32011C04), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011444, 32011C04, +REG64( C_19_TRACE_TRDATA_CONFIG_1 , RULL(0x33011C04), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011444, 33011C04, +REG64( C_20_TRACE_TRDATA_CONFIG_1 , RULL(0x34011C04), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011444, 34011C04, +REG64( C_21_TRACE_TRDATA_CONFIG_1 , RULL(0x35011C04), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011444, 35011C04, +REG64( C_22_TRACE_TRDATA_CONFIG_1 , RULL(0x36011C04), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011444, 36011C04, +REG64( C_23_TRACE_TRDATA_CONFIG_1 , RULL(0x37011C04), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011444, 37011C04, +REG64( EX_TRACE_TRDATA_CONFIG_1 , RULL(0x20011444), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011444, 21011484, 21011444, +REG64( EX_0_TRACE_TRDATA_CONFIG_1 , RULL(0x20011444), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011444, 21011484, 21011444, +REG64( EX_1_TRACE_TRDATA_CONFIG_1 , RULL(0x22011444), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011444, 23011484, 23011444, +REG64( EX_2_TRACE_TRDATA_CONFIG_1 , RULL(0x24011444), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011444, 25011484, 25011444, +REG64( EX_3_TRACE_TRDATA_CONFIG_1 , RULL(0x26011444), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011444, 27011484, 27011444, +REG64( EX_4_TRACE_TRDATA_CONFIG_1 , RULL(0x28011444), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011444, 29011484, 29011444, +REG64( EX_5_TRACE_TRDATA_CONFIG_1 , RULL(0x2A011484), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011444, 2B011484, 2B011444, +REG64( EX_6_TRACE_TRDATA_CONFIG_1 , RULL(0x2C011484), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011444, 2D011484, 2D011444, +REG64( EX_7_TRACE_TRDATA_CONFIG_1 , RULL(0x2F011484), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011444, 2F011484, 2F011444, +REG64( EX_8_TRACE_TRDATA_CONFIG_1 , RULL(0x30011444), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011444, 31011484, 31011444, +REG64( EX_9_TRACE_TRDATA_CONFIG_1 , RULL(0x32011444), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011444, 33011484, 33011444, +REG64( EX_0_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x20011C04), SH_UNT_EX_0_L3 , + SH_ACS_SCOM ); //DUPS: 21011C04, +REG64( EX_10_TRACE_TRDATA_CONFIG_1 , RULL(0x34011444), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011444, 35011484, 35011444, +REG64( EX_11_TRACE_TRDATA_CONFIG_1 , RULL(0x36011444), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011444, 37011484, 37011444, +REG64( EX_10_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x34011C04), SH_UNT_EX_10_L3 , + SH_ACS_SCOM ); //DUPS: 35011C04, +REG64( EX_11_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x36011C04), SH_UNT_EX_11_L3 , + SH_ACS_SCOM ); //DUPS: 37011C04, +REG64( EX_1_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x22011C04), SH_UNT_EX_1_L3 , + SH_ACS_SCOM ); //DUPS: 23011C04, +REG64( EX_2_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x24011C04), SH_UNT_EX_2_L3 , + SH_ACS_SCOM ); //DUPS: 25011C04, +REG64( EX_3_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x26011C04), SH_UNT_EX_3_L3 , + SH_ACS_SCOM ); //DUPS: 27011C04, +REG64( EX_4_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x28011C04), SH_UNT_EX_4_L3 , + SH_ACS_SCOM ); //DUPS: 29011C04, +REG64( EX_5_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x2A011C04), SH_UNT_EX_5_L3 , + SH_ACS_SCOM ); //DUPS: 2B011C04, +REG64( EX_6_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x2C011C04), SH_UNT_EX_6_L3 , + SH_ACS_SCOM ); //DUPS: 2D011C04, +REG64( EX_7_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x2F011C04), SH_UNT_EX_7_L3 , + SH_ACS_SCOM ); //DUPS: 2F011C04, +REG64( EX_8_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x30011C04), SH_UNT_EX_8_L3 , + SH_ACS_SCOM ); //DUPS: 31011C04, +REG64( EX_9_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x32011C04), SH_UNT_EX_9_L3 , + SH_ACS_SCOM ); //DUPS: 33011C04, +REG64( EX_L3_TRACE_TRDATA_CONFIG_1 , RULL(0x20011C04), SH_UNT_EX_L3 , + SH_ACS_SCOM ); //DUPS: 21011C04, + +REG64( C_TRACE_TRDATA_CONFIG_2 , RULL(0x20011C05), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011445, 20011C05, +REG64( C_0_TRACE_TRDATA_CONFIG_2 , RULL(0x20011C05), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011445, 20011C05, +REG64( C_1_TRACE_TRDATA_CONFIG_2 , RULL(0x21011C05), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011445, 21011C05, +REG64( C_2_TRACE_TRDATA_CONFIG_2 , RULL(0x22011C05), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011445, 22011C05, +REG64( C_3_TRACE_TRDATA_CONFIG_2 , RULL(0x23011C05), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011445, 23011C05, +REG64( C_4_TRACE_TRDATA_CONFIG_2 , RULL(0x24011C05), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011445, 24011C05, +REG64( C_5_TRACE_TRDATA_CONFIG_2 , RULL(0x25011C05), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011445, 25011C05, +REG64( C_6_TRACE_TRDATA_CONFIG_2 , RULL(0x26011C05), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011445, 26011C05, +REG64( C_7_TRACE_TRDATA_CONFIG_2 , RULL(0x27011C05), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011445, 27011C05, +REG64( C_8_TRACE_TRDATA_CONFIG_2 , RULL(0x28011C05), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011445, 28011C05, +REG64( C_9_TRACE_TRDATA_CONFIG_2 , RULL(0x29011C05), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011445, 29011C05, +REG64( C_10_TRACE_TRDATA_CONFIG_2 , RULL(0x2A011485), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011445, 2A011C05, +REG64( C_11_TRACE_TRDATA_CONFIG_2 , RULL(0x2B011485), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011445, 2B011C05, +REG64( C_12_TRACE_TRDATA_CONFIG_2 , RULL(0x2C011485), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011445, 2C011C05, +REG64( C_13_TRACE_TRDATA_CONFIG_2 , RULL(0x2D011485), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011445, 2D011C05, +REG64( C_14_TRACE_TRDATA_CONFIG_2 , RULL(0x2E011C05), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011445, 2E011C05, +REG64( C_15_TRACE_TRDATA_CONFIG_2 , RULL(0x2F011485), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011445, 2F011C05, +REG64( C_16_TRACE_TRDATA_CONFIG_2 , RULL(0x30011C05), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011445, 30011C05, +REG64( C_17_TRACE_TRDATA_CONFIG_2 , RULL(0x31011C05), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011445, 31011C05, +REG64( C_18_TRACE_TRDATA_CONFIG_2 , RULL(0x32011C05), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011445, 32011C05, +REG64( C_19_TRACE_TRDATA_CONFIG_2 , RULL(0x33011C05), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011445, 33011C05, +REG64( C_20_TRACE_TRDATA_CONFIG_2 , RULL(0x34011C05), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011445, 34011C05, +REG64( C_21_TRACE_TRDATA_CONFIG_2 , RULL(0x35011C05), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011445, 35011C05, +REG64( C_22_TRACE_TRDATA_CONFIG_2 , RULL(0x36011C05), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011445, 36011C05, +REG64( C_23_TRACE_TRDATA_CONFIG_2 , RULL(0x37011C05), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011445, 37011C05, +REG64( EX_TRACE_TRDATA_CONFIG_2 , RULL(0x20011445), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011445, 21011485, 21011445, +REG64( EX_0_TRACE_TRDATA_CONFIG_2 , RULL(0x20011445), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011445, 21011485, 21011445, +REG64( EX_1_TRACE_TRDATA_CONFIG_2 , RULL(0x22011445), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011445, 23011485, 23011445, +REG64( EX_2_TRACE_TRDATA_CONFIG_2 , RULL(0x24011445), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011445, 25011485, 25011445, +REG64( EX_3_TRACE_TRDATA_CONFIG_2 , RULL(0x26011445), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011445, 27011485, 27011445, +REG64( EX_4_TRACE_TRDATA_CONFIG_2 , RULL(0x28011445), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011445, 29011485, 29011445, +REG64( EX_5_TRACE_TRDATA_CONFIG_2 , RULL(0x2A011485), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011445, 2B011485, 2B011445, +REG64( EX_6_TRACE_TRDATA_CONFIG_2 , RULL(0x2C011485), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011445, 2D011485, 2D011445, +REG64( EX_7_TRACE_TRDATA_CONFIG_2 , RULL(0x2F011485), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011445, 2F011485, 2F011445, +REG64( EX_8_TRACE_TRDATA_CONFIG_2 , RULL(0x30011445), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011445, 31011485, 31011445, +REG64( EX_9_TRACE_TRDATA_CONFIG_2 , RULL(0x32011445), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011445, 33011485, 33011445, +REG64( EX_0_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x20011C05), SH_UNT_EX_0_L3 , + SH_ACS_SCOM ); //DUPS: 21011C05, +REG64( EX_10_TRACE_TRDATA_CONFIG_2 , RULL(0x34011445), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011445, 35011485, 35011445, +REG64( EX_11_TRACE_TRDATA_CONFIG_2 , RULL(0x36011445), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011445, 37011485, 37011445, +REG64( EX_10_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x34011C05), SH_UNT_EX_10_L3 , + SH_ACS_SCOM ); //DUPS: 35011C05, +REG64( EX_11_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x36011C05), SH_UNT_EX_11_L3 , + SH_ACS_SCOM ); //DUPS: 37011C05, +REG64( EX_1_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x22011C05), SH_UNT_EX_1_L3 , + SH_ACS_SCOM ); //DUPS: 23011C05, +REG64( EX_2_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x24011C05), SH_UNT_EX_2_L3 , + SH_ACS_SCOM ); //DUPS: 25011C05, +REG64( EX_3_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x26011C05), SH_UNT_EX_3_L3 , + SH_ACS_SCOM ); //DUPS: 27011C05, +REG64( EX_4_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x28011C05), SH_UNT_EX_4_L3 , + SH_ACS_SCOM ); //DUPS: 29011C05, +REG64( EX_5_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x2A011C05), SH_UNT_EX_5_L3 , + SH_ACS_SCOM ); //DUPS: 2B011C05, +REG64( EX_6_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x2C011C05), SH_UNT_EX_6_L3 , + SH_ACS_SCOM ); //DUPS: 2D011C05, +REG64( EX_7_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x2F011C05), SH_UNT_EX_7_L3 , + SH_ACS_SCOM ); //DUPS: 2F011C05, +REG64( EX_8_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x30011C05), SH_UNT_EX_8_L3 , + SH_ACS_SCOM ); //DUPS: 31011C05, +REG64( EX_9_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x32011C05), SH_UNT_EX_9_L3 , + SH_ACS_SCOM ); //DUPS: 33011C05, +REG64( EX_L3_TRACE_TRDATA_CONFIG_2 , RULL(0x20011C05), SH_UNT_EX_L3 , + SH_ACS_SCOM ); //DUPS: 21011C05, + +REG64( C_TRACE_TRDATA_CONFIG_3 , RULL(0x20011C06), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011446, 20011C06, +REG64( C_0_TRACE_TRDATA_CONFIG_3 , RULL(0x20011C06), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011446, 20011C06, +REG64( C_1_TRACE_TRDATA_CONFIG_3 , RULL(0x21011C06), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011446, 21011C06, +REG64( C_2_TRACE_TRDATA_CONFIG_3 , RULL(0x22011C06), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011446, 22011C06, +REG64( C_3_TRACE_TRDATA_CONFIG_3 , RULL(0x23011C06), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011446, 23011C06, +REG64( C_4_TRACE_TRDATA_CONFIG_3 , RULL(0x24011C06), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011446, 24011C06, +REG64( C_5_TRACE_TRDATA_CONFIG_3 , RULL(0x25011C06), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011446, 25011C06, +REG64( C_6_TRACE_TRDATA_CONFIG_3 , RULL(0x26011C06), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011446, 26011C06, +REG64( C_7_TRACE_TRDATA_CONFIG_3 , RULL(0x27011C06), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011446, 27011C06, +REG64( C_8_TRACE_TRDATA_CONFIG_3 , RULL(0x28011C06), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011446, 28011C06, +REG64( C_9_TRACE_TRDATA_CONFIG_3 , RULL(0x29011C06), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011446, 29011C06, +REG64( C_10_TRACE_TRDATA_CONFIG_3 , RULL(0x2A011486), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011446, 2A011C06, +REG64( C_11_TRACE_TRDATA_CONFIG_3 , RULL(0x2B011486), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011446, 2B011C06, +REG64( C_12_TRACE_TRDATA_CONFIG_3 , RULL(0x2C011486), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011446, 2C011C06, +REG64( C_13_TRACE_TRDATA_CONFIG_3 , RULL(0x2D011486), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011446, 2D011C06, +REG64( C_14_TRACE_TRDATA_CONFIG_3 , RULL(0x2E011C06), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011446, 2E011C06, +REG64( C_15_TRACE_TRDATA_CONFIG_3 , RULL(0x2F011486), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011446, 2F011C06, +REG64( C_16_TRACE_TRDATA_CONFIG_3 , RULL(0x30011C06), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011446, 30011C06, +REG64( C_17_TRACE_TRDATA_CONFIG_3 , RULL(0x31011C06), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011446, 31011C06, +REG64( C_18_TRACE_TRDATA_CONFIG_3 , RULL(0x32011C06), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011446, 32011C06, +REG64( C_19_TRACE_TRDATA_CONFIG_3 , RULL(0x33011C06), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011446, 33011C06, +REG64( C_20_TRACE_TRDATA_CONFIG_3 , RULL(0x34011C06), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011446, 34011C06, +REG64( C_21_TRACE_TRDATA_CONFIG_3 , RULL(0x35011C06), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011446, 35011C06, +REG64( C_22_TRACE_TRDATA_CONFIG_3 , RULL(0x36011C06), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011446, 36011C06, +REG64( C_23_TRACE_TRDATA_CONFIG_3 , RULL(0x37011C06), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011446, 37011C06, +REG64( EX_TRACE_TRDATA_CONFIG_3 , RULL(0x20011446), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011446, 21011486, 21011446, +REG64( EX_0_TRACE_TRDATA_CONFIG_3 , RULL(0x20011446), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011446, 21011486, 21011446, +REG64( EX_1_TRACE_TRDATA_CONFIG_3 , RULL(0x22011446), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011446, 23011486, 23011446, +REG64( EX_2_TRACE_TRDATA_CONFIG_3 , RULL(0x24011446), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011446, 25011486, 25011446, +REG64( EX_3_TRACE_TRDATA_CONFIG_3 , RULL(0x26011446), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011446, 27011486, 27011446, +REG64( EX_4_TRACE_TRDATA_CONFIG_3 , RULL(0x28011446), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011446, 29011486, 29011446, +REG64( EX_5_TRACE_TRDATA_CONFIG_3 , RULL(0x2A011486), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011446, 2B011486, 2B011446, +REG64( EX_6_TRACE_TRDATA_CONFIG_3 , RULL(0x2C011486), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011446, 2D011486, 2D011446, +REG64( EX_7_TRACE_TRDATA_CONFIG_3 , RULL(0x2F011486), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011446, 2F011486, 2F011446, +REG64( EX_8_TRACE_TRDATA_CONFIG_3 , RULL(0x30011446), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011446, 31011486, 31011446, +REG64( EX_9_TRACE_TRDATA_CONFIG_3 , RULL(0x32011446), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011446, 33011486, 33011446, +REG64( EX_0_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x20011C06), SH_UNT_EX_0_L3 , + SH_ACS_SCOM ); //DUPS: 21011C06, +REG64( EX_10_TRACE_TRDATA_CONFIG_3 , RULL(0x34011446), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011446, 35011486, 35011446, +REG64( EX_11_TRACE_TRDATA_CONFIG_3 , RULL(0x36011446), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011446, 37011486, 37011446, +REG64( EX_10_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x34011C06), SH_UNT_EX_10_L3 , + SH_ACS_SCOM ); //DUPS: 35011C06, +REG64( EX_11_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x36011C06), SH_UNT_EX_11_L3 , + SH_ACS_SCOM ); //DUPS: 37011C06, +REG64( EX_1_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x22011C06), SH_UNT_EX_1_L3 , + SH_ACS_SCOM ); //DUPS: 23011C06, +REG64( EX_2_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x24011C06), SH_UNT_EX_2_L3 , + SH_ACS_SCOM ); //DUPS: 25011C06, +REG64( EX_3_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x26011C06), SH_UNT_EX_3_L3 , + SH_ACS_SCOM ); //DUPS: 27011C06, +REG64( EX_4_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x28011C06), SH_UNT_EX_4_L3 , + SH_ACS_SCOM ); //DUPS: 29011C06, +REG64( EX_5_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x2A011C06), SH_UNT_EX_5_L3 , + SH_ACS_SCOM ); //DUPS: 2B011C06, +REG64( EX_6_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x2C011C06), SH_UNT_EX_6_L3 , + SH_ACS_SCOM ); //DUPS: 2D011C06, +REG64( EX_7_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x2F011C06), SH_UNT_EX_7_L3 , + SH_ACS_SCOM ); //DUPS: 2F011C06, +REG64( EX_8_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x30011C06), SH_UNT_EX_8_L3 , + SH_ACS_SCOM ); //DUPS: 31011C06, +REG64( EX_9_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x32011C06), SH_UNT_EX_9_L3 , + SH_ACS_SCOM ); //DUPS: 33011C06, +REG64( EX_L3_TRACE_TRDATA_CONFIG_3 , RULL(0x20011C06), SH_UNT_EX_L3 , + SH_ACS_SCOM ); //DUPS: 21011C06, + +REG64( C_TRACE_TRDATA_CONFIG_4 , RULL(0x20011C07), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011447, 20011C07, +REG64( C_0_TRACE_TRDATA_CONFIG_4 , RULL(0x20011C07), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011447, 20011C07, +REG64( C_1_TRACE_TRDATA_CONFIG_4 , RULL(0x21011C07), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011447, 21011C07, +REG64( C_2_TRACE_TRDATA_CONFIG_4 , RULL(0x22011C07), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011447, 22011C07, +REG64( C_3_TRACE_TRDATA_CONFIG_4 , RULL(0x23011C07), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011447, 23011C07, +REG64( C_4_TRACE_TRDATA_CONFIG_4 , RULL(0x24011C07), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011447, 24011C07, +REG64( C_5_TRACE_TRDATA_CONFIG_4 , RULL(0x25011C07), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011447, 25011C07, +REG64( C_6_TRACE_TRDATA_CONFIG_4 , RULL(0x26011C07), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011447, 26011C07, +REG64( C_7_TRACE_TRDATA_CONFIG_4 , RULL(0x27011C07), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011447, 27011C07, +REG64( C_8_TRACE_TRDATA_CONFIG_4 , RULL(0x28011C07), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011447, 28011C07, +REG64( C_9_TRACE_TRDATA_CONFIG_4 , RULL(0x29011C07), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011447, 29011C07, +REG64( C_10_TRACE_TRDATA_CONFIG_4 , RULL(0x2A011487), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011447, 2A011C07, +REG64( C_11_TRACE_TRDATA_CONFIG_4 , RULL(0x2B011487), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011447, 2B011C07, +REG64( C_12_TRACE_TRDATA_CONFIG_4 , RULL(0x2C011487), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011447, 2C011C07, +REG64( C_13_TRACE_TRDATA_CONFIG_4 , RULL(0x2D011487), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011447, 2D011C07, +REG64( C_14_TRACE_TRDATA_CONFIG_4 , RULL(0x2E011C07), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011447, 2E011C07, +REG64( C_15_TRACE_TRDATA_CONFIG_4 , RULL(0x2F011487), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011447, 2F011C07, +REG64( C_16_TRACE_TRDATA_CONFIG_4 , RULL(0x30011C07), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011447, 30011C07, +REG64( C_17_TRACE_TRDATA_CONFIG_4 , RULL(0x31011C07), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011447, 31011C07, +REG64( C_18_TRACE_TRDATA_CONFIG_4 , RULL(0x32011C07), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011447, 32011C07, +REG64( C_19_TRACE_TRDATA_CONFIG_4 , RULL(0x33011C07), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011447, 33011C07, +REG64( C_20_TRACE_TRDATA_CONFIG_4 , RULL(0x34011C07), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011447, 34011C07, +REG64( C_21_TRACE_TRDATA_CONFIG_4 , RULL(0x35011C07), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011447, 35011C07, +REG64( C_22_TRACE_TRDATA_CONFIG_4 , RULL(0x36011C07), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011447, 36011C07, +REG64( C_23_TRACE_TRDATA_CONFIG_4 , RULL(0x37011C07), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011447, 37011C07, +REG64( EX_TRACE_TRDATA_CONFIG_4 , RULL(0x20011447), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011447, 21011487, 21011447, +REG64( EX_0_TRACE_TRDATA_CONFIG_4 , RULL(0x20011447), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011447, 21011487, 21011447, +REG64( EX_1_TRACE_TRDATA_CONFIG_4 , RULL(0x22011447), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011447, 23011487, 23011447, +REG64( EX_2_TRACE_TRDATA_CONFIG_4 , RULL(0x24011447), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011447, 25011487, 25011447, +REG64( EX_3_TRACE_TRDATA_CONFIG_4 , RULL(0x26011447), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011447, 27011487, 27011447, +REG64( EX_4_TRACE_TRDATA_CONFIG_4 , RULL(0x28011447), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011447, 29011487, 29011447, +REG64( EX_5_TRACE_TRDATA_CONFIG_4 , RULL(0x2A011487), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011447, 2B011487, 2B011447, +REG64( EX_6_TRACE_TRDATA_CONFIG_4 , RULL(0x2C011487), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011447, 2D011487, 2D011447, +REG64( EX_7_TRACE_TRDATA_CONFIG_4 , RULL(0x2F011487), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011447, 2F011487, 2F011447, +REG64( EX_8_TRACE_TRDATA_CONFIG_4 , RULL(0x30011447), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011447, 31011487, 31011447, +REG64( EX_9_TRACE_TRDATA_CONFIG_4 , RULL(0x32011447), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011447, 33011487, 33011447, +REG64( EX_0_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x20011C07), SH_UNT_EX_0_L3 , + SH_ACS_SCOM ); //DUPS: 21011C07, +REG64( EX_10_TRACE_TRDATA_CONFIG_4 , RULL(0x34011447), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011447, 35011487, 35011447, +REG64( EX_11_TRACE_TRDATA_CONFIG_4 , RULL(0x36011447), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011447, 37011487, 37011447, +REG64( EX_10_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x34011C07), SH_UNT_EX_10_L3 , + SH_ACS_SCOM ); //DUPS: 35011C07, +REG64( EX_11_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x36011C07), SH_UNT_EX_11_L3 , + SH_ACS_SCOM ); //DUPS: 37011C07, +REG64( EX_1_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x22011C07), SH_UNT_EX_1_L3 , + SH_ACS_SCOM ); //DUPS: 23011C07, +REG64( EX_2_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x24011C07), SH_UNT_EX_2_L3 , + SH_ACS_SCOM ); //DUPS: 25011C07, +REG64( EX_3_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x26011C07), SH_UNT_EX_3_L3 , + SH_ACS_SCOM ); //DUPS: 27011C07, +REG64( EX_4_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x28011C07), SH_UNT_EX_4_L3 , + SH_ACS_SCOM ); //DUPS: 29011C07, +REG64( EX_5_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x2A011C07), SH_UNT_EX_5_L3 , + SH_ACS_SCOM ); //DUPS: 2B011C07, +REG64( EX_6_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x2C011C07), SH_UNT_EX_6_L3 , + SH_ACS_SCOM ); //DUPS: 2D011C07, +REG64( EX_7_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x2F011C07), SH_UNT_EX_7_L3 , + SH_ACS_SCOM ); //DUPS: 2F011C07, +REG64( EX_8_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x30011C07), SH_UNT_EX_8_L3 , + SH_ACS_SCOM ); //DUPS: 31011C07, +REG64( EX_9_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x32011C07), SH_UNT_EX_9_L3 , + SH_ACS_SCOM ); //DUPS: 33011C07, +REG64( EX_L3_TRACE_TRDATA_CONFIG_4 , RULL(0x20011C07), SH_UNT_EX_L3 , + SH_ACS_SCOM ); //DUPS: 21011C07, + +REG64( C_TRACE_TRDATA_CONFIG_5 , RULL(0x20011C08), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011448, 20011C08, +REG64( C_0_TRACE_TRDATA_CONFIG_5 , RULL(0x20011C08), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011448, 20011C08, +REG64( C_1_TRACE_TRDATA_CONFIG_5 , RULL(0x21011C08), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011448, 21011C08, +REG64( C_2_TRACE_TRDATA_CONFIG_5 , RULL(0x22011C08), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011448, 22011C08, +REG64( C_3_TRACE_TRDATA_CONFIG_5 , RULL(0x23011C08), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011448, 23011C08, +REG64( C_4_TRACE_TRDATA_CONFIG_5 , RULL(0x24011C08), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011448, 24011C08, +REG64( C_5_TRACE_TRDATA_CONFIG_5 , RULL(0x25011C08), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011448, 25011C08, +REG64( C_6_TRACE_TRDATA_CONFIG_5 , RULL(0x26011C08), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011448, 26011C08, +REG64( C_7_TRACE_TRDATA_CONFIG_5 , RULL(0x27011C08), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011448, 27011C08, +REG64( C_8_TRACE_TRDATA_CONFIG_5 , RULL(0x28011C08), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011448, 28011C08, +REG64( C_9_TRACE_TRDATA_CONFIG_5 , RULL(0x29011C08), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011448, 29011C08, +REG64( C_10_TRACE_TRDATA_CONFIG_5 , RULL(0x2A011488), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011448, 2A011C08, +REG64( C_11_TRACE_TRDATA_CONFIG_5 , RULL(0x2B011488), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011448, 2B011C08, +REG64( C_12_TRACE_TRDATA_CONFIG_5 , RULL(0x2C011488), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011448, 2C011C08, +REG64( C_13_TRACE_TRDATA_CONFIG_5 , RULL(0x2D011488), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011448, 2D011C08, +REG64( C_14_TRACE_TRDATA_CONFIG_5 , RULL(0x2E011C08), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011448, 2E011C08, +REG64( C_15_TRACE_TRDATA_CONFIG_5 , RULL(0x2F011488), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011448, 2F011C08, +REG64( C_16_TRACE_TRDATA_CONFIG_5 , RULL(0x30011C08), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011448, 30011C08, +REG64( C_17_TRACE_TRDATA_CONFIG_5 , RULL(0x31011C08), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011448, 31011C08, +REG64( C_18_TRACE_TRDATA_CONFIG_5 , RULL(0x32011C08), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011448, 32011C08, +REG64( C_19_TRACE_TRDATA_CONFIG_5 , RULL(0x33011C08), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011448, 33011C08, +REG64( C_20_TRACE_TRDATA_CONFIG_5 , RULL(0x34011C08), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011448, 34011C08, +REG64( C_21_TRACE_TRDATA_CONFIG_5 , RULL(0x35011C08), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011448, 35011C08, +REG64( C_22_TRACE_TRDATA_CONFIG_5 , RULL(0x36011C08), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011448, 36011C08, +REG64( C_23_TRACE_TRDATA_CONFIG_5 , RULL(0x37011C08), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011448, 37011C08, +REG64( EX_TRACE_TRDATA_CONFIG_5 , RULL(0x20011C08), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011448, 20011C08, 21011488, 21011448, 21011C08, +REG64( EX_0_TRACE_TRDATA_CONFIG_5 , RULL(0x20011C08), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011448, 20011C08, 21011488, 21011448, 21011C08, +REG64( EX_1_TRACE_TRDATA_CONFIG_5 , RULL(0x22011C08), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011448, 22011C08, 23011488, 23011448, 23011C08, +REG64( EX_2_TRACE_TRDATA_CONFIG_5 , RULL(0x24011C08), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011448, 24011C08, 25011488, 25011448, 25011C08, +REG64( EX_3_TRACE_TRDATA_CONFIG_5 , RULL(0x26011C08), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011448, 26011C08, 27011488, 27011448, 27011C08, +REG64( EX_4_TRACE_TRDATA_CONFIG_5 , RULL(0x28011C08), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011448, 28011C08, 29011488, 29011448, 29011C08, +REG64( EX_5_TRACE_TRDATA_CONFIG_5 , RULL(0x2A011488), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011448, 2A011C08, 2B011488, 2B011448, 2B011C08, +REG64( EX_6_TRACE_TRDATA_CONFIG_5 , RULL(0x2C011488), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011448, 2C011C08, 2D011488, 2D011448, 2D011C08, +REG64( EX_7_TRACE_TRDATA_CONFIG_5 , RULL(0x2F011488), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011448, 2E011C08, 2F011488, 2F011448, 2F011C08, +REG64( EX_8_TRACE_TRDATA_CONFIG_5 , RULL(0x30011C08), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011448, 30011C08, 31011488, 31011448, 31011C08, +REG64( EX_9_TRACE_TRDATA_CONFIG_5 , RULL(0x32011C08), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011448, 32011C08, 33011488, 33011448, 33011C08, +REG64( EX_10_TRACE_TRDATA_CONFIG_5 , RULL(0x34011C08), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011448, 34011C08, 35011488, 35011448, 35011C08, +REG64( EX_11_TRACE_TRDATA_CONFIG_5 , RULL(0x36011C08), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011448, 36011C08, 37011488, 37011448, 37011C08, + +REG64( C_TRACE_TRDATA_CONFIG_9 , RULL(0x20011C09), SH_UNT_C , + SH_ACS_SCOM ); //DUPS: 20011449, 20011C09, +REG64( C_0_TRACE_TRDATA_CONFIG_9 , RULL(0x20011C09), SH_UNT_C_0 , + SH_ACS_SCOM ); //DUPS: 20011449, 20011C09, +REG64( C_1_TRACE_TRDATA_CONFIG_9 , RULL(0x21011C09), SH_UNT_C_1 , + SH_ACS_SCOM ); //DUPS: 21011449, 21011C09, +REG64( C_2_TRACE_TRDATA_CONFIG_9 , RULL(0x22011C09), SH_UNT_C_2 , + SH_ACS_SCOM ); //DUPS: 22011449, 22011C09, +REG64( C_3_TRACE_TRDATA_CONFIG_9 , RULL(0x23011C09), SH_UNT_C_3 , + SH_ACS_SCOM ); //DUPS: 23011449, 23011C09, +REG64( C_4_TRACE_TRDATA_CONFIG_9 , RULL(0x24011C09), SH_UNT_C_4 , + SH_ACS_SCOM ); //DUPS: 24011449, 24011C09, +REG64( C_5_TRACE_TRDATA_CONFIG_9 , RULL(0x25011C09), SH_UNT_C_5 , + SH_ACS_SCOM ); //DUPS: 25011449, 25011C09, +REG64( C_6_TRACE_TRDATA_CONFIG_9 , RULL(0x26011C09), SH_UNT_C_6 , + SH_ACS_SCOM ); //DUPS: 26011449, 26011C09, +REG64( C_7_TRACE_TRDATA_CONFIG_9 , RULL(0x27011C09), SH_UNT_C_7 , + SH_ACS_SCOM ); //DUPS: 27011449, 27011C09, +REG64( C_8_TRACE_TRDATA_CONFIG_9 , RULL(0x28011C09), SH_UNT_C_8 , + SH_ACS_SCOM ); //DUPS: 28011449, 28011C09, +REG64( C_9_TRACE_TRDATA_CONFIG_9 , RULL(0x29011C09), SH_UNT_C_9 , + SH_ACS_SCOM ); //DUPS: 29011449, 29011C09, +REG64( C_10_TRACE_TRDATA_CONFIG_9 , RULL(0x2A011489), SH_UNT_C_10 , + SH_ACS_SCOM ); //DUPS: 2A011449, 2A011C09, +REG64( C_11_TRACE_TRDATA_CONFIG_9 , RULL(0x2B011489), SH_UNT_C_11 , + SH_ACS_SCOM ); //DUPS: 2B011449, 2B011C09, +REG64( C_12_TRACE_TRDATA_CONFIG_9 , RULL(0x2C011489), SH_UNT_C_12 , + SH_ACS_SCOM ); //DUPS: 2C011449, 2C011C09, +REG64( C_13_TRACE_TRDATA_CONFIG_9 , RULL(0x2D011489), SH_UNT_C_13 , + SH_ACS_SCOM ); //DUPS: 2D011449, 2D011C09, +REG64( C_14_TRACE_TRDATA_CONFIG_9 , RULL(0x2E011C09), SH_UNT_C_14 , + SH_ACS_SCOM ); //DUPS: 2E011449, 2E011C09, +REG64( C_15_TRACE_TRDATA_CONFIG_9 , RULL(0x2F011489), SH_UNT_C_15 , + SH_ACS_SCOM ); //DUPS: 2F011449, 2F011C09, +REG64( C_16_TRACE_TRDATA_CONFIG_9 , RULL(0x30011C09), SH_UNT_C_16 , + SH_ACS_SCOM ); //DUPS: 30011449, 30011C09, +REG64( C_17_TRACE_TRDATA_CONFIG_9 , RULL(0x31011C09), SH_UNT_C_17 , + SH_ACS_SCOM ); //DUPS: 31011449, 31011C09, +REG64( C_18_TRACE_TRDATA_CONFIG_9 , RULL(0x32011C09), SH_UNT_C_18 , + SH_ACS_SCOM ); //DUPS: 32011449, 32011C09, +REG64( C_19_TRACE_TRDATA_CONFIG_9 , RULL(0x33011C09), SH_UNT_C_19 , + SH_ACS_SCOM ); //DUPS: 33011449, 33011C09, +REG64( C_20_TRACE_TRDATA_CONFIG_9 , RULL(0x34011C09), SH_UNT_C_20 , + SH_ACS_SCOM ); //DUPS: 34011449, 34011C09, +REG64( C_21_TRACE_TRDATA_CONFIG_9 , RULL(0x35011C09), SH_UNT_C_21 , + SH_ACS_SCOM ); //DUPS: 35011449, 35011C09, +REG64( C_22_TRACE_TRDATA_CONFIG_9 , RULL(0x36011C09), SH_UNT_C_22 , + SH_ACS_SCOM ); //DUPS: 36011449, 36011C09, +REG64( C_23_TRACE_TRDATA_CONFIG_9 , RULL(0x37011C09), SH_UNT_C_23 , + SH_ACS_SCOM ); //DUPS: 37011449, 37011C09, +REG64( EX_TRACE_TRDATA_CONFIG_9 , RULL(0x20011C09), SH_UNT_EX , + SH_ACS_SCOM ); //DUPS: 20011449, 20011C09, 21011489, 21011449, 21011C09, +REG64( EX_0_TRACE_TRDATA_CONFIG_9 , RULL(0x20011C09), SH_UNT_EX_0 , + SH_ACS_SCOM ); //DUPS: 20011449, 20011C09, 21011489, 21011449, 21011C09, +REG64( EX_1_TRACE_TRDATA_CONFIG_9 , RULL(0x22011C09), SH_UNT_EX_1 , + SH_ACS_SCOM ); //DUPS: 22011449, 22011C09, 23011489, 23011449, 23011C09, +REG64( EX_2_TRACE_TRDATA_CONFIG_9 , RULL(0x24011C09), SH_UNT_EX_2 , + SH_ACS_SCOM ); //DUPS: 24011449, 24011C09, 25011489, 25011449, 25011C09, +REG64( EX_3_TRACE_TRDATA_CONFIG_9 , RULL(0x26011C09), SH_UNT_EX_3 , + SH_ACS_SCOM ); //DUPS: 26011449, 26011C09, 27011489, 27011449, 27011C09, +REG64( EX_4_TRACE_TRDATA_CONFIG_9 , RULL(0x28011C09), SH_UNT_EX_4 , + SH_ACS_SCOM ); //DUPS: 28011449, 28011C09, 29011489, 29011449, 29011C09, +REG64( EX_5_TRACE_TRDATA_CONFIG_9 , RULL(0x2A011489), SH_UNT_EX_5 , + SH_ACS_SCOM ); //DUPS: 2A011449, 2A011C09, 2B011489, 2B011449, 2B011C09, +REG64( EX_6_TRACE_TRDATA_CONFIG_9 , RULL(0x2C011489), SH_UNT_EX_6 , + SH_ACS_SCOM ); //DUPS: 2C011449, 2C011C09, 2D011489, 2D011449, 2D011C09, +REG64( EX_7_TRACE_TRDATA_CONFIG_9 , RULL(0x2F011489), SH_UNT_EX_7 , + SH_ACS_SCOM ); //DUPS: 2E011449, 2E011C09, 2F011489, 2F011449, 2F011C09, +REG64( EX_8_TRACE_TRDATA_CONFIG_9 , RULL(0x30011C09), SH_UNT_EX_8 , + SH_ACS_SCOM ); //DUPS: 30011449, 30011C09, 31011489, 31011449, 31011C09, +REG64( EX_9_TRACE_TRDATA_CONFIG_9 , RULL(0x32011C09), SH_UNT_EX_9 , + SH_ACS_SCOM ); //DUPS: 32011449, 32011C09, 33011489, 33011449, 33011C09, +REG64( EX_10_TRACE_TRDATA_CONFIG_9 , RULL(0x34011C09), SH_UNT_EX_10 , + SH_ACS_SCOM ); //DUPS: 34011449, 34011C09, 35011489, 35011449, 35011C09, +REG64( EX_11_TRACE_TRDATA_CONFIG_9 , RULL(0x36011C09), SH_UNT_EX_11 , + SH_ACS_SCOM ); //DUPS: 36011449, 36011C09, 37011489, 37011449, 37011C09, REG64( C_V0_HMER_WAND , RULL(0x20010A92), SH_UNT_C , SH_ACS_SCOM1_WAND ); @@ -23051,17 +25038,17 @@ REG64( C_22_V0_HMER_OR , RULL(0x36010A8E REG64( C_23_V0_HMER_WAND , RULL(0x37010A92), SH_UNT_C_23 , SH_ACS_SCOM1_WAND ); REG64( C_23_V0_HMER_OR , RULL(0x37010A8E), SH_UNT_C_23 , SH_ACS_SCOM2_OR ); -REG64( EX_V0_HMER , RULL(0x21010A8E), SH_UNT_EX , +REG64( EX_V0_HMER , RULL(0x20010A8E), SH_UNT_EX , SH_ACS_SCOM2_OR ); //DUPS: 20010A8E, -REG64( EX_0_V0_HMER , RULL(0x21010A8E), SH_UNT_EX_0 , +REG64( EX_0_V0_HMER , RULL(0x20010A8E), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 20010A8E, -REG64( EX_1_V0_HMER , RULL(0x23010A8E), SH_UNT_EX_1 , +REG64( EX_1_V0_HMER , RULL(0x22010A8E), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 22010A8E, -REG64( EX_2_V0_HMER , RULL(0x25010A8E), SH_UNT_EX_2 , +REG64( EX_2_V0_HMER , RULL(0x24010A8E), SH_UNT_EX_2 , SH_ACS_SCOM2_OR ); //DUPS: 24010A8E, -REG64( EX_3_V0_HMER , RULL(0x27010A8E), SH_UNT_EX_3 , +REG64( EX_3_V0_HMER , RULL(0x26010A8E), SH_UNT_EX_3 , SH_ACS_SCOM2_OR ); //DUPS: 26010A8E, -REG64( EX_4_V0_HMER , RULL(0x29010A8E), SH_UNT_EX_4 , +REG64( EX_4_V0_HMER , RULL(0x28010A8E), SH_UNT_EX_4 , SH_ACS_SCOM2_OR ); //DUPS: 28010A8E, REG64( EX_5_V0_HMER , RULL(0x2B010A8E), SH_UNT_EX_5 , SH_ACS_SCOM2_OR ); //DUPS: 2A010A8E, @@ -23069,27 +25056,27 @@ REG64( EX_6_V0_HMER , RULL(0x2D010A8E SH_ACS_SCOM2_OR ); //DUPS: 2C010A8E, REG64( EX_7_V0_HMER , RULL(0x2F010A8E), SH_UNT_EX_7 , SH_ACS_SCOM2_OR ); //DUPS: 2E010A8E, -REG64( EX_8_V0_HMER , RULL(0x31010A8E), SH_UNT_EX_8 , +REG64( EX_8_V0_HMER , RULL(0x30010A8E), SH_UNT_EX_8 , SH_ACS_SCOM2_OR ); //DUPS: 30010A8E, -REG64( EX_9_V0_HMER , RULL(0x33010A8E), SH_UNT_EX_9 , +REG64( EX_9_V0_HMER , RULL(0x32010A8E), SH_UNT_EX_9 , SH_ACS_SCOM2_OR ); //DUPS: 32010A8E, -REG64( EX_0_L2_V0_HMER , RULL(0x21010A92), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_V0_HMER , RULL(0x20010A92), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A92, -REG64( EX_10_V0_HMER , RULL(0x35010A8E), SH_UNT_EX_10 , +REG64( EX_10_V0_HMER , RULL(0x34010A8E), SH_UNT_EX_10 , SH_ACS_SCOM2_OR ); //DUPS: 34010A8E, -REG64( EX_11_V0_HMER , RULL(0x37010A8E), SH_UNT_EX_11 , +REG64( EX_11_V0_HMER , RULL(0x36010A8E), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); //DUPS: 36010A8E, -REG64( EX_10_L2_V0_HMER , RULL(0x35010A92), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_V0_HMER , RULL(0x34010A92), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 34010A92, -REG64( EX_11_L2_V0_HMER , RULL(0x37010A92), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_V0_HMER , RULL(0x36010A92), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 36010A92, -REG64( EX_1_L2_V0_HMER , RULL(0x23010A92), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_V0_HMER , RULL(0x22010A92), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 22010A92, -REG64( EX_2_L2_V0_HMER , RULL(0x25010A92), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_V0_HMER , RULL(0x24010A92), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 24010A92, -REG64( EX_3_L2_V0_HMER , RULL(0x27010A92), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_V0_HMER , RULL(0x26010A92), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 26010A92, -REG64( EX_4_L2_V0_HMER , RULL(0x29010A92), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_V0_HMER , RULL(0x28010A92), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 28010A92, REG64( EX_5_L2_V0_HMER , RULL(0x2B010A92), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 2A010A92, @@ -23097,11 +25084,11 @@ REG64( EX_6_L2_V0_HMER , RULL(0x2D010A92 SH_ACS_SCOM1_WAND ); //DUPS: 2C010A92, REG64( EX_7_L2_V0_HMER , RULL(0x2F010A92), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 2E010A92, -REG64( EX_8_L2_V0_HMER , RULL(0x31010A92), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_V0_HMER , RULL(0x30010A92), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 30010A92, -REG64( EX_9_L2_V0_HMER , RULL(0x33010A92), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_V0_HMER , RULL(0x32010A92), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 32010A92, -REG64( EX_L2_V0_HMER , RULL(0x21010A92), SH_UNT_EX_L2 , +REG64( EX_L2_V0_HMER , RULL(0x20010A92), SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A92, REG64( C_V1_HMER_WAND , RULL(0x20010A93), SH_UNT_C , @@ -23179,17 +25166,17 @@ REG64( C_22_V1_HMER_OR , RULL(0x36010A8F REG64( C_23_V1_HMER_WAND , RULL(0x37010A93), SH_UNT_C_23 , SH_ACS_SCOM1_WAND ); REG64( C_23_V1_HMER_OR , RULL(0x37010A8F), SH_UNT_C_23 , SH_ACS_SCOM2_OR ); -REG64( EX_V1_HMER , RULL(0x21010A8F), SH_UNT_EX , +REG64( EX_V1_HMER , RULL(0x20010A8F), SH_UNT_EX , SH_ACS_SCOM2_OR ); //DUPS: 20010A8F, -REG64( EX_0_V1_HMER , RULL(0x21010A8F), SH_UNT_EX_0 , +REG64( EX_0_V1_HMER , RULL(0x20010A8F), SH_UNT_EX_0 , SH_ACS_SCOM2_OR ); //DUPS: 20010A8F, -REG64( EX_1_V1_HMER , RULL(0x23010A8F), SH_UNT_EX_1 , +REG64( EX_1_V1_HMER , RULL(0x22010A8F), SH_UNT_EX_1 , SH_ACS_SCOM2_OR ); //DUPS: 22010A8F, -REG64( EX_2_V1_HMER , RULL(0x25010A8F), SH_UNT_EX_2 , +REG64( EX_2_V1_HMER , RULL(0x24010A8F), SH_UNT_EX_2 , SH_ACS_SCOM2_OR ); //DUPS: 24010A8F, -REG64( EX_3_V1_HMER , RULL(0x27010A8F), SH_UNT_EX_3 , +REG64( EX_3_V1_HMER , RULL(0x26010A8F), SH_UNT_EX_3 , SH_ACS_SCOM2_OR ); //DUPS: 26010A8F, -REG64( EX_4_V1_HMER , RULL(0x29010A8F), SH_UNT_EX_4 , +REG64( EX_4_V1_HMER , RULL(0x28010A8F), SH_UNT_EX_4 , SH_ACS_SCOM2_OR ); //DUPS: 28010A8F, REG64( EX_5_V1_HMER , RULL(0x2B010A8F), SH_UNT_EX_5 , SH_ACS_SCOM2_OR ); //DUPS: 2A010A8F, @@ -23197,27 +25184,27 @@ REG64( EX_6_V1_HMER , RULL(0x2D010A8F SH_ACS_SCOM2_OR ); //DUPS: 2C010A8F, REG64( EX_7_V1_HMER , RULL(0x2F010A8F), SH_UNT_EX_7 , SH_ACS_SCOM2_OR ); //DUPS: 2E010A8F, -REG64( EX_8_V1_HMER , RULL(0x31010A8F), SH_UNT_EX_8 , +REG64( EX_8_V1_HMER , RULL(0x30010A8F), SH_UNT_EX_8 , SH_ACS_SCOM2_OR ); //DUPS: 30010A8F, -REG64( EX_9_V1_HMER , RULL(0x33010A8F), SH_UNT_EX_9 , +REG64( EX_9_V1_HMER , RULL(0x32010A8F), SH_UNT_EX_9 , SH_ACS_SCOM2_OR ); //DUPS: 32010A8F, -REG64( EX_0_L2_V1_HMER , RULL(0x21010A93), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_V1_HMER , RULL(0x20010A93), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A93, -REG64( EX_10_V1_HMER , RULL(0x35010A8F), SH_UNT_EX_10 , +REG64( EX_10_V1_HMER , RULL(0x34010A8F), SH_UNT_EX_10 , SH_ACS_SCOM2_OR ); //DUPS: 34010A8F, -REG64( EX_11_V1_HMER , RULL(0x37010A8F), SH_UNT_EX_11 , +REG64( EX_11_V1_HMER , RULL(0x36010A8F), SH_UNT_EX_11 , SH_ACS_SCOM2_OR ); //DUPS: 36010A8F, -REG64( EX_10_L2_V1_HMER , RULL(0x35010A93), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_V1_HMER , RULL(0x34010A93), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 34010A93, -REG64( EX_11_L2_V1_HMER , RULL(0x37010A93), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_V1_HMER , RULL(0x36010A93), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 36010A93, -REG64( EX_1_L2_V1_HMER , RULL(0x23010A93), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_V1_HMER , RULL(0x22010A93), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 22010A93, -REG64( EX_2_L2_V1_HMER , RULL(0x25010A93), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_V1_HMER , RULL(0x24010A93), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 24010A93, -REG64( EX_3_L2_V1_HMER , RULL(0x27010A93), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_V1_HMER , RULL(0x26010A93), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 26010A93, -REG64( EX_4_L2_V1_HMER , RULL(0x29010A93), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_V1_HMER , RULL(0x28010A93), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 28010A93, REG64( EX_5_L2_V1_HMER , RULL(0x2B010A93), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 2A010A93, @@ -23225,11 +25212,11 @@ REG64( EX_6_L2_V1_HMER , RULL(0x2D010A93 SH_ACS_SCOM1_WAND ); //DUPS: 2C010A93, REG64( EX_7_L2_V1_HMER , RULL(0x2F010A93), SH_UNT_EX_7_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 2E010A93, -REG64( EX_8_L2_V1_HMER , RULL(0x31010A93), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_V1_HMER , RULL(0x30010A93), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 30010A93, -REG64( EX_9_L2_V1_HMER , RULL(0x33010A93), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_V1_HMER , RULL(0x32010A93), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 32010A93, -REG64( EX_L2_V1_HMER , RULL(0x21010A93), SH_UNT_EX_L2 , +REG64( EX_L2_V1_HMER , RULL(0x20010A93), SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A93, REG64( C_V2_HMER_WAND , RULL(0x20010A94), SH_UNT_C , @@ -23307,33 +25294,33 @@ REG64( C_22_V2_HMER_OR , RULL(0x36010A90 REG64( C_23_V2_HMER_WAND , RULL(0x37010A94), SH_UNT_C_23 , SH_ACS_SCOM1_WAND ); REG64( C_23_V2_HMER_OR , RULL(0x37010A90), SH_UNT_C_23 , SH_ACS_SCOM2_OR ); -REG64( EX_0_L2_V2_HMER_WAND , RULL(0x21010A94), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_V2_HMER_WAND , RULL(0x20010A94), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A94, -REG64( EX_0_L2_V2_HMER_OR , RULL(0x21010A90), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_V2_HMER_OR , RULL(0x20010A90), SH_UNT_EX_0_L2 , SH_ACS_SCOM2_OR ); //DUPS: 20010A90, -REG64( EX_10_L2_V2_HMER_WAND , RULL(0x35010A94), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_V2_HMER_WAND , RULL(0x34010A94), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 34010A94, -REG64( EX_10_L2_V2_HMER_OR , RULL(0x35010A90), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_V2_HMER_OR , RULL(0x34010A90), SH_UNT_EX_10_L2 , SH_ACS_SCOM2_OR ); //DUPS: 34010A90, -REG64( EX_11_L2_V2_HMER_WAND , RULL(0x37010A94), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_V2_HMER_WAND , RULL(0x36010A94), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 36010A94, -REG64( EX_11_L2_V2_HMER_OR , RULL(0x37010A90), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_V2_HMER_OR , RULL(0x36010A90), SH_UNT_EX_11_L2 , SH_ACS_SCOM2_OR ); //DUPS: 36010A90, -REG64( EX_1_L2_V2_HMER_WAND , RULL(0x23010A94), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_V2_HMER_WAND , RULL(0x22010A94), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 22010A94, -REG64( EX_1_L2_V2_HMER_OR , RULL(0x23010A90), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_V2_HMER_OR , RULL(0x22010A90), SH_UNT_EX_1_L2 , SH_ACS_SCOM2_OR ); //DUPS: 22010A90, -REG64( EX_2_L2_V2_HMER_WAND , RULL(0x25010A94), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_V2_HMER_WAND , RULL(0x24010A94), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 24010A94, -REG64( EX_2_L2_V2_HMER_OR , RULL(0x25010A90), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_V2_HMER_OR , RULL(0x24010A90), SH_UNT_EX_2_L2 , SH_ACS_SCOM2_OR ); //DUPS: 24010A90, -REG64( EX_3_L2_V2_HMER_WAND , RULL(0x27010A94), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_V2_HMER_WAND , RULL(0x26010A94), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 26010A94, -REG64( EX_3_L2_V2_HMER_OR , RULL(0x27010A90), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_V2_HMER_OR , RULL(0x26010A90), SH_UNT_EX_3_L2 , SH_ACS_SCOM2_OR ); //DUPS: 26010A90, -REG64( EX_4_L2_V2_HMER_WAND , RULL(0x29010A94), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_V2_HMER_WAND , RULL(0x28010A94), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 28010A94, -REG64( EX_4_L2_V2_HMER_OR , RULL(0x29010A90), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_V2_HMER_OR , RULL(0x28010A90), SH_UNT_EX_4_L2 , SH_ACS_SCOM2_OR ); //DUPS: 28010A90, REG64( EX_5_L2_V2_HMER_WAND , RULL(0x2B010A94), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 2A010A94, @@ -23347,17 +25334,17 @@ REG64( EX_7_L2_V2_HMER_WAND , RULL(0x2F010A94 SH_ACS_SCOM1_WAND ); //DUPS: 2E010A94, REG64( EX_7_L2_V2_HMER_OR , RULL(0x2F010A90), SH_UNT_EX_7_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2E010A90, -REG64( EX_8_L2_V2_HMER_WAND , RULL(0x31010A94), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_V2_HMER_WAND , RULL(0x30010A94), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 30010A94, -REG64( EX_8_L2_V2_HMER_OR , RULL(0x31010A90), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_V2_HMER_OR , RULL(0x30010A90), SH_UNT_EX_8_L2 , SH_ACS_SCOM2_OR ); //DUPS: 30010A90, -REG64( EX_9_L2_V2_HMER_WAND , RULL(0x33010A94), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_V2_HMER_WAND , RULL(0x32010A94), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 32010A94, -REG64( EX_9_L2_V2_HMER_OR , RULL(0x33010A90), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_V2_HMER_OR , RULL(0x32010A90), SH_UNT_EX_9_L2 , SH_ACS_SCOM2_OR ); //DUPS: 32010A90, -REG64( EX_L2_V2_HMER_WAND , RULL(0x21010A94), SH_UNT_EX_L2 , +REG64( EX_L2_V2_HMER_WAND , RULL(0x20010A94), SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A94, -REG64( EX_L2_V2_HMER_OR , RULL(0x21010A90), SH_UNT_EX_L2 , +REG64( EX_L2_V2_HMER_OR , RULL(0x20010A90), SH_UNT_EX_L2 , SH_ACS_SCOM2_OR ); //DUPS: 20010A90, REG64( C_V3_HMER_WAND , RULL(0x20010A95), SH_UNT_C , @@ -23435,33 +25422,33 @@ REG64( C_22_V3_HMER_OR , RULL(0x36010A91 REG64( C_23_V3_HMER_WAND , RULL(0x37010A95), SH_UNT_C_23 , SH_ACS_SCOM1_WAND ); REG64( C_23_V3_HMER_OR , RULL(0x37010A91), SH_UNT_C_23 , SH_ACS_SCOM2_OR ); -REG64( EX_0_L2_V3_HMER_WAND , RULL(0x21010A95), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_V3_HMER_WAND , RULL(0x20010A95), SH_UNT_EX_0_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A95, -REG64( EX_0_L2_V3_HMER_OR , RULL(0x21010A91), SH_UNT_EX_0_L2 , +REG64( EX_0_L2_V3_HMER_OR , RULL(0x20010A91), SH_UNT_EX_0_L2 , SH_ACS_SCOM2_OR ); //DUPS: 20010A91, -REG64( EX_10_L2_V3_HMER_WAND , RULL(0x35010A95), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_V3_HMER_WAND , RULL(0x34010A95), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 34010A95, -REG64( EX_10_L2_V3_HMER_OR , RULL(0x35010A91), SH_UNT_EX_10_L2 , +REG64( EX_10_L2_V3_HMER_OR , RULL(0x34010A91), SH_UNT_EX_10_L2 , SH_ACS_SCOM2_OR ); //DUPS: 34010A91, -REG64( EX_11_L2_V3_HMER_WAND , RULL(0x37010A95), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_V3_HMER_WAND , RULL(0x36010A95), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 36010A95, -REG64( EX_11_L2_V3_HMER_OR , RULL(0x37010A91), SH_UNT_EX_11_L2 , +REG64( EX_11_L2_V3_HMER_OR , RULL(0x36010A91), SH_UNT_EX_11_L2 , SH_ACS_SCOM2_OR ); //DUPS: 36010A91, -REG64( EX_1_L2_V3_HMER_WAND , RULL(0x23010A95), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_V3_HMER_WAND , RULL(0x22010A95), SH_UNT_EX_1_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 22010A95, -REG64( EX_1_L2_V3_HMER_OR , RULL(0x23010A91), SH_UNT_EX_1_L2 , +REG64( EX_1_L2_V3_HMER_OR , RULL(0x22010A91), SH_UNT_EX_1_L2 , SH_ACS_SCOM2_OR ); //DUPS: 22010A91, -REG64( EX_2_L2_V3_HMER_WAND , RULL(0x25010A95), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_V3_HMER_WAND , RULL(0x24010A95), SH_UNT_EX_2_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 24010A95, -REG64( EX_2_L2_V3_HMER_OR , RULL(0x25010A91), SH_UNT_EX_2_L2 , +REG64( EX_2_L2_V3_HMER_OR , RULL(0x24010A91), SH_UNT_EX_2_L2 , SH_ACS_SCOM2_OR ); //DUPS: 24010A91, -REG64( EX_3_L2_V3_HMER_WAND , RULL(0x27010A95), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_V3_HMER_WAND , RULL(0x26010A95), SH_UNT_EX_3_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 26010A95, -REG64( EX_3_L2_V3_HMER_OR , RULL(0x27010A91), SH_UNT_EX_3_L2 , +REG64( EX_3_L2_V3_HMER_OR , RULL(0x26010A91), SH_UNT_EX_3_L2 , SH_ACS_SCOM2_OR ); //DUPS: 26010A91, -REG64( EX_4_L2_V3_HMER_WAND , RULL(0x29010A95), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_V3_HMER_WAND , RULL(0x28010A95), SH_UNT_EX_4_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 28010A95, -REG64( EX_4_L2_V3_HMER_OR , RULL(0x29010A91), SH_UNT_EX_4_L2 , +REG64( EX_4_L2_V3_HMER_OR , RULL(0x28010A91), SH_UNT_EX_4_L2 , SH_ACS_SCOM2_OR ); //DUPS: 28010A91, REG64( EX_5_L2_V3_HMER_WAND , RULL(0x2B010A95), SH_UNT_EX_5_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 2A010A95, @@ -23475,17 +25462,17 @@ REG64( EX_7_L2_V3_HMER_WAND , RULL(0x2F010A95 SH_ACS_SCOM1_WAND ); //DUPS: 2E010A95, REG64( EX_7_L2_V3_HMER_OR , RULL(0x2F010A91), SH_UNT_EX_7_L2 , SH_ACS_SCOM2_OR ); //DUPS: 2E010A91, -REG64( EX_8_L2_V3_HMER_WAND , RULL(0x31010A95), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_V3_HMER_WAND , RULL(0x30010A95), SH_UNT_EX_8_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 30010A95, -REG64( EX_8_L2_V3_HMER_OR , RULL(0x31010A91), SH_UNT_EX_8_L2 , +REG64( EX_8_L2_V3_HMER_OR , RULL(0x30010A91), SH_UNT_EX_8_L2 , SH_ACS_SCOM2_OR ); //DUPS: 30010A91, -REG64( EX_9_L2_V3_HMER_WAND , RULL(0x33010A95), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_V3_HMER_WAND , RULL(0x32010A95), SH_UNT_EX_9_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 32010A95, -REG64( EX_9_L2_V3_HMER_OR , RULL(0x33010A91), SH_UNT_EX_9_L2 , +REG64( EX_9_L2_V3_HMER_OR , RULL(0x32010A91), SH_UNT_EX_9_L2 , SH_ACS_SCOM2_OR ); //DUPS: 32010A91, -REG64( EX_L2_V3_HMER_WAND , RULL(0x21010A95), SH_UNT_EX_L2 , +REG64( EX_L2_V3_HMER_WAND , RULL(0x20010A95), SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND ); //DUPS: 20010A95, -REG64( EX_L2_V3_HMER_OR , RULL(0x21010A91), SH_UNT_EX_L2 , +REG64( EX_L2_V3_HMER_OR , RULL(0x20010A91), SH_UNT_EX_L2 , SH_ACS_SCOM2_OR ); //DUPS: 20010A91, REG64( C_VITAL_SCAN_OUT , RULL(0x200F0017), SH_UNT_C , SH_ACS_SCOM_RO ); @@ -23524,7 +25511,7 @@ REG64( EX_VITAL_SCAN_OUT , RULL(0x200F0017 SH_ACS_SCOM_RO ); //DUPS: 210F0017, REG64( EX_0_VITAL_SCAN_OUT , RULL(0x200F0017), SH_UNT_EX_0 , SH_ACS_SCOM_RO ); //DUPS: 210F0017, -REG64( EX_1_VITAL_SCAN_OUT , RULL(0x230F0017), SH_UNT_EX_1 , +REG64( EX_1_VITAL_SCAN_OUT , RULL(0x220F0017), SH_UNT_EX_1 , SH_ACS_SCOM_RO ); //DUPS: 220F0017, REG64( EX_2_VITAL_SCAN_OUT , RULL(0x240F0017), SH_UNT_EX_2 , SH_ACS_SCOM_RO ); //DUPS: 250F0017, @@ -23595,7 +25582,7 @@ REG64( EX_5_WRITE_PROTECT_ENABLE_REG , RULL(0x2A010005 SH_ACS_SCOM ); //DUPS: 2B010005, REG64( EX_6_WRITE_PROTECT_ENABLE_REG , RULL(0x2C010005), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010005, -REG64( EX_7_WRITE_PROTECT_ENABLE_REG , RULL(0x2E010005), SH_UNT_EX_7 , +REG64( EX_7_WRITE_PROTECT_ENABLE_REG , RULL(0x2F010005), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010005, REG64( EX_8_WRITE_PROTECT_ENABLE_REG , RULL(0x30010005), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010005, @@ -23654,7 +25641,7 @@ REG64( EX_5_WRITE_PROTECT_RINGS_REG , RULL(0x2A010006 SH_ACS_SCOM ); //DUPS: 2B010006, REG64( EX_6_WRITE_PROTECT_RINGS_REG , RULL(0x2C010006), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D010006, -REG64( EX_7_WRITE_PROTECT_RINGS_REG , RULL(0x2E010006), SH_UNT_EX_7 , +REG64( EX_7_WRITE_PROTECT_RINGS_REG , RULL(0x2F010006), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F010006, REG64( EX_8_WRITE_PROTECT_RINGS_REG , RULL(0x30010006), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31010006, @@ -23665,19 +25652,19 @@ REG64( EX_10_WRITE_PROTECT_RINGS_REG , RULL(0x34010006 REG64( EX_11_WRITE_PROTECT_RINGS_REG , RULL(0x36010006), SH_UNT_EX_11 , SH_ACS_SCOM ); //DUPS: 37010006, -REG64( EQ_WR_EPS_REG , RULL(0x10010811), SH_UNT_EQ , +REG64( EQ_WR_EPS_REG , RULL(0x10010C11), SH_UNT_EQ , SH_ACS_SCOM ); //DUPS: 10010C11, -REG64( EQ_0_WR_EPS_REG , RULL(0x10010811), SH_UNT_EQ_0 , +REG64( EQ_0_WR_EPS_REG , RULL(0x10010C11), SH_UNT_EQ_0 , SH_ACS_SCOM ); //DUPS: 10010C11, -REG64( EQ_1_WR_EPS_REG , RULL(0x11010811), SH_UNT_EQ_1 , +REG64( EQ_1_WR_EPS_REG , RULL(0x11010C11), SH_UNT_EQ_1 , SH_ACS_SCOM ); //DUPS: 11010C11, -REG64( EQ_2_WR_EPS_REG , RULL(0x12010811), SH_UNT_EQ_2 , +REG64( EQ_2_WR_EPS_REG , RULL(0x12010C11), SH_UNT_EQ_2 , SH_ACS_SCOM ); //DUPS: 12010C11, -REG64( EQ_3_WR_EPS_REG , RULL(0x13010811), SH_UNT_EQ_3 , +REG64( EQ_3_WR_EPS_REG , RULL(0x13010C11), SH_UNT_EQ_3 , SH_ACS_SCOM ); //DUPS: 13010C11, -REG64( EQ_4_WR_EPS_REG , RULL(0x14010811), SH_UNT_EQ_4 , +REG64( EQ_4_WR_EPS_REG , RULL(0x14010C11), SH_UNT_EQ_4 , SH_ACS_SCOM ); //DUPS: 14010C11, -REG64( EQ_5_WR_EPS_REG , RULL(0x15010811), SH_UNT_EQ_5 , +REG64( EQ_5_WR_EPS_REG , RULL(0x15010C11), SH_UNT_EQ_5 , SH_ACS_SCOM ); //DUPS: 15010C11, REG64( EX_0_L2_WR_EPS_REG , RULL(0x10010811), SH_UNT_EX_0_L2 , SH_ACS_SCOM ); REG64( EX_10_L2_WR_EPS_REG , RULL(0x15010811), SH_UNT_EX_10_L2 , SH_ACS_SCOM ); @@ -23741,7 +25728,7 @@ REG64( EX_5_XFIR , RULL(0x2A040000 SH_ACS_SCOM ); //DUPS: 2B040000, REG64( EX_6_XFIR , RULL(0x2C040000), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D040000, -REG64( EX_7_XFIR , RULL(0x2E040000), SH_UNT_EX_7 , +REG64( EX_7_XFIR , RULL(0x2F040000), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F040000, REG64( EX_8_XFIR , RULL(0x30040000), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 31040000, @@ -23800,7 +25787,7 @@ REG64( EX_5_XSTOP1 , RULL(0x2A03000C SH_ACS_SCOM ); //DUPS: 2B03000C, REG64( EX_6_XSTOP1 , RULL(0x2C03000C), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D03000C, -REG64( EX_7_XSTOP1 , RULL(0x2E03000C), SH_UNT_EX_7 , +REG64( EX_7_XSTOP1 , RULL(0x2F03000C), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F03000C, REG64( EX_8_XSTOP1 , RULL(0x3003000C), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3103000C, @@ -23859,7 +25846,7 @@ REG64( EX_5_XSTOP2 , RULL(0x2A03000D SH_ACS_SCOM ); //DUPS: 2B03000D, REG64( EX_6_XSTOP2 , RULL(0x2C03000D), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D03000D, -REG64( EX_7_XSTOP2 , RULL(0x2E03000D), SH_UNT_EX_7 , +REG64( EX_7_XSTOP2 , RULL(0x2F03000D), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F03000D, REG64( EX_8_XSTOP2 , RULL(0x3003000D), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3103000D, @@ -23918,7 +25905,7 @@ REG64( EX_5_XSTOP3 , RULL(0x2A03000E SH_ACS_SCOM ); //DUPS: 2B03000E, REG64( EX_6_XSTOP3 , RULL(0x2C03000E), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D03000E, -REG64( EX_7_XSTOP3 , RULL(0x2E03000E), SH_UNT_EX_7 , +REG64( EX_7_XSTOP3 , RULL(0x2F03000E), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F03000E, REG64( EX_8_XSTOP3 , RULL(0x3003000E), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 3103000E, @@ -23965,7 +25952,7 @@ REG64( EX_XSTOP_INTERRUPT_REG , RULL(0x200F001C SH_ACS_SCOM ); //DUPS: 210F001C, REG64( EX_0_XSTOP_INTERRUPT_REG , RULL(0x200F001C), SH_UNT_EX_0 , SH_ACS_SCOM ); //DUPS: 210F001C, -REG64( EX_1_XSTOP_INTERRUPT_REG , RULL(0x230F001C), SH_UNT_EX_1 , +REG64( EX_1_XSTOP_INTERRUPT_REG , RULL(0x220F001C), SH_UNT_EX_1 , SH_ACS_SCOM ); //DUPS: 220F001C, REG64( EX_2_XSTOP_INTERRUPT_REG , RULL(0x240F001C), SH_UNT_EX_2 , SH_ACS_SCOM ); //DUPS: 250F001C, @@ -24036,7 +26023,7 @@ REG64( EX_5_XTRA_TRACE_MODE , RULL(0x2A0107D1 SH_ACS_SCOM ); //DUPS: 2B0107D1, REG64( EX_6_XTRA_TRACE_MODE , RULL(0x2C0107D1), SH_UNT_EX_6 , SH_ACS_SCOM ); //DUPS: 2D0107D1, -REG64( EX_7_XTRA_TRACE_MODE , RULL(0x2E0107D1), SH_UNT_EX_7 , +REG64( EX_7_XTRA_TRACE_MODE , RULL(0x2F0107D1), SH_UNT_EX_7 , SH_ACS_SCOM ); //DUPS: 2F0107D1, REG64( EX_8_XTRA_TRACE_MODE , RULL(0x300107D1), SH_UNT_EX_8 , SH_ACS_SCOM ); //DUPS: 310107D1, diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H index d299f20f..44846c04 100644 --- a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H @@ -104,6 +104,27 @@ REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); +REG64_FLD( EQ_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ATTN ); +REG64_FLD( EQ_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_RECOV ); +REG64_FLD( EQ_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSTOP ); + +REG64_FLD( EX_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ATTN ); +REG64_FLD( EX_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RECOV ); +REG64_FLD( EX_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSTOP ); + +REG64_FLD( C_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ATTN ); +REG64_FLD( C_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RECOV ); +REG64_FLD( C_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , @@ -152,6 +173,15 @@ REG64_FLD( C_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UN REG64_FLD( C_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); +REG64_FLD( EQ_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ATTN ); + +REG64_FLD( EX_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ATTN ); + +REG64_FLD( C_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ATTN ); + REG64_FLD( EQ_BIST_TC_START_TEST_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_START_TEST_DC ); REG64_FLD( EQ_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_EQ , SH_ACS_SCOM , @@ -647,6 +677,10 @@ REG64_FLD( EX_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UN SH_FLD_TRACE_MODE_SEL ); REG64_FLD( EX_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( EX_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_EX , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15 ); +REG64_FLD( EX_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_EX , SH_ACS_PPE2 , + SH_FLD_RESERVED12_15_LEN ); REG64_FLD( EX_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( EX_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_EX , SH_ACS_PPE2 , @@ -657,6 +691,8 @@ REG64_FLD( EX_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UN SH_FLD_TRACE_DATA_SEL ); REG64_FLD( EX_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); +REG64_FLD( EX_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_EX , SH_ACS_PPE2 , + SH_FLD_HALT_INPUT ); REG64_FLD( EQ_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_MASK ); @@ -866,6 +902,16 @@ REG64_FLD( EX_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UN REG64_FLD( EX_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_42_43_LEN ); +REG64_FLD( EQ_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( EQ_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_STATUS_LEN ); + +REG64_FLD( EX_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_STATUS ); +REG64_FLD( EX_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_INTERRUPT_STATUS_LEN ); + REG64_FLD( EQ_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( EQ_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , @@ -904,21 +950,6 @@ REG64_FLD( EX_CME_LCL_ICSR_COMM_SEND , 0 , SH_UN REG64_FLD( EX_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); -REG64_FLD( EX_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_RESET_IMPRECISE_QERR ); -REG64_FLD( EX_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_SET_ECC_INJECT_ERR ); -REG64_FLD( EX_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( EX_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); -REG64_FLD( EX_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_FENCE_EISR ); -REG64_FLD( EX_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); -REG64_FLD( EX_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_EX , SH_ACS_PPE , - SH_FLD_PC_DISABLE_DROOP ); - REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , @@ -1392,96 +1423,6 @@ REG64_FLD( EX_CME_SCOM_FLAGS_DATA , 0 , SH_UN REG64_FLD( EX_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DATA_LEN ); -REG64_FLD( EQ_CME_SCOM_FWMR_PMCR_OVERRIDE_EN , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_PMCR_OVERRIDE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_PSCR_OVERRIDE_EN , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_PSCR_OVERRIDE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_PMSR_OVERRIDE_EN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_PMSR_OVERRIDE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_BCESCR_OVERRIDE_EN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_BCESCR_OVERRIDE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_IDR_LCL_SAMPLE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_VDM_LCL_SAMPLE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_FREQ_LCL_SAMPLE_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_LOCK_PCB_ON_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_LOCK_PCB_ON_ERR ); -REG64_FLD( EQ_CME_SCOM_FWMR_QUEUED_WR_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_QUEUED_WR_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_QUEUED_RD_EN , 9 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_QUEUED_RD_EN ); -REG64_FLD( EQ_CME_SCOM_FWMR_MASK_PURGE_INTERFACE , 10 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_MASK_PURGE_INTERFACE ); -REG64_FLD( EQ_CME_SCOM_FWMR_IGNORE_PECE , 11 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_IGNORE_PECE ); -REG64_FLD( EQ_CME_SCOM_FWMR_STOP_OVERRIDE_MODE , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_STOP_OVERRIDE_MODE ); -REG64_FLD( EQ_CME_SCOM_FWMR_STOP_ACTIVE_MASK , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_STOP_ACTIVE_MASK ); -REG64_FLD( EQ_CME_SCOM_FWMR_AUTO_STOP1_DISABLE , 18 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_AUTO_STOP1_DISABLE ); -REG64_FLD( EQ_CME_SCOM_FWMR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_STOP1_ACTIVE_ENABLE ); -REG64_FLD( EQ_CME_SCOM_FWMR_FENCE_EISR , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_FENCE_EISR ); -REG64_FLD( EQ_CME_SCOM_FWMR_PC_DISABLE_DROOP , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_PC_DISABLE_DROOP ); -REG64_FLD( EQ_CME_SCOM_FWMR_SPARE_22_23 , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_SPARE_22_23 ); -REG64_FLD( EQ_CME_SCOM_FWMR_SPARE_22_23_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_SPARE_22_23_LEN ); -REG64_FLD( EQ_CME_SCOM_FWMR_AVG_FREQ_TSEL , 24 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_AVG_FREQ_TSEL ); -REG64_FLD( EQ_CME_SCOM_FWMR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , - SH_FLD_AVG_FREQ_TSEL_LEN ); - -REG64_FLD( EX_CME_SCOM_FWMR_PMCR_OVERRIDE_EN , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_PMCR_OVERRIDE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_PSCR_OVERRIDE_EN , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_PSCR_OVERRIDE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_PMSR_OVERRIDE_EN , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_PMSR_OVERRIDE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_BCESCR_OVERRIDE_EN , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_BCESCR_OVERRIDE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_IDR_LCL_SAMPLE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_VDM_LCL_SAMPLE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_FREQ_LCL_SAMPLE_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_LOCK_PCB_ON_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_LOCK_PCB_ON_ERR ); -REG64_FLD( EX_CME_SCOM_FWMR_QUEUED_WR_EN , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_QUEUED_WR_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_QUEUED_RD_EN , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_QUEUED_RD_EN ); -REG64_FLD( EX_CME_SCOM_FWMR_MASK_PURGE_INTERFACE , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_MASK_PURGE_INTERFACE ); -REG64_FLD( EX_CME_SCOM_FWMR_IGNORE_PECE , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_IGNORE_PECE ); -REG64_FLD( EX_CME_SCOM_FWMR_STOP_OVERRIDE_MODE , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_STOP_OVERRIDE_MODE ); -REG64_FLD( EX_CME_SCOM_FWMR_STOP_ACTIVE_MASK , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_STOP_ACTIVE_MASK ); -REG64_FLD( EX_CME_SCOM_FWMR_AUTO_STOP1_DISABLE , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_AUTO_STOP1_DISABLE ); -REG64_FLD( EX_CME_SCOM_FWMR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_STOP1_ACTIVE_ENABLE ); -REG64_FLD( EX_CME_SCOM_FWMR_FENCE_EISR , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_FENCE_EISR ); -REG64_FLD( EX_CME_SCOM_FWMR_PC_DISABLE_DROOP , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_PC_DISABLE_DROOP ); -REG64_FLD( EX_CME_SCOM_FWMR_SPARE_22_23 , 22 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_SPARE_22_23 ); -REG64_FLD( EX_CME_SCOM_FWMR_SPARE_22_23_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_SPARE_22_23_LEN ); -REG64_FLD( EX_CME_SCOM_FWMR_AVG_FREQ_TSEL , 24 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_AVG_FREQ_TSEL ); -REG64_FLD( EX_CME_SCOM_FWMR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , - SH_FLD_AVG_FREQ_TSEL_LEN ); - REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , @@ -1576,9 +1517,25 @@ REG64_FLD( EQ_CME_SCOM_LFIR_BCE_ERROR , 10 , SH_UN SH_FLD_BCE_ERROR ); REG64_FLD( EQ_CME_SCOM_LFIR_SPARE11 , 11 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE11 ); -REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , +REG64_FLD( EQ_CME_SCOM_LFIR_SPARE12 , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_SPARE12 ); +REG64_FLD( EQ_CME_SCOM_LFIR_C0_IVRM_DROPOUT , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_C0_IVRM_DROPOUT ); +REG64_FLD( EQ_CME_SCOM_LFIR_C1_IVRM_DROPOUT , 14 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_C1_IVRM_DROPOUT ); +REG64_FLD( EQ_CME_SCOM_LFIR_CACHE_IVRM_DROPOUT , 15 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_CACHE_IVRM_DROPOUT ); +REG64_FLD( EQ_CME_SCOM_LFIR_EXTREME_DROOP_ERR , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_EXTREME_DROOP_ERR ); +REG64_FLD( EQ_CME_SCOM_LFIR_LARGE_DROOP_ERR , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_LARGE_DROOP_ERR ); +REG64_FLD( EQ_CME_SCOM_LFIR_SMALL_DROOP_ERR , 18 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_SMALL_DROOP_ERR ); +REG64_FLD( EQ_CME_SCOM_LFIR_UNEXPECTED_DROOP_ENCODE , 19 , SH_UNT_EQ , SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTED_DROOP_ENCODE ); +REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_DUP ); -REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , +REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_INTERNAL_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , @@ -1605,41 +1562,179 @@ REG64_FLD( EX_CME_SCOM_LFIR_BCE_ERROR , 10 , SH_UN SH_FLD_BCE_ERROR ); REG64_FLD( EX_CME_SCOM_LFIR_SPARE11 , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE11 ); -REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , +REG64_FLD( EX_CME_SCOM_LFIR_SPARE12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE12 ); +REG64_FLD( EX_CME_SCOM_LFIR_C0_IVRM_DROPOUT , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_C0_IVRM_DROPOUT ); +REG64_FLD( EX_CME_SCOM_LFIR_C1_IVRM_DROPOUT , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_C1_IVRM_DROPOUT ); +REG64_FLD( EX_CME_SCOM_LFIR_CACHE_IVRM_DROPOUT , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_CACHE_IVRM_DROPOUT ); +REG64_FLD( EX_CME_SCOM_LFIR_EXTREME_DROOP_ERR , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_EXTREME_DROOP_ERR ); +REG64_FLD( EX_CME_SCOM_LFIR_LARGE_DROOP_ERR , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_LARGE_DROOP_ERR ); +REG64_FLD( EX_CME_SCOM_LFIR_SMALL_DROOP_ERR , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SMALL_DROOP_ERR ); +REG64_FLD( EX_CME_SCOM_LFIR_UNEXPECTED_DROOP_ENCODE , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_UNEXPECTED_DROOP_ENCODE ); +REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_DUP ); -REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , +REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0 ); -REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , +REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0_LEN ); REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0 ); -REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , +REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0_LEN ); REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1 ); -REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , +REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1_LEN ); REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1 ); -REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , +REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1_LEN ); REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); -REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK_LEN , 14 , SH_UNT_EQ , SH_ACS_SCOM2_OR , +REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); -REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK_LEN , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , +REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); +REG64_FLD( EQ_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( EQ_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( EQ_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPARE_11 ); +REG64_FLD( EQ_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( EQ_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( EQ_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( EQ_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( EQ_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( EQ_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( EQ_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( EQ_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( EQ_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( EQ_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( EQ_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( EQ_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( EQ_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( EQ_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SET_ECC_INJECT_ERR ); + +REG64_FLD( EX_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_PMCR_OVERRIDE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_PSCR_OVERRIDE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_PMSR_OVERRIDE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_BCECSR_OVERRIDE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_IDR_LCL_SAMPLE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_VDM_LCL_SAMPLE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_FREQ_LCL_SAMPLE_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_LOCK_PCB_ON_ERR ); +REG64_FLD( EX_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_QUEUED_WR_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_QUEUED_RD_EN ); +REG64_FLD( EX_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_MASK_PURGE_INTERFACE ); +REG64_FLD( EX_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPARE_11 ); +REG64_FLD( EX_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( EX_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); +REG64_FLD( EX_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( EX_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); +REG64_FLD( EX_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_STOP_OVERRIDE_MODE ); +REG64_FLD( EX_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_STOP_ACTIVE_MASK ); +REG64_FLD( EX_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_AUTO_STOP1_DISABLE ); +REG64_FLD( EX_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_STOP1_ACTIVE_ENABLE ); +REG64_FLD( EX_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_FENCE_EISR ); +REG64_FLD( EX_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_PC_DISABLE_DROOP ); +REG64_FLD( EX_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPARE_22_23 ); +REG64_FLD( EX_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPARE_22_23_LEN ); +REG64_FLD( EX_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_AVG_FREQ_TSEL ); +REG64_FLD( EX_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_AVG_FREQ_TSEL_LEN ); +REG64_FLD( EX_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPARE_28_31 ); +REG64_FLD( EX_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPARE_28_31_LEN ); +REG64_FLD( EX_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_RESET_IMPRECISE_QERR ); +REG64_FLD( EX_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SET_ECC_INJECT_ERR ); + REG64_FLD( EQ_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , @@ -2352,8 +2447,8 @@ REG64_FLD( EQ_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( EQ_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( EQ_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , - SH_FLD_RESERVED20 ); +REG64_FLD( EQ_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( EQ_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( EQ_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_EQ , SH_ACS_SCOM2 , @@ -2413,8 +2508,8 @@ REG64_FLD( EX_CME_SCOM_SICR_L2_PURGE , 18 , SH_UN SH_FLD_L2_PURGE ); REG64_FLD( EX_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( EX_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_EX , SH_ACS_SCOM2 , - SH_FLD_RESERVED20 ); +REG64_FLD( EX_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( EX_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( EX_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_EX , SH_ACS_SCOM2 , @@ -2730,6 +2825,46 @@ REG64_FLD( EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UN REG64_FLD( EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_OVERVOLT_CTR_LEN ); +REG64_FLD( EQ_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA ); +REG64_FLD( EQ_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( EX_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA ); +REG64_FLD( EX_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( EQ_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA ); +REG64_FLD( EQ_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( EX_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA ); +REG64_FLD( EX_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_DATA_LEN ); + +REG64_FLD( EQ_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO ); +REG64_FLD( EQ_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( EX_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO ); +REG64_FLD( EX_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( EQ_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO ); +REG64_FLD( EQ_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO_LEN ); + +REG64_FLD( EX_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO ); +REG64_FLD( EX_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCBM_INFO_LEN ); + REG64_FLD( EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO ); REG64_FLD( EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , @@ -2750,6 +2885,1479 @@ REG64_FLD( EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO , 0 , SH_UN REG64_FLD( EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO_LEN ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_ADDR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_ADDR ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_ADDR_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_ADDR_LEN ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_R_NW , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_R_NW ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_BUSY , 33 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_BUSY ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_RSP_INFO , 49 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_RSP_INFO ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_RSP_INFO_LEN ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); +REG64_FLD( EQ_CME_SCOM_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PIB_DATAOP_PENDING ); + +REG64_FLD( EX_CME_SCOM_XISIB_PIB_ADDR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_ADDR ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_ADDR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_ADDR_LEN ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_R_NW , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_R_NW ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_BUSY , 33 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_BUSY ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_RSP_INFO , 49 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_RSP_INFO ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_RSP_INFO_LEN ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); +REG64_FLD( EX_CME_SCOM_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PIB_DATAOP_PENDING ); + +REG64_FLD( EQ_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_RESET_TRIP_HISTORY ); +REG64_FLD( EQ_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_PULSE_CNT ); +REG64_FLD( EQ_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_RD ); +REG64_FLD( EQ_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_WR ); +REG64_FLD( EQ_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_DTS ); +REG64_FLD( EQ_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS ); +REG64_FLD( EQ_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); +REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L1RESULTS ); +REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L2RESULTS ); +REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L3RESULTS ); +REG64_FLD( EQ_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); +REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_MEASURE_VOLT ); +REG64_FLD( EQ_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_FORCE_SHIFT_SENSOR ); + +REG64_FLD( EX_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RESET_TRIP_HISTORY ); +REG64_FLD( EX_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_PULSE_CNT ); +REG64_FLD( EX_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_RD ); +REG64_FLD( EX_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_WR ); +REG64_FLD( EX_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_DTS ); +REG64_FLD( EX_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS ); +REG64_FLD( EX_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); +REG64_FLD( EX_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L1RESULTS ); +REG64_FLD( EX_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L2RESULTS ); +REG64_FLD( EX_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L3RESULTS ); +REG64_FLD( EX_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); +REG64_FLD( EX_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_MEASURE_VOLT ); +REG64_FLD( EX_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_FORCE_SHIFT_SENSOR ); + +REG64_FLD( C_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESET_TRIP_HISTORY ); +REG64_FLD( C_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_PULSE_CNT ); +REG64_FLD( C_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_RD ); +REG64_FLD( C_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_F_RESET_CPM_WR ); +REG64_FLD( C_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESET_SAMPLE_DTS ); +REG64_FLD( C_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS ); +REG64_FLD( C_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); +REG64_FLD( C_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L1RESULTS ); +REG64_FLD( C_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L2RESULTS ); +REG64_FLD( C_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_THRES_L3RESULTS ); +REG64_FLD( C_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); +REG64_FLD( C_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_RESET_MEASURE_VOLT ); +REG64_FLD( C_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FORCE_SHIFT_SENSOR ); + +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_SRAM_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_6 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_7 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_CI_UE_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_18 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_19 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_21 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_22 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_23 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SETDELETE_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_40 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_42 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_44 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_46 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HYP_RES_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_49 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_50 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_51 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_54 ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SCOM_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( C_CORE_ACTION0_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_SRAM_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_6 ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_7 ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_CI_UE_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_18 ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_19 ); +REG64_FLD( C_CORE_ACTION0_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_21 ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_22 ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_23 ); +REG64_FLD( C_CORE_ACTION0_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SETDELETE_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_40 ); +REG64_FLD( C_CORE_ACTION0_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_42 ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_44 ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_46 ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HYP_RES_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_49 ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_50 ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_51 ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_54 ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SCOM_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION0_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_SRAM_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_6 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_7 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_CI_UE_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_18 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_19 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_21 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_22 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_23 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SETDELETE_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_40 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_42 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_44 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_46 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HYP_RES_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_49 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_50 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_51 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_54 ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SCOM_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( C_CORE_ACTION1_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_SRAM_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_6 ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_7 ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_CI_UE_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_18 ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_19 ); +REG64_FLD( C_CORE_ACTION1_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_21 ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_22 ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_23 ); +REG64_FLD( C_CORE_ACTION1_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SETDELETE_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_40 ); +REG64_FLD( C_CORE_ACTION1_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_42 ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_44 ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_46 ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HYP_RES_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_49 ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_50 ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_51 ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_UNUSED_54 ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_SCOM_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( C_CORE_ACTION1_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( EX_L2_CORE_FIR_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_IF_SRAM_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_TC_FIR_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_IF_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_IF_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_IF_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_6 ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_7 ); +REG64_FLD( EX_L2_CORE_FIR_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_L2_UE_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_CI_UE_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_18 ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_19 ); +REG64_FLD( EX_L2_CORE_FIR_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SD_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_21 ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_22 ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_23 ); +REG64_FLD( EX_L2_CORE_FIR_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_VS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_VS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_VS_DU_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_SRAM_PARITY_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_SETDELETE_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_NOT_MT_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_40 ); +REG64_FLD( EX_L2_CORE_FIR_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LS_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_42 ); +REG64_FLD( EX_L2_CORE_FIR_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_44 ); +REG64_FLD( EX_L2_CORE_FIR_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_46 ); +REG64_FLD( EX_L2_CORE_FIR_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_HYP_RES_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_49 ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_50 ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_51 ); +REG64_FLD( EX_L2_CORE_FIR_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( EX_L2_CORE_FIR_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_CORE_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_54 ); +REG64_FLD( EX_L2_CORE_FIR_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_OTHER_CORE_CHIPLET_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_SCOM_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_FW_INJ_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIR_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( C_CORE_FIR_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_IF_SRAM_REC_ERROR ); +REG64_FLD( C_CORE_FIR_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_TC_FIR_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_IF_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_FIR_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_IF_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIR_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_IF_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_6 ); +REG64_FLD( C_CORE_FIR_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_7 ); +REG64_FLD( C_CORE_FIR_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_FIR_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIR_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( C_CORE_FIR_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( C_CORE_FIR_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_L2_UE_ERROR ); +REG64_FLD( C_CORE_FIR_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( C_CORE_FIR_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_CI_UE_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_18 ); +REG64_FLD( C_CORE_FIR_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_19 ); +REG64_FLD( C_CORE_FIR_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SD_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_21 ); +REG64_FLD( C_CORE_FIR_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_22 ); +REG64_FLD( C_CORE_FIR_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_23 ); +REG64_FLD( C_CORE_FIR_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_VS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIR_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_VS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( C_CORE_FIR_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_VS_DU_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIR_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_SRAM_PARITY_ERROR ); +REG64_FLD( C_CORE_FIR_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_SETDELETE_ERROR ); +REG64_FLD( C_CORE_FIR_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_FIR_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_FIR_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_FIR_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_FIR_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( C_CORE_FIR_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIR_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_NOT_MT_REC_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_40 ); +REG64_FLD( C_CORE_FIR_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_LS_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_42 ); +REG64_FLD( C_CORE_FIR_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_44 ); +REG64_FLD( C_CORE_FIR_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_46 ); +REG64_FLD( C_CORE_FIR_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_HYP_RES_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_49 ); +REG64_FLD( C_CORE_FIR_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_50 ); +REG64_FLD( C_CORE_FIR_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_51 ); +REG64_FLD( C_CORE_FIR_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( C_CORE_FIR_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_CORE_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_FIR_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED_54 ); +REG64_FLD( C_CORE_FIR_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_FIR_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_OTHER_CORE_CHIPLET_REC_ERROR ); +REG64_FLD( C_CORE_FIR_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_SCOM_ERROR ); +REG64_FLD( C_CORE_FIR_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( C_CORE_FIR_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_FW_INJ_REC_ERROR ); +REG64_FLD( C_CORE_FIR_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIR_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_SRAM_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_TC_FIR_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_6 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_7 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_L2_UE_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_CI_UE_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_18 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_19 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_21 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_22 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_23 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_VS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_VS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_VS_DU_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SRAM_PARITY_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SETDELETE_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_RFILE_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_LOG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_NOT_MT_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_40 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_42 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_44 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_LOG_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_46 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_HYP_RES_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_49 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_50 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_51 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_54 ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_OTHER_CHIPLET_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_SCOM_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_FW_INJ_REC_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( C_CORE_FIRMASK_MASK_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_SRAM_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_TC_FIR_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_IF_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_6 ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_7 ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_L2_UE_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_CI_UE_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_18 ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_19 ); +REG64_FLD( C_CORE_FIRMASK_MASK_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_SD_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_21 ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_22 ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_23 ); +REG64_FLD( C_CORE_FIRMASK_MASK_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_VS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_VS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_VS_DU_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SRAM_PARITY_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SETDELETE_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_NOT_MT_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_40 ); +REG64_FLD( C_CORE_FIRMASK_MASK_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LS_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_42 ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_44 ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_46 ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_HYP_RES_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_49 ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_50 ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_51 ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_UNUSED_54 ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_OTHER_CHIPLET_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_SCOM_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_FW_INJ_REC_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( C_CORE_FIRMASK_MASK_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_MASK_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( EX_L2_CORE_FUSES_FP_THROTTLE_EN , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_FP_THROTTLE_EN ); +REG64_FLD( EX_L2_CORE_FUSES_VMX_CRYPTO_DIS , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VMX_CRYPTO_DIS ); + +REG64_FLD( C_CORE_FUSES_FP_THROTTLE_EN , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_FP_THROTTLE_EN ); +REG64_FLD( C_CORE_FUSES_VMX_CRYPTO_DIS , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VMX_CRYPTO_DIS ); + +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT0_PSSCR_RL , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT0_PSSCR_RL ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT0_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT0_PSSCR_RL_LEN ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT1_PSSCR_RL , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT1_PSSCR_RL ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT1_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT1_PSSCR_RL_LEN ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT2_PSSCR_RL , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT2_PSSCR_RL ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT2_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT2_PSSCR_RL_LEN ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT3_PSSCR_RL , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT3_PSSCR_RL ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT3_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT3_PSSCR_RL_LEN ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT0_STOP_STATE , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT0_STOP_STATE ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT1_STOP_STATE , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT1_STOP_STATE ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT2_STOP_STATE , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT2_STOP_STATE ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_VT3_STOP_STATE , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT3_STOP_STATE ); +REG64_FLD( EX_L2_CORE_THREAD_STATE_LPAR_FUSED_CORE_MODE , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LPAR_FUSED_CORE_MODE ); + +REG64_FLD( C_CORE_THREAD_STATE_VT0_PSSCR_RL , 32 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT0_PSSCR_RL ); +REG64_FLD( C_CORE_THREAD_STATE_VT0_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT0_PSSCR_RL_LEN ); +REG64_FLD( C_CORE_THREAD_STATE_VT1_PSSCR_RL , 36 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT1_PSSCR_RL ); +REG64_FLD( C_CORE_THREAD_STATE_VT1_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT1_PSSCR_RL_LEN ); +REG64_FLD( C_CORE_THREAD_STATE_VT2_PSSCR_RL , 40 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT2_PSSCR_RL ); +REG64_FLD( C_CORE_THREAD_STATE_VT2_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT2_PSSCR_RL_LEN ); +REG64_FLD( C_CORE_THREAD_STATE_VT3_PSSCR_RL , 44 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT3_PSSCR_RL ); +REG64_FLD( C_CORE_THREAD_STATE_VT3_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT3_PSSCR_RL_LEN ); +REG64_FLD( C_CORE_THREAD_STATE_VT0_STOP_STATE , 56 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT0_STOP_STATE ); +REG64_FLD( C_CORE_THREAD_STATE_VT1_STOP_STATE , 57 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT1_STOP_STATE ); +REG64_FLD( C_CORE_THREAD_STATE_VT2_STOP_STATE , 58 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT2_STOP_STATE ); +REG64_FLD( C_CORE_THREAD_STATE_VT3_STOP_STATE , 59 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT3_STOP_STATE ); +REG64_FLD( C_CORE_THREAD_STATE_LPAR_FUSED_CORE_MODE , 63 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LPAR_FUSED_CORE_MODE ); + +REG64_FLD( EX_CORE_WOF_WOF_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_SRAM_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_TC_FIR_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_RFILE_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_IF_LOG_REC_ERROR , 4 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_LOG_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_LOG_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_6 , 6 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_6 ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_7 , 7 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_7 ); +REG64_FLD( EX_CORE_WOF_WOF_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_RFILE_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_LOG_REC_ERROR , 11 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_LOG_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_LOG_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_L2_UE_ERROR , 15 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_L2_UE_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_SD_CI_UE_ERROR , 17 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_CI_UE_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_18 , 18 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_18 ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_19 , 19 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_19 ); +REG64_FLD( EX_CORE_WOF_WOF_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_SYS_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_21 , 21 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_21 ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_22 , 22 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_22 ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_23 , 23 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_23 ); +REG64_FLD( EX_CORE_WOF_WOF_VS_LOG_REC_ERROR , 24 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_VS_LOG_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_VS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_VS_DU_LOG_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_SYS_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SRAM_PARITY_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_SETDELETE_ERROR , 30 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SETDELETE_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_RFILE_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_LOG_REC_ERROR , 37 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_LOG_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_LOG_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_NOT_MT_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_40 , 40 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_40 ); +REG64_FLD( EX_CORE_WOF_WOF_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SYS_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_42 , 42 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_42 ); +REG64_FLD( EX_CORE_WOF_WOF_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_44 , 44 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_44 ); +REG64_FLD( EX_CORE_WOF_WOF_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_LOG_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_46 , 46 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_46 ); +REG64_FLD( EX_CORE_WOF_WOF_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_HYP_RES_ERROR , 48 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_HYP_RES_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_49 , 49 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_49 ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_50 , 50 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_50 ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_51 , 51 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_51 ); +REG64_FLD( EX_CORE_WOF_WOF_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( EX_CORE_WOF_WOF_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_CORE_HANG_DETECT_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_UNUSED_54 , 54 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_54 ); +REG64_FLD( EX_CORE_WOF_WOF_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_SCOM_ERROR , 59 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_SCOM_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_FW_INJ_REC_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( EX_CORE_WOF_WOF_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_PHYP_XSTOP_ERROR ); + +REG64_FLD( C_CORE_WOF_WOF_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_SRAM_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_TC_FIR_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_LOG_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_IF_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_6 ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_7 ); +REG64_FLD( C_CORE_WOF_WOF_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_RECOV_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_LOG_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_NOT_MT_CI_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_MCHK_AND_ME_EQ_0_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_L2_UE_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_L2_UE_OVER_THRES_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_CI_UE_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_18 ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_19 ); +REG64_FLD( C_CORE_WOF_WOF_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_SD_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_21 ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_22 ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_23 ); +REG64_FLD( C_CORE_WOF_WOF_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_VS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_VS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_RECOV_IN_MAINT_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_VS_DU_LOG_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SRAM_PARITY_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SETDELETE_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_RFILE_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_RFILE_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_TLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SLB_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_DERAT_MULTIHIT_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_FWD_PROGRESS_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_LOG_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_NOT_MT_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_40 ); +REG64_FLD( C_CORE_WOF_WOF_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LS_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_42 ); +REG64_FLD( C_CORE_WOF_WOF_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_THREAD_HANG_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_44 ); +REG64_FLD( C_CORE_WOF_WOF_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_LOG_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_46 ); +REG64_FLD( C_CORE_WOF_WOF_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_TFAC_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_HYP_RES_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_49 ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_50 ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_51 ); +REG64_FLD( C_CORE_WOF_WOF_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_HANG_RECOVERY_FAILED ); +REG64_FLD( C_CORE_WOF_WOF_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_CORE_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_UNUSED_54 ); +REG64_FLD( C_CORE_WOF_WOF_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_NEST_HANG_DETECT_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_SCOM_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_FW_INJ_REC_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_FW_INJ_XSTOP_ERROR ); +REG64_FLD( C_CORE_WOF_WOF_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_PC_PHYP_XSTOP_ERROR ); + REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, @@ -3005,42 +4613,36 @@ REG64_FLD( C_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UN REG64_FLD( C_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); -REG64_FLD( EQ_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_0D ); -REG64_FLD( EQ_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_1D ); -REG64_FLD( EQ_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_2D ); -REG64_FLD( EQ_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_3D ); -REG64_FLD( EQ_CPLT_CONF1_TC_PBIOO0_IOVALID , 4 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBIOO0_IOVALID ); -REG64_FLD( EQ_CPLT_CONF1_TC_PBIOO1_IOVALID , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PBIOO1_IOVALID ); -REG64_FLD( EQ_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_6D ); -REG64_FLD( EQ_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_7D ); -REG64_FLD( EQ_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_8D ); -REG64_FLD( EQ_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_9D ); -REG64_FLD( EQ_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_10D ); -REG64_FLD( EQ_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_11D ); -REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_12D ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_EQ ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_PWR_UP ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_PWR_DN ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_L3_UP ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_L3_DN ); +REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_13D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_14D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_15D ); -REG64_FLD( EQ_CPLT_CONF1_TC_OB_RATIO_DC , 16 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_OB_RATIO_DC ); -REG64_FLD( EQ_CPLT_CONF1_TC_OB_RATIO_DC_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_OB_RATIO_DC_LEN ); +REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_16D ); +REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_17D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_18D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, @@ -3070,26 +4672,38 @@ REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UN REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ , 0 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_EQ ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_UP ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_DN ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_UP ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_DN ); -REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN ); +REG64_FLD( EX_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_0D ); +REG64_FLD( EX_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_1D ); +REG64_FLD( EX_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_2D ); +REG64_FLD( EX_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_3D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_4D , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_4D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_5D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_6D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_7D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_8D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_9D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_10D ); +REG64_FLD( EX_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_11D ); +REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_12D ); +REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_13D ); +REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_14D ); +REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_15D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, @@ -3123,26 +4737,38 @@ REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UN REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ , 0 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_EQ ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_UP ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_DN ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_UP ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_DN ); -REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN ); +REG64_FLD( C_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_0D ); +REG64_FLD( C_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_1D ); +REG64_FLD( C_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_2D ); +REG64_FLD( C_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_3D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_4D , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_4D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_5D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_6D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_7D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_8D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_9D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_10D ); +REG64_FLD( C_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_11D ); +REG64_FLD( C_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_12D ); +REG64_FLD( C_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_13D ); +REG64_FLD( C_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_14D ); +REG64_FLD( C_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_15D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, @@ -3188,8 +4814,8 @@ REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC , 4 , SH_UN SH_FLD_TC_UNIT_ARY_WRT_THRU_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_AVP_MODE , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_AVP_MODE ); -REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_6A , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_FREE_USAGE_6A ); +REG64_FLD( EQ_CPLT_CTRL0_TC_BIT6_CHIPLET_ID_DC , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_BIT6_CHIPLET_ID_DC ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_7A , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_7A ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, @@ -3537,24 +5163,24 @@ REG64_FLD( EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE , 3 , SH_UN SH_FLD_TC_VITL_REGION_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE , 4 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PERV_REGION_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_5B , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_5B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_6B , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_6B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_7B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_8B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_9B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_10B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_11B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_12B ); -REG64_FLD( EQ_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_13B ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION1_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION2_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION3_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION4_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION5_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION6_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION7_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION8_FENCE , 12 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION8_FENCE ); +REG64_FLD( EQ_CPLT_CTRL1_TC_REGION9_FENCE , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION9_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( EQ_CPLT_CTRL1_RESERVED , 15 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, @@ -3606,20 +5232,20 @@ REG64_FLD( EX_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UN SH_FLD_TC_REGION1_FENCE ); REG64_FLD( EX_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION3_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION4_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION5_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION6_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION7_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION8_FENCE , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION8_FENCE ); -REG64_FLD( EX_CPLT_CTRL1_TC_REGION9_FENCE , 13 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION9_FENCE ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_7B ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_8B ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_9B ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_10B ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_11B ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_12B ); +REG64_FLD( EX_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_13B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( EX_CPLT_CTRL1_RESERVED , 15 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, @@ -3671,20 +5297,20 @@ REG64_FLD( C_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UN SH_FLD_TC_REGION1_FENCE ); REG64_FLD( C_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION3_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION4_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION5_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION6_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION7_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION8_FENCE , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION8_FENCE ); -REG64_FLD( C_CPLT_CTRL1_TC_REGION9_FENCE , 13 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION9_FENCE ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_7B ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_8B ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_9B ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_10B ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_11B ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_12B ); +REG64_FLD( C_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_13B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( C_CPLT_CTRL1_RESERVED , 15 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, @@ -3806,10 +5432,10 @@ REG64_FLD( EX_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UN SH_FLD_CC_CTRL_OPCG_DONE_DC ); REG64_FLD( EX_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); -REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_10E , 10 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_FREE_USAGE_10E ); -REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_11E , 11 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_FREE_USAGE_11E ); +REG64_FLD( EX_CPLT_STAT0_PC_TC_VALID_NOT_HV_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PC_TC_VALID_NOT_HV_MODE ); +REG64_FLD( EX_CPLT_STAT0_PC_TC_AVP_OUT , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PC_TC_AVP_OUT ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_12E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_EX , SH_ACS_SCOM , @@ -3855,10 +5481,10 @@ REG64_FLD( C_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UN SH_FLD_CC_CTRL_OPCG_DONE_DC ); REG64_FLD( C_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); -REG64_FLD( C_CPLT_STAT0_FREE_USAGE_10E , 10 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_FREE_USAGE_10E ); -REG64_FLD( C_CPLT_STAT0_FREE_USAGE_11E , 11 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_FREE_USAGE_11E ); +REG64_FLD( C_CPLT_STAT0_PC_TC_VALID_NOT_HV_MODE , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PC_TC_VALID_NOT_HV_MODE ); +REG64_FLD( C_CPLT_STAT0_PC_TC_AVP_OUT , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PC_TC_AVP_OUT ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_12E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_C , SH_ACS_SCOM , @@ -3976,6 +5602,98 @@ REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_SPARE , 12 , SH_UN REG64_FLD( C_CPPM_CACSR_CLK_SYNC_DONE , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_CLK_SYNC_DONE ); +REG64_FLD( EX_CPPM_CIIR_MSGSND_INTR_INJECT , 28 , SH_UNT_EX , SH_ACS_SCOM_4P , + SH_FLD_MSGSND_INTR_INJECT ); +REG64_FLD( EX_CPPM_CIIR_MSGSND_INTR_INJECT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_4P , + SH_FLD_MSGSND_INTR_INJECT_LEN ); + +REG64_FLD( C_CPPM_CIIR_MSGSND_INTR_INJECT , 28 , SH_UNT_C , SH_ACS_SCOM_4P , + SH_FLD_MSGSND_INTR_INJECT ); +REG64_FLD( C_CPPM_CIIR_MSGSND_INTR_INJECT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_4P , + SH_FLD_MSGSND_INTR_INJECT_LEN ); + +REG64_FLD( EX_CPPM_CISR_HYP_INTR_PRESENT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_PRESENT ); +REG64_FLD( EX_CPPM_CISR_HYP_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_PRESENT_LEN ); +REG64_FLD( EX_CPPM_CISR_OS_INTR_PRESENT , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_PRESENT ); +REG64_FLD( EX_CPPM_CISR_OS_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_PRESENT_LEN ); +REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_PRESENT , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_PRESENT ); +REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_PRESENT_LEN ); +REG64_FLD( EX_CPPM_CISR_EBB_INTR_PRESENT , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_EBB_INTR_PRESENT ); +REG64_FLD( EX_CPPM_CISR_EBB_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_EBB_INTR_PRESENT_LEN ); +REG64_FLD( EX_CPPM_CISR_HYP_INTR_REQUESTED , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_REQUESTED ); +REG64_FLD( EX_CPPM_CISR_HYP_INTR_REQUESTED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_REQUESTED_LEN ); +REG64_FLD( EX_CPPM_CISR_OS_INTR_REQUESTED , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_REQUESTED ); +REG64_FLD( EX_CPPM_CISR_OS_INTR_REQUESTED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_REQUESTED_LEN ); +REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_REQUESTED , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_REQUESTED ); +REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_REQUESTED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_REQUESTED_LEN ); +REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_SAMPLE , 28 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_SAMPLE ); +REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_SAMPLE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_SAMPLE_LEN ); +REG64_FLD( EX_CPPM_CISR_MSGSND_ACK , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_ACK ); +REG64_FLD( EX_CPPM_CISR_MALF_ALERT_PRESENT , 33 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MALF_ALERT_PRESENT ); +REG64_FLD( EX_CPPM_CISR_MALF_ALERT_REQUESTED , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MALF_ALERT_REQUESTED ); +REG64_FLD( EX_CPPM_CISR_CME_SPECIAL_WKUP_DONE , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_CME_SPECIAL_WKUP_DONE ); + +REG64_FLD( C_CPPM_CISR_HYP_INTR_PRESENT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_PRESENT ); +REG64_FLD( C_CPPM_CISR_HYP_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_PRESENT_LEN ); +REG64_FLD( C_CPPM_CISR_OS_INTR_PRESENT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_PRESENT ); +REG64_FLD( C_CPPM_CISR_OS_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_PRESENT_LEN ); +REG64_FLD( C_CPPM_CISR_MSGSND_INTR_PRESENT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_PRESENT ); +REG64_FLD( C_CPPM_CISR_MSGSND_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_PRESENT_LEN ); +REG64_FLD( C_CPPM_CISR_EBB_INTR_PRESENT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_EBB_INTR_PRESENT ); +REG64_FLD( C_CPPM_CISR_EBB_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_EBB_INTR_PRESENT_LEN ); +REG64_FLD( C_CPPM_CISR_HYP_INTR_REQUESTED , 16 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_REQUESTED ); +REG64_FLD( C_CPPM_CISR_HYP_INTR_REQUESTED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_HYP_INTR_REQUESTED_LEN ); +REG64_FLD( C_CPPM_CISR_OS_INTR_REQUESTED , 20 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_REQUESTED ); +REG64_FLD( C_CPPM_CISR_OS_INTR_REQUESTED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_OS_INTR_REQUESTED_LEN ); +REG64_FLD( C_CPPM_CISR_MSGSND_INTR_REQUESTED , 24 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_REQUESTED ); +REG64_FLD( C_CPPM_CISR_MSGSND_INTR_REQUESTED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_REQUESTED_LEN ); +REG64_FLD( C_CPPM_CISR_MSGSND_INTR_SAMPLE , 28 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_SAMPLE ); +REG64_FLD( C_CPPM_CISR_MSGSND_INTR_SAMPLE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_INTR_SAMPLE_LEN ); +REG64_FLD( C_CPPM_CISR_MSGSND_ACK , 32 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MSGSND_ACK ); +REG64_FLD( C_CPPM_CISR_MALF_ALERT_PRESENT , 33 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MALF_ALERT_PRESENT ); +REG64_FLD( C_CPPM_CISR_MALF_ALERT_REQUESTED , 34 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MALF_ALERT_REQUESTED ); +REG64_FLD( C_CPPM_CISR_CME_SPECIAL_WKUP_DONE , 35 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_CME_SPECIAL_WKUP_DONE ); + REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_LOCAL_CONTROL ); REG64_FLD( EX_CPPM_CIVRMLCR_RESERVED_1_2 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , @@ -4138,45 +5856,53 @@ REG64_FLD( EX_CPPM_ERR_PCB_INTERRUPT_PROTOCOL , 0 , SH_UN SH_FLD_PCB_INTERRUPT_PROTOCOL ); REG64_FLD( EX_CPPM_ERR_SPECIAL_WKUP_PROTOCOL , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_PROTOCOL ); -REG64_FLD( EX_CPPM_ERR_PFET_SEQ_PROGRAM , 2 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_CPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL ); +REG64_FLD( EX_CPPM_ERR_PFET_SEQ_PROGRAM , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PFET_SEQ_PROGRAM ); -REG64_FLD( EX_CPPM_ERR_CLK_SYNC , 3 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_CPPM_ERR_CLK_SYNC , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLK_SYNC ); -REG64_FLD( EX_CPPM_ERR_PECE_INTR_DISABLED , 4 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_CPPM_ERR_PECE_INTR_DISABLED , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PECE_INTR_DISABLED ); -REG64_FLD( EX_CPPM_ERR_DECONFIGURED_INTR , 5 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_CPPM_ERR_DECONFIGURED_INTR , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DECONFIGURED_INTR ); -REG64_FLD( EX_CPPM_ERR_RESERVED_6_7 , 6 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_RESERVED_6_7 ); -REG64_FLD( EX_CPPM_ERR_RESERVED_6_7_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_RESERVED_6_7_LEN ); +REG64_FLD( EX_CPPM_ERR_RESERVED_7 , 7 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RESERVED_7 ); +REG64_FLD( EX_CPPM_ERR_RESERVED_8_11 , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RESERVED_8_11 ); +REG64_FLD( EX_CPPM_ERR_RESERVED_8_11_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RESERVED_8_11_LEN ); REG64_FLD( C_CPPM_ERR_PCB_INTERRUPT_PROTOCOL , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_INTERRUPT_PROTOCOL ); REG64_FLD( C_CPPM_ERR_SPECIAL_WKUP_PROTOCOL , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_PROTOCOL ); -REG64_FLD( C_CPPM_ERR_PFET_SEQ_PROGRAM , 2 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_CPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL ); +REG64_FLD( C_CPPM_ERR_PFET_SEQ_PROGRAM , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PFET_SEQ_PROGRAM ); -REG64_FLD( C_CPPM_ERR_CLK_SYNC , 3 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_CPPM_ERR_CLK_SYNC , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLK_SYNC ); -REG64_FLD( C_CPPM_ERR_PECE_INTR_DISABLED , 4 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_CPPM_ERR_PECE_INTR_DISABLED , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PECE_INTR_DISABLED ); -REG64_FLD( C_CPPM_ERR_DECONFIGURED_INTR , 5 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_CPPM_ERR_DECONFIGURED_INTR , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DECONFIGURED_INTR ); -REG64_FLD( C_CPPM_ERR_RESERVED_6_7 , 6 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_RESERVED_6_7 ); -REG64_FLD( C_CPPM_ERR_RESERVED_6_7_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_RESERVED_6_7_LEN ); - -REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_7 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_7 ); -REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_7_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_7_LEN ); - -REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_7 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_7 ); -REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_7_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_7_LEN ); +REG64_FLD( C_CPPM_ERR_RESERVED_7 , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESERVED_7 ); +REG64_FLD( C_CPPM_ERR_RESERVED_8_11 , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESERVED_8_11 ); +REG64_FLD( C_CPPM_ERR_RESERVED_8_11_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESERVED_8_11_LEN ); + +REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_11 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_11 ); +REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_11_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_11_LEN ); + +REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_11 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_11 ); +REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_11_LEN , 12 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_11_LEN ); REG64_FLD( EX_CPPM_IPPMCMD_QPPM_REG , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_REG ); @@ -4230,6 +5956,68 @@ REG64_FLD( C_CPPM_IPPMWDATA_QPPM_WDATA , 0 , SH_UN REG64_FLD( C_CPPM_IPPMWDATA_QPPM_WDATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_WDATA_LEN ); +REG64_FLD( EX_CPPM_NC0INDIR_NC_N_INDIRECT , 0 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT ); +REG64_FLD( EX_CPPM_NC0INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT_LEN ); + +REG64_FLD( C_CPPM_NC0INDIR_NC_N_INDIRECT , 0 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT ); +REG64_FLD( C_CPPM_NC0INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT_LEN ); + +REG64_FLD( EX_CPPM_NC1INDIR_NC_N_INDIRECT , 0 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT ); +REG64_FLD( EX_CPPM_NC1INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT_LEN ); + +REG64_FLD( C_CPPM_NC1INDIR_NC_N_INDIRECT , 0 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT ); +REG64_FLD( C_CPPM_NC1INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_NC_N_INDIRECT_LEN ); + +REG64_FLD( EX_CPPM_PECES_PECE_T0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T0 ); +REG64_FLD( EX_CPPM_PECES_PECE_T0_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T0_LEN ); +REG64_FLD( EX_CPPM_PECES_PECE_T1 , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T1 ); +REG64_FLD( EX_CPPM_PECES_PECE_T1_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T1_LEN ); +REG64_FLD( EX_CPPM_PECES_PECE_T2 , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T2 ); +REG64_FLD( EX_CPPM_PECES_PECE_T2_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T2_LEN ); +REG64_FLD( EX_CPPM_PECES_PECE_T3 , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T3 ); +REG64_FLD( EX_CPPM_PECES_PECE_T3_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PECE_T3_LEN ); +REG64_FLD( EX_CPPM_PECES_USE_PECE , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_USE_PECE ); +REG64_FLD( EX_CPPM_PECES_USE_PECE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_USE_PECE_LEN ); + +REG64_FLD( C_CPPM_PECES_PECE_T0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T0 ); +REG64_FLD( C_CPPM_PECES_PECE_T0_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T0_LEN ); +REG64_FLD( C_CPPM_PECES_PECE_T1 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T1 ); +REG64_FLD( C_CPPM_PECES_PECE_T1_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T1_LEN ); +REG64_FLD( C_CPPM_PECES_PECE_T2 , 16 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T2 ); +REG64_FLD( C_CPPM_PECES_PECE_T2_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T2_LEN ); +REG64_FLD( C_CPPM_PECES_PECE_T3 , 24 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T3 ); +REG64_FLD( C_CPPM_PECES_PECE_T3_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PECE_T3_LEN ); +REG64_FLD( C_CPPM_PECES_USE_PECE , 32 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_USE_PECE ); +REG64_FLD( C_CPPM_PECES_USE_PECE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_USE_PECE_LEN ); + REG64_FLD( EX_CPPM_PERRSUM_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM_WCLEAR, SH_FLD_ERROR ); @@ -4314,6 +6102,8 @@ REG64_FLD( EX_L2_CTRL_T6_RUN_Q , 54 , SH_UN SH_FLD_T6_RUN_Q ); REG64_FLD( EX_L2_CTRL_T7_RUN_Q , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T7_RUN_Q ); +REG64_FLD( EX_L2_CTRL_RUN_LATCH , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , + SH_FLD_RUN_LATCH ); REG64_FLD( C_CTRL_T0_RUN_Q , 48 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T0_RUN_Q ); @@ -4331,6 +6121,8 @@ REG64_FLD( C_CTRL_T6_RUN_Q , 54 , SH_UN SH_FLD_T6_RUN_Q ); REG64_FLD( C_CTRL_T7_RUN_Q , 55 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T7_RUN_Q ); +REG64_FLD( C_CTRL_RUN_LATCH , 63 , SH_UNT_C , SH_ACS_SCOM_NC , + SH_FLD_RUN_LATCH ); REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE ); @@ -5089,10 +6881,14 @@ REG64_FLD( EQ_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( EQ_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( EQ_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_EQ , SH_ACS_SCOM , +REG64_FLD( EQ_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( EQ_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_EQ , SH_ACS_SCOM , +REG64_FLD( EQ_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( EQ_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( EQ_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_EQ , SH_ACS_SCOM , @@ -5101,15 +6897,23 @@ REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( EQ_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( EQ_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( EQ_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( EX_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( EX_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( EX_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( EX_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( EX_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( EX_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( EX_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_EX , SH_ACS_SCOM , @@ -5118,15 +6922,23 @@ REG64_FLD( EX_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( EX_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( EX_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( EX_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( C_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( C_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( C_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( C_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( C_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( C_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( C_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( C_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_C , SH_ACS_SCOM , @@ -5135,6 +6947,10 @@ REG64_FLD( C_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( C_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( C_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( C_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); @@ -5577,6 +7393,189 @@ REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UN REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + +REG64_FLD( EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + +REG64_FLD( C_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( C_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( C_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CLEAR_MAINT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T0_CLEAR_MAINT ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_SRESET_REQUEST , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T0_SRESET_REQUEST ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CORE_STEP , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T0_CORE_STEP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CORE_START , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T0_CORE_START ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CORE_STOP , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T0_CORE_STOP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CLEAR_MAINT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T1_CLEAR_MAINT ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_SRESET_REQUEST , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T1_SRESET_REQUEST ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CORE_STEP , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T1_CORE_STEP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CORE_START , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T1_CORE_START ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CORE_STOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T1_CORE_STOP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CLEAR_MAINT , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T2_CLEAR_MAINT ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_SRESET_REQUEST , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T2_SRESET_REQUEST ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CORE_STEP , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T2_CORE_STEP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CORE_START , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T2_CORE_START ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CORE_STOP , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T2_CORE_STOP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CLEAR_MAINT , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T3_CLEAR_MAINT ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_SRESET_REQUEST , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T3_SRESET_REQUEST ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CORE_STEP , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T3_CORE_STEP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CORE_START , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T3_CORE_START ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CORE_STOP , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_DC_T3_CORE_STOP ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T0_PM_STATE , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_WRITE_T0_PM_STATE ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_PLS , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_PLS ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_PLS_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_SRR1 , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_SRR1 ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_SRR1_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T1_PM_STATE , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_WRITE_T1_PM_STATE ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_PLS , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_PLS ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_PLS_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_SRR1 , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_SRR1 ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_SRR1_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T2_PM_STATE , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_WRITE_T2_PM_STATE ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_PLS , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_PLS ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_PLS_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_SRR1 , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_SRR1 ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_SRR1_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T3_PM_STATE , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_WRITE_T3_PM_STATE ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_PLS , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_PLS ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_PLS_LEN ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_SRR1 , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_SRR1 ); +REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_SRR1_LEN ); + +REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CLEAR_MAINT , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T0_CLEAR_MAINT ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T0_SRESET_REQUEST , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T0_SRESET_REQUEST ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CORE_STEP , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T0_CORE_STEP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CORE_START , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T0_CORE_START ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CORE_STOP , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T0_CORE_STOP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CLEAR_MAINT , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T1_CLEAR_MAINT ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T1_SRESET_REQUEST , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T1_SRESET_REQUEST ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CORE_STEP , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T1_CORE_STEP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CORE_START , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T1_CORE_START ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CORE_STOP , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T1_CORE_STOP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CLEAR_MAINT , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T2_CLEAR_MAINT ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T2_SRESET_REQUEST , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T2_SRESET_REQUEST ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CORE_STEP , 21 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T2_CORE_STEP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CORE_START , 22 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T2_CORE_START ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CORE_STOP , 23 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T2_CORE_STOP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CLEAR_MAINT , 27 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T3_CLEAR_MAINT ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T3_SRESET_REQUEST , 28 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T3_SRESET_REQUEST ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CORE_STEP , 29 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T3_CORE_STEP ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CORE_START , 30 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T3_CORE_START ); +REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CORE_STOP , 31 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DC_T3_CORE_STOP ); +REG64_FLD( C_DIRECT_CONTROLS_WRITE_T0_PM_STATE , 32 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WRITE_T0_PM_STATE ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_PLS , 33 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_PLS ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_PLS_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_SRR1 , 37 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_SRR1 ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T0_SRR1_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_WRITE_T1_PM_STATE , 40 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WRITE_T1_PM_STATE ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_PLS , 41 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_PLS ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_PLS_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_SRR1 , 45 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_SRR1 ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T1_SRR1_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_WRITE_T2_PM_STATE , 48 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WRITE_T2_PM_STATE ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_PLS , 49 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_PLS ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_PLS_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_SRR1 , 53 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_SRR1 ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T2_SRR1_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_WRITE_T3_PM_STATE , 56 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WRITE_T3_PM_STATE ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_PLS , 57 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_PLS ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_PLS_LEN ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_SRR1 , 61 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_SRR1 ); +REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSSCR_T3_SRR1_LEN ); + REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MAJOR ); REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , @@ -5725,6 +7724,21 @@ REG64_FLD( EX_L3_EDRAM_REG_L3_UTIL_MON_BITS , 7 , SH_UN REG64_FLD( EX_L3_EDRAM_REG_L3_UTIL_MON_BITS_LEN , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_UTIL_MON_BITS_LEN ); +REG64_FLD( EQ_EDRAM_STATUS_STAT , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STAT ); +REG64_FLD( EQ_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STAT_LEN ); + +REG64_FLD( EX_EDRAM_STATUS_STAT , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STAT ); +REG64_FLD( EX_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STAT_LEN ); + +REG64_FLD( C_EDRAM_STATUS_STAT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STAT ); +REG64_FLD( C_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STAT_LEN ); + REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_VAL , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_VAL ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE , 1 , SH_UNT_EQ , SH_ACS_SCOM , @@ -5819,8 +7833,8 @@ REG64_FLD( EQ_ERROR_REG_PCB_INTERFACE , 16 , SH_UN SH_FLD_PCB_INTERFACE ); REG64_FLD( EQ_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); -REG64_FLD( EQ_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_CHIPLET_GRID_SKITTER ); +REG64_FLD( EQ_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( EQ_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( EQ_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_EQ , SH_ACS_SCOM , @@ -5872,8 +7886,8 @@ REG64_FLD( EX_ERROR_REG_PCB_INTERFACE , 16 , SH_UN SH_FLD_PCB_INTERFACE ); REG64_FLD( EX_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); -REG64_FLD( EX_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_CHIPLET_GRID_SKITTER ); +REG64_FLD( EX_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( EX_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( EX_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_EX , SH_ACS_SCOM , @@ -5925,8 +7939,8 @@ REG64_FLD( C_ERROR_REG_PCB_INTERFACE , 16 , SH_UN SH_FLD_PCB_INTERFACE ); REG64_FLD( C_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); -REG64_FLD( C_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_CHIPLET_GRID_SKITTER ); +REG64_FLD( C_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( C_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( C_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_C , SH_ACS_SCOM , @@ -5944,20 +7958,200 @@ REG64_FLD( C_ERROR_REG_PLL_UNLOCK , 25 , SH_UN REG64_FLD( C_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); -REG64_FLD( EQ_ERROR_STATUS_ERRORS , 0 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_ERRORS ); -REG64_FLD( EQ_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_ERRORS_LEN ); - -REG64_FLD( EX_ERROR_STATUS_ERRORS , 0 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_ERRORS ); -REG64_FLD( EX_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_ERRORS_LEN ); - -REG64_FLD( C_ERROR_STATUS_ERRORS , 0 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_ERRORS ); -REG64_FLD( C_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_ERRORS_LEN ); +REG64_FLD( EQ_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_CMD_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_ADDR_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_DATA_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); +REG64_FLD( EQ_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); +REG64_FLD( EQ_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_CONFLICT_ERR ); +REG64_FLD( EQ_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SCAN_COLLISION_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); +REG64_FLD( EQ_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_OPCG_TRIGGER_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PHASE_CNT_CORRUPTION_ERR ); +REG64_FLD( EQ_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_PREVENTED_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_SM_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_REG_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_XSTOP_REG_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_GPIO_REG_ERR ); +REG64_FLD( EQ_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_CLKCMD_REQUEST_ERR ); +REG64_FLD( EQ_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_CBS_PROTOCOL_ERR ); +REG64_FLD( EQ_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_VITL_ALIGN_ERR ); +REG64_FLD( EQ_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNIT_SYNC_LVL_ERR ); +REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); +REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR27 ); +REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR28 ); +REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR29 ); +REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR30 ); +REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR31 ); + +REG64_FLD( EX_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_CMD_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_ADDR_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_DATA_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); +REG64_FLD( EX_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); +REG64_FLD( EX_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); +REG64_FLD( EX_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_CONFLICT_ERR ); +REG64_FLD( EX_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SCAN_COLLISION_ERR ); +REG64_FLD( EX_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); +REG64_FLD( EX_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_OPCG_TRIGGER_ERR ); +REG64_FLD( EX_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PHASE_CNT_CORRUPTION_ERR ); +REG64_FLD( EX_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_PREVENTED_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_SM_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_REG_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_XSTOP_REG_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_GPIO_REG_ERR ); +REG64_FLD( EX_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CLKCMD_REQUEST_ERR ); +REG64_FLD( EX_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CBS_PROTOCOL_ERR ); +REG64_FLD( EX_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_VITL_ALIGN_ERR ); +REG64_FLD( EX_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNIT_SYNC_LVL_ERR ); +REG64_FLD( EX_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); +REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR27 ); +REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR28 ); +REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR29 ); +REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR30 ); +REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR31 ); + +REG64_FLD( C_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_CMD_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_ADDR_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_DATA_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); +REG64_FLD( C_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); +REG64_FLD( C_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); +REG64_FLD( C_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_CONFLICT_ERR ); +REG64_FLD( C_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SCAN_COLLISION_ERR ); +REG64_FLD( C_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); +REG64_FLD( C_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_OPCG_TRIGGER_ERR ); +REG64_FLD( C_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PHASE_CNT_CORRUPTION_ERR ); +REG64_FLD( C_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_PREVENTED_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_SM_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_OPCG_REG_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_XSTOP_REG_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_GPIO_REG_ERR ); +REG64_FLD( C_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CLKCMD_REQUEST_ERR ); +REG64_FLD( C_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CBS_PROTOCOL_ERR ); +REG64_FLD( C_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VITL_ALIGN_ERR ); +REG64_FLD( C_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNIT_SYNC_LVL_ERR ); +REG64_FLD( C_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); +REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR27 ); +REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR28 ); +REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR29 ); +REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR30 ); +REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED_ERROR31 ); REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_CAC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SINGLE_CAC ); @@ -5978,6 +8172,39 @@ REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_LRU , 7 , SH_UN REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_LRU , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SOLID_LRU ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCSET0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCSET0 ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCSET1 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCSET1 ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCSET2 , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCSET2 ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD0 , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLICE_DCD0 ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD1 , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLICE_DCD1 ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD2 , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLICE_DCD2 ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCACHE , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCACHE ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DDIR , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DDIR ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SETP , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SETP ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DERAT , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DERAT ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DERAT_MULTIHIT , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DERAT_MULTIHIT ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLB , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLB ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLB_MULTIHIT , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLB_MULTIHIT ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_ITLB , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_ITLB ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DTLB , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DTLB ); +REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DTLB_MULTIHIT , 15 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DTLB_MULTIHIT ); + REG64_FLD( EX_L2_ERR_INJ_REG_DW_TYPE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DW_TYPE ); REG64_FLD( EX_L2_ERR_INJ_REG_DW_TYPE_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , @@ -5996,6 +8223,41 @@ REG64_FLD( EX_L2_ERR_INJ_REG_CPI_TYPE_LEN , 3 , SH_UN SH_FLD_CPI_TYPE_LEN ); REG64_FLD( EX_L2_ERR_INJ_REG_LVDIR_EN , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_LVDIR_EN ); +REG64_FLD( EX_L2_ERR_INJ_REG_LRU_EN , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_LRU_EN ); + +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCSET0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCSET0 ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCSET1 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCSET1 ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCSET2 , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCSET2 ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD0 , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLICE_DCD0 ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD1 , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLICE_DCD1 ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD2 , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLICE_DCD2 ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCACHE , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DCACHE ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DDIR , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DDIR ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SETP , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SETP ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DERAT , 9 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DERAT ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DERAT_MULTIHIT , 10 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DERAT_MULTIHIT ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLB , 11 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLB ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLB_MULTIHIT , 12 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_SLB_MULTIHIT ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_ITLB , 13 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_ITLB ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DTLB , 14 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DTLB ); +REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DTLB_MULTIHIT , 15 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ERROR_INJ_DTLB_MULTIHIT ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_CAC , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SINGLE_CAC ); @@ -6016,6 +8278,8 @@ REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_LRU , 7 , SH_UN REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_LRU , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SOLID_LRU ); +REG64_FLD( EQ_ERR_RPT0_RSV , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_RSV ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_RLD_BARRIER ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_SNP , 2 , SH_UNT_EQ , SH_ACS_SCOM , @@ -6099,6 +8363,8 @@ REG64_FLD( EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP , 40 , SH_UN REG64_FLD( EQ_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP ); +REG64_FLD( EX_L2_ERR_RPT0_RSV , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RSV ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_RLD_BARRIER ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_SNP , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , @@ -6422,6 +8688,38 @@ REG64_FLD( EX_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC , 28 , SH_UN REG64_FLD( EX_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR19_ST_TGT_NODAL_DINC ); +REG64_FLD( EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_STATE_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_ERR_HOLD ); +REG64_FLD( EQ_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , @@ -6452,7 +8750,69 @@ REG64_FLD( EQ_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); +REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT_LEN ); +REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT_LEN ); +REG64_FLD( EQ_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_DTS_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_VOLT_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT_LEN ); +REG64_FLD( EQ_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT_LEN ); +REG64_FLD( EQ_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_SAMPLE_DTS_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_MEASURE_VOLT_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_READ_CPM_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CPM_LT ); +REG64_FLD( EQ_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); +REG64_FLD( EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_STATE_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_ERR_HOLD ); +REG64_FLD( EX_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , @@ -6483,7 +8843,69 @@ REG64_FLD( EX_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( EX_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); +REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT ); +REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT_LEN ); +REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT ); +REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT_LEN ); +REG64_FLD( EX_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_DTS_LT ); +REG64_FLD( EX_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_VOLT_LT ); +REG64_FLD( EX_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT ); +REG64_FLD( EX_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT_LEN ); +REG64_FLD( EX_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT ); +REG64_FLD( EX_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT_LEN ); +REG64_FLD( EX_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_SAMPLE_DTS_LT ); +REG64_FLD( EX_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_MEASURE_VOLT_LT ); +REG64_FLD( EX_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_READ_CPM_LT ); +REG64_FLD( EX_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CPM_LT ); +REG64_FLD( EX_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); +REG64_FLD( C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_STATE_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_ERR_HOLD ); +REG64_FLD( C_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_C , SH_ACS_SCOM_RO , @@ -6514,6 +8936,36 @@ REG64_FLD( C_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( C_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); +REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT ); +REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_LT_LEN ); +REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT ); +REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_LT_LEN ); +REG64_FLD( C_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_DTS_LT ); +REG64_FLD( C_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SHIFT_VOLT_LT ); +REG64_FLD( C_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT ); +REG64_FLD( C_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_READ_STATE_LT_LEN ); +REG64_FLD( C_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT ); +REG64_FLD( C_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WRITE_STATE_LT_LEN ); +REG64_FLD( C_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SAMPLE_DTS_LT ); +REG64_FLD( C_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_MEASURE_VOLT_LT ); +REG64_FLD( C_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_READ_CPM_LT ); +REG64_FLD( C_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WRITE_CPM_LT ); +REG64_FLD( C_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); REG64_FLD( EQ_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); @@ -6565,6 +9017,8 @@ REG64_FLD( EX_L2_FIR_ERR_INJ_TO_VSU , 3 , SH_UN SH_FLD_TO_VSU ); REG64_FLD( EX_L2_FIR_ERR_INJ_TO_PC , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TO_PC ); +REG64_FLD( EX_L2_FIR_ERR_INJ_RESERVED , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_RESERVED ); REG64_FLD( EX_L2_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ERROR_PULSE_OR_LEVEL ); REG64_FLD( EX_L2_FIR_ERR_INJ_CLEAR_STICKY_LEVEL , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , @@ -6606,6 +9060,8 @@ REG64_FLD( C_FIR_ERR_INJ_TO_VSU , 3 , SH_UN SH_FLD_TO_VSU ); REG64_FLD( C_FIR_ERR_INJ_TO_PC , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TO_PC ); +REG64_FLD( C_FIR_ERR_INJ_RESERVED , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_RESERVED ); REG64_FLD( C_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_PULSE_OR_LEVEL ); REG64_FLD( C_FIR_ERR_INJ_CLEAR_STICKY_LEVEL , 7 , SH_UNT_C , SH_ACS_SCOM_RW , @@ -6703,6 +9159,77 @@ REG64_FLD( EX_L2_FIR_MASK_REG_L2 , 0 , SH_UN REG64_FLD( EX_L2_FIR_MASK_REG_L2_LEN , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_L2_LEN ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR_MASK , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_FIR_SPARE1_MASK , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_FIR_SPARE1_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_FIR_SPARE2_MASK , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_FIR_SPARE2_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_DRAM_POS_WORDLINE_FAIL_MASK , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_DRAM_POS_WORDLINE_FAIL_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ_MASK , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_RD_UE_DET_MASK , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_RD_UE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_RD_SUE_DET_MASK , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_RD_SUE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_CE_FROM_PB_MASK , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_UE_FROM_PB_MASK , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_SUE_FROM_PB_MASK , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_CE_FROM_L2_MASK , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_UE_FROM_L2_MASK , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC_MASK , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_DIR_RD_CE_DET_MASK , 13 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_DIR_RD_CE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_DIR_RD_UE_DET_MASK , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_DIR_RD_UE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_DIR_RD_PHANTOM_ERROR_MASK , 15 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_DIR_RD_PHANTOM_ERROR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_WR_ADDR_ERR_MASK , 16 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PB_MAST_WR_ADDR_ERR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_RD_ADDR_ERR_MASK , 17 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PB_MAST_RD_ADDR_ERR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_ADDR_HANG_DETECTED_MASK , 18 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_ADDR_HANG_DETECTED_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_LRU_INVAL_CNT_MASK , 19 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_LRU_INVAL_CNT_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PPE_RD_CE_DET_MASK , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PPE_RD_CE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PPE_RD_UE_DET_MASK , 21 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PPE_RD_UE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PPE_RD_SUE_DET_MASK , 22 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PPE_RD_SUE_DET_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_MACH_HANG_DETECTED_MASK , 23 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_MACH_HANG_DETECTED_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_HW_CONTROL_ERR_MASK , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_HW_CONTROL_ERR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_SNP_CACHE_INHIBIT_ERR_MASK , 25 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_SNP_CACHE_INHIBIT_ERR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_LINE_DEL_CE_DONE_MASK , 26 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_LINE_DEL_CE_DONE_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_DRAM_ERROR_MASK , 27 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_DRAM_ERROR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_LRU_ERROR_MASK , 28 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_LRU_ERROR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_ALL_MEMBERS_DELETED_ERROR_MASK , 29 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_REFRESH_TIMER_ERROR_MASK , 30 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_REFRESH_TIMER_ERROR_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_WR_ACK_DEAD_MASK , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PB_MAST_WR_ACK_DEAD_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_RD_ACK_DEAD_MASK , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_PB_MAST_RD_ACK_DEAD_MASK ); +REG64_FLD( EX_L3_FIR_MASK_REG_SCOM_ERR_MASK1 , 33 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_MASK1 ); +REG64_FLD( EX_L3_FIR_MASK_REG_SCOM_ERR_MASK2 , 34 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_MASK2 ); + REG64_FLD( EQ_FIR_REG_CONTROL_ERR , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CONTROL_ERR ); REG64_FLD( EQ_FIR_REG_TLBIE_CONTROL_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , @@ -6869,15 +9396,23 @@ REG64_FLD( EX_L2_FIR_REG_DARN_DATA_TIMEOUT , 28 , SH_UN SH_FLD_DARN_DATA_TIMEOUT ); REG64_FLD( EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV ); +REG64_FLD( EX_L2_FIR_REG_SPARE2TO1 , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE2TO1 ); +REG64_FLD( EX_L2_FIR_REG_SPARE2TO1_LEN , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE2TO1_LEN ); REG64_FLD( EX_L2_FIR_REG_CACHE_RD_CE_AND_UE , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_RD_CE_AND_UE ); +REG64_FLD( EX_L2_FIR_REG_SPARE1TO1 , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE1TO1 ); +REG64_FLD( EX_L2_FIR_REG_SPARE1TO1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE1TO1_LEN ); REG64_FLD( EX_L2_FIR_REG_SCOM_ERR1 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR1 ); REG64_FLD( EX_L2_FIR_REG_SCOM_ERR2 , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); -REG64_FLD( EX_L3_FIR_REG_L3_SPARE0 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , - SH_FLD_L3_SPARE0 ); +REG64_FLD( EX_L3_FIR_REG_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , + SH_FLD_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR ); REG64_FLD( EX_L3_FIR_REG_L3_SPARE1 , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_SPARE1 ); REG64_FLD( EX_L3_FIR_REG_L3_SPARE2 , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , @@ -7271,6 +9806,10 @@ REG64_FLD( EX_L2_HANG_CONTROL_ACTIVE_MASK , 29 , SH_UN SH_FLD_ACTIVE_MASK ); REG64_FLD( EX_L2_HANG_CONTROL_ACTIVE_MASK_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_MASK_LEN ); +REG64_FLD( EX_L2_HANG_CONTROL_TLBIE_STALL_LIMIT , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_TLBIE_STALL_LIMIT ); +REG64_FLD( EX_L2_HANG_CONTROL_TLBIE_STALL_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_TLBIE_STALL_LIMIT_LEN ); REG64_FLD( C_HANG_CONTROL_CORE_LIMIT , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CORE_LIMIT ); @@ -7296,6 +9835,10 @@ REG64_FLD( C_HANG_CONTROL_ACTIVE_MASK , 29 , SH_UN SH_FLD_ACTIVE_MASK ); REG64_FLD( C_HANG_CONTROL_ACTIVE_MASK_LEN , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_MASK_LEN ); +REG64_FLD( C_HANG_CONTROL_TLBIE_STALL_LIMIT , 34 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_TLBIE_STALL_LIMIT ); +REG64_FLD( C_HANG_CONTROL_TLBIE_STALL_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_TLBIE_STALL_LIMIT_LEN ); REG64_FLD( EQ_HANG_PULSE_0_REG_0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_0 ); @@ -7453,35 +9996,53 @@ REG64_FLD( EX_HEARTBEAT_REG_DEAD , 0 , SH_UN REG64_FLD( C_HEARTBEAT_REG_DEAD , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEAD ); -REG64_FLD( EX_L2_HID_ONE_PPC , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_ONE_PPC , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ONE_PPC ); -REG64_FLD( EX_L2_HID_EN_INSTRUC_TRACE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_EN_INSTRUC_TRACE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_EN_INSTRUC_TRACE ); -REG64_FLD( EX_L2_HID_FLUSH_IC , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_FLUSH_IC , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FLUSH_IC ); -REG64_FLD( EX_L2_HID_EN_ATTN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_EN_ATTN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_EN_ATTN ); -REG64_FLD( EX_L2_HID_HILE , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_HILE , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_HILE ); -REG64_FLD( EX_L2_HID_DIS_RECOVERY , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_DIS_RECOVERY , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DIS_RECOVERY ); -REG64_FLD( EX_L2_HID_MEGAMOUTH , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , +REG64_FLD( EX_L2_HID_MEGAMOUTH , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MEGAMOUTH ); +REG64_FLD( EX_L2_HID_PREFETCH_RESET , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PREFETCH_RESET ); +REG64_FLD( EX_L2_HID_LSU_SPARE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_LSU_SPARE ); -REG64_FLD( C_HID_ONE_PPC , 0 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_ONE_PPC , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ONE_PPC ); -REG64_FLD( C_HID_EN_INSTRUC_TRACE , 1 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_EN_INSTRUC_TRACE , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_EN_INSTRUC_TRACE ); -REG64_FLD( C_HID_FLUSH_IC , 2 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_FLUSH_IC , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FLUSH_IC ); -REG64_FLD( C_HID_EN_ATTN , 3 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_EN_ATTN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_EN_ATTN ); -REG64_FLD( C_HID_HILE , 4 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_HILE , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_HILE ); -REG64_FLD( C_HID_DIS_RECOVERY , 5 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_DIS_RECOVERY , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DIS_RECOVERY ); -REG64_FLD( C_HID_MEGAMOUTH , 6 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_HID_MEGAMOUTH , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MEGAMOUTH ); +REG64_FLD( C_HID_PREFETCH_RESET , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PREFETCH_RESET ); +REG64_FLD( C_HID_LSU_SPARE , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_LSU_SPARE ); + +REG64_FLD( EX_L2_HMEER_ENABLE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ENABLE ); +REG64_FLD( EX_L2_HMEER_ENABLE_LEN , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( C_HMEER_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ENABLE ); +REG64_FLD( C_HMEER_ENABLE_LEN , 24 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_LEN ); REG64_FLD( EQ_HOSTATTN_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN0 ); @@ -8023,6 +10584,468 @@ REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_TYPE , 6 , SH_UN REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_TYPE_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE_LEN ); +REG64_FLD( EX_L2_HV_STATE_VT0_MSR_HV , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT0_MSR_HV ); +REG64_FLD( EX_L2_HV_STATE_VT1_MSR_HV , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT1_MSR_HV ); +REG64_FLD( EX_L2_HV_STATE_VT2_MSR_HV , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT2_MSR_HV ); +REG64_FLD( EX_L2_HV_STATE_VT3_MSR_HV , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT3_MSR_HV ); +REG64_FLD( EX_L2_HV_STATE_VT0_MSR_PR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT0_MSR_PR ); +REG64_FLD( EX_L2_HV_STATE_VT1_MSR_PR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT1_MSR_PR ); +REG64_FLD( EX_L2_HV_STATE_VT2_MSR_PR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT2_MSR_PR ); +REG64_FLD( EX_L2_HV_STATE_VT3_MSR_PR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT3_MSR_PR ); + +REG64_FLD( C_HV_STATE_VT0_MSR_HV , 56 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT0_MSR_HV ); +REG64_FLD( C_HV_STATE_VT1_MSR_HV , 57 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT1_MSR_HV ); +REG64_FLD( C_HV_STATE_VT2_MSR_HV , 58 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT2_MSR_HV ); +REG64_FLD( C_HV_STATE_VT3_MSR_HV , 59 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT3_MSR_HV ); +REG64_FLD( C_HV_STATE_VT0_MSR_PR , 60 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT0_MSR_PR ); +REG64_FLD( C_HV_STATE_VT1_MSR_PR , 61 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT1_MSR_PR ); +REG64_FLD( C_HV_STATE_VT2_MSR_PR , 62 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT2_MSR_PR ); +REG64_FLD( C_HV_STATE_VT3_MSR_PR , 63 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT3_MSR_PR ); + +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_UNUSED , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_UNUSED_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_UNUSED_LEN ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_IFAR_PARITY_HOLD_OUT_2 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_IFAR_PARITY_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_MULTI_THREAD_HOLD_OUT_2 , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_MULTI_THREAD_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFSE_SPR_PARITY_HOLD_OUT_2 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFSE_SPR_PARITY_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_EADIR_ILLEGAL_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_EADIR_ILLEGAL_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_ERAT_PTY_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_ERAT_PTY_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT ); + +REG64_FLD( C_IFU_HOLD_OUT_0_UNUSED , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); +REG64_FLD( C_IFU_HOLD_OUT_0_UNUSED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_UNUSED_LEN ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_IFAR_PARITY_HOLD_OUT_2 , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_IFAR_PARITY_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_MULTI_THREAD_HOLD_OUT_2 , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_MULTI_THREAD_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFSE_SPR_PARITY_HOLD_OUT_2 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFSE_SPR_PARITY_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_EADIR_ILLEGAL_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_EADIR_ILLEGAL_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_ERAT_PTY_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_ERAT_PTY_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT ); + +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_ICACHE_PE_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_ICACHE_PE_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IDIR_EA_PTY_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IDIR_EA_PTY_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IDIR_PTY_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IDIR_PTY_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IERAT_WRT_EA_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IERAT_WRT_EA_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK1_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IFAR_CHECK1_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK2_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IFAR_CHECK2_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IFFIW_IDIR_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IFFIW_IDIR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2 , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFLC_WRITE_COLL_HOLD_OUT_2 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFLC_WRITE_COLL_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 ); + +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_ICACHE_PE_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_ICACHE_PE_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IDIR_EA_PTY_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IDIR_EA_PTY_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IDIR_PTY_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IDIR_PTY_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IERAT_WRT_EA_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IERAT_WRT_EA_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK1_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IFAR_CHECK1_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK2_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IFAR_CHECK2_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IFFIW_IDIR_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFEC_IFFIW_IDIR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2 , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFFLC_WRITE_COLL_HOLD_OUT_2 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFLC_WRITE_COLL_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_1_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 ); + +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFCP_CIABR_PERR_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFCP_CIABR_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_UNUSED_1 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_UNUSED_1 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBC_BREX_PRED_CHECKER_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_PRED_CHECKER_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT ); + +REG64_FLD( C_IFU_HOLD_OUT_2_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFFCP_CIABR_PERR_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFCP_CIABR_PERR_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_UNUSED_1 , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_UNUSED_1 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBC_BREX_PRED_CHECKER_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_PRED_CHECKER_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 ); +REG64_FLD( C_IFU_HOLD_OUT_2_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT ); + +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_NIA_P_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_NIA_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_TAIL_P_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_TAIL_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_UNUSED_2 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_UNUSED_2 ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFRC_REFETCH_EAT_P_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFRC_REFETCH_EAT_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFRC_REFETCH_SPR_P_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IFFRC_REFETCH_SPR_P_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_TCC_TC_FIR_SCOM_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_TCC_TC_FIR_SCOM_HOLD_OUT ); +REG64_FLD( EX_L2_IFU_HOLD_OUT_3_UNUSED , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); + +REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_NIA_P_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_NIA_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_TAIL_P_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_TAIL_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_UNUSED_2 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_UNUSED_2 ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFRC_REFETCH_EAT_P_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFRC_REFETCH_EAT_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_IFFRC_REFETCH_SPR_P_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IFFRC_REFETCH_SPR_P_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_TCC_TC_FIR_SCOM_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_TCC_TC_FIR_SCOM_HOLD_OUT ); +REG64_FLD( C_IFU_HOLD_OUT_3_UNUSED , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_UNUSED ); + +REG64_FLD( EX_IMA_EVENT_MASK_ECONL_0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECONL_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECRL_0 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECRL_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECH_0 , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECH_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECP_0 , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECP_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECS_0 , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECS_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECA_0 , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECA_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECTA0_0 , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECTA0_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECTA1_0 , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECTA1_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECUS0_0 , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECUS0_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECUS1_0 , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECUS1_0 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECONL_1 , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECONL_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECRL_1 , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECRL_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECH_1 , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECH_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECP_1 , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECP_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECS_1 , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECS_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECA_1 , 15 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECA_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECTA0_1 , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECTA0_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECTA1_1 , 17 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECTA1_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECUS0_1 , 18 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECUS0_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECUS1_1 , 19 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECUS1_1 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECONL_2 , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECONL_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECRL_2 , 21 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECRL_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECH_2 , 22 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECH_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECP_2 , 23 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECP_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECS_2 , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECS_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECA_2 , 25 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECA_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECTA0_2 , 26 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECTA0_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECTA1_2 , 27 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECTA1_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECUS0_2 , 28 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECUS0_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_ECUS1_2 , 29 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_ECUS1_2 ); +REG64_FLD( EX_IMA_EVENT_MASK_IC_TAP , 30 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_IC_TAP ); +REG64_FLD( EX_IMA_EVENT_MASK_IC_TAP_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_IC_TAP_LEN ); +REG64_FLD( EX_IMA_EVENT_MASK_DISABLE_WRAP , 33 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_WRAP ); +REG64_FLD( EX_IMA_EVENT_MASK_CME_POWSAV , 34 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CME_POWSAV ); + +REG64_FLD( C_IMA_EVENT_MASK_ECONL_0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECONL_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECRL_0 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECRL_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECH_0 , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECH_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECP_0 , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECP_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECS_0 , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECS_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECA_0 , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECA_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECTA0_0 , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECTA0_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECTA1_0 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECTA1_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECUS0_0 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECUS0_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECUS1_0 , 9 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECUS1_0 ); +REG64_FLD( C_IMA_EVENT_MASK_ECONL_1 , 10 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECONL_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECRL_1 , 11 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECRL_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECH_1 , 12 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECH_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECP_1 , 13 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECP_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECS_1 , 14 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECS_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECA_1 , 15 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECA_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECTA0_1 , 16 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECTA0_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECTA1_1 , 17 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECTA1_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECUS0_1 , 18 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECUS0_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECUS1_1 , 19 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECUS1_1 ); +REG64_FLD( C_IMA_EVENT_MASK_ECONL_2 , 20 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECONL_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECRL_2 , 21 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECRL_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECH_2 , 22 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECH_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECP_2 , 23 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECP_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECS_2 , 24 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECS_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECA_2 , 25 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECA_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECTA0_2 , 26 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECTA0_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECTA1_2 , 27 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECTA1_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECUS0_2 , 28 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECUS0_2 ); +REG64_FLD( C_IMA_EVENT_MASK_ECUS1_2 , 29 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ECUS1_2 ); +REG64_FLD( C_IMA_EVENT_MASK_IC_TAP , 30 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_IC_TAP ); +REG64_FLD( C_IMA_EVENT_MASK_IC_TAP_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_IC_TAP_LEN ); +REG64_FLD( C_IMA_EVENT_MASK_DISABLE_WRAP , 33 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_DISABLE_WRAP ); +REG64_FLD( C_IMA_EVENT_MASK_CME_POWSAV , 34 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CME_POWSAV ); + +REG64_FLD( EX_IMA_TRACE_SAMPSEL , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SAMPSEL ); +REG64_FLD( EX_IMA_TRACE_SAMPSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SAMPSEL_LEN ); +REG64_FLD( EX_IMA_TRACE_CPMC_LOAD , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CPMC_LOAD ); +REG64_FLD( EX_IMA_TRACE_CPMC_LOAD_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CPMC_LOAD_LEN ); +REG64_FLD( EX_IMA_TRACE_CPMC1SEL , 34 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CPMC1SEL ); +REG64_FLD( EX_IMA_TRACE_CPMC1SEL_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CPMC1SEL_LEN ); +REG64_FLD( EX_IMA_TRACE_CPMC2SEL , 41 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CPMC2SEL ); +REG64_FLD( EX_IMA_TRACE_CPMC2SEL_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_CPMC2SEL_LEN ); + +REG64_FLD( C_IMA_TRACE_SAMPSEL , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SAMPSEL ); +REG64_FLD( C_IMA_TRACE_SAMPSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SAMPSEL_LEN ); +REG64_FLD( C_IMA_TRACE_CPMC_LOAD , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CPMC_LOAD ); +REG64_FLD( C_IMA_TRACE_CPMC_LOAD_LEN , 32 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CPMC_LOAD_LEN ); +REG64_FLD( C_IMA_TRACE_CPMC1SEL , 34 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CPMC1SEL ); +REG64_FLD( C_IMA_TRACE_CPMC1SEL_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CPMC1SEL_LEN ); +REG64_FLD( C_IMA_TRACE_CPMC2SEL , 41 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CPMC2SEL ); +REG64_FLD( C_IMA_TRACE_CPMC2SEL_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_CPMC2SEL_LEN ); + REG64_FLD( EQ_INJECT_REG_THERM_TRIP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_TRIP ); REG64_FLD( EQ_INJECT_REG_THERM_TRIP_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , @@ -8060,6 +11083,410 @@ REG64_FLD( EX_INJ_REG_STQ_ERR , 0 , SH_UN REG64_FLD( EX_INJ_REG_STQ_ERR_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STQ_ERR_LEN ); +REG64_FLD( EX_L2_INV_ERATE_INVALIDATE_ERAT , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_INVALIDATE_ERAT ); + +REG64_FLD( C_INV_ERATE_INVALIDATE_ERAT , 63 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_INVALIDATE_ERAT ); + +REG64_FLD( EX_L2_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ISU_HLD_OUT_REG6 ); +REG64_FLD( EX_L2_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6_LEN , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ISU_HLD_OUT_REG6_LEN ); + +REG64_FLD( C_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ISU_HLD_OUT_REG6 ); +REG64_FLD( C_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6_LEN , 18 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ISU_HLD_OUT_REG6_LEN ); + +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCR_ERR_INJ , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCR_ERR_INJ ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T0_HEAD_TAIL_XSTOP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T0_HEAD_TAIL_XSTOP ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T1_HEAD_TAIL_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T1_HEAD_TAIL_XSTOP ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T2_HEAD_TAIL_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T2_HEAD_TAIL_XSTOP ); +REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T3_HEAD_TAIL_XSTOP , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T3_HEAD_TAIL_XSTOP ); + +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCR_ERR_INJ , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCR_ERR_INJ ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T0_HEAD_TAIL_XSTOP , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T0_HEAD_TAIL_XSTOP ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T1_HEAD_TAIL_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T1_HEAD_TAIL_XSTOP ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T2_HEAD_TAIL_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T2_HEAD_TAIL_XSTOP ); +REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T3_HEAD_TAIL_XSTOP , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T3_HEAD_TAIL_XSTOP ); + +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_ERR_INJ_RECOV , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_ERR_INJ_RECOV ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T0_COMP_RCOV , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCCC_T0_COMP_RCOV ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T1_COMP_RCOV , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCCC_T1_COMP_RCOV ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T2_COMP_RCOV , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCCC_T2_COMP_RCOV ); +REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T3_COMP_RCOV , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCCC_T3_COMP_RCOV ); + +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_ERR_INJ_RECOV , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ERR_INJ_RECOV ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T0_COMP_RCOV , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCCC_T0_COMP_RCOV ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T1_COMP_RCOV , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCCC_T1_COMP_RCOV ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T2_COMP_RCOV , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCCC_T2_COMP_RCOV ); +REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T3_COMP_RCOV , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCCC_T3_COMP_RCOV ); + +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_WAT_INJECT_INT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_WAT_INJECT_INT ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCA_RCOV , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCA_RCOV ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCU_RAM_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCU_RAM_XSTOP ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCU_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCU_XSTOP ); +REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_WAT_INJECT_INT_RECOV , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_WAT_INJECT_INT_RECOV ); + +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_WAT_INJECT_INT , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WAT_INJECT_INT ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCA_RCOV , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCA_RCOV ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCU_RAM_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCU_RAM_XSTOP ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCU_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCU_XSTOP ); +REG64_FLD( C_ISU_REG2_HOLD_OUT_WAT_INJECT_INT_RECOV , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WAT_INJECT_INT_RECOV ); + +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T0_FLUSH_XSTOP , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCV_T0_FLUSH_XSTOP ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T1_FLUSH_XSTOP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCV_T1_FLUSH_XSTOP ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T2_FLUSH_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCV_T2_FLUSH_XSTOP ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T3_FLUSH_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCV_T3_FLUSH_XSTOP ); +REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_1B , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S0_1B ); + +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T0_FLUSH_XSTOP , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCV_T0_FLUSH_XSTOP ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T1_FLUSH_XSTOP , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCV_T1_FLUSH_XSTOP ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T2_FLUSH_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCV_T2_FLUSH_XSTOP ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T3_FLUSH_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCV_T3_FLUSH_XSTOP ); +REG64_FLD( C_ISU_REG3_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_1B , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S0_1B ); + +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_1B , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S1_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_1B , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S2_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_1B , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S0_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_1B , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S1_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_1B , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S2_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_1B , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S0_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_1B , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S1_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_1B , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S2_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S0_1B , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S0_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S1_1B , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S1_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S2_1B , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S2_1B ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_2B_XSTOP , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S0_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_2B_XSTOP , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S1_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_2B_XSTOP , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S2_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_2B_XSTOP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S0_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_2B_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S1_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_2B_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S2_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_2B_XSTOP , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S0_2B_XSTOP ); + +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_1B , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S1_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_1B , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S2_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_1B , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S0_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_1B , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S1_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_1B , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S2_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_1B , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S0_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_1B , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S1_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_1B , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S2_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S0_1B , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S0_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S1_1B , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S1_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S2_1B , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S2_1B ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_2B_XSTOP , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S0_2B_XSTOP ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_2B_XSTOP , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S1_2B_XSTOP ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_2B_XSTOP , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_EVEN_S2_2B_XSTOP ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_2B_XSTOP , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S0_2B_XSTOP ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_2B_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S1_2B_XSTOP ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_2B_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS0_ODD_S2_2B_XSTOP ); +REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_2B_XSTOP , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S0_2B_XSTOP ); + +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_2B_XSTOP , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S1_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_2B_XSTOP , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S2_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S0_2B_XSTOP , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S0_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S1_2B_XSTOP , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S1_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S2_2B_XSTOP , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S2_2B_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCXC_ERR_RPT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCXC_ERR_RPT ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T0_CRITICAL_IS_XSTOP , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T0_CRITICAL_IS_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T1_CRITICAL_IS_XSTOP , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T1_CRITICAL_IS_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T2_CRITICAL_IS_XSTOP , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T2_CRITICAL_IS_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T3_CRITICAL_IS_XSTOP , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SDCC_T3_CRITICAL_IS_XSTOP ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_GND , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_GND ); +REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_GND_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_GND_LEN ); + +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_2B_XSTOP , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S1_2B_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_2B_XSTOP , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_EVEN_S2_2B_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S0_2B_XSTOP , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S0_2B_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S1_2B_XSTOP , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S1_2B_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S2_2B_XSTOP , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDKSMRF_SS1_ODD_S2_2B_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCXC_ERR_RPT , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCXC_ERR_RPT ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T0_CRITICAL_IS_XSTOP , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T0_CRITICAL_IS_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T1_CRITICAL_IS_XSTOP , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T1_CRITICAL_IS_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T2_CRITICAL_IS_XSTOP , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T2_CRITICAL_IS_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T3_CRITICAL_IS_XSTOP , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SDCC_T3_CRITICAL_IS_XSTOP ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_GND , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_GND ); +REG64_FLD( C_ISU_REG5_HOLD_OUT_GND_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_GND_LEN ); + REG64_FLD( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , @@ -8090,8 +11517,28 @@ REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -8183,6 +11630,14 @@ REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -8214,8 +11669,28 @@ REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -8307,6 +11782,14 @@ REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -8338,8 +11821,28 @@ REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -8431,6 +11934,14 @@ REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -8462,8 +11973,28 @@ REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -8555,6 +12086,14 @@ REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL0_BAD_HPC ); @@ -9416,18 +12955,294 @@ REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG , 20 , SH_UN REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_COLUMN_MD_CFG_LEN ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FFN_AND_NOT_UC_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FFN_AND_NOT_UC_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_INVALID_FLUSH_CASE_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_FLSH_INVALID_FLUSH_CASE_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLRQE_CI_CDF_STUCK_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLRQE_CI_CDF_STUCK_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLRQE_OVERFLOW_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLRQE_OVERFLOW_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLRQF_OVERFLOW_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLRQF_OVERFLOW_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLSAQ_OVERFLOW_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLSAQ_OVERFLOW_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_INV_RD_ERR_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSLMQE_INV_RD_ERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_SCOM_PARITY_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_SCOM_PARITY_HOLD_OUT ); + +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FFN_AND_NOT_UC_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FFN_AND_NOT_UC_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_INVALID_FLUSH_CASE_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_FLSH_INVALID_FLUSH_CASE_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLRQE_CI_CDF_STUCK_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLRQE_CI_CDF_STUCK_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLRQE_OVERFLOW_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLRQE_OVERFLOW_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLRQF_OVERFLOW_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLRQF_OVERFLOW_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLSAQ_OVERFLOW_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLSAQ_OVERFLOW_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLMQE_INV_RD_ERR_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSLMQE_INV_RD_ERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG0_SCOM_PARITY_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SCOM_PARITY_HOLD_OUT ); + +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , + SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LS_S2QR_PERR_P2_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS_S2QR_PERR_P2_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_SPR_PERR_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_SPR_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSAMRD_SPR_PERR_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSAMRD_SPR_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSAMRS_SPR_PERR_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSAMRS_SPR_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSINTR_SPR_PERR_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSINTR_SPR_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSXREG_SPR_PERR_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSXREG_SPR_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT ); + +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LS_S2QR_PERR_P2_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS_S2QR_PERR_P2_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_SPR_PERR_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_SPR_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSAMRD_SPR_PERR_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSAMRD_SPR_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSAMRS_SPR_PERR_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSAMRS_SPR_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSINTR_SPR_PERR_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSINTR_SPR_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSXREG_SPR_PERR_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSXREG_SPR_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG1_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT ); + +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS0_DCAC_FIN_PERR_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS0_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS1_DCAC_FIN_PERR_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS1_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS2_DCAC_FIN_PERR_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS2_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS3_DCAC_FIN_PERR_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS3_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_DYNAM_SET_DELETED_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_DYNAM_SET_DELETED_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_SLB_MULTIHIT_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS_SLB_MULTIHIT_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_SLB_P_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS_SLB_P_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_TLB_MULTIHIT_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS_TLB_MULTIHIT_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_TLB_P_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS_TLB_P_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM0_RP2_SETP_PERR_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_STPM0_RP2_SETP_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM1_RP2_SETP_PERR_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_STPM1_RP2_SETP_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM2_RP1_SETP_PERR_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_STPM2_RP1_SETP_PERR_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM3_RP1_SETP_PERR_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_STPM3_RP1_SETP_PERR_HOLD_OUT ); + +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS0_DCAC_FIN_PERR_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS0_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS1_DCAC_FIN_PERR_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS1_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS2_DCAC_FIN_PERR_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS2_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS3_DCAC_FIN_PERR_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS3_DCAC_FIN_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_DYNAM_SET_DELETED_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DYNAM_SET_DELETED_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_SLB_MULTIHIT_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS_SLB_MULTIHIT_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_SLB_P_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS_SLB_P_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_TLB_MULTIHIT_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS_TLB_MULTIHIT_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_TLB_P_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS_TLB_P_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM0_RP2_SETP_PERR_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_STPM0_RP2_SETP_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM1_RP2_SETP_PERR_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_STPM1_RP2_SETP_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM2_RP1_SETP_PERR_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_STPM2_RP1_SETP_PERR_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM3_RP1_SETP_PERR_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_STPM3_RP1_SETP_PERR_HOLD_OUT ); + +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG0_FIN_RF_PARITY_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_DMAG0_FIN_RF_PARITY_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG1_FIN_RF_PARITY_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_DMAG1_FIN_RF_PARITY_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG2_RP2_RF_PARITY_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_DMAG2_RP2_RF_PARITY_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG3_RP2_RF_PARITY_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_DMAG3_RP2_RF_PARITY_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSERTD_FIN_P_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSERTD_FIN_P_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSERTD_FIN_ERATMHE_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSERTD_FIN_ERATMHE_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSSRQ_RES_OVERFLOW_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_LSSRQ_RES_OVERFLOW_HOLD_OUT ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED0 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_RESERVED0 ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED1 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_RESERVED1 ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED2 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_RESERVED2 ); +REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED3 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_RESERVED3 ); + +REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG0_FIN_RF_PARITY_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DMAG0_FIN_RF_PARITY_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG1_FIN_RF_PARITY_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DMAG1_FIN_RF_PARITY_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG2_RP2_RF_PARITY_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DMAG2_RP2_RF_PARITY_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG3_RP2_RF_PARITY_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DMAG3_RP2_RF_PARITY_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LSERTD_FIN_P_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSERTD_FIN_P_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LSERTD_FIN_ERATMHE_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSERTD_FIN_ERATMHE_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_LSSRQ_RES_OVERFLOW_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LSSRQ_RES_OVERFLOW_HOLD_OUT ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED0 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RESERVED0 ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED1 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RESERVED1 ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED2 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RESERVED2 ); +REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED3 , 15 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RESERVED3 ); + REG64_FLD( EQ_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( EQ_MIB_XIICAC_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_CME_SCOM_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( EQ_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( EQ_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( EX_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -9435,12 +13250,24 @@ REG64_FLD( EX_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( EX_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( EX_MIB_XIICAC_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_CME_SCOM_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( EX_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( EX_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( EX_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( EX_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( EQ_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -9692,6 +13519,10 @@ REG64_FLD( EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL , 35 , SH_UN SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL ); REG64_FLD( EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN ); +REG64_FLD( EX_L2_MODE_REG0_CFG_SKIP_GRP_SCOPE_EN , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_CFG_SKIP_GRP_SCOPE_EN ); +REG64_FLD( EX_L2_MODE_REG0_MODE_REG0_SPARE , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG0_SPARE ); REG64_FLD( EX_L3_MODE_REG0_L3_DISABLED_CFG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DISABLED_CFG ); @@ -9751,6 +13582,10 @@ REG64_FLD( EX_L2_MODE_REG1_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS , 0 , SH_UN SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS ); REG64_FLD( EX_L2_MODE_REG1_CFG_ECCCK_UE_SUE_DET_DIS , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE0 , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE0 ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE0_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE0_LEN ); REG64_FLD( EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV ); REG64_FLD( EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , @@ -9759,14 +13594,26 @@ REG64_FLD( EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV , 8 , SH_UN SH_FLD_DATA_POLL_PULSE_DIV ); REG64_FLD( EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DATA_POLL_PULSE_DIV_LEN ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE1 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE1 ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE1_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE1_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM03_SMT_ROTATION_DIS , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM03_SMT_ROTATION_DIS ); REG64_FLD( EX_L2_MODE_REG1_PM47_SMT_ROTATION_DIS , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM47_SMT_ROTATION_DIS ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE2 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE2 ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE2_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE2_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM07_TID_ROTATE_PLSS_RATE ); REG64_FLD( EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE3 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE3 ); +REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE3_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_MODE_REG1_SPARE3_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_EN , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM03_L23_EVENT_TID_SEL_EN ); REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , @@ -10205,10 +14052,8 @@ REG64_FLD( EQ_NET_CTRL0_CPLT_RCTRL , 19 , SH_UN SH_FLD_CPLT_RCTRL ); REG64_FLD( EQ_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); -REG64_FLD( EQ_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE0 ); -REG64_FLD( EQ_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( EQ_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, + SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( EQ_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( EQ_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, @@ -10219,6 +14064,8 @@ REG64_FLD( EQ_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( EQ_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( EQ_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, + SH_FLD_PM_ACCESS ); REG64_FLD( EQ_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); @@ -10264,10 +14111,8 @@ REG64_FLD( EX_NET_CTRL0_CPLT_RCTRL , 19 , SH_UN SH_FLD_CPLT_RCTRL ); REG64_FLD( EX_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); -REG64_FLD( EX_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_EX , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE0 ); -REG64_FLD( EX_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_EX , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( EX_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_EX , SH_ACS_SCOM2_WOR, + SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( EX_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( EX_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_EX , SH_ACS_SCOM2_WOR, @@ -10278,6 +14123,8 @@ REG64_FLD( EX_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( EX_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( EX_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_EX , SH_ACS_SCOM2_WOR, + SH_FLD_PM_ACCESS ); REG64_FLD( EX_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); @@ -10323,10 +14170,8 @@ REG64_FLD( C_NET_CTRL0_CPLT_RCTRL , 19 , SH_UN SH_FLD_CPLT_RCTRL ); REG64_FLD( C_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); -REG64_FLD( C_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_C , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE0 ); -REG64_FLD( C_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_C , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE1 ); +REG64_FLD( C_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_C , SH_ACS_SCOM2_WOR, + SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( C_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( C_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_C , SH_ACS_SCOM2_WOR, @@ -10337,6 +14182,8 @@ REG64_FLD( C_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( C_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( C_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_C , SH_ACS_SCOM2_WOR, + SH_FLD_PM_ACCESS ); REG64_FLD( C_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); @@ -10378,6 +14225,10 @@ REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UN SH_FLD_CLK_PULSE_MODE ); REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); +REG64_FLD( EQ_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS ); +REG64_FLD( EQ_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( EX_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); @@ -10417,6 +14268,10 @@ REG64_FLD( EX_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UN SH_FLD_CLK_PULSE_MODE ); REG64_FLD( EX_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); +REG64_FLD( EX_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_EX , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS ); +REG64_FLD( EX_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( C_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); @@ -10456,16 +14311,20 @@ REG64_FLD( C_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UN SH_FLD_CLK_PULSE_MODE ); REG64_FLD( C_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); +REG64_FLD( C_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_C , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS ); +REG64_FLD( C_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_WOR, + SH_FLD_PCB_ACCESS_LEN ); -REG64_FLD( EX_L2_OCC_SCOMC_MODE , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , - SH_FLD_MODE ); -REG64_FLD( EX_L2_OCC_SCOMC_MODE_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , - SH_FLD_MODE_LEN ); +REG64_FLD( EX_L2_OCC_SCOMC_MODE_CX , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX ); +REG64_FLD( EX_L2_OCC_SCOMC_MODE_CX_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX_LEN ); -REG64_FLD( C_OCC_SCOMC_MODE , 54 , SH_UNT_C , SH_ACS_SCOM_RW , - SH_FLD_MODE ); -REG64_FLD( C_OCC_SCOMC_MODE_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , - SH_FLD_MODE_LEN ); +REG64_FLD( C_OCC_SCOMC_MODE_CX , 54 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX ); +REG64_FLD( C_OCC_SCOMC_MODE_CX_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX_LEN ); REG64_FLD( EQ_OPCG_ALIGN_INOP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INOP ); @@ -11218,8 +15077,8 @@ REG64_FLD( EQ_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UN SH_FLD_MISR_INIT_WAIT ); REG64_FLD( EQ_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); -REG64_FLD( EQ_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( EQ_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( EQ_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( EQ_OPCG_REG1_UNUSED2 , 50 , SH_UNT_EQ , SH_ACS_SCOM , @@ -11261,8 +15120,8 @@ REG64_FLD( EX_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UN SH_FLD_MISR_INIT_WAIT ); REG64_FLD( EX_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); -REG64_FLD( EX_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( EX_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( EX_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( EX_OPCG_REG1_UNUSED2 , 50 , SH_UNT_EX , SH_ACS_SCOM , @@ -11304,8 +15163,8 @@ REG64_FLD( C_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UN SH_FLD_MISR_INIT_WAIT ); REG64_FLD( C_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); -REG64_FLD( C_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( C_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( C_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( C_OPCG_REG1_UNUSED2 , 50 , SH_UNT_C , SH_ACS_SCOM , @@ -11466,8 +15325,16 @@ REG64_FLD( EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UN SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); +REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1 , 7 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_1 ); +REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_1_LEN ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); +REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2 , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_2 ); +REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_2_LEN ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , @@ -11487,8 +15354,16 @@ REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UN SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); +REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1 , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_1 ); +REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_1_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); +REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2 , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_2 ); +REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_L3_PHYP_PURGE_RESERVED_2_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , @@ -11498,6 +15373,119 @@ REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR , 17 , SH_UN REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR_LEN , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR_LEN ); +REG64_FLD( EQ_PLL_LOCK_REG_LOCK , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCK ); +REG64_FLD( EQ_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCK_LEN ); + +REG64_FLD( EX_PLL_LOCK_REG_LOCK , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LOCK ); +REG64_FLD( EX_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LOCK_LEN ); + +REG64_FLD( C_PLL_LOCK_REG_LOCK , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LOCK ); +REG64_FLD( C_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LOCK_LEN ); + +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT0_SPR_HOLD_OUT ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT0_SPR_HOLD_OUT_LEN ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT1_SPR_HOLD_OUT ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT1_SPR_HOLD_OUT_LEN ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT2_SPR_HOLD_OUT ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT2_SPR_HOLD_OUT_LEN ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT3_SPR_HOLD_OUT ); +REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PMUT3_SPR_HOLD_OUT_LEN ); + +REG64_FLD( C_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT0_SPR_HOLD_OUT ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT0_SPR_HOLD_OUT_LEN ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT1_SPR_HOLD_OUT ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT1_SPR_HOLD_OUT_LEN ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT2_SPR_HOLD_OUT ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT2_SPR_HOLD_OUT_LEN ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT3_SPR_HOLD_OUT ); +REG64_FLD( C_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PMUT3_SPR_HOLD_OUT_LEN ); + +REG64_FLD( EX_L2_PMU_SCOMC_PMC1 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PMC1 ); +REG64_FLD( EX_L2_PMU_SCOMC_PMC2 , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PMC2 ); +REG64_FLD( EX_L2_PMU_SCOMC_PMC3 , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PMC3 ); +REG64_FLD( EX_L2_PMU_SCOMC_PMC4 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PMC4 ); +REG64_FLD( EX_L2_PMU_SCOMC_PMC5 , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PMC5 ); +REG64_FLD( EX_L2_PMU_SCOMC_PMC6 , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_PMC6 ); +REG64_FLD( EX_L2_PMU_SCOMC_MMCRC , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MMCRC ); +REG64_FLD( EX_L2_PMU_SCOMC_MMCR0 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MMCR0 ); +REG64_FLD( EX_L2_PMU_SCOMC_MMCR1 , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MMCR1 ); +REG64_FLD( EX_L2_PMU_SCOMC_MMCR2 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MMCR2 ); +REG64_FLD( EX_L2_PMU_SCOMC_MMCRA , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MMCRA ); +REG64_FLD( EX_L2_PMU_SCOMC_SIER , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_SIER ); +REG64_FLD( EX_L2_PMU_SCOMC_THREAD_ID , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_THREAD_ID ); +REG64_FLD( EX_L2_PMU_SCOMC_THREAD_ID_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_THREAD_ID_LEN ); + +REG64_FLD( C_PMU_SCOMC_PMC1 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PMC1 ); +REG64_FLD( C_PMU_SCOMC_PMC2 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PMC2 ); +REG64_FLD( C_PMU_SCOMC_PMC3 , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PMC3 ); +REG64_FLD( C_PMU_SCOMC_PMC4 , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PMC4 ); +REG64_FLD( C_PMU_SCOMC_PMC5 , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PMC5 ); +REG64_FLD( C_PMU_SCOMC_PMC6 , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PMC6 ); +REG64_FLD( C_PMU_SCOMC_MMCRC , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MMCRC ); +REG64_FLD( C_PMU_SCOMC_MMCR0 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MMCR0 ); +REG64_FLD( C_PMU_SCOMC_MMCR1 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MMCR1 ); +REG64_FLD( C_PMU_SCOMC_MMCR2 , 9 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MMCR2 ); +REG64_FLD( C_PMU_SCOMC_MMCRA , 10 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MMCRA ); +REG64_FLD( C_PMU_SCOMC_SIER , 11 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SIER ); +REG64_FLD( C_PMU_SCOMC_THREAD_ID , 12 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_THREAD_ID ); +REG64_FLD( C_PMU_SCOMC_THREAD_ID_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_THREAD_ID_LEN ); + +REG64_FLD( EX_L2_PMU_SCOMC_EN_ENABLE_INDIRECT_PMU_SCOM , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_INDIRECT_PMU_SCOM ); + +REG64_FLD( C_PMU_SCOMC_EN_ENABLE_INDIRECT_PMU_SCOM , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_INDIRECT_PMU_SCOM ); + REG64_FLD( EQ_PM_L2_RCMD_DIS_REG_L3_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CFG ); @@ -11524,45 +15512,205 @@ REG64_FLD( EX_L3_PM_PURGE_REG_L3_BUSY_ERR , 1 , SH_UN REG64_FLD( EX_L3_PM_PURGE_REG_L3_ABORT , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_ABORT ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( EQ_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( EQ_PPE_XIDBGPRO_IAR , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( EQ_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( EX_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( EX_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( EX_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( EX_PPE_XIDBGPRO_IAR , 32 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( EX_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( EQ_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( EX_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( EX_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM , @@ -11659,6 +15807,156 @@ REG64_FLD( C_PPM_CGCR_RESERVED_1_2_LEN , 2 , SH_UN REG64_FLD( C_PPM_CGCR_CLKGLM_SEL , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_SEL ); +REG64_FLD( EQ_PPM_GPMMR_SPECIAL_WKUP_DONE , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EQ_PPM_GPMMR_SPECIAL_WKUP_ACTIVE , 1 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_ACTIVE ); +REG64_FLD( EQ_PPM_GPMMR_REGULAR_WKUP_ACTIVE , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_ACTIVE ); +REG64_FLD( EQ_PPM_GPMMR_SPECIAL_WKUP_REQUESTED , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_REQUESTED ); +REG64_FLD( EQ_PPM_GPMMR_REGULAR_WKUP_REQUESTED , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_REQUESTED ); +REG64_FLD( EQ_PPM_GPMMR_REGULAR_WKUP_PRESENT , 5 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_PRESENT ); +REG64_FLD( EQ_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS , 6 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_BLOCK_REG_WKUP_EVENTS ); +REG64_FLD( EQ_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS , 7 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_BLOCK_ALL_WKUP_EVENTS ); +REG64_FLD( EQ_PPM_GPMMR_WKUP_OVERRIDE_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_WKUP_OVERRIDE_EN ); +REG64_FLD( EQ_PPM_GPMMR_SPC_WKUP_OVERRIDE , 9 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_SPC_WKUP_OVERRIDE ); +REG64_FLD( EQ_PPM_GPMMR_REG_WKUP_OVERRIDE , 10 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_REG_WKUP_OVERRIDE ); +REG64_FLD( EQ_PPM_GPMMR_CHIPLET_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_CHIPLET_ENABLE ); +REG64_FLD( EQ_PPM_GPMMR_RESERVED_12_14 , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_RESERVED_12_14 ); +REG64_FLD( EQ_PPM_GPMMR_RESERVED_12_14_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_RESERVED_12_14_LEN ); +REG64_FLD( EQ_PPM_GPMMR_RESET_STATE_INDICATOR , 15 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_RESET_STATE_INDICATOR ); + +REG64_FLD( EX_PPM_GPMMR_SPECIAL_WKUP_DONE , 0 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EX_PPM_GPMMR_SPECIAL_WKUP_ACTIVE , 1 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_ACTIVE ); +REG64_FLD( EX_PPM_GPMMR_REGULAR_WKUP_ACTIVE , 2 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_ACTIVE ); +REG64_FLD( EX_PPM_GPMMR_SPECIAL_WKUP_REQUESTED , 3 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_REQUESTED ); +REG64_FLD( EX_PPM_GPMMR_REGULAR_WKUP_REQUESTED , 4 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_REQUESTED ); +REG64_FLD( EX_PPM_GPMMR_REGULAR_WKUP_PRESENT , 5 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_PRESENT ); +REG64_FLD( EX_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS , 6 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_BLOCK_REG_WKUP_EVENTS ); +REG64_FLD( EX_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS , 7 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_BLOCK_ALL_WKUP_EVENTS ); +REG64_FLD( EX_PPM_GPMMR_WKUP_OVERRIDE_EN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_WKUP_OVERRIDE_EN ); +REG64_FLD( EX_PPM_GPMMR_SPC_WKUP_OVERRIDE , 9 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_SPC_WKUP_OVERRIDE ); +REG64_FLD( EX_PPM_GPMMR_REG_WKUP_OVERRIDE , 10 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_REG_WKUP_OVERRIDE ); +REG64_FLD( EX_PPM_GPMMR_CHIPLET_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_CHIPLET_ENABLE ); +REG64_FLD( EX_PPM_GPMMR_RESERVED_12_14 , 12 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_RESERVED_12_14 ); +REG64_FLD( EX_PPM_GPMMR_RESERVED_12_14_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_RESERVED_12_14_LEN ); +REG64_FLD( EX_PPM_GPMMR_RESET_STATE_INDICATOR , 15 , SH_UNT_EX , SH_ACS_SCOM2 , + SH_FLD_RESET_STATE_INDICATOR ); + +REG64_FLD( C_PPM_GPMMR_SPECIAL_WKUP_DONE , 0 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( C_PPM_GPMMR_SPECIAL_WKUP_ACTIVE , 1 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_ACTIVE ); +REG64_FLD( C_PPM_GPMMR_REGULAR_WKUP_ACTIVE , 2 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_ACTIVE ); +REG64_FLD( C_PPM_GPMMR_SPECIAL_WKUP_REQUESTED , 3 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_SPECIAL_WKUP_REQUESTED ); +REG64_FLD( C_PPM_GPMMR_REGULAR_WKUP_REQUESTED , 4 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_REQUESTED ); +REG64_FLD( C_PPM_GPMMR_REGULAR_WKUP_PRESENT , 5 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_REGULAR_WKUP_PRESENT ); +REG64_FLD( C_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS , 6 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_BLOCK_REG_WKUP_EVENTS ); +REG64_FLD( C_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS , 7 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_BLOCK_ALL_WKUP_EVENTS ); +REG64_FLD( C_PPM_GPMMR_WKUP_OVERRIDE_EN , 8 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_WKUP_OVERRIDE_EN ); +REG64_FLD( C_PPM_GPMMR_SPC_WKUP_OVERRIDE , 9 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_SPC_WKUP_OVERRIDE ); +REG64_FLD( C_PPM_GPMMR_REG_WKUP_OVERRIDE , 10 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_REG_WKUP_OVERRIDE ); +REG64_FLD( C_PPM_GPMMR_CHIPLET_ENABLE , 11 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_CHIPLET_ENABLE ); +REG64_FLD( C_PPM_GPMMR_RESERVED_12_14 , 12 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_RESERVED_12_14 ); +REG64_FLD( C_PPM_GPMMR_RESERVED_12_14_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_RESERVED_12_14_LEN ); +REG64_FLD( C_PPM_GPMMR_RESET_STATE_INDICATOR , 15 , SH_UNT_C , SH_ACS_SCOM2 , + SH_FLD_RESET_STATE_INDICATOR ); + +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_IVID , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_IVID ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_IVID_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_IVID_LEN ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PROTECT_ACTIVE ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_PFET_STRENGTH , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PFET_STRENGTH ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PFET_STRENGTH_LEN ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_VID_VALID , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_VID_VALID ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_BYPASS_B , 25 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_BYPASS_B ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_POWERON , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_POWERON ); +REG64_FLD( EQ_PPM_IVRMAVR_IVRM_VREG_SLOW_DC , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_IVRM_VREG_SLOW_DC ); + +REG64_FLD( EX_PPM_IVRMAVR_IVRM_IVID , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_IVID ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_IVID_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_IVID_LEN ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PROTECT_ACTIVE ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_PFET_STRENGTH , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PFET_STRENGTH ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PFET_STRENGTH_LEN ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_VID_VALID , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_VID_VALID ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_BYPASS_B , 25 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_BYPASS_B ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_POWERON , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_POWERON ); +REG64_FLD( EX_PPM_IVRMAVR_IVRM_VREG_SLOW_DC , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_IVRM_VREG_SLOW_DC ); + +REG64_FLD( C_PPM_IVRMAVR_IVRM_IVID , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_IVID ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_IVID_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_IVID_LEN ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PROTECT_ACTIVE ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_PFET_STRENGTH , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PFET_STRENGTH ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN , 5 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_PFET_STRENGTH_LEN ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_VID_VALID , 24 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_VID_VALID ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_BYPASS_B , 25 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_BYPASS_B ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_POWERON , 26 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_POWERON ); +REG64_FLD( C_PPM_IVRMAVR_IVRM_VREG_SLOW_DC , 27 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IVRM_VREG_SLOW_DC ); + REG64_FLD( EQ_PPM_IVRMCR_IVRM_VID_VALID , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VID_VALID ); REG64_FLD( EQ_PPM_IVRMCR_IVRM_BYPASS_B , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , @@ -11995,6 +16293,117 @@ REG64_FLD( C_PPM_PFOFF_VCS_VOFF_SEL , 4 , SH_UN REG64_FLD( C_PPM_PFOFF_VCS_VOFF_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL_LEN ); +REG64_FLD( EQ_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VDD_PFETS_ENABLED_SENSE ); +REG64_FLD( EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VDD_PFETS_DISABLED_SENSE ); +REG64_FLD( EQ_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VCS_PFETS_ENABLED_SENSE ); +REG64_FLD( EQ_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VCS_PFETS_DISABLED_SENSE ); +REG64_FLD( EQ_PPM_PFSNS_RESERVED_4_15 , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_4_15 ); +REG64_FLD( EQ_PPM_PFSNS_RESERVED_4_15_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_4_15_LEN ); +REG64_FLD( EQ_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL ); +REG64_FLD( EQ_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN ); +REG64_FLD( EQ_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL ); +REG64_FLD( EQ_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN ); +REG64_FLD( EQ_PPM_PFSNS_VDD_PG_STATE , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_STATE ); +REG64_FLD( EQ_PPM_PFSNS_VDD_PG_STATE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_STATE_LEN ); +REG64_FLD( EQ_PPM_PFSNS_VDD_PG_SEL , 46 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_SEL ); +REG64_FLD( EQ_PPM_PFSNS_VDD_PG_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_SEL_LEN ); +REG64_FLD( EQ_PPM_PFSNS_VCS_PG_STATE , 50 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_STATE ); +REG64_FLD( EQ_PPM_PFSNS_VCS_PG_STATE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_STATE_LEN ); +REG64_FLD( EQ_PPM_PFSNS_VCS_PG_SEL , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_SEL ); +REG64_FLD( EQ_PPM_PFSNS_VCS_PG_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_SEL_LEN ); + +REG64_FLD( EX_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VDD_PFETS_ENABLED_SENSE ); +REG64_FLD( EX_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VDD_PFETS_DISABLED_SENSE ); +REG64_FLD( EX_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VCS_PFETS_ENABLED_SENSE ); +REG64_FLD( EX_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VCS_PFETS_DISABLED_SENSE ); +REG64_FLD( EX_PPM_PFSNS_RESERVED_4_15 , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_4_15 ); +REG64_FLD( EX_PPM_PFSNS_RESERVED_4_15_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_4_15_LEN ); +REG64_FLD( EX_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL ); +REG64_FLD( EX_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN ); +REG64_FLD( EX_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL ); +REG64_FLD( EX_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN ); +REG64_FLD( EX_PPM_PFSNS_VDD_PG_STATE , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_STATE ); +REG64_FLD( EX_PPM_PFSNS_VDD_PG_STATE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_STATE_LEN ); +REG64_FLD( EX_PPM_PFSNS_VDD_PG_SEL , 46 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_SEL ); +REG64_FLD( EX_PPM_PFSNS_VDD_PG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_SEL_LEN ); +REG64_FLD( EX_PPM_PFSNS_VCS_PG_STATE , 50 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_STATE ); +REG64_FLD( EX_PPM_PFSNS_VCS_PG_STATE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_STATE_LEN ); +REG64_FLD( EX_PPM_PFSNS_VCS_PG_SEL , 54 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_SEL ); +REG64_FLD( EX_PPM_PFSNS_VCS_PG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_SEL_LEN ); + +REG64_FLD( C_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VDD_PFETS_ENABLED_SENSE ); +REG64_FLD( C_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VDD_PFETS_DISABLED_SENSE ); +REG64_FLD( C_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VCS_PFETS_ENABLED_SENSE ); +REG64_FLD( C_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE , 3 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VCS_PFETS_DISABLED_SENSE ); +REG64_FLD( C_PPM_PFSNS_RESERVED_4_15 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_4_15 ); +REG64_FLD( C_PPM_PFSNS_RESERVED_4_15_LEN , 12 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_4_15_LEN ); +REG64_FLD( C_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL , 16 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL ); +REG64_FLD( C_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN ); +REG64_FLD( C_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL , 24 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL ); +REG64_FLD( C_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN ); +REG64_FLD( C_PPM_PFSNS_VDD_PG_STATE , 42 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_STATE ); +REG64_FLD( C_PPM_PFSNS_VDD_PG_STATE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_STATE_LEN ); +REG64_FLD( C_PPM_PFSNS_VDD_PG_SEL , 46 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_SEL ); +REG64_FLD( C_PPM_PFSNS_VDD_PG_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VDD_PG_SEL_LEN ); +REG64_FLD( C_PPM_PFSNS_VCS_PG_STATE , 50 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_STATE ); +REG64_FLD( C_PPM_PFSNS_VCS_PG_STATE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_STATE_LEN ); +REG64_FLD( C_PPM_PFSNS_VCS_PG_SEL , 54 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_SEL ); +REG64_FLD( C_PPM_PFSNS_VCS_PG_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VCS_PG_SEL_LEN ); + REG64_FLD( EQ_PPM_PIG_REQ_INTR_TYPE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE ); REG64_FLD( EQ_PPM_PIG_REQ_INTR_TYPE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , @@ -12136,6 +16545,393 @@ REG64_FLD( EX_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP , 0 , SH_UN REG64_FLD( C_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_OTR_SPECIAL_WKUP ); +REG64_FLD( EQ_PPM_SSHFSP_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EQ_PPM_SSHFSP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EQ_PPM_SSHFSP_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EQ_PPM_SSHFSP_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EQ_PPM_SSHFSP_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHFSP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHFSP_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHFSP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP ); +REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN ); +REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP ); +REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN ); +REG64_FLD( EQ_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP , 20 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_FSP ); + +REG64_FLD( EX_PPM_SSHFSP_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EX_PPM_SSHFSP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EX_PPM_SSHFSP_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EX_PPM_SSHFSP_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EX_PPM_SSHFSP_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHFSP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHFSP_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHFSP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP ); +REG64_FLD( EX_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN ); +REG64_FLD( EX_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP ); +REG64_FLD( EX_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN ); +REG64_FLD( EX_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP , 20 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_FSP ); + +REG64_FLD( C_PPM_SSHFSP_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( C_PPM_SSHFSP_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( C_PPM_SSHFSP_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( C_PPM_SSHFSP_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( C_PPM_SSHFSP_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHFSP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHFSP_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHFSP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP ); +REG64_FLD( C_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN ); +REG64_FLD( C_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP ); +REG64_FLD( C_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN ); +REG64_FLD( C_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_FSP ); + +REG64_FLD( EQ_PPM_SSHHYP_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EQ_PPM_SSHHYP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EQ_PPM_SSHHYP_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EQ_PPM_SSHHYP_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EQ_PPM_SSHHYP_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHHYP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHHYP_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHHYP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP ); +REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN ); +REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP ); +REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN ); +REG64_FLD( EQ_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP , 20 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_HYP ); + +REG64_FLD( EX_PPM_SSHHYP_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EX_PPM_SSHHYP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EX_PPM_SSHHYP_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EX_PPM_SSHHYP_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EX_PPM_SSHHYP_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHHYP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHHYP_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHHYP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP ); +REG64_FLD( EX_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN ); +REG64_FLD( EX_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP ); +REG64_FLD( EX_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN ); +REG64_FLD( EX_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP , 20 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_HYP ); + +REG64_FLD( C_PPM_SSHHYP_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( C_PPM_SSHHYP_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( C_PPM_SSHHYP_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( C_PPM_SSHHYP_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( C_PPM_SSHHYP_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHHYP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHHYP_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHHYP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP ); +REG64_FLD( C_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN ); +REG64_FLD( C_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP ); +REG64_FLD( C_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN ); +REG64_FLD( C_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_HYP ); + +REG64_FLD( EQ_PPM_SSHOCC_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EQ_PPM_SSHOCC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EQ_PPM_SSHOCC_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EQ_PPM_SSHOCC_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EQ_PPM_SSHOCC_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHOCC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHOCC_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHOCC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC ); +REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN ); +REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC ); +REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN ); +REG64_FLD( EQ_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC , 20 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_OCC ); + +REG64_FLD( EX_PPM_SSHOCC_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EX_PPM_SSHOCC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EX_PPM_SSHOCC_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EX_PPM_SSHOCC_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EX_PPM_SSHOCC_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHOCC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHOCC_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHOCC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC ); +REG64_FLD( EX_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN ); +REG64_FLD( EX_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC ); +REG64_FLD( EX_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN ); +REG64_FLD( EX_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC , 20 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_OCC ); + +REG64_FLD( C_PPM_SSHOCC_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( C_PPM_SSHOCC_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( C_PPM_SSHOCC_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( C_PPM_SSHOCC_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( C_PPM_SSHOCC_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHOCC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHOCC_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHOCC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC ); +REG64_FLD( C_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN ); +REG64_FLD( C_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC ); +REG64_FLD( C_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN ); +REG64_FLD( C_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_OCC ); + +REG64_FLD( EQ_PPM_SSHOTR_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EQ_PPM_SSHOTR_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EQ_PPM_SSHOTR_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EQ_PPM_SSHOTR_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EQ_PPM_SSHOTR_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHOTR_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHOTR_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHOTR_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR ); +REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN ); +REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR , 16 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR ); +REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN ); +REG64_FLD( EQ_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR , 20 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_OTR ); + +REG64_FLD( EX_PPM_SSHOTR_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EX_PPM_SSHOTR_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EX_PPM_SSHOTR_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EX_PPM_SSHOTR_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EX_PPM_SSHOTR_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHOTR_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHOTR_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHOTR_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR ); +REG64_FLD( EX_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN ); +REG64_FLD( EX_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR , 16 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR ); +REG64_FLD( EX_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN ); +REG64_FLD( EX_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR , 20 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_OTR ); + +REG64_FLD( C_PPM_SSHOTR_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( C_PPM_SSHOTR_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( C_PPM_SSHOTR_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( C_PPM_SSHOTR_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( C_PPM_SSHOTR_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHOTR_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHOTR_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHOTR_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR ); +REG64_FLD( C_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN ); +REG64_FLD( C_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR ); +REG64_FLD( C_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN ); +REG64_FLD( C_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IVRM_ENABLED_HISTORY_OTR ); + +REG64_FLD( EQ_PPM_SSHSRC_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EQ_PPM_SSHSRC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EQ_PPM_SSHSRC_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EQ_PPM_SSHSRC_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EQ_PPM_SSHSRC_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHSRC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHSRC_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EQ_PPM_SSHSRC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EQ_PPM_SSHSRC_REQ_WRITE_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_REQ_WRITE_ENABLE ); +REG64_FLD( EQ_PPM_SSHSRC_ACT_WRITE_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ACT_WRITE_ENABLE ); + +REG64_FLD( EX_PPM_SSHSRC_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( EX_PPM_SSHSRC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( EX_PPM_SSHSRC_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( EX_PPM_SSHSRC_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( EX_PPM_SSHSRC_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHSRC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHSRC_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( EX_PPM_SSHSRC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( EX_PPM_SSHSRC_REQ_WRITE_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_REQ_WRITE_ENABLE ); +REG64_FLD( EX_PPM_SSHSRC_ACT_WRITE_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ACT_WRITE_ENABLE ); + +REG64_FLD( C_PPM_SSHSRC_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_GATED ); +REG64_FLD( C_PPM_SSHSRC_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPECIAL_WKUP_DONE ); +REG64_FLD( C_PPM_SSHSRC_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION ); +REG64_FLD( C_PPM_SSHSRC_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_STOP_TRANSITION_LEN ); +REG64_FLD( C_PPM_SSHSRC_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHSRC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHSRC_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL ); +REG64_FLD( C_PPM_SSHSRC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_STOP_LEVEL_LEN ); +REG64_FLD( C_PPM_SSHSRC_REQ_WRITE_ENABLE , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_REQ_WRITE_ENABLE ); +REG64_FLD( C_PPM_SSHSRC_ACT_WRITE_ENABLE , 13 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ACT_WRITE_ENABLE ); + REG64_FLD( EQ_PPM_VDMCR_VDM_POWERON , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_VDM_POWERON ); REG64_FLD( EQ_PPM_VDMCR_VDM_DISABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , @@ -12211,8 +17007,16 @@ REG64_FLD( EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UN SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); +REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1 , 7 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_1 ); +REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_1_LEN ); REG64_FLD( EQ_PRD_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); +REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2 , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_2 ); +REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_2_LEN ); REG64_FLD( EQ_PRD_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EQ_PRD_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , @@ -12232,8 +17036,16 @@ REG64_FLD( EX_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UN SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EX_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); +REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1 , 7 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_1 ); +REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_1_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); +REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2 , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_2 ); +REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_L3_PRD_PURGE_RESERVED_2_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EX_PRD_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , @@ -12258,6 +17070,21 @@ REG64_FLD( C_PRE_COUNTER_REG_COUNTER , 0 , SH_UN REG64_FLD( C_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COUNTER_LEN ); +REG64_FLD( EQ_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS ); +REG64_FLD( EQ_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS_LEN ); + +REG64_FLD( EX_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS ); +REG64_FLD( EX_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS_LEN ); + +REG64_FLD( C_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS ); +REG64_FLD( C_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PRIMARY_ADDRESS_LEN ); + REG64_FLD( EQ_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EQ_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , @@ -12887,43 +17714,47 @@ REG64_FLD( EQ_QPPM_ERR_PCB_INTERRUPT_PROTOCOL , 0 , SH_UN SH_FLD_PCB_INTERRUPT_PROTOCOL ); REG64_FLD( EQ_QPPM_ERR_SPECIAL_WKUP_PROTOCOL , 1 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_SPECIAL_WKUP_PROTOCOL ); -REG64_FLD( EQ_QPPM_ERR_PFET_SEQ_PROGRAM , 2 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL , 2 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, + SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL ); +REG64_FLD( EQ_QPPM_ERR_PFET_SEQ_PROGRAM , 3 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_PFET_SEQ_PROGRAM ); -REG64_FLD( EQ_QPPM_ERR_OCC_HEARTBEAT_LOSS , 3 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_OCC_HEARTBEAT_LOSS , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_OCC_HEARTBEAT_LOSS ); -REG64_FLD( EQ_QPPM_ERR_L2_EX0_CLK_SYNC , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_L2_EX0_CLK_SYNC , 5 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_L2_EX0_CLK_SYNC ); -REG64_FLD( EQ_QPPM_ERR_L2_EX1_CLK_SYNC , 5 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_L2_EX1_CLK_SYNC , 6 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_L2_EX1_CLK_SYNC ); -REG64_FLD( EQ_QPPM_ERR_EDRAM_SEQUENCE , 6 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_EDRAM_SEQUENCE , 7 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_EDRAM_SEQUENCE ); -REG64_FLD( EQ_QPPM_ERR_EDRAM_PGATE , 7 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_EDRAM_PGATE , 8 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_EDRAM_PGATE ); -REG64_FLD( EQ_QPPM_ERR_DPLL_INT , 8 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_DPLL_INT , 9 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_INT ); -REG64_FLD( EQ_QPPM_ERR_DPLL_DYN_FMIN , 9 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_DPLL_DYN_FMIN , 10 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_DYN_FMIN ); -REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_FULL , 10 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_FULL , 11 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_DCO_FULL ); -REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_EMPTY , 11 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_EMPTY , 12 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_DCO_EMPTY ); -REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA , 12 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA , 13 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_INVERTED_VDM_DATA ); REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_INVERTED_VDM_DATA_LEN ); -REG64_FLD( EQ_QPPM_ERR_CME0_IVRM_DROPOUT , 16 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_CME0_IVRM_DROPOUT , 17 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_CME0_IVRM_DROPOUT ); -REG64_FLD( EQ_QPPM_ERR_CME1_IVRM_DROPOUT , 17 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, +REG64_FLD( EQ_QPPM_ERR_CME1_IVRM_DROPOUT , 18 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_CME1_IVRM_DROPOUT ); -REG64_FLD( EQ_QPPM_ERR_SPARE_18_19 , 18 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, - SH_FLD_SPARE_18_19 ); -REG64_FLD( EQ_QPPM_ERR_SPARE_18_19_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, - SH_FLD_SPARE_18_19_LEN ); - -REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_19 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_19 ); -REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_19_LEN , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_19_LEN ); +REG64_FLD( EQ_QPPM_ERR_SPARE_19 , 19 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, + SH_FLD_SPARE_19 ); +REG64_FLD( EQ_QPPM_ERR_SPARE_20_23 , 20 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, + SH_FLD_SPARE_20_23 ); +REG64_FLD( EQ_QPPM_ERR_SPARE_20_23_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, + SH_FLD_SPARE_20_23_LEN ); + +REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_23 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_23 ); +REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_23_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_23_LEN ); REG64_FLD( EQ_QPPM_ERRSUM_PM_ERROR , 0 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_PM_ERROR ); @@ -13102,8 +17933,8 @@ REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_DATA_LEN , 4 , SH_UN SH_FLD_PULSE_DROOP_DATA_LEN ); REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_ENABLE , 24 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PULSE_DROOP_ENABLE ); -REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_PLS , 30 , SH_UNT_EQ , SH_ACS_SCOM2 , - SH_FLD_PB_PURGE_PLS ); +REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_REQ , 30 , SH_UNT_EQ , SH_ACS_SCOM2 , + SH_FLD_PB_PURGE_REQ ); REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_DONE_LVL , 31 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PB_PURGE_DONE_LVL ); REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL , 32 , SH_UNT_EQ , SH_ACS_SCOM2 , @@ -13196,6 +18027,164 @@ REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN_LEN , 8 , SH_UN REG64_FLD( EQ_QPPM_VOLT_CHAR_IVRM_ENABLED_HISTORY , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_ENABLED_HISTORY ); +REG64_FLD( EX_RAM_CTRL_RAM_VTID , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_RAM_VTID ); +REG64_FLD( EX_RAM_CTRL_RAM_VTID_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_RAM_VTID_LEN ); +REG64_FLD( EX_RAM_CTRL_PPC_PREDCD , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PPC_PREDCD ); +REG64_FLD( EX_RAM_CTRL_PPC_PREDCD_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PPC_PREDCD_LEN ); +REG64_FLD( EX_RAM_CTRL_SPARE , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SPARE ); +REG64_FLD( EX_RAM_CTRL_SPARE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SPARE_LEN ); +REG64_FLD( EX_RAM_CTRL_PPC_INSTR , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PPC_INSTR ); +REG64_FLD( EX_RAM_CTRL_PPC_INSTR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_PPC_INSTR_LEN ); + +REG64_FLD( C_RAM_CTRL_RAM_VTID , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_RAM_VTID ); +REG64_FLD( C_RAM_CTRL_RAM_VTID_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_RAM_VTID_LEN ); +REG64_FLD( C_RAM_CTRL_PPC_PREDCD , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PPC_PREDCD ); +REG64_FLD( C_RAM_CTRL_PPC_PREDCD_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PPC_PREDCD_LEN ); +REG64_FLD( C_RAM_CTRL_SPARE , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SPARE ); +REG64_FLD( C_RAM_CTRL_SPARE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SPARE_LEN ); +REG64_FLD( C_RAM_CTRL_PPC_INSTR , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PPC_INSTR ); +REG64_FLD( C_RAM_CTRL_PPC_INSTR_LEN , 32 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_PPC_INSTR_LEN ); + +REG64_FLD( EX_RAM_MODEREG_MODE_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_MODE_ENABLE ); + +REG64_FLD( C_RAM_MODEREG_MODE_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MODE_ENABLE ); + +REG64_FLD( EX_L2_RAM_STATUS_RAM_CONTROL_ACCESS_DURING_RECOV , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RAM_CONTROL_ACCESS_DURING_RECOV ); +REG64_FLD( EX_L2_RAM_STATUS_RAM_COMPLETION , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RAM_COMPLETION ); +REG64_FLD( EX_L2_RAM_STATUS_RAM_EXCEPTION , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RAM_EXCEPTION ); +REG64_FLD( EX_L2_RAM_STATUS_LSU_EMPTY , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LSU_EMPTY ); + +REG64_FLD( C_RAM_STATUS_RAM_CONTROL_ACCESS_DURING_RECOV , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RAM_CONTROL_ACCESS_DURING_RECOV ); +REG64_FLD( C_RAM_STATUS_RAM_COMPLETION , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RAM_COMPLETION ); +REG64_FLD( C_RAM_STATUS_RAM_EXCEPTION , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RAM_EXCEPTION ); +REG64_FLD( C_RAM_STATUS_LSU_EMPTY , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LSU_EMPTY ); + +REG64_FLD( EX_L2_RAS_MODEREG_MR_DIS_PMON_INTR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MR_DIS_PMON_INTR ); +REG64_FLD( EX_L2_RAS_MODEREG_MR_FENCE_INTERRUPTS , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MR_FENCE_INTERRUPTS ); +REG64_FLD( EX_L2_RAS_MODEREG_MR_BLOCK_HMI_IN_MAINT , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MR_BLOCK_HMI_IN_MAINT ); +REG64_FLD( EX_L2_RAS_MODEREG_MR_FENCE_INTR_ON_CHECKSTOP , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MR_FENCE_INTR_ON_CHECKSTOP ); + +REG64_FLD( C_RAS_MODEREG_MR_DIS_PMON_INTR , 56 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MR_DIS_PMON_INTR ); +REG64_FLD( C_RAS_MODEREG_MR_FENCE_INTERRUPTS , 57 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MR_FENCE_INTERRUPTS ); +REG64_FLD( C_RAS_MODEREG_MR_BLOCK_HMI_IN_MAINT , 62 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MR_BLOCK_HMI_IN_MAINT ); +REG64_FLD( C_RAS_MODEREG_MR_FENCE_INTR_ON_CHECKSTOP , 63 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MR_FENCE_INTR_ON_CHECKSTOP ); + +REG64_FLD( EX_L2_RAS_STATUS_T0_CORE_MAINT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T0_CORE_MAINT ); +REG64_FLD( EX_L2_RAS_STATUS_T0_THREAD_QUIESCED , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T0_THREAD_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T0_ICT_EMPTY , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T0_ICT_EMPTY ); +REG64_FLD( EX_L2_RAS_STATUS_T0_LSU_QUIESCED , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T0_LSU_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T0_STEP_SUCCESS , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T0_STEP_SUCCESS ); +REG64_FLD( EX_L2_RAS_STATUS_T1_CORE_MAINT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T1_CORE_MAINT ); +REG64_FLD( EX_L2_RAS_STATUS_T1_THREAD_QUIESCED , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T1_THREAD_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T1_ICT_EMPTY , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T1_ICT_EMPTY ); +REG64_FLD( EX_L2_RAS_STATUS_T1_LSU_QUIESCED , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T1_LSU_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T1_STEP_SUCCESS , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T1_STEP_SUCCESS ); +REG64_FLD( EX_L2_RAS_STATUS_T2_CORE_MAINT , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T2_CORE_MAINT ); +REG64_FLD( EX_L2_RAS_STATUS_T2_THREAD_QUIESCED , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T2_THREAD_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T2_ICT_EMPTY , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T2_ICT_EMPTY ); +REG64_FLD( EX_L2_RAS_STATUS_T2_LSU_QUIESCED , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T2_LSU_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T2_STEP_SUCCESS , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T2_STEP_SUCCESS ); +REG64_FLD( EX_L2_RAS_STATUS_T3_CORE_MAINT , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T3_CORE_MAINT ); +REG64_FLD( EX_L2_RAS_STATUS_T3_THREAD_QUIESCED , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T3_THREAD_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T3_ICT_EMPTY , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T3_ICT_EMPTY ); +REG64_FLD( EX_L2_RAS_STATUS_T3_LSU_QUIESCED , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T3_LSU_QUIESCED ); +REG64_FLD( EX_L2_RAS_STATUS_T3_STEP_SUCCESS , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_T3_STEP_SUCCESS ); + +REG64_FLD( C_RAS_STATUS_T0_CORE_MAINT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T0_CORE_MAINT ); +REG64_FLD( C_RAS_STATUS_T0_THREAD_QUIESCED , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T0_THREAD_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T0_ICT_EMPTY , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T0_ICT_EMPTY ); +REG64_FLD( C_RAS_STATUS_T0_LSU_QUIESCED , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T0_LSU_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T0_STEP_SUCCESS , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T0_STEP_SUCCESS ); +REG64_FLD( C_RAS_STATUS_T1_CORE_MAINT , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T1_CORE_MAINT ); +REG64_FLD( C_RAS_STATUS_T1_THREAD_QUIESCED , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T1_THREAD_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T1_ICT_EMPTY , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T1_ICT_EMPTY ); +REG64_FLD( C_RAS_STATUS_T1_LSU_QUIESCED , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T1_LSU_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T1_STEP_SUCCESS , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T1_STEP_SUCCESS ); +REG64_FLD( C_RAS_STATUS_T2_CORE_MAINT , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T2_CORE_MAINT ); +REG64_FLD( C_RAS_STATUS_T2_THREAD_QUIESCED , 17 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T2_THREAD_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T2_ICT_EMPTY , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T2_ICT_EMPTY ); +REG64_FLD( C_RAS_STATUS_T2_LSU_QUIESCED , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T2_LSU_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T2_STEP_SUCCESS , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T2_STEP_SUCCESS ); +REG64_FLD( C_RAS_STATUS_T3_CORE_MAINT , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T3_CORE_MAINT ); +REG64_FLD( C_RAS_STATUS_T3_THREAD_QUIESCED , 25 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T3_THREAD_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T3_ICT_EMPTY , 26 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T3_ICT_EMPTY ); +REG64_FLD( C_RAS_STATUS_T3_LSU_QUIESCED , 27 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T3_LSU_QUIESCED ); +REG64_FLD( C_RAS_STATUS_T3_STEP_SUCCESS , 28 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_T3_STEP_SUCCESS ); + REG64_FLD( EQ_RD_EPS_REG_TIER0_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER0_VALUE ); REG64_FLD( EQ_RD_EPS_REG_TIER0_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , @@ -13222,6 +18211,53 @@ REG64_FLD( EX_L2_RD_EPS_REG_TIER2_VALUE , 24 , SH_UN REG64_FLD( EX_L2_RD_EPS_REG_TIER2_VALUE_LEN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER2_VALUE_LEN ); +REG64_FLD( EX_L2_RECOV_FWD_PROG_CTRL_RESET_FWD_PROG , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RESET_FWD_PROG ); +REG64_FLD( EX_L2_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_FWD_PROG_THOLD ); +REG64_FLD( EX_L2_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_FWD_PROG_THOLD_LEN ); + +REG64_FLD( C_RECOV_FWD_PROG_CTRL_RESET_FWD_PROG , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESET_FWD_PROG ); +REG64_FLD( C_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FWD_PROG_THOLD ); +REG64_FLD( C_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_FWD_PROG_THOLD_LEN ); + +REG64_FLD( EQ_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_RECOV ); + +REG64_FLD( EX_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_RECOV ); + +REG64_FLD( C_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RECOV ); + +REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_LIMIT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_LIMIT ); +REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_LIMIT_LEN ); +REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_RESET , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_RESET ); +REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_RESET_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_RESET_LEN ); + +REG64_FLD( C_RECOV_THOLD_THRESHOLD_LIMIT , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_LIMIT ); +REG64_FLD( C_RECOV_THOLD_THRESHOLD_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_LIMIT_LEN ); +REG64_FLD( C_RECOV_THOLD_THRESHOLD_RESET , 8 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_RESET ); +REG64_FLD( C_RECOV_THOLD_THRESHOLD_RESET_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_THRESHOLD_RESET_LEN ); + +REG64_FLD( EX_L2_RESET_KEEPER_RESET_KEEPER , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RESET_KEEPER ); + +REG64_FLD( C_RESET_KEEPER_RESET_KEEPER , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RESET_KEEPER ); + REG64_FLD( EQ_RFIR_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EQ_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM , @@ -13271,22 +18307,16 @@ REG64_FLD( C_RFIR_IN5 , 3 , SH_UN REG64_FLD( C_RFIR_IN5_LEN , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5_LEN ); -REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_DISABLED ); REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_C , SH_ACS_SCOM , @@ -13445,15 +18475,35 @@ REG64_FLD( C_SCAN_REGION_TYPE_CMSK , 58 , SH_UN REG64_FLD( C_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INEX ); -REG64_FLD( EX_L2_SCOMC_MODE , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , - SH_FLD_MODE ); -REG64_FLD( EX_L2_SCOMC_MODE_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , - SH_FLD_MODE_LEN ); +REG64_FLD( EX_L2_SCOMC_MODE_CX , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX ); +REG64_FLD( EX_L2_SCOMC_MODE_CX_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX_LEN ); + +REG64_FLD( C_SCOMC_MODE_CX , 54 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX ); +REG64_FLD( C_SCOMC_MODE_CX_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_MODE_CX_LEN ); + +REG64_FLD( EX_L2_SHID0_TRIG2_TRACE_EN , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_TRIG2_TRACE_EN ); +REG64_FLD( EX_L2_SHID0_DIS_TRACE_SPR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , + SH_FLD_DIS_TRACE_SPR ); -REG64_FLD( C_SCOMC_MODE , 54 , SH_UNT_C , SH_ACS_SCOM_RW , - SH_FLD_MODE ); -REG64_FLD( C_SCOMC_MODE_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , - SH_FLD_MODE_LEN ); +REG64_FLD( C_SHID0_TRIG2_TRACE_EN , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_TRIG2_TRACE_EN ); +REG64_FLD( C_SHID0_DIS_TRACE_SPR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_DIS_TRACE_SPR ); + +REG64_FLD( EX_SIER_MASK_SIER_MASK_TBD , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SIER_MASK_TBD ); +REG64_FLD( EX_SIER_MASK_SIER_MASK_TBD_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SIER_MASK_TBD_LEN ); + +REG64_FLD( C_SIER_MASK_SIER_MASK_TBD , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SIER_MASK_TBD ); +REG64_FLD( C_SIER_MASK_SIER_MASK_TBD_LEN , 64 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SIER_MASK_TBD_LEN ); REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SKITTER0 ); @@ -13584,7 +18634,7 @@ REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UN SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); -REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , +REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_EX , SH_ACS_SCOM , @@ -13605,7 +18655,7 @@ REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UN SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); -REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , +REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_C , SH_ACS_SCOM , @@ -13626,7 +18676,7 @@ REG64_FLD( C_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UN SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); -REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , +REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( EQ_SPATTN_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM2_NC , @@ -13650,6 +18700,267 @@ REG64_FLD( EQ_SPATTN_IN8 , 8 , SH_UN REG64_FLD( EQ_SPATTN_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN9 ); +REG64_FLD( EX_SPATTN_LT0_SPR_INSTR_STOP , 0 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT0_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT0_ATTN_COMPLETE , 1 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT0_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 2 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT0_CORE_CODE_TO_SP , 3 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT0_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT1_SPR_INSTR_STOP , 4 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT1_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT1_ATTN_COMPLETE , 5 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT1_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 6 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT1_CORE_CODE_TO_SP , 7 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT1_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT2_SPR_INSTR_STOP , 8 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT2_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT2_ATTN_COMPLETE , 9 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT2_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 10 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT2_CORE_CODE_TO_SP , 11 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT2_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT3_SPR_INSTR_STOP , 12 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT3_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT3_ATTN_COMPLETE , 13 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT3_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 14 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT3_CORE_CODE_TO_SP , 15 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT3_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT4_SPR_INSTR_STOP , 16 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT4_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT4_ATTN_COMPLETE , 17 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT4_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 18 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT4_CORE_CODE_TO_SP , 19 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT4_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT5_SPR_INSTR_STOP , 20 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT5_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT5_ATTN_COMPLETE , 21 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT5_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 22 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT5_CORE_CODE_TO_SP , 23 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT5_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT6_SPR_INSTR_STOP , 24 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT6_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT6_ATTN_COMPLETE , 25 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT6_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 26 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT6_CORE_CODE_TO_SP , 27 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT6_CORE_CODE_TO_SP ); +REG64_FLD( EX_SPATTN_LT7_SPR_INSTR_STOP , 28 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT7_SPR_INSTR_STOP ); +REG64_FLD( EX_SPATTN_LT7_ATTN_COMPLETE , 29 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT7_ATTN_COMPLETE ); +REG64_FLD( EX_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 30 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_SPATTN_LT7_CORE_CODE_TO_SP , 31 , SH_UNT_EX , SH_ACS_SCOM2_NC , + SH_FLD_LT7_CORE_CODE_TO_SP ); + +REG64_FLD( EX_L2_SPATTN_LT0_SPR_INSTR_STOP , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT0_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT0_ATTN_COMPLETE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT0_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT0_CORE_CODE_TO_SP , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT0_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT1_SPR_INSTR_STOP , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT1_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT1_ATTN_COMPLETE , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT1_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT1_CORE_CODE_TO_SP , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT1_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT2_SPR_INSTR_STOP , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT2_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT2_ATTN_COMPLETE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT2_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT2_CORE_CODE_TO_SP , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT2_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT3_SPR_INSTR_STOP , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT3_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT3_ATTN_COMPLETE , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT3_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT3_CORE_CODE_TO_SP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT3_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT4_SPR_INSTR_STOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT4_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT4_ATTN_COMPLETE , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT4_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT4_CORE_CODE_TO_SP , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT4_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT5_SPR_INSTR_STOP , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT5_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT5_ATTN_COMPLETE , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT5_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT5_CORE_CODE_TO_SP , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT5_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT6_SPR_INSTR_STOP , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT6_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT6_ATTN_COMPLETE , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT6_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT6_CORE_CODE_TO_SP , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT6_CORE_CODE_TO_SP ); +REG64_FLD( EX_L2_SPATTN_LT7_SPR_INSTR_STOP , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT7_SPR_INSTR_STOP ); +REG64_FLD( EX_L2_SPATTN_LT7_ATTN_COMPLETE , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT7_ATTN_COMPLETE ); +REG64_FLD( EX_L2_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( EX_L2_SPATTN_LT7_CORE_CODE_TO_SP , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_LT7_CORE_CODE_TO_SP ); + +REG64_FLD( C_SPATTN_LT0_SPR_INSTR_STOP , 0 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT0_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT0_ATTN_COMPLETE , 1 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT0_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 2 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT0_CORE_CODE_TO_SP , 3 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT0_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT1_SPR_INSTR_STOP , 4 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT1_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT1_ATTN_COMPLETE , 5 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT1_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 6 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT1_CORE_CODE_TO_SP , 7 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT1_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT2_SPR_INSTR_STOP , 8 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT2_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT2_ATTN_COMPLETE , 9 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT2_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 10 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT2_CORE_CODE_TO_SP , 11 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT2_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT3_SPR_INSTR_STOP , 12 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT3_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT3_ATTN_COMPLETE , 13 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT3_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 14 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT3_CORE_CODE_TO_SP , 15 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT3_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT4_SPR_INSTR_STOP , 16 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT4_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT4_ATTN_COMPLETE , 17 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT4_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 18 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT4_CORE_CODE_TO_SP , 19 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT4_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT5_SPR_INSTR_STOP , 20 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT5_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT5_ATTN_COMPLETE , 21 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT5_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 22 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT5_CORE_CODE_TO_SP , 23 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT5_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT6_SPR_INSTR_STOP , 24 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT6_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT6_ATTN_COMPLETE , 25 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT6_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 26 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT6_CORE_CODE_TO_SP , 27 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT6_CORE_CODE_TO_SP ); +REG64_FLD( C_SPATTN_LT7_SPR_INSTR_STOP , 28 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT7_SPR_INSTR_STOP ); +REG64_FLD( C_SPATTN_LT7_ATTN_COMPLETE , 29 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT7_ATTN_COMPLETE ); +REG64_FLD( C_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 30 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); +REG64_FLD( C_SPATTN_LT7_CORE_CODE_TO_SP , 31 , SH_UNT_C , SH_ACS_SCOM2_NC , + SH_FLD_LT7_CORE_CODE_TO_SP ); + +REG64_FLD( EX_L2_SPATTN_MASK_LT0_SPATTN_MASK , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT0_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT0_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT0_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT1_SPATTN_MASK , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT1_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT1_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT1_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT2_SPATTN_MASK , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT2_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT2_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT2_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT3_SPATTN_MASK , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT3_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT3_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT3_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT4_SPATTN_MASK , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT4_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT4_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT4_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT5_SPATTN_MASK , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT5_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT5_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT5_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT6_SPATTN_MASK , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT6_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT6_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT6_SPATTN_MASK_LEN ); +REG64_FLD( EX_L2_SPATTN_MASK_LT7_SPATTN_MASK , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT7_SPATTN_MASK ); +REG64_FLD( EX_L2_SPATTN_MASK_LT7_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_LT7_SPATTN_MASK_LEN ); + +REG64_FLD( C_SPATTN_MASK_LT0_SPATTN_MASK , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT0_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT0_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT0_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT1_SPATTN_MASK , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT1_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT1_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT1_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT2_SPATTN_MASK , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT2_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT2_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT2_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT3_SPATTN_MASK , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT3_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT3_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT3_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT4_SPATTN_MASK , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT4_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT4_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT4_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT5_SPATTN_MASK , 20 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT5_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT5_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT5_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT6_SPATTN_MASK , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT6_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT6_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT6_SPATTN_MASK_LEN ); +REG64_FLD( C_SPATTN_MASK_LT7_SPATTN_MASK , 28 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT7_SPATTN_MASK ); +REG64_FLD( C_SPATTN_MASK_LT7_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LT7_SPATTN_MASK_LEN ); + REG64_FLD( EQ_SPA_MASK_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_SPA_MASK_IN_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM , @@ -13665,6 +18976,40 @@ REG64_FLD( C_SPA_MASK_IN , 0 , SH_UN REG64_FLD( C_SPA_MASK_IN_LEN , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_IMA_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_IMA_HOLD_OUT ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_PTID_RECONFIG_SM_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_PTID_RECONFIG_SM_HOLD_OUT ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VS_ERR_HOLD_OUT ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT_LEN , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VS_ERR_HOLD_OUT_LEN ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT0_LPCR_ONL_PAR_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT0_LPCR_ONL_PAR_HOLD_OUT ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT1_LPCR_ONL_PAR_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT1_LPCR_ONL_PAR_HOLD_OUT ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT2_LPCR_ONL_PAR_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT2_LPCR_ONL_PAR_HOLD_OUT ); +REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT3_LPCR_ONL_PAR_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , + SH_FLD_VT3_LPCR_ONL_PAR_HOLD_OUT ); + +REG64_FLD( C_SPR_CORE_HOLD_OUT_IMA_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_IMA_HOLD_OUT ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_PTID_RECONFIG_SM_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_PTID_RECONFIG_SM_HOLD_OUT ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VS_ERR_HOLD_OUT ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VS_ERR_HOLD_OUT_LEN ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_VT0_LPCR_ONL_PAR_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT0_LPCR_ONL_PAR_HOLD_OUT ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_VT1_LPCR_ONL_PAR_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT1_LPCR_ONL_PAR_HOLD_OUT ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_VT2_LPCR_ONL_PAR_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT2_LPCR_ONL_PAR_HOLD_OUT ); +REG64_FLD( C_SPR_CORE_HOLD_OUT_VT3_LPCR_ONL_PAR_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_VT3_LPCR_ONL_PAR_HOLD_OUT ); + REG64_FLD( EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_TFAC_ERR_INJ ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , @@ -13741,6 +19086,16 @@ REG64_FLD( C_SPURR_FREQ_SCALE_FACTOR , 1 , SH_UN REG64_FLD( C_SPURR_FREQ_SCALE_FACTOR_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FACTOR_LEN ); +REG64_FLD( EX_SRC_MASK_SRC_MASK_TBD , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SRC_MASK_TBD ); +REG64_FLD( EX_SRC_MASK_SRC_MASK_TBD_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SRC_MASK_TBD_LEN ); + +REG64_FLD( C_SRC_MASK_SRC_MASK_TBD , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SRC_MASK_TBD ); +REG64_FLD( C_SRC_MASK_SRC_MASK_TBD_LEN , 64 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SRC_MASK_TBD_LEN ); + REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SMASK_IN0 ); REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , @@ -13786,16 +19141,18 @@ REG64_FLD( EQ_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( EQ_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( EQ_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); +REG64_FLD( EQ_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( EQ_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( EQ_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); -REG64_FLD( EQ_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_UNUSED1119 ); -REG64_FLD( EQ_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_UNUSED1119_LEN ); +REG64_FLD( EQ_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_PULSE_OUT_DIS ); +REG64_FLD( EQ_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED1219 ); +REG64_FLD( EQ_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_UNUSED1219_LEN ); REG64_FLD( EX_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); @@ -13809,16 +19166,18 @@ REG64_FLD( EX_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( EX_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( EX_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); +REG64_FLD( EX_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( EX_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( EX_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); -REG64_FLD( EX_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_UNUSED1119 ); -REG64_FLD( EX_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_UNUSED1119_LEN ); +REG64_FLD( EX_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PULSE_OUT_DIS ); +REG64_FLD( EX_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED1219 ); +REG64_FLD( EX_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_UNUSED1219_LEN ); REG64_FLD( C_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); @@ -13832,16 +19191,138 @@ REG64_FLD( C_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( C_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( C_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); +REG64_FLD( C_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( C_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( C_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); -REG64_FLD( C_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_UNUSED1119 ); -REG64_FLD( C_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , - SH_FLD_UNUSED1119_LEN ); +REG64_FLD( C_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PULSE_OUT_DIS ); +REG64_FLD( C_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED1219 ); +REG64_FLD( C_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_UNUSED1219_LEN ); + +REG64_FLD( EX_L2_T0_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( EX_L2_T0_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( EX_L2_T0_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( EX_L2_T0_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( EX_L2_T0_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( EX_L2_T0_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( EX_L2_T0_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( C_T0_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( C_T0_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( C_T0_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( C_T0_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( C_T0_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( C_T0_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( C_T0_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( EX_L2_T1_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( EX_L2_T1_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( EX_L2_T1_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( EX_L2_T1_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( EX_L2_T1_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( EX_L2_T1_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( EX_L2_T1_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( C_T1_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( C_T1_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( C_T1_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( C_T1_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( C_T1_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( C_T1_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( C_T1_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( EX_L2_T2_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( EX_L2_T2_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( EX_L2_T2_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( EX_L2_T2_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( EX_L2_T2_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( EX_L2_T2_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( EX_L2_T2_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( C_T2_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( C_T2_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( C_T2_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( C_T2_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( C_T2_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( C_T2_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( C_T2_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( EX_L2_T3_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( EX_L2_T3_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( EX_L2_T3_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( EX_L2_T3_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( EX_L2_T3_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( EX_L2_T3_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( EX_L2_T3_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); + +REG64_FLD( C_T3_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY ); +REG64_FLD( C_T3_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_IDLE_DELAY_LEN ); +REG64_FLD( C_T3_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY ); +REG64_FLD( C_T3_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_COMPLETION_DELAY_LEN ); +REG64_FLD( C_T3_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SAMPLE_OVERRIDE ); +REG64_FLD( C_T3_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL ); +REG64_FLD( C_T3_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( EQ_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -13877,6 +19358,10 @@ REG64_FLD( EQ_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UN SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( EQ_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); +REG64_FLD( EQ_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1 ); +REG64_FLD( EQ_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1_LEN ); REG64_FLD( EX_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -13912,6 +19397,10 @@ REG64_FLD( EX_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UN SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( EX_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); +REG64_FLD( EX_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1 ); +REG64_FLD( EX_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1_LEN ); REG64_FLD( C_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -13947,6 +19436,153 @@ REG64_FLD( C_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UN SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( C_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); +REG64_FLD( C_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1 ); +REG64_FLD( C_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_THERM_CPM_ENABLE_L1_LEN ); + +REG64_FLD( EX_L2_THREAD_INFO_VTID0_V , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID0_V ); +REG64_FLD( EX_L2_THREAD_INFO_VTID1_V , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID1_V ); +REG64_FLD( EX_L2_THREAD_INFO_VTID2_V , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID2_V ); +REG64_FLD( EX_L2_THREAD_INFO_VTID3_V , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID3_V ); +REG64_FLD( EX_L2_THREAD_INFO_PTID0_V , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PTID0_V ); +REG64_FLD( EX_L2_THREAD_INFO_PTID1_V , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PTID1_V ); +REG64_FLD( EX_L2_THREAD_INFO_PTID2_V , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PTID2_V ); +REG64_FLD( EX_L2_THREAD_INFO_PTID3_V , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PTID3_V ); +REG64_FLD( EX_L2_THREAD_INFO_SMT_MODE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SMT_MODE ); +REG64_FLD( EX_L2_THREAD_INFO_SMT_MODE_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_SMT_MODE_LEN ); +REG64_FLD( EX_L2_THREAD_INFO_VTID0_TO_PTID_MAP , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID0_TO_PTID_MAP ); +REG64_FLD( EX_L2_THREAD_INFO_VTID0_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID0_TO_PTID_MAP_LEN ); +REG64_FLD( EX_L2_THREAD_INFO_VTID1_TO_PTID_MAP , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID1_TO_PTID_MAP ); +REG64_FLD( EX_L2_THREAD_INFO_VTID1_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID1_TO_PTID_MAP_LEN ); +REG64_FLD( EX_L2_THREAD_INFO_VTID2_TO_PTID_MAP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID2_TO_PTID_MAP ); +REG64_FLD( EX_L2_THREAD_INFO_VTID2_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID2_TO_PTID_MAP_LEN ); +REG64_FLD( EX_L2_THREAD_INFO_VTID3_TO_PTID_MAP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID3_TO_PTID_MAP ); +REG64_FLD( EX_L2_THREAD_INFO_VTID3_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_VTID3_TO_PTID_MAP_LEN ); +REG64_FLD( EX_L2_THREAD_INFO_RAM_THREAD_ACTIVE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RAM_THREAD_ACTIVE ); +REG64_FLD( EX_L2_THREAD_INFO_RAM_THREAD_ACTIVE_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_RAM_THREAD_ACTIVE_LEN ); +REG64_FLD( EX_L2_THREAD_INFO_PSCOM_PURGE , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , + SH_FLD_PSCOM_PURGE ); + +REG64_FLD( C_THREAD_INFO_VTID0_V , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID0_V ); +REG64_FLD( C_THREAD_INFO_VTID1_V , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID1_V ); +REG64_FLD( C_THREAD_INFO_VTID2_V , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID2_V ); +REG64_FLD( C_THREAD_INFO_VTID3_V , 3 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID3_V ); +REG64_FLD( C_THREAD_INFO_PTID0_V , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PTID0_V ); +REG64_FLD( C_THREAD_INFO_PTID1_V , 5 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PTID1_V ); +REG64_FLD( C_THREAD_INFO_PTID2_V , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PTID2_V ); +REG64_FLD( C_THREAD_INFO_PTID3_V , 7 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PTID3_V ); +REG64_FLD( C_THREAD_INFO_SMT_MODE , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SMT_MODE ); +REG64_FLD( C_THREAD_INFO_SMT_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SMT_MODE_LEN ); +REG64_FLD( C_THREAD_INFO_VTID0_TO_PTID_MAP , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID0_TO_PTID_MAP ); +REG64_FLD( C_THREAD_INFO_VTID0_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID0_TO_PTID_MAP_LEN ); +REG64_FLD( C_THREAD_INFO_VTID1_TO_PTID_MAP , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID1_TO_PTID_MAP ); +REG64_FLD( C_THREAD_INFO_VTID1_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID1_TO_PTID_MAP_LEN ); +REG64_FLD( C_THREAD_INFO_VTID2_TO_PTID_MAP , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID2_TO_PTID_MAP ); +REG64_FLD( C_THREAD_INFO_VTID2_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID2_TO_PTID_MAP_LEN ); +REG64_FLD( C_THREAD_INFO_VTID3_TO_PTID_MAP , 16 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID3_TO_PTID_MAP ); +REG64_FLD( C_THREAD_INFO_VTID3_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_VTID3_TO_PTID_MAP_LEN ); +REG64_FLD( C_THREAD_INFO_RAM_THREAD_ACTIVE , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RAM_THREAD_ACTIVE ); +REG64_FLD( C_THREAD_INFO_RAM_THREAD_ACTIVE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_RAM_THREAD_ACTIVE_LEN ); +REG64_FLD( C_THREAD_INFO_PSCOM_PURGE , 22 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PSCOM_PURGE ); + +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DIDT_THROTTLE ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DIDT_THROTTLE_LEN ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DIDT_TRIGGER_ENABLE , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DIDT_TRIGGER_ENABLE ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_CORE_SLOWDOWN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_CORE_SLOWDOWN ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_FORCE_DYN_SUPPRESS , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FORCE_DYN_SUPPRESS ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DYN_SUPPRESS_ON_THROTTLE , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DYN_SUPPRESS_ON_THROTTLE ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DISABLE_DROOP , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DISABLE_DROOP ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DISABLE_DROOP_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DISABLE_DROOP_LEN ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DROOP_MODE_DISABLE ); +REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DROOP_MODE_DISABLE_LEN ); + +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DIDT_THROTTLE ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DIDT_THROTTLE_LEN ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DIDT_TRIGGER_ENABLE , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DIDT_TRIGGER_ENABLE ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_CORE_SLOWDOWN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_CORE_SLOWDOWN ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_FORCE_DYN_SUPPRESS , 4 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_FORCE_DYN_SUPPRESS ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DYN_SUPPRESS_ON_THROTTLE , 5 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DYN_SUPPRESS_ON_THROTTLE ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DISABLE_DROOP , 6 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DISABLE_DROOP ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DISABLE_DROOP_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DISABLE_DROOP_LEN ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE , 9 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DROOP_MODE_DISABLE ); +REG64_FLD( C_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , + SH_FLD_SCOM_DROOP_MODE_DISABLE_LEN ); + +REG64_FLD( EQ_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT ); +REG64_FLD( EQ_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT_LEN ); + +REG64_FLD( EX_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT ); +REG64_FLD( EX_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT_LEN ); + +REG64_FLD( C_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT ); +REG64_FLD( C_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_INT_TIMEOUT_LEN ); REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VALUE ); @@ -14181,13 +19817,53 @@ REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -14325,6 +20001,14 @@ REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); @@ -14370,6 +20054,14 @@ REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_TPLC20_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -14429,13 +20121,53 @@ REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -14573,6 +20305,14 @@ REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); @@ -14618,6 +20358,14 @@ REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_TPLC21_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -14649,8 +20397,28 @@ REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -14742,6 +20510,14 @@ REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( EQ_TPLC21_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -14773,8 +20549,28 @@ REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UN REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , - SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -14866,6 +20662,390 @@ REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UN SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); + +REG64_FLD( EX_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( EX_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( C_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( C_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( EX_L3_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( EX_L3_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( EX_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( EX_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( EX_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( EX_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( EX_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( EX_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( EX_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( EX_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( EX_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( EX_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( EX_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( C_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( C_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( C_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( C_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( C_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( C_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( C_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( C_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( C_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( C_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( C_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_C , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( EX_L3_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EXTENDED_STORE_ON_TRIG_MODE ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL , 12 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LCL_CLK_GATE_CTRL ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_LCL_CLK_GATE_CTRL_LEN ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D , 14 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRCTRL_CONFIG_D ); +REG64_FLD( EX_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRCTRL_CONFIG_D_LEN ); + +REG64_FLD( C_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_EXTENDED_STORE_ON_TRIG_MODE ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL , 12 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LCL_CLK_GATE_CTRL ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_LCL_CLK_GATE_CTRL_LEN ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRCTRL_CONFIG_D ); +REG64_FLD( C_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRCTRL_CONFIG_D_LEN ); + +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_EXTENDED_STORE_ON_TRIG_MODE ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_LCL_CLK_GATE_CTRL ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_LCL_CLK_GATE_CTRL_LEN ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_TRCTRL_CONFIG_D ); +REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D_LEN , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_TRCTRL_CONFIG_D_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_SPARE_LT , 36 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); +REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_SPARE_LT_LEN ); + +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_SPARE_LT , 36 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_LT ); +REG64_FLD( C_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_SPARE_LT_LEN ); REG64_FLD( EX_V0_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); @@ -14873,20 +21053,40 @@ REG64_FLD( EX_V0_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( EX_V0_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( EX_V0_HMER_SPARE_3 , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( EX_V0_HMER_TFAC_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_V0_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( EX_V0_HMER_SPARE_6 , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( EX_V0_HMER_SPARE_7 , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( EX_V0_HMER_XSCOM_FAIL , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_V0_HMER_XSCOM_DONE , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( EX_V0_HMER_SPARE_10 , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( EX_V0_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( EX_V0_HMER_SPARE_12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( EX_V0_HMER_SPARE_13 , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( EX_V0_HMER_SPARE_14 , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( EX_V0_HMER_SPARE_15 , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( EX_V0_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_V0_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( EX_V0_HMER_SPARE_18 , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( EX_V0_HMER_SPARE_19 , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( EX_V0_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_V0_HMER_XSCOM_STATUS , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , @@ -14900,20 +21100,40 @@ REG64_FLD( EX_L2_V0_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V0_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( EX_L2_V0_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V0_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V0_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( EX_L2_V0_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_6 ); +REG64_FLD( EX_L2_V0_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V0_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V0_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_DONE ); +REG64_FLD( EX_L2_V0_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V0_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( EX_L2_V0_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_12 ); +REG64_FLD( EX_L2_V0_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_13 ); +REG64_FLD( EX_L2_V0_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_14 ); +REG64_FLD( EX_L2_V0_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V0_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V0_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( EX_L2_V0_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_18 ); +REG64_FLD( EX_L2_V0_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V0_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V0_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, @@ -14927,20 +21147,40 @@ REG64_FLD( C_V0_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( C_V0_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( C_V0_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( C_V0_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V0_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( C_V0_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( C_V0_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( C_V0_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V0_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( C_V0_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( C_V0_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( C_V0_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( C_V0_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( C_V0_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( C_V0_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( C_V0_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V0_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( C_V0_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( C_V0_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( C_V0_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V0_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , @@ -14954,20 +21194,40 @@ REG64_FLD( EX_V1_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( EX_V1_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( EX_V1_HMER_SPARE_3 , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( EX_V1_HMER_TFAC_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_V1_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( EX_V1_HMER_SPARE_6 , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( EX_V1_HMER_SPARE_7 , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( EX_V1_HMER_XSCOM_FAIL , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_V1_HMER_XSCOM_DONE , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( EX_V1_HMER_SPARE_10 , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( EX_V1_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( EX_V1_HMER_SPARE_12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( EX_V1_HMER_SPARE_13 , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( EX_V1_HMER_SPARE_14 , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( EX_V1_HMER_SPARE_15 , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( EX_V1_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_V1_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( EX_V1_HMER_SPARE_18 , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( EX_V1_HMER_SPARE_19 , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( EX_V1_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_V1_HMER_XSCOM_STATUS , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , @@ -14981,20 +21241,40 @@ REG64_FLD( EX_L2_V1_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V1_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( EX_L2_V1_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V1_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V1_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( EX_L2_V1_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_6 ); +REG64_FLD( EX_L2_V1_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V1_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V1_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_DONE ); +REG64_FLD( EX_L2_V1_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V1_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( EX_L2_V1_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_12 ); +REG64_FLD( EX_L2_V1_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_13 ); +REG64_FLD( EX_L2_V1_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_14 ); +REG64_FLD( EX_L2_V1_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V1_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V1_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( EX_L2_V1_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_18 ); +REG64_FLD( EX_L2_V1_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, + SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V1_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V1_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, @@ -15008,20 +21288,40 @@ REG64_FLD( C_V1_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( C_V1_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( C_V1_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( C_V1_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V1_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( C_V1_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( C_V1_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( C_V1_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V1_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( C_V1_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( C_V1_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( C_V1_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( C_V1_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( C_V1_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( C_V1_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( C_V1_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V1_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( C_V1_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( C_V1_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( C_V1_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V1_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , @@ -15035,20 +21335,40 @@ REG64_FLD( EX_L2_V2_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V2_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( EX_L2_V2_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V2_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V2_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( EX_L2_V2_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( EX_L2_V2_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V2_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V2_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( EX_L2_V2_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V2_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( EX_L2_V2_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( EX_L2_V2_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( EX_L2_V2_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( EX_L2_V2_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V2_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V2_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( EX_L2_V2_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( EX_L2_V2_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V2_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V2_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , @@ -15062,20 +21382,40 @@ REG64_FLD( C_V2_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( C_V2_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( C_V2_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( C_V2_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V2_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( C_V2_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( C_V2_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( C_V2_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V2_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( C_V2_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( C_V2_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( C_V2_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( C_V2_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( C_V2_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( C_V2_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( C_V2_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V2_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( C_V2_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( C_V2_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( C_V2_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V2_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , @@ -15089,20 +21429,40 @@ REG64_FLD( EX_L2_V3_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V3_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( EX_L2_V3_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V3_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V3_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( EX_L2_V3_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( EX_L2_V3_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V3_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V3_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( EX_L2_V3_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V3_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( EX_L2_V3_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( EX_L2_V3_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( EX_L2_V3_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( EX_L2_V3_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V3_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V3_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( EX_L2_V3_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( EX_L2_V3_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V3_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V3_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , @@ -15116,20 +21476,40 @@ REG64_FLD( C_V3_HMER_CME_REQUEST , 1 , SH_UN SH_FLD_CME_REQUEST ); REG64_FLD( C_V3_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); +REG64_FLD( C_V3_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); REG64_FLD( C_V3_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V3_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); +REG64_FLD( C_V3_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6 ); +REG64_FLD( C_V3_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_7 ); REG64_FLD( C_V3_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V3_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); +REG64_FLD( C_V3_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); REG64_FLD( C_V3_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); +REG64_FLD( C_V3_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( C_V3_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( C_V3_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( C_V3_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); REG64_FLD( C_V3_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V3_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); +REG64_FLD( C_V3_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( C_V3_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); REG64_FLD( C_V3_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V3_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , @@ -15591,6 +21971,15 @@ REG64_FLD( C_XSTOP3_WAIT_CYCLES , 48 , SH_UN REG64_FLD( C_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); +REG64_FLD( EQ_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_EQ , SH_ACS_SCOM , + SH_FLD_XSTOP ); + +REG64_FLD( EX_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_EX , SH_ACS_SCOM , + SH_FLD_XSTOP ); + +REG64_FLD( C_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_C , SH_ACS_SCOM , + SH_FLD_XSTOP ); + REG64_FLD( EQ_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( EQ_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_EQ , SH_ACS_SCOM , diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H index 8c8fc4a7..2ed5532e 100644 --- a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H +++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H @@ -59,23 +59,5 @@ REG64_FLD( EQ_QPPM_QACCR_L2_EX0_CLKGLM_SEL , 19 , SH_UN REG64_FLD( EQ_QPPM_QACCR_L2_EX1_CLKGLM_SEL , 39 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L2_EX1_CLKGLM_SEL ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION1_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION2_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION3_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION4_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION5_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION6_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION7_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION8_FENCE , 12 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION8_FENCE ); -REG64_FLD( EQ_CPLT_CTRL1_TC_REGION9_FENCE , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_REGION9_FENCE ); #endif diff --git a/src/import/chips/p9/common/include/p9_scom_template_consts.H b/src/import/chips/p9/common/include/p9_scom_template_consts.H index 0c7d6a5c..a0a985d7 100644 --- a/src/import/chips/p9/common/include/p9_scom_template_consts.H +++ b/src/import/chips/p9/common/include/p9_scom_template_consts.H @@ -198,129 +198,172 @@ static const uint64_t SH_UNT_PERV_0_PIB2OPB0 = 159; static const uint64_t SH_UNT_PERV_0_PIB2OPB1 = 160; static const uint64_t SH_UNT_PERV_1 = 161; static const uint64_t SH_UNT_PERV_12 = 162; -static const uint64_t SH_UNT_PERV_13 = 163; -static const uint64_t SH_UNT_PERV_14 = 164; -static const uint64_t SH_UNT_PERV_15 = 165; -static const uint64_t SH_UNT_PERV_16 = 166; -static const uint64_t SH_UNT_PERV_17 = 167; -static const uint64_t SH_UNT_PERV_18 = 168; -static const uint64_t SH_UNT_PERV_19 = 169; -static const uint64_t SH_UNT_PERV_2 = 170; -static const uint64_t SH_UNT_PERV_20 = 171; -static const uint64_t SH_UNT_PERV_21 = 172; -static const uint64_t SH_UNT_PERV_3 = 173; -static const uint64_t SH_UNT_PERV_32 = 174; -static const uint64_t SH_UNT_PERV_33 = 175; -static const uint64_t SH_UNT_PERV_34 = 176; -static const uint64_t SH_UNT_PERV_35 = 177; -static const uint64_t SH_UNT_PERV_36 = 178; -static const uint64_t SH_UNT_PERV_37 = 179; -static const uint64_t SH_UNT_PERV_38 = 180; -static const uint64_t SH_UNT_PERV_39 = 181; -static const uint64_t SH_UNT_PERV_4 = 182; -static const uint64_t SH_UNT_PERV_40 = 183; -static const uint64_t SH_UNT_PERV_41 = 184; -static const uint64_t SH_UNT_PERV_42 = 185; -static const uint64_t SH_UNT_PERV_43 = 186; -static const uint64_t SH_UNT_PERV_44 = 187; -static const uint64_t SH_UNT_PERV_45 = 188; -static const uint64_t SH_UNT_PERV_46 = 189; -static const uint64_t SH_UNT_PERV_47 = 190; -static const uint64_t SH_UNT_PERV_48 = 191; -static const uint64_t SH_UNT_PERV_49 = 192; -static const uint64_t SH_UNT_PERV_5 = 193; -static const uint64_t SH_UNT_PERV_50 = 194; -static const uint64_t SH_UNT_PERV_51 = 195; -static const uint64_t SH_UNT_PERV_52 = 196; -static const uint64_t SH_UNT_PERV_53 = 197; -static const uint64_t SH_UNT_PERV_54 = 198; -static const uint64_t SH_UNT_PERV_55 = 199; -static const uint64_t SH_UNT_PERV_6 = 200; -static const uint64_t SH_UNT_PERV_7 = 201; -static const uint64_t SH_UNT_PERV_8 = 202; -static const uint64_t SH_UNT_PERV_9 = 203; -static const uint64_t SH_UNT_PERV_FSB = 204; -static const uint64_t SH_UNT_PERV_FSI2PIB = 205; -static const uint64_t SH_UNT_PERV_FSII2C = 206; -static const uint64_t SH_UNT_PERV_FSISHIFT = 207; -static const uint64_t SH_UNT_PERV_PIB2OPB0 = 208; -static const uint64_t SH_UNT_PERV_PIB2OPB1 = 209; -static const uint64_t SH_UNT_PHB = 210; -static const uint64_t SH_UNT_PHB_0 = 211; -static const uint64_t SH_UNT_PHB_1 = 212; -static const uint64_t SH_UNT_PHB_2 = 213; -static const uint64_t SH_UNT_PHB_3 = 214; -static const uint64_t SH_UNT_PHB_4 = 215; -static const uint64_t SH_UNT_PHB_5 = 216; -static const uint64_t SH_UNT_PU_CME0 = 217; -static const uint64_t SH_UNT_PU_CME1 = 218; -static const uint64_t SH_UNT_PU_CME10 = 219; -static const uint64_t SH_UNT_PU_CME11 = 220; -static const uint64_t SH_UNT_PU_CME2 = 221; -static const uint64_t SH_UNT_PU_CME3 = 222; -static const uint64_t SH_UNT_PU_CME4 = 223; -static const uint64_t SH_UNT_PU_CME5 = 224; -static const uint64_t SH_UNT_PU_CME6 = 225; -static const uint64_t SH_UNT_PU_CME7 = 226; -static const uint64_t SH_UNT_PU_CME8 = 227; -static const uint64_t SH_UNT_PU_CME9 = 228; -static const uint64_t SH_UNT_PU_HTM0 = 229; -static const uint64_t SH_UNT_PU_HTM1 = 230; -static const uint64_t SH_UNT_PU_IOE = 231; -static const uint64_t SH_UNT_PU_MCD1 = 232; -static const uint64_t SH_UNT_PU_N0 = 233; -static const uint64_t SH_UNT_PU_N1 = 234; -static const uint64_t SH_UNT_PU_N2 = 235; -static const uint64_t SH_UNT_PU_N3 = 236; -static const uint64_t SH_UNT_PU_NMMU = 237; -static const uint64_t SH_UNT_PU_NPU = 238; -static const uint64_t SH_UNT_PU_NPU0 = 239; -static const uint64_t SH_UNT_PU_NPU0_CTL = 240; -static const uint64_t SH_UNT_PU_NPU0_DAT = 241; -static const uint64_t SH_UNT_PU_NPU0_SM0 = 242; -static const uint64_t SH_UNT_PU_NPU0_SM1 = 243; -static const uint64_t SH_UNT_PU_NPU0_SM2 = 244; -static const uint64_t SH_UNT_PU_NPU0_SM3 = 245; -static const uint64_t SH_UNT_PU_NPU1 = 246; -static const uint64_t SH_UNT_PU_NPU1_CTL = 247; -static const uint64_t SH_UNT_PU_NPU1_DAT = 248; -static const uint64_t SH_UNT_PU_NPU1_SM0 = 249; -static const uint64_t SH_UNT_PU_NPU1_SM1 = 250; -static const uint64_t SH_UNT_PU_NPU1_SM2 = 251; -static const uint64_t SH_UNT_PU_NPU1_SM3 = 252; -static const uint64_t SH_UNT_PU_NPU2 = 253; -static const uint64_t SH_UNT_PU_NPU2_CTL = 254; -static const uint64_t SH_UNT_PU_NPU2_DAT = 255; -static const uint64_t SH_UNT_PU_NPU2_NTL0 = 256; -static const uint64_t SH_UNT_PU_NPU2_NTL1 = 257; -static const uint64_t SH_UNT_PU_NPU2_SM0 = 258; -static const uint64_t SH_UNT_PU_NPU2_SM1 = 259; -static const uint64_t SH_UNT_PU_NPU2_SM2 = 260; -static const uint64_t SH_UNT_PU_NPU2_SM3 = 261; -static const uint64_t SH_UNT_PU_NPU_CTL = 262; -static const uint64_t SH_UNT_PU_NPU_DAT = 263; -static const uint64_t SH_UNT_PU_NPU_MSC_SM0 = 264; -static const uint64_t SH_UNT_PU_NPU_MSC_SM2 = 265; -static const uint64_t SH_UNT_PU_NPU_NTL0 = 266; -static const uint64_t SH_UNT_PU_NPU_NTL1 = 267; -static const uint64_t SH_UNT_PU_NPU_SM0 = 268; -static const uint64_t SH_UNT_PU_NPU_SM1 = 269; -static const uint64_t SH_UNT_PU_NPU_SM2 = 270; -static const uint64_t SH_UNT_PU_NPU_SM3 = 271; -static const uint64_t SH_UNT_PU_OTPROM0 = 272; -static const uint64_t SH_UNT_PU_OTPROM1 = 273; -static const uint64_t SH_UNT_PU_PBAIB_STACK1 = 274; -static const uint64_t SH_UNT_PU_PBAIB_STACK2 = 275; -static const uint64_t SH_UNT_PU_PBAIB_STACK5 = 276; -static const uint64_t SH_UNT_PU_PB_CENT_SM0 = 277; -static const uint64_t SH_UNT_PU_PB_CENT_SM1 = 278; -static const uint64_t SH_UNT_PU_PB_WEST_SM0 = 279; -static const uint64_t SH_UNT_XBUS = 280; -static const uint64_t SH_UNT_XBUS_0 = 281; -static const uint64_t SH_UNT_XBUS_1 = 282; -static const uint64_t SH_UNT_XBUS_2 = 283; -static const uint64_t SH_UNT_XBUS_IOPPE = 284; -static const uint64_t SH_UNT_XBUS_PERV = 285; +static const uint64_t SH_UNT_PERV_12_FSI2PIB = 163; +static const uint64_t SH_UNT_PERV_13 = 164; +static const uint64_t SH_UNT_PERV_13_FSI2PIB = 165; +static const uint64_t SH_UNT_PERV_14 = 166; +static const uint64_t SH_UNT_PERV_14_FSI2PIB = 167; +static const uint64_t SH_UNT_PERV_15 = 168; +static const uint64_t SH_UNT_PERV_15_FSI2PIB = 169; +static const uint64_t SH_UNT_PERV_16 = 170; +static const uint64_t SH_UNT_PERV_16_FSI2PIB = 171; +static const uint64_t SH_UNT_PERV_17 = 172; +static const uint64_t SH_UNT_PERV_17_FSI2PIB = 173; +static const uint64_t SH_UNT_PERV_18 = 174; +static const uint64_t SH_UNT_PERV_18_FSI2PIB = 175; +static const uint64_t SH_UNT_PERV_19 = 176; +static const uint64_t SH_UNT_PERV_19_FSI2PIB = 177; +static const uint64_t SH_UNT_PERV_1_FSI2PIB = 178; +static const uint64_t SH_UNT_PERV_2 = 179; +static const uint64_t SH_UNT_PERV_20 = 180; +static const uint64_t SH_UNT_PERV_20_FSI2PIB = 181; +static const uint64_t SH_UNT_PERV_21 = 182; +static const uint64_t SH_UNT_PERV_21_FSI2PIB = 183; +static const uint64_t SH_UNT_PERV_2_FSI2PIB = 184; +static const uint64_t SH_UNT_PERV_3 = 185; +static const uint64_t SH_UNT_PERV_32 = 186; +static const uint64_t SH_UNT_PERV_32_FSI2PIB = 187; +static const uint64_t SH_UNT_PERV_33 = 188; +static const uint64_t SH_UNT_PERV_33_FSI2PIB = 189; +static const uint64_t SH_UNT_PERV_34 = 190; +static const uint64_t SH_UNT_PERV_34_FSI2PIB = 191; +static const uint64_t SH_UNT_PERV_35 = 192; +static const uint64_t SH_UNT_PERV_35_FSI2PIB = 193; +static const uint64_t SH_UNT_PERV_36 = 194; +static const uint64_t SH_UNT_PERV_36_FSI2PIB = 195; +static const uint64_t SH_UNT_PERV_37 = 196; +static const uint64_t SH_UNT_PERV_37_FSI2PIB = 197; +static const uint64_t SH_UNT_PERV_38 = 198; +static const uint64_t SH_UNT_PERV_38_FSI2PIB = 199; +static const uint64_t SH_UNT_PERV_39 = 200; +static const uint64_t SH_UNT_PERV_39_FSI2PIB = 201; +static const uint64_t SH_UNT_PERV_3_FSI2PIB = 202; +static const uint64_t SH_UNT_PERV_4 = 203; +static const uint64_t SH_UNT_PERV_40 = 204; +static const uint64_t SH_UNT_PERV_40_FSI2PIB = 205; +static const uint64_t SH_UNT_PERV_41 = 206; +static const uint64_t SH_UNT_PERV_41_FSI2PIB = 207; +static const uint64_t SH_UNT_PERV_42 = 208; +static const uint64_t SH_UNT_PERV_42_FSI2PIB = 209; +static const uint64_t SH_UNT_PERV_43 = 210; +static const uint64_t SH_UNT_PERV_43_FSI2PIB = 211; +static const uint64_t SH_UNT_PERV_44 = 212; +static const uint64_t SH_UNT_PERV_44_FSI2PIB = 213; +static const uint64_t SH_UNT_PERV_45 = 214; +static const uint64_t SH_UNT_PERV_45_FSI2PIB = 215; +static const uint64_t SH_UNT_PERV_46 = 216; +static const uint64_t SH_UNT_PERV_46_FSI2PIB = 217; +static const uint64_t SH_UNT_PERV_47 = 218; +static const uint64_t SH_UNT_PERV_47_FSI2PIB = 219; +static const uint64_t SH_UNT_PERV_48 = 220; +static const uint64_t SH_UNT_PERV_48_FSI2PIB = 221; +static const uint64_t SH_UNT_PERV_49 = 222; +static const uint64_t SH_UNT_PERV_49_FSI2PIB = 223; +static const uint64_t SH_UNT_PERV_4_FSI2PIB = 224; +static const uint64_t SH_UNT_PERV_5 = 225; +static const uint64_t SH_UNT_PERV_50 = 226; +static const uint64_t SH_UNT_PERV_50_FSI2PIB = 227; +static const uint64_t SH_UNT_PERV_51 = 228; +static const uint64_t SH_UNT_PERV_51_FSI2PIB = 229; +static const uint64_t SH_UNT_PERV_52 = 230; +static const uint64_t SH_UNT_PERV_52_FSI2PIB = 231; +static const uint64_t SH_UNT_PERV_53 = 232; +static const uint64_t SH_UNT_PERV_53_FSI2PIB = 233; +static const uint64_t SH_UNT_PERV_54 = 234; +static const uint64_t SH_UNT_PERV_54_FSI2PIB = 235; +static const uint64_t SH_UNT_PERV_55 = 236; +static const uint64_t SH_UNT_PERV_55_FSI2PIB = 237; +static const uint64_t SH_UNT_PERV_5_FSI2PIB = 238; +static const uint64_t SH_UNT_PERV_6 = 239; +static const uint64_t SH_UNT_PERV_6_FSI2PIB = 240; +static const uint64_t SH_UNT_PERV_7 = 241; +static const uint64_t SH_UNT_PERV_7_FSI2PIB = 242; +static const uint64_t SH_UNT_PERV_8 = 243; +static const uint64_t SH_UNT_PERV_8_FSI2PIB = 244; +static const uint64_t SH_UNT_PERV_9 = 245; +static const uint64_t SH_UNT_PERV_9_FSI2PIB = 246; +static const uint64_t SH_UNT_PERV_FSB = 247; +static const uint64_t SH_UNT_PERV_FSI2PIB = 248; +static const uint64_t SH_UNT_PERV_FSII2C = 249; +static const uint64_t SH_UNT_PERV_FSISHIFT = 250; +static const uint64_t SH_UNT_PERV_PIB2OPB0 = 251; +static const uint64_t SH_UNT_PERV_PIB2OPB1 = 252; +static const uint64_t SH_UNT_PHB = 253; +static const uint64_t SH_UNT_PHB_0 = 254; +static const uint64_t SH_UNT_PHB_1 = 255; +static const uint64_t SH_UNT_PHB_2 = 256; +static const uint64_t SH_UNT_PHB_3 = 257; +static const uint64_t SH_UNT_PHB_4 = 258; +static const uint64_t SH_UNT_PHB_5 = 259; +static const uint64_t SH_UNT_PU_CME0 = 260; +static const uint64_t SH_UNT_PU_CME1 = 261; +static const uint64_t SH_UNT_PU_CME10 = 262; +static const uint64_t SH_UNT_PU_CME11 = 263; +static const uint64_t SH_UNT_PU_CME2 = 264; +static const uint64_t SH_UNT_PU_CME3 = 265; +static const uint64_t SH_UNT_PU_CME4 = 266; +static const uint64_t SH_UNT_PU_CME5 = 267; +static const uint64_t SH_UNT_PU_CME6 = 268; +static const uint64_t SH_UNT_PU_CME7 = 269; +static const uint64_t SH_UNT_PU_CME8 = 270; +static const uint64_t SH_UNT_PU_CME9 = 271; +static const uint64_t SH_UNT_PU_HTM0 = 272; +static const uint64_t SH_UNT_PU_HTM1 = 273; +static const uint64_t SH_UNT_PU_IOE = 274; +static const uint64_t SH_UNT_PU_MCD1 = 275; +static const uint64_t SH_UNT_PU_N0 = 276; +static const uint64_t SH_UNT_PU_N1 = 277; +static const uint64_t SH_UNT_PU_N2 = 278; +static const uint64_t SH_UNT_PU_N3 = 279; +static const uint64_t SH_UNT_PU_NMMU = 280; +static const uint64_t SH_UNT_PU_NPU = 281; +static const uint64_t SH_UNT_PU_NPU0 = 282; +static const uint64_t SH_UNT_PU_NPU0_CTL = 283; +static const uint64_t SH_UNT_PU_NPU0_DAT = 284; +static const uint64_t SH_UNT_PU_NPU0_SM0 = 285; +static const uint64_t SH_UNT_PU_NPU0_SM1 = 286; +static const uint64_t SH_UNT_PU_NPU0_SM2 = 287; +static const uint64_t SH_UNT_PU_NPU0_SM3 = 288; +static const uint64_t SH_UNT_PU_NPU1 = 289; +static const uint64_t SH_UNT_PU_NPU1_CTL = 290; +static const uint64_t SH_UNT_PU_NPU1_DAT = 291; +static const uint64_t SH_UNT_PU_NPU1_SM0 = 292; +static const uint64_t SH_UNT_PU_NPU1_SM1 = 293; +static const uint64_t SH_UNT_PU_NPU1_SM2 = 294; +static const uint64_t SH_UNT_PU_NPU1_SM3 = 295; +static const uint64_t SH_UNT_PU_NPU2 = 296; +static const uint64_t SH_UNT_PU_NPU2_CTL = 297; +static const uint64_t SH_UNT_PU_NPU2_DAT = 298; +static const uint64_t SH_UNT_PU_NPU2_NTL0 = 299; +static const uint64_t SH_UNT_PU_NPU2_NTL1 = 300; +static const uint64_t SH_UNT_PU_NPU2_SM0 = 301; +static const uint64_t SH_UNT_PU_NPU2_SM1 = 302; +static const uint64_t SH_UNT_PU_NPU2_SM2 = 303; +static const uint64_t SH_UNT_PU_NPU2_SM3 = 304; +static const uint64_t SH_UNT_PU_NPU_CTL = 305; +static const uint64_t SH_UNT_PU_NPU_DAT = 306; +static const uint64_t SH_UNT_PU_NPU_MSC_SM0 = 307; +static const uint64_t SH_UNT_PU_NPU_MSC_SM2 = 308; +static const uint64_t SH_UNT_PU_NPU_NTL0 = 309; +static const uint64_t SH_UNT_PU_NPU_NTL1 = 310; +static const uint64_t SH_UNT_PU_NPU_SM0 = 311; +static const uint64_t SH_UNT_PU_NPU_SM1 = 312; +static const uint64_t SH_UNT_PU_NPU_SM2 = 313; +static const uint64_t SH_UNT_PU_NPU_SM3 = 314; +static const uint64_t SH_UNT_PU_OTPROM0 = 315; +static const uint64_t SH_UNT_PU_OTPROM1 = 316; +static const uint64_t SH_UNT_PU_PBAIB_STACK1 = 317; +static const uint64_t SH_UNT_PU_PBAIB_STACK2 = 318; +static const uint64_t SH_UNT_PU_PBAIB_STACK5 = 319; +static const uint64_t SH_UNT_PU_PB_CENT_SM0 = 320; +static const uint64_t SH_UNT_PU_PB_CENT_SM1 = 321; +static const uint64_t SH_UNT_PU_PB_WEST_SM0 = 322; +static const uint64_t SH_UNT_XBUS = 323; +static const uint64_t SH_UNT_XBUS_0 = 324; +static const uint64_t SH_UNT_XBUS_1 = 325; +static const uint64_t SH_UNT_XBUS_2 = 326; +static const uint64_t SH_UNT_XBUS_IOPPE = 327; +static const uint64_t SH_UNT_XBUS_PERV = 328; static const uint64_t SH_ACS_FSI = 0; @@ -367,16 +410,17 @@ static const uint64_t SH_ACS_SCOMFSI1_RW = 40; static const uint64_t SH_ACS_SCOM_4P = 41; static const uint64_t SH_ACS_SCOM_CLRPART = 42; static const uint64_t SH_ACS_SCOM_NC = 43; -static const uint64_t SH_ACS_SCOM_RCLRPART = 44; -static const uint64_t SH_ACS_SCOM_RO = 45; -static const uint64_t SH_ACS_SCOM_RW = 46; -static const uint64_t SH_ACS_SCOM_W = 47; -static const uint64_t SH_ACS_SCOM_WAND = 48; -static const uint64_t SH_ACS_SCOM_WCLEAR = 49; -static const uint64_t SH_ACS_SCOM_WCLRPART = 50; -static const uint64_t SH_ACS_SCOM_WCLRREG = 51; -static const uint64_t SH_ACS_SCOM_WO = 52; -static const uint64_t SH_ACS_SCOM_WOR = 53; +static const uint64_t SH_ACS_SCOM_R0 = 44; +static const uint64_t SH_ACS_SCOM_RCLRPART = 45; +static const uint64_t SH_ACS_SCOM_RO = 46; +static const uint64_t SH_ACS_SCOM_RW = 47; +static const uint64_t SH_ACS_SCOM_W = 48; +static const uint64_t SH_ACS_SCOM_WAND = 49; +static const uint64_t SH_ACS_SCOM_WCLEAR = 50; +static const uint64_t SH_ACS_SCOM_WCLRPART = 51; +static const uint64_t SH_ACS_SCOM_WCLRREG = 52; +static const uint64_t SH_ACS_SCOM_WO = 53; +static const uint64_t SH_ACS_SCOM_WOR = 54; @@ -886,18684 +930,22063 @@ static const uint64_t SH_FLD_01_REFERENCE3 = 502; // 16 static const uint64_t SH_FLD_01_REFERENCE3_LEN = 503; // 16 static const uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP = 504; // 32 static const uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN = 505; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 = 506; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN = 507; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN = 508; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE = 509; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN = 510; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER = 511; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN = 512; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER = 513; // 32 -static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN = 514; // 32 -static const uint64_t SH_FLD_01_ROT0 = 515; // 16 -static const uint64_t SH_FLD_01_ROT0_LEN = 516; // 16 -static const uint64_t SH_FLD_01_ROT1 = 517; // 16 -static const uint64_t SH_FLD_01_ROT1_LEN = 518; // 16 -static const uint64_t SH_FLD_01_ROT_CLK_N0 = 519; // 128 -static const uint64_t SH_FLD_01_ROT_CLK_N0_LEN = 520; // 128 -static const uint64_t SH_FLD_01_ROT_CLK_N1 = 521; // 128 -static const uint64_t SH_FLD_01_ROT_CLK_N1_LEN = 522; // 128 -static const uint64_t SH_FLD_01_ROT_N0 = 523; // 128 -static const uint64_t SH_FLD_01_ROT_N0_LEN = 524; // 128 -static const uint64_t SH_FLD_01_ROT_N1 = 525; // 128 -static const uint64_t SH_FLD_01_ROT_N1_LEN = 526; // 128 -static const uint64_t SH_FLD_01_ROT_OVERRIDE = 527; // 32 -static const uint64_t SH_FLD_01_ROT_OVERRIDE_EN = 528; // 32 -static const uint64_t SH_FLD_01_ROT_OVERRIDE_LEN = 529; // 32 -static const uint64_t SH_FLD_01_RXCAL_DETECT_DONE_META = 530; // 32 -static const uint64_t SH_FLD_01_RXCAL_PD_CAL_LAG_META = 531; // 32 -static const uint64_t SH_FLD_01_RXCAL_PD_MAIN_LAG_META = 532; // 32 -static const uint64_t SH_FLD_01_RXCAL_PD_MAIN_LEAD_META = 533; // 32 -static const uint64_t SH_FLD_01_RXREG_COMPCON_DC = 534; // 32 -static const uint64_t SH_FLD_01_RXREG_COMPCON_DC_LEN = 535; // 32 -static const uint64_t SH_FLD_01_RXREG_CON_DC = 536; // 32 -static const uint64_t SH_FLD_01_RXREG_DAC_PULLUP_DC = 537; // 32 -static const uint64_t SH_FLD_01_RXREG_DRVCON_DC = 538; // 32 -static const uint64_t SH_FLD_01_RXREG_DRVCON_DC_LEN = 539; // 32 -static const uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC = 540; // 32 -static const uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN = 541; // 32 -static const uint64_t SH_FLD_01_RXREG_FINECAL_2XILSB_DC = 542; // 32 -static const uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC = 543; // 32 -static const uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 544; // 32 -static const uint64_t SH_FLD_01_RXREG_REF_SEL_DC = 545; // 32 -static const uint64_t SH_FLD_01_RXREG_REF_SEL_DC_LEN = 546; // 32 -static const uint64_t SH_FLD_01_S0ACENSLICENDRV_DC = 547; // 16 -static const uint64_t SH_FLD_01_S0ACENSLICENDRV_DC_LEN = 548; // 16 -static const uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC = 549; // 16 -static const uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC_LEN = 550; // 16 -static const uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC = 551; // 16 -static const uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC_LEN = 552; // 16 -static const uint64_t SH_FLD_01_S0INSDLYTAP = 553; // 16 -static const uint64_t SH_FLD_01_S1ACENSLICENDRV_DC = 554; // 16 -static const uint64_t SH_FLD_01_S1ACENSLICENDRV_DC_LEN = 555; // 16 -static const uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC = 556; // 16 -static const uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC_LEN = 557; // 16 -static const uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC = 558; // 16 -static const uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC_LEN = 559; // 16 -static const uint64_t SH_FLD_01_S1INSDLYTAP = 560; // 16 -static const uint64_t SH_FLD_01_SEL0 = 561; // 32 -static const uint64_t SH_FLD_01_SEL0_LEN = 562; // 16 -static const uint64_t SH_FLD_01_SEL1 = 563; // 32 -static const uint64_t SH_FLD_01_SEL10 = 564; // 32 -static const uint64_t SH_FLD_01_SEL10_LEN = 565; // 32 -static const uint64_t SH_FLD_01_SEL11 = 566; // 32 -static const uint64_t SH_FLD_01_SEL11_LEN = 567; // 32 -static const uint64_t SH_FLD_01_SEL12 = 568; // 32 -static const uint64_t SH_FLD_01_SEL12_LEN = 569; // 32 -static const uint64_t SH_FLD_01_SEL13 = 570; // 32 -static const uint64_t SH_FLD_01_SEL13_LEN = 571; // 32 -static const uint64_t SH_FLD_01_SEL14 = 572; // 32 -static const uint64_t SH_FLD_01_SEL14_LEN = 573; // 32 -static const uint64_t SH_FLD_01_SEL15 = 574; // 32 -static const uint64_t SH_FLD_01_SEL15_LEN = 575; // 32 -static const uint64_t SH_FLD_01_SEL1_LEN = 576; // 32 -static const uint64_t SH_FLD_01_SEL2 = 577; // 32 -static const uint64_t SH_FLD_01_SEL2_LEN = 578; // 32 -static const uint64_t SH_FLD_01_SEL3 = 579; // 32 -static const uint64_t SH_FLD_01_SEL3_LEN = 580; // 32 -static const uint64_t SH_FLD_01_SEL4 = 581; // 32 -static const uint64_t SH_FLD_01_SEL4_LEN = 582; // 32 -static const uint64_t SH_FLD_01_SEL5 = 583; // 32 -static const uint64_t SH_FLD_01_SEL5_LEN = 584; // 32 -static const uint64_t SH_FLD_01_SEL6 = 585; // 32 -static const uint64_t SH_FLD_01_SEL6_LEN = 586; // 32 -static const uint64_t SH_FLD_01_SEL7 = 587; // 32 -static const uint64_t SH_FLD_01_SEL7_LEN = 588; // 32 -static const uint64_t SH_FLD_01_SEL8 = 589; // 32 -static const uint64_t SH_FLD_01_SEL8_LEN = 590; // 16 -static const uint64_t SH_FLD_01_SEL9 = 591; // 32 -static const uint64_t SH_FLD_01_SEL9_LEN = 592; // 32 -static const uint64_t SH_FLD_01_SEL_A = 593; // 16 -static const uint64_t SH_FLD_01_SEL_A_LEN = 594; // 16 -static const uint64_t SH_FLD_01_SEL_B = 595; // 16 -static const uint64_t SH_FLD_01_SEL_B_LEN = 596; // 16 -static const uint64_t SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN = 597; // 32 -static const uint64_t SH_FLD_01_SLAVE_VREG_DAC_COARSE = 598; // 32 -static const uint64_t SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN = 599; // 32 -static const uint64_t SH_FLD_01_SLAVE_VREG_OVERRIDE = 600; // 32 -static const uint64_t SH_FLD_01_SLAVE_VREG_REF_SEL_DC = 601; // 32 -static const uint64_t SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN = 602; // 32 -static const uint64_t SH_FLD_01_SMALL_STEP_LEFT = 603; // 16 -static const uint64_t SH_FLD_01_SMALL_STEP_RIGHT = 604; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE = 605; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR0 = 606; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR1 = 607; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR2 = 608; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR3 = 609; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK1 = 610; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK2 = 611; // 16 -static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK3 = 612; // 16 -static const uint64_t SH_FLD_01_SYNC = 613; // 16 -static const uint64_t SH_FLD_01_SYNC_LEN = 614; // 16 -static const uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET = 615; // 16 -static const uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN = 616; // 16 -static const uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET = 617; // 16 -static const uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN = 618; // 16 -static const uint64_t SH_FLD_01_TEST_4TO1_MODE = 619; // 16 -static const uint64_t SH_FLD_01_TEST_CHECK_EN = 620; // 16 -static const uint64_t SH_FLD_01_TEST_CLEAR_ERROR = 621; // 16 -static const uint64_t SH_FLD_01_TEST_DATA_EN = 622; // 16 -static const uint64_t SH_FLD_01_TEST_GEN_EN = 623; // 16 -static const uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL = 624; // 16 -static const uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN = 625; // 16 -static const uint64_t SH_FLD_01_TEST_MODE = 626; // 16 -static const uint64_t SH_FLD_01_TEST_MODE_LEN = 627; // 16 -static const uint64_t SH_FLD_01_TEST_RESET = 628; // 16 -static const uint64_t SH_FLD_01_TRAILING_EDGE_FOUND_MASK = 629; // 16 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND = 630; // 16 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 = 631; // 8 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 632; // 8 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 = 633; // 8 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 634; // 8 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 = 635; // 16 -static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 636; // 16 -static const uint64_t SH_FLD_01_TRIG_PERIOD = 637; // 16 -static const uint64_t SH_FLD_01_TSYS = 638; // 16 -static const uint64_t SH_FLD_01_TSYS_LEN = 639; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE = 640; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 = 641; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 = 642; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 = 643; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 = 644; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 = 645; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 = 646; // 16 -static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 = 647; // 16 -static const uint64_t SH_FLD_01_UPPER = 648; // 32 -static const uint64_t SH_FLD_01_UPPER_LEN = 649; // 32 -static const uint64_t SH_FLD_01_VALID_NS_BIG_L = 650; // 16 -static const uint64_t SH_FLD_01_VALID_NS_BIG_L_MASK = 651; // 16 -static const uint64_t SH_FLD_01_VALID_NS_BIG_R = 652; // 16 -static const uint64_t SH_FLD_01_VALID_NS_BIG_R_MASK = 653; // 16 -static const uint64_t SH_FLD_01_VALID_NS_JUMP_BACK = 654; // 16 -static const uint64_t SH_FLD_01_VALID_NS_JUMP_BACK_MASK = 655; // 16 -static const uint64_t SH_FLD_01_VALUE_DRAM0 = 656; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM0_LEN = 657; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM1 = 658; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM1_LEN = 659; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM2 = 660; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM2_LEN = 661; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM3 = 662; // 64 -static const uint64_t SH_FLD_01_VALUE_DRAM3_LEN = 663; // 64 -static const uint64_t SH_FLD_01_VREG_RXCAL_COMP_OUT_META = 664; // 32 -static const uint64_t SH_FLD_01_VREG_SLAVE_COMP_OUT = 665; // 32 -static const uint64_t SH_FLD_01_WL_ADVANCE_DISABLE = 666; // 16 -static const uint64_t SH_FLD_01_WL_ERR_CLK16 = 667; // 32 -static const uint64_t SH_FLD_01_WL_ERR_CLK16_MASK = 668; // 16 -static const uint64_t SH_FLD_01_WL_ERR_CLK18 = 669; // 32 -static const uint64_t SH_FLD_01_WL_ERR_CLK18_MASK = 670; // 16 -static const uint64_t SH_FLD_01_WL_ERR_CLK20 = 671; // 32 -static const uint64_t SH_FLD_01_WL_ERR_CLK20_MASK = 672; // 16 -static const uint64_t SH_FLD_01_WL_ERR_CLK22 = 673; // 32 -static const uint64_t SH_FLD_01_WRAPSEL = 674; // 16 -static const uint64_t SH_FLD_01_WTRFL_AVE_DIS = 675; // 16 -static const uint64_t SH_FLD_01_ZERO_DETECTED = 676; // 16 -static const uint64_t SH_FLD_0X00_DATA_PARITY = 677; // 4 -static const uint64_t SH_FLD_0X00_SPARE_30_31 = 678; // 1 -static const uint64_t SH_FLD_0X00_SPARE_30_31_LEN = 679; // 1 -static const uint64_t SH_FLD_0X01_DATA_PARITY = 680; // 4 -static const uint64_t SH_FLD_0X01_SPARE_03 = 681; // 1 -static const uint64_t SH_FLD_0X01_SPARE_28_31 = 682; // 1 -static const uint64_t SH_FLD_0X01_SPARE_28_31_LEN = 683; // 1 -static const uint64_t SH_FLD_0X02_DATA_PARITY = 684; // 4 -static const uint64_t SH_FLD_0X02_SPARE_03 = 685; // 1 -static const uint64_t SH_FLD_0X02_SPARE_28_31 = 686; // 1 -static const uint64_t SH_FLD_0X02_SPARE_28_31_LEN = 687; // 1 -static const uint64_t SH_FLD_0X03_DATA_PARITY = 688; // 4 -static const uint64_t SH_FLD_0X03_SPARE_03 = 689; // 1 -static const uint64_t SH_FLD_0X03_SPARE_28_31 = 690; // 1 -static const uint64_t SH_FLD_0X03_SPARE_28_31_LEN = 691; // 1 -static const uint64_t SH_FLD_0X04_DATA_PARITY = 692; // 4 -static const uint64_t SH_FLD_0X04_SPARE_03 = 693; // 1 -static const uint64_t SH_FLD_0X04_SPARE_28_31 = 694; // 1 -static const uint64_t SH_FLD_0X04_SPARE_28_31_LEN = 695; // 1 -static const uint64_t SH_FLD_0X05_DATA_PARITY = 696; // 4 -static const uint64_t SH_FLD_0X05_SPARE_01 = 697; // 1 -static const uint64_t SH_FLD_0X05_SPARE_05 = 698; // 1 -static const uint64_t SH_FLD_0X06_DATA_PARITY = 699; // 4 -static const uint64_t SH_FLD_0X06_SPARE_02_04 = 700; // 1 -static const uint64_t SH_FLD_0X06_SPARE_02_04_LEN = 701; // 1 -static const uint64_t SH_FLD_0X06_SPARE_16_21 = 702; // 1 -static const uint64_t SH_FLD_0X06_SPARE_16_21_LEN = 703; // 1 -static const uint64_t SH_FLD_0X07_DATA_PARITY = 704; // 4 -static const uint64_t SH_FLD_0X07_SPARE_19 = 705; // 1 -static const uint64_t SH_FLD_0X07_SPARE_20 = 706; // 1 -static const uint64_t SH_FLD_0X07_SPARE_22_31 = 707; // 1 -static const uint64_t SH_FLD_0X07_SPARE_22_31_LEN = 708; // 1 -static const uint64_t SH_FLD_0X08_DATA_PARITY = 709; // 4 -static const uint64_t SH_FLD_0X08_SPARE_03 = 710; // 1 -static const uint64_t SH_FLD_0X08_SPARE_30 = 711; // 1 -static const uint64_t SH_FLD_0X09_DATA_PARITY = 712; // 4 -static const uint64_t SH_FLD_0X0A_DATA_PARITY = 713; // 4 -static const uint64_t SH_FLD_0X0A_SPARE_13_15 = 714; // 1 -static const uint64_t SH_FLD_0X0A_SPARE_13_15_LEN = 715; // 1 -static const uint64_t SH_FLD_0X0B_DATA_PARITY = 716; // 4 -static const uint64_t SH_FLD_0X0B_SPARE_04_05 = 717; // 1 -static const uint64_t SH_FLD_0X0B_SPARE_04_05_LEN = 718; // 1 -static const uint64_t SH_FLD_0X0B_SPARE_17 = 719; // 1 -static const uint64_t SH_FLD_0X0B_SPARE_33_39 = 720; // 1 -static const uint64_t SH_FLD_0X0B_SPARE_33_39_LEN = 721; // 1 -static const uint64_t SH_FLD_0X0C_DATA_PARITY = 722; // 4 -static const uint64_t SH_FLD_0X0D_SPARE_60_62 = 723; // 1 -static const uint64_t SH_FLD_0X0D_SPARE_60_62_LEN = 724; // 1 -static const uint64_t SH_FLD_0X10_DATA_PARITY = 725; // 4 -static const uint64_t SH_FLD_0X10_SPARE_17_18 = 726; // 1 -static const uint64_t SH_FLD_0X10_SPARE_17_18_LEN = 727; // 1 -static const uint64_t SH_FLD_0X10_SPARE_19_23 = 728; // 1 -static const uint64_t SH_FLD_0X10_SPARE_19_23_LEN = 729; // 1 -static const uint64_t SH_FLD_0X10_SPARE_24_25 = 730; // 1 -static const uint64_t SH_FLD_0X10_SPARE_24_25_LEN = 731; // 1 -static const uint64_t SH_FLD_0X10_SPARE_27 = 732; // 1 -static const uint64_t SH_FLD_0X10_SPARE_29 = 733; // 1 -static const uint64_t SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 734; // 4 -static const uint64_t SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY = 735; // 4 -static const uint64_t SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY = 736; // 4 -static const uint64_t SH_FLD_0X20_DATA_PARITY = 737; // 4 -static const uint64_t SH_FLD_0X22_SPARE_01 = 738; // 1 -static const uint64_t SH_FLD_0X22_SPARE_03_07 = 739; // 1 -static const uint64_t SH_FLD_0X22_SPARE_03_07_LEN = 740; // 1 -static const uint64_t SH_FLD_0X23_DATA_PARITY = 741; // 4 -static const uint64_t SH_FLD_0X23_SPARE_06_07 = 742; // 1 -static const uint64_t SH_FLD_0X23_SPARE_06_07_LEN = 743; // 1 -static const uint64_t SH_FLD_0X24_DATA_PARITY = 744; // 4 -static const uint64_t SH_FLD_0X24_SPARE_05_07 = 745; // 1 -static const uint64_t SH_FLD_0X24_SPARE_05_07_LEN = 746; // 1 -static const uint64_t SH_FLD_0X27_DATA_PARITY = 747; // 4 -static const uint64_t SH_FLD_0X27_SPARE_34 = 748; // 1 -static const uint64_t SH_FLD_0X27_SPARE_36 = 749; // 1 -static const uint64_t SH_FLD_0X29_DATA_PARITY = 750; // 4 -static const uint64_t SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY = 751; // 4 -static const uint64_t SH_FLD_0_2 = 752; // 16 -static const uint64_t SH_FLD_0_CANNED_0 = 753; // 2 -static const uint64_t SH_FLD_0_CANNED_0_LEN = 754; // 2 -static const uint64_t SH_FLD_0_CANNED_1 = 755; // 2 -static const uint64_t SH_FLD_0_CANNED_1_LEN = 756; // 2 -static const uint64_t SH_FLD_0_CPS = 757; // 2 -static const uint64_t SH_FLD_0_CPS_LEN = 758; // 2 -static const uint64_t SH_FLD_0_DATA = 759; // 1 -static const uint64_t SH_FLD_0_DATA_LEN = 760; // 1 -static const uint64_t SH_FLD_0_LEN = 761; // 62 -static const uint64_t SH_FLD_0_LOCAL_STEP_MODE_ENABLE = 762; // 1 -static const uint64_t SH_FLD_0_OSC_NOT_VALID = 763; // 1 -static const uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT = 764; // 1 -static const uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 765; // 1 -static const uint64_t SH_FLD_0_RESULT = 766; // 43 -static const uint64_t SH_FLD_0_RESULT_LEN = 767; // 43 -static const uint64_t SH_FLD_0_SELECT = 768; // 1 -static const uint64_t SH_FLD_0_SELECT_LEN = 769; // 1 -static const uint64_t SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL = 770; // 3 -static const uint64_t SH_FLD_0_STEP_ALIGN_DISABLE = 771; // 1 -static const uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD = 772; // 1 -static const uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN = 773; // 1 -static const uint64_t SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 774; // 2 -static const uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION = 775; // 2 -static const uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN = 776; // 2 -static const uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT = 777; // 2 -static const uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN = 778; // 2 -static const uint64_t SH_FLD_0_STEP_STEER_ENABLE = 779; // 1 -static const uint64_t SH_FLD_1 = 780; // 525 -static const uint64_t SH_FLD_10 = 781; // 8 -static const uint64_t SH_FLD_10_RESERVED = 782; // 3 -static const uint64_t SH_FLD_10_SPARE_REFCLOCK = 783; // 3 -static const uint64_t SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL = 784; // 3 -static const uint64_t SH_FLD_11 = 785; // 8 -static const uint64_t SH_FLD_11_RESERVED = 786; // 3 -static const uint64_t SH_FLD_11_SPARE_REFCLOCK = 787; // 3 -static const uint64_t SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL = 788; // 3 -static const uint64_t SH_FLD_12 = 789; // 8 -static const uint64_t SH_FLD_12GB_ENABLE = 790; // 8 -static const uint64_t SH_FLD_12_RESERVED = 791; // 3 -static const uint64_t SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL = 792; // 3 -static const uint64_t SH_FLD_13 = 793; // 8 -static const uint64_t SH_FLD_13_RESERVED = 794; // 3 -static const uint64_t SH_FLD_13_SPARE_OPB_CONTROL = 795; // 3 -static const uint64_t SH_FLD_13_SPARE_PROBE = 796; // 3 -static const uint64_t SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL = 797; // 3 -static const uint64_t SH_FLD_14 = 798; // 8 -static const uint64_t SH_FLD_14_RESERVED = 799; // 3 -static const uint64_t SH_FLD_14_SPARE_OPB_CONTROL = 800; // 3 -static const uint64_t SH_FLD_14_SPARE_PLL = 801; // 3 -static const uint64_t SH_FLD_14_SPARE_PROBE = 802; // 3 -static const uint64_t SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL = 803; // 3 -static const uint64_t SH_FLD_15 = 804; // 8 -static const uint64_t SH_FLD_15_RESERVED = 805; // 3 -static const uint64_t SH_FLD_15_SPARE_OPB_CONTROL = 806; // 3 -static const uint64_t SH_FLD_15_SPARE_OSC = 807; // 3 -static const uint64_t SH_FLD_15_SPARE_PLL = 808; // 3 -static const uint64_t SH_FLD_15_SPARE_PROBE = 809; // 3 -static const uint64_t SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL = 810; // 3 -static const uint64_t SH_FLD_16 = 811; // 6 -static const uint64_t SH_FLD_16_SPARE_OSC = 812; // 3 -static const uint64_t SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL = 813; // 3 -static const uint64_t SH_FLD_17 = 814; // 6 -static const uint64_t SH_FLD_17_SPARE_OSC = 815; // 3 -static const uint64_t SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL = 816; // 3 -static const uint64_t SH_FLD_18 = 817; // 6 -static const uint64_t SH_FLD_18_31_SPARE = 818; // 8 -static const uint64_t SH_FLD_18_31_SPARE_LEN = 819; // 8 -static const uint64_t SH_FLD_18_SPARE_MUX_CONTROL = 820; // 3 -static const uint64_t SH_FLD_18_SPARE_OSC = 821; // 3 -static const uint64_t SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL = 822; // 3 -static const uint64_t SH_FLD_19 = 823; // 6 -static const uint64_t SH_FLD_19_SPARE_MUX_CONTROL = 824; // 3 -static const uint64_t SH_FLD_19_SPARE_OSC = 825; // 3 -static const uint64_t SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL = 826; // 3 -static const uint64_t SH_FLD_1_3 = 827; // 16 -static const uint64_t SH_FLD_1_CANNED_0 = 828; // 2 -static const uint64_t SH_FLD_1_CANNED_0_LEN = 829; // 2 -static const uint64_t SH_FLD_1_CANNED_1 = 830; // 2 -static const uint64_t SH_FLD_1_CANNED_1_LEN = 831; // 2 -static const uint64_t SH_FLD_1_CPS = 832; // 2 -static const uint64_t SH_FLD_1_CPS_LEN = 833; // 2 -static const uint64_t SH_FLD_1_DATA = 834; // 1 -static const uint64_t SH_FLD_1_DATA_LEN = 835; // 1 -static const uint64_t SH_FLD_1_LEN = 836; // 105 -static const uint64_t SH_FLD_1_LOCAL_STEP_MODE_ENABLE = 837; // 1 -static const uint64_t SH_FLD_1_OSC_NOT_VALID = 838; // 1 -static const uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT = 839; // 1 -static const uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 840; // 1 -static const uint64_t SH_FLD_1_RESULT = 841; // 43 -static const uint64_t SH_FLD_1_RESULT_LEN = 842; // 43 -static const uint64_t SH_FLD_1_SELECT = 843; // 1 -static const uint64_t SH_FLD_1_SELECT_LEN = 844; // 1 -static const uint64_t SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL = 845; // 3 -static const uint64_t SH_FLD_1_STEP_ALIGN_DISABLE = 846; // 1 -static const uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD = 847; // 1 -static const uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN = 848; // 1 -static const uint64_t SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 849; // 2 -static const uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION = 850; // 2 -static const uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN = 851; // 2 -static const uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT = 852; // 2 -static const uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN = 853; // 2 -static const uint64_t SH_FLD_1_STEP_STEER_ENABLE = 854; // 1 -static const uint64_t SH_FLD_1_UNUSED = 855; // 1 -static const uint64_t SH_FLD_2 = 856; // 466 -static const uint64_t SH_FLD_20 = 857; // 6 -static const uint64_t SH_FLD_20_RESERVED = 858; // 3 -static const uint64_t SH_FLD_20_SPARE_OSC = 859; // 3 -static const uint64_t SH_FLD_20_SPARE_PLL_CONTROL = 860; // 3 -static const uint64_t SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL = 861; // 3 -static const uint64_t SH_FLD_21 = 862; // 6 -static const uint64_t SH_FLD_21_FREE_USAGE = 863; // 3 -static const uint64_t SH_FLD_21_RESERVED = 864; // 3 -static const uint64_t SH_FLD_21_SPARE_OSC = 865; // 3 -static const uint64_t SH_FLD_21_SPARE_PLL_CONTROL = 866; // 3 -static const uint64_t SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL = 867; // 3 -static const uint64_t SH_FLD_22 = 868; // 6 -static const uint64_t SH_FLD_22_FREE_USAGE = 869; // 3 -static const uint64_t SH_FLD_22_RESERVED = 870; // 6 -static const uint64_t SH_FLD_22_SPARE_OSC = 871; // 3 -static const uint64_t SH_FLD_22_SPARE_PLL_CONTROL = 872; // 3 -static const uint64_t SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL = 873; // 3 -static const uint64_t SH_FLD_22_SPARE_TEST = 874; // 3 -static const uint64_t SH_FLD_23 = 875; // 134 -static const uint64_t SH_FLD_23_0_11 = 876; // 16 -static const uint64_t SH_FLD_23_0_11_LEN = 877; // 16 -static const uint64_t SH_FLD_23_12_15 = 878; // 16 -static const uint64_t SH_FLD_23_12_15_LEN = 879; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE = 880; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR0 = 881; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR1 = 882; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR2 = 883; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR3 = 884; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK1 = 885; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK2 = 886; // 16 -static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK3 = 887; // 16 -static const uint64_t SH_FLD_23_ADVANCE_PING_PONG = 888; // 16 -static const uint64_t SH_FLD_23_ADVANCE_PR_VALUE = 889; // 16 -static const uint64_t SH_FLD_23_ATESTSEL_0_4 = 890; // 16 -static const uint64_t SH_FLD_23_ATESTSEL_0_4_LEN = 891; // 16 -static const uint64_t SH_FLD_23_ATEST_SEL_0_1 = 892; // 16 -static const uint64_t SH_FLD_23_ATEST_SEL_0_1_LEN = 893; // 16 -static const uint64_t SH_FLD_23_BAD_BIT = 894; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_ERR0 = 895; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_ERR1 = 896; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_ERR2 = 897; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_ERR3 = 898; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_MASK1 = 899; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_MASK2 = 900; // 16 -static const uint64_t SH_FLD_23_BAD_BIT_MASK3 = 901; // 16 -static const uint64_t SH_FLD_23_BB_LOCK0 = 902; // 16 -static const uint64_t SH_FLD_23_BB_LOCK1 = 903; // 16 -static const uint64_t SH_FLD_23_BIG_STEP_RIGHT = 904; // 16 -static const uint64_t SH_FLD_23_BIT_CENTERED = 905; // 16 -static const uint64_t SH_FLD_23_BIT_CENTERED_LEN = 906; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA = 907; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR0 = 908; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR1 = 909; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR2 = 910; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR3 = 911; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK1 = 912; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK2 = 913; // 16 -static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK3 = 914; // 16 -static const uint64_t SH_FLD_23_BLFIFO_DIS = 915; // 16 -static const uint64_t SH_FLD_23_BUMP = 916; // 16 -static const uint64_t SH_FLD_23_CALGATE_ON = 917; // 16 -static const uint64_t SH_FLD_23_CALIBRATE_BIT = 918; // 16 -static const uint64_t SH_FLD_23_CALIBRATE_BIT_LEN = 919; // 16 -static const uint64_t SH_FLD_23_CAL_CKTS_ACTIVE = 920; // 32 -static const uint64_t SH_FLD_23_CAL_ERROR = 921; // 32 -static const uint64_t SH_FLD_23_CAL_ERROR_FINE = 922; // 32 -static const uint64_t SH_FLD_23_CAL_GOOD = 923; // 32 -static const uint64_t SH_FLD_23_CAL_PD_ENABLE = 924; // 32 -static const uint64_t SH_FLD_23_CHECKER_ENABLE = 925; // 16 -static const uint64_t SH_FLD_23_CHECKER_RESET = 926; // 16 -static const uint64_t SH_FLD_23_CHICKSW_HW278227 = 927; // 16 -static const uint64_t SH_FLD_23_CLK16_SINGLE_ENDED = 928; // 64 -static const uint64_t SH_FLD_23_CLK18_SINGLE_ENDED = 929; // 64 -static const uint64_t SH_FLD_23_CLK20_SINGLE_ENDED = 930; // 64 -static const uint64_t SH_FLD_23_CLK22_SINGLE_ENDED = 931; // 64 -static const uint64_t SH_FLD_23_CLK_LEVEL = 932; // 16 -static const uint64_t SH_FLD_23_CLK_LEVEL_LEN = 933; // 16 -static const uint64_t SH_FLD_23_CNTL_POL = 934; // 16 -static const uint64_t SH_FLD_23_CNTL_SRC = 935; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0 = 936; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK = 937; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1 = 938; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK = 939; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2 = 940; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK = 941; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3 = 942; // 16 -static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK = 943; // 16 -static const uint64_t SH_FLD_23_CONTINUOUS_UPDATE = 944; // 32 -static const uint64_t SH_FLD_23_CTR_1D_CHICKEN_SWITCH = 945; // 16 -static const uint64_t SH_FLD_23_CTR_2D_BIG_STEP_VAL = 946; // 16 -static const uint64_t SH_FLD_23_CTR_2D_BIG_STEP_VAL_LEN = 947; // 16 -static const uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL = 948; // 16 -static const uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN = 949; // 16 -static const uint64_t SH_FLD_23_CTR_CUR = 950; // 16 -static const uint64_t SH_FLD_23_CTR_CUR_LEN = 951; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP = 952; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN = 953; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP = 954; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN = 955; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT = 956; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN = 957; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT = 958; // 16 -static const uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN = 959; // 16 -static const uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER = 960; // 16 -static const uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER_LEN = 961; // 16 -static const uint64_t SH_FLD_23_CTR_RANGE_SELECT = 962; // 16 -static const uint64_t SH_FLD_23_CTR_RUN_FULL_1D = 963; // 16 -static const uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX = 964; // 16 -static const uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN = 965; // 16 -static const uint64_t SH_FLD_23_DD2_DQS_FIX_DIS = 966; // 16 -static const uint64_t SH_FLD_23_DD2_FIX_DIS = 967; // 16 -static const uint64_t SH_FLD_23_DD2_WTRFL_SYNC_DIS = 968; // 16 -static const uint64_t SH_FLD_23_DELAY1 = 969; // 16 -static const uint64_t SH_FLD_23_DELAY10 = 970; // 16 -static const uint64_t SH_FLD_23_DELAY10_LEN = 971; // 16 -static const uint64_t SH_FLD_23_DELAY11 = 972; // 16 -static const uint64_t SH_FLD_23_DELAY11_LEN = 973; // 16 -static const uint64_t SH_FLD_23_DELAY12 = 974; // 16 -static const uint64_t SH_FLD_23_DELAY12_LEN = 975; // 16 -static const uint64_t SH_FLD_23_DELAY13 = 976; // 16 -static const uint64_t SH_FLD_23_DELAY13_LEN = 977; // 16 -static const uint64_t SH_FLD_23_DELAY14 = 978; // 16 -static const uint64_t SH_FLD_23_DELAY14_LEN = 979; // 16 -static const uint64_t SH_FLD_23_DELAY15 = 980; // 16 -static const uint64_t SH_FLD_23_DELAY15_LEN = 981; // 16 -static const uint64_t SH_FLD_23_DELAY1_LEN = 982; // 16 -static const uint64_t SH_FLD_23_DELAY2 = 983; // 16 -static const uint64_t SH_FLD_23_DELAY2_LEN = 984; // 16 -static const uint64_t SH_FLD_23_DELAY3 = 985; // 16 -static const uint64_t SH_FLD_23_DELAY3_LEN = 986; // 16 -static const uint64_t SH_FLD_23_DELAY4 = 987; // 16 -static const uint64_t SH_FLD_23_DELAY4_LEN = 988; // 16 -static const uint64_t SH_FLD_23_DELAY5 = 989; // 16 -static const uint64_t SH_FLD_23_DELAY5_LEN = 990; // 16 -static const uint64_t SH_FLD_23_DELAY6 = 991; // 16 -static const uint64_t SH_FLD_23_DELAY6_LEN = 992; // 16 -static const uint64_t SH_FLD_23_DELAY7 = 993; // 16 -static const uint64_t SH_FLD_23_DELAY7_LEN = 994; // 16 -static const uint64_t SH_FLD_23_DELAY8 = 995; // 16 -static const uint64_t SH_FLD_23_DELAY8_LEN = 996; // 16 -static const uint64_t SH_FLD_23_DELAY9 = 997; // 16 -static const uint64_t SH_FLD_23_DELAY9_LEN = 998; // 16 -static const uint64_t SH_FLD_23_DELAYG = 999; // 1280 -static const uint64_t SH_FLD_23_DELAYG_LEN = 1000; // 1280 -static const uint64_t SH_FLD_23_DELAY_PING_PONG_HALF = 1001; // 16 -static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 1002; // 16 -static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1003; // 16 -static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW = 1004; // 16 -static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1005; // 16 -static const uint64_t SH_FLD_23_DETECT_REQ = 1006; // 32 -static const uint64_t SH_FLD_23_DFT_FORCE_OUTPUTS = 1007; // 16 -static const uint64_t SH_FLD_23_DFT_PRBS7_GEN_EN = 1008; // 16 -static const uint64_t SH_FLD_23_DIGITAL_EN = 1009; // 16 -static const uint64_t SH_FLD_23_DIR_0_15 = 1010; // 16 -static const uint64_t SH_FLD_23_DIR_0_15_LEN = 1011; // 16 -static const uint64_t SH_FLD_23_DISABLE_0_15 = 1012; // 64 -static const uint64_t SH_FLD_23_DISABLE_0_15_LEN = 1013; // 64 -static const uint64_t SH_FLD_23_DISABLE_16_23 = 1014; // 64 -static const uint64_t SH_FLD_23_DISABLE_16_23_LEN = 1015; // 64 -static const uint64_t SH_FLD_23_DISABLE_PING_PONG = 1016; // 16 -static const uint64_t SH_FLD_23_DISABLE_TERMINATION = 1017; // 16 -static const uint64_t SH_FLD_23_DIS_CLK_GATE = 1018; // 16 -static const uint64_t SH_FLD_23_DI_ADR0_ADR1 = 1019; // 16 -static const uint64_t SH_FLD_23_DI_ADR10_ADR11 = 1020; // 16 -static const uint64_t SH_FLD_23_DI_ADR12_ADR13 = 1021; // 16 -static const uint64_t SH_FLD_23_DI_ADR14_ADR15 = 1022; // 16 -static const uint64_t SH_FLD_23_DI_ADR2 = 1023; // 8 -static const uint64_t SH_FLD_23_DI_ADR3 = 1024; // 8 -static const uint64_t SH_FLD_23_DI_ADR4_ADR5 = 1025; // 16 -static const uint64_t SH_FLD_23_DI_ADR6_ADR7 = 1026; // 16 -static const uint64_t SH_FLD_23_DI_ADR8_ADR9 = 1027; // 16 -static const uint64_t SH_FLD_23_DLL_ADJUST = 1028; // 32 -static const uint64_t SH_FLD_23_DLL_ADJUST_LEN = 1029; // 32 -static const uint64_t SH_FLD_23_DLL_COMPARE_OUT = 1030; // 32 -static const uint64_t SH_FLD_23_DLL_CORRECT_EN = 1031; // 32 -static const uint64_t SH_FLD_23_DLL_ITER_A = 1032; // 32 -static const uint64_t SH_FLD_23_DL_FORCE_ON = 1033; // 16 -static const uint64_t SH_FLD_23_DONE = 1034; // 32 -static const uint64_t SH_FLD_23_DQS = 1035; // 16 -static const uint64_t SH_FLD_23_DQSCLK_SELECT0 = 1036; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT0_LEN = 1037; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT1 = 1038; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT1_LEN = 1039; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT2 = 1040; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT2_LEN = 1041; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT3 = 1042; // 64 -static const uint64_t SH_FLD_23_DQSCLK_SELECT3_LEN = 1043; // 64 -static const uint64_t SH_FLD_23_DQS_ALIGN_CNTR = 1044; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_CNTR_LEN = 1045; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_FIX_DIS = 1046; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_JITTER = 1047; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_QUAD = 1048; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_QUAD_LEN = 1049; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_SM = 1050; // 16 -static const uint64_t SH_FLD_23_DQS_ALIGN_SM_LEN = 1051; // 16 -static const uint64_t SH_FLD_23_DQS_LEN = 1052; // 16 -static const uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS = 1053; // 16 -static const uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS_LEN = 1054; // 16 -static const uint64_t SH_FLD_23_DQS_QUAD_CONFIG = 1055; // 16 -static const uint64_t SH_FLD_23_DQS_QUAD_CONFIG_LEN = 1056; // 16 -static const uint64_t SH_FLD_23_DRIFT_ERROR = 1057; // 16 -static const uint64_t SH_FLD_23_DRIFT_MASK = 1058; // 16 -static const uint64_t SH_FLD_23_DRVREN_MODE = 1059; // 32 -static const uint64_t SH_FLD_23_DYN_MCTERM_CNTL_EN = 1060; // 16 -static const uint64_t SH_FLD_23_DYN_POWER_CNTL_EN = 1061; // 16 -static const uint64_t SH_FLD_23_DYN_RX_GATE_CNTL_EN = 1062; // 16 -static const uint64_t SH_FLD_23_ENABLE_0_15 = 1063; // 16 -static const uint64_t SH_FLD_23_ENABLE_0_15_LEN = 1064; // 16 -static const uint64_t SH_FLD_23_ENABLE_16_23 = 1065; // 16 -static const uint64_t SH_FLD_23_ENABLE_16_23_LEN = 1066; // 16 -static const uint64_t SH_FLD_23_EN_DQS_OFFSET = 1067; // 16 -static const uint64_t SH_FLD_23_EN_DRIVER_INVFB_DC = 1068; // 32 -static const uint64_t SH_FLD_23_EN_N_WR = 1069; // 16 -static const uint64_t SH_FLD_23_EN_N_WR_LEN = 1070; // 16 -static const uint64_t SH_FLD_23_EN_P_WR = 1071; // 32 -static const uint64_t SH_FLD_23_EN_P_WR_LEN = 1072; // 32 -static const uint64_t SH_FLD_23_ERROR = 1073; // 16 -static const uint64_t SH_FLD_23_ERROR_LEN = 1074; // 16 -static const uint64_t SH_FLD_23_ERR_CLK22_MASK = 1075; // 16 -static const uint64_t SH_FLD_23_EYE_CLIPPING = 1076; // 16 -static const uint64_t SH_FLD_23_EYE_CLIPPING_MASK = 1077; // 16 -static const uint64_t SH_FLD_23_FINE_STEPPING = 1078; // 16 -static const uint64_t SH_FLD_23_FLUSH = 1079; // 16 -static const uint64_t SH_FLD_23_FORCE_DQS_LANES_ON = 1080; // 16 -static const uint64_t SH_FLD_23_FORCE_FIFO_CAPTURE = 1081; // 16 -static const uint64_t SH_FLD_23_FREE_USAGE = 1082; // 3 -static const uint64_t SH_FLD_23_FW_LEFT_SIDE = 1083; // 16 -static const uint64_t SH_FLD_23_FW_LEFT_SIDE_LEN = 1084; // 16 -static const uint64_t SH_FLD_23_FW_RIGHT_SIDE = 1085; // 16 -static const uint64_t SH_FLD_23_FW_RIGHT_SIDE_LEN = 1086; // 16 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0 = 1087; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3 = 1088; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3_LEN = 1089; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_LEN = 1090; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0 = 1091; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3 = 1092; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3_LEN = 1093; // 8 -static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_LEN = 1094; // 8 -static const uint64_t SH_FLD_23_HS_PROBE_A = 1095; // 16 -static const uint64_t SH_FLD_23_HS_PROBE_A_LEN = 1096; // 16 -static const uint64_t SH_FLD_23_HS_PROBE_B = 1097; // 16 -static const uint64_t SH_FLD_23_HS_PROBE_B_LEN = 1098; // 16 -static const uint64_t SH_FLD_23_HW_VALUE = 1099; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N0 = 1100; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N0_MASK = 1101; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N1 = 1102; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N1_MASK = 1103; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N2 = 1104; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N2_MASK = 1105; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N3 = 1106; // 16 -static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N3_MASK = 1107; // 16 -static const uint64_t SH_FLD_23_INIT_IO = 1108; // 16 -static const uint64_t SH_FLD_23_INIT_RXDLL_CAL_RESET = 1109; // 32 -static const uint64_t SH_FLD_23_INIT_RXDLL_CAL_UPDATE = 1110; // 32 -static const uint64_t SH_FLD_23_INTERP_SIG_SLEW = 1111; // 16 -static const uint64_t SH_FLD_23_INTERP_SIG_SLEW_LEN = 1112; // 16 -static const uint64_t SH_FLD_23_INVALID_NS_BIG_R = 1113; // 16 -static const uint64_t SH_FLD_23_INVALID_NS_BIG_R_MASK = 1114; // 16 -static const uint64_t SH_FLD_23_INVALID_NS_SMALL_L = 1115; // 16 -static const uint64_t SH_FLD_23_INVALID_NS_SMALL_L_MASK = 1116; // 16 -static const uint64_t SH_FLD_23_INVALID_NS_SMALL_R = 1117; // 16 -static const uint64_t SH_FLD_23_INVALID_NS_SMALL_R_MASK = 1118; // 16 -static const uint64_t SH_FLD_23_ITERATION_CNTR = 1119; // 16 -static const uint64_t SH_FLD_23_ITERATION_CNTR_LEN = 1120; // 16 -static const uint64_t SH_FLD_23_JUMP_BACK_RIGHT = 1121; // 16 -static const uint64_t SH_FLD_23_LANE__0_11_PD = 1122; // 16 -static const uint64_t SH_FLD_23_LANE__0_11_PD_LEN = 1123; // 16 -static const uint64_t SH_FLD_23_LANE__12_15_PD = 1124; // 16 -static const uint64_t SH_FLD_23_LANE__12_15_PD_LEN = 1125; // 16 -static const uint64_t SH_FLD_23_LEADING_EDGE_FOUND_MASK = 1126; // 16 -static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND = 1127; // 16 -static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 = 1128; // 16 -static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1129; // 16 -static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 = 1130; // 16 -static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1131; // 16 -static const uint64_t SH_FLD_23_LEN = 1132; // 128 -static const uint64_t SH_FLD_23_LOOPBACK_DLY12 = 1133; // 16 -static const uint64_t SH_FLD_23_LOOPBACK_FIX_EN = 1134; // 16 -static const uint64_t SH_FLD_23_LOWER = 1135; // 32 -static const uint64_t SH_FLD_23_LOWER_LEN = 1136; // 32 -static const uint64_t SH_FLD_23_MAIN_PD_ENABLE = 1137; // 32 -static const uint64_t SH_FLD_23_MATCH_STEP_RIGHT = 1138; // 16 -static const uint64_t SH_FLD_23_MAX_DQS = 1139; // 16 -static const uint64_t SH_FLD_23_MAX_DQS_ITER = 1140; // 16 -static const uint64_t SH_FLD_23_MAX_DQS_LEN = 1141; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE = 1142; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_ERR0 = 1143; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_ERR1 = 1144; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_ERR2 = 1145; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_ERR3 = 1146; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_MASK1 = 1147; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_MASK2 = 1148; // 16 -static const uint64_t SH_FLD_23_MAX_RANGE_MASK3 = 1149; // 16 -static const uint64_t SH_FLD_23_MEMINTD00 = 1150; // 16 -static const uint64_t SH_FLD_23_MEMINTD00_LEN = 1151; // 16 -static const uint64_t SH_FLD_23_MEMINTD01 = 1152; // 16 -static const uint64_t SH_FLD_23_MEMINTD01_LEN = 1153; // 16 -static const uint64_t SH_FLD_23_MEMINTD02 = 1154; // 16 -static const uint64_t SH_FLD_23_MEMINTD02_LEN = 1155; // 16 -static const uint64_t SH_FLD_23_MEMINTD03 = 1156; // 16 -static const uint64_t SH_FLD_23_MEMINTD03_LEN = 1157; // 16 -static const uint64_t SH_FLD_23_MEMINTD04 = 1158; // 16 -static const uint64_t SH_FLD_23_MEMINTD04_LEN = 1159; // 16 -static const uint64_t SH_FLD_23_MEMINTD05 = 1160; // 16 -static const uint64_t SH_FLD_23_MEMINTD05_LEN = 1161; // 16 -static const uint64_t SH_FLD_23_MEMINTD06 = 1162; // 16 -static const uint64_t SH_FLD_23_MEMINTD06_LEN = 1163; // 16 -static const uint64_t SH_FLD_23_MEMINTD07 = 1164; // 16 -static const uint64_t SH_FLD_23_MEMINTD07_LEN = 1165; // 16 -static const uint64_t SH_FLD_23_MEMINTD08 = 1166; // 16 -static const uint64_t SH_FLD_23_MEMINTD08_LEN = 1167; // 16 -static const uint64_t SH_FLD_23_MEMINTD09 = 1168; // 16 -static const uint64_t SH_FLD_23_MEMINTD09_LEN = 1169; // 16 -static const uint64_t SH_FLD_23_MEMINTD10 = 1170; // 16 -static const uint64_t SH_FLD_23_MEMINTD10_LEN = 1171; // 16 -static const uint64_t SH_FLD_23_MEMINTD11 = 1172; // 16 -static const uint64_t SH_FLD_23_MEMINTD11_LEN = 1173; // 16 -static const uint64_t SH_FLD_23_MEMINTD12 = 1174; // 16 -static const uint64_t SH_FLD_23_MEMINTD12_LEN = 1175; // 16 -static const uint64_t SH_FLD_23_MEMINTD13 = 1176; // 16 -static const uint64_t SH_FLD_23_MEMINTD13_LEN = 1177; // 16 -static const uint64_t SH_FLD_23_MEMINTD14 = 1178; // 16 -static const uint64_t SH_FLD_23_MEMINTD14_LEN = 1179; // 16 -static const uint64_t SH_FLD_23_MEMINTD15 = 1180; // 16 -static const uint64_t SH_FLD_23_MEMINTD15_LEN = 1181; // 16 -static const uint64_t SH_FLD_23_MEMINTD16 = 1182; // 16 -static const uint64_t SH_FLD_23_MEMINTD16_LEN = 1183; // 16 -static const uint64_t SH_FLD_23_MEMINTD17 = 1184; // 16 -static const uint64_t SH_FLD_23_MEMINTD17_LEN = 1185; // 16 -static const uint64_t SH_FLD_23_MEMINTD18 = 1186; // 16 -static const uint64_t SH_FLD_23_MEMINTD18_LEN = 1187; // 16 -static const uint64_t SH_FLD_23_MEMINTD19 = 1188; // 16 -static const uint64_t SH_FLD_23_MEMINTD19_LEN = 1189; // 16 -static const uint64_t SH_FLD_23_MEMINTD20 = 1190; // 16 -static const uint64_t SH_FLD_23_MEMINTD20_LEN = 1191; // 16 -static const uint64_t SH_FLD_23_MEMINTD21 = 1192; // 16 -static const uint64_t SH_FLD_23_MEMINTD21_LEN = 1193; // 16 -static const uint64_t SH_FLD_23_MEMINTD22 = 1194; // 16 -static const uint64_t SH_FLD_23_MEMINTD22_LEN = 1195; // 16 -static const uint64_t SH_FLD_23_MEMINTD23 = 1196; // 16 -static const uint64_t SH_FLD_23_MEMINTD23_LEN = 1197; // 16 -static const uint64_t SH_FLD_23_MIN_EYE = 1198; // 16 -static const uint64_t SH_FLD_23_MIN_EYE_MASK = 1199; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE = 1200; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_ERR0 = 1201; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_ERR1 = 1202; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_ERR2 = 1203; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_ERR3 = 1204; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_MASK1 = 1205; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_MASK2 = 1206; // 16 -static const uint64_t SH_FLD_23_MIN_RANGE_MASK3 = 1207; // 16 -static const uint64_t SH_FLD_23_MIN_RD_EYE_SIZE = 1208; // 16 -static const uint64_t SH_FLD_23_MIN_RD_EYE_SIZE_LEN = 1209; // 16 -static const uint64_t SH_FLD_23_MRS_CMD_N0 = 1210; // 16 -static const uint64_t SH_FLD_23_MRS_CMD_N1 = 1211; // 16 -static const uint64_t SH_FLD_23_MRS_CMD_N2 = 1212; // 16 -static const uint64_t SH_FLD_23_MRS_CMD_N3 = 1213; // 16 -static const uint64_t SH_FLD_23_N0 = 1214; // 128 -static const uint64_t SH_FLD_23_N0_LEN = 1215; // 128 -static const uint64_t SH_FLD_23_N1 = 1216; // 128 -static const uint64_t SH_FLD_23_N1_LEN = 1217; // 128 -static const uint64_t SH_FLD_23_N2 = 1218; // 128 -static const uint64_t SH_FLD_23_N2_LEN = 1219; // 128 -static const uint64_t SH_FLD_23_N3 = 1220; // 128 -static const uint64_t SH_FLD_23_N3_LEN = 1221; // 128 -static const uint64_t SH_FLD_23_NIB0 = 1222; // 16 -static const uint64_t SH_FLD_23_NIB0TCFLIP_DC = 1223; // 16 -static const uint64_t SH_FLD_23_NIB0_EN_FORCE = 1224; // 16 -static const uint64_t SH_FLD_23_NIB0_LEN = 1225; // 16 -static const uint64_t SH_FLD_23_NIB1 = 1226; // 16 -static const uint64_t SH_FLD_23_NIB1TCFLIP_DC = 1227; // 16 -static const uint64_t SH_FLD_23_NIB1_EN_FORCE = 1228; // 16 -static const uint64_t SH_FLD_23_NIB1_LEN = 1229; // 16 -static const uint64_t SH_FLD_23_NIB2 = 1230; // 16 -static const uint64_t SH_FLD_23_NIB2TCFLIP_DC = 1231; // 16 -static const uint64_t SH_FLD_23_NIB2_EN_FORCE = 1232; // 16 -static const uint64_t SH_FLD_23_NIB2_LEN = 1233; // 16 -static const uint64_t SH_FLD_23_NIB3 = 1234; // 16 -static const uint64_t SH_FLD_23_NIB3TCFLIP_DC = 1235; // 16 -static const uint64_t SH_FLD_23_NIB3_EN_FORCE = 1236; // 16 -static const uint64_t SH_FLD_23_NIB3_LEN = 1237; // 16 -static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP = 1238; // 16 -static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN = 1239; // 16 -static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES = 1240; // 16 -static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES_LEN = 1241; // 16 -static const uint64_t SH_FLD_23_NIB_0_DQSEL_CAP = 1242; // 16 -static const uint64_t SH_FLD_23_NIB_0_DQSEL_CAP_LEN = 1243; // 16 -static const uint64_t SH_FLD_23_NIB_0_DQSEL_RES = 1244; // 16 -static const uint64_t SH_FLD_23_NIB_0_DQSEL_RES_LEN = 1245; // 16 -static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP = 1246; // 16 -static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN = 1247; // 16 -static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES = 1248; // 16 -static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES_LEN = 1249; // 16 -static const uint64_t SH_FLD_23_NIB_1_DQSEL_CAP = 1250; // 16 -static const uint64_t SH_FLD_23_NIB_1_DQSEL_CAP_LEN = 1251; // 16 -static const uint64_t SH_FLD_23_NIB_1_DQSEL_RES = 1252; // 16 -static const uint64_t SH_FLD_23_NIB_1_DQSEL_RES_LEN = 1253; // 16 -static const uint64_t SH_FLD_23_NO_DQS = 1254; // 16 -static const uint64_t SH_FLD_23_NO_DQS_MASK = 1255; // 16 -static const uint64_t SH_FLD_23_NO_EYE_DETECTED = 1256; // 16 -static const uint64_t SH_FLD_23_NO_EYE_DETECTED_MASK = 1257; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE = 1258; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_ERR0 = 1259; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_ERR1 = 1260; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_ERR2 = 1261; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_ERR3 = 1262; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_MASK1 = 1263; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_MASK2 = 1264; // 16 -static const uint64_t SH_FLD_23_NO_INCREASE_MASK3 = 1265; // 16 -static const uint64_t SH_FLD_23_NO_LOCK = 1266; // 16 -static const uint64_t SH_FLD_23_NO_LOCK_MASK = 1267; // 16 -static const uint64_t SH_FLD_23_OFFSET0 = 1268; // 16 -static const uint64_t SH_FLD_23_OFFSET0_LEN = 1269; // 16 -static const uint64_t SH_FLD_23_OFFSET1 = 1270; // 16 -static const uint64_t SH_FLD_23_OFFSET1_LEN = 1271; // 16 -static const uint64_t SH_FLD_23_OFFSET2 = 1272; // 32 -static const uint64_t SH_FLD_23_OFFSET2_LEN = 1273; // 32 -static const uint64_t SH_FLD_23_OFFSET3 = 1274; // 32 -static const uint64_t SH_FLD_23_OFFSET3_LEN = 1275; // 32 -static const uint64_t SH_FLD_23_OFFSET4 = 1276; // 32 -static const uint64_t SH_FLD_23_OFFSET4_LEN = 1277; // 32 -static const uint64_t SH_FLD_23_OFFSET5 = 1278; // 32 -static const uint64_t SH_FLD_23_OFFSET5_LEN = 1279; // 32 -static const uint64_t SH_FLD_23_OFFSET6 = 1280; // 32 -static const uint64_t SH_FLD_23_OFFSET6_LEN = 1281; // 32 -static const uint64_t SH_FLD_23_OFFSET7 = 1282; // 32 -static const uint64_t SH_FLD_23_OFFSET7_LEN = 1283; // 32 -static const uint64_t SH_FLD_23_OFFSET_ERR = 1284; // 16 -static const uint64_t SH_FLD_23_OFFSET_ERR_MASK = 1285; // 16 -static const uint64_t SH_FLD_23_OPERATE_MODE = 1286; // 16 -static const uint64_t SH_FLD_23_OPERATE_MODE_LEN = 1287; // 16 -static const uint64_t SH_FLD_23_OVERRIDE = 1288; // 32 -static const uint64_t SH_FLD_23_PERCAL_PWR_DIS = 1289; // 16 -static const uint64_t SH_FLD_23_PER_CAL_UPDATE_DISABLE = 1290; // 16 -static const uint64_t SH_FLD_23_PHASE_ALIGN_RESET = 1291; // 32 -static const uint64_t SH_FLD_23_PHASE_CNTL_EN = 1292; // 32 -static const uint64_t SH_FLD_23_PHASE_DEFAULT_EN = 1293; // 32 -static const uint64_t SH_FLD_23_POS_EDGE_ALIGN = 1294; // 32 -static const uint64_t SH_FLD_23_QUAD0 = 1295; // 16 -static const uint64_t SH_FLD_23_QUAD0_CLK16 = 1296; // 128 -static const uint64_t SH_FLD_23_QUAD0_CLK18 = 1297; // 128 -static const uint64_t SH_FLD_23_QUAD0_LEN = 1298; // 16 -static const uint64_t SH_FLD_23_QUAD1 = 1299; // 16 -static const uint64_t SH_FLD_23_QUAD1_CLK16 = 1300; // 128 -static const uint64_t SH_FLD_23_QUAD1_CLK18 = 1301; // 128 -static const uint64_t SH_FLD_23_QUAD1_LEN = 1302; // 16 -static const uint64_t SH_FLD_23_QUAD2 = 1303; // 16 -static const uint64_t SH_FLD_23_QUAD2_CLK16 = 1304; // 64 -static const uint64_t SH_FLD_23_QUAD2_CLK18 = 1305; // 64 -static const uint64_t SH_FLD_23_QUAD2_CLK20 = 1306; // 128 -static const uint64_t SH_FLD_23_QUAD2_CLK22 = 1307; // 128 -static const uint64_t SH_FLD_23_QUAD2_LEN = 1308; // 16 -static const uint64_t SH_FLD_23_QUAD3 = 1309; // 16 -static const uint64_t SH_FLD_23_QUAD3_CLK16 = 1310; // 64 -static const uint64_t SH_FLD_23_QUAD3_CLK18 = 1311; // 64 -static const uint64_t SH_FLD_23_QUAD3_CLK20 = 1312; // 128 -static const uint64_t SH_FLD_23_QUAD3_CLK22 = 1313; // 128 -static const uint64_t SH_FLD_23_QUAD3_LEN = 1314; // 16 -static const uint64_t SH_FLD_23_RANGE_DRAM0 = 1315; // 64 -static const uint64_t SH_FLD_23_RANGE_DRAM1 = 1316; // 64 -static const uint64_t SH_FLD_23_RANGE_DRAM2 = 1317; // 64 -static const uint64_t SH_FLD_23_RANGE_DRAM3 = 1318; // 64 -static const uint64_t SH_FLD_23_RD = 1319; // 272 -static const uint64_t SH_FLD_23_RDCLK_SELECT0 = 1320; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT0_LEN = 1321; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT1 = 1322; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT1_LEN = 1323; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT2 = 1324; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT2_LEN = 1325; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT3 = 1326; // 64 -static const uint64_t SH_FLD_23_RDCLK_SELECT3_LEN = 1327; // 64 -static const uint64_t SH_FLD_23_RD_DELAY0 = 1328; // 112 -static const uint64_t SH_FLD_23_RD_DELAY0_LEN = 1329; // 112 -static const uint64_t SH_FLD_23_RD_DELAY1 = 1330; // 112 -static const uint64_t SH_FLD_23_RD_DELAY1_LEN = 1331; // 112 -static const uint64_t SH_FLD_23_RD_DELAY2 = 1332; // 112 -static const uint64_t SH_FLD_23_RD_DELAY2_LEN = 1333; // 112 -static const uint64_t SH_FLD_23_RD_DELAY3 = 1334; // 112 -static const uint64_t SH_FLD_23_RD_DELAY3_LEN = 1335; // 112 -static const uint64_t SH_FLD_23_RD_DELAY4 = 1336; // 112 -static const uint64_t SH_FLD_23_RD_DELAY4_LEN = 1337; // 112 -static const uint64_t SH_FLD_23_RD_DELAY5 = 1338; // 112 -static const uint64_t SH_FLD_23_RD_DELAY5_LEN = 1339; // 112 -static const uint64_t SH_FLD_23_RD_DELAY6 = 1340; // 112 -static const uint64_t SH_FLD_23_RD_DELAY6_LEN = 1341; // 112 -static const uint64_t SH_FLD_23_RD_DELAY7 = 1342; // 112 -static const uint64_t SH_FLD_23_RD_DELAY7_LEN = 1343; // 112 -static const uint64_t SH_FLD_23_RD_LEN = 1344; // 272 -static const uint64_t SH_FLD_23_RD_SIZE0 = 1345; // 176 -static const uint64_t SH_FLD_23_RD_SIZE0_LEN = 1346; // 176 -static const uint64_t SH_FLD_23_RD_SIZE1 = 1347; // 176 -static const uint64_t SH_FLD_23_RD_SIZE1_LEN = 1348; // 176 -static const uint64_t SH_FLD_23_RD_SIZE2 = 1349; // 176 -static const uint64_t SH_FLD_23_RD_SIZE2_LEN = 1350; // 176 -static const uint64_t SH_FLD_23_RD_SIZE3 = 1351; // 176 -static const uint64_t SH_FLD_23_RD_SIZE3_LEN = 1352; // 176 -static const uint64_t SH_FLD_23_RD_SIZE4 = 1353; // 176 -static const uint64_t SH_FLD_23_RD_SIZE4_LEN = 1354; // 176 -static const uint64_t SH_FLD_23_RD_SIZE5 = 1355; // 176 -static const uint64_t SH_FLD_23_RD_SIZE5_LEN = 1356; // 176 -static const uint64_t SH_FLD_23_RD_SIZE6 = 1357; // 176 -static const uint64_t SH_FLD_23_RD_SIZE6_LEN = 1358; // 176 -static const uint64_t SH_FLD_23_RD_SIZE7 = 1359; // 176 -static const uint64_t SH_FLD_23_RD_SIZE7_LEN = 1360; // 176 -static const uint64_t SH_FLD_23_READ_CENTERING_MODE = 1361; // 16 -static const uint64_t SH_FLD_23_READ_CENTERING_MODE_LEN = 1362; // 16 -static const uint64_t SH_FLD_23_REFERENCE1 = 1363; // 16 -static const uint64_t SH_FLD_23_REFERENCE1_LEN = 1364; // 16 -static const uint64_t SH_FLD_23_REFERENCE2 = 1365; // 16 -static const uint64_t SH_FLD_23_REFERENCE2_LEN = 1366; // 16 -static const uint64_t SH_FLD_23_REFERENCE3 = 1367; // 16 -static const uint64_t SH_FLD_23_REFERENCE3_LEN = 1368; // 16 -static const uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP = 1369; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN = 1370; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 = 1371; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN = 1372; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN = 1373; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE = 1374; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN = 1375; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER = 1376; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN = 1377; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER = 1378; // 32 -static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN = 1379; // 32 -static const uint64_t SH_FLD_23_RESERVED = 1380; // 6 -static const uint64_t SH_FLD_23_ROT0 = 1381; // 16 -static const uint64_t SH_FLD_23_ROT0_LEN = 1382; // 16 -static const uint64_t SH_FLD_23_ROT1 = 1383; // 16 -static const uint64_t SH_FLD_23_ROT1_LEN = 1384; // 16 -static const uint64_t SH_FLD_23_ROT_CLK_N0 = 1385; // 128 -static const uint64_t SH_FLD_23_ROT_CLK_N0_LEN = 1386; // 128 -static const uint64_t SH_FLD_23_ROT_CLK_N1 = 1387; // 128 -static const uint64_t SH_FLD_23_ROT_CLK_N1_LEN = 1388; // 128 -static const uint64_t SH_FLD_23_ROT_N0 = 1389; // 128 -static const uint64_t SH_FLD_23_ROT_N0_LEN = 1390; // 128 -static const uint64_t SH_FLD_23_ROT_N1 = 1391; // 128 -static const uint64_t SH_FLD_23_ROT_N1_LEN = 1392; // 128 -static const uint64_t SH_FLD_23_ROT_OVERRIDE = 1393; // 32 -static const uint64_t SH_FLD_23_ROT_OVERRIDE_EN = 1394; // 32 -static const uint64_t SH_FLD_23_ROT_OVERRIDE_LEN = 1395; // 32 -static const uint64_t SH_FLD_23_RXCAL_DETECT_DONE_META = 1396; // 32 -static const uint64_t SH_FLD_23_RXCAL_PD_CAL_LAG_META = 1397; // 32 -static const uint64_t SH_FLD_23_RXCAL_PD_MAIN_LAG_META = 1398; // 32 -static const uint64_t SH_FLD_23_RXCAL_PD_MAIN_LEAD_META = 1399; // 32 -static const uint64_t SH_FLD_23_RXREG_COMPCON_DC = 1400; // 32 -static const uint64_t SH_FLD_23_RXREG_COMPCON_DC_LEN = 1401; // 32 -static const uint64_t SH_FLD_23_RXREG_CON_DC = 1402; // 32 -static const uint64_t SH_FLD_23_RXREG_DAC_PULLUP_DC = 1403; // 32 -static const uint64_t SH_FLD_23_RXREG_DRVCON_DC = 1404; // 32 -static const uint64_t SH_FLD_23_RXREG_DRVCON_DC_LEN = 1405; // 32 -static const uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC = 1406; // 32 -static const uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN = 1407; // 32 -static const uint64_t SH_FLD_23_RXREG_FINECAL_2XILSB_DC = 1408; // 32 -static const uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC = 1409; // 32 -static const uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1410; // 32 -static const uint64_t SH_FLD_23_RXREG_REF_SEL_DC = 1411; // 32 -static const uint64_t SH_FLD_23_RXREG_REF_SEL_DC_LEN = 1412; // 32 -static const uint64_t SH_FLD_23_S0ACENSLICENDRV_DC = 1413; // 16 -static const uint64_t SH_FLD_23_S0ACENSLICENDRV_DC_LEN = 1414; // 16 -static const uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC = 1415; // 16 -static const uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC_LEN = 1416; // 16 -static const uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC = 1417; // 16 -static const uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC_LEN = 1418; // 16 -static const uint64_t SH_FLD_23_S0INSDLYTAP = 1419; // 16 -static const uint64_t SH_FLD_23_S1ACENSLICENDRV_DC = 1420; // 16 -static const uint64_t SH_FLD_23_S1ACENSLICENDRV_DC_LEN = 1421; // 16 -static const uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC = 1422; // 16 -static const uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC_LEN = 1423; // 16 -static const uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC = 1424; // 16 -static const uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC_LEN = 1425; // 16 -static const uint64_t SH_FLD_23_S1INSDLYTAP = 1426; // 16 -static const uint64_t SH_FLD_23_SEL0 = 1427; // 32 -static const uint64_t SH_FLD_23_SEL0_LEN = 1428; // 16 -static const uint64_t SH_FLD_23_SEL1 = 1429; // 32 -static const uint64_t SH_FLD_23_SEL10 = 1430; // 32 -static const uint64_t SH_FLD_23_SEL10_LEN = 1431; // 32 -static const uint64_t SH_FLD_23_SEL11 = 1432; // 32 -static const uint64_t SH_FLD_23_SEL11_LEN = 1433; // 32 -static const uint64_t SH_FLD_23_SEL12 = 1434; // 32 -static const uint64_t SH_FLD_23_SEL12_LEN = 1435; // 32 -static const uint64_t SH_FLD_23_SEL13 = 1436; // 32 -static const uint64_t SH_FLD_23_SEL13_LEN = 1437; // 32 -static const uint64_t SH_FLD_23_SEL14 = 1438; // 32 -static const uint64_t SH_FLD_23_SEL14_LEN = 1439; // 32 -static const uint64_t SH_FLD_23_SEL15 = 1440; // 32 -static const uint64_t SH_FLD_23_SEL15_LEN = 1441; // 32 -static const uint64_t SH_FLD_23_SEL1_LEN = 1442; // 32 -static const uint64_t SH_FLD_23_SEL2 = 1443; // 32 -static const uint64_t SH_FLD_23_SEL2_LEN = 1444; // 32 -static const uint64_t SH_FLD_23_SEL3 = 1445; // 32 -static const uint64_t SH_FLD_23_SEL3_LEN = 1446; // 32 -static const uint64_t SH_FLD_23_SEL4 = 1447; // 32 -static const uint64_t SH_FLD_23_SEL4_LEN = 1448; // 32 -static const uint64_t SH_FLD_23_SEL5 = 1449; // 32 -static const uint64_t SH_FLD_23_SEL5_LEN = 1450; // 32 -static const uint64_t SH_FLD_23_SEL6 = 1451; // 32 -static const uint64_t SH_FLD_23_SEL6_LEN = 1452; // 32 -static const uint64_t SH_FLD_23_SEL7 = 1453; // 32 -static const uint64_t SH_FLD_23_SEL7_LEN = 1454; // 32 -static const uint64_t SH_FLD_23_SEL8 = 1455; // 32 -static const uint64_t SH_FLD_23_SEL8_LEN = 1456; // 16 -static const uint64_t SH_FLD_23_SEL9 = 1457; // 32 -static const uint64_t SH_FLD_23_SEL9_LEN = 1458; // 32 -static const uint64_t SH_FLD_23_SEL_A = 1459; // 16 -static const uint64_t SH_FLD_23_SEL_A_LEN = 1460; // 16 -static const uint64_t SH_FLD_23_SEL_B = 1461; // 16 -static const uint64_t SH_FLD_23_SEL_B_LEN = 1462; // 16 -static const uint64_t SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN = 1463; // 32 -static const uint64_t SH_FLD_23_SLAVE_VREG_DAC_COARSE = 1464; // 32 -static const uint64_t SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN = 1465; // 32 -static const uint64_t SH_FLD_23_SLAVE_VREG_OVERRIDE = 1466; // 32 -static const uint64_t SH_FLD_23_SLAVE_VREG_REF_SEL_DC = 1467; // 32 -static const uint64_t SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN = 1468; // 32 -static const uint64_t SH_FLD_23_SMALL_STEP_LEFT = 1469; // 16 -static const uint64_t SH_FLD_23_SMALL_STEP_RIGHT = 1470; // 16 -static const uint64_t SH_FLD_23_SPARE_OSC = 1471; // 3 -static const uint64_t SH_FLD_23_SPARE_PLL_CONTROL = 1472; // 3 -static const uint64_t SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL = 1473; // 3 -static const uint64_t SH_FLD_23_SPARE_TEST = 1474; // 3 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE = 1475; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR0 = 1476; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR1 = 1477; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR2 = 1478; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR3 = 1479; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK1 = 1480; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK2 = 1481; // 16 -static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK3 = 1482; // 16 -static const uint64_t SH_FLD_23_SYNC = 1483; // 16 -static const uint64_t SH_FLD_23_SYNC_LEN = 1484; // 16 -static const uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET = 1485; // 16 -static const uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN = 1486; // 16 -static const uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET = 1487; // 16 -static const uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN = 1488; // 16 -static const uint64_t SH_FLD_23_TEST_4TO1_MODE = 1489; // 16 -static const uint64_t SH_FLD_23_TEST_CHECK_EN = 1490; // 16 -static const uint64_t SH_FLD_23_TEST_CLEAR_ERROR = 1491; // 16 -static const uint64_t SH_FLD_23_TEST_DATA_EN = 1492; // 16 -static const uint64_t SH_FLD_23_TEST_GEN_EN = 1493; // 16 -static const uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL = 1494; // 16 -static const uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN = 1495; // 16 -static const uint64_t SH_FLD_23_TEST_MODE = 1496; // 16 -static const uint64_t SH_FLD_23_TEST_MODE_LEN = 1497; // 16 -static const uint64_t SH_FLD_23_TEST_RESET = 1498; // 16 -static const uint64_t SH_FLD_23_TRAILING_EDGE_FOUND_MASK = 1499; // 16 -static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND = 1500; // 16 -static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 = 1501; // 16 -static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1502; // 16 -static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 = 1503; // 16 -static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1504; // 16 -static const uint64_t SH_FLD_23_TRIG_PERIOD = 1505; // 16 -static const uint64_t SH_FLD_23_TSYS = 1506; // 16 -static const uint64_t SH_FLD_23_TSYS_LEN = 1507; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE = 1508; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 = 1509; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 = 1510; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 = 1511; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 = 1512; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 = 1513; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 = 1514; // 16 -static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 = 1515; // 16 -static const uint64_t SH_FLD_23_UPPER = 1516; // 32 -static const uint64_t SH_FLD_23_UPPER_LEN = 1517; // 32 -static const uint64_t SH_FLD_23_VALID_NS_BIG_L = 1518; // 16 -static const uint64_t SH_FLD_23_VALID_NS_BIG_L_MASK = 1519; // 16 -static const uint64_t SH_FLD_23_VALID_NS_BIG_R = 1520; // 16 -static const uint64_t SH_FLD_23_VALID_NS_BIG_R_MASK = 1521; // 16 -static const uint64_t SH_FLD_23_VALID_NS_JUMP_BACK = 1522; // 16 -static const uint64_t SH_FLD_23_VALID_NS_JUMP_BACK_MASK = 1523; // 16 -static const uint64_t SH_FLD_23_VALUE_DRAM0 = 1524; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM0_LEN = 1525; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM1 = 1526; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM1_LEN = 1527; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM2 = 1528; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM2_LEN = 1529; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM3 = 1530; // 64 -static const uint64_t SH_FLD_23_VALUE_DRAM3_LEN = 1531; // 64 -static const uint64_t SH_FLD_23_VREG_RXCAL_COMP_OUT_META = 1532; // 32 -static const uint64_t SH_FLD_23_VREG_SLAVE_COMP_OUT = 1533; // 32 -static const uint64_t SH_FLD_23_WL_ADVANCE_DISABLE = 1534; // 16 -static const uint64_t SH_FLD_23_WL_ERR_CLK16 = 1535; // 32 -static const uint64_t SH_FLD_23_WL_ERR_CLK16_MASK = 1536; // 16 -static const uint64_t SH_FLD_23_WL_ERR_CLK18 = 1537; // 32 -static const uint64_t SH_FLD_23_WL_ERR_CLK18_MASK = 1538; // 16 -static const uint64_t SH_FLD_23_WL_ERR_CLK20 = 1539; // 32 -static const uint64_t SH_FLD_23_WL_ERR_CLK20_MASK = 1540; // 16 -static const uint64_t SH_FLD_23_WL_ERR_CLK22 = 1541; // 32 -static const uint64_t SH_FLD_23_WRAPSEL = 1542; // 16 -static const uint64_t SH_FLD_23_WTRFL_AVE_DIS = 1543; // 16 -static const uint64_t SH_FLD_23_ZERO_DETECTED = 1544; // 16 -static const uint64_t SH_FLD_24 = 1545; // 6 -static const uint64_t SH_FLD_24_RESERVED = 1546; // 6 -static const uint64_t SH_FLD_24_SPARE_CBS_CONTROL = 1547; // 3 -static const uint64_t SH_FLD_24_SPARE_OSC = 1548; // 3 -static const uint64_t SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL = 1549; // 3 -static const uint64_t SH_FLD_25 = 1550; // 6 -static const uint64_t SH_FLD_256K = 1551; // 12 -static const uint64_t SH_FLD_25_SPARE_CBS_CONTROL = 1552; // 3 -static const uint64_t SH_FLD_25_SPARE_CLKIN_CONTROL = 1553; // 3 -static const uint64_t SH_FLD_25_SPARE_OSC = 1554; // 3 -static const uint64_t SH_FLD_25_SPARE_REFCLOCK_CONTROL = 1555; // 3 -static const uint64_t SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL = 1556; // 3 -static const uint64_t SH_FLD_26 = 1557; // 6 -static const uint64_t SH_FLD_26_FREE_USAGE = 1558; // 3 -static const uint64_t SH_FLD_26_SPARE_CBS_CONTROL = 1559; // 3 -static const uint64_t SH_FLD_26_SPARE_CLKIN_CONTROL = 1560; // 3 -static const uint64_t SH_FLD_26_SPARE_OSC = 1561; // 3 -static const uint64_t SH_FLD_26_SPARE_REFCLOCK_CONTROL = 1562; // 3 -static const uint64_t SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL = 1563; // 3 -static const uint64_t SH_FLD_27 = 1564; // 6 -static const uint64_t SH_FLD_27_FREE_USAGE = 1565; // 3 -static const uint64_t SH_FLD_27_SPARE_CBS_CONTROL = 1566; // 3 -static const uint64_t SH_FLD_27_SPARE_CLKIN_CONTROL = 1567; // 3 -static const uint64_t SH_FLD_27_SPARE_OSC = 1568; // 3 -static const uint64_t SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL = 1569; // 3 -static const uint64_t SH_FLD_28 = 1570; // 6 -static const uint64_t SH_FLD_28_FREE_USAGE = 1571; // 3 -static const uint64_t SH_FLD_28_RESERVED_FOR_HTB = 1572; // 3 -static const uint64_t SH_FLD_28_SPARE_OSC = 1573; // 3 -static const uint64_t SH_FLD_28_SPARE_RESET = 1574; // 3 -static const uint64_t SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL = 1575; // 3 -static const uint64_t SH_FLD_28_SPARE_TEST_CONTROL = 1576; // 3 -static const uint64_t SH_FLD_29 = 1577; // 6 -static const uint64_t SH_FLD_29_FREE_USAGE = 1578; // 3 -static const uint64_t SH_FLD_29_RESERVED_FOR_HTB = 1579; // 3 -static const uint64_t SH_FLD_29_SPARE_OSC = 1580; // 3 -static const uint64_t SH_FLD_29_SPARE_REFCLOCK_CONTROL = 1581; // 3 -static const uint64_t SH_FLD_29_SPARE_RESET = 1582; // 3 -static const uint64_t SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL = 1583; // 3 -static const uint64_t SH_FLD_29_SPARE_TEST_CONTROL = 1584; // 3 -static const uint64_t SH_FLD_2_CANNED_0 = 1585; // 2 -static const uint64_t SH_FLD_2_CANNED_0_LEN = 1586; // 2 -static const uint64_t SH_FLD_2_CANNED_1 = 1587; // 2 -static const uint64_t SH_FLD_2_CANNED_1_LEN = 1588; // 2 -static const uint64_t SH_FLD_2_DATA = 1589; // 1 -static const uint64_t SH_FLD_2_DATA_LEN = 1590; // 1 -static const uint64_t SH_FLD_2_LEN = 1591; // 46 -static const uint64_t SH_FLD_2_RESERVED = 1592; // 3 -static const uint64_t SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL = 1593; // 3 -static const uint64_t SH_FLD_3 = 1594; // 466 -static const uint64_t SH_FLD_30 = 1595; // 6 -static const uint64_t SH_FLD_30_RESERVED = 1596; // 3 -static const uint64_t SH_FLD_30_RESERVED_FOR_HTB = 1597; // 3 -static const uint64_t SH_FLD_30_SPARE_OSC = 1598; // 3 -static const uint64_t SH_FLD_30_SPARE_REFCLOCK_CONTROL = 1599; // 3 -static const uint64_t SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL = 1600; // 3 -static const uint64_t SH_FLD_30_SPARE_TEST_CONTROL = 1601; // 3 -static const uint64_t SH_FLD_31 = 1602; // 6 -static const uint64_t SH_FLD_31_RESERVED_FOR_HTB = 1603; // 3 -static const uint64_t SH_FLD_31_SPARE_OSC = 1604; // 3 -static const uint64_t SH_FLD_31_SPARE_REFCLOCK_CONTROL = 1605; // 3 -static const uint64_t SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL = 1606; // 3 -static const uint64_t SH_FLD_31_SPARE_TEST_CONTROL = 1607; // 3 -static const uint64_t SH_FLD_3_DATA = 1608; // 1 -static const uint64_t SH_FLD_3_DATA_LEN = 1609; // 1 -static const uint64_t SH_FLD_3_LEN = 1610; // 46 -static const uint64_t SH_FLD_3_RESERVED = 1611; // 3 -static const uint64_t SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL = 1612; // 3 -static const uint64_t SH_FLD_3_SPARE_SS_PLL_CONTROL = 1613; // 3 -static const uint64_t SH_FLD_4 = 1614; // 520 -static const uint64_t SH_FLD_4X4_MODE = 1615; // 2 -static const uint64_t SH_FLD_4_1D_EYE_NOISE = 1616; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR0 = 1617; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR1 = 1618; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR2 = 1619; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR3 = 1620; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK1 = 1621; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK2 = 1622; // 8 -static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK3 = 1623; // 8 -static const uint64_t SH_FLD_4_ADVANCE_PING_PONG = 1624; // 8 -static const uint64_t SH_FLD_4_ADVANCE_PR_VALUE = 1625; // 8 -static const uint64_t SH_FLD_4_ATESTSEL_0 = 1626; // 8 -static const uint64_t SH_FLD_4_ATESTSEL_0_LEN = 1627; // 8 -static const uint64_t SH_FLD_4_ATEST_SEL_0_1 = 1628; // 8 -static const uint64_t SH_FLD_4_ATEST_SEL_0_1_LEN = 1629; // 8 -static const uint64_t SH_FLD_4_BAD_BIT = 1630; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_ERR0 = 1631; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_ERR1 = 1632; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_ERR2 = 1633; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_ERR3 = 1634; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_MASK1 = 1635; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_MASK2 = 1636; // 8 -static const uint64_t SH_FLD_4_BAD_BIT_MASK3 = 1637; // 8 -static const uint64_t SH_FLD_4_BB_LOCK0 = 1638; // 8 -static const uint64_t SH_FLD_4_BB_LOCK1 = 1639; // 8 -static const uint64_t SH_FLD_4_BIG_STEP_RIGHT = 1640; // 8 -static const uint64_t SH_FLD_4_BIT_CENTERED = 1641; // 8 -static const uint64_t SH_FLD_4_BIT_CENTERED_LEN = 1642; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA = 1643; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR0 = 1644; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR1 = 1645; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR2 = 1646; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR3 = 1647; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK1 = 1648; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK2 = 1649; // 8 -static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK3 = 1650; // 8 -static const uint64_t SH_FLD_4_BLFIFO_DIS = 1651; // 8 -static const uint64_t SH_FLD_4_BUMP = 1652; // 8 -static const uint64_t SH_FLD_4_CALGATE_ON = 1653; // 8 -static const uint64_t SH_FLD_4_CALIBRATE_BIT = 1654; // 8 -static const uint64_t SH_FLD_4_CALIBRATE_BIT_LEN = 1655; // 8 -static const uint64_t SH_FLD_4_CAL_CKTS_ACTIVE = 1656; // 16 -static const uint64_t SH_FLD_4_CAL_ERROR = 1657; // 16 -static const uint64_t SH_FLD_4_CAL_ERROR_FINE = 1658; // 16 -static const uint64_t SH_FLD_4_CAL_GOOD = 1659; // 16 -static const uint64_t SH_FLD_4_CAL_PD_ENABLE = 1660; // 16 -static const uint64_t SH_FLD_4_CHECKER_ENABLE = 1661; // 8 -static const uint64_t SH_FLD_4_CHECKER_RESET = 1662; // 8 -static const uint64_t SH_FLD_4_CHICKSW_HW278227 = 1663; // 8 -static const uint64_t SH_FLD_4_CLK16_SINGLE_ENDED = 1664; // 32 -static const uint64_t SH_FLD_4_CLK18_SINGLE_ENDED = 1665; // 32 -static const uint64_t SH_FLD_4_CLK20_SINGLE_ENDED = 1666; // 32 -static const uint64_t SH_FLD_4_CLK22_SINGLE_ENDED = 1667; // 32 -static const uint64_t SH_FLD_4_CLK_LEVEL = 1668; // 8 -static const uint64_t SH_FLD_4_CLK_LEVEL_LEN = 1669; // 8 -static const uint64_t SH_FLD_4_CNTL_POL = 1670; // 8 -static const uint64_t SH_FLD_4_CNTL_SRC = 1671; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0 = 1672; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK = 1673; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1 = 1674; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK = 1675; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2 = 1676; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK = 1677; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3 = 1678; // 8 -static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK = 1679; // 8 -static const uint64_t SH_FLD_4_CONTINUOUS_UPDATE = 1680; // 16 -static const uint64_t SH_FLD_4_CTR_1D_CHICKEN_SWITCH = 1681; // 8 -static const uint64_t SH_FLD_4_CTR_2D_BIG_STEP_VAL = 1682; // 8 -static const uint64_t SH_FLD_4_CTR_2D_BIG_STEP_VAL_LEN = 1683; // 8 -static const uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL = 1684; // 8 -static const uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL_LEN = 1685; // 8 -static const uint64_t SH_FLD_4_CTR_CUR = 1686; // 8 -static const uint64_t SH_FLD_4_CTR_CUR_LEN = 1687; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP = 1688; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP_LEN = 1689; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP = 1690; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP_LEN = 1691; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT = 1692; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT_LEN = 1693; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT = 1694; // 8 -static const uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT_LEN = 1695; // 8 -static const uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER = 1696; // 8 -static const uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER_LEN = 1697; // 8 -static const uint64_t SH_FLD_4_CTR_RANGE_SELECT = 1698; // 8 -static const uint64_t SH_FLD_4_CTR_RUN_FULL_1D = 1699; // 8 -static const uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX = 1700; // 8 -static const uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN = 1701; // 8 -static const uint64_t SH_FLD_4_DD2_DQS_FIX_DIS = 1702; // 8 -static const uint64_t SH_FLD_4_DD2_FIX_DIS = 1703; // 8 -static const uint64_t SH_FLD_4_DD2_WTRFL_SYNC_DIS = 1704; // 8 -static const uint64_t SH_FLD_4_DELAYG = 1705; // 608 -static const uint64_t SH_FLD_4_DELAYG_LEN = 1706; // 608 -static const uint64_t SH_FLD_4_DELAY_PING_PONG_HALF = 1707; // 8 -static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 1708; // 8 -static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1709; // 8 -static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW = 1710; // 8 -static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1711; // 8 -static const uint64_t SH_FLD_4_DETECT_REQ = 1712; // 16 -static const uint64_t SH_FLD_4_DFT_FORCE_OUTPUTS = 1713; // 8 -static const uint64_t SH_FLD_4_DFT_PRBS7_GEN_EN = 1714; // 8 -static const uint64_t SH_FLD_4_DIGITAL_EN = 1715; // 8 -static const uint64_t SH_FLD_4_DIR_0_15 = 1716; // 8 -static const uint64_t SH_FLD_4_DIR_0_15_LEN = 1717; // 8 -static const uint64_t SH_FLD_4_DISABLE_0_15 = 1718; // 32 -static const uint64_t SH_FLD_4_DISABLE_0_15_LEN = 1719; // 32 -static const uint64_t SH_FLD_4_DISABLE_16_23 = 1720; // 32 -static const uint64_t SH_FLD_4_DISABLE_16_23_LEN = 1721; // 32 -static const uint64_t SH_FLD_4_DISABLE_PING_PONG = 1722; // 8 -static const uint64_t SH_FLD_4_DISABLE_TERMINATION = 1723; // 8 -static const uint64_t SH_FLD_4_DIS_CLK_GATE = 1724; // 8 -static const uint64_t SH_FLD_4_DLL_ADJUST = 1725; // 16 -static const uint64_t SH_FLD_4_DLL_ADJUST_LEN = 1726; // 16 -static const uint64_t SH_FLD_4_DLL_COMPARE_OUT = 1727; // 16 -static const uint64_t SH_FLD_4_DLL_CORRECT_EN = 1728; // 16 -static const uint64_t SH_FLD_4_DLL_ITER_A = 1729; // 16 -static const uint64_t SH_FLD_4_DL_FORCE_ON = 1730; // 8 -static const uint64_t SH_FLD_4_DONE = 1731; // 16 -static const uint64_t SH_FLD_4_DQS = 1732; // 8 -static const uint64_t SH_FLD_4_DQSCLK_SELECT0 = 1733; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT0_LEN = 1734; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT1 = 1735; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT1_LEN = 1736; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT2 = 1737; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT2_LEN = 1738; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT3 = 1739; // 32 -static const uint64_t SH_FLD_4_DQSCLK_SELECT3_LEN = 1740; // 32 -static const uint64_t SH_FLD_4_DQS_ALIGN_CNTR = 1741; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_CNTR_LEN = 1742; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_FIX_DIS = 1743; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_JITTER = 1744; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_QUAD = 1745; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_QUAD_LEN = 1746; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_SM = 1747; // 8 -static const uint64_t SH_FLD_4_DQS_ALIGN_SM_LEN = 1748; // 8 -static const uint64_t SH_FLD_4_DQS_LEN = 1749; // 8 -static const uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS = 1750; // 8 -static const uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS_LEN = 1751; // 8 -static const uint64_t SH_FLD_4_DQS_QUAD_CONFIG = 1752; // 8 -static const uint64_t SH_FLD_4_DQS_QUAD_CONFIG_LEN = 1753; // 8 -static const uint64_t SH_FLD_4_DRIFT_ERROR = 1754; // 8 -static const uint64_t SH_FLD_4_DRIFT_MASK = 1755; // 8 -static const uint64_t SH_FLD_4_DRVREN_MODE = 1756; // 16 -static const uint64_t SH_FLD_4_DYN_MCTERM_CNTL_EN = 1757; // 8 -static const uint64_t SH_FLD_4_DYN_POWER_CNTL_EN = 1758; // 8 -static const uint64_t SH_FLD_4_DYN_RX_GATE_CNTL_EN = 1759; // 8 -static const uint64_t SH_FLD_4_ENABLE_0_15 = 1760; // 8 -static const uint64_t SH_FLD_4_ENABLE_0_15_LEN = 1761; // 8 -static const uint64_t SH_FLD_4_ENABLE_16_23 = 1762; // 8 -static const uint64_t SH_FLD_4_ENABLE_16_23_LEN = 1763; // 8 -static const uint64_t SH_FLD_4_EN_DQS_OFFSET = 1764; // 8 -static const uint64_t SH_FLD_4_EN_DRIVER_INVFB_DC = 1765; // 16 -static const uint64_t SH_FLD_4_EN_N_WR = 1766; // 8 -static const uint64_t SH_FLD_4_EN_N_WR_LEN = 1767; // 8 -static const uint64_t SH_FLD_4_EN_P_WR = 1768; // 16 -static const uint64_t SH_FLD_4_EN_P_WR_LEN = 1769; // 16 -static const uint64_t SH_FLD_4_ERROR = 1770; // 8 -static const uint64_t SH_FLD_4_ERROR_LEN = 1771; // 8 -static const uint64_t SH_FLD_4_ERR_CLK22_MASK = 1772; // 8 -static const uint64_t SH_FLD_4_EYE_CLIPPING = 1773; // 8 -static const uint64_t SH_FLD_4_EYE_CLIPPING_MASK = 1774; // 8 -static const uint64_t SH_FLD_4_FINE_STEPPING = 1775; // 8 -static const uint64_t SH_FLD_4_FLUSH = 1776; // 8 -static const uint64_t SH_FLD_4_FORCE_DQS_LANES_ON = 1777; // 8 -static const uint64_t SH_FLD_4_FORCE_FIFO_CAPTURE = 1778; // 8 -static const uint64_t SH_FLD_4_FW_LEFT_SIDE = 1779; // 8 -static const uint64_t SH_FLD_4_FW_LEFT_SIDE_LEN = 1780; // 8 -static const uint64_t SH_FLD_4_FW_RIGHT_SIDE = 1781; // 8 -static const uint64_t SH_FLD_4_FW_RIGHT_SIDE_LEN = 1782; // 8 -static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3 = 1783; // 8 -static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3_LEN = 1784; // 8 -static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3 = 1785; // 8 -static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3_LEN = 1786; // 8 -static const uint64_t SH_FLD_4_HS_PROBE_A = 1787; // 8 -static const uint64_t SH_FLD_4_HS_PROBE_A_LEN = 1788; // 8 -static const uint64_t SH_FLD_4_HS_PROBE_B = 1789; // 8 -static const uint64_t SH_FLD_4_HS_PROBE_B_LEN = 1790; // 8 -static const uint64_t SH_FLD_4_HW_VALUE = 1791; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N0 = 1792; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N0_MASK = 1793; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N1 = 1794; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N1_MASK = 1795; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N2 = 1796; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N2_MASK = 1797; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N3 = 1798; // 8 -static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N3_MASK = 1799; // 8 -static const uint64_t SH_FLD_4_INIT_IO = 1800; // 8 -static const uint64_t SH_FLD_4_INIT_RXDLL_CAL_RESET = 1801; // 16 -static const uint64_t SH_FLD_4_INIT_RXDLL_CAL_UPDATE = 1802; // 16 -static const uint64_t SH_FLD_4_INTERP_SIG_SLEW = 1803; // 8 -static const uint64_t SH_FLD_4_INTERP_SIG_SLEW_LEN = 1804; // 8 -static const uint64_t SH_FLD_4_INVALID_NS_BIG_R = 1805; // 8 -static const uint64_t SH_FLD_4_INVALID_NS_BIG_R_MASK = 1806; // 8 -static const uint64_t SH_FLD_4_INVALID_NS_SMALL_L = 1807; // 8 -static const uint64_t SH_FLD_4_INVALID_NS_SMALL_L_MASK = 1808; // 8 -static const uint64_t SH_FLD_4_INVALID_NS_SMALL_R = 1809; // 8 -static const uint64_t SH_FLD_4_INVALID_NS_SMALL_R_MASK = 1810; // 8 -static const uint64_t SH_FLD_4_ITERATION_CNTR = 1811; // 8 -static const uint64_t SH_FLD_4_ITERATION_CNTR_LEN = 1812; // 8 -static const uint64_t SH_FLD_4_JUMP_BACK_RIGHT = 1813; // 8 -static const uint64_t SH_FLD_4_LEADING_EDGE_FOUND_MASK = 1814; // 8 -static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND = 1815; // 8 -static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 = 1816; // 8 -static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1817; // 8 -static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 = 1818; // 8 -static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1819; // 8 -static const uint64_t SH_FLD_4_LEN = 1820; // 100 -static const uint64_t SH_FLD_4_LOOPBACK_DLY12 = 1821; // 8 -static const uint64_t SH_FLD_4_LOOPBACK_FIX_EN = 1822; // 8 -static const uint64_t SH_FLD_4_LOWER = 1823; // 16 -static const uint64_t SH_FLD_4_LOWER_LEN = 1824; // 16 -static const uint64_t SH_FLD_4_MAIN_PD_ENABLE = 1825; // 16 -static const uint64_t SH_FLD_4_MATCH_STEP_RIGHT = 1826; // 8 -static const uint64_t SH_FLD_4_MAX_DQS = 1827; // 8 -static const uint64_t SH_FLD_4_MAX_DQS_ITER = 1828; // 8 -static const uint64_t SH_FLD_4_MAX_DQS_LEN = 1829; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE = 1830; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_ERR0 = 1831; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_ERR1 = 1832; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_ERR2 = 1833; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_ERR3 = 1834; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_MASK1 = 1835; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_MASK2 = 1836; // 8 -static const uint64_t SH_FLD_4_MAX_RANGE_MASK3 = 1837; // 8 -static const uint64_t SH_FLD_4_MEMINTD00 = 1838; // 8 -static const uint64_t SH_FLD_4_MEMINTD00_LEN = 1839; // 8 -static const uint64_t SH_FLD_4_MEMINTD01 = 1840; // 8 -static const uint64_t SH_FLD_4_MEMINTD01_LEN = 1841; // 8 -static const uint64_t SH_FLD_4_MEMINTD02 = 1842; // 8 -static const uint64_t SH_FLD_4_MEMINTD02_LEN = 1843; // 8 -static const uint64_t SH_FLD_4_MEMINTD03 = 1844; // 8 -static const uint64_t SH_FLD_4_MEMINTD03_LEN = 1845; // 8 -static const uint64_t SH_FLD_4_MEMINTD04 = 1846; // 8 -static const uint64_t SH_FLD_4_MEMINTD04_LEN = 1847; // 8 -static const uint64_t SH_FLD_4_MEMINTD05 = 1848; // 8 -static const uint64_t SH_FLD_4_MEMINTD05_LEN = 1849; // 8 -static const uint64_t SH_FLD_4_MEMINTD06 = 1850; // 8 -static const uint64_t SH_FLD_4_MEMINTD06_LEN = 1851; // 8 -static const uint64_t SH_FLD_4_MEMINTD07 = 1852; // 8 -static const uint64_t SH_FLD_4_MEMINTD07_LEN = 1853; // 8 -static const uint64_t SH_FLD_4_MEMINTD08 = 1854; // 8 -static const uint64_t SH_FLD_4_MEMINTD08_LEN = 1855; // 8 -static const uint64_t SH_FLD_4_MEMINTD09 = 1856; // 8 -static const uint64_t SH_FLD_4_MEMINTD09_LEN = 1857; // 8 -static const uint64_t SH_FLD_4_MEMINTD10 = 1858; // 8 -static const uint64_t SH_FLD_4_MEMINTD10_LEN = 1859; // 8 -static const uint64_t SH_FLD_4_MEMINTD11 = 1860; // 8 -static const uint64_t SH_FLD_4_MEMINTD11_LEN = 1861; // 8 -static const uint64_t SH_FLD_4_MEMINTD12 = 1862; // 8 -static const uint64_t SH_FLD_4_MEMINTD12_LEN = 1863; // 8 -static const uint64_t SH_FLD_4_MEMINTD13 = 1864; // 8 -static const uint64_t SH_FLD_4_MEMINTD13_LEN = 1865; // 8 -static const uint64_t SH_FLD_4_MEMINTD14 = 1866; // 8 -static const uint64_t SH_FLD_4_MEMINTD14_LEN = 1867; // 8 -static const uint64_t SH_FLD_4_MEMINTD15 = 1868; // 8 -static const uint64_t SH_FLD_4_MEMINTD15_LEN = 1869; // 8 -static const uint64_t SH_FLD_4_MEMINTD16 = 1870; // 8 -static const uint64_t SH_FLD_4_MEMINTD16_LEN = 1871; // 8 -static const uint64_t SH_FLD_4_MEMINTD17 = 1872; // 8 -static const uint64_t SH_FLD_4_MEMINTD17_LEN = 1873; // 8 -static const uint64_t SH_FLD_4_MEMINTD18 = 1874; // 8 -static const uint64_t SH_FLD_4_MEMINTD18_LEN = 1875; // 8 -static const uint64_t SH_FLD_4_MEMINTD19 = 1876; // 8 -static const uint64_t SH_FLD_4_MEMINTD19_LEN = 1877; // 8 -static const uint64_t SH_FLD_4_MEMINTD20 = 1878; // 8 -static const uint64_t SH_FLD_4_MEMINTD20_LEN = 1879; // 8 -static const uint64_t SH_FLD_4_MEMINTD21 = 1880; // 8 -static const uint64_t SH_FLD_4_MEMINTD21_LEN = 1881; // 8 -static const uint64_t SH_FLD_4_MEMINTD22 = 1882; // 8 -static const uint64_t SH_FLD_4_MEMINTD22_LEN = 1883; // 8 -static const uint64_t SH_FLD_4_MEMINTD23 = 1884; // 8 -static const uint64_t SH_FLD_4_MEMINTD23_LEN = 1885; // 8 -static const uint64_t SH_FLD_4_MIN_EYE = 1886; // 8 -static const uint64_t SH_FLD_4_MIN_EYE_MASK = 1887; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE = 1888; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_ERR0 = 1889; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_ERR1 = 1890; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_ERR2 = 1891; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_ERR3 = 1892; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_MASK1 = 1893; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_MASK2 = 1894; // 8 -static const uint64_t SH_FLD_4_MIN_RANGE_MASK3 = 1895; // 8 -static const uint64_t SH_FLD_4_MIN_RD_EYE_SIZE = 1896; // 8 -static const uint64_t SH_FLD_4_MIN_RD_EYE_SIZE_LEN = 1897; // 8 -static const uint64_t SH_FLD_4_MRS_CMD_N0 = 1898; // 8 -static const uint64_t SH_FLD_4_MRS_CMD_N1 = 1899; // 8 -static const uint64_t SH_FLD_4_MRS_CMD_N2 = 1900; // 8 -static const uint64_t SH_FLD_4_MRS_CMD_N3 = 1901; // 8 -static const uint64_t SH_FLD_4_N0 = 1902; // 64 -static const uint64_t SH_FLD_4_N0_LEN = 1903; // 64 -static const uint64_t SH_FLD_4_N1 = 1904; // 64 -static const uint64_t SH_FLD_4_N1_LEN = 1905; // 64 -static const uint64_t SH_FLD_4_N2 = 1906; // 64 -static const uint64_t SH_FLD_4_N2_LEN = 1907; // 64 -static const uint64_t SH_FLD_4_N3 = 1908; // 64 -static const uint64_t SH_FLD_4_N3_LEN = 1909; // 64 -static const uint64_t SH_FLD_4_NIB0 = 1910; // 8 -static const uint64_t SH_FLD_4_NIB0TCFLIP_DC = 1911; // 8 -static const uint64_t SH_FLD_4_NIB0_EN_FORCE = 1912; // 8 -static const uint64_t SH_FLD_4_NIB0_LEN = 1913; // 8 -static const uint64_t SH_FLD_4_NIB1 = 1914; // 8 -static const uint64_t SH_FLD_4_NIB1TCFLIP_DC = 1915; // 8 -static const uint64_t SH_FLD_4_NIB1_EN_FORCE = 1916; // 8 -static const uint64_t SH_FLD_4_NIB1_LEN = 1917; // 8 -static const uint64_t SH_FLD_4_NIB2 = 1918; // 8 -static const uint64_t SH_FLD_4_NIB2TCFLIP_DC = 1919; // 8 -static const uint64_t SH_FLD_4_NIB2_EN_FORCE = 1920; // 8 -static const uint64_t SH_FLD_4_NIB2_LEN = 1921; // 8 -static const uint64_t SH_FLD_4_NIB3 = 1922; // 8 -static const uint64_t SH_FLD_4_NIB3TCFLIP_DC = 1923; // 8 -static const uint64_t SH_FLD_4_NIB3_EN_FORCE = 1924; // 8 -static const uint64_t SH_FLD_4_NIB3_LEN = 1925; // 8 -static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP = 1926; // 16 -static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN = 1927; // 16 -static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES = 1928; // 16 -static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES_LEN = 1929; // 16 -static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP = 1930; // 16 -static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN = 1931; // 16 -static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES = 1932; // 16 -static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES_LEN = 1933; // 16 -static const uint64_t SH_FLD_4_NO_DQS = 1934; // 8 -static const uint64_t SH_FLD_4_NO_DQS_MASK = 1935; // 8 -static const uint64_t SH_FLD_4_NO_EYE_DETECTED = 1936; // 8 -static const uint64_t SH_FLD_4_NO_EYE_DETECTED_MASK = 1937; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE = 1938; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_ERR0 = 1939; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_ERR1 = 1940; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_ERR2 = 1941; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_ERR3 = 1942; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_MASK1 = 1943; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_MASK2 = 1944; // 8 -static const uint64_t SH_FLD_4_NO_INCREASE_MASK3 = 1945; // 8 -static const uint64_t SH_FLD_4_NO_LOCK = 1946; // 8 -static const uint64_t SH_FLD_4_NO_LOCK_MASK = 1947; // 8 -static const uint64_t SH_FLD_4_OFFSET0 = 1948; // 8 -static const uint64_t SH_FLD_4_OFFSET0_LEN = 1949; // 8 -static const uint64_t SH_FLD_4_OFFSET1 = 1950; // 8 -static const uint64_t SH_FLD_4_OFFSET1_LEN = 1951; // 8 -static const uint64_t SH_FLD_4_OFFSET2 = 1952; // 16 -static const uint64_t SH_FLD_4_OFFSET2_LEN = 1953; // 16 -static const uint64_t SH_FLD_4_OFFSET3 = 1954; // 16 -static const uint64_t SH_FLD_4_OFFSET3_LEN = 1955; // 16 -static const uint64_t SH_FLD_4_OFFSET4 = 1956; // 16 -static const uint64_t SH_FLD_4_OFFSET4_LEN = 1957; // 16 -static const uint64_t SH_FLD_4_OFFSET5 = 1958; // 16 -static const uint64_t SH_FLD_4_OFFSET5_LEN = 1959; // 16 -static const uint64_t SH_FLD_4_OFFSET6 = 1960; // 16 -static const uint64_t SH_FLD_4_OFFSET6_LEN = 1961; // 16 -static const uint64_t SH_FLD_4_OFFSET7 = 1962; // 16 -static const uint64_t SH_FLD_4_OFFSET7_LEN = 1963; // 16 -static const uint64_t SH_FLD_4_OFFSET_ERR = 1964; // 8 -static const uint64_t SH_FLD_4_OFFSET_ERR_MASK = 1965; // 8 -static const uint64_t SH_FLD_4_OPERATE_MODE = 1966; // 8 -static const uint64_t SH_FLD_4_OPERATE_MODE_LEN = 1967; // 8 -static const uint64_t SH_FLD_4_OVERRIDE = 1968; // 16 -static const uint64_t SH_FLD_4_PERCAL_PWR_DIS = 1969; // 8 -static const uint64_t SH_FLD_4_PER_CAL_UPDATE_DISABLE = 1970; // 8 -static const uint64_t SH_FLD_4_PHASE_ALIGN_RESET = 1971; // 16 -static const uint64_t SH_FLD_4_PHASE_CNTL_EN = 1972; // 16 -static const uint64_t SH_FLD_4_PHASE_DEFAULT_EN = 1973; // 16 -static const uint64_t SH_FLD_4_POS_EDGE_ALIGN = 1974; // 16 -static const uint64_t SH_FLD_4_QUAD0 = 1975; // 8 -static const uint64_t SH_FLD_4_QUAD0_CLK16 = 1976; // 64 -static const uint64_t SH_FLD_4_QUAD0_CLK18 = 1977; // 64 -static const uint64_t SH_FLD_4_QUAD0_LEN = 1978; // 8 -static const uint64_t SH_FLD_4_QUAD1 = 1979; // 8 -static const uint64_t SH_FLD_4_QUAD1_CLK16 = 1980; // 64 -static const uint64_t SH_FLD_4_QUAD1_CLK18 = 1981; // 64 -static const uint64_t SH_FLD_4_QUAD1_LEN = 1982; // 8 -static const uint64_t SH_FLD_4_QUAD2 = 1983; // 8 -static const uint64_t SH_FLD_4_QUAD2_CLK16 = 1984; // 32 -static const uint64_t SH_FLD_4_QUAD2_CLK18 = 1985; // 32 -static const uint64_t SH_FLD_4_QUAD2_CLK20 = 1986; // 64 -static const uint64_t SH_FLD_4_QUAD2_CLK22 = 1987; // 64 -static const uint64_t SH_FLD_4_QUAD2_LEN = 1988; // 8 -static const uint64_t SH_FLD_4_QUAD3 = 1989; // 8 -static const uint64_t SH_FLD_4_QUAD3_CLK16 = 1990; // 32 -static const uint64_t SH_FLD_4_QUAD3_CLK18 = 1991; // 32 -static const uint64_t SH_FLD_4_QUAD3_CLK20 = 1992; // 64 -static const uint64_t SH_FLD_4_QUAD3_CLK22 = 1993; // 64 -static const uint64_t SH_FLD_4_QUAD3_LEN = 1994; // 8 -static const uint64_t SH_FLD_4_RANGE_DRAM0 = 1995; // 32 -static const uint64_t SH_FLD_4_RANGE_DRAM1 = 1996; // 32 -static const uint64_t SH_FLD_4_RANGE_DRAM2 = 1997; // 32 -static const uint64_t SH_FLD_4_RANGE_DRAM3 = 1998; // 32 -static const uint64_t SH_FLD_4_RD = 1999; // 136 -static const uint64_t SH_FLD_4_RDCLK_SELECT0 = 2000; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT0_LEN = 2001; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT1 = 2002; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT1_LEN = 2003; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT2 = 2004; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT2_LEN = 2005; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT3 = 2006; // 32 -static const uint64_t SH_FLD_4_RDCLK_SELECT3_LEN = 2007; // 32 -static const uint64_t SH_FLD_4_RD_DELAY0 = 2008; // 56 -static const uint64_t SH_FLD_4_RD_DELAY0_LEN = 2009; // 56 -static const uint64_t SH_FLD_4_RD_DELAY1 = 2010; // 56 -static const uint64_t SH_FLD_4_RD_DELAY1_LEN = 2011; // 56 -static const uint64_t SH_FLD_4_RD_DELAY2 = 2012; // 56 -static const uint64_t SH_FLD_4_RD_DELAY2_LEN = 2013; // 56 -static const uint64_t SH_FLD_4_RD_DELAY3 = 2014; // 56 -static const uint64_t SH_FLD_4_RD_DELAY3_LEN = 2015; // 56 -static const uint64_t SH_FLD_4_RD_DELAY4 = 2016; // 56 -static const uint64_t SH_FLD_4_RD_DELAY4_LEN = 2017; // 56 -static const uint64_t SH_FLD_4_RD_DELAY5 = 2018; // 56 -static const uint64_t SH_FLD_4_RD_DELAY5_LEN = 2019; // 56 -static const uint64_t SH_FLD_4_RD_DELAY6 = 2020; // 56 -static const uint64_t SH_FLD_4_RD_DELAY6_LEN = 2021; // 56 -static const uint64_t SH_FLD_4_RD_DELAY7 = 2022; // 56 -static const uint64_t SH_FLD_4_RD_DELAY7_LEN = 2023; // 56 -static const uint64_t SH_FLD_4_RD_LEN = 2024; // 136 -static const uint64_t SH_FLD_4_RD_SIZE0 = 2025; // 88 -static const uint64_t SH_FLD_4_RD_SIZE0_LEN = 2026; // 88 -static const uint64_t SH_FLD_4_RD_SIZE1 = 2027; // 88 -static const uint64_t SH_FLD_4_RD_SIZE1_LEN = 2028; // 88 -static const uint64_t SH_FLD_4_RD_SIZE2 = 2029; // 88 -static const uint64_t SH_FLD_4_RD_SIZE2_LEN = 2030; // 88 -static const uint64_t SH_FLD_4_RD_SIZE3 = 2031; // 88 -static const uint64_t SH_FLD_4_RD_SIZE3_LEN = 2032; // 88 -static const uint64_t SH_FLD_4_RD_SIZE4 = 2033; // 88 -static const uint64_t SH_FLD_4_RD_SIZE4_LEN = 2034; // 88 -static const uint64_t SH_FLD_4_RD_SIZE5 = 2035; // 88 -static const uint64_t SH_FLD_4_RD_SIZE5_LEN = 2036; // 88 -static const uint64_t SH_FLD_4_RD_SIZE6 = 2037; // 88 -static const uint64_t SH_FLD_4_RD_SIZE6_LEN = 2038; // 88 -static const uint64_t SH_FLD_4_RD_SIZE7 = 2039; // 88 -static const uint64_t SH_FLD_4_RD_SIZE7_LEN = 2040; // 88 -static const uint64_t SH_FLD_4_READ_CENTERING_MODE = 2041; // 8 -static const uint64_t SH_FLD_4_READ_CENTERING_MODE_LEN = 2042; // 8 -static const uint64_t SH_FLD_4_REFERENCE1 = 2043; // 8 -static const uint64_t SH_FLD_4_REFERENCE1_LEN = 2044; // 8 -static const uint64_t SH_FLD_4_REFERENCE2 = 2045; // 8 -static const uint64_t SH_FLD_4_REFERENCE2_LEN = 2046; // 8 -static const uint64_t SH_FLD_4_REFERENCE3 = 2047; // 8 -static const uint64_t SH_FLD_4_REFERENCE3_LEN = 2048; // 8 -static const uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP = 2049; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN = 2050; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 = 2051; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN = 2052; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN = 2053; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE = 2054; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN = 2055; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER = 2056; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN = 2057; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER = 2058; // 16 -static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN = 2059; // 16 -static const uint64_t SH_FLD_4_RESERVED = 2060; // 3 -static const uint64_t SH_FLD_4_ROT0 = 2061; // 8 -static const uint64_t SH_FLD_4_ROT0_LEN = 2062; // 8 -static const uint64_t SH_FLD_4_ROT1 = 2063; // 8 -static const uint64_t SH_FLD_4_ROT1_LEN = 2064; // 8 -static const uint64_t SH_FLD_4_ROT_CLK_N0 = 2065; // 64 -static const uint64_t SH_FLD_4_ROT_CLK_N0_LEN = 2066; // 64 -static const uint64_t SH_FLD_4_ROT_CLK_N1 = 2067; // 64 -static const uint64_t SH_FLD_4_ROT_CLK_N1_LEN = 2068; // 64 -static const uint64_t SH_FLD_4_ROT_N0 = 2069; // 64 -static const uint64_t SH_FLD_4_ROT_N0_LEN = 2070; // 64 -static const uint64_t SH_FLD_4_ROT_N1 = 2071; // 64 -static const uint64_t SH_FLD_4_ROT_N1_LEN = 2072; // 64 -static const uint64_t SH_FLD_4_ROT_OVERRIDE = 2073; // 16 -static const uint64_t SH_FLD_4_ROT_OVERRIDE_EN = 2074; // 16 -static const uint64_t SH_FLD_4_ROT_OVERRIDE_LEN = 2075; // 16 -static const uint64_t SH_FLD_4_RXCAL_DETECT_DONE_META = 2076; // 16 -static const uint64_t SH_FLD_4_RXCAL_PD_CAL_LAG_META = 2077; // 16 -static const uint64_t SH_FLD_4_RXCAL_PD_MAIN_LAG_META = 2078; // 16 -static const uint64_t SH_FLD_4_RXCAL_PD_MAIN_LEAD_META = 2079; // 16 -static const uint64_t SH_FLD_4_RXREG_COMPCON_DC = 2080; // 16 -static const uint64_t SH_FLD_4_RXREG_COMPCON_DC_LEN = 2081; // 16 -static const uint64_t SH_FLD_4_RXREG_CON_DC = 2082; // 16 -static const uint64_t SH_FLD_4_RXREG_DAC_PULLUP_DC = 2083; // 16 -static const uint64_t SH_FLD_4_RXREG_DRVCON_DC = 2084; // 16 -static const uint64_t SH_FLD_4_RXREG_DRVCON_DC_LEN = 2085; // 16 -static const uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC = 2086; // 16 -static const uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN = 2087; // 16 -static const uint64_t SH_FLD_4_RXREG_FINECAL_2XILSB_DC = 2088; // 16 -static const uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC = 2089; // 16 -static const uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2090; // 16 -static const uint64_t SH_FLD_4_RXREG_REF_SEL_DC = 2091; // 16 -static const uint64_t SH_FLD_4_RXREG_REF_SEL_DC_LEN = 2092; // 16 -static const uint64_t SH_FLD_4_S0ACENSLICENDRV_DC = 2093; // 8 -static const uint64_t SH_FLD_4_S0ACENSLICENDRV_DC_LEN = 2094; // 8 -static const uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC = 2095; // 8 -static const uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC_LEN = 2096; // 8 -static const uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC = 2097; // 8 -static const uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC_LEN = 2098; // 8 -static const uint64_t SH_FLD_4_S0INSDLYTAP = 2099; // 8 -static const uint64_t SH_FLD_4_S1ACENSLICENDRV_DC = 2100; // 8 -static const uint64_t SH_FLD_4_S1ACENSLICENDRV_DC_LEN = 2101; // 8 -static const uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC = 2102; // 8 -static const uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC_LEN = 2103; // 8 -static const uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC = 2104; // 8 -static const uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC_LEN = 2105; // 8 -static const uint64_t SH_FLD_4_S1INSDLYTAP = 2106; // 8 -static const uint64_t SH_FLD_4_SEL_A = 2107; // 8 -static const uint64_t SH_FLD_4_SEL_A_LEN = 2108; // 8 -static const uint64_t SH_FLD_4_SEL_B = 2109; // 8 -static const uint64_t SH_FLD_4_SEL_B_LEN = 2110; // 8 -static const uint64_t SH_FLD_4_SEND_ENABLE = 2111; // 1 -static const uint64_t SH_FLD_4_SEND_MODE = 2112; // 1 -static const uint64_t SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN = 2113; // 16 -static const uint64_t SH_FLD_4_SLAVE_VREG_DAC_COARSE = 2114; // 16 -static const uint64_t SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN = 2115; // 16 -static const uint64_t SH_FLD_4_SLAVE_VREG_OVERRIDE = 2116; // 16 -static const uint64_t SH_FLD_4_SLAVE_VREG_REF_SEL_DC = 2117; // 16 -static const uint64_t SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN = 2118; // 16 -static const uint64_t SH_FLD_4_SMALL_STEP_LEFT = 2119; // 8 -static const uint64_t SH_FLD_4_SMALL_STEP_RIGHT = 2120; // 8 -static const uint64_t SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL = 2121; // 3 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE = 2122; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR0 = 2123; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR1 = 2124; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR2 = 2125; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR3 = 2126; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK1 = 2127; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK2 = 2128; // 8 -static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK3 = 2129; // 8 -static const uint64_t SH_FLD_4_SYNC = 2130; // 8 -static const uint64_t SH_FLD_4_SYNC_LEN = 2131; // 8 -static const uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET = 2132; // 8 -static const uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN = 2133; // 8 -static const uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET = 2134; // 8 -static const uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN = 2135; // 8 -static const uint64_t SH_FLD_4_TRAILING_EDGE_FOUND_MASK = 2136; // 8 -static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND = 2137; // 8 -static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 = 2138; // 8 -static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 2139; // 8 -static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 = 2140; // 8 -static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 2141; // 8 -static const uint64_t SH_FLD_4_TRIG_PERIOD = 2142; // 8 -static const uint64_t SH_FLD_4_TSYS = 2143; // 8 -static const uint64_t SH_FLD_4_TSYS_LEN = 2144; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE = 2145; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR0 = 2146; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR1 = 2147; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR2 = 2148; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR3 = 2149; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK1 = 2150; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK2 = 2151; // 8 -static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK3 = 2152; // 8 -static const uint64_t SH_FLD_4_UPPER = 2153; // 16 -static const uint64_t SH_FLD_4_UPPER_LEN = 2154; // 16 -static const uint64_t SH_FLD_4_VALID_NS_BIG_L = 2155; // 8 -static const uint64_t SH_FLD_4_VALID_NS_BIG_L_MASK = 2156; // 8 -static const uint64_t SH_FLD_4_VALID_NS_BIG_R = 2157; // 8 -static const uint64_t SH_FLD_4_VALID_NS_BIG_R_MASK = 2158; // 8 -static const uint64_t SH_FLD_4_VALID_NS_JUMP_BACK = 2159; // 8 -static const uint64_t SH_FLD_4_VALID_NS_JUMP_BACK_MASK = 2160; // 8 -static const uint64_t SH_FLD_4_VALUE_DRAM0 = 2161; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM0_LEN = 2162; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM1 = 2163; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM1_LEN = 2164; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM2 = 2165; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM2_LEN = 2166; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM3 = 2167; // 32 -static const uint64_t SH_FLD_4_VALUE_DRAM3_LEN = 2168; // 32 -static const uint64_t SH_FLD_4_VREG_RXCAL_COMP_OUT_META = 2169; // 16 -static const uint64_t SH_FLD_4_VREG_SLAVE_COMP_OUT = 2170; // 16 -static const uint64_t SH_FLD_4_WL_ADVANCE_DISABLE = 2171; // 8 -static const uint64_t SH_FLD_4_WL_ERR_CLK16 = 2172; // 16 -static const uint64_t SH_FLD_4_WL_ERR_CLK16_MASK = 2173; // 8 -static const uint64_t SH_FLD_4_WL_ERR_CLK18 = 2174; // 16 -static const uint64_t SH_FLD_4_WL_ERR_CLK18_MASK = 2175; // 8 -static const uint64_t SH_FLD_4_WL_ERR_CLK20 = 2176; // 16 -static const uint64_t SH_FLD_4_WL_ERR_CLK20_MASK = 2177; // 8 -static const uint64_t SH_FLD_4_WL_ERR_CLK22 = 2178; // 16 -static const uint64_t SH_FLD_4_WRAPSEL = 2179; // 8 -static const uint64_t SH_FLD_4_WTRFL_AVE_DIS = 2180; // 8 -static const uint64_t SH_FLD_4_ZERO_DETECTED = 2181; // 8 -static const uint64_t SH_FLD_5 = 2182; // 457 -static const uint64_t SH_FLD_5_LEN = 2183; // 43 -static const uint64_t SH_FLD_5_RESERVED = 2184; // 3 -static const uint64_t SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL = 2185; // 3 -static const uint64_t SH_FLD_6 = 2186; // 457 -static const uint64_t SH_FLD_6_LEN = 2187; // 43 -static const uint64_t SH_FLD_6_RESERVED = 2188; // 3 -static const uint64_t SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL = 2189; // 3 -static const uint64_t SH_FLD_6_SPARE_TERM_DIS = 2190; // 3 -static const uint64_t SH_FLD_7 = 2191; // 414 -static const uint64_t SH_FLD_7_RESERVED = 2192; // 3 -static const uint64_t SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL = 2193; // 3 -static const uint64_t SH_FLD_7_SPARE_TERM_DIS = 2194; // 3 -static const uint64_t SH_FLD_8 = 2195; // 8 -static const uint64_t SH_FLD_842_FC_SELECT = 2196; // 1 -static const uint64_t SH_FLD_842_FC_SELECT_LEN = 2197; // 1 -static const uint64_t SH_FLD_842_LATENCY_CFG = 2198; // 1 -static const uint64_t SH_FLD_8_11_SPARE = 2199; // 8 -static const uint64_t SH_FLD_8_11_SPARE_LEN = 2200; // 8 -static const uint64_t SH_FLD_8_9 = 2201; // 6 -static const uint64_t SH_FLD_8_9_LEN = 2202; // 6 -static const uint64_t SH_FLD_8_RESERVED = 2203; // 6 -static const uint64_t SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL = 2204; // 3 -static const uint64_t SH_FLD_9 = 2205; // 8 -static const uint64_t SH_FLD_9_RESERVED = 2206; // 3 -static const uint64_t SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL = 2207; // 3 -static const uint64_t SH_FLD_AACR_PE = 2208; // 8 -static const uint64_t SH_FLD_AADR_PE = 2209; // 8 -static const uint64_t SH_FLD_AAER_PE = 2210; // 8 -static const uint64_t SH_FLD_ABIST = 2211; // 43 -static const uint64_t SH_FLD_ABORT = 2212; // 6 -static const uint64_t SH_FLD_ABORTED_CMD = 2213; // 1 -static const uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL = 2214; // 6 -static const uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN = 2215; // 6 -static const uint64_t SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR = 2216; // 43 -static const uint64_t SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 2217; // 43 -static const uint64_t SH_FLD_ABORT_ON_ERROR = 2218; // 8 -static const uint64_t SH_FLD_ABORT_ON_ERR_EN = 2219; // 8 -static const uint64_t SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR = 2220; // 43 -static const uint64_t SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR = 2221; // 43 -static const uint64_t SH_FLD_ABUS_LOCK = 2222; // 1 -static const uint64_t SH_FLD_ACCUM = 2223; // 6 -static const uint64_t SH_FLD_ACCUMULATED_DL_RETURN_P0 = 2224; // 43 -static const uint64_t SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2225; // 43 -static const uint64_t SH_FLD_ACCUMULATED_GENERAL_TIMEOUT = 2226; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID = 2227; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD = 2228; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD = 2229; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 2230; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE = 2231; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY = 2232; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY = 2233; // 43 -static const uint64_t SH_FLD_ACCUMULATED_PCB_WDATA_PARITY = 2234; // 43 -static const uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 2235; // 43 -static const uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 2236; // 43 -static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 2237; // 43 -static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 2238; // 43 -static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 2239; // 43 -static const uint64_t SH_FLD_ACCUMULATED_UL_P0 = 2240; // 43 -static const uint64_t SH_FLD_ACCUMULATED_UL_RDATA_PARITY = 2241; // 43 -static const uint64_t SH_FLD_ACCUM_HIST = 2242; // 43 -static const uint64_t SH_FLD_ACCUM_LEN = 2243; // 6 -static const uint64_t SH_FLD_ACK = 2244; // 1 -static const uint64_t SH_FLD_ACK_DEAD_CRESP = 2245; // 2 -static const uint64_t SH_FLD_ACK_FIFO_CAP_ADDR = 2246; // 10 -static const uint64_t SH_FLD_ACK_FIFO_CAP_ADDR_LEN = 2247; // 10 -static const uint64_t SH_FLD_ACK_FIFO_CAP_VALID = 2248; // 10 -static const uint64_t SH_FLD_ACK_QUEUE_HIGH = 2249; // 2 -static const uint64_t SH_FLD_ACK_QUEUE_HIGH_LEN = 2250; // 2 -static const uint64_t SH_FLD_ACK_QUEUE_LOW = 2251; // 2 -static const uint64_t SH_FLD_ACK_QUEUE_LOW_LEN = 2252; // 2 -static const uint64_t SH_FLD_ACK_QUEUE_START = 2253; // 2 -static const uint64_t SH_FLD_ACK_QUEUE_START_LEN = 2254; // 2 -static const uint64_t SH_FLD_ACT = 2255; // 63 -static const uint64_t SH_FLD_ACTCYCLECNT = 2256; // 3 -static const uint64_t SH_FLD_ACTCYCLECNT_LEN = 2257; // 3 -static const uint64_t SH_FLD_ACTION0 = 2258; // 60 -static const uint64_t SH_FLD_ACTION0_LEN = 2259; // 60 -static const uint64_t SH_FLD_ACTION1 = 2260; // 60 -static const uint64_t SH_FLD_ACTION1_LEN = 2261; // 60 -static const uint64_t SH_FLD_ACTION_0 = 2262; // 4 -static const uint64_t SH_FLD_ACTION_0_LEN = 2263; // 4 -static const uint64_t SH_FLD_ACTION_1 = 2264; // 4 -static const uint64_t SH_FLD_ACTION_1_LEN = 2265; // 4 -static const uint64_t SH_FLD_ACTIVATE_COUNT = 2266; // 8 -static const uint64_t SH_FLD_ACTIVATE_COUNT_LEN = 2267; // 8 -static const uint64_t SH_FLD_ACTIVE_CHANNEL_CNT = 2268; // 1 -static const uint64_t SH_FLD_ACTIVE_CHANNEL_CNT_LEN = 2269; // 1 -static const uint64_t SH_FLD_ACTIVE_MASK = 2270; // 24 -static const uint64_t SH_FLD_ACTIVE_MASK_LEN = 2271; // 24 -static const uint64_t SH_FLD_ACTIVITY = 2272; // 129 -static const uint64_t SH_FLD_ACTIVITY_LEN = 2273; // 129 -static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE = 2274; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN = 2275; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN = 2276; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SB_SPARE = 2277; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH = 2278; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN = 2279; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK = 2280; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN = 2281; // 24 -static const uint64_t SH_FLD_ACTUAL_CLK_SW_SPARE = 2282; // 24 -static const uint64_t SH_FLD_ACTUAL_ERROR = 2283; // 3 -static const uint64_t SH_FLD_ACTUAL_ERROR_LEN = 2284; // 3 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE = 2285; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN = 2286; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN = 2287; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_SPARE0 = 2288; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH = 2289; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN = 2290; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK = 2291; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN = 2292; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_SPARE1 = 2293; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE = 2294; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN = 2295; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN = 2296; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_SPARE0 = 2297; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH = 2298; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN = 2299; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK = 2300; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN = 2301; // 6 -static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_SPARE1 = 2302; // 6 -static const uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL = 2303; // 4 -static const uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN = 2304; // 4 -static const uint64_t SH_FLD_ACT_DIS = 2305; // 43 -static const uint64_t SH_FLD_AC_COUPLED = 2306; // 2 -static const uint64_t SH_FLD_ADAPTEST_1BIT_ENABLE = 2307; // 1 -static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX = 2308; // 1 -static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 2309; // 1 -static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN = 2310; // 1 -static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 2311; // 1 -static const uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH = 2312; // 1 -static const uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 2313; // 1 -static const uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH = 2314; // 1 -static const uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 2315; // 1 -static const uint64_t SH_FLD_ADAPTEST_ENABLE = 2316; // 1 -static const uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH = 2317; // 1 -static const uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 2318; // 1 -static const uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH = 2319; // 1 -static const uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 2320; // 1 -static const uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE = 2321; // 1 -static const uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN = 2322; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 2323; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 2324; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 2325; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 2326; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 2327; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 2328; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 2329; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 2330; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH = 2331; // 1 -static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN = 2332; // 1 -static const uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE = 2333; // 1 -static const uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE_LEN = 2334; // 1 -static const uint64_t SH_FLD_ADCFSM_ONGOING = 2335; // 1 -static const uint64_t SH_FLD_ADDR = 2336; // 39 -static const uint64_t SH_FLD_ADDR0 = 2337; // 8 -static const uint64_t SH_FLD_ADDR0_LEN = 2338; // 8 -static const uint64_t SH_FLD_ADDR1 = 2339; // 8 -static const uint64_t SH_FLD_ADDR1_LEN = 2340; // 8 -static const uint64_t SH_FLD_ADDR2 = 2341; // 16 -static const uint64_t SH_FLD_ADDR2_LEN = 2342; // 16 -static const uint64_t SH_FLD_ADDR3 = 2343; // 16 -static const uint64_t SH_FLD_ADDR3_LEN = 2344; // 16 -static const uint64_t SH_FLD_ADDR4 = 2345; // 16 -static const uint64_t SH_FLD_ADDR4_LEN = 2346; // 16 -static const uint64_t SH_FLD_ADDRESS = 2347; // 221 -static const uint64_t SH_FLD_ADDRESS_8_63 = 2348; // 1 -static const uint64_t SH_FLD_ADDRESS_8_63_LEN = 2349; // 1 -static const uint64_t SH_FLD_ADDRESS_LEN = 2350; // 220 -static const uint64_t SH_FLD_ADDRESS_PARITY = 2351; // 43 -static const uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 2352; // 2 -static const uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 2353; // 2 -static const uint64_t SH_FLD_ADDR_21_37 = 2354; // 1 -static const uint64_t SH_FLD_ADDR_21_37_LEN = 2355; // 1 -static const uint64_t SH_FLD_ADDR_26_38 = 2356; // 1 -static const uint64_t SH_FLD_ADDR_26_38_LEN = 2357; // 1 -static const uint64_t SH_FLD_ADDR_8_37 = 2358; // 1 -static const uint64_t SH_FLD_ADDR_8_37_LEN = 2359; // 1 -static const uint64_t SH_FLD_ADDR_8_38 = 2360; // 1 -static const uint64_t SH_FLD_ADDR_8_38_LEN = 2361; // 1 -static const uint64_t SH_FLD_ADDR_8_48 = 2362; // 1 -static const uint64_t SH_FLD_ADDR_8_48_LEN = 2363; // 1 -static const uint64_t SH_FLD_ADDR_8_49 = 2364; // 2 -static const uint64_t SH_FLD_ADDR_8_49_LEN = 2365; // 2 -static const uint64_t SH_FLD_ADDR_BAR = 2366; // 2 -static const uint64_t SH_FLD_ADDR_BAR_MODE = 2367; // 2 -static const uint64_t SH_FLD_ADDR_BUFFER = 2368; // 43 -static const uint64_t SH_FLD_ADDR_ERROR = 2369; // 2 -static const uint64_t SH_FLD_ADDR_ERROR_PULSE = 2370; // 2 -static const uint64_t SH_FLD_ADDR_INVALID_FACES = 2371; // 1 -static const uint64_t SH_FLD_ADDR_INVALID_PIB = 2372; // 1 -static const uint64_t SH_FLD_ADDR_LEN = 2373; // 39 -static const uint64_t SH_FLD_ADDR_MIRROR_A11_A13 = 2374; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_A3_A4 = 2375; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_A5_A6 = 2376; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_A7_A8 = 2377; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_BA0_BA1 = 2378; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_BG0_BG1 = 2379; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP0_PRI = 2380; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP0_QUA = 2381; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP0_SEC = 2382; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP0_TER = 2383; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP1_PRI = 2384; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP1_QUA = 2385; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP1_SEC = 2386; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP1_TER = 2387; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP2_PRI = 2388; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP2_QUA = 2389; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP2_SEC = 2390; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP2_TER = 2391; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP3_PRI = 2392; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP3_QUA = 2393; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP3_SEC = 2394; // 8 -static const uint64_t SH_FLD_ADDR_MIRROR_RP3_TER = 2395; // 8 -static const uint64_t SH_FLD_ADDR_NVLD = 2396; // 1 -static const uint64_t SH_FLD_ADDR_PARITY_ERR = 2397; // 4 -static const uint64_t SH_FLD_ADDR_RESET_INTR_FACES = 2398; // 1 -static const uint64_t SH_FLD_ADDR_RESET_INTR_FACES_LEN = 2399; // 1 -static const uint64_t SH_FLD_ADDR_RESET_INTR_PIB = 2400; // 1 -static const uint64_t SH_FLD_ADDR_RESET_INTR_PIB_LEN = 2401; // 1 -static const uint64_t SH_FLD_ADDR_TAG = 2402; // 1 -static const uint64_t SH_FLD_ADDR_TAG_LEN = 2403; // 1 -static const uint64_t SH_FLD_ADR = 2404; // 4 -static const uint64_t SH_FLD_ADR0 = 2405; // 16 -static const uint64_t SH_FLD_ADR0_ANALOG_WRAPON = 2406; // 8 -static const uint64_t SH_FLD_ADR0_ATESTSEL_0_2 = 2407; // 8 -static const uint64_t SH_FLD_ADR0_ATESTSEL_0_2_LEN = 2408; // 8 -static const uint64_t SH_FLD_ADR0_ATEST_SEL_0 = 2409; // 8 -static const uint64_t SH_FLD_ADR0_ATEST_SEL_0_LEN = 2410; // 8 -static const uint64_t SH_FLD_ADR0_BB_LOCK = 2411; // 8 -static const uint64_t SH_FLD_ADR0_CAL_CKTS_ACTIVE = 2412; // 8 -static const uint64_t SH_FLD_ADR0_CAL_ERROR = 2413; // 8 -static const uint64_t SH_FLD_ADR0_CAL_ERROR_FINE = 2414; // 8 -static const uint64_t SH_FLD_ADR0_CAL_GOOD = 2415; // 8 -static const uint64_t SH_FLD_ADR0_CAL_PD_ENABLE = 2416; // 8 -static const uint64_t SH_FLD_ADR0_CONTINUOUS_UPDATE = 2417; // 8 -static const uint64_t SH_FLD_ADR0_DETECT_REQ = 2418; // 8 -static const uint64_t SH_FLD_ADR0_DLL_ADJUST = 2419; // 8 -static const uint64_t SH_FLD_ADR0_DLL_ADJUST_LEN = 2420; // 8 -static const uint64_t SH_FLD_ADR0_DLL_COMPARE_OUT = 2421; // 8 -static const uint64_t SH_FLD_ADR0_DLL_CORRECT_EN = 2422; // 8 -static const uint64_t SH_FLD_ADR0_DLL_ITER_A = 2423; // 8 -static const uint64_t SH_FLD_ADR0_EN = 2424; // 8 -static const uint64_t SH_FLD_ADR0_EN_DRIVER_INVFB_DC = 2425; // 8 -static const uint64_t SH_FLD_ADR0_FLUSH = 2426; // 8 -static const uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 = 2427; // 8 -static const uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN = 2428; // 8 -static const uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 = 2429; // 8 -static const uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN = 2430; // 8 -static const uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 = 2431; // 8 -static const uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN = 2432; // 8 -static const uint64_t SH_FLD_ADR0_INIT_IO = 2433; // 8 -static const uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_RESET = 2434; // 8 -static const uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE = 2435; // 8 -static const uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW = 2436; // 8 -static const uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_LEN = 2437; // 8 -static const uint64_t SH_FLD_ADR0_LEN = 2438; // 16 -static const uint64_t SH_FLD_ADR0_MAIN_PD_ENABLE = 2439; // 8 -static const uint64_t SH_FLD_ADR0_OVERRIDE = 2440; // 16 -static const uint64_t SH_FLD_ADR0_OVERRIDE_EN = 2441; // 8 -static const uint64_t SH_FLD_ADR0_OVERRIDE_LEN = 2442; // 8 -static const uint64_t SH_FLD_ADR0_PHASE_ALIGN_RESET = 2443; // 8 -static const uint64_t SH_FLD_ADR0_PHASE_DEFAULT_EN = 2444; // 8 -static const uint64_t SH_FLD_ADR0_PHASE_EN = 2445; // 8 -static const uint64_t SH_FLD_ADR0_POS_EDGE_ALIGN = 2446; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP = 2447; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2448; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 2449; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC = 2450; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC_LEN = 2451; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_EN = 2452; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_EN_LEN = 2453; // 8 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG = 2454; // 16 -static const uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG_LEN = 2455; // 16 -static const uint64_t SH_FLD_ADR0_ROT = 2456; // 8 -static const uint64_t SH_FLD_ADR0_ROT_LEN = 2457; // 8 -static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE = 2458; // 8 -static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE_EN = 2459; // 8 -static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE_LEN = 2460; // 8 -static const uint64_t SH_FLD_ADR0_RXCAL_DETECT_DONE_META = 2461; // 8 -static const uint64_t SH_FLD_ADR0_RXCAL_PD_CAL_LAG_META = 2462; // 8 -static const uint64_t SH_FLD_ADR0_RXCAL_PD_MAIN_LAG_META = 2463; // 8 -static const uint64_t SH_FLD_ADR0_RXCAL_PD_MAIN_LEAD_META = 2464; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC = 2465; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC_LEN = 2466; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_CON_DC = 2467; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_DAC_PULLUP_DC = 2468; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC = 2469; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC_LEN = 2470; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC = 2471; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 2472; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_FINECAL_2XILSB_DC = 2473; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 2474; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2475; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC = 2476; // 8 -static const uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN = 2477; // 8 -static const uint64_t SH_FLD_ADR0_SLAVE_CAL_CKT_POWERDOWN = 2478; // 8 -static const uint64_t SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE = 2479; // 8 -static const uint64_t SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE_LEN = 2480; // 8 -static const uint64_t SH_FLD_ADR0_SLAVE_VREG_OVERRIDE = 2481; // 8 -static const uint64_t SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC = 2482; // 8 -static const uint64_t SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC_LEN = 2483; // 8 -static const uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS = 2484; // 8 -static const uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS_LEN = 2485; // 8 -static const uint64_t SH_FLD_ADR0_START = 2486; // 8 -static const uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET = 2487; // 8 -static const uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET_LEN = 2488; // 8 -static const uint64_t SH_FLD_ADR0_TSYS = 2489; // 8 -static const uint64_t SH_FLD_ADR0_TSYS_LEN = 2490; // 8 -static const uint64_t SH_FLD_ADR0_VALUE = 2491; // 16 -static const uint64_t SH_FLD_ADR0_VALUE_LEN = 2492; // 16 -static const uint64_t SH_FLD_ADR0_VREG_RXCAL_COMP_OUT_META = 2493; // 8 -static const uint64_t SH_FLD_ADR0_VREG_SLAVE1_COMP_OUT = 2494; // 8 -static const uint64_t SH_FLD_ADR0_VREG_SLAVE2_COMP_OUT = 2495; // 8 -static const uint64_t SH_FLD_ADR1 = 2496; // 16 -static const uint64_t SH_FLD_ADR1_ANALOG_WRAPON = 2497; // 8 -static const uint64_t SH_FLD_ADR1_ATESTSEL_0_2 = 2498; // 8 -static const uint64_t SH_FLD_ADR1_ATESTSEL_0_2_LEN = 2499; // 8 -static const uint64_t SH_FLD_ADR1_ATEST_SEL_0 = 2500; // 8 -static const uint64_t SH_FLD_ADR1_ATEST_SEL_0_LEN = 2501; // 8 -static const uint64_t SH_FLD_ADR1_BB_LOCK = 2502; // 8 -static const uint64_t SH_FLD_ADR1_CAL_CKTS_ACTIVE = 2503; // 8 -static const uint64_t SH_FLD_ADR1_CAL_ERROR = 2504; // 8 -static const uint64_t SH_FLD_ADR1_CAL_ERROR_FINE = 2505; // 8 -static const uint64_t SH_FLD_ADR1_CAL_GOOD = 2506; // 8 -static const uint64_t SH_FLD_ADR1_CAL_PD_ENABLE = 2507; // 8 -static const uint64_t SH_FLD_ADR1_CONTINUOUS_UPDATE = 2508; // 8 -static const uint64_t SH_FLD_ADR1_DETECT_REQ = 2509; // 8 -static const uint64_t SH_FLD_ADR1_DLL_ADJUST = 2510; // 8 -static const uint64_t SH_FLD_ADR1_DLL_ADJUST_LEN = 2511; // 8 -static const uint64_t SH_FLD_ADR1_DLL_COMPARE_OUT = 2512; // 8 -static const uint64_t SH_FLD_ADR1_DLL_CORRECT_EN = 2513; // 8 -static const uint64_t SH_FLD_ADR1_DLL_ITER_A = 2514; // 8 -static const uint64_t SH_FLD_ADR1_EN = 2515; // 8 -static const uint64_t SH_FLD_ADR1_EN_DRIVER_INVFB_DC = 2516; // 8 -static const uint64_t SH_FLD_ADR1_FLUSH = 2517; // 8 -static const uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 = 2518; // 8 -static const uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN = 2519; // 8 -static const uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 = 2520; // 8 -static const uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN = 2521; // 8 -static const uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 = 2522; // 8 -static const uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN = 2523; // 8 -static const uint64_t SH_FLD_ADR1_INIT_IO = 2524; // 8 -static const uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_RESET = 2525; // 8 -static const uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE = 2526; // 8 -static const uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW = 2527; // 8 -static const uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_LEN = 2528; // 8 -static const uint64_t SH_FLD_ADR1_LEN = 2529; // 16 -static const uint64_t SH_FLD_ADR1_MAIN_PD_ENABLE = 2530; // 8 -static const uint64_t SH_FLD_ADR1_OVERRIDE = 2531; // 16 -static const uint64_t SH_FLD_ADR1_OVERRIDE_EN = 2532; // 8 -static const uint64_t SH_FLD_ADR1_OVERRIDE_LEN = 2533; // 8 -static const uint64_t SH_FLD_ADR1_PHASE_ALIGN_RESET = 2534; // 8 -static const uint64_t SH_FLD_ADR1_PHASE_DEFAULT_EN = 2535; // 8 -static const uint64_t SH_FLD_ADR1_PHASE_EN = 2536; // 8 -static const uint64_t SH_FLD_ADR1_POS_EDGE_ALIGN = 2537; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP = 2538; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2539; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 2540; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC = 2541; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC_LEN = 2542; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_EN = 2543; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_EN_LEN = 2544; // 8 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG = 2545; // 16 -static const uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG_LEN = 2546; // 16 -static const uint64_t SH_FLD_ADR1_ROT = 2547; // 8 -static const uint64_t SH_FLD_ADR1_ROT_LEN = 2548; // 8 -static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE = 2549; // 8 -static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE_EN = 2550; // 8 -static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE_LEN = 2551; // 8 -static const uint64_t SH_FLD_ADR1_RXCAL_DETECT_DONE_META = 2552; // 8 -static const uint64_t SH_FLD_ADR1_RXCAL_PD_CAL_LAG_META = 2553; // 8 -static const uint64_t SH_FLD_ADR1_RXCAL_PD_MAIN_LAG_META = 2554; // 8 -static const uint64_t SH_FLD_ADR1_RXCAL_PD_MAIN_LEAD_META = 2555; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC = 2556; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC_LEN = 2557; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_CON_DC = 2558; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_DAC_PULLUP_DC = 2559; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC = 2560; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC_LEN = 2561; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC = 2562; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 2563; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_FINECAL_2XILSB_DC = 2564; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 2565; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2566; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC = 2567; // 8 -static const uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN = 2568; // 8 -static const uint64_t SH_FLD_ADR1_SLAVE_CAL_CKT_POWERDOWN = 2569; // 8 -static const uint64_t SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE = 2570; // 8 -static const uint64_t SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE_LEN = 2571; // 8 -static const uint64_t SH_FLD_ADR1_SLAVE_VREG_OVERRIDE = 2572; // 8 -static const uint64_t SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC = 2573; // 8 -static const uint64_t SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC_LEN = 2574; // 8 -static const uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS = 2575; // 8 -static const uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS_LEN = 2576; // 8 -static const uint64_t SH_FLD_ADR1_START = 2577; // 8 -static const uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET = 2578; // 8 -static const uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET_LEN = 2579; // 8 -static const uint64_t SH_FLD_ADR1_TSYS = 2580; // 8 -static const uint64_t SH_FLD_ADR1_TSYS_LEN = 2581; // 8 -static const uint64_t SH_FLD_ADR1_VALUE = 2582; // 16 -static const uint64_t SH_FLD_ADR1_VALUE_LEN = 2583; // 16 -static const uint64_t SH_FLD_ADR1_VREG_RXCAL_COMP_OUT_META = 2584; // 8 -static const uint64_t SH_FLD_ADR1_VREG_SLAVE1_COMP_OUT = 2585; // 8 -static const uint64_t SH_FLD_ADR1_VREG_SLAVE2_COMP_OUT = 2586; // 8 -static const uint64_t SH_FLD_ADR_DLL_CAL_ERROR = 2587; // 8 -static const uint64_t SH_FLD_ADR_DLL_CAL_ERROR_FINE = 2588; // 8 -static const uint64_t SH_FLD_ADR_ERROR = 2589; // 8 -static const uint64_t SH_FLD_ADR_ERROR_FINE = 2590; // 8 -static const uint64_t SH_FLD_ADR_GOOD = 2591; // 8 -static const uint64_t SH_FLD_ADR_LEN = 2592; // 4 -static const uint64_t SH_FLD_ADR_SLAVE_SEL = 2593; // 8 -static const uint64_t SH_FLD_ADS_HANG = 2594; // 1 -static const uint64_t SH_FLD_ADU_MALF_ALERT = 2595; // 1 -static const uint64_t SH_FLD_ADVANCE_RD_VALID = 2596; // 8 -static const uint64_t SH_FLD_AECS = 2597; // 6 -static const uint64_t SH_FLD_AECS_LEN = 2598; // 6 -static const uint64_t SH_FLD_AESSHA_LATENCY_CFG = 2599; // 1 -static const uint64_t SH_FLD_AES_LATENCY_CFG = 2600; // 1 -static const uint64_t SH_FLD_AIB_ACCESS_ERROR = 2601; // 6 -static const uint64_t SH_FLD_AIB_ADDRESS_INVALID = 2602; // 6 -static const uint64_t SH_FLD_AIB_COMMAND_INVALID = 2603; // 6 -static const uint64_t SH_FLD_AIB_FATAL_CLASS_ERROR = 2604; // 6 -static const uint64_t SH_FLD_AIB_INF_CLASS_ERROR = 2605; // 6 -static const uint64_t SH_FLD_AIB_IN_CMD_CTL_PERR = 2606; // 1 -static const uint64_t SH_FLD_AIB_IN_CMD_PERR = 2607; // 1 -static const uint64_t SH_FLD_AIB_IN_DAT_CTL_PERR = 2608; // 1 -static const uint64_t SH_FLD_AI_ECC_CE = 2609; // 1 -static const uint64_t SH_FLD_AI_ECC_UE = 2610; // 1 -static const uint64_t SH_FLD_ALIGN_ON_EVEN_CYCLES = 2611; // 8 -static const uint64_t SH_FLD_ALLOC = 2612; // 24 -static const uint64_t SH_FLD_ALLOC_LEN = 2613; // 24 -static const uint64_t SH_FLD_ALLOW_CRYPTO = 2614; // 1 -static const uint64_t SH_FLD_ALLOW_RD_FIFO_AUTO_RESET = 2615; // 8 -static const uint64_t SH_FLD_ALLOW_REG_WAKEUP_C0 = 2616; // 12 -static const uint64_t SH_FLD_ALLOW_REG_WAKEUP_C1 = 2617; // 12 -static const uint64_t SH_FLD_ALTD_DATA_ITAG = 2618; // 1 -static const uint64_t SH_FLD_ALTD_DATA_TX = 2619; // 1 -static const uint64_t SH_FLD_ALTD_DATA_TX_LEN = 2620; // 1 -static const uint64_t SH_FLD_ALTD_DATA_TX_OVERWRITE = 2621; // 1 -static const uint64_t SH_FLD_ALT_M = 2622; // 8 -static const uint64_t SH_FLD_ALT_M_LEN = 2623; // 8 -static const uint64_t SH_FLD_ALT_SEGSZ_DIS = 2624; // 1 -static const uint64_t SH_FLD_ALU_ADR = 2625; // 3 -static const uint64_t SH_FLD_ALU_ADR_LEN = 2626; // 3 -static const uint64_t SH_FLD_ALU_FLIP_ENDIAN_BIG = 2627; // 3 -static const uint64_t SH_FLD_ALU_FLIP_ENDIAN_LITTLE = 2628; // 3 -static const uint64_t SH_FLD_ALU_SAFE_LATENCY = 2629; // 3 -static const uint64_t SH_FLD_ALU_SZ = 2630; // 3 -static const uint64_t SH_FLD_ALU_TYPE = 2631; // 3 -static const uint64_t SH_FLD_ALU_TYPE_LEN = 2632; // 3 -static const uint64_t SH_FLD_ALWAYS_RTY = 2633; // 8 -static const uint64_t SH_FLD_AMAX_HIGH = 2634; // 6 -static const uint64_t SH_FLD_AMAX_HIGH_LEN = 2635; // 6 -static const uint64_t SH_FLD_AMAX_LOW = 2636; // 6 -static const uint64_t SH_FLD_AMAX_LOW_LEN = 2637; // 6 -static const uint64_t SH_FLD_AMIN_CFG = 2638; // 6 -static const uint64_t SH_FLD_AMIN_CFG_LEN = 2639; // 6 -static const uint64_t SH_FLD_AMIN_ENABLE_HDAC = 2640; // 4 -static const uint64_t SH_FLD_AMIN_TIMEOUT = 2641; // 6 -static const uint64_t SH_FLD_AMIN_TIMEOUT_LEN = 2642; // 6 -static const uint64_t SH_FLD_AMO_DRAM_SIZE_128B = 2643; // 8 -static const uint64_t SH_FLD_AMO_LIMIT = 2644; // 8 -static const uint64_t SH_FLD_AMO_LIMIT_LEN = 2645; // 8 -static const uint64_t SH_FLD_AMP0_FILTER_MASK = 2646; // 6 -static const uint64_t SH_FLD_AMP0_FILTER_MASK_LEN = 2647; // 6 -static const uint64_t SH_FLD_AMP1_FILTER_MASK = 2648; // 6 -static const uint64_t SH_FLD_AMP1_FILTER_MASK_LEN = 2649; // 6 -static const uint64_t SH_FLD_AMP_CFG = 2650; // 6 -static const uint64_t SH_FLD_AMP_CFG_LEN = 2651; // 6 -static const uint64_t SH_FLD_AMP_GAIN_CNT_MAX = 2652; // 6 -static const uint64_t SH_FLD_AMP_GAIN_CNT_MAX_LEN = 2653; // 6 -static const uint64_t SH_FLD_AMP_INIT_CFG = 2654; // 6 -static const uint64_t SH_FLD_AMP_INIT_CFG_LEN = 2655; // 6 -static const uint64_t SH_FLD_AMP_INIT_TIMEOUT = 2656; // 6 -static const uint64_t SH_FLD_AMP_INIT_TIMEOUT_LEN = 2657; // 6 -static const uint64_t SH_FLD_AMP_RECAL_CFG = 2658; // 6 -static const uint64_t SH_FLD_AMP_RECAL_CFG_LEN = 2659; // 6 -static const uint64_t SH_FLD_AMP_RECAL_TIMEOUT = 2660; // 6 -static const uint64_t SH_FLD_AMP_RECAL_TIMEOUT_LEN = 2661; // 6 -static const uint64_t SH_FLD_AMP_START_VAL = 2662; // 6 -static const uint64_t SH_FLD_AMP_START_VAL_LEN = 2663; // 6 -static const uint64_t SH_FLD_AMP_TIMEOUT = 2664; // 6 -static const uint64_t SH_FLD_AMP_TIMEOUT_LEN = 2665; // 6 -static const uint64_t SH_FLD_AMP_VAL = 2666; // 120 -static const uint64_t SH_FLD_AMP_VAL_LEN = 2667; // 120 -static const uint64_t SH_FLD_AMR = 2668; // 256 -static const uint64_t SH_FLD_AMR_LEN = 2669; // 256 -static const uint64_t SH_FLD_ANALOGTUNE = 2670; // 20 -static const uint64_t SH_FLD_ANALOGTUNE_LEN = 2671; // 20 -static const uint64_t SH_FLD_ANALOG_INPUT_STAB = 2672; // 8 -static const uint64_t SH_FLD_AND_TRIGGER_MODE1 = 2673; // 86 -static const uint64_t SH_FLD_AND_TRIGGER_MODE2 = 2674; // 86 -static const uint64_t SH_FLD_ANY_ERROR = 2675; // 1 -static const uint64_t SH_FLD_ANY_REQ_ACTIVE = 2676; // 12 -static const uint64_t SH_FLD_AP = 2677; // 8 -static const uint64_t SH_FLD_AP110_AP010_DELTA_MAX = 2678; // 6 -static const uint64_t SH_FLD_AP110_AP010_DELTA_MAX_LEN = 2679; // 6 -static const uint64_t SH_FLD_APB = 2680; // 8 -static const uint64_t SH_FLD_APB_MASK = 2681; // 8 -static const uint64_t SH_FLD_APC0_ENABLE = 2682; // 2 -static const uint64_t SH_FLD_APC0_SC_RDATA_PARITY_ERRHOLD = 2683; // 2 -static const uint64_t SH_FLD_APC1_ENABLE = 2684; // 2 -static const uint64_t SH_FLD_APCARY = 2685; // 4 -static const uint64_t SH_FLD_APCARY_ADDRESS = 2686; // 2 -static const uint64_t SH_FLD_APCARY_ADDRESS_LEN = 2687; // 2 -static const uint64_t SH_FLD_APCARY_LEN = 2688; // 4 -static const uint64_t SH_FLD_APCCTL_ADR_BAR_MODE = 2689; // 2 -static const uint64_t SH_FLD_APCCTL_CFG_BKILL_INC = 2690; // 2 -static const uint64_t SH_FLD_APCCTL_DISABLE_G = 2691; // 2 -static const uint64_t SH_FLD_APCCTL_DISABLE_LN = 2692; // 2 -static const uint64_t SH_FLD_APCCTL_DISABLE_NN_RN = 2693; // 2 -static const uint64_t SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE = 2694; // 2 -static const uint64_t SH_FLD_APCCTL_DISABLE_VG_NOT_SYS = 2695; // 2 -static const uint64_t SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 2696; // 2 -static const uint64_t SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT = 2697; // 2 -static const uint64_t SH_FLD_APCCTL_ENB_CRESP_EXAM = 2698; // 2 -static const uint64_t SH_FLD_APCCTL_ENB_FRC_ADDR13 = 2699; // 2 -static const uint64_t SH_FLD_APCCTL_HANG_ARE = 2700; // 2 -static const uint64_t SH_FLD_APCCTL_HANG_DEAD = 2701; // 2 -static const uint64_t SH_FLD_APCCTL_MAX_RETRY = 2702; // 2 -static const uint64_t SH_FLD_APCCTL_MAX_RETRY_LEN = 2703; // 2 -static const uint64_t SH_FLD_APCCTL_MEM_SEL_MODE = 2704; // 2 -static const uint64_t SH_FLD_APCCTL_P9_MODE = 2705; // 2 -static const uint64_t SH_FLD_APCCTL_PHB_SEL = 2706; // 2 -static const uint64_t SH_FLD_APCCTL_PHB_SEL_LEN = 2707; // 2 -static const uint64_t SH_FLD_APCCTL_SKIP_G = 2708; // 2 -static const uint64_t SH_FLD_APCCTL_SYSADDR = 2709; // 2 -static const uint64_t SH_FLD_APCCTL_SYSADDR_LEN = 2710; // 2 -static const uint64_t SH_FLD_APC_ARRAY_CMD_CE_ERPT = 2711; // 4 -static const uint64_t SH_FLD_APC_ARRAY_CMD_UE_ERPT = 2712; // 4 -static const uint64_t SH_FLD_APC_RDFSM_MASK = 2713; // 2 -static const uint64_t SH_FLD_APC_RDFSM_MASK_LEN = 2714; // 2 -static const uint64_t SH_FLD_APC_SC_RDATA_PARITY_ERRHOLD = 2715; // 2 -static const uint64_t SH_FLD_APX111_HIGH = 2716; // 6 -static const uint64_t SH_FLD_APX111_HIGH_LEN = 2717; // 6 -static const uint64_t SH_FLD_APX111_LOW = 2718; // 6 -static const uint64_t SH_FLD_APX111_LOW_LEN = 2719; // 6 -static const uint64_t SH_FLD_AP_LEN = 2720; // 8 -static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_0 = 2721; // 4 -static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_1 = 2722; // 2 -static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_2 = 2723; // 2 -static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_3 = 2724; // 2 -static const uint64_t SH_FLD_ARB_BLIF_COMPLETION_ERROR = 2725; // 6 -static const uint64_t SH_FLD_ARB_COMMON_FATAL_ERROR = 2726; // 6 -static const uint64_t SH_FLD_ARB_ECC_CORRECTABLE_ERROR = 2727; // 6 -static const uint64_t SH_FLD_ARB_ECC_INJECT_ERR = 2728; // 3 -static const uint64_t SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR = 2729; // 6 -static const uint64_t SH_FLD_ARB_EN_SEND_ALL_WRITES = 2730; // 1 -static const uint64_t SH_FLD_ARB_IODA_FATAL_ERROR = 2731; // 6 -static const uint64_t SH_FLD_ARB_MSI_ADDRESS_ERROR = 2732; // 6 -static const uint64_t SH_FLD_ARB_MSI_PE_MATCH_ERROR = 2733; // 6 -static const uint64_t SH_FLD_ARB_PCT_TIMEOUT_ERROR = 2734; // 6 -static const uint64_t SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 2735; // 6 -static const uint64_t SH_FLD_ARB_RCVD_FATAL_ERROR_MSG = 2736; // 6 -static const uint64_t SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG = 2737; // 6 -static const uint64_t SH_FLD_ARB_RTT_PENUM_INVALID_ERROR = 2738; // 6 -static const uint64_t SH_FLD_ARB_STALL = 2739; // 1 -static const uint64_t SH_FLD_ARB_STOP = 2740; // 1 -static const uint64_t SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR = 2741; // 6 -static const uint64_t SH_FLD_ARB_TLP_POISON_SIGNALED = 2742; // 6 -static const uint64_t SH_FLD_ARB_TVT_ERROR = 2743; // 6 -static const uint64_t SH_FLD_ARM_SEL = 2744; // 43 -static const uint64_t SH_FLD_ARM_SEL_LEN = 2745; // 43 -static const uint64_t SH_FLD_ARRAY_ADDR = 2746; // 6 -static const uint64_t SH_FLD_ARRAY_ADDR_LEN = 2747; // 6 -static const uint64_t SH_FLD_ARRAY_ECC_CE = 2748; // 2 -static const uint64_t SH_FLD_ARRAY_ECC_UE = 2749; // 2 -static const uint64_t SH_FLD_ARRAY_POINTER_SELECT = 2750; // 6 -static const uint64_t SH_FLD_ARRAY_POINTER_SELECT_LEN = 2751; // 6 -static const uint64_t SH_FLD_ARRAY_SELECT = 2752; // 1 -static const uint64_t SH_FLD_ARRAY_SELECT_LEN = 2753; // 1 -static const uint64_t SH_FLD_ARRAY_WRITE_ASSIST_EN = 2754; // 43 -static const uint64_t SH_FLD_ARX_TIMEOUT = 2755; // 1 -static const uint64_t SH_FLD_ARX_TIMEOUT_LEN = 2756; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_AIB = 2757; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_AIB_LEN = 2758; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_AT_SSA = 2759; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_BAR_SRAM = 2760; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_CMD_SSA = 2761; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_CMD_SSA_LEN = 2762; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_VPC_SSA = 2763; // 1 -static const uint64_t SH_FLD_ARY_SELECT_ATX_VPC_SSA_LEN = 2764; // 1 -static const uint64_t SH_FLD_ARY_SELECT_CMD_RSP_SRAM = 2765; // 1 -static const uint64_t SH_FLD_ARY_SELECT_CMD_VRQ_SRAM = 2766; // 1 -static const uint64_t SH_FLD_ARY_SELECT_CRESP_SRAM = 2767; // 1 -static const uint64_t SH_FLD_ASSIGN_DONE = 2768; // 1 -static const uint64_t SH_FLD_ASYNC_IF_ERROR = 2769; // 16 -static const uint64_t SH_FLD_ASYNC_INJ = 2770; // 16 -static const uint64_t SH_FLD_ASYNC_INJ_LEN = 2771; // 16 -static const uint64_t SH_FLD_ASYNC_MODE = 2772; // 6 -static const uint64_t SH_FLD_ASYNC_OBS = 2773; // 43 -static const uint64_t SH_FLD_ASYNC_TYPE = 2774; // 43 -static const uint64_t SH_FLD_AS_RCMD0_PARITY_ERR_ERRHOLD = 2775; // 2 -static const uint64_t SH_FLD_AS_REGS_PARITY_ERR_ERRHOLD = 2776; // 2 -static const uint64_t SH_FLD_AS_REG_RDATA_PERR_ERRHOLD = 2777; // 2 -static const uint64_t SH_FLD_AS_SM_ERRHOLD = 2778; // 2 -static const uint64_t SH_FLD_ATAG_0_15 = 2779; // 1 -static const uint64_t SH_FLD_ATAG_0_15_LEN = 2780; // 1 -static const uint64_t SH_FLD_ATOMIC_ALT_CE_INJ = 2781; // 2 -static const uint64_t SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ = 2782; // 2 -static const uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL = 2783; // 2 -static const uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN = 2784; // 2 -static const uint64_t SH_FLD_ATOMIC_ALT_SUE_INJ = 2785; // 2 -static const uint64_t SH_FLD_ATOMIC_ALT_UE_INJ = 2786; // 2 -static const uint64_t SH_FLD_ATRMISS_ADDR = 2787; // 1 -static const uint64_t SH_FLD_ATRMISS_ADDR_LEN = 2788; // 1 -static const uint64_t SH_FLD_ATRMISS_BDF = 2789; // 1 -static const uint64_t SH_FLD_ATRMISS_BDF_LEN = 2790; // 1 -static const uint64_t SH_FLD_ATRMISS_ENA = 2791; // 1 -static const uint64_t SH_FLD_ATRMISS_FLAG_DMD = 2792; // 1 -static const uint64_t SH_FLD_ATRMISS_FLAG_FENCE = 2793; // 1 -static const uint64_t SH_FLD_ATRMISS_FLAG_MAP = 2794; // 1 -static const uint64_t SH_FLD_ATRMISS_FLAG_OTHER = 2795; // 1 -static const uint64_t SH_FLD_ATRMISS_FLAG_PREF = 2796; // 1 -static const uint64_t SH_FLD_ATRMISS_GPA = 2797; // 1 -static const uint64_t SH_FLD_ATRMISS_IRQENA = 2798; // 1 -static const uint64_t SH_FLD_ATRMISS_PASID = 2799; // 1 -static const uint64_t SH_FLD_ATRMISS_PASID_LEN = 2800; // 1 -static const uint64_t SH_FLD_ATRMISS_RETIRE = 2801; // 1 -static const uint64_t SH_FLD_ATRMISS_SECOND = 2802; // 1 -static const uint64_t SH_FLD_ATRMISS_TRIGGERED = 2803; // 1 -static const uint64_t SH_FLD_ATRR = 2804; // 3 -static const uint64_t SH_FLD_ATR_ARBSTATE = 2805; // 1 -static const uint64_t SH_FLD_ATR_ERR_INJ_PEND = 2806; // 1 -static const uint64_t SH_FLD_ATR_MISS_IRQ = 2807; // 1 -static const uint64_t SH_FLD_ATR_SM_STATE = 2808; // 1 -static const uint64_t SH_FLD_ATR_TIMEOUT = 2809; // 2 -static const uint64_t SH_FLD_ATR_TIMEOUT_LEN = 2810; // 1 -static const uint64_t SH_FLD_ATSD_BAD_TAG = 2811; // 1 -static const uint64_t SH_FLD_ATSD_SM_STATE = 2812; // 1 -static const uint64_t SH_FLD_ATSD_TIMEOUT = 2813; // 2 -static const uint64_t SH_FLD_ATSD_TIMEOUT_LEN = 2814; // 1 -static const uint64_t SH_FLD_ATSREQ = 2815; // 3 -static const uint64_t SH_FLD_ATSTSEL = 2816; // 17 -static const uint64_t SH_FLD_ATSTSEL_LEN = 2817; // 17 -static const uint64_t SH_FLD_ATSXLATE = 2818; // 12 -static const uint64_t SH_FLD_ATS_AT_EA_CE = 2819; // 1 -static const uint64_t SH_FLD_ATS_AT_EA_UE = 2820; // 1 -static const uint64_t SH_FLD_ATS_AT_RSPOUT_CE = 2821; // 1 -static const uint64_t SH_FLD_ATS_AT_RSPOUT_UE = 2822; // 1 -static const uint64_t SH_FLD_ATS_AT_TDRMEM_CE = 2823; // 1 -static const uint64_t SH_FLD_ATS_AT_TDRMEM_UE = 2824; // 1 -static const uint64_t SH_FLD_ATS_INVAL_IODA_TBL_SEL = 2825; // 1 -static const uint64_t SH_FLD_ATS_IODA_ADDR_PERR = 2826; // 1 -static const uint64_t SH_FLD_ATS_NPU_CTRL_PERR = 2827; // 1 -static const uint64_t SH_FLD_ATS_NPU_TOR_PERR = 2828; // 1 -static const uint64_t SH_FLD_ATS_RSVD_19 = 2829; // 1 -static const uint64_t SH_FLD_ATS_SYNC = 2830; // 3 -static const uint64_t SH_FLD_ATS_TCD_PERR = 2831; // 1 -static const uint64_t SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR = 2832; // 1 -static const uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR = 2833; // 1 -static const uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR = 2834; // 1 -static const uint64_t SH_FLD_ATS_TCE_REQ_TO_ERR = 2835; // 1 -static const uint64_t SH_FLD_ATS_TDR_PERR = 2836; // 1 -static const uint64_t SH_FLD_ATS_TVT_ADDR_RANGE_ERR = 2837; // 1 -static const uint64_t SH_FLD_ATS_TVT_ENTRY_INVALID = 2838; // 1 -static const uint64_t SH_FLD_ATS_TVT_PERR = 2839; // 1 -static const uint64_t SH_FLD_ATTENTION = 2840; // 1 -static const uint64_t SH_FLD_ATX_FOR_BLCK_UPD = 2841; // 1 -static const uint64_t SH_FLD_ATX_FOR_BLCK_UPD_LEN = 2842; // 1 -static const uint64_t SH_FLD_ATX_FOR_REGS = 2843; // 1 -static const uint64_t SH_FLD_ATX_FOR_REGS_LEN = 2844; // 1 -static const uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR = 2845; // 1 -static const uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN = 2846; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_CI_LD = 2847; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_CI_LD_LEN = 2848; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_DMA = 2849; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_DMA_LEN = 2850; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT = 2851; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT_LEN = 2852; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC = 2853; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN = 2854; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT = 2855; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_LEN = 2856; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC = 2857; // 1 -static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN = 2858; // 1 -static const uint64_t SH_FLD_ATX_LIMIT_AT_DEM_IN_PIPE = 2859; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP = 2860; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2861; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA = 2862; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN = 2863; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_IRQ = 2864; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_IRQ_LEN = 2865; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_IVC = 2866; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_IVC_LEN = 2867; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD = 2868; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2869; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_REGS = 2870; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_REGS_LEN = 2871; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA = 2872; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN = 2873; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP = 2874; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2875; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD = 2876; // 1 -static const uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN = 2877; // 1 -static const uint64_t SH_FLD_ATYPE = 2878; // 24 -static const uint64_t SH_FLD_ATYPE_LEN = 2879; // 24 -static const uint64_t SH_FLD_AT_EA_CE_ESR = 2880; // 1 -static const uint64_t SH_FLD_AT_EA_UE_ESR = 2881; // 1 -static const uint64_t SH_FLD_AT_TDRMEM_CE_ESR = 2882; // 1 -static const uint64_t SH_FLD_AT_TDRMEM_UE_ESR = 2883; // 1 -static const uint64_t SH_FLD_AUE = 2884; // 2 -static const uint64_t SH_FLD_AUE_LEN = 2885; // 2 -static const uint64_t SH_FLD_AUTOINC = 2886; // 12 -static const uint64_t SH_FLD_AUTO_INC = 2887; // 7 -static const uint64_t SH_FLD_AUTO_INCREMENT = 2888; // 3 -static const uint64_t SH_FLD_AUTO_INC_TRIG = 2889; // 6 -static const uint64_t SH_FLD_AUTO_INC_TRIG_LEN = 2890; // 6 -static const uint64_t SH_FLD_AUTO_POST_DECREMENT_FACES = 2891; // 1 -static const uint64_t SH_FLD_AUTO_POST_DECREMENT_PIB = 2892; // 1 -static const uint64_t SH_FLD_AUTO_PRE_INCREMENT_FACES = 2893; // 1 -static const uint64_t SH_FLD_AUTO_PRE_INCREMENT_PIB = 2894; // 1 -static const uint64_t SH_FLD_AUTO_RELOAD_N = 2895; // 2 -static const uint64_t SH_FLD_AUTO_STOP1_DISABLE = 2896; // 12 -static const uint64_t SH_FLD_AUTO_TDM_AND_NOT_OR = 2897; // 5 -static const uint64_t SH_FLD_AUTO_TDM_BW_DIFF = 2898; // 5 -static const uint64_t SH_FLD_AUTO_TDM_BW_DIFF_LEN = 2899; // 5 -static const uint64_t SH_FLD_AUTO_TDM_ERROR_RATE = 2900; // 5 -static const uint64_t SH_FLD_AUTO_TDM_ERROR_RATE_LEN = 2901; // 5 -static const uint64_t SH_FLD_AUTO_TDM_RX = 2902; // 5 -static const uint64_t SH_FLD_AUTO_TDM_TX = 2903; // 5 -static const uint64_t SH_FLD_AVA = 2904; // 8 -static const uint64_t SH_FLD_AVAIL_GROUPS = 2905; // 2 -static const uint64_t SH_FLD_AVAIL_GROUPS_LEN = 2906; // 2 -static const uint64_t SH_FLD_AVA_LEN = 2907; // 8 -static const uint64_t SH_FLD_AVG_CYCLE_SAMPLE = 2908; // 12 -static const uint64_t SH_FLD_AVG_CYCLE_SAMPLE_LEN = 2909; // 12 -static const uint64_t SH_FLD_AVG_FREQ_TSEL = 2910; // 12 -static const uint64_t SH_FLD_AVG_FREQ_TSEL_LEN = 2911; // 12 -static const uint64_t SH_FLD_AVS_SLAVE0 = 2912; // 1 -static const uint64_t SH_FLD_AVS_SLAVE1 = 2913; // 1 -static const uint64_t SH_FLD_AXFLOW_ERR = 2914; // 1 -static const uint64_t SH_FLD_AXFLOW_ERR_MASK = 2915; // 1 -static const uint64_t SH_FLD_AXPUSH_WRERR = 2916; // 1 -static const uint64_t SH_FLD_AXPUSH_WRERR_MASK = 2917; // 1 -static const uint64_t SH_FLD_AXRCV_DLO_ERR = 2918; // 1 -static const uint64_t SH_FLD_AXRCV_DLO_ERR_MASK = 2919; // 1 -static const uint64_t SH_FLD_AXRCV_DLO_TO = 2920; // 1 -static const uint64_t SH_FLD_AXRCV_DLO_TO_MASK = 2921; // 1 -static const uint64_t SH_FLD_AXRCV_RSVDATA_TO = 2922; // 1 -static const uint64_t SH_FLD_AXRCV_RSVDATA_TO_MASK = 2923; // 1 -static const uint64_t SH_FLD_AXSND_DHI_RTYTO = 2924; // 1 -static const uint64_t SH_FLD_AXSND_DHI_RTYTO_MASK = 2925; // 1 -static const uint64_t SH_FLD_AXSND_DLO_RTYTO = 2926; // 1 -static const uint64_t SH_FLD_AXSND_DLO_RTYTO_MASK = 2927; // 1 -static const uint64_t SH_FLD_AXSND_RSVERR = 2928; // 1 -static const uint64_t SH_FLD_AXSND_RSVERR_MASK = 2929; // 1 -static const uint64_t SH_FLD_AXSND_RSVTO = 2930; // 1 -static const uint64_t SH_FLD_AXSND_RSVTO_MASK = 2931; // 1 -static const uint64_t SH_FLD_A_AP = 2932; // 144 -static const uint64_t SH_FLD_A_AP_LEN = 2933; // 144 -static const uint64_t SH_FLD_A_BAD_DFE_CONV = 2934; // 144 -static const uint64_t SH_FLD_A_BANK_CONTROLS = 2935; // 48 -static const uint64_t SH_FLD_A_BANK_CONTROLS_LEN = 2936; // 48 -static const uint64_t SH_FLD_A_BIST_EN = 2937; // 6 -static const uint64_t SH_FLD_A_CONTROLS = 2938; // 120 -static const uint64_t SH_FLD_A_CONTROLS_LEN = 2939; // 120 -static const uint64_t SH_FLD_A_CTLE_COARSE = 2940; // 48 -static const uint64_t SH_FLD_A_CTLE_COARSE_LEN = 2941; // 48 -static const uint64_t SH_FLD_A_CTLE_GAIN = 2942; // 120 -static const uint64_t SH_FLD_A_CTLE_GAIN_LEN = 2943; // 120 -static const uint64_t SH_FLD_A_CTLE_PEAK = 2944; // 72 -static const uint64_t SH_FLD_A_CTLE_PEAK_LEN = 2945; // 72 -static const uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN = 2946; // 120 -static const uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN = 2947; // 120 -static const uint64_t SH_FLD_A_H10_VAL = 2948; // 72 -static const uint64_t SH_FLD_A_H10_VAL_LEN = 2949; // 72 -static const uint64_t SH_FLD_A_H11_VAL = 2950; // 72 -static const uint64_t SH_FLD_A_H11_VAL_LEN = 2951; // 72 -static const uint64_t SH_FLD_A_H12_VAL = 2952; // 72 -static const uint64_t SH_FLD_A_H12_VAL_LEN = 2953; // 72 -static const uint64_t SH_FLD_A_H1AP_AT_LIMIT = 2954; // 144 -static const uint64_t SH_FLD_A_H1ARATIO_VAL = 2955; // 72 -static const uint64_t SH_FLD_A_H1ARATIO_VAL_LEN = 2956; // 72 -static const uint64_t SH_FLD_A_H1CAL_EN = 2957; // 72 -static const uint64_t SH_FLD_A_H1CAL_VAL = 2958; // 72 -static const uint64_t SH_FLD_A_H1CAL_VAL_LEN = 2959; // 72 -static const uint64_t SH_FLD_A_H1E_VAL = 2960; // 120 -static const uint64_t SH_FLD_A_H1E_VAL_LEN = 2961; // 120 -static const uint64_t SH_FLD_A_H1O_VAL = 2962; // 120 -static const uint64_t SH_FLD_A_H1O_VAL_LEN = 2963; // 120 -static const uint64_t SH_FLD_A_H2E_VAL = 2964; // 72 -static const uint64_t SH_FLD_A_H2E_VAL_LEN = 2965; // 72 -static const uint64_t SH_FLD_A_H2O_VAL = 2966; // 72 -static const uint64_t SH_FLD_A_H2O_VAL_LEN = 2967; // 72 -static const uint64_t SH_FLD_A_H3E_VAL = 2968; // 72 -static const uint64_t SH_FLD_A_H3E_VAL_LEN = 2969; // 72 -static const uint64_t SH_FLD_A_H3O_VAL = 2970; // 72 -static const uint64_t SH_FLD_A_H3O_VAL_LEN = 2971; // 72 -static const uint64_t SH_FLD_A_H4E_VAL = 2972; // 72 -static const uint64_t SH_FLD_A_H4E_VAL_LEN = 2973; // 72 -static const uint64_t SH_FLD_A_H4O_VAL = 2974; // 72 -static const uint64_t SH_FLD_A_H4O_VAL_LEN = 2975; // 72 -static const uint64_t SH_FLD_A_H5E_VAL = 2976; // 72 -static const uint64_t SH_FLD_A_H5E_VAL_LEN = 2977; // 72 -static const uint64_t SH_FLD_A_H5O_VAL = 2978; // 72 -static const uint64_t SH_FLD_A_H5O_VAL_LEN = 2979; // 72 -static const uint64_t SH_FLD_A_H6_VAL = 2980; // 72 -static const uint64_t SH_FLD_A_H6_VAL_LEN = 2981; // 72 -static const uint64_t SH_FLD_A_H7_VAL = 2982; // 72 -static const uint64_t SH_FLD_A_H7_VAL_LEN = 2983; // 72 -static const uint64_t SH_FLD_A_H8_VAL = 2984; // 72 -static const uint64_t SH_FLD_A_H8_VAL_LEN = 2985; // 72 -static const uint64_t SH_FLD_A_H9_VAL = 2986; // 72 -static const uint64_t SH_FLD_A_H9_VAL_LEN = 2987; // 72 -static const uint64_t SH_FLD_A_INTEG_COARSE_GAIN = 2988; // 120 -static const uint64_t SH_FLD_A_INTEG_COARSE_GAIN_LEN = 2989; // 120 -static const uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN = 2990; // 120 -static const uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN = 2991; // 120 -static const uint64_t SH_FLD_A_OFFSET_E0 = 2992; // 120 -static const uint64_t SH_FLD_A_OFFSET_E0_LEN = 2993; // 120 -static const uint64_t SH_FLD_A_OFFSET_E1 = 2994; // 120 -static const uint64_t SH_FLD_A_OFFSET_E1_LEN = 2995; // 120 -static const uint64_t SH_FLD_A_OFFSET_O0 = 2996; // 120 -static const uint64_t SH_FLD_A_OFFSET_O0_LEN = 2997; // 120 -static const uint64_t SH_FLD_A_OFFSET_O1 = 2998; // 120 -static const uint64_t SH_FLD_A_OFFSET_O1_LEN = 2999; // 120 -static const uint64_t SH_FLD_A_PATH_OFF_EVEN = 3000; // 144 -static const uint64_t SH_FLD_A_PATH_OFF_EVEN_LEN = 3001; // 144 -static const uint64_t SH_FLD_A_PATH_OFF_ODD = 3002; // 144 -static const uint64_t SH_FLD_A_PATH_OFF_ODD_LEN = 3003; // 144 -static const uint64_t SH_FLD_A_PR_DFE_CLKADJ = 3004; // 120 -static const uint64_t SH_FLD_A_PR_DFE_CLKADJ_LEN = 3005; // 120 -static const uint64_t SH_FLD_B = 3006; // 8 -static const uint64_t SH_FLD_B0_63 = 3007; // 2 -static const uint64_t SH_FLD_B0_63_LEN = 3008; // 2 -static const uint64_t SH_FLD_B64_87 = 3009; // 2 -static const uint64_t SH_FLD_B64_87_LEN = 3010; // 2 -static const uint64_t SH_FLD_BACKUP_SEEPROM_SELECT = 3011; // 1 -static const uint64_t SH_FLD_BAD_128K_VP_OP = 3012; // 1 -static const uint64_t SH_FLD_BAD_ARRAY_ADDRESS_FACES = 3013; // 1 -static const uint64_t SH_FLD_BAD_ARRAY_ADDR_FACES = 3014; // 1 -static const uint64_t SH_FLD_BAD_ARRAY_ADDR_PIB = 3015; // 1 -static const uint64_t SH_FLD_BAD_BLOCK_LOCK = 3016; // 96 -static const uint64_t SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 3017; // 4 -static const uint64_t SH_FLD_BAD_DESKEW = 3018; // 96 -static const uint64_t SH_FLD_BAD_EYE_OPT_BER = 3019; // 96 -static const uint64_t SH_FLD_BAD_EYE_OPT_DDC = 3020; // 96 -static const uint64_t SH_FLD_BAD_EYE_OPT_HEIGHT = 3021; // 96 -static const uint64_t SH_FLD_BAD_EYE_OPT_WIDTH = 3022; // 96 -static const uint64_t SH_FLD_BAD_LANE1 = 3023; // 4 -static const uint64_t SH_FLD_BAD_LANE1_GCRMSG = 3024; // 4 -static const uint64_t SH_FLD_BAD_LANE1_GCRMSG_LEN = 3025; // 4 -static const uint64_t SH_FLD_BAD_LANE1_LEN = 3026; // 4 -static const uint64_t SH_FLD_BAD_LANE2 = 3027; // 4 -static const uint64_t SH_FLD_BAD_LANE2_GCRMSG = 3028; // 4 -static const uint64_t SH_FLD_BAD_LANE2_GCRMSG_LEN = 3029; // 4 -static const uint64_t SH_FLD_BAD_LANE2_LEN = 3030; // 4 -static const uint64_t SH_FLD_BAD_LANE_CODE = 3031; // 4 -static const uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG = 3032; // 4 -static const uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG_LEN = 3033; // 4 -static const uint64_t SH_FLD_BAD_LANE_CODE_LEN = 3034; // 4 -static const uint64_t SH_FLD_BAD_LANE_DURATION = 3035; // 2 -static const uint64_t SH_FLD_BAD_LANE_DURATION_LEN = 3036; // 2 -static const uint64_t SH_FLD_BAD_LANE_MAX = 3037; // 2 -static const uint64_t SH_FLD_BAD_LANE_MAX_LEN = 3038; // 2 -static const uint64_t SH_FLD_BAD_SKEW = 3039; // 96 -static const uint64_t SH_FLD_BANDSEL = 3040; // 20 -static const uint64_t SH_FLD_BANDSEL_LEN = 3041; // 20 -static const uint64_t SH_FLD_BANK = 3042; // 24 -static const uint64_t SH_FLD_BANK0_BIT_MAP = 3043; // 8 -static const uint64_t SH_FLD_BANK0_BIT_MAP_LEN = 3044; // 8 -static const uint64_t SH_FLD_BANK1_BIT_MAP = 3045; // 8 -static const uint64_t SH_FLD_BANK1_BIT_MAP_LEN = 3046; // 8 -static const uint64_t SH_FLD_BANK2_BIT_MAP = 3047; // 8 -static const uint64_t SH_FLD_BANK2_BIT_MAP_LEN = 3048; // 8 -static const uint64_t SH_FLD_BANK_GROUP0_BIT_MAP = 3049; // 8 -static const uint64_t SH_FLD_BANK_GROUP0_BIT_MAP_LEN = 3050; // 8 -static const uint64_t SH_FLD_BANK_GROUP1_BIT_MAP = 3051; // 8 -static const uint64_t SH_FLD_BANK_GROUP1_BIT_MAP_LEN = 3052; // 8 -static const uint64_t SH_FLD_BANK_ON_RUNN_MATCH = 3053; // 43 -static const uint64_t SH_FLD_BANK_PDWN = 3054; // 48 -static const uint64_t SH_FLD_BANK_PDWN_LEN = 3055; // 48 -static const uint64_t SH_FLD_BANK_SEL_A = 3056; // 48 -static const uint64_t SH_FLD_BAR = 3057; // 6 -static const uint64_t SH_FLD_BAR1_EN = 3058; // 4 -static const uint64_t SH_FLD_BAR1_MS_GROUP_CHIP = 3059; // 2 -static const uint64_t SH_FLD_BAR1_MS_GROUP_CHIP_LEN = 3060; // 2 -static const uint64_t SH_FLD_BAR1_SIZE = 3061; // 2 -static const uint64_t SH_FLD_BAR1_SIZE_LEN = 3062; // 2 -static const uint64_t SH_FLD_BAR1_STARTING_ADDRESS = 3063; // 4 -static const uint64_t SH_FLD_BAR1_STARTING_ADDRESS_LEN = 3064; // 4 -static const uint64_t SH_FLD_BAR1_SYSTEM = 3065; // 2 -static const uint64_t SH_FLD_BAR1_SYSTEM_LEN = 3066; // 2 -static const uint64_t SH_FLD_BARSEL = 3067; // 12 -static const uint64_t SH_FLD_BAR_LEN = 3068; // 6 -static const uint64_t SH_FLD_BAR_PE = 3069; // 4 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR1 = 3070; // 1 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR2 = 3071; // 1 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR3 = 3072; // 1 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR4 = 3073; // 1 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR5 = 3074; // 1 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR6 = 3075; // 1 -static const uint64_t SH_FLD_BAR_PIB_ON_ERROR7 = 3076; // 1 -static const uint64_t SH_FLD_BASE = 3077; // 26 -static const uint64_t SH_FLD_BASE_ADDR = 3078; // 2 -static const uint64_t SH_FLD_BASE_ADDR_LEN = 3079; // 2 -static const uint64_t SH_FLD_BASE_IDLE_COUNT = 3080; // 8 -static const uint64_t SH_FLD_BASE_IDLE_COUNT_LEN = 3081; // 8 -static const uint64_t SH_FLD_BASE_LEN = 3082; // 26 -static const uint64_t SH_FLD_BASE_UPPER_BITS = 3083; // 1 -static const uint64_t SH_FLD_BASE_UPPER_BITS_LEN = 3084; // 1 -static const uint64_t SH_FLD_BBUF_AIDX = 3085; // 3 -static const uint64_t SH_FLD_BBUF_AIDX_LEN = 3086; // 3 -static const uint64_t SH_FLD_BBUF_RSRC = 3087; // 3 -static const uint64_t SH_FLD_BBUF_RSRC_LEN = 3088; // 3 -static const uint64_t SH_FLD_BBUF_WSRC = 3089; // 3 -static const uint64_t SH_FLD_BBUF_WSRC_LEN = 3090; // 3 -static const uint64_t SH_FLD_BBWR_MASK = 3091; // 3 -static const uint64_t SH_FLD_BBWR_MASK_LEN = 3092; // 3 -static const uint64_t SH_FLD_BCAST_DONE = 3093; // 1 -static const uint64_t SH_FLD_BCDE_CE = 3094; // 1 -static const uint64_t SH_FLD_BCDE_CE_MASK = 3095; // 1 -static const uint64_t SH_FLD_BCDE_OCITRANS = 3096; // 1 -static const uint64_t SH_FLD_BCDE_OCITRANS_LEN = 3097; // 1 -static const uint64_t SH_FLD_BCDE_OCI_DATERR = 3098; // 1 -static const uint64_t SH_FLD_BCDE_OCI_DATERR_MASK = 3099; // 1 -static const uint64_t SH_FLD_BCDE_PB_ACK_DEAD = 3100; // 1 -static const uint64_t SH_FLD_BCDE_PB_ACK_DEAD_MASK = 3101; // 1 -static const uint64_t SH_FLD_BCDE_PB_ADRERR = 3102; // 1 -static const uint64_t SH_FLD_BCDE_PB_ADRERR_MASK = 3103; // 1 -static const uint64_t SH_FLD_BCDE_RDDATATO_ERR = 3104; // 1 -static const uint64_t SH_FLD_BCDE_RDDATATO_ERR_MASK = 3105; // 1 -static const uint64_t SH_FLD_BCDE_SETUP_ERR = 3106; // 1 -static const uint64_t SH_FLD_BCDE_SETUP_ERR_MASK = 3107; // 1 -static const uint64_t SH_FLD_BCDE_SUE_ERR = 3108; // 1 -static const uint64_t SH_FLD_BCDE_SUE_ERR_MASK = 3109; // 1 -static const uint64_t SH_FLD_BCDE_UE_ERR = 3110; // 1 -static const uint64_t SH_FLD_BCDE_UE_ERR_MASK = 3111; // 1 -static const uint64_t SH_FLD_BCESCR_OVERRIDE_EN = 3112; // 12 -static const uint64_t SH_FLD_BCE_BUSY_HIGH = 3113; // 12 -static const uint64_t SH_FLD_BCE_BUSY_LOW = 3114; // 12 -static const uint64_t SH_FLD_BCE_ERROR = 3115; // 13 -static const uint64_t SH_FLD_BCE_TIMEOUT = 3116; // 24 -static const uint64_t SH_FLD_BCUE_OCITRANS = 3117; // 1 -static const uint64_t SH_FLD_BCUE_OCITRANS_LEN = 3118; // 1 -static const uint64_t SH_FLD_BCUE_OCI_DATERR = 3119; // 1 -static const uint64_t SH_FLD_BCUE_OCI_DATERR_MASK = 3120; // 1 -static const uint64_t SH_FLD_BCUE_PB_ACK_DEAD = 3121; // 1 -static const uint64_t SH_FLD_BCUE_PB_ACK_DEAD_MASK = 3122; // 1 -static const uint64_t SH_FLD_BCUE_PB_ADRERR = 3123; // 1 -static const uint64_t SH_FLD_BCUE_PB_ADRERR_MASK = 3124; // 1 -static const uint64_t SH_FLD_BCUE_SETUP_ERR = 3125; // 1 -static const uint64_t SH_FLD_BCUE_SETUP_ERR_MASK = 3126; // 1 -static const uint64_t SH_FLD_BDF = 3127; // 52 -static const uint64_t SH_FLD_BDF2PE_00 = 3128; // 1 -static const uint64_t SH_FLD_BDF2PE_01 = 3129; // 1 -static const uint64_t SH_FLD_BDF2PE_02 = 3130; // 1 -static const uint64_t SH_FLD_BDF2PE_10 = 3131; // 1 -static const uint64_t SH_FLD_BDF2PE_11 = 3132; // 1 -static const uint64_t SH_FLD_BDF2PE_12 = 3133; // 1 -static const uint64_t SH_FLD_BDF2PE_20 = 3134; // 1 -static const uint64_t SH_FLD_BDF2PE_21 = 3135; // 1 -static const uint64_t SH_FLD_BDF2PE_22 = 3136; // 1 -static const uint64_t SH_FLD_BDF2PE_30 = 3137; // 1 -static const uint64_t SH_FLD_BDF2PE_31 = 3138; // 1 -static const uint64_t SH_FLD_BDF2PE_32 = 3139; // 1 -static const uint64_t SH_FLD_BDF2PE_40 = 3140; // 1 -static const uint64_t SH_FLD_BDF2PE_41 = 3141; // 1 -static const uint64_t SH_FLD_BDF2PE_42 = 3142; // 1 -static const uint64_t SH_FLD_BDF2PE_50 = 3143; // 1 -static const uint64_t SH_FLD_BDF2PE_51 = 3144; // 1 -static const uint64_t SH_FLD_BDF2PE_52 = 3145; // 1 -static const uint64_t SH_FLD_BDF_LEN = 3146; // 52 -static const uint64_t SH_FLD_BE = 3147; // 6 -static const uint64_t SH_FLD_BEAT_NUM = 3148; // 1 -static const uint64_t SH_FLD_BEAT_NUM_ERR = 3149; // 1 -static const uint64_t SH_FLD_BEAT_REC = 3150; // 1 -static const uint64_t SH_FLD_BEAT_REC_ERR = 3151; // 1 -static const uint64_t SH_FLD_BENIGN_PTR_DATA = 3152; // 2 -static const uint64_t SH_FLD_BER_CFG = 3153; // 120 -static const uint64_t SH_FLD_BER_CFG_LEN = 3154; // 120 -static const uint64_t SH_FLD_BER_CLR_COUNT_ON_READ_EN = 3155; // 6 -static const uint64_t SH_FLD_BER_CLR_TIMER_ON_READ_EN = 3156; // 6 -static const uint64_t SH_FLD_BER_COUNT_FREEZE_EN = 3157; // 6 -static const uint64_t SH_FLD_BER_COUNT_SEL = 3158; // 6 -static const uint64_t SH_FLD_BER_COUNT_SEL_LEN = 3159; // 6 -static const uint64_t SH_FLD_BER_DPIPE_MUX_SEL = 3160; // 120 -static const uint64_t SH_FLD_BER_EN = 3161; // 6 -static const uint64_t SH_FLD_BER_TIMEOUT = 3162; // 6 -static const uint64_t SH_FLD_BER_TIMEOUT_LEN = 3163; // 6 -static const uint64_t SH_FLD_BER_TIMER_FREEZE_EN = 3164; // 6 -static const uint64_t SH_FLD_BER_TIMER_SEL = 3165; // 6 -static const uint64_t SH_FLD_BER_TIMER_SEL_LEN = 3166; // 6 -static const uint64_t SH_FLD_BE_ACC_ERROR_0 = 3167; // 4 -static const uint64_t SH_FLD_BE_ACC_ERROR_1 = 3168; // 2 -static const uint64_t SH_FLD_BE_ACC_ERROR_2 = 3169; // 2 -static const uint64_t SH_FLD_BE_ACC_ERROR_3 = 3170; // 2 -static const uint64_t SH_FLD_BE_OV_ERROR_0 = 3171; // 4 -static const uint64_t SH_FLD_BE_OV_ERROR_1 = 3172; // 2 -static const uint64_t SH_FLD_BE_OV_ERROR_2 = 3173; // 2 -static const uint64_t SH_FLD_BE_OV_ERROR_3 = 3174; // 2 -static const uint64_t SH_FLD_BGOFFSET = 3175; // 14 -static const uint64_t SH_FLD_BGOFFSET_LEN = 3176; // 14 -static const uint64_t SH_FLD_BG_SCAN_RATE = 3177; // 3 -static const uint64_t SH_FLD_BG_SCAN_RATE_LEN = 3178; // 3 -static const uint64_t SH_FLD_BHR_DIR_STATE = 3179; // 2 -static const uint64_t SH_FLD_BHR_DIR_STATE_LEN = 3180; // 2 -static const uint64_t SH_FLD_BIG_RSP = 3181; // 1 -static const uint64_t SH_FLD_BIG_STEP = 3182; // 8 -static const uint64_t SH_FLD_BIG_STEP_LEN = 3183; // 8 -static const uint64_t SH_FLD_BISTCLK_EN = 3184; // 2 -static const uint64_t SH_FLD_BISTCLK_EN_LEN = 3185; // 2 -static const uint64_t SH_FLD_BIST_BIT_FAIL_TH = 3186; // 1 -static const uint64_t SH_FLD_BIST_BIT_FAIL_TH_LEN = 3187; // 1 -static const uint64_t SH_FLD_BIST_BUS_DATA_MODE = 3188; // 6 -static const uint64_t SH_FLD_BIST_COMPLETE = 3189; // 1 -static const uint64_t SH_FLD_BIST_CUPLL_LOCK_CHECK_EN = 3190; // 6 -static const uint64_t SH_FLD_BIST_CU_PLL_ERR = 3191; // 4 -static const uint64_t SH_FLD_BIST_DONE = 3192; // 6 -static const uint64_t SH_FLD_BIST_EN = 3193; // 13 -static const uint64_t SH_FLD_BIST_ENABLE = 3194; // 1 -static const uint64_t SH_FLD_BIST_ERR = 3195; // 96 -static const uint64_t SH_FLD_BIST_ERROR = 3196; // 1 -static const uint64_t SH_FLD_BIST_ERROR_LEN = 3197; // 1 -static const uint64_t SH_FLD_BIST_ERR_A = 3198; // 48 -static const uint64_t SH_FLD_BIST_ERR_B = 3199; // 48 -static const uint64_t SH_FLD_BIST_ERR_E = 3200; // 48 -static const uint64_t SH_FLD_BIST_EXT_START_MODE = 3201; // 6 -static const uint64_t SH_FLD_BIST_EYE_A_WIDTH = 3202; // 6 -static const uint64_t SH_FLD_BIST_EYE_A_WIDTH_LEN = 3203; // 6 -static const uint64_t SH_FLD_BIST_EYE_B_WIDTH = 3204; // 6 -static const uint64_t SH_FLD_BIST_EYE_B_WIDTH_LEN = 3205; // 6 -static const uint64_t SH_FLD_BIST_INIT_DISABLE = 3206; // 6 -static const uint64_t SH_FLD_BIST_INIT_DISABLE_LEN = 3207; // 6 -static const uint64_t SH_FLD_BIST_INIT_DONE = 3208; // 6 -static const uint64_t SH_FLD_BIST_JITTER_PULSE_SEL = 3209; // 4 -static const uint64_t SH_FLD_BIST_JITTER_PULSE_SEL_LEN = 3210; // 4 -static const uint64_t SH_FLD_BIST_LL_ERR = 3211; // 2 -static const uint64_t SH_FLD_BIST_LL_TEST_EN = 3212; // 2 -static const uint64_t SH_FLD_BIST_MIN_EYE_WIDTH = 3213; // 6 -static const uint64_t SH_FLD_BIST_MIN_EYE_WIDTH_LEN = 3214; // 6 -static const uint64_t SH_FLD_BIST_NO_EDGE_DET = 3215; // 6 -static const uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT = 3216; // 4 -static const uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN = 3217; // 4 -static const uint64_t SH_FLD_BIST_PRBS_PROP_TIME = 3218; // 6 -static const uint64_t SH_FLD_BIST_PRBS_PROP_TIME_LEN = 3219; // 6 -static const uint64_t SH_FLD_BIST_PRBS_TEST_TIME = 3220; // 6 -static const uint64_t SH_FLD_BIST_PRBS_TEST_TIME_LEN = 3221; // 6 -static const uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL = 3222; // 6 -static const uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN = 3223; // 6 -static const uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL = 3224; // 6 -static const uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN = 3225; // 6 -static const uint64_t SH_FLD_BITS = 3226; // 27 -static const uint64_t SH_FLD_BITSEL = 3227; // 4 -static const uint64_t SH_FLD_BITSEL_LEN = 3228; // 4 -static const uint64_t SH_FLD_BITS_LEN = 3229; // 27 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_0 = 3230; // 6 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_0_LEN = 3231; // 6 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_1 = 3232; // 3 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_1_LEN = 3233; // 3 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_2 = 3234; // 3 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_2_LEN = 3235; // 3 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_3 = 3236; // 3 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_3_LEN = 3237; // 3 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE = 3238; // 1 -static const uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN = 3239; // 1 -static const uint64_t SH_FLD_BKINV_INTERLOCK_DIS = 3240; // 1 -static const uint64_t SH_FLD_BKLG0 = 3241; // 1 -static const uint64_t SH_FLD_BKLG0_LEN = 3242; // 1 -static const uint64_t SH_FLD_BKLG1 = 3243; // 1 -static const uint64_t SH_FLD_BKLG1_LEN = 3244; // 1 -static const uint64_t SH_FLD_BKLG2 = 3245; // 1 -static const uint64_t SH_FLD_BKLG2_LEN = 3246; // 1 -static const uint64_t SH_FLD_BKLG3 = 3247; // 1 -static const uint64_t SH_FLD_BKLG3_LEN = 3248; // 1 -static const uint64_t SH_FLD_BKLG4 = 3249; // 1 -static const uint64_t SH_FLD_BKLG4_LEN = 3250; // 1 -static const uint64_t SH_FLD_BKLG5 = 3251; // 1 -static const uint64_t SH_FLD_BKLG5_LEN = 3252; // 1 -static const uint64_t SH_FLD_BKLG6 = 3253; // 1 -static const uint64_t SH_FLD_BKLG6_LEN = 3254; // 1 -static const uint64_t SH_FLD_BKLG7 = 3255; // 1 -static const uint64_t SH_FLD_BKLG7_LEN = 3256; // 1 -static const uint64_t SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR = 3257; // 6 -static const uint64_t SH_FLD_BLK_UPDT_DONE = 3258; // 1 -static const uint64_t SH_FLD_BLOCK = 3259; // 24 -static const uint64_t SH_FLD_BLOCKID = 3260; // 15 -static const uint64_t SH_FLD_BLOCKID_LEN = 3261; // 15 -static const uint64_t SH_FLD_BLOCKY0 = 3262; // 24 -static const uint64_t SH_FLD_BLOCKY1 = 3263; // 24 -static const uint64_t SH_FLD_BLOCK_ACTIVE = 3264; // 6 -static const uint64_t SH_FLD_BLOCK_CMD_OVERLAP = 3265; // 1 -static const uint64_t SH_FLD_BLOCK_INTR_INPUTS = 3266; // 24 -static const uint64_t SH_FLD_BLOCK_LEN = 3267; // 24 -static const uint64_t SH_FLD_BLOCK_MUX_PORT_SEL = 3268; // 2 -static const uint64_t SH_FLD_BLOCK_MUX_PORT_SEL_LEN = 3269; // 2 -static const uint64_t SH_FLD_BLOCK_SEL = 3270; // 2 -static const uint64_t SH_FLD_BLOCK_SEL_LEN = 3271; // 2 -static const uint64_t SH_FLD_BNDY = 3272; // 43 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD0 = 3273; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD0_LEN = 3274; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD1 = 3275; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD1_LEN = 3276; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD2 = 3277; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD2_LEN = 3278; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD3 = 3279; // 1 -static const uint64_t SH_FLD_BOOT_VECTOR_WORD3_LEN = 3280; // 1 -static const uint64_t SH_FLD_BRAZOS = 3281; // 1 -static const uint64_t SH_FLD_BREAKPOINT_ERROR = 3282; // 1 -static const uint64_t SH_FLD_BRICK = 3283; // 16 -static const uint64_t SH_FLD_BRICK_DEBUG_MODE = 3284; // 6 -static const uint64_t SH_FLD_BRICK_ENABLE = 3285; // 6 -static const uint64_t SH_FLD_BRIDGE_ENABLE = 3286; // 1 -static const uint64_t SH_FLD_BRINGUP = 3287; // 4 -static const uint64_t SH_FLD_BRINGUP_LEN = 3288; // 4 -static const uint64_t SH_FLD_BRK0 = 3289; // 1 -static const uint64_t SH_FLD_BRK0_CLUSTER = 3290; // 1 -static const uint64_t SH_FLD_BRK0_CLUSTER_LEN = 3291; // 1 -static const uint64_t SH_FLD_BRK0_NVL = 3292; // 3 -static const uint64_t SH_FLD_BRK0_RLX = 3293; // 3 -static const uint64_t SH_FLD_BRK1 = 3294; // 1 -static const uint64_t SH_FLD_BRK1_CLUSTER = 3295; // 1 -static const uint64_t SH_FLD_BRK1_CLUSTER_LEN = 3296; // 1 -static const uint64_t SH_FLD_BRK1_NVL = 3297; // 3 -static const uint64_t SH_FLD_BRK1_RLX = 3298; // 3 -static const uint64_t SH_FLD_BRK2 = 3299; // 1 -static const uint64_t SH_FLD_BRK2_CLUSTER = 3300; // 1 -static const uint64_t SH_FLD_BRK2_CLUSTER_LEN = 3301; // 1 -static const uint64_t SH_FLD_BRK3 = 3302; // 1 -static const uint64_t SH_FLD_BRK3_CLUSTER = 3303; // 1 -static const uint64_t SH_FLD_BRK3_CLUSTER_LEN = 3304; // 1 -static const uint64_t SH_FLD_BRK4 = 3305; // 1 -static const uint64_t SH_FLD_BRK4_CLUSTER = 3306; // 1 -static const uint64_t SH_FLD_BRK4_CLUSTER_LEN = 3307; // 1 -static const uint64_t SH_FLD_BRK5 = 3308; // 1 -static const uint64_t SH_FLD_BRK5_CLUSTER = 3309; // 1 -static const uint64_t SH_FLD_BRK5_CLUSTER_LEN = 3310; // 1 -static const uint64_t SH_FLD_BROADCAST_SYNC_EN = 3311; // 2 -static const uint64_t SH_FLD_BROADCAST_SYNC_WAIT = 3312; // 2 -static const uint64_t SH_FLD_BROADCAST_SYNC_WAIT_LEN = 3313; // 2 -static const uint64_t SH_FLD_BUF0_REG_DATA0 = 3314; // 2 -static const uint64_t SH_FLD_BUF0_REG_DATA0_LEN = 3315; // 2 -static const uint64_t SH_FLD_BUF1_REG_DATA0 = 3316; // 1 -static const uint64_t SH_FLD_BUF1_REG_DATA0_LEN = 3317; // 1 -static const uint64_t SH_FLD_BUF1_REG_DATA1 = 3318; // 1 -static const uint64_t SH_FLD_BUF1_REG_DATA1_LEN = 3319; // 1 -static const uint64_t SH_FLD_BUFFER = 3320; // 12 -static const uint64_t SH_FLD_BUFFER_OVERRUN = 3321; // 8 -static const uint64_t SH_FLD_BUFFER_STATUS = 3322; // 6 -static const uint64_t SH_FLD_BUFFER_STATUS_LEN = 3323; // 6 -static const uint64_t SH_FLD_BUF_ALLOC_A = 3324; // 4 -static const uint64_t SH_FLD_BUF_ALLOC_B = 3325; // 4 -static const uint64_t SH_FLD_BUF_ALLOC_C = 3326; // 4 -static const uint64_t SH_FLD_BUF_ALLOC_W = 3327; // 4 -static const uint64_t SH_FLD_BUF_INVALIDATE_CTL = 3328; // 4 -static const uint64_t SH_FLD_BURST_WINDOW = 3329; // 8 -static const uint64_t SH_FLD_BURST_WINDOW_LEN = 3330; // 8 -static const uint64_t SH_FLD_BUSY = 3331; // 44 -static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0 = 3332; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN = 3333; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1 = 3334; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN = 3335; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2 = 3336; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN = 3337; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT = 3338; // 8 -static const uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN = 3339; // 8 -static const uint64_t SH_FLD_BUSY_ENABLE = 3340; // 3 -static const uint64_t SH_FLD_BUSY_RESPONSE_CODE = 3341; // 1 -static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_LEN = 3342; // 1 -static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1 = 3343; // 1 -static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN = 3344; // 1 -static const uint64_t SH_FLD_BUSY_STATUS = 3345; // 1 -static const uint64_t SH_FLD_BUSY_STATUS_LEN = 3346; // 1 -static const uint64_t SH_FLD_BUS_ADDR_NVLD_0 = 3347; // 1 -static const uint64_t SH_FLD_BUS_ADDR_NVLD_1 = 3348; // 1 -static const uint64_t SH_FLD_BUS_ADDR_NVLD_2 = 3349; // 1 -static const uint64_t SH_FLD_BUS_ADDR_NVLD_3 = 3350; // 1 -static const uint64_t SH_FLD_BUS_ADDR_P_ERR_0 = 3351; // 1 -static const uint64_t SH_FLD_BUS_ADDR_P_ERR_1 = 3352; // 1 -static const uint64_t SH_FLD_BUS_ADDR_P_ERR_2 = 3353; // 1 -static const uint64_t SH_FLD_BUS_ADDR_P_ERR_3 = 3354; // 1 -static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 = 3355; // 1 -static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 = 3356; // 1 -static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 = 3357; // 1 -static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 = 3358; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 = 3359; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 = 3360; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 = 3361; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 = 3362; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 = 3363; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 = 3364; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 = 3365; // 1 -static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 = 3366; // 1 -static const uint64_t SH_FLD_BUS_BUSY_0 = 3367; // 1 -static const uint64_t SH_FLD_BUS_BUSY_1 = 3368; // 1 -static const uint64_t SH_FLD_BUS_BUSY_2 = 3369; // 1 -static const uint64_t SH_FLD_BUS_BUSY_3 = 3370; // 1 -static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_0 = 3371; // 1 -static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_1 = 3372; // 1 -static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_2 = 3373; // 1 -static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_3 = 3374; // 1 -static const uint64_t SH_FLD_BUS_DATA_REQUEST_0 = 3375; // 1 -static const uint64_t SH_FLD_BUS_DATA_REQUEST_1 = 3376; // 1 -static const uint64_t SH_FLD_BUS_DATA_REQUEST_2 = 3377; // 1 -static const uint64_t SH_FLD_BUS_DATA_REQUEST_3 = 3378; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0 = 3379; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN = 3380; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1 = 3381; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN = 3382; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2 = 3383; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN = 3384; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3 = 3385; // 1 -static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN = 3386; // 1 -static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_0 = 3387; // 1 -static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_1 = 3388; // 1 -static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_2 = 3389; // 1 -static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_3 = 3390; // 1 -static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_0 = 3391; // 1 -static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_1 = 3392; // 1 -static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_2 = 3393; // 1 -static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_3 = 3394; // 1 -static const uint64_t SH_FLD_BUS_ID = 3395; // 12 -static const uint64_t SH_FLD_BUS_ID_LEN = 3396; // 12 -static const uint64_t SH_FLD_BUS_INVALID_COMMAND_0 = 3397; // 1 -static const uint64_t SH_FLD_BUS_INVALID_COMMAND_1 = 3398; // 1 -static const uint64_t SH_FLD_BUS_INVALID_COMMAND_2 = 3399; // 1 -static const uint64_t SH_FLD_BUS_INVALID_COMMAND_3 = 3400; // 1 -static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_0 = 3401; // 1 -static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_1 = 3402; // 1 -static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_2 = 3403; // 1 -static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_3 = 3404; // 1 -static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_0 = 3405; // 1 -static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_1 = 3406; // 1 -static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_2 = 3407; // 1 -static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_3 = 3408; // 1 -static const uint64_t SH_FLD_BUS_PARITY_ERROR_0 = 3409; // 1 -static const uint64_t SH_FLD_BUS_PARITY_ERROR_1 = 3410; // 1 -static const uint64_t SH_FLD_BUS_PARITY_ERROR_2 = 3411; // 1 -static const uint64_t SH_FLD_BUS_PARITY_ERROR_3 = 3412; // 1 -static const uint64_t SH_FLD_BUS_PAR_ERR_0 = 3413; // 1 -static const uint64_t SH_FLD_BUS_PAR_ERR_1 = 3414; // 1 -static const uint64_t SH_FLD_BUS_PAR_ERR_2 = 3415; // 1 -static const uint64_t SH_FLD_BUS_PAR_ERR_3 = 3416; // 1 -static const uint64_t SH_FLD_BUS_READ_NVLD_0 = 3417; // 1 -static const uint64_t SH_FLD_BUS_READ_NVLD_1 = 3418; // 1 -static const uint64_t SH_FLD_BUS_READ_NVLD_2 = 3419; // 1 -static const uint64_t SH_FLD_BUS_READ_NVLD_3 = 3420; // 1 -static const uint64_t SH_FLD_BUS_STOP_ERROR_0 = 3421; // 1 -static const uint64_t SH_FLD_BUS_STOP_ERROR_1 = 3422; // 1 -static const uint64_t SH_FLD_BUS_STOP_ERROR_2 = 3423; // 1 -static const uint64_t SH_FLD_BUS_STOP_ERROR_3 = 3424; // 1 -static const uint64_t SH_FLD_BUS_WIDTH = 3425; // 4 -static const uint64_t SH_FLD_BUS_WIDTH_LEN = 3426; // 4 -static const uint64_t SH_FLD_BUS_WRITE_NVLD_0 = 3427; // 1 -static const uint64_t SH_FLD_BUS_WRITE_NVLD_1 = 3428; // 1 -static const uint64_t SH_FLD_BUS_WRITE_NVLD_2 = 3429; // 1 -static const uint64_t SH_FLD_BUS_WRITE_NVLD_3 = 3430; // 1 -static const uint64_t SH_FLD_BW_SAMPLE_SIZE = 3431; // 5 -static const uint64_t SH_FLD_BW_WINDOW_SIZE = 3432; // 5 -static const uint64_t SH_FLD_BYPASSCLKOUT = 3433; // 3 -static const uint64_t SH_FLD_BYPASSING_RESET_SEQUENCE_PIB_I2CM = 3434; // 1 -static const uint64_t SH_FLD_BYPASSN = 3435; // 10 -static const uint64_t SH_FLD_BYTE0_SEL = 3436; // 8 -static const uint64_t SH_FLD_BYTE0_SEL_LEN = 3437; // 8 -static const uint64_t SH_FLD_BYTE1_SEL = 3438; // 8 -static const uint64_t SH_FLD_BYTE1_SEL_LEN = 3439; // 8 -static const uint64_t SH_FLD_BYTE2_SEL = 3440; // 8 -static const uint64_t SH_FLD_BYTE2_SEL_LEN = 3441; // 8 -static const uint64_t SH_FLD_BYTE3_SEL = 3442; // 8 -static const uint64_t SH_FLD_BYTE3_SEL_LEN = 3443; // 8 -static const uint64_t SH_FLD_B_BAD_DFE_CONV = 3444; // 48 -static const uint64_t SH_FLD_B_BANK_CONTROLS = 3445; // 48 -static const uint64_t SH_FLD_B_BANK_CONTROLS_LEN = 3446; // 48 -static const uint64_t SH_FLD_B_BIST_EN = 3447; // 2 -static const uint64_t SH_FLD_B_CONTROLS = 3448; // 48 -static const uint64_t SH_FLD_B_CONTROLS_LEN = 3449; // 48 -static const uint64_t SH_FLD_B_CTLE_COARSE = 3450; // 48 -static const uint64_t SH_FLD_B_CTLE_COARSE_LEN = 3451; // 48 -static const uint64_t SH_FLD_B_CTLE_GAIN = 3452; // 48 -static const uint64_t SH_FLD_B_CTLE_GAIN_LEN = 3453; // 48 -static const uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN = 3454; // 48 -static const uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN = 3455; // 48 -static const uint64_t SH_FLD_B_H1AP_AT_LIMIT = 3456; // 48 -static const uint64_t SH_FLD_B_H1E_VAL = 3457; // 48 -static const uint64_t SH_FLD_B_H1E_VAL_LEN = 3458; // 48 -static const uint64_t SH_FLD_B_H1O_VAL = 3459; // 48 -static const uint64_t SH_FLD_B_H1O_VAL_LEN = 3460; // 48 -static const uint64_t SH_FLD_B_INTEG_COARSE_GAIN = 3461; // 48 -static const uint64_t SH_FLD_B_INTEG_COARSE_GAIN_LEN = 3462; // 48 -static const uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN = 3463; // 48 -static const uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN = 3464; // 48 -static const uint64_t SH_FLD_B_OFFSET_E0 = 3465; // 48 -static const uint64_t SH_FLD_B_OFFSET_E0_LEN = 3466; // 48 -static const uint64_t SH_FLD_B_OFFSET_E1 = 3467; // 48 -static const uint64_t SH_FLD_B_OFFSET_E1_LEN = 3468; // 48 -static const uint64_t SH_FLD_B_OFFSET_O0 = 3469; // 48 -static const uint64_t SH_FLD_B_OFFSET_O0_LEN = 3470; // 48 -static const uint64_t SH_FLD_B_OFFSET_O1 = 3471; // 48 -static const uint64_t SH_FLD_B_OFFSET_O1_LEN = 3472; // 48 -static const uint64_t SH_FLD_B_PATH_OFF_EVEN = 3473; // 48 -static const uint64_t SH_FLD_B_PATH_OFF_EVEN_LEN = 3474; // 48 -static const uint64_t SH_FLD_B_PATH_OFF_ODD = 3475; // 48 -static const uint64_t SH_FLD_B_PATH_OFF_ODD_LEN = 3476; // 48 -static const uint64_t SH_FLD_B_PR_DFE_CLKADJ = 3477; // 48 -static const uint64_t SH_FLD_B_PR_DFE_CLKADJ_LEN = 3478; // 48 -static const uint64_t SH_FLD_C0_DROPOUT_EVENT_COUNT = 3479; // 12 -static const uint64_t SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN = 3480; // 12 -static const uint64_t SH_FLD_C0_DROPOUT_INAROW_COUNT = 3481; // 12 -static const uint64_t SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN = 3482; // 12 -static const uint64_t SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE = 3483; // 12 -static const uint64_t SH_FLD_C1_COUNT_LT = 3484; // 86 -static const uint64_t SH_FLD_C1_COUNT_LT_LEN = 3485; // 86 -static const uint64_t SH_FLD_C1_DROPOUT_EVENT_COUNT = 3486; // 12 -static const uint64_t SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN = 3487; // 12 -static const uint64_t SH_FLD_C1_DROPOUT_INAROW_COUNT = 3488; // 12 -static const uint64_t SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN = 3489; // 12 -static const uint64_t SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE = 3490; // 12 -static const uint64_t SH_FLD_C1_INAROW_MODE = 3491; // 86 -static const uint64_t SH_FLD_C2_COUNT_LT = 3492; // 86 -static const uint64_t SH_FLD_C2_COUNT_LT_LEN = 3493; // 86 -static const uint64_t SH_FLD_C2_INAROW_MODE = 3494; // 86 -static const uint64_t SH_FLD_C405DCU_M_TIMEOUT = 3495; // 1 -static const uint64_t SH_FLD_C405DCU_M_TIMEOUT_MASK = 3496; // 1 -static const uint64_t SH_FLD_C405ICU_M_TIMEOUT = 3497; // 1 -static const uint64_t SH_FLD_C405ICU_M_TIMEOUT_MASK = 3498; // 1 -static const uint64_t SH_FLD_C405_DCU_ECC_CE = 3499; // 1 -static const uint64_t SH_FLD_C405_DCU_ECC_UE = 3500; // 1 -static const uint64_t SH_FLD_C405_ECC_CE = 3501; // 1 -static const uint64_t SH_FLD_C405_ECC_CE_MASK = 3502; // 1 -static const uint64_t SH_FLD_C405_ECC_UE = 3503; // 1 -static const uint64_t SH_FLD_C405_ECC_UE_MASK = 3504; // 1 -static const uint64_t SH_FLD_C405_ICU_ECC_CE = 3505; // 1 -static const uint64_t SH_FLD_C405_ICU_ECC_UE = 3506; // 1 -static const uint64_t SH_FLD_C405_OCI_MACHINECHECK = 3507; // 1 -static const uint64_t SH_FLD_C405_OCI_MACHINECHECK_MASK = 3508; // 1 -static const uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT = 3509; // 4 -static const uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT_LEN = 3510; // 4 -static const uint64_t SH_FLD_CACHE_DROPOUT_ENABLE = 3511; // 12 -static const uint64_t SH_FLD_CACHE_DROPOUT_EVENT_COUNT = 3512; // 12 -static const uint64_t SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN = 3513; // 12 -static const uint64_t SH_FLD_CACHE_DROPOUT_INAROW_COUNT = 3514; // 12 -static const uint64_t SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN = 3515; // 12 -static const uint64_t SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 3516; // 12 -static const uint64_t SH_FLD_CACHE_RD_CE = 3517; // 12 -static const uint64_t SH_FLD_CACHE_RD_CE_AND_UE = 3518; // 12 -static const uint64_t SH_FLD_CACHE_RD_SUE = 3519; // 12 -static const uint64_t SH_FLD_CACHE_RD_UE = 3520; // 12 -static const uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO = 3521; // 12 -static const uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO = 3522; // 12 -static const uint64_t SH_FLD_CAC_ALLOC_DIS = 3523; // 2 -static const uint64_t SH_FLD_CAC_PERR_CHK_DIS = 3524; // 2 -static const uint64_t SH_FLD_CAL0_PE = 3525; // 8 -static const uint64_t SH_FLD_CAL1_PE = 3526; // 8 -static const uint64_t SH_FLD_CAL2_PE = 3527; // 8 -static const uint64_t SH_FLD_CAL3_PE = 3528; // 8 -static const uint64_t SH_FLD_CALIBRATION_ENABLE = 3529; // 8 -static const uint64_t SH_FLD_CALRECAL = 3530; // 10 -static const uint64_t SH_FLD_CALREQ = 3531; // 10 -static const uint64_t SH_FLD_CAL_LANE_GCRMSG = 3532; // 4 -static const uint64_t SH_FLD_CAL_LANE_GCRMSG_LEN = 3533; // 4 -static const uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG = 3534; // 6 -static const uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG_LEN = 3535; // 6 -static const uint64_t SH_FLD_CAL_LANE_SEL = 3536; // 188 -static const uint64_t SH_FLD_CAL_LANE_VAL_GCRMSG = 3537; // 4 -static const uint64_t SH_FLD_CAL_SM_1HOT = 3538; // 8 -static const uint64_t SH_FLD_CAM256_MAX_CNT = 3539; // 6 -static const uint64_t SH_FLD_CAM256_MAX_CNT_LEN = 3540; // 6 -static const uint64_t SH_FLD_CAM_DISPLAY_REG_0 = 3541; // 1 -static const uint64_t SH_FLD_CAM_DISPLAY_REG_0_LEN = 3542; // 1 -static const uint64_t SH_FLD_CAM_DISPLAY_REG_1 = 3543; // 1 -static const uint64_t SH_FLD_CAM_DISPLAY_REG_1_LEN = 3544; // 1 -static const uint64_t SH_FLD_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD = 3545; // 2 -static const uint64_t SH_FLD_CAPSEL = 3546; // 4 -static const uint64_t SH_FLD_CASCADE = 3547; // 19 -static const uint64_t SH_FLD_CASCADE_LEN = 3548; // 19 -static const uint64_t SH_FLD_CC = 3549; // 10 -static const uint64_t SH_FLD_CCALBANDSEL = 3550; // 10 -static const uint64_t SH_FLD_CCALBANDSEL_LEN = 3551; // 10 -static const uint64_t SH_FLD_CCALCOMP = 3552; // 10 -static const uint64_t SH_FLD_CCALCVHOLD = 3553; // 10 -static const uint64_t SH_FLD_CCALERR = 3554; // 10 -static const uint64_t SH_FLD_CCALFMAX = 3555; // 10 -static const uint64_t SH_FLD_CCALFMIN = 3556; // 10 -static const uint64_t SH_FLD_CCALLOAD = 3557; // 10 -static const uint64_t SH_FLD_CCALMETH = 3558; // 10 -static const uint64_t SH_FLD_CCFG_GPTR = 3559; // 43 -static const uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ = 3560; // 2 -static const uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE = 3561; // 2 -static const uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ = 3562; // 2 -static const uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE = 3563; // 2 -static const uint64_t SH_FLD_CCS_CNTLQ_PE_HOLD_OUT = 3564; // 2 -static const uint64_t SH_FLD_CCS_FSM_INJ_MODE = 3565; // 2 -static const uint64_t SH_FLD_CCS_FSM_INJ_REG = 3566; // 2 -static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0 = 3567; // 2 -static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN = 3568; // 2 -static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1 = 3569; // 2 -static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN = 3570; // 2 -static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2 = 3571; // 2 -static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN = 3572; // 2 -static const uint64_t SH_FLD_CC_ACTIVITY_0 = 3573; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_0_LEN = 3574; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_1 = 3575; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_1_LEN = 3576; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_2 = 3577; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_2_LEN = 3578; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_3 = 3579; // 1 -static const uint64_t SH_FLD_CC_ACTIVITY_3_LEN = 3580; // 1 -static const uint64_t SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 3581; // 43 -static const uint64_t SH_FLD_CC_CTRL_OPCG_DONE_DC = 3582; // 43 -static const uint64_t SH_FLD_CC_ENABLE_0 = 3583; // 1 -static const uint64_t SH_FLD_CC_ENABLE_1 = 3584; // 1 -static const uint64_t SH_FLD_CC_ENABLE_2 = 3585; // 1 -static const uint64_t SH_FLD_CC_ENABLE_3 = 3586; // 1 -static const uint64_t SH_FLD_CC_ID_0 = 3587; // 1 -static const uint64_t SH_FLD_CC_ID_0_LEN = 3588; // 1 -static const uint64_t SH_FLD_CC_ID_1 = 3589; // 1 -static const uint64_t SH_FLD_CC_ID_1_LEN = 3590; // 1 -static const uint64_t SH_FLD_CC_ID_2 = 3591; // 1 -static const uint64_t SH_FLD_CC_ID_2_LEN = 3592; // 1 -static const uint64_t SH_FLD_CC_ID_3 = 3593; // 1 -static const uint64_t SH_FLD_CC_ID_3_LEN = 3594; // 1 -static const uint64_t SH_FLD_CC_MASK = 3595; // 8 -static const uint64_t SH_FLD_CC_READ_ENABLE_0 = 3596; // 1 -static const uint64_t SH_FLD_CC_READ_ENABLE_1 = 3597; // 1 -static const uint64_t SH_FLD_CC_READ_ENABLE_2 = 3598; // 1 -static const uint64_t SH_FLD_CC_READ_ENABLE_3 = 3599; // 1 -static const uint64_t SH_FLD_CC_WRITE_ENABLE_0 = 3600; // 1 -static const uint64_t SH_FLD_CC_WRITE_ENABLE_1 = 3601; // 1 -static const uint64_t SH_FLD_CC_WRITE_ENABLE_2 = 3602; // 1 -static const uint64_t SH_FLD_CC_WRITE_ENABLE_3 = 3603; // 1 -static const uint64_t SH_FLD_CD_ALL_DONE_GCRMSG = 3604; // 4 -static const uint64_t SH_FLD_CD_PREV_DONE_GCRMSG = 3605; // 4 -static const uint64_t SH_FLD_CE = 3606; // 53 -static const uint64_t SH_FLD_CE1_0_OUT = 3607; // 4 -static const uint64_t SH_FLD_CE1_1_OUT = 3608; // 4 -static const uint64_t SH_FLD_CE1_2_OUT = 3609; // 4 -static const uint64_t SH_FLD_CE1_3_OUT = 3610; // 4 -static const uint64_t SH_FLD_CE1_4_OUT = 3611; // 4 -static const uint64_t SH_FLD_CE1_5_OUT = 3612; // 4 -static const uint64_t SH_FLD_CE1_6_OUT = 3613; // 4 -static const uint64_t SH_FLD_CE1_7_OUT = 3614; // 4 -static const uint64_t SH_FLD_CE2_0_OUT = 3615; // 4 -static const uint64_t SH_FLD_CE2_1_OUT = 3616; // 4 -static const uint64_t SH_FLD_CE2_2_OUT = 3617; // 4 -static const uint64_t SH_FLD_CE2_3_OUT = 3618; // 4 -static const uint64_t SH_FLD_CE2_4_OUT = 3619; // 4 -static const uint64_t SH_FLD_CE2_5_OUT = 3620; // 4 -static const uint64_t SH_FLD_CE2_6_OUT = 3621; // 4 -static const uint64_t SH_FLD_CE2_7_OUT = 3622; // 4 -static const uint64_t SH_FLD_CEC_PSI_INTERRUPT = 3623; // 1 -static const uint64_t SH_FLD_CENTAURP_ENABLE_BYPASS_CMD = 3624; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD = 3625; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_CP_ME = 3626; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND = 3627; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_DTAG_CR = 3628; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC = 3629; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_ECRESP = 3630; // 4 -static const uint64_t SH_FLD_CENTAURP_ENABLE_NEW_AMO = 3631; // 4 -static const uint64_t SH_FLD_CENTAURP_INBAND_IS_63 = 3632; // 4 -static const uint64_t SH_FLD_CENTAUR_MODE = 3633; // 4 -static const uint64_t SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED = 3634; // 4 -static const uint64_t SH_FLD_CERR_AXFLOW_ERR = 3635; // 1 -static const uint64_t SH_FLD_CERR_AXFLOW_ERR_LEN = 3636; // 1 -static const uint64_t SH_FLD_CERR_AXPUSH_WRERR = 3637; // 1 -static const uint64_t SH_FLD_CERR_AXPUSH_WRERR_LEN = 3638; // 1 -static const uint64_t SH_FLD_CERR_BAR_PARITY_ERR = 3639; // 1 -static const uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR = 3640; // 1 -static const uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN = 3641; // 1 -static const uint64_t SH_FLD_CERR_BCDE_SETUP_ERR = 3642; // 1 -static const uint64_t SH_FLD_CERR_BCDE_SETUP_ERR_LEN = 3643; // 1 -static const uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR = 3644; // 1 -static const uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN = 3645; // 1 -static const uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR = 3646; // 1 -static const uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR_LEN = 3647; // 1 -static const uint64_t SH_FLD_CERR_BCUE_SETUP_ERR = 3648; // 1 -static const uint64_t SH_FLD_CERR_BCUE_SETUP_ERR_LEN = 3649; // 1 -static const uint64_t SH_FLD_CERR_PBDOUT_PARITY_ERR = 3650; // 1 -static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD = 3651; // 1 -static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN = 3652; // 1 -static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR = 3653; // 1 -static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN = 3654; // 1 -static const uint64_t SH_FLD_CERR_PB_BADCRESP = 3655; // 1 -static const uint64_t SH_FLD_CERR_PB_BADCRESP_LEN = 3656; // 1 -static const uint64_t SH_FLD_CERR_PB_OPERTO = 3657; // 1 -static const uint64_t SH_FLD_CERR_PB_OPERTO_LEN = 3658; // 1 -static const uint64_t SH_FLD_CERR_PB_PARITY_ERR = 3659; // 1 -static const uint64_t SH_FLD_CERR_PB_PARITY_ERR_LEN = 3660; // 1 -static const uint64_t SH_FLD_CERR_PB_RDADRERR_FW = 3661; // 1 -static const uint64_t SH_FLD_CERR_PB_RDADRERR_FW_LEN = 3662; // 1 -static const uint64_t SH_FLD_CERR_PB_RDDATATO_FW = 3663; // 1 -static const uint64_t SH_FLD_CERR_PB_RDDATATO_FW_LEN = 3664; // 1 -static const uint64_t SH_FLD_CERR_PB_UNEXPCRESP = 3665; // 1 -static const uint64_t SH_FLD_CERR_PB_UNEXPCRESP_LEN = 3666; // 1 -static const uint64_t SH_FLD_CERR_PB_UNEXPDATA = 3667; // 1 -static const uint64_t SH_FLD_CERR_PB_UNEXPDATA_LEN = 3668; // 1 -static const uint64_t SH_FLD_CERR_PB_WRADRERR_FW = 3669; // 1 -static const uint64_t SH_FLD_CERR_PB_WRADRERR_FW_LEN = 3670; // 1 -static const uint64_t SH_FLD_CERR_SCOMTB_ERR = 3671; // 1 -static const uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR = 3672; // 1 -static const uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR_LEN = 3673; // 1 -static const uint64_t SH_FLD_CERR_SPARE = 3674; // 1 -static const uint64_t SH_FLD_CERR_SPARE_LEN = 3675; // 1 -static const uint64_t SH_FLD_CE_LEN = 3676; // 10 -static const uint64_t SH_FLD_CFG = 3677; // 46 -static const uint64_t SH_FLD_CFG_0_1_OP = 3678; // 2 -static const uint64_t SH_FLD_CFG_0_1_OP_LEN = 3679; // 2 -static const uint64_t SH_FLD_CFG_10_11_OP = 3680; // 2 -static const uint64_t SH_FLD_CFG_10_11_OP_LEN = 3681; // 2 -static const uint64_t SH_FLD_CFG_12_13_OP = 3682; // 2 -static const uint64_t SH_FLD_CFG_12_13_OP_LEN = 3683; // 2 -static const uint64_t SH_FLD_CFG_14_15_OP = 3684; // 2 -static const uint64_t SH_FLD_CFG_14_15_OP_LEN = 3685; // 2 -static const uint64_t SH_FLD_CFG_16_17_OP = 3686; // 2 -static const uint64_t SH_FLD_CFG_16_17_OP_LEN = 3687; // 2 -static const uint64_t SH_FLD_CFG_18_19_OP = 3688; // 2 -static const uint64_t SH_FLD_CFG_18_19_OP_LEN = 3689; // 2 -static const uint64_t SH_FLD_CFG_20_21_OP = 3690; // 2 -static const uint64_t SH_FLD_CFG_20_21_OP_LEN = 3691; // 2 -static const uint64_t SH_FLD_CFG_22_23_OP = 3692; // 2 -static const uint64_t SH_FLD_CFG_22_23_OP_LEN = 3693; // 2 -static const uint64_t SH_FLD_CFG_24_25_OP = 3694; // 2 -static const uint64_t SH_FLD_CFG_24_25_OP_LEN = 3695; // 2 -static const uint64_t SH_FLD_CFG_26_27_OP = 3696; // 2 -static const uint64_t SH_FLD_CFG_26_27_OP_LEN = 3697; // 2 -static const uint64_t SH_FLD_CFG_28_29_OP = 3698; // 2 -static const uint64_t SH_FLD_CFG_28_29_OP_LEN = 3699; // 2 -static const uint64_t SH_FLD_CFG_2N_ADDR = 3700; // 8 -static const uint64_t SH_FLD_CFG_2_3_OP = 3701; // 2 -static const uint64_t SH_FLD_CFG_2_3_OP_LEN = 3702; // 2 -static const uint64_t SH_FLD_CFG_30_31_OP = 3703; // 2 -static const uint64_t SH_FLD_CFG_30_31_OP_LEN = 3704; // 2 -static const uint64_t SH_FLD_CFG_4_5_OP = 3705; // 2 -static const uint64_t SH_FLD_CFG_4_5_OP_LEN = 3706; // 2 -static const uint64_t SH_FLD_CFG_6_7_OP = 3707; // 2 -static const uint64_t SH_FLD_CFG_6_7_OP_LEN = 3708; // 2 -static const uint64_t SH_FLD_CFG_8_9_OP = 3709; // 2 -static const uint64_t SH_FLD_CFG_8_9_OP_LEN = 3710; // 2 -static const uint64_t SH_FLD_CFG_ACM_EN = 3711; // 1 -static const uint64_t SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME = 3712; // 8 -static const uint64_t SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 3713; // 8 -static const uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY = 3714; // 8 -static const uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 3715; // 8 -static const uint64_t SH_FLD_CFG_ADDRESS_COUNTER = 3716; // 2 -static const uint64_t SH_FLD_CFG_ADDRESS_COUNTER_LEN = 3717; // 2 -static const uint64_t SH_FLD_CFG_ADDR_BAR = 3718; // 6 -static const uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE = 3719; // 2 -static const uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE_LEN = 3720; // 2 -static const uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH = 3721; // 8 -static const uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN = 3722; // 8 -static const uint64_t SH_FLD_CFG_ALL_PERIODIC_TB = 3723; // 8 -static const uint64_t SH_FLD_CFG_ALL_PERIODIC_TB_LEN = 3724; // 8 -static const uint64_t SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME = 3725; // 8 -static const uint64_t SH_FLD_CFG_AMAP_BANK0 = 3726; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK0_LEN = 3727; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK1 = 3728; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK1_LEN = 3729; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK2 = 3730; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK2_LEN = 3731; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0 = 3732; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0_LEN = 3733; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1 = 3734; // 2 -static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1_LEN = 3735; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL2 = 3736; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL2_LEN = 3737; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL3 = 3738; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL3_LEN = 3739; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL4 = 3740; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL4_LEN = 3741; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL5 = 3742; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL5_LEN = 3743; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL6 = 3744; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL6_LEN = 3745; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL7 = 3746; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL7_LEN = 3747; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL8 = 3748; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL8_LEN = 3749; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL9 = 3750; // 2 -static const uint64_t SH_FLD_CFG_AMAP_COL9_LEN = 3751; // 2 -static const uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT = 3752; // 2 -static const uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT_LEN = 3753; // 2 -static const uint64_t SH_FLD_CFG_AMAP_MRANK0 = 3754; // 2 -static const uint64_t SH_FLD_CFG_AMAP_MRANK0_LEN = 3755; // 2 -static const uint64_t SH_FLD_CFG_AMAP_MRANK1 = 3756; // 2 -static const uint64_t SH_FLD_CFG_AMAP_MRANK1_LEN = 3757; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW0 = 3758; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW0_LEN = 3759; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW1 = 3760; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW10 = 3761; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW10_LEN = 3762; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW11 = 3763; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW11_LEN = 3764; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW12 = 3765; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW12_LEN = 3766; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW13 = 3767; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW13_LEN = 3768; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW14 = 3769; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW14_LEN = 3770; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW15 = 3771; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW15_LEN = 3772; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW16 = 3773; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW16_LEN = 3774; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW17 = 3775; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW17_LEN = 3776; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW1_LEN = 3777; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW2 = 3778; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW2_LEN = 3779; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW3 = 3780; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW3_LEN = 3781; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW4 = 3782; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW4_LEN = 3783; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW5 = 3784; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW5_LEN = 3785; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW6 = 3786; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW6_LEN = 3787; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW7 = 3788; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW7_LEN = 3789; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW8 = 3790; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW8_LEN = 3791; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW9 = 3792; // 2 -static const uint64_t SH_FLD_CFG_AMAP_ROW9_LEN = 3793; // 2 -static const uint64_t SH_FLD_CFG_AMAP_SRANK0 = 3794; // 2 -static const uint64_t SH_FLD_CFG_AMAP_SRANK0_LEN = 3795; // 2 -static const uint64_t SH_FLD_CFG_AMAP_SRANK1 = 3796; // 2 -static const uint64_t SH_FLD_CFG_AMAP_SRANK1_LEN = 3797; // 2 -static const uint64_t SH_FLD_CFG_AMAP_SRANK2 = 3798; // 2 -static const uint64_t SH_FLD_CFG_AMAP_SRANK2_LEN = 3799; // 2 -static const uint64_t SH_FLD_CFG_APM_DD1_MODE = 3800; // 1 -static const uint64_t SH_FLD_CFG_APM_ENABLE = 3801; // 1 -static const uint64_t SH_FLD_CFG_APM_LM_HI_COMP = 3802; // 2 -static const uint64_t SH_FLD_CFG_APM_LM_HI_COMP_LEN = 3803; // 1 -static const uint64_t SH_FLD_CFG_APM_LM_LO_COMP = 3804; // 2 -static const uint64_t SH_FLD_CFG_APM_LM_LO_COMP_LEN = 3805; // 1 -static const uint64_t SH_FLD_CFG_APM_NM_HI_COMP = 3806; // 2 -static const uint64_t SH_FLD_CFG_APM_NM_HI_COMP_LEN = 3807; // 1 -static const uint64_t SH_FLD_CFG_APM_NM_LO_COMP = 3808; // 2 -static const uint64_t SH_FLD_CFG_APM_NM_LO_COMP_LEN = 3809; // 1 -static const uint64_t SH_FLD_CFG_APM_SAMPLE_SEL = 3810; // 1 -static const uint64_t SH_FLD_CFG_APM_SAMPLE_SEL_LEN = 3811; // 1 -static const uint64_t SH_FLD_CFG_APM_SEL = 3812; // 1 -static const uint64_t SH_FLD_CFG_APM_SEL_LEN = 3813; // 1 -static const uint64_t SH_FLD_CFG_A_AGGREGATE = 3814; // 6 -static const uint64_t SH_FLD_CFG_A_CMD_RATE = 3815; // 6 -static const uint64_t SH_FLD_CFG_A_CMD_RATE_LEN = 3816; // 6 -static const uint64_t SH_FLD_CFG_A_GATHER_ENABLE = 3817; // 6 -static const uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS = 3818; // 8 -static const uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN = 3819; // 8 -static const uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS = 3820; // 8 -static const uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 3821; // 8 -static const uint64_t SH_FLD_CFG_BC4_EN = 3822; // 2 -static const uint64_t SH_FLD_CFG_BLOCK_EN = 3823; // 1 -static const uint64_t SH_FLD_CFG_BLOCK_GROUP_EN = 3824; // 1 -static const uint64_t SH_FLD_CFG_BLOCK_RCMD_FILTER_EN = 3825; // 1 -static const uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY = 3826; // 1 -static const uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY_LEN = 3827; // 1 -static const uint64_t SH_FLD_CFG_BLOCK_VPD_EN = 3828; // 1 -static const uint64_t SH_FLD_CFG_BW_SNAPSHOT = 3829; // 8 -static const uint64_t SH_FLD_CFG_BW_SNAPSHOT_LEN = 3830; // 8 -static const uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL = 3831; // 12 -static const uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 3832; // 12 -static const uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL = 3833; // 12 -static const uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 3834; // 12 -static const uint64_t SH_FLD_CFG_CAC_ERR_REPAIR_EN = 3835; // 12 -static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE = 3836; // 8 -static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE = 3837; // 8 -static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE = 3838; // 8 -static const uint64_t SH_FLD_CFG_CAL_RANK_ENABLE = 3839; // 8 -static const uint64_t SH_FLD_CFG_CAL_RANK_ENABLE_LEN = 3840; // 8 -static const uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE = 3841; // 8 -static const uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN = 3842; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE = 3843; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE = 3844; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE = 3845; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN = 3846; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE = 3847; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE = 3848; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE = 3849; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN = 3850; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE = 3851; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE = 3852; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE = 3853; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN = 3854; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE = 3855; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR = 3856; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 3857; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 3858; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 3859; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_SINGLE_RANK = 3860; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC = 3861; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN = 3862; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE = 3863; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE = 3864; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE = 3865; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN = 3866; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE = 3867; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE = 3868; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE = 3869; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN = 3870; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE = 3871; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE = 3872; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE = 3873; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN = 3874; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_SINGLE_RANK = 3875; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC = 3876; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN = 3877; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE = 3878; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE = 3879; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE = 3880; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN = 3881; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE = 3882; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE = 3883; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE = 3884; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN = 3885; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE = 3886; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE = 3887; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE = 3888; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN = 3889; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_SINGLE_RANK = 3890; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 3891; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC = 3892; // 8 -static const uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN = 3893; // 8 -static const uint64_t SH_FLD_CFG_CAPI = 3894; // 6 -static const uint64_t SH_FLD_CFG_CASCADE_PMU0 = 3895; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU0_LEN = 3896; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU1 = 3897; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU1_LEN = 3898; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU2 = 3899; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU2_LEN = 3900; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU3 = 3901; // 2 -static const uint64_t SH_FLD_CFG_CASCADE_PMU3_LEN = 3902; // 2 -static const uint64_t SH_FLD_CFG_CCS_ADDR_MUX_SEL = 3903; // 8 -static const uint64_t SH_FLD_CFG_CCS_INST_RESET_ENABLE = 3904; // 8 -static const uint64_t SH_FLD_CFG_CCS_RETRY_DIS = 3905; // 2 -static const uint64_t SH_FLD_CFG_CHG_RATE_GP_MASTER = 3906; // 6 -static const uint64_t SH_FLD_CFG_CHG_RATE_SP_MASTER = 3907; // 6 -static const uint64_t SH_FLD_CFG_CHIPID = 3908; // 1 -static const uint64_t SH_FLD_CFG_CHIPID_LEN = 3909; // 1 -static const uint64_t SH_FLD_CFG_CHIPID_OVERRIDE = 3910; // 1 -static const uint64_t SH_FLD_CFG_CHIP_IS_SYSTEM = 3911; // 3 -static const uint64_t SH_FLD_CFG_CKE_PUP_STATE = 3912; // 8 -static const uint64_t SH_FLD_CFG_CKE_PUP_STATE_LEN = 3913; // 8 -static const uint64_t SH_FLD_CFG_CLOCK_MONITOR_EN = 3914; // 2 -static const uint64_t SH_FLD_CFG_CMD0_BANK = 3915; // 8 -static const uint64_t SH_FLD_CFG_CMD0_BANK_LEN = 3916; // 8 -static const uint64_t SH_FLD_CFG_CMD0_BANK_MATCH_EN = 3917; // 8 -static const uint64_t SH_FLD_CFG_CMD0_BG = 3918; // 8 -static const uint64_t SH_FLD_CFG_CMD0_BG_LEN = 3919; // 8 -static const uint64_t SH_FLD_CFG_CMD0_BG_MATCH_EN = 3920; // 8 -static const uint64_t SH_FLD_CFG_CMD0_MRANK = 3921; // 8 -static const uint64_t SH_FLD_CFG_CMD0_MRANK_LEN = 3922; // 8 -static const uint64_t SH_FLD_CFG_CMD0_MRANK_MATCH_EN = 3923; // 8 -static const uint64_t SH_FLD_CFG_CMD0_SRANK = 3924; // 8 -static const uint64_t SH_FLD_CFG_CMD0_SRANK_LEN = 3925; // 8 -static const uint64_t SH_FLD_CFG_CMD0_SRANK_MATCH_EN = 3926; // 8 -static const uint64_t SH_FLD_CFG_CMD0_TYPE = 3927; // 8 -static const uint64_t SH_FLD_CFG_CMD0_TYPE_LEN = 3928; // 8 -static const uint64_t SH_FLD_CFG_CMD1_BANK = 3929; // 8 -static const uint64_t SH_FLD_CFG_CMD1_BANK_LEN = 3930; // 8 -static const uint64_t SH_FLD_CFG_CMD1_BANK_MATCH_EN = 3931; // 8 -static const uint64_t SH_FLD_CFG_CMD1_BG = 3932; // 8 -static const uint64_t SH_FLD_CFG_CMD1_BG_LEN = 3933; // 8 -static const uint64_t SH_FLD_CFG_CMD1_BG_MATCH_EN = 3934; // 8 -static const uint64_t SH_FLD_CFG_CMD1_MRANK = 3935; // 8 -static const uint64_t SH_FLD_CFG_CMD1_MRANK_LEN = 3936; // 8 -static const uint64_t SH_FLD_CFG_CMD1_MRANK_MATCH_EN = 3937; // 8 -static const uint64_t SH_FLD_CFG_CMD1_SRANK = 3938; // 8 -static const uint64_t SH_FLD_CFG_CMD1_SRANK_LEN = 3939; // 8 -static const uint64_t SH_FLD_CFG_CMD1_SRANK_MATCH_EN = 3940; // 8 -static const uint64_t SH_FLD_CFG_CMD1_TYPE = 3941; // 8 -static const uint64_t SH_FLD_CFG_CMD1_TYPE_LEN = 3942; // 8 -static const uint64_t SH_FLD_CFG_CMD2_BANK = 3943; // 8 -static const uint64_t SH_FLD_CFG_CMD2_BANK_LEN = 3944; // 8 -static const uint64_t SH_FLD_CFG_CMD2_BANK_MATCH_EN = 3945; // 8 -static const uint64_t SH_FLD_CFG_CMD2_BG = 3946; // 8 -static const uint64_t SH_FLD_CFG_CMD2_BG_LEN = 3947; // 8 -static const uint64_t SH_FLD_CFG_CMD2_BG_MATCH_EN = 3948; // 8 -static const uint64_t SH_FLD_CFG_CMD2_MRANK = 3949; // 8 -static const uint64_t SH_FLD_CFG_CMD2_MRANK_LEN = 3950; // 8 -static const uint64_t SH_FLD_CFG_CMD2_MRANK_MATCH_EN = 3951; // 8 -static const uint64_t SH_FLD_CFG_CMD2_SRANK = 3952; // 8 -static const uint64_t SH_FLD_CFG_CMD2_SRANK_LEN = 3953; // 8 -static const uint64_t SH_FLD_CFG_CMD2_SRANK_MATCH_EN = 3954; // 8 -static const uint64_t SH_FLD_CFG_CMD2_TYPE = 3955; // 8 -static const uint64_t SH_FLD_CFG_CMD2_TYPE_LEN = 3956; // 8 -static const uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE = 3957; // 2 -static const uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN = 3958; // 2 -static const uint64_t SH_FLD_CFG_CNPME_BITWISE_ENABLE = 3959; // 1 -static const uint64_t SH_FLD_CFG_CNPME_BITWISE_ENABLE_LEN = 3960; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C0 = 3961; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C0_LEN = 3962; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C1 = 3963; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C1_LEN = 3964; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C2 = 3965; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C2_LEN = 3966; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C3 = 3967; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP0_C3_LEN = 3968; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C0 = 3969; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C0_LEN = 3970; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C1 = 3971; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C1_LEN = 3972; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C2 = 3973; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C2_LEN = 3974; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C3 = 3975; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP1_C3_LEN = 3976; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C0 = 3977; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C0_LEN = 3978; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C1 = 3979; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C1_LEN = 3980; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C2 = 3981; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C2_LEN = 3982; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C3 = 3983; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP2_C3_LEN = 3984; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C0 = 3985; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C0_LEN = 3986; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C1 = 3987; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C1_LEN = 3988; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C2 = 3989; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C2_LEN = 3990; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C3 = 3991; // 1 -static const uint64_t SH_FLD_CFG_CNPME_GRP3_C3_LEN = 3992; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_BITWISE_ENABLE = 3993; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_BITWISE_ENABLE_LEN = 3994; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C0 = 3995; // 2 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C1 = 3996; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C1_LEN = 3997; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C2 = 3998; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C2_LEN = 3999; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C3 = 4000; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C3_LEN = 4001; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C0 = 4002; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C0_LEN = 4003; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C1 = 4004; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C1_LEN = 4005; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C2 = 4006; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C2_LEN = 4007; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C3 = 4008; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C3_LEN = 4009; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C0 = 4010; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C0_LEN = 4011; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C1 = 4012; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C1_LEN = 4013; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C2 = 4014; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C2_LEN = 4015; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C3 = 4016; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C3_LEN = 4017; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C0 = 4018; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C0_LEN = 4019; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C1 = 4020; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C1_LEN = 4021; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C2 = 4022; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C2_LEN = 4023; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C3 = 4024; // 1 -static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C3_LEN = 4025; // 1 -static const uint64_t SH_FLD_CFG_COMPA_PRESP = 4026; // 1 -static const uint64_t SH_FLD_CFG_COMPA_PRESP_LEN = 4027; // 1 -static const uint64_t SH_FLD_CFG_COMPA_PRESP_MASK = 4028; // 1 -static const uint64_t SH_FLD_CFG_COMPA_PRESP_MASK_LEN = 4029; // 1 -static const uint64_t SH_FLD_CFG_COMPA_SCOPE_MASK = 4030; // 1 -static const uint64_t SH_FLD_CFG_COMPA_SCOPE_MASK_LEN = 4031; // 1 -static const uint64_t SH_FLD_CFG_COMPB_PRESP = 4032; // 1 -static const uint64_t SH_FLD_CFG_COMPB_PRESP_LEN = 4033; // 1 -static const uint64_t SH_FLD_CFG_COMPB_PRESP_MASK = 4034; // 1 -static const uint64_t SH_FLD_CFG_COMPB_PRESP_MASK_LEN = 4035; // 1 -static const uint64_t SH_FLD_CFG_COMPB_SCOPE_MASK = 4036; // 1 -static const uint64_t SH_FLD_CFG_COMPB_SCOPE_MASK_LEN = 4037; // 1 -static const uint64_t SH_FLD_CFG_CORE_PUSH_EN = 4038; // 1 -static const uint64_t SH_FLD_CFG_COUNTER_MODE = 4039; // 2 -static const uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 4040; // 12 -static const uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN = 4041; // 12 -static const uint64_t SH_FLD_CFG_CPU_RATIO_OVERRIDE = 4042; // 1 -static const uint64_t SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN = 4043; // 1 -static const uint64_t SH_FLD_CFG_CRESP = 4044; // 2 -static const uint64_t SH_FLD_CFG_CRESP_LEN = 4045; // 2 -static const uint64_t SH_FLD_CFG_CRESP_MASK = 4046; // 2 -static const uint64_t SH_FLD_CFG_CRESP_MASK_LEN = 4047; // 2 -static const uint64_t SH_FLD_CFG_CRESP_POLARITY = 4048; // 2 -static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP = 4049; // 2 -static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN = 4050; // 2 -static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 4051; // 2 -static const uint64_t SH_FLD_CFG_CURRENT_DIMM_TRAP = 4052; // 2 -static const uint64_t SH_FLD_CFG_CURRENT_PORT_TRAP = 4053; // 2 -static const uint64_t SH_FLD_CFG_CURRENT_PORT_TRAP_LEN = 4054; // 2 -static const uint64_t SH_FLD_CFG_DATA_ROT = 4055; // 2 -static const uint64_t SH_FLD_CFG_DATA_ROT_LEN = 4056; // 2 -static const uint64_t SH_FLD_CFG_DATA_ROT_SEED = 4057; // 4 -static const uint64_t SH_FLD_CFG_DATA_ROT_SEED_LEN = 4058; // 4 -static const uint64_t SH_FLD_CFG_DATA_SEED_MODE = 4059; // 2 -static const uint64_t SH_FLD_CFG_DATA_SEED_MODE_LEN = 4060; // 2 -static const uint64_t SH_FLD_CFG_DBG_ENABLE = 4061; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01 = 4062; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01_LEN = 4063; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23 = 4064; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23_LEN = 4065; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01 = 4066; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01_LEN = 4067; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23 = 4068; // 2 -static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23_LEN = 4069; // 2 -static const uint64_t SH_FLD_CFG_DBG_SRQ_ENABLE = 4070; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL0 = 4071; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL0_LEN = 4072; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL1 = 4073; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL1_LEN = 4074; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL2 = 4075; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL2_LEN = 4076; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL3 = 4077; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL3_LEN = 4078; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL4 = 4079; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL4_LEN = 4080; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL5 = 4081; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL5_LEN = 4082; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL6 = 4083; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL6_LEN = 4084; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL7 = 4085; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL7_LEN = 4086; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ = 4087; // 8 -static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN = 4088; // 8 -static const uint64_t SH_FLD_CFG_DCACHE_CAPP = 4089; // 6 -static const uint64_t SH_FLD_CFG_DCACHE_CAPP_LPC_EN = 4090; // 12 -static const uint64_t SH_FLD_CFG_DCBZ_TRASHMODE_EN = 4091; // 12 -static const uint64_t SH_FLD_CFG_DDR4E_BLIND_STEER_MODE = 4092; // 2 -static const uint64_t SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS = 4093; // 8 -static const uint64_t SH_FLD_CFG_DDR_DPHY_NCLK = 4094; // 8 -static const uint64_t SH_FLD_CFG_DDR_DPHY_NCLK_LEN = 4095; // 8 -static const uint64_t SH_FLD_CFG_DDR_DPHY_PCLK = 4096; // 8 -static const uint64_t SH_FLD_CFG_DDR_DPHY_PCLK_LEN = 4097; // 8 -static const uint64_t SH_FLD_CFG_DDR_RESETN = 4098; // 8 -static const uint64_t SH_FLD_CFG_DGEN_FIXED_MODE = 4099; // 2 -static const uint64_t SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK = 4100; // 43 -static const uint64_t SH_FLD_CFG_DISABLE_FAST_PATH = 4101; // 8 -static const uint64_t SH_FLD_CFG_DISABLE_FORCE_TO_ZERO = 4102; // 43 -static const uint64_t SH_FLD_CFG_DISABLE_HEARTBEAT = 4103; // 43 -static const uint64_t SH_FLD_CFG_DISABLE_MALF_PULSE_GEN = 4104; // 43 -static const uint64_t SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK = 4105; // 43 -static const uint64_t SH_FLD_CFG_DISABLE_RCD_RECOVERY = 4106; // 8 -static const uint64_t SH_FLD_CFG_DISABLE_RD_PG_MODE = 4107; // 8 -static const uint64_t SH_FLD_CFG_DISABLE_RESET_RECOVER = 4108; // 8 -static const uint64_t SH_FLD_CFG_DISABLE_WR_PG_MODE = 4109; // 8 -static const uint64_t SH_FLD_CFG_DIS_CLK_IN_STR = 4110; // 8 -static const uint64_t SH_FLD_CFG_DIS_SMDR = 4111; // 8 -static const uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP = 4112; // 1 -static const uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN = 4113; // 1 -static const uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL = 4114; // 1 -static const uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 4115; // 1 -static const uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL = 4116; // 1 -static const uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 4117; // 1 -static const uint64_t SH_FLD_CFG_DONE_PRIO_IACK = 4118; // 1 -static const uint64_t SH_FLD_CFG_DONE_PRIO_IACK_LEN = 4119; // 1 -static const uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP = 4120; // 1 -static const uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN = 4121; // 1 -static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH = 4122; // 8 -static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN = 4123; // 8 -static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB = 4124; // 8 -static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN = 4125; // 8 -static const uint64_t SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 4126; // 12 -static const uint64_t SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS = 4127; // 12 -static const uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN = 4128; // 8 -static const uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN = 4129; // 8 -static const uint64_t SH_FLD_CFG_EN = 4130; // 3 -static const uint64_t SH_FLD_CFG_ENABLE_HOST_ATTN = 4131; // 10 -static const uint64_t SH_FLD_CFG_ENABLE_PERFTRACE_FIXED_WIN = 4132; // 1 -static const uint64_t SH_FLD_CFG_ENABLE_PERFTRACE_PRESCALE = 4133; // 1 -static const uint64_t SH_FLD_CFG_ENABLE_SPEC_ATTN = 4134; // 10 -static const uint64_t SH_FLD_CFG_END_ADDR_0 = 4135; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_0_LEN = 4136; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_1 = 4137; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_1_LEN = 4138; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_2 = 4139; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_2_LEN = 4140; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_3 = 4141; // 2 -static const uint64_t SH_FLD_CFG_END_ADDR_3_LEN = 4142; // 2 -static const uint64_t SH_FLD_CFG_ENTER_STR_TIME = 4143; // 8 -static const uint64_t SH_FLD_CFG_ENTER_STR_TIME_LEN = 4144; // 8 -static const uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 4145; // 8 -static const uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 4146; // 8 -static const uint64_t SH_FLD_CFG_EN_RANDCMD_GAP = 4147; // 2 -static const uint64_t SH_FLD_CFG_EVENT0_SELECT = 4148; // 8 -static const uint64_t SH_FLD_CFG_EVENT0_SELECT_LEN = 4149; // 8 -static const uint64_t SH_FLD_CFG_EVENT1_SELECT = 4150; // 8 -static const uint64_t SH_FLD_CFG_EVENT1_SELECT_LEN = 4151; // 8 -static const uint64_t SH_FLD_CFG_EVENT2_SELECT = 4152; // 8 -static const uint64_t SH_FLD_CFG_EVENT2_SELECT_LEN = 4153; // 8 -static const uint64_t SH_FLD_CFG_EVENT3_SELECT = 4154; // 8 -static const uint64_t SH_FLD_CFG_EVENT3_SELECT_LEN = 4155; // 8 -static const uint64_t SH_FLD_CFG_EXTERNAL_FREEZE = 4156; // 2 -static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH = 4157; // 8 -static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN = 4158; // 8 -static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB = 4159; // 8 -static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN = 4160; // 8 -static const uint64_t SH_FLD_CFG_FARB_CLOSE_ALL_PAGES = 4161; // 8 -static const uint64_t SH_FLD_CFG_FIXED_SEED = 4162; // 16 -static const uint64_t SH_FLD_CFG_FIXED_SEED1 = 4163; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED1_LEN = 4164; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED2 = 4165; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED2_LEN = 4166; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED3 = 4167; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED3_LEN = 4168; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED4 = 4169; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED4_LEN = 4170; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED5 = 4171; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED5_LEN = 4172; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED6 = 4173; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED6_LEN = 4174; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED7 = 4175; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED7_LEN = 4176; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED8 = 4177; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED8_LEN = 4178; // 2 -static const uint64_t SH_FLD_CFG_FIXED_SEED_LEN = 4179; // 16 -static const uint64_t SH_FLD_CFG_FIXED_WIDTH = 4180; // 2 -static const uint64_t SH_FLD_CFG_FIXED_WIDTH_LEN = 4181; // 2 -static const uint64_t SH_FLD_CFG_FORCE_MCLK_LOW_N = 4182; // 8 -static const uint64_t SH_FLD_CFG_FORCE_SPARE_PUP = 4183; // 8 -static const uint64_t SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS = 4184; // 8 -static const uint64_t SH_FLD_CFG_FUSE_CORE_EN = 4185; // 1 -static const uint64_t SH_FLD_CFG_GLOBAL_PMISC_DIS = 4186; // 2 -static const uint64_t SH_FLD_CFG_GLOBAL_PMISC_MODE = 4187; // 2 -static const uint64_t SH_FLD_CFG_GP_BIT_3_ENABLE = 4188; // 8 -static const uint64_t SH_FLD_CFG_GP_HW_MARK = 4189; // 3 -static const uint64_t SH_FLD_CFG_GP_HW_MARK_LEN = 4190; // 3 -static const uint64_t SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN = 4191; // 1 -static const uint64_t SH_FLD_CFG_HASH_L3_ADDR_EN = 4192; // 12 -static const uint64_t SH_FLD_CFG_HNG_CHK_DISABLE = 4193; // 3 -static const uint64_t SH_FLD_CFG_HOP = 4194; // 6 -static const uint64_t SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 4195; // 12 -static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 = 4196; // 8 -static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT = 4197; // 8 -static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_WEN = 4198; // 8 -static const uint64_t SH_FLD_CFG_INJ_CANCEL_ACK_ERR = 4199; // 8 -static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH = 4200; // 8 -static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN = 4201; // 8 -static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB = 4202; // 8 -static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB_LEN = 4203; // 8 -static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0 = 4204; // 8 -static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN = 4205; // 8 -static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1 = 4206; // 8 -static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN = 4207; // 8 -static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2 = 4208; // 8 -static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN = 4209; // 8 -static const uint64_t SH_FLD_CFG_INT_MASK = 4210; // 1 -static const uint64_t SH_FLD_CFG_L3_DIS = 4211; // 12 -static const uint64_t SH_FLD_CFG_LCL_HW_MARK = 4212; // 3 -static const uint64_t SH_FLD_CFG_LCL_HW_MARK_LEN = 4213; // 3 -static const uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD = 4214; // 1 -static const uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN = 4215; // 1 -static const uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD = 4216; // 1 -static const uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD_LEN = 4217; // 1 -static const uint64_t SH_FLD_CFG_LFSR_MASK_A0 = 4218; // 2 -static const uint64_t SH_FLD_CFG_LFSR_MASK_A0_LEN = 4219; // 2 -static const uint64_t SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN = 4220; // 12 -static const uint64_t SH_FLD_CFG_LINK_A0_EN = 4221; // 6 -static const uint64_t SH_FLD_CFG_LINK_A0_GROUPID = 4222; // 6 -static const uint64_t SH_FLD_CFG_LINK_A0_GROUPID_LEN = 4223; // 6 -static const uint64_t SH_FLD_CFG_LINK_A1_EN = 4224; // 6 -static const uint64_t SH_FLD_CFG_LINK_A1_GROUPID = 4225; // 6 -static const uint64_t SH_FLD_CFG_LINK_A1_GROUPID_LEN = 4226; // 6 -static const uint64_t SH_FLD_CFG_LINK_A2_EN = 4227; // 6 -static const uint64_t SH_FLD_CFG_LINK_A2_GROUPID = 4228; // 6 -static const uint64_t SH_FLD_CFG_LINK_A2_GROUPID_LEN = 4229; // 6 -static const uint64_t SH_FLD_CFG_LINK_A3_EN = 4230; // 6 -static const uint64_t SH_FLD_CFG_LINK_A3_GROUPID = 4231; // 6 -static const uint64_t SH_FLD_CFG_LINK_A3_GROUPID_LEN = 4232; // 6 -static const uint64_t SH_FLD_CFG_LINK_NA0_ADDR_DIS = 4233; // 6 -static const uint64_t SH_FLD_CFG_LINK_NA1_ADDR_DIS = 4234; // 6 -static const uint64_t SH_FLD_CFG_LINK_NA2_ADDR_DIS = 4235; // 6 -static const uint64_t SH_FLD_CFG_LINK_NA3_ADDR_DIS = 4236; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX0_ADDR_DIS = 4237; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX1_ADDR_DIS = 4238; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX2_ADDR_DIS = 4239; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX3_ADDR_DIS = 4240; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX4_ADDR_DIS = 4241; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX5_ADDR_DIS = 4242; // 6 -static const uint64_t SH_FLD_CFG_LINK_NX6_ADDR_DIS = 4243; // 6 -static const uint64_t SH_FLD_CFG_LINK_X0_CHIPID = 4244; // 6 -static const uint64_t SH_FLD_CFG_LINK_X0_CHIPID_LEN = 4245; // 6 -static const uint64_t SH_FLD_CFG_LINK_X0_EN = 4246; // 6 -static const uint64_t SH_FLD_CFG_LINK_X1_CHIPID = 4247; // 6 -static const uint64_t SH_FLD_CFG_LINK_X1_CHIPID_LEN = 4248; // 6 -static const uint64_t SH_FLD_CFG_LINK_X1_EN = 4249; // 6 -static const uint64_t SH_FLD_CFG_LINK_X2_CHIPID = 4250; // 6 -static const uint64_t SH_FLD_CFG_LINK_X2_CHIPID_LEN = 4251; // 6 -static const uint64_t SH_FLD_CFG_LINK_X2_EN = 4252; // 6 -static const uint64_t SH_FLD_CFG_LINK_X3_CHIPID = 4253; // 6 -static const uint64_t SH_FLD_CFG_LINK_X3_CHIPID_LEN = 4254; // 6 -static const uint64_t SH_FLD_CFG_LINK_X3_EN = 4255; // 6 -static const uint64_t SH_FLD_CFG_LINK_X4_CHIPID = 4256; // 6 -static const uint64_t SH_FLD_CFG_LINK_X4_CHIPID_LEN = 4257; // 6 -static const uint64_t SH_FLD_CFG_LINK_X4_EN = 4258; // 6 -static const uint64_t SH_FLD_CFG_LINK_X5_CHIPID = 4259; // 6 -static const uint64_t SH_FLD_CFG_LINK_X5_CHIPID_LEN = 4260; // 6 -static const uint64_t SH_FLD_CFG_LINK_X5_EN = 4261; // 6 -static const uint64_t SH_FLD_CFG_LINK_X6_CHIPID = 4262; // 6 -static const uint64_t SH_FLD_CFG_LINK_X6_CHIPID_LEN = 4263; // 6 -static const uint64_t SH_FLD_CFG_LINK_X6_EN = 4264; // 6 -static const uint64_t SH_FLD_CFG_LOGIC_SIGNALED_ERROR = 4265; // 6 -static const uint64_t SH_FLD_CFG_LOG_COUNTS_IN_TRACE = 4266; // 2 -static const uint64_t SH_FLD_CFG_LP_SUB_CNT = 4267; // 8 -static const uint64_t SH_FLD_CFG_LP_SUB_CNT_LEN = 4268; // 8 -static const uint64_t SH_FLD_CFG_LRU_DIRECT_MAP = 4269; // 12 -static const uint64_t SH_FLD_CFG_LTE_MC = 4270; // 2 -static const uint64_t SH_FLD_CFG_LTE_MC_LEN = 4271; // 2 -static const uint64_t SH_FLD_CFG_LVL0 = 4272; // 2 -static const uint64_t SH_FLD_CFG_LVL0_LEN = 4273; // 2 -static const uint64_t SH_FLD_CFG_LVL1 = 4274; // 2 -static const uint64_t SH_FLD_CFG_LVL1_LEN = 4275; // 2 -static const uint64_t SH_FLD_CFG_LVL2 = 4276; // 2 -static const uint64_t SH_FLD_CFG_LVL2_LEN = 4277; // 2 -static const uint64_t SH_FLD_CFG_LVL3 = 4278; // 2 -static const uint64_t SH_FLD_CFG_LVL3_LEN = 4279; // 2 -static const uint64_t SH_FLD_CFG_LVL4 = 4280; // 2 -static const uint64_t SH_FLD_CFG_LVL4_LEN = 4281; // 2 -static const uint64_t SH_FLD_CFG_LVL5 = 4282; // 2 -static const uint64_t SH_FLD_CFG_LVL5_LEN = 4283; // 2 -static const uint64_t SH_FLD_CFG_LVL6 = 4284; // 2 -static const uint64_t SH_FLD_CFG_LVL6_LEN = 4285; // 2 -static const uint64_t SH_FLD_CFG_LVL7 = 4286; // 2 -static const uint64_t SH_FLD_CFG_LVL7_LEN = 4287; // 2 -static const uint64_t SH_FLD_CFG_MAINT_ADDR_MODE_EN = 4288; // 2 -static const uint64_t SH_FLD_CFG_MAINT_BROADCAST_MODE_EN = 4289; // 2 -static const uint64_t SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 4290; // 2 -static const uint64_t SH_FLD_CFG_MAINT_RCE_WITH_CE = 4291; // 2 -static const uint64_t SH_FLD_CFG_MASK = 4292; // 2 -static const uint64_t SH_FLD_CFG_MASTER_CHIP = 4293; // 6 -static const uint64_t SH_FLD_CFG_MAX = 4294; // 1 -static const uint64_t SH_FLD_CFG_MAX_LEN = 4295; // 1 -static const uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW = 4296; // 8 -static const uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN = 4297; // 8 -static const uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW = 4298; // 8 -static const uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN = 4299; // 8 -static const uint64_t SH_FLD_CFG_MC0_MCS0_MASK = 4300; // 1 -static const uint64_t SH_FLD_CFG_MC0_MCS1_MASK = 4301; // 1 -static const uint64_t SH_FLD_CFG_MC1_MCS0_MASK = 4302; // 1 -static const uint64_t SH_FLD_CFG_MC1_MCS1_MASK = 4303; // 1 -static const uint64_t SH_FLD_CFG_MC2_MCS0_MASK = 4304; // 1 -static const uint64_t SH_FLD_CFG_MC2_MCS1_MASK = 4305; // 1 -static const uint64_t SH_FLD_CFG_MC3_MCS0_MASK = 4306; // 1 -static const uint64_t SH_FLD_CFG_MC3_MCS1_MASK = 4307; // 1 -static const uint64_t SH_FLD_CFG_MCB_LEN64 = 4308; // 2 -static const uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 4309; // 2 -static const uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 4310; // 2 -static const uint64_t SH_FLD_CFG_MCD_MASK = 4311; // 1 -static const uint64_t SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 4312; // 2 -static const uint64_t SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 4313; // 2 -static const uint64_t SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 4314; // 2 -static const uint64_t SH_FLD_CFG_MIN_CMD_GAP = 4315; // 2 -static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER = 4316; // 2 -static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 4317; // 2 -static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_LEN = 4318; // 2 -static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 4319; // 8 -static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 4320; // 8 -static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME = 4321; // 8 -static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 4322; // 8 -static const uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE = 4323; // 2 -static const uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 4324; // 2 -static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS = 4325; // 8 -static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE = 4326; // 8 -static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_LEN = 4327; // 8 -static const uint64_t SH_FLD_CFG_MISR_BLOCK = 4328; // 8 -static const uint64_t SH_FLD_CFG_MISR_BLOCK_LEN = 4329; // 8 -static const uint64_t SH_FLD_CFG_MISR_FEEDBACK_ENABLE = 4330; // 8 -static const uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH = 4331; // 8 -static const uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH_LEN = 4332; // 8 -static const uint64_t SH_FLD_CFG_MPR_READEYE_TB = 4333; // 8 -static const uint64_t SH_FLD_CFG_MPR_READEYE_TB_LEN = 4334; // 8 -static const uint64_t SH_FLD_CFG_MSGSND = 4335; // 1 -static const uint64_t SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 4336; // 2 -static const uint64_t SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 4337; // 2 -static const uint64_t SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 4338; // 2 -static const uint64_t SH_FLD_CFG_NM_CAS_WEIGHT = 4339; // 8 -static const uint64_t SH_FLD_CFG_NM_CAS_WEIGHT_LEN = 4340; // 8 -static const uint64_t SH_FLD_CFG_NM_CHANGE_AFTER_SYNC = 4341; // 8 -static const uint64_t SH_FLD_CFG_NM_M = 4342; // 8 -static const uint64_t SH_FLD_CFG_NM_M_LEN = 4343; // 8 -static const uint64_t SH_FLD_CFG_NM_N_PER_PORT = 4344; // 8 -static const uint64_t SH_FLD_CFG_NM_N_PER_PORT_LEN = 4345; // 8 -static const uint64_t SH_FLD_CFG_NM_N_PER_SLOT = 4346; // 8 -static const uint64_t SH_FLD_CFG_NM_N_PER_SLOT_LEN = 4347; // 8 -static const uint64_t SH_FLD_CFG_NM_RAS_WEIGHT = 4348; // 8 -static const uint64_t SH_FLD_CFG_NM_RAS_WEIGHT_LEN = 4349; // 8 -static const uint64_t SH_FLD_CFG_NOISE_WAIT_TIME = 4350; // 8 -static const uint64_t SH_FLD_CFG_NOISE_WAIT_TIME_LEN = 4351; // 8 -static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL = 4352; // 8 -static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4353; // 8 -static const uint64_t SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN = 4354; // 8 -static const uint64_t SH_FLD_CFG_OE_ALWAYS_ON = 4355; // 8 -static const uint64_t SH_FLD_CFG_OPT0 = 4356; // 6 -static const uint64_t SH_FLD_CFG_OPT0_LEN = 4357; // 6 -static const uint64_t SH_FLD_CFG_OPT1 = 4358; // 6 -static const uint64_t SH_FLD_CFG_OPT1_LEN = 4359; // 6 -static const uint64_t SH_FLD_CFG_OPT2 = 4360; // 6 -static const uint64_t SH_FLD_CFG_OPT2_LEN = 4361; // 6 -static const uint64_t SH_FLD_CFG_OPT3 = 4362; // 6 -static const uint64_t SH_FLD_CFG_OPT3_LEN = 4363; // 6 -static const uint64_t SH_FLD_CFG_OPT_RD_SIZE = 4364; // 8 -static const uint64_t SH_FLD_CFG_OPT_RD_SIZE_LEN = 4365; // 8 -static const uint64_t SH_FLD_CFG_PARITY_AFTER_CMD = 4366; // 10 -static const uint64_t SH_FLD_CFG_PARITY_DETECT_TIME = 4367; // 8 -static const uint64_t SH_FLD_CFG_PARITY_DETECT_TIME_LEN = 4368; // 8 -static const uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL = 4369; // 1 -static const uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN = 4370; // 1 -static const uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL = 4371; // 1 -static const uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN = 4372; // 1 -static const uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL = 4373; // 1 -static const uint64_t SH_FLD_CFG_PAUSE_MCB_ERROR = 4374; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_MCB_LOG_FULL = 4375; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_AUE = 4376; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE = 4377; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN = 4378; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_MCE = 4379; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_MPE = 4380; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_RCD = 4381; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_SCE = 4382; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_SUE = 4383; // 2 -static const uint64_t SH_FLD_CFG_PAUSE_ON_UE = 4384; // 2 -static const uint64_t SH_FLD_CFG_PBIEN_DBG_0_SEL = 4385; // 1 -static const uint64_t SH_FLD_CFG_PBIEN_DBG_0_SEL_LEN = 4386; // 1 -static const uint64_t SH_FLD_CFG_PBIEN_DBG_1_SEL = 4387; // 1 -static const uint64_t SH_FLD_CFG_PBIEN_DBG_1_SEL_LEN = 4388; // 1 -static const uint64_t SH_FLD_CFG_PBIES_DBG_0_SEL = 4389; // 1 -static const uint64_t SH_FLD_CFG_PBIES_DBG_0_SEL_LEN = 4390; // 1 -static const uint64_t SH_FLD_CFG_PBIES_DBG_1_SEL = 4391; // 1 -static const uint64_t SH_FLD_CFG_PBIES_DBG_1_SEL_LEN = 4392; // 1 -static const uint64_t SH_FLD_CFG_PBIOT_DBG_0_SEL = 4393; // 1 -static const uint64_t SH_FLD_CFG_PBIOT_DBG_0_SEL_LEN = 4394; // 1 -static const uint64_t SH_FLD_CFG_PBIOT_DBG_1_SEL = 4395; // 1 -static const uint64_t SH_FLD_CFG_PBIOT_DBG_1_SEL_LEN = 4396; // 1 -static const uint64_t SH_FLD_CFG_PBIOT_SEL = 4397; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_DONE = 4398; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_DONE_LEN = 4399; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP = 4400; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN = 4401; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET = 4402; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN = 4403; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_RR = 4404; // 1 -static const uint64_t SH_FLD_CFG_PCMD_PRIO_RR_LEN = 4405; // 1 -static const uint64_t SH_FLD_CFG_PDN_PUP = 4406; // 8 -static const uint64_t SH_FLD_CFG_PDN_PUP_LEN = 4407; // 8 -static const uint64_t SH_FLD_CFG_PE0_MASK = 4408; // 2 -static const uint64_t SH_FLD_CFG_PE1_MASK = 4409; // 2 -static const uint64_t SH_FLD_CFG_PE2_MASK = 4410; // 2 -static const uint64_t SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL = 4411; // 12 -static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_MATCH = 4412; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_MATCH_LEN = 4413; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_SEL = 4414; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_SEL_LEN = 4415; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_EN = 4416; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_GRP1_SEL = 4417; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_GRP2_SEL = 4418; // 1 -static const uint64_t SH_FLD_CFG_PERFTRACE_TRIG = 4419; // 1 -static const uint64_t SH_FLD_CFG_PER_BANK_REFRESH = 4420; // 8 -static const uint64_t SH_FLD_CFG_PE_MATCH0 = 4421; // 1 -static const uint64_t SH_FLD_CFG_PE_MATCH0_LEN = 4422; // 1 -static const uint64_t SH_FLD_CFG_PE_MATCH1 = 4423; // 1 -static const uint64_t SH_FLD_CFG_PE_MATCH1_LEN = 4424; // 1 -static const uint64_t SH_FLD_CFG_PHYP_IS_GROUP = 4425; // 6 -static const uint64_t SH_FLD_CFG_PMUCNT_EN = 4426; // 1 -static const uint64_t SH_FLD_CFG_PMUCNT_SEL = 4427; // 1 -static const uint64_t SH_FLD_CFG_PMUCNT_SEL_LEN = 4428; // 1 -static const uint64_t SH_FLD_CFG_PMU_FREEZE_MODE = 4429; // 1 -static const uint64_t SH_FLD_CFG_PMU_PORT = 4430; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL0 = 4431; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL0_LEN = 4432; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL1 = 4433; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL1_LEN = 4434; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL2 = 4435; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL2_LEN = 4436; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL3 = 4437; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL3_LEN = 4438; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL4 = 4439; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL4_LEN = 4440; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL5 = 4441; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL5_LEN = 4442; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL6 = 4443; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL6_LEN = 4444; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL7 = 4445; // 1 -static const uint64_t SH_FLD_CFG_PMU_SEL7_LEN = 4446; // 1 -static const uint64_t SH_FLD_CFG_PM_DISABLE = 4447; // 43 -static const uint64_t SH_FLD_CFG_PM_MUX_DISABLE = 4448; // 43 -static const uint64_t SH_FLD_CFG_PORT_FAIL_DISABLE = 4449; // 8 -static const uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME = 4450; // 8 -static const uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN = 4451; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C0 = 4452; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C0_LEN = 4453; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C1 = 4454; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C1_LEN = 4455; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C2 = 4456; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C2_LEN = 4457; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C3 = 4458; // 8 -static const uint64_t SH_FLD_CFG_PRESCALER_C3_LEN = 4459; // 8 -static const uint64_t SH_FLD_CFG_PRIO_LSI = 4460; // 1 -static const uint64_t SH_FLD_CFG_PRIO_LSI_LEN = 4461; // 1 -static const uint64_t SH_FLD_CFG_PRIO_MMIO = 4462; // 1 -static const uint64_t SH_FLD_CFG_PRIO_MMIO_LEN = 4463; // 1 -static const uint64_t SH_FLD_CFG_PRIO_PULL = 4464; // 2 -static const uint64_t SH_FLD_CFG_PRIO_PULL_LEN = 4465; // 2 -static const uint64_t SH_FLD_CFG_PRIO_PUSH = 4466; // 1 -static const uint64_t SH_FLD_CFG_PRIO_PUSH_ARX = 4467; // 1 -static const uint64_t SH_FLD_CFG_PRIO_PUSH_ARX_LEN = 4468; // 1 -static const uint64_t SH_FLD_CFG_PRIO_PUSH_LCL = 4469; // 1 -static const uint64_t SH_FLD_CFG_PRIO_PUSH_LCL_LEN = 4470; // 1 -static const uint64_t SH_FLD_CFG_PRIO_PUSH_LEN = 4471; // 1 -static const uint64_t SH_FLD_CFG_PRIO_QUERY = 4472; // 1 -static const uint64_t SH_FLD_CFG_PRIO_QUERY_LEN = 4473; // 1 -static const uint64_t SH_FLD_CFG_PRIO_RR = 4474; // 3 -static const uint64_t SH_FLD_CFG_PRIO_RR_LEN = 4475; // 3 -static const uint64_t SH_FLD_CFG_PRIO_RSVD = 4476; // 1 -static const uint64_t SH_FLD_CFG_PRIO_RSVD_LEN = 4477; // 1 -static const uint64_t SH_FLD_CFG_PRIO_VRQ_REQ = 4478; // 1 -static const uint64_t SH_FLD_CFG_PRIO_VRQ_REQ_LEN = 4479; // 1 -static const uint64_t SH_FLD_CFG_PRIO_VRQ_RSP = 4480; // 1 -static const uint64_t SH_FLD_CFG_PRIO_VRQ_RSP_LEN = 4481; // 1 -static const uint64_t SH_FLD_CFG_PULL_LMIT = 4482; // 1 -static const uint64_t SH_FLD_CFG_PULL_LMIT_LEN = 4483; // 1 -static const uint64_t SH_FLD_CFG_PULL_PRIO_HYP = 4484; // 1 -static const uint64_t SH_FLD_CFG_PULL_PRIO_HYP_LEN = 4485; // 1 -static const uint64_t SH_FLD_CFG_PULL_RSVD = 4486; // 1 -static const uint64_t SH_FLD_CFG_PULL_RSVD_LEN = 4487; // 1 -static const uint64_t SH_FLD_CFG_PULSE_WIDTH = 4488; // 1 -static const uint64_t SH_FLD_CFG_PULSE_WIDTH_LEN = 4489; // 1 -static const uint64_t SH_FLD_CFG_PUMP = 4490; // 8 -static const uint64_t SH_FLD_CFG_PUMP_MODE = 4491; // 1 -static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 4492; // 8 -static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 4493; // 8 -static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 4494; // 8 -static const uint64_t SH_FLD_CFG_PUP_ALL_WRITES_PENDING = 4495; // 8 -static const uint64_t SH_FLD_CFG_PUP_AVAIL = 4496; // 8 -static const uint64_t SH_FLD_CFG_PUP_AVAIL_LEN = 4497; // 8 -static const uint64_t SH_FLD_CFG_PUP_PDN = 4498; // 8 -static const uint64_t SH_FLD_CFG_PUP_PDN_LEN = 4499; // 8 -static const uint64_t SH_FLD_CFG_PUSH_ARX_LMIT = 4500; // 1 -static const uint64_t SH_FLD_CFG_PUSH_ARX_LMIT_LEN = 4501; // 1 -static const uint64_t SH_FLD_CFG_PUSH_ARX_RSVD = 4502; // 1 -static const uint64_t SH_FLD_CFG_PUSH_ARX_RSVD_LEN = 4503; // 1 -static const uint64_t SH_FLD_CFG_PUSH_LCL_LMIT = 4504; // 1 -static const uint64_t SH_FLD_CFG_PUSH_LCL_LMIT_LEN = 4505; // 1 -static const uint64_t SH_FLD_CFG_PUSH_LCL_RSVD = 4506; // 1 -static const uint64_t SH_FLD_CFG_PUSH_LCL_RSVD_LEN = 4507; // 1 -static const uint64_t SH_FLD_CFG_PUSH_PRIO_HYP = 4508; // 1 -static const uint64_t SH_FLD_CFG_PUSH_PRIO_HYP_LEN = 4509; // 1 -static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL = 4510; // 1 -static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL_LEN = 4511; // 1 -static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL = 4512; // 1 -static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 4513; // 1 -static const uint64_t SH_FLD_CFG_Q_BIT_TID_MASK = 4514; // 12 -static const uint64_t SH_FLD_CFG_Q_BIT_TID_MASK_LEN = 4515; // 12 -static const uint64_t SH_FLD_CFG_RANDCMD_WGT = 4516; // 2 -static const uint64_t SH_FLD_CFG_RANDCMD_WGT_LEN = 4517; // 2 -static const uint64_t SH_FLD_CFG_RANDGAP_WGT = 4518; // 2 -static const uint64_t SH_FLD_CFG_RANDGAP_WGT_LEN = 4519; // 2 -static const uint64_t SH_FLD_CFG_RANDOM_EN = 4520; // 12 -static const uint64_t SH_FLD_CFG_RANK0_RD_ODT = 4521; // 8 -static const uint64_t SH_FLD_CFG_RANK0_RD_ODT_LEN = 4522; // 8 -static const uint64_t SH_FLD_CFG_RANK0_WR_ODT = 4523; // 8 -static const uint64_t SH_FLD_CFG_RANK0_WR_ODT_LEN = 4524; // 8 -static const uint64_t SH_FLD_CFG_RANK1_RD_ODT = 4525; // 8 -static const uint64_t SH_FLD_CFG_RANK1_RD_ODT_LEN = 4526; // 8 -static const uint64_t SH_FLD_CFG_RANK1_WR_ODT = 4527; // 8 -static const uint64_t SH_FLD_CFG_RANK1_WR_ODT_LEN = 4528; // 8 -static const uint64_t SH_FLD_CFG_RANK2_RD_ODT = 4529; // 8 -static const uint64_t SH_FLD_CFG_RANK2_RD_ODT_LEN = 4530; // 8 -static const uint64_t SH_FLD_CFG_RANK2_WR_ODT = 4531; // 8 -static const uint64_t SH_FLD_CFG_RANK2_WR_ODT_LEN = 4532; // 8 -static const uint64_t SH_FLD_CFG_RANK3_RD_ODT = 4533; // 8 -static const uint64_t SH_FLD_CFG_RANK3_RD_ODT_LEN = 4534; // 8 -static const uint64_t SH_FLD_CFG_RANK3_WR_ODT = 4535; // 8 -static const uint64_t SH_FLD_CFG_RANK3_WR_ODT_LEN = 4536; // 8 -static const uint64_t SH_FLD_CFG_RANK4_RD_ODT = 4537; // 8 -static const uint64_t SH_FLD_CFG_RANK4_RD_ODT_LEN = 4538; // 8 -static const uint64_t SH_FLD_CFG_RANK4_WR_ODT = 4539; // 8 -static const uint64_t SH_FLD_CFG_RANK4_WR_ODT_LEN = 4540; // 8 -static const uint64_t SH_FLD_CFG_RANK5_RD_ODT = 4541; // 8 -static const uint64_t SH_FLD_CFG_RANK5_RD_ODT_LEN = 4542; // 8 -static const uint64_t SH_FLD_CFG_RANK5_WR_ODT = 4543; // 8 -static const uint64_t SH_FLD_CFG_RANK5_WR_ODT_LEN = 4544; // 8 -static const uint64_t SH_FLD_CFG_RANK6_RD_ODT = 4545; // 8 -static const uint64_t SH_FLD_CFG_RANK6_RD_ODT_LEN = 4546; // 8 -static const uint64_t SH_FLD_CFG_RANK6_WR_ODT = 4547; // 8 -static const uint64_t SH_FLD_CFG_RANK6_WR_ODT_LEN = 4548; // 8 -static const uint64_t SH_FLD_CFG_RANK7_RD_ODT = 4549; // 8 -static const uint64_t SH_FLD_CFG_RANK7_RD_ODT_LEN = 4550; // 8 -static const uint64_t SH_FLD_CFG_RANK7_WR_ODT = 4551; // 8 -static const uint64_t SH_FLD_CFG_RANK7_WR_ODT_LEN = 4552; // 8 -static const uint64_t SH_FLD_CFG_RANK_SM_STALL_DISABLE = 4553; // 8 -static const uint64_t SH_FLD_CFG_RCD_PARITY_DLY = 4554; // 8 -static const uint64_t SH_FLD_CFG_RCD_PARITY_DLY_LEN = 4555; // 8 -static const uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME = 4556; // 8 -static const uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME_LEN = 4557; // 8 -static const uint64_t SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN = 4558; // 12 -static const uint64_t SH_FLD_CFG_RD2PRE = 4559; // 8 -static const uint64_t SH_FLD_CFG_RD2PRE_LEN = 4560; // 8 -static const uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT = 4561; // 8 -static const uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 4562; // 8 -static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH = 4563; // 8 -static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN = 4564; // 8 -static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB = 4565; // 8 -static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN = 4566; // 8 -static const uint64_t SH_FLD_CFG_RDTAG_DLY = 4567; // 8 -static const uint64_t SH_FLD_CFG_RDTAG_DLY_LEN = 4568; // 8 -static const uint64_t SH_FLD_CFG_RDTAG_MBX_CYCLE = 4569; // 8 -static const uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR = 4570; // 8 -static const uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN = 4571; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_DEBUG_SELECT = 4572; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_ENABLE = 4573; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 4574; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL = 4575; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_LEN = 4576; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 4577; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 4578; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD = 4579; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 4580; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL = 4581; // 8 -static const uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN = 4582; // 8 -static const uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL = 4583; // 8 -static const uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN = 4584; // 8 -static const uint64_t SH_FLD_CFG_REFR_TSV_STACK = 4585; // 8 -static const uint64_t SH_FLD_CFG_REFR_TSV_STACK_LEN = 4586; // 8 -static const uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY = 4587; // 8 -static const uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN = 4588; // 8 -static const uint64_t SH_FLD_CFG_REG_PARITY_ERRHOLD = 4589; // 2 -static const uint64_t SH_FLD_CFG_REQ_GATHER_ENABLE = 4590; // 3 -static const uint64_t SH_FLD_CFG_RESET_CNTS_START_OF_RANK = 4591; // 2 -static const uint64_t SH_FLD_CFG_RESET_ERROR_CAPTURE = 4592; // 1 -static const uint64_t SH_FLD_CFG_RESET_MODE = 4593; // 2 -static const uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT = 4594; // 8 -static const uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 4595; // 8 -static const uint64_t SH_FLD_CFG_RNS_LVL0 = 4596; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL0_LEN = 4597; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL1 = 4598; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL1_LEN = 4599; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL2 = 4600; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL2_LEN = 4601; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL3 = 4602; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL3_LEN = 4603; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL4 = 4604; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL4_LEN = 4605; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL5 = 4606; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL5_LEN = 4607; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL6 = 4608; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL6_LEN = 4609; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL7 = 4610; // 2 -static const uint64_t SH_FLD_CFG_RNS_LVL7_LEN = 4611; // 2 -static const uint64_t SH_FLD_CFG_RODT_BC4_END_DLY = 4612; // 8 -static const uint64_t SH_FLD_CFG_RODT_BC4_END_DLY_LEN = 4613; // 8 -static const uint64_t SH_FLD_CFG_RODT_END_DLY = 4614; // 8 -static const uint64_t SH_FLD_CFG_RODT_END_DLY_LEN = 4615; // 8 -static const uint64_t SH_FLD_CFG_RODT_START_DLY = 4616; // 8 -static const uint64_t SH_FLD_CFG_RODT_START_DLY_LEN = 4617; // 8 -static const uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD = 4618; // 8 -static const uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN = 4619; // 8 -static const uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING = 4620; // 8 -static const uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4621; // 8 -static const uint64_t SH_FLD_CFG_RRQ_DEPTH = 4622; // 8 -static const uint64_t SH_FLD_CFG_RRQ_DEPTH_LEN = 4623; // 8 -static const uint64_t SH_FLD_CFG_RRQ_ENTRY0_ENABLE = 4624; // 8 -static const uint64_t SH_FLD_CFG_RRQ_FIFO_MODE = 4625; // 8 -static const uint64_t SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE = 4626; // 8 -static const uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT = 4627; // 8 -static const uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN = 4628; // 8 -static const uint64_t SH_FLD_CFG_RSV0 = 4629; // 8 -static const uint64_t SH_FLD_CFG_RSV0_LEN = 4630; // 8 -static const uint64_t SH_FLD_CFG_RUNTIME_CTR = 4631; // 2 -static const uint64_t SH_FLD_CFG_RUNTIME_CTR_LEN = 4632; // 2 -static const uint64_t SH_FLD_CFG_RUNTIME_MCBALL = 4633; // 2 -static const uint64_t SH_FLD_CFG_RUNTIME_OVERHEAD = 4634; // 2 -static const uint64_t SH_FLD_CFG_RUNTIME_SUBTEST = 4635; // 2 -static const uint64_t SH_FLD_CFG_RUNTIME_SUBTEST_LEN = 4636; // 2 -static const uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL = 4637; // 8 -static const uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN = 4638; // 8 -static const uint64_t SH_FLD_CFG_SCOPE = 4639; // 2 -static const uint64_t SH_FLD_CFG_SCOPE_LEN = 4640; // 2 -static const uint64_t SH_FLD_CFG_SELCR0 = 4641; // 1 -static const uint64_t SH_FLD_CFG_SELCR0_LEN = 4642; // 1 -static const uint64_t SH_FLD_CFG_SELCR1 = 4643; // 1 -static const uint64_t SH_FLD_CFG_SELCR1_LEN = 4644; // 1 -static const uint64_t SH_FLD_CFG_SELCR2 = 4645; // 1 -static const uint64_t SH_FLD_CFG_SELCR2_LEN = 4646; // 1 -static const uint64_t SH_FLD_CFG_SELCR3 = 4647; // 1 -static const uint64_t SH_FLD_CFG_SELCR3_LEN = 4648; // 1 -static const uint64_t SH_FLD_CFG_SELECT = 4649; // 3 -static const uint64_t SH_FLD_CFG_SELECT_LEN = 4650; // 3 -static const uint64_t SH_FLD_CFG_SELRT = 4651; // 1 -static const uint64_t SH_FLD_CFG_SELRT_LEN = 4652; // 1 -static const uint64_t SH_FLD_CFG_SELSN0 = 4653; // 1 -static const uint64_t SH_FLD_CFG_SELSN0_LEN = 4654; // 1 -static const uint64_t SH_FLD_CFG_SELSN1 = 4655; // 1 -static const uint64_t SH_FLD_CFG_SELSN1_LEN = 4656; // 1 -static const uint64_t SH_FLD_CFG_SELSN2 = 4657; // 1 -static const uint64_t SH_FLD_CFG_SELSN2_LEN = 4658; // 1 -static const uint64_t SH_FLD_CFG_SELSN3 = 4659; // 1 -static const uint64_t SH_FLD_CFG_SELSN3_LEN = 4660; // 1 -static const uint64_t SH_FLD_CFG_SHIFT_COUNT = 4661; // 3 -static const uint64_t SH_FLD_CFG_SHIFT_COUNT_LEN = 4662; // 3 -static const uint64_t SH_FLD_CFG_SHIFT_DATA = 4663; // 3 -static const uint64_t SH_FLD_CFG_SHIFT_DATA_LEN = 4664; // 3 -static const uint64_t SH_FLD_CFG_SIM_FAST_NOISE_WINDOW = 4665; // 8 -static const uint64_t SH_FLD_CFG_SINGLE_MEM = 4666; // 12 -static const uint64_t SH_FLD_CFG_SINGLE_MEM_EN = 4667; // 12 -static const uint64_t SH_FLD_CFG_SINGLE_MEM_LEN = 4668; // 12 -static const uint64_t SH_FLD_CFG_SLOT0_S0_CID = 4669; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S0_CID_LEN = 4670; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S1_CID = 4671; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S1_CID_LEN = 4672; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S2_CID = 4673; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S2_CID_LEN = 4674; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S3_CID = 4675; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S3_CID_LEN = 4676; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S4_CID = 4677; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S4_CID_LEN = 4678; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S5_CID = 4679; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S5_CID_LEN = 4680; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S6_CID = 4681; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S6_CID_LEN = 4682; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S7_CID = 4683; // 8 -static const uint64_t SH_FLD_CFG_SLOT0_S7_CID_LEN = 4684; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S0_CID = 4685; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S0_CID_LEN = 4686; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S1_CID = 4687; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S1_CID_LEN = 4688; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S2_CID = 4689; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S2_CID_LEN = 4690; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S3_CID = 4691; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S3_CID_LEN = 4692; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S4_CID = 4693; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S4_CID_LEN = 4694; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S5_CID = 4695; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S5_CID_LEN = 4696; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S6_CID = 4697; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S6_CID_LEN = 4698; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S7_CID = 4699; // 8 -static const uint64_t SH_FLD_CFG_SLOT1_S7_CID_LEN = 4700; // 8 -static const uint64_t SH_FLD_CFG_SLOW = 4701; // 3 -static const uint64_t SH_FLD_CFG_SMP_OPTICS = 4702; // 6 -static const uint64_t SH_FLD_CFG_SMT_MODE = 4703; // 1 -static const uint64_t SH_FLD_CFG_SMT_MODE_LEN = 4704; // 1 -static const uint64_t SH_FLD_CFG_SP_HW_MARK = 4705; // 3 -static const uint64_t SH_FLD_CFG_SP_HW_MARK_LEN = 4706; // 3 -static const uint64_t SH_FLD_CFG_STALL_PULL = 4707; // 1 -static const uint64_t SH_FLD_CFG_STALL_PUSH_ARX = 4708; // 1 -static const uint64_t SH_FLD_CFG_STALL_PUSH_LCL = 4709; // 1 -static const uint64_t SH_FLD_CFG_START_ADDR_0 = 4710; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_0_LEN = 4711; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_1 = 4712; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_1_LEN = 4713; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_2 = 4714; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_2_LEN = 4715; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_3 = 4716; // 2 -static const uint64_t SH_FLD_CFG_START_ADDR_3_LEN = 4717; // 2 -static const uint64_t SH_FLD_CFG_STATIC_IDLE_DLY = 4718; // 8 -static const uint64_t SH_FLD_CFG_STATIC_IDLE_DLY_LEN = 4719; // 8 -static const uint64_t SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP = 4720; // 43 -static const uint64_t SH_FLD_CFG_STQ_PF_EN = 4721; // 12 -static const uint64_t SH_FLD_CFG_STR_ENABLE = 4722; // 8 -static const uint64_t SH_FLD_CFG_STR_STATE = 4723; // 8 -static const uint64_t SH_FLD_CFG_SWITCH_CD_PULSE = 4724; // 3 -static const uint64_t SH_FLD_CFG_SWITCH_OPTION_AB = 4725; // 3 -static const uint64_t SH_FLD_CFG_SW_AB_WAIT = 4726; // 3 -static const uint64_t SH_FLD_CFG_SW_AB_WAIT_LEN = 4727; // 3 -static const uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE = 4728; // 2 -static const uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN = 4729; // 2 -static const uint64_t SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL = 4730; // 12 -static const uint64_t SH_FLD_CFG_TCKESR = 4731; // 8 -static const uint64_t SH_FLD_CFG_TCKESR_LEN = 4732; // 8 -static const uint64_t SH_FLD_CFG_TCKSRE = 4733; // 8 -static const uint64_t SH_FLD_CFG_TCKSRE_LEN = 4734; // 8 -static const uint64_t SH_FLD_CFG_TCKSRX = 4735; // 8 -static const uint64_t SH_FLD_CFG_TCKSRX_LEN = 4736; // 8 -static const uint64_t SH_FLD_CFG_TFAW = 4737; // 8 -static const uint64_t SH_FLD_CFG_TFAW_LEN = 4738; // 8 -static const uint64_t SH_FLD_CFG_THRD_C0_EN = 4739; // 1 -static const uint64_t SH_FLD_CFG_THRD_C0_EN_LEN = 4740; // 1 -static const uint64_t SH_FLD_CFG_THRD_C10_EN = 4741; // 1 -static const uint64_t SH_FLD_CFG_THRD_C10_EN_LEN = 4742; // 1 -static const uint64_t SH_FLD_CFG_THRD_C11_EN = 4743; // 1 -static const uint64_t SH_FLD_CFG_THRD_C11_EN_LEN = 4744; // 1 -static const uint64_t SH_FLD_CFG_THRD_C1_EN = 4745; // 1 -static const uint64_t SH_FLD_CFG_THRD_C1_EN_LEN = 4746; // 1 -static const uint64_t SH_FLD_CFG_THRD_C2_EN = 4747; // 1 -static const uint64_t SH_FLD_CFG_THRD_C2_EN_LEN = 4748; // 1 -static const uint64_t SH_FLD_CFG_THRD_C3_EN = 4749; // 1 -static const uint64_t SH_FLD_CFG_THRD_C3_EN_LEN = 4750; // 1 -static const uint64_t SH_FLD_CFG_THRD_C4_EN = 4751; // 1 -static const uint64_t SH_FLD_CFG_THRD_C4_EN_LEN = 4752; // 1 -static const uint64_t SH_FLD_CFG_THRD_C5_EN = 4753; // 1 -static const uint64_t SH_FLD_CFG_THRD_C5_EN_LEN = 4754; // 1 -static const uint64_t SH_FLD_CFG_THRD_C6_EN = 4755; // 1 -static const uint64_t SH_FLD_CFG_THRD_C6_EN_LEN = 4756; // 1 -static const uint64_t SH_FLD_CFG_THRD_C7_EN = 4757; // 1 -static const uint64_t SH_FLD_CFG_THRD_C7_EN_LEN = 4758; // 1 -static const uint64_t SH_FLD_CFG_THRD_C8_EN = 4759; // 1 -static const uint64_t SH_FLD_CFG_THRD_C8_EN_LEN = 4760; // 1 -static const uint64_t SH_FLD_CFG_THRD_C9_EN = 4761; // 1 -static const uint64_t SH_FLD_CFG_THRD_C9_EN_LEN = 4762; // 1 -static const uint64_t SH_FLD_CFG_THRESH_MAG_ICE = 4763; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_ICE_LEN = 4764; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD = 4765; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN = 4766; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT = 4767; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN = 4768; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT = 4769; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN = 4770; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD = 4771; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN = 4772; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT = 4773; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN = 4774; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT = 4775; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN = 4776; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_RCE = 4777; // 2 -static const uint64_t SH_FLD_CFG_THRESH_MAG_RCE_LEN = 4778; // 2 -static const uint64_t SH_FLD_CFG_TIME_BASE_TMR0 = 4779; // 8 -static const uint64_t SH_FLD_CFG_TIME_BASE_TMR0_LEN = 4780; // 8 -static const uint64_t SH_FLD_CFG_TIME_BASE_TMR1 = 4781; // 8 -static const uint64_t SH_FLD_CFG_TIME_BASE_TMR1_LEN = 4782; // 8 -static const uint64_t SH_FLD_CFG_TIME_BASE_TMR2 = 4783; // 8 -static const uint64_t SH_FLD_CFG_TIME_BASE_TMR2_LEN = 4784; // 8 -static const uint64_t SH_FLD_CFG_TM_MASTER = 4785; // 6 -static const uint64_t SH_FLD_CFG_TRAS = 4786; // 8 -static const uint64_t SH_FLD_CFG_TRAS_LEN = 4787; // 8 -static const uint64_t SH_FLD_CFG_TRCD = 4788; // 8 -static const uint64_t SH_FLD_CFG_TRCD_LEN = 4789; // 8 -static const uint64_t SH_FLD_CFG_TRFC = 4790; // 8 -static const uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS = 4791; // 8 -static const uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS_LEN = 4792; // 8 -static const uint64_t SH_FLD_CFG_TRFC_LEN = 4793; // 8 -static const uint64_t SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF = 4794; // 8 -static const uint64_t SH_FLD_CFG_TRP = 4795; // 8 -static const uint64_t SH_FLD_CFG_TRP_LEN = 4796; // 8 -static const uint64_t SH_FLD_CFG_TSIZE = 4797; // 2 -static const uint64_t SH_FLD_CFG_TSIZE_LEN = 4798; // 2 -static const uint64_t SH_FLD_CFG_TSIZE_MASK = 4799; // 2 -static const uint64_t SH_FLD_CFG_TSIZE_MASK_LEN = 4800; // 2 -static const uint64_t SH_FLD_CFG_TTAG = 4801; // 2 -static const uint64_t SH_FLD_CFG_TTAG_LEN = 4802; // 2 -static const uint64_t SH_FLD_CFG_TTAG_MASK = 4803; // 2 -static const uint64_t SH_FLD_CFG_TTAG_MASK_LEN = 4804; // 2 -static const uint64_t SH_FLD_CFG_TTYPE = 4805; // 2 -static const uint64_t SH_FLD_CFG_TTYPE_LEN = 4806; // 2 -static const uint64_t SH_FLD_CFG_TTYPE_MASK = 4807; // 2 -static const uint64_t SH_FLD_CFG_TTYPE_MASK_LEN = 4808; // 2 -static const uint64_t SH_FLD_CFG_TXSDLL = 4809; // 8 -static const uint64_t SH_FLD_CFG_TXSDLL_LEN = 4810; // 8 -static const uint64_t SH_FLD_CFG_VAS_MASK = 4811; // 1 -static const uint64_t SH_FLD_CFG_VG_LVL0 = 4812; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL0_LEN = 4813; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL1 = 4814; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL1_LEN = 4815; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL2 = 4816; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL2_LEN = 4817; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL3 = 4818; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL3_LEN = 4819; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL4 = 4820; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL4_LEN = 4821; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL5 = 4822; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL5_LEN = 4823; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL6 = 4824; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL6_LEN = 4825; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL7 = 4826; // 2 -static const uint64_t SH_FLD_CFG_VG_LVL7_LEN = 4827; // 2 -static const uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 4828; // 2 -static const uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4829; // 2 -static const uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 4830; // 2 -static const uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4831; // 2 -static const uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE = 4832; // 2 -static const uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4833; // 2 -static const uint64_t SH_FLD_CFG_WAT_CAL_SYNC = 4834; // 8 -static const uint64_t SH_FLD_CFG_WAT_CAL_SYNC_LEN = 4835; // 8 -static const uint64_t SH_FLD_CFG_WAT_CNTL = 4836; // 8 -static const uint64_t SH_FLD_CFG_WAT_CNTL_LEN = 4837; // 8 -static const uint64_t SH_FLD_CFG_WAT_CNT_VALUE = 4838; // 2 -static const uint64_t SH_FLD_CFG_WAT_CNT_VALUE_LEN = 4839; // 2 -static const uint64_t SH_FLD_CFG_WAT_DIS_RD_PG = 4840; // 8 -static const uint64_t SH_FLD_CFG_WAT_DIS_RD_PG_LEN = 4841; // 8 -static const uint64_t SH_FLD_CFG_WAT_DIS_WR_PG = 4842; // 8 -static const uint64_t SH_FLD_CFG_WAT_DIS_WR_PG_LEN = 4843; // 8 -static const uint64_t SH_FLD_CFG_WAT_EMER_TH = 4844; // 8 -static const uint64_t SH_FLD_CFG_WAT_EMER_TH_LEN = 4845; // 8 -static const uint64_t SH_FLD_CFG_WAT_ENABLE = 4846; // 2 -static const uint64_t SH_FLD_CFG_WAT_EVENT_SEL = 4847; // 8 -static const uint64_t SH_FLD_CFG_WAT_EVENT_SEL_LEN = 4848; // 8 -static const uint64_t SH_FLD_CFG_WAT_EXIT_STR = 4849; // 8 -static const uint64_t SH_FLD_CFG_WAT_EXIT_STR_LEN = 4850; // 8 -static const uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL = 4851; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL_LEN = 4852; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT = 4853; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT_LEN = 4854; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL = 4855; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL_LEN = 4856; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL = 4857; // 2 -static const uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL_LEN = 4858; // 2 -static const uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT = 4859; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT_LEN = 4860; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_REF_GT = 4861; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_REF_GT_LEN = 4862; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT = 4863; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT_LEN = 4864; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT = 4865; // 8 -static const uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT_LEN = 4866; // 8 -static const uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP = 4867; // 8 -static const uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4868; // 8 -static const uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP = 4869; // 8 -static const uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4870; // 8 -static const uint64_t SH_FLD_CFG_WAT_FP_DIS = 4871; // 8 -static const uint64_t SH_FLD_CFG_WAT_FP_DIS_LEN = 4872; // 8 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL = 4873; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL_LEN = 4874; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL = 4875; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL_LEN = 4876; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL = 4877; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL_LEN = 4878; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL = 4879; // 2 -static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL_LEN = 4880; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL = 4881; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL_LEN = 4882; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL = 4883; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL_LEN = 4884; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL = 4885; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL_LEN = 4886; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL = 4887; // 2 -static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL_LEN = 4888; // 2 -static const uint64_t SH_FLD_CFG_WAT_MSKA = 4889; // 8 -static const uint64_t SH_FLD_CFG_WAT_MSKA_LEN = 4890; // 8 -static const uint64_t SH_FLD_CFG_WAT_MSKB = 4891; // 8 -static const uint64_t SH_FLD_CFG_WAT_MSKB_LEN = 4892; // 8 -static const uint64_t SH_FLD_CFG_WAT_OUTPUT_PULSE = 4893; // 2 -static const uint64_t SH_FLD_CFG_WAT_PATA = 4894; // 8 -static const uint64_t SH_FLD_CFG_WAT_PATA_LEN = 4895; // 8 -static const uint64_t SH_FLD_CFG_WAT_PATB = 4896; // 8 -static const uint64_t SH_FLD_CFG_WAT_PATB_LEN = 4897; // 8 -static const uint64_t SH_FLD_CFG_WAT_PUP_ALL = 4898; // 8 -static const uint64_t SH_FLD_CFG_WAT_PUP_ALL_LEN = 4899; // 8 -static const uint64_t SH_FLD_CFG_WAT_REF_HP = 4900; // 8 -static const uint64_t SH_FLD_CFG_WAT_REF_HP_LEN = 4901; // 8 -static const uint64_t SH_FLD_CFG_WAT_REF_SAFE = 4902; // 8 -static const uint64_t SH_FLD_CFG_WAT_REF_SAFE_LEN = 4903; // 8 -static const uint64_t SH_FLD_CFG_WAT_REF_SYNC = 4904; // 8 -static const uint64_t SH_FLD_CFG_WAT_REF_SYNC_LEN = 4905; // 8 -static const uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT = 4906; // 8 -static const uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT_LEN = 4907; // 8 -static const uint64_t SH_FLD_CFG_WAT_SET_FIR = 4908; // 8 -static const uint64_t SH_FLD_CFG_WAT_SET_FIR_LEN = 4909; // 8 -static const uint64_t SH_FLD_CFG_WAT_START_RECOVERY = 4910; // 8 -static const uint64_t SH_FLD_CFG_WAT_START_RECOVERY_LEN = 4911; // 8 -static const uint64_t SH_FLD_CFG_WAT_TMR_VALUE = 4912; // 2 -static const uint64_t SH_FLD_CFG_WAT_TMR_VALUE_LEN = 4913; // 2 -static const uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT = 4914; // 8 -static const uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT_LEN = 4915; // 8 -static const uint64_t SH_FLD_CFG_WDF_SERIAL_SEQ_MODE = 4916; // 8 -static const uint64_t SH_FLD_CFG_WODT_BC4_END_DLY = 4917; // 8 -static const uint64_t SH_FLD_CFG_WODT_BC4_END_DLY_LEN = 4918; // 8 -static const uint64_t SH_FLD_CFG_WODT_END_DLY = 4919; // 8 -static const uint64_t SH_FLD_CFG_WODT_END_DLY_LEN = 4920; // 8 -static const uint64_t SH_FLD_CFG_WODT_START_DLY = 4921; // 8 -static const uint64_t SH_FLD_CFG_WODT_START_DLY_LEN = 4922; // 8 -static const uint64_t SH_FLD_CFG_WR2PRE = 4923; // 8 -static const uint64_t SH_FLD_CFG_WR2PRE_LEN = 4924; // 8 -static const uint64_t SH_FLD_CFG_WRDATA_DLY = 4925; // 8 -static const uint64_t SH_FLD_CFG_WRDATA_DLY_LEN = 4926; // 8 -static const uint64_t SH_FLD_CFG_WRDONE_DLY = 4927; // 8 -static const uint64_t SH_FLD_CFG_WRDONE_DLY_LEN = 4928; // 8 -static const uint64_t SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE = 4929; // 6 -static const uint64_t SH_FLD_CFG_WRITE_HW_MARK = 4930; // 8 -static const uint64_t SH_FLD_CFG_WRITE_HW_MARK_LEN = 4931; // 8 -static const uint64_t SH_FLD_CFG_WRITE_LW_MARK = 4932; // 8 -static const uint64_t SH_FLD_CFG_WRITE_LW_MARK_LEN = 4933; // 8 -static const uint64_t SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS = 4934; // 16 -static const uint64_t SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS = 4935; // 16 -static const uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING = 4936; // 8 -static const uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4937; // 8 -static const uint64_t SH_FLD_CFG_WRQ_DEPTH = 4938; // 8 -static const uint64_t SH_FLD_CFG_WRQ_DEPTH_LEN = 4939; // 8 -static const uint64_t SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR = 4940; // 8 -static const uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY = 4941; // 8 -static const uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN = 4942; // 8 -static const uint64_t SH_FLD_CFG_WRQ_FIFO_MODE = 4943; // 8 -static const uint64_t SH_FLD_CFG_WRQ_FLUSH_WR_RANK = 4944; // 8 -static const uint64_t SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE = 4945; // 8 -static const uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT = 4946; // 8 -static const uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN = 4947; // 8 -static const uint64_t SH_FLD_CFG_XLATE_ADDR_TO_ID = 4948; // 6 -static const uint64_t SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN = 4949; // 6 -static const uint64_t SH_FLD_CFG_X_AGGREGATE = 4950; // 6 -static const uint64_t SH_FLD_CFG_X_CMD_RATE = 4951; // 6 -static const uint64_t SH_FLD_CFG_X_CMD_RATE_LEN = 4952; // 6 -static const uint64_t SH_FLD_CFG_X_FP_DISABLED = 4953; // 6 -static const uint64_t SH_FLD_CFG_X_GATHER_ENABLE = 4954; // 6 -static const uint64_t SH_FLD_CFG_X_INDIRECT_EN = 4955; // 6 -static const uint64_t SH_FLD_CGC = 4956; // 24 -static const uint64_t SH_FLD_CGC_LEN = 4957; // 24 -static const uint64_t SH_FLD_CH0EFT_ACTION = 4958; // 1 -static const uint64_t SH_FLD_CH0EFT_ENA = 4959; // 1 -static const uint64_t SH_FLD_CH0EFT_SELECT = 4960; // 1 -static const uint64_t SH_FLD_CH0EFT_SELECT_LEN = 4961; // 1 -static const uint64_t SH_FLD_CH0EFT_TYPE = 4962; // 1 -static const uint64_t SH_FLD_CH0_842_ECC_CE = 4963; // 1 -static const uint64_t SH_FLD_CH0_842_ECC_UE = 4964; // 1 -static const uint64_t SH_FLD_CH0_CMD_CREDITS_0_5 = 4965; // 1 -static const uint64_t SH_FLD_CH0_CMD_CREDITS_0_5_LEN = 4966; // 1 -static const uint64_t SH_FLD_CH0_EFT = 4967; // 1 -static const uint64_t SH_FLD_CH0_INVALID_STATE = 4968; // 1 -static const uint64_t SH_FLD_CH0_MAX = 4969; // 2 -static const uint64_t SH_FLD_CH0_MAX_LEN = 4970; // 2 -static const uint64_t SH_FLD_CH0_REF_DIV = 4971; // 1 -static const uint64_t SH_FLD_CH0_REF_DIV_LEN = 4972; // 1 -static const uint64_t SH_FLD_CH0_TIMER_ENBL = 4973; // 1 -static const uint64_t SH_FLD_CH1EFT_ACTION = 4974; // 1 -static const uint64_t SH_FLD_CH1EFT_ENA = 4975; // 1 -static const uint64_t SH_FLD_CH1EFT_SELECT = 4976; // 1 -static const uint64_t SH_FLD_CH1EFT_SELECT_LEN = 4977; // 1 -static const uint64_t SH_FLD_CH1EFT_TYPE = 4978; // 1 -static const uint64_t SH_FLD_CH1_842_ECC_CE = 4979; // 1 -static const uint64_t SH_FLD_CH1_842_ECC_UE = 4980; // 1 -static const uint64_t SH_FLD_CH1_CMD_CREDITS_0_5 = 4981; // 1 -static const uint64_t SH_FLD_CH1_CMD_CREDITS_0_5_LEN = 4982; // 1 -static const uint64_t SH_FLD_CH1_DAT_CREDITS_0_5 = 4983; // 1 -static const uint64_t SH_FLD_CH1_DAT_CREDITS_0_5_LEN = 4984; // 1 -static const uint64_t SH_FLD_CH1_EFT = 4985; // 1 -static const uint64_t SH_FLD_CH1_INVALID_STATE = 4986; // 1 -static const uint64_t SH_FLD_CH1_MAX = 4987; // 2 -static const uint64_t SH_FLD_CH1_MAX_LEN = 4988; // 2 -static const uint64_t SH_FLD_CH1_REF_DIV = 4989; // 1 -static const uint64_t SH_FLD_CH1_REF_DIV_LEN = 4990; // 1 -static const uint64_t SH_FLD_CH1_TIMER_ENBL = 4991; // 1 -static const uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5 = 4992; // 1 -static const uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN = 4993; // 1 -static const uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5 = 4994; // 1 -static const uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN = 4995; // 1 -static const uint64_t SH_FLD_CH2_INVALID_STATE = 4996; // 1 -static const uint64_t SH_FLD_CH2_MAX = 4997; // 2 -static const uint64_t SH_FLD_CH2_MAX_LEN = 4998; // 2 -static const uint64_t SH_FLD_CH2_REF_DIV = 4999; // 1 -static const uint64_t SH_FLD_CH2_REF_DIV_LEN = 5000; // 1 -static const uint64_t SH_FLD_CH2_SYM = 5001; // 1 -static const uint64_t SH_FLD_CH2_TIMER_ENBL = 5002; // 1 -static const uint64_t SH_FLD_CH3_INVALID_STATE = 5003; // 1 -static const uint64_t SH_FLD_CH3_MAX = 5004; // 2 -static const uint64_t SH_FLD_CH3_MAX_LEN = 5005; // 2 -static const uint64_t SH_FLD_CH3_REF_DIV = 5006; // 1 -static const uint64_t SH_FLD_CH3_REF_DIV_LEN = 5007; // 1 -static const uint64_t SH_FLD_CH3_SYM = 5008; // 1 -static const uint64_t SH_FLD_CH3_TIMER_ENBL = 5009; // 1 -static const uint64_t SH_FLD_CH4GZIP_ACTION = 5010; // 1 -static const uint64_t SH_FLD_CH4GZIP_ENA = 5011; // 1 -static const uint64_t SH_FLD_CH4GZIP_SELECT = 5012; // 1 -static const uint64_t SH_FLD_CH4GZIP_SELECT_LEN = 5013; // 1 -static const uint64_t SH_FLD_CH4GZIP_TYPE = 5014; // 1 -static const uint64_t SH_FLD_CH4_AMF_ECC_CE = 5015; // 1 -static const uint64_t SH_FLD_CH4_AMF_ECC_UE = 5016; // 1 -static const uint64_t SH_FLD_CH4_GZIP = 5017; // 1 -static const uint64_t SH_FLD_CH4_INVALID_STATE = 5018; // 1 -static const uint64_t SH_FLD_CH4_REF_DIV = 5019; // 1 -static const uint64_t SH_FLD_CH4_REF_DIV_LEN = 5020; // 1 -static const uint64_t SH_FLD_CH4_TIMER_ENBL = 5021; // 1 -static const uint64_t SH_FLD_CH5_AMF_ECC_CE = 5022; // 1 -static const uint64_t SH_FLD_CH5_AMF_ECC_UE = 5023; // 1 -static const uint64_t SH_FLD_CH5_INVALID_STATE = 5024; // 1 -static const uint64_t SH_FLD_CH6_AMF_ECC_CE = 5025; // 1 -static const uint64_t SH_FLD_CH6_AMF_ECC_UE = 5026; // 1 -static const uint64_t SH_FLD_CH6_INVALID_STATE = 5027; // 1 -static const uint64_t SH_FLD_CH7_AMF_ECC_CE = 5028; // 1 -static const uint64_t SH_FLD_CH7_AMF_ECC_UE = 5029; // 1 -static const uint64_t SH_FLD_CH7_INVALID_STATE = 5030; // 1 -static const uint64_t SH_FLD_CHANGE_IN_PROGRESS = 5031; // 2 -static const uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 5032; // 4 -static const uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 5033; // 4 -static const uint64_t SH_FLD_CHANNEL_0_TIMEOUT_ERROR = 5034; // 4 -static const uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 5035; // 4 -static const uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 5036; // 4 -static const uint64_t SH_FLD_CHANNEL_1_TIMEOUT_ERROR = 5037; // 4 -static const uint64_t SH_FLD_CHANNEL_SELECT = 5038; // 4 -static const uint64_t SH_FLD_CHANNEL_SELECT_LEN = 5039; // 4 -static const uint64_t SH_FLD_CHAN_FAIL_MASK = 5040; // 4 -static const uint64_t SH_FLD_CHAN_FAIL_MASK_LEN = 5041; // 4 -static const uint64_t SH_FLD_CHECKSTOP = 5042; // 1 -static const uint64_t SH_FLD_CHECK_CMDS = 5043; // 2 -static const uint64_t SH_FLD_CHECK_CMDS_EN = 5044; // 2 -static const uint64_t SH_FLD_CHECK_CMDS_LEN = 5045; // 2 -static const uint64_t SH_FLD_CHECK_STOP_GPE0 = 5046; // 1 -static const uint64_t SH_FLD_CHECK_STOP_GPE1 = 5047; // 1 -static const uint64_t SH_FLD_CHECK_STOP_GPE2 = 5048; // 1 -static const uint64_t SH_FLD_CHECK_STOP_GPE3 = 5049; // 1 -static const uint64_t SH_FLD_CHECK_STOP_PPC405 = 5050; // 1 -static const uint64_t SH_FLD_CHGRATE = 5051; // 12 -static const uint64_t SH_FLD_CHICKEN_SWITCH = 5052; // 1 -static const uint64_t SH_FLD_CHIPLET_ATOMIC_LOCK = 5053; // 43 -static const uint64_t SH_FLD_CHIPLET_ENABLE = 5054; // 43 -static const uint64_t SH_FLD_CHIPLET_ERRORS = 5055; // 43 -static const uint64_t SH_FLD_CHIPLET_ERRORS_LEN = 5056; // 43 -static const uint64_t SH_FLD_CHIPLET_GRID_SKITTER = 5057; // 43 -static const uint64_t SH_FLD_CHIPLET_INTERRUPT_FROM_HOST = 5058; // 1 -static const uint64_t SH_FLD_CHIPLET_IS_ALIGNED = 5059; // 43 -static const uint64_t SH_FLD_CHIPLET_OFFLINE = 5060; // 43 -static const uint64_t SH_FLD_CHIPMARK = 5061; // 72 -static const uint64_t SH_FLD_CHIPMARK_LEN = 5062; // 72 -static const uint64_t SH_FLD_CHIPPOS = 5063; // 1 -static const uint64_t SH_FLD_CHIP_INTERFACEMODE = 5064; // 2 -static const uint64_t SH_FLD_CHIP_PERSONALISATION = 5065; // 2 -static const uint64_t SH_FLD_CHIP_RESET = 5066; // 1 -static const uint64_t SH_FLD_CHIP_STATUS = 5067; // 194 -static const uint64_t SH_FLD_CHIP_STATUS_LEN = 5068; // 194 -static const uint64_t SH_FLD_CHIP_TOD_STATUS = 5069; // 98 -static const uint64_t SH_FLD_CHIP_TOD_STATUS_LEN = 5070; // 98 -static const uint64_t SH_FLD_CHKSW_ALLOW1_RD = 5071; // 1 -static const uint64_t SH_FLD_CHKSW_ALLOW1_RDWR = 5072; // 1 -static const uint64_t SH_FLD_CHKSW_ALLOW1_WR = 5073; // 1 -static const uint64_t SH_FLD_CHKSW_AR012 = 5074; // 3 -static const uint64_t SH_FLD_CHKSW_AR012_0 = 5075; // 1 -static const uint64_t SH_FLD_CHKSW_AR012_1 = 5076; // 1 -static const uint64_t SH_FLD_CHKSW_AR012_2 = 5077; // 1 -static const uint64_t SH_FLD_CHKSW_AR012_3 = 5078; // 1 -static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_0 = 5079; // 1 -static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_1 = 5080; // 1 -static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_2 = 5081; // 1 -static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_3 = 5082; // 1 -static const uint64_t SH_FLD_CHKSW_I2C_BUSY_0 = 5083; // 2 -static const uint64_t SH_FLD_CHKSW_I2C_BUSY_1 = 5084; // 1 -static const uint64_t SH_FLD_CHKSW_I2C_BUSY_2 = 5085; // 1 -static const uint64_t SH_FLD_CHKSW_I2C_BUSY_3 = 5086; // 1 -static const uint64_t SH_FLD_CHKSW_OCI_PARCHK_DIS = 5087; // 1 -static const uint64_t SH_FLD_CHKSW_SO_SPARE = 5088; // 1 -static const uint64_t SH_FLD_CHKSW_SO_SPARE_LEN = 5089; // 1 -static const uint64_t SH_FLD_CHKSW_SPARE_6 = 5090; // 1 -static const uint64_t SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS = 5091; // 1 -static const uint64_t SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS = 5092; // 1 -static const uint64_t SH_FLD_CHKSW_WRFSM_DLY_DIS = 5093; // 1 -static const uint64_t SH_FLD_CHOP1G = 5094; // 1 -static const uint64_t SH_FLD_CHSW_DIS_DATA_HANG = 5095; // 1 -static const uint64_t SH_FLD_CHSW_DIS_ECC_CHECK = 5096; // 1 -static const uint64_t SH_FLD_CHSW_DIS_GROUP_SCOPE = 5097; // 1 -static const uint64_t SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK = 5098; // 1 -static const uint64_t SH_FLD_CHSW_DIS_OCIBEPAR_CHECK = 5099; // 1 -static const uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK = 5100; // 1 -static const uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_GEN = 5101; // 1 -static const uint64_t SH_FLD_CHSW_DIS_OPER_HANG = 5102; // 1 -static const uint64_t SH_FLD_CHSW_DIS_PB_PARITY_CHK = 5103; // 1 -static const uint64_t SH_FLD_CHSW_DIS_RETRY_BACKOFF = 5104; // 1 -static const uint64_t SH_FLD_CHSW_DIS_RTAG_PARITY_CHK = 5105; // 1 -static const uint64_t SH_FLD_CHSW_DIS_WRITE_MATCH_REARB = 5106; // 1 -static const uint64_t SH_FLD_CHSW_EXIT_ON_INVALID_CRESP = 5107; // 1 -static const uint64_t SH_FLD_CHSW_HANG_ON_ADRERROR = 5108; // 1 -static const uint64_t SH_FLD_CHSW_HANG_ON_DERROR = 5109; // 1 -static const uint64_t SH_FLD_CHSW_SKIP_GROUP_SCOPE = 5110; // 1 -static const uint64_t SH_FLD_CHSW_USE_CL_DMA_INJ = 5111; // 1 -static const uint64_t SH_FLD_CHSW_USE_PR_DMA_INJ = 5112; // 1 -static const uint64_t SH_FLD_CHTM_PURGE_C0 = 5113; // 12 -static const uint64_t SH_FLD_CHTM_PURGE_C1 = 5114; // 12 -static const uint64_t SH_FLD_CHTM_PURGE_DONE_C0 = 5115; // 24 -static const uint64_t SH_FLD_CHTM_PURGE_DONE_C1 = 5116; // 24 -static const uint64_t SH_FLD_CI_BUFF_AVAIL = 5117; // 2 -static const uint64_t SH_FLD_CI_BUFF_MIN = 5118; // 2 -static const uint64_t SH_FLD_CI_BUFF_MIN_LEN = 5119; // 2 -static const uint64_t SH_FLD_CI_LOAD = 5120; // 2 -static const uint64_t SH_FLD_CI_LOAD_LEN = 5121; // 2 -static const uint64_t SH_FLD_CI_MACHINE_HANG = 5122; // 12 -static const uint64_t SH_FLD_CI_READ = 5123; // 1 -static const uint64_t SH_FLD_CI_SM_CTL_ERR_DET = 5124; // 1 -static const uint64_t SH_FLD_CI_STORE = 5125; // 1 -static const uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD = 5126; // 2 -static const uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN = 5127; // 2 -static const uint64_t SH_FLD_CI_STORE_LEN = 5128; // 1 -static const uint64_t SH_FLD_CI_STORE_RMT = 5129; // 1 -static const uint64_t SH_FLD_CI_STORE_RMT_LEN = 5130; // 1 -static const uint64_t SH_FLD_CI_STORE_RMT_VC = 5131; // 1 -static const uint64_t SH_FLD_CI_STORE_RMT_VC_LEN = 5132; // 1 -static const uint64_t SH_FLD_CI_TIMEOUT_ERR_DET = 5133; // 1 -static const uint64_t SH_FLD_CI_WRITE = 5134; // 1 -static const uint64_t SH_FLD_CKINSM_DIS = 5135; // 1 -static const uint64_t SH_FLD_CKINSM_DIS_LEN = 5136; // 1 -static const uint64_t SH_FLD_CKIN_PROT_ERR_CHK_DIS = 5137; // 1 -static const uint64_t SH_FLD_CKIN_TIMEOUT_CHK_DIS = 5138; // 1 -static const uint64_t SH_FLD_CL = 5139; // 1 -static const uint64_t SH_FLD_CLEAR = 5140; // 1 -static const uint64_t SH_FLD_CLEAR_BAD_LANE_COUNTER = 5141; // 2 -static const uint64_t SH_FLD_CLEAR_CHIPLET_IS_ALIGNED = 5142; // 43 -static const uint64_t SH_FLD_CLEAR_LINK_FAIL_COUNTER = 5143; // 2 -static const uint64_t SH_FLD_CLEAR_STICKY_LEVEL = 5144; // 24 -static const uint64_t SH_FLD_CLKDIST_PDWN = 5145; // 12 -static const uint64_t SH_FLD_CLKDIST_PDWN_LEN = 5146; // 4 -static const uint64_t SH_FLD_CLKGLM_ASYNC_RESET = 5147; // 30 -static const uint64_t SH_FLD_CLKGLM_SEL = 5148; // 30 -static const uint64_t SH_FLD_CLK_ASYNC_RESET = 5149; // 43 -static const uint64_t SH_FLD_CLK_BIST_ACTIVITY_DET = 5150; // 4 -static const uint64_t SH_FLD_CLK_BIST_ERR = 5151; // 4 -static const uint64_t SH_FLD_CLK_DCC_BYPASS_EN = 5152; // 43 -static const uint64_t SH_FLD_CLK_DIV_BYPASS_EN = 5153; // 43 -static const uint64_t SH_FLD_CLK_DLY = 5154; // 1 -static const uint64_t SH_FLD_CLK_DLY_LEN = 5155; // 1 -static const uint64_t SH_FLD_CLK_HALF_WIDTH_MODE = 5156; // 4 -static const uint64_t SH_FLD_CLK_INVERT = 5157; // 6 -static const uint64_t SH_FLD_CLK_PDLY_BYPASS_EN = 5158; // 43 -static const uint64_t SH_FLD_CLK_PULSE_EN = 5159; // 43 -static const uint64_t SH_FLD_CLK_PULSE_MODE = 5160; // 43 -static const uint64_t SH_FLD_CLK_PULSE_MODE_LEN = 5161; // 43 -static const uint64_t SH_FLD_CLK_QUIESCE = 5162; // 4 -static const uint64_t SH_FLD_CLK_QUIESCE_LEN = 5163; // 4 -static const uint64_t SH_FLD_CLK_QUIESCE_N = 5164; // 1 -static const uint64_t SH_FLD_CLK_QUIESCE_N_LEN = 5165; // 1 -static const uint64_t SH_FLD_CLK_QUIESCE_P = 5166; // 1 -static const uint64_t SH_FLD_CLK_QUIESCE_P_LEN = 5167; // 1 -static const uint64_t SH_FLD_CLK_RATE = 5168; // 4 -static const uint64_t SH_FLD_CLK_RATE_LEN = 5169; // 4 -static const uint64_t SH_FLD_CLK_RATE_SEL = 5170; // 1 -static const uint64_t SH_FLD_CLK_RATE_SEL_LEN = 5171; // 1 -static const uint64_t SH_FLD_CLK_RUN_COUNT = 5172; // 4 -static const uint64_t SH_FLD_CLK_SB_PULSE_MODE = 5173; // 24 -static const uint64_t SH_FLD_CLK_SB_PULSE_MODE_EN = 5174; // 24 -static const uint64_t SH_FLD_CLK_SB_PULSE_MODE_LEN = 5175; // 24 -static const uint64_t SH_FLD_CLK_SB_SPARE = 5176; // 24 -static const uint64_t SH_FLD_CLK_SB_STRENGTH = 5177; // 24 -static const uint64_t SH_FLD_CLK_SB_STRENGTH_LEN = 5178; // 24 -static const uint64_t SH_FLD_CLK_SW_RESCLK = 5179; // 24 -static const uint64_t SH_FLD_CLK_SW_RESCLK_LEN = 5180; // 24 -static const uint64_t SH_FLD_CLK_SW_SPARE = 5181; // 24 -static const uint64_t SH_FLD_CLK_SYNC = 5182; // 24 -static const uint64_t SH_FLD_CLK_SYNC_DONE = 5183; // 24 -static const uint64_t SH_FLD_CLK_SYNC_ENABLE = 5184; // 24 -static const uint64_t SH_FLD_CLK_UNLOAD_CLK_DISABLE = 5185; // 4 -static const uint64_t SH_FLD_CLK_UNLOAD_SEL = 5186; // 4 -static const uint64_t SH_FLD_CLK_UNLOAD_SEL_LEN = 5187; // 4 -static const uint64_t SH_FLD_CLOCK_CMD = 5188; // 43 -static const uint64_t SH_FLD_CLOCK_CMD_LEN = 5189; // 43 -static const uint64_t SH_FLD_CLOCK_DIVIDER = 5190; // 1 -static const uint64_t SH_FLD_CLOCK_DIVIDER_LEN = 5191; // 1 -static const uint64_t SH_FLD_CLOCK_DIV_4 = 5192; // 3 -static const uint64_t SH_FLD_CLOCK_PERV = 5193; // 43 -static const uint64_t SH_FLD_CLOCK_PULSE_USE_EVEN = 5194; // 43 -static const uint64_t SH_FLD_CLOCK_RATE_SELECTION = 5195; // 3 -static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_0 = 5196; // 1 -static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_0_LEN = 5197; // 1 -static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_1 = 5198; // 2 -static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_1_LEN = 5199; // 2 -static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_LEN = 5200; // 3 -static const uint64_t SH_FLD_CLOCK_UNIT1 = 5201; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT10 = 5202; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT2 = 5203; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT3 = 5204; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT4 = 5205; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT5 = 5206; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT6 = 5207; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT7 = 5208; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT8 = 5209; // 43 -static const uint64_t SH_FLD_CLOCK_UNIT9 = 5210; // 43 -static const uint64_t SH_FLD_CLONE_CS_MODE = 5211; // 8 -static const uint64_t SH_FLD_CLR_PAR_ERRS = 5212; // 16 -static const uint64_t SH_FLD_CLSTATE_DEBUG_SEL = 5213; // 8 -static const uint64_t SH_FLD_CLSTATE_DEBUG_SEL_LEN = 5214; // 8 -static const uint64_t SH_FLD_CL_DATA = 5215; // 43 -static const uint64_t SH_FLD_CL_ECC_CE = 5216; // 1 -static const uint64_t SH_FLD_CL_ECC_UE = 5217; // 1 -static const uint64_t SH_FLD_CL_FINE_DISABLE = 5218; // 4 -static const uint64_t SH_FLD_CL_FINE_DISABLE_LEN = 5219; // 4 -static const uint64_t SH_FLD_CL_FSM = 5220; // 43 -static const uint64_t SH_FLD_CL_GLOBAL_DISABLE = 5221; // 4 -static const uint64_t SH_FLD_CL_GLOBAL_DISABLE_LEN = 5222; // 4 -static const uint64_t SH_FLD_CL_LEN = 5223; // 1 -static const uint64_t SH_FLD_CL_PROBE_PB_HANG = 5224; // 2 -static const uint64_t SH_FLD_CL_TIMEOUT_SEL = 5225; // 4 -static const uint64_t SH_FLD_CL_TIMEOUT_SEL_LEN = 5226; // 4 -static const uint64_t SH_FLD_CL_WRAP_DEBUG_SEL = 5227; // 8 -static const uint64_t SH_FLD_CL_WRAP_DEBUG_SEL_LEN = 5228; // 8 -static const uint64_t SH_FLD_CMD = 5229; // 43 -static const uint64_t SH_FLD_CMDREG_BROADCAST_FLAG = 5230; // 1 -static const uint64_t SH_FLD_CMDREG_SCAN_ADDRESS = 5231; // 1 -static const uint64_t SH_FLD_CMDREG_SCAN_ADDRESS_LEN = 5232; // 1 -static const uint64_t SH_FLD_CMDREG_SCAN_REGION = 5233; // 1 -static const uint64_t SH_FLD_CMDREG_SCAN_REGION_LEN = 5234; // 1 -static const uint64_t SH_FLD_CMDREG_SCAN_TYPE = 5235; // 1 -static const uint64_t SH_FLD_CMDREG_SCAN_TYPE_LEN = 5236; // 1 -static const uint64_t SH_FLD_CMDREG_WRITE_FLAG = 5237; // 1 -static const uint64_t SH_FLD_CMD_BUFFER_PAR_ERR = 5238; // 4 -static const uint64_t SH_FLD_CMD_COUNT_ERR = 5239; // 1 -static const uint64_t SH_FLD_CMD_EXP_TIME = 5240; // 7 -static const uint64_t SH_FLD_CMD_EXP_TIME_LEN = 5241; // 7 -static const uint64_t SH_FLD_CMD_IN_PROG = 5242; // 1 -static const uint64_t SH_FLD_CMD_LEN = 5243; // 43 -static const uint64_t SH_FLD_CMD_PARITY_ERROR = 5244; // 19 -static const uint64_t SH_FLD_CMD_PRECEDE_TIME = 5245; // 8 -static const uint64_t SH_FLD_CMD_PRECEDE_TIME_LEN = 5246; // 8 -static const uint64_t SH_FLD_CMD_QX_SEVERE_ERR = 5247; // 1 -static const uint64_t SH_FLD_CMD_REG = 5248; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_1 = 5249; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_1_LEN = 5250; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_2 = 5251; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_2_LEN = 5252; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_3 = 5253; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_3_LEN = 5254; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_4 = 5255; // 1 -static const uint64_t SH_FLD_CMD_REG_ADDR_4_LEN = 5256; // 1 -static const uint64_t SH_FLD_CMD_REG_BIT_READCONT = 5257; // 1 -static const uint64_t SH_FLD_CMD_REG_BIT_RNW = 5258; // 1 -static const uint64_t SH_FLD_CMD_REG_BIT_WITHADDR = 5259; // 1 -static const uint64_t SH_FLD_CMD_REG_BIT_WITHSTART = 5260; // 1 -static const uint64_t SH_FLD_CMD_REG_BIT_WITHSTOP = 5261; // 1 -static const uint64_t SH_FLD_CMD_REG_LEN = 5262; // 1 -static const uint64_t SH_FLD_CMD_REG_LENGTH = 5263; // 1 -static const uint64_t SH_FLD_CMD_REG_LENGTH_LEN = 5264; // 1 -static const uint64_t SH_FLD_CMD_SCOPE = 5265; // 4 -static const uint64_t SH_FLD_CMD_SCOPE_LEN = 5266; // 4 -static const uint64_t SH_FLD_CMD_STATUS = 5267; // 1 -static const uint64_t SH_FLD_CMD_STATUS_LEN = 5268; // 1 -static const uint64_t SH_FLD_CME0_IVRM_DROPOUT = 5269; // 6 -static const uint64_t SH_FLD_CME1_IVRM_DROPOUT = 5270; // 6 -static const uint64_t SH_FLD_CMETH = 5271; // 6 -static const uint64_t SH_FLD_CMETH_LEN = 5272; // 6 -static const uint64_t SH_FLD_CME_ERROR_NOTIFY = 5273; // 1 -static const uint64_t SH_FLD_CME_ERR_NOTIFY_DIS = 5274; // 24 -static const uint64_t SH_FLD_CME_INTERPPM_ACLK_ENABLE = 5275; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_ACLK_SEL = 5276; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_DPLL_ENABLE = 5277; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_DPLL_SEL = 5278; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_IVRM_ENABLE = 5279; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_IVRM_SEL = 5280; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_VDATA_ENABLE = 5281; // 6 -static const uint64_t SH_FLD_CME_INTERPPM_VDATA_SEL = 5282; // 6 -static const uint64_t SH_FLD_CME_MESSAGE = 5283; // 24 -static const uint64_t SH_FLD_CME_MESSAGE_HI = 5284; // 48 -static const uint64_t SH_FLD_CME_MESSAGE_HI_LEN = 5285; // 48 -static const uint64_t SH_FLD_CME_MESSAGE_LEN = 5286; // 24 -static const uint64_t SH_FLD_CME_MESSAGE_NUMBER0 = 5287; // 24 -static const uint64_t SH_FLD_CME_MESSAGE_NUMBER0_LEN = 5288; // 24 -static const uint64_t SH_FLD_CME_MESSAGE_NUMBER_N = 5289; // 72 -static const uint64_t SH_FLD_CME_MESSAGE_NUMBER_N_LEN = 5290; // 72 -static const uint64_t SH_FLD_CME_REQUEST = 5291; // 96 -static const uint64_t SH_FLD_CME_SPECIAL_WKUP_DONE_DIS = 5292; // 24 -static const uint64_t SH_FLD_CMFSI_ACCESS_PROTCT = 5293; // 1 -static const uint64_t SH_FLD_CMLEN = 5294; // 7 -static const uint64_t SH_FLD_CMLEN100 = 5295; // 3 -static const uint64_t SH_FLD_CMLEN133 = 5296; // 3 -static const uint64_t SH_FLD_CMLEN156 = 5297; // 3 -static const uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87 = 5298; // 90 -static const uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN = 5299; // 90 -static const uint64_t SH_FLD_CMP_MSK_LT_B_TO_63 = 5300; // 90 -static const uint64_t SH_FLD_CMP_MSK_LT_B_TO_63_LEN = 5301; // 90 -static const uint64_t SH_FLD_CMSK = 5302; // 43 -static const uint64_t SH_FLD_CM_CFG = 5303; // 6 -static const uint64_t SH_FLD_CM_CFG_LEN = 5304; // 6 -static const uint64_t SH_FLD_CM_CNTL = 5305; // 120 -static const uint64_t SH_FLD_CM_CNTL_LEN = 5306; // 120 -static const uint64_t SH_FLD_CM_OFFSET_VAL = 5307; // 6 -static const uint64_t SH_FLD_CM_OFFSET_VAL_LEN = 5308; // 6 -static const uint64_t SH_FLD_CM_TIMEOUT = 5309; // 6 -static const uint64_t SH_FLD_CM_TIMEOUT_LEN = 5310; // 6 -static const uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE = 5311; // 1 -static const uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE_LEN = 5312; // 1 -static const uint64_t SH_FLD_CNT0 = 5313; // 2 -static const uint64_t SH_FLD_CNT0_BIT_PAIR_SEL = 5314; // 1 -static const uint64_t SH_FLD_CNT0_BIT_PAIR_SEL_LEN = 5315; // 1 -static const uint64_t SH_FLD_CNT0_ENABLE = 5316; // 1 -static const uint64_t SH_FLD_CNT0_EVENT_SEL = 5317; // 1 -static const uint64_t SH_FLD_CNT0_EVENT_SEL_LEN = 5318; // 1 -static const uint64_t SH_FLD_CNT0_LEN = 5319; // 2 -static const uint64_t SH_FLD_CNT0_MUX_SEL = 5320; // 2 -static const uint64_t SH_FLD_CNT0_MUX_SEL_LEN = 5321; // 2 -static const uint64_t SH_FLD_CNT0_PAIR_OP = 5322; // 2 -static const uint64_t SH_FLD_CNT0_PAIR_OP_LEN = 5323; // 2 -static const uint64_t SH_FLD_CNT0_POSEDGE_SEL = 5324; // 1 -static const uint64_t SH_FLD_CNT1 = 5325; // 2 -static const uint64_t SH_FLD_CNT1_BIT_PAIR_SEL = 5326; // 1 -static const uint64_t SH_FLD_CNT1_BIT_PAIR_SEL_LEN = 5327; // 1 -static const uint64_t SH_FLD_CNT1_ENABLE = 5328; // 1 -static const uint64_t SH_FLD_CNT1_EVENT_SEL = 5329; // 1 -static const uint64_t SH_FLD_CNT1_EVENT_SEL_LEN = 5330; // 1 -static const uint64_t SH_FLD_CNT1_LEN = 5331; // 2 -static const uint64_t SH_FLD_CNT1_MUX_SEL = 5332; // 2 -static const uint64_t SH_FLD_CNT1_MUX_SEL_LEN = 5333; // 2 -static const uint64_t SH_FLD_CNT1_PAIR_OP = 5334; // 2 -static const uint64_t SH_FLD_CNT1_PAIR_OP_LEN = 5335; // 2 -static const uint64_t SH_FLD_CNT1_POSEDGE_SEL = 5336; // 1 -static const uint64_t SH_FLD_CNT2 = 5337; // 2 -static const uint64_t SH_FLD_CNT2_BIT_PAIR_SEL = 5338; // 1 -static const uint64_t SH_FLD_CNT2_BIT_PAIR_SEL_LEN = 5339; // 1 -static const uint64_t SH_FLD_CNT2_ENABLE = 5340; // 1 -static const uint64_t SH_FLD_CNT2_EVENT_SEL = 5341; // 1 -static const uint64_t SH_FLD_CNT2_EVENT_SEL_LEN = 5342; // 1 -static const uint64_t SH_FLD_CNT2_LEN = 5343; // 2 -static const uint64_t SH_FLD_CNT2_MUX_SEL = 5344; // 2 -static const uint64_t SH_FLD_CNT2_MUX_SEL_LEN = 5345; // 2 -static const uint64_t SH_FLD_CNT2_PAIR_OP = 5346; // 2 -static const uint64_t SH_FLD_CNT2_PAIR_OP_LEN = 5347; // 2 -static const uint64_t SH_FLD_CNT2_POSEDGE_SEL = 5348; // 1 -static const uint64_t SH_FLD_CNT3 = 5349; // 2 -static const uint64_t SH_FLD_CNT3_BIT_PAIR_SEL = 5350; // 1 -static const uint64_t SH_FLD_CNT3_BIT_PAIR_SEL_LEN = 5351; // 1 -static const uint64_t SH_FLD_CNT3_ENABLE = 5352; // 1 -static const uint64_t SH_FLD_CNT3_EVENT_SEL = 5353; // 1 -static const uint64_t SH_FLD_CNT3_EVENT_SEL_LEN = 5354; // 1 -static const uint64_t SH_FLD_CNT3_LEN = 5355; // 2 -static const uint64_t SH_FLD_CNT3_MUX_SEL = 5356; // 2 -static const uint64_t SH_FLD_CNT3_MUX_SEL_LEN = 5357; // 2 -static const uint64_t SH_FLD_CNT3_PAIR_OP = 5358; // 2 -static const uint64_t SH_FLD_CNT3_PAIR_OP_LEN = 5359; // 2 -static const uint64_t SH_FLD_CNT3_POSEDGE_SEL = 5360; // 1 -static const uint64_t SH_FLD_CNTL = 5361; // 8 -static const uint64_t SH_FLD_CNTLS_PREV_LDED_GCRMSG = 5362; // 4 -static const uint64_t SH_FLD_CNTL_LEN = 5363; // 8 -static const uint64_t SH_FLD_CNT_BROADCAST = 5364; // 1 -static const uint64_t SH_FLD_CNT_BROADCAST_LEN = 5365; // 1 -static const uint64_t SH_FLD_CNT_CI_STORE_REPLAY = 5366; // 1 -static const uint64_t SH_FLD_CNT_CI_STORE_REPLAY_LEN = 5367; // 1 -static const uint64_t SH_FLD_CNT_DEM_CACHE_HIT = 5368; // 1 -static const uint64_t SH_FLD_CNT_DEM_CACHE_HIT_LEN = 5369; // 1 -static const uint64_t SH_FLD_CNT_DMA_RD = 5370; // 6 -static const uint64_t SH_FLD_CNT_DMA_RD_LEN = 5371; // 6 -static const uint64_t SH_FLD_CNT_DMA_WR = 5372; // 6 -static const uint64_t SH_FLD_CNT_DMA_WR_LEN = 5373; // 6 -static const uint64_t SH_FLD_CNT_EOI_CACHE_HIT = 5374; // 1 -static const uint64_t SH_FLD_CNT_EOI_CACHE_HIT_LEN = 5375; // 1 -static const uint64_t SH_FLD_CNT_EOI_RESP_REPLAY = 5376; // 2 -static const uint64_t SH_FLD_CNT_EOI_RESP_REPLAY_LEN = 5377; // 2 -static const uint64_t SH_FLD_CNT_EQC_COMMAND = 5378; // 1 -static const uint64_t SH_FLD_CNT_EQC_COMMAND_LEN = 5379; // 1 -static const uint64_t SH_FLD_CNT_EQD_FETCH = 5380; // 1 -static const uint64_t SH_FLD_CNT_EQD_FETCH_LEN = 5381; // 1 -static const uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY = 5382; // 1 -static const uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY_LEN = 5383; // 1 -static const uint64_t SH_FLD_CNT_EQP = 5384; // 1 -static const uint64_t SH_FLD_CNT_EQP_LEN = 5385; // 1 -static const uint64_t SH_FLD_CNT_EQP_REPLAY = 5386; // 1 -static const uint64_t SH_FLD_CNT_EQP_REPLAY_LEN = 5387; // 1 -static const uint64_t SH_FLD_CNT_EQ_FWD = 5388; // 1 -static const uint64_t SH_FLD_CNT_EQ_FWD_LEN = 5389; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC = 5390; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 5391; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC = 5392; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 5393; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD = 5394; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN = 5395; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI = 5396; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN = 5397; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS = 5398; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 5399; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT = 5400; // 1 -static const uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN = 5401; // 1 -static const uint64_t SH_FLD_CNT_ESCALATE = 5402; // 1 -static const uint64_t SH_FLD_CNT_ESCALATE_LEN = 5403; // 1 -static const uint64_t SH_FLD_CNT_FIFO_FULL = 5404; // 6 -static const uint64_t SH_FLD_CNT_FIFO_FULL_LEN = 5405; // 6 -static const uint64_t SH_FLD_CNT_GROUP = 5406; // 1 -static const uint64_t SH_FLD_CNT_GROUP_LEN = 5407; // 1 -static const uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT = 5408; // 1 -static const uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN = 5409; // 1 -static const uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE = 5410; // 1 -static const uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN = 5411; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE = 5412; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN = 5413; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC = 5414; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 5415; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE = 5416; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN = 5417; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC = 5418; // 1 -static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 5419; // 1 -static const uint64_t SH_FLD_CNT_ISB_FETCH = 5420; // 1 -static const uint64_t SH_FLD_CNT_ISB_FETCH_LEN = 5421; // 1 -static const uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY = 5422; // 1 -static const uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY_LEN = 5423; // 1 -static const uint64_t SH_FLD_CNT_ISB_WRITE = 5424; // 1 -static const uint64_t SH_FLD_CNT_ISB_WRITE_LEN = 5425; // 1 -static const uint64_t SH_FLD_CNT_IVC_DEMAND = 5426; // 1 -static const uint64_t SH_FLD_CNT_IVC_DEMAND_LEN = 5427; // 1 -static const uint64_t SH_FLD_CNT_IVC_PRF = 5428; // 1 -static const uint64_t SH_FLD_CNT_IVC_PRF_LEN = 5429; // 1 -static const uint64_t SH_FLD_CNT_IVC_RESP_REPLAY = 5430; // 1 -static const uint64_t SH_FLD_CNT_IVC_RESP_REPLAY_LEN = 5431; // 1 -static const uint64_t SH_FLD_CNT_IVE_FETCH = 5432; // 1 -static const uint64_t SH_FLD_CNT_IVE_FETCH_LEN = 5433; // 1 -static const uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY = 5434; // 1 -static const uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY_LEN = 5435; // 1 -static const uint64_t SH_FLD_CNT_IVVC_RESP = 5436; // 1 -static const uint64_t SH_FLD_CNT_IVVC_RESP_LEN = 5437; // 1 -static const uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY = 5438; // 1 -static const uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN = 5439; // 1 -static const uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF = 5440; // 1 -static const uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF_LEN = 5441; // 1 -static const uint64_t SH_FLD_CNT_LCL_REDIST = 5442; // 1 -static const uint64_t SH_FLD_CNT_LCL_REDIST_LEN = 5443; // 1 -static const uint64_t SH_FLD_CNT_LD_CACHE_HIT = 5444; // 1 -static const uint64_t SH_FLD_CNT_LD_CACHE_HIT_LEN = 5445; // 1 -static const uint64_t SH_FLD_CNT_LD_REQ_REPLAY = 5446; // 1 -static const uint64_t SH_FLD_CNT_LD_REQ_REPLAY_LEN = 5447; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_ESCALATE = 5448; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_ESCALATE_LEN = 5449; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT = 5450; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN = 5451; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY = 5452; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN = 5453; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN = 5454; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN = 5455; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY = 5456; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN = 5457; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_SBC_UPD = 5458; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_SBC_UPD_LEN = 5459; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY = 5460; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN = 5461; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_VPC_UPD = 5462; // 1 -static const uint64_t SH_FLD_CNT_LOCAL_VPC_UPD_LEN = 5463; // 1 -static const uint64_t SH_FLD_CNT_LS = 5464; // 1 -static const uint64_t SH_FLD_CNT_LS_LEN = 5465; // 1 -static const uint64_t SH_FLD_CNT_NEW_CMD_STALLED = 5466; // 1 -static const uint64_t SH_FLD_CNT_NEW_CMD_STALLED_LEN = 5467; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_EOI = 5468; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_LEN = 5469; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED = 5470; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 5471; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED = 5472; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN = 5473; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_LOAD = 5474; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_LOAD_LEN = 5475; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD = 5476; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN = 5477; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD = 5478; // 1 -static const uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN = 5479; // 1 -static const uint64_t SH_FLD_CNT_OTHER_CACHE_HIT = 5480; // 1 -static const uint64_t SH_FLD_CNT_OTHER_CACHE_HIT_LEN = 5481; // 1 -static const uint64_t SH_FLD_CNT_PRF_CACHE_HIT = 5482; // 2 -static const uint64_t SH_FLD_CNT_PRF_CACHE_HIT_LEN = 5483; // 2 -static const uint64_t SH_FLD_CNT_R0 = 5484; // 6 -static const uint64_t SH_FLD_CNT_R0_LEN = 5485; // 6 -static const uint64_t SH_FLD_CNT_R10R = 5486; // 3 -static const uint64_t SH_FLD_CNT_R10R_LEN = 5487; // 3 -static const uint64_t SH_FLD_CNT_R10W = 5488; // 3 -static const uint64_t SH_FLD_CNT_R10W_LEN = 5489; // 3 -static const uint64_t SH_FLD_CNT_R1R = 5490; // 6 -static const uint64_t SH_FLD_CNT_R1R_LEN = 5491; // 6 -static const uint64_t SH_FLD_CNT_R1W = 5492; // 6 -static const uint64_t SH_FLD_CNT_R1W_LEN = 5493; // 6 -static const uint64_t SH_FLD_CNT_R2 = 5494; // 6 -static const uint64_t SH_FLD_CNT_R2_LEN = 5495; // 6 -static const uint64_t SH_FLD_CNT_R3 = 5496; // 6 -static const uint64_t SH_FLD_CNT_R3_LEN = 5497; // 6 -static const uint64_t SH_FLD_CNT_R4 = 5498; // 3 -static const uint64_t SH_FLD_CNT_R4R = 5499; // 3 -static const uint64_t SH_FLD_CNT_R4R_LEN = 5500; // 3 -static const uint64_t SH_FLD_CNT_R4W = 5501; // 3 -static const uint64_t SH_FLD_CNT_R4W_LEN = 5502; // 3 -static const uint64_t SH_FLD_CNT_R4_LEN = 5503; // 3 -static const uint64_t SH_FLD_CNT_R5 = 5504; // 3 -static const uint64_t SH_FLD_CNT_R5R = 5505; // 3 -static const uint64_t SH_FLD_CNT_R5R_LEN = 5506; // 3 -static const uint64_t SH_FLD_CNT_R5W = 5507; // 3 -static const uint64_t SH_FLD_CNT_R5W_LEN = 5508; // 3 -static const uint64_t SH_FLD_CNT_R5_LEN = 5509; // 3 -static const uint64_t SH_FLD_CNT_R6 = 5510; // 6 -static const uint64_t SH_FLD_CNT_R6_LEN = 5511; // 6 -static const uint64_t SH_FLD_CNT_R7 = 5512; // 3 -static const uint64_t SH_FLD_CNT_R7EQP = 5513; // 3 -static const uint64_t SH_FLD_CNT_R7EQP_LEN = 5514; // 3 -static const uint64_t SH_FLD_CNT_R7INT = 5515; // 3 -static const uint64_t SH_FLD_CNT_R7INT_LEN = 5516; // 3 -static const uint64_t SH_FLD_CNT_R7RSP = 5517; // 3 -static const uint64_t SH_FLD_CNT_R7RSP_LEN = 5518; // 3 -static const uint64_t SH_FLD_CNT_R7_LEN = 5519; // 3 -static const uint64_t SH_FLD_CNT_R8 = 5520; // 6 -static const uint64_t SH_FLD_CNT_R8_LEN = 5521; // 6 -static const uint64_t SH_FLD_CNT_R9 = 5522; // 6 -static const uint64_t SH_FLD_CNT_R9_LEN = 5523; // 6 -static const uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY = 5524; // 1 -static const uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 5525; // 1 -static const uint64_t SH_FLD_CNT_REMOTE_SBC_UPD = 5526; // 1 -static const uint64_t SH_FLD_CNT_REMOTE_SBC_UPD_LEN = 5527; // 1 -static const uint64_t SH_FLD_CNT_REMOTE_VPC_UPD = 5528; // 1 -static const uint64_t SH_FLD_CNT_REMOTE_VPC_UPD_LEN = 5529; // 1 -static const uint64_t SH_FLD_CNT_REPLAY = 5530; // 1 -static const uint64_t SH_FLD_CNT_REPLAY_LEN = 5531; // 1 -static const uint64_t SH_FLD_CNT_RETRY = 5532; // 3 -static const uint64_t SH_FLD_CNT_RETRY_LEN = 5533; // 3 -static const uint64_t SH_FLD_CNT_RMT_PULL_1STGRP = 5534; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_1STGRP_LEN = 5535; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_1STVP = 5536; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_1STVP_LEN = 5537; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_GRP = 5538; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_GRP_LEN = 5539; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_VP = 5540; // 1 -static const uint64_t SH_FLD_CNT_RMT_PULL_VP_LEN = 5541; // 1 -static const uint64_t SH_FLD_CNT_RMT_PUSH = 5542; // 1 -static const uint64_t SH_FLD_CNT_RMT_PUSH_LEN = 5543; // 1 -static const uint64_t SH_FLD_CNT_RMT_PUSH_VC = 5544; // 1 -static const uint64_t SH_FLD_CNT_RMT_PUSH_VC_LEN = 5545; // 1 -static const uint64_t SH_FLD_CNT_RSP_ATX_REPLAY = 5546; // 1 -static const uint64_t SH_FLD_CNT_RSP_ATX_REPLAY_LEN = 5547; // 1 -static const uint64_t SH_FLD_CNT_RSP_LCL_TCTXT = 5548; // 1 -static const uint64_t SH_FLD_CNT_RSP_LCL_TCTXT_LEN = 5549; // 1 -static const uint64_t SH_FLD_CNT_RSP_LCL_VC = 5550; // 1 -static const uint64_t SH_FLD_CNT_RSP_LCL_VC_LEN = 5551; // 1 -static const uint64_t SH_FLD_CNT_RSP_RMT = 5552; // 1 -static const uint64_t SH_FLD_CNT_RSP_RMT_LEN = 5553; // 1 -static const uint64_t SH_FLD_CNT_RSP_RMT_VC = 5554; // 1 -static const uint64_t SH_FLD_CNT_RSP_RMT_VC_LEN = 5555; // 1 -static const uint64_t SH_FLD_CNT_RSP_SW_LD = 5556; // 1 -static const uint64_t SH_FLD_CNT_RSP_SW_LD_LEN = 5557; // 1 -static const uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY = 5558; // 1 -static const uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN = 5559; // 1 -static const uint64_t SH_FLD_CNT_SAME_VPD_REPLAY = 5560; // 1 -static const uint64_t SH_FLD_CNT_SAME_VPD_REPLAY_LEN = 5561; // 1 -static const uint64_t SH_FLD_CNT_SBC_LOOKUP = 5562; // 1 -static const uint64_t SH_FLD_CNT_SBC_LOOKUP_LEN = 5563; // 1 -static const uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY = 5564; // 1 -static const uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN = 5565; // 1 -static const uint64_t SH_FLD_CNT_SINGLE_LANE_RECAL = 5566; // 6 -static const uint64_t SH_FLD_CNT_SPEC_EOI = 5567; // 1 -static const uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT = 5568; // 1 -static const uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN = 5569; // 1 -static const uint64_t SH_FLD_CNT_SPEC_EOI_LEN = 5570; // 1 -static const uint64_t SH_FLD_CNT_ST_LCL_REPLAY = 5571; // 1 -static const uint64_t SH_FLD_CNT_ST_LCL_REPLAY_LEN = 5572; // 1 -static const uint64_t SH_FLD_CNT_ST_RMT_REPLAY = 5573; // 1 -static const uint64_t SH_FLD_CNT_ST_RMT_REPLAY_LEN = 5574; // 1 -static const uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY = 5575; // 1 -static const uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN = 5576; // 1 -static const uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES = 5577; // 3 -static const uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES_LEN = 5578; // 3 -static const uint64_t SH_FLD_CNT_TRIG_DROPPED = 5579; // 6 -static const uint64_t SH_FLD_CNT_TRIG_DROPPED_LEN = 5580; // 6 -static const uint64_t SH_FLD_CNT_TRIG_FROM_AIB = 5581; // 6 -static const uint64_t SH_FLD_CNT_TRIG_FROM_AIB_LEN = 5582; // 6 -static const uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC = 5583; // 6 -static const uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN = 5584; // 6 -static const uint64_t SH_FLD_CNT_USE_L2_DIVIDER_EN = 5585; // 12 -static const uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE = 5586; // 2 -static const uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN = 5587; // 2 -static const uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE = 5588; // 2 -static const uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN = 5589; // 2 -static const uint64_t SH_FLD_CNT_VICTIM_IS_LRU = 5590; // 4 -static const uint64_t SH_FLD_CNT_VICTIM_IS_LRU_LEN = 5591; // 4 -static const uint64_t SH_FLD_CNT_VP = 5592; // 1 -static const uint64_t SH_FLD_CNT_VPD_FETCH = 5593; // 1 -static const uint64_t SH_FLD_CNT_VPD_FETCH_LEN = 5594; // 1 -static const uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY = 5595; // 1 -static const uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY_LEN = 5596; // 1 -static const uint64_t SH_FLD_CNT_VPD_WB = 5597; // 1 -static const uint64_t SH_FLD_CNT_VPD_WB_LEN = 5598; // 1 -static const uint64_t SH_FLD_CNT_VP_LEN = 5599; // 1 -static const uint64_t SH_FLD_CNT_VRQ_CACHE_HIT = 5600; // 1 -static const uint64_t SH_FLD_CNT_VRQ_CACHE_HIT_LEN = 5601; // 1 -static const uint64_t SH_FLD_CNT_VRQ_PULL = 5602; // 1 -static const uint64_t SH_FLD_CNT_VRQ_PULL_LEN = 5603; // 1 -static const uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL = 5604; // 1 -static const uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN = 5605; // 1 -static const uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE = 5606; // 1 -static const uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN = 5607; // 1 -static const uint64_t SH_FLD_CNT_WAKEUP = 5608; // 1 -static const uint64_t SH_FLD_CNT_WAKEUP_LEN = 5609; // 1 -static const uint64_t SH_FLD_COARSE_CAL_STEP_SIZE = 5610; // 8 -static const uint64_t SH_FLD_COARSE_CAL_STEP_SIZE_LEN = 5611; // 8 -static const uint64_t SH_FLD_COARSE_DIR_ENABLE = 5612; // 2 -static const uint64_t SH_FLD_COARSE_DIR_SECTORS = 5613; // 2 -static const uint64_t SH_FLD_COARSE_RD = 5614; // 8 -static const uint64_t SH_FLD_COFSM_ADDR = 5615; // 12 -static const uint64_t SH_FLD_COHERENCY_ERROR = 5616; // 2 -static const uint64_t SH_FLD_COL4_BIT_MAP = 5617; // 8 -static const uint64_t SH_FLD_COL4_BIT_MAP_LEN = 5618; // 8 -static const uint64_t SH_FLD_COL5_BIT_MAP = 5619; // 8 -static const uint64_t SH_FLD_COL5_BIT_MAP_LEN = 5620; // 8 -static const uint64_t SH_FLD_COL6_BIT_MAP = 5621; // 8 -static const uint64_t SH_FLD_COL6_BIT_MAP_LEN = 5622; // 8 -static const uint64_t SH_FLD_COL7_BIT_MAP = 5623; // 8 -static const uint64_t SH_FLD_COL7_BIT_MAP_LEN = 5624; // 8 -static const uint64_t SH_FLD_COL8_BIT_MAP = 5625; // 8 -static const uint64_t SH_FLD_COL8_BIT_MAP_LEN = 5626; // 8 -static const uint64_t SH_FLD_COL9_BIT_MAP = 5627; // 8 -static const uint64_t SH_FLD_COL9_BIT_MAP_LEN = 5628; // 8 -static const uint64_t SH_FLD_COLLISION_MODES = 5629; // 4 -static const uint64_t SH_FLD_COLLISION_MODES_LEN = 5630; // 4 -static const uint64_t SH_FLD_COLLISON = 5631; // 1 -static const uint64_t SH_FLD_COMMAND_ADDRESS_TIMEOUT = 5632; // 2 -static const uint64_t SH_FLD_COMMAND_COMPLETE = 5633; // 1 -static const uint64_t SH_FLD_COMMAND_LIST_TIMEOUT = 5634; // 4 -static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE = 5635; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_EN = 5636; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_LEN = 5637; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SB_SPARE = 5638; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH = 5639; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH_LEN = 5640; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SW_RESCLK = 5641; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SW_RESCLK_LEN = 5642; // 6 -static const uint64_t SH_FLD_COMMON_CLK_SW_SPARE = 5643; // 6 -static const uint64_t SH_FLD_COMMON_FREEZE_MODE = 5644; // 7 -static const uint64_t SH_FLD_COMM_ACK = 5645; // 12 -static const uint64_t SH_FLD_COMM_NACK = 5646; // 12 -static const uint64_t SH_FLD_COMM_RECV = 5647; // 12 -static const uint64_t SH_FLD_COMM_RECVD = 5648; // 12 -static const uint64_t SH_FLD_COMM_RECV_LEN = 5649; // 12 -static const uint64_t SH_FLD_COMM_SEND = 5650; // 12 -static const uint64_t SH_FLD_COMM_SEND_ACK = 5651; // 12 -static const uint64_t SH_FLD_COMM_SEND_LEN = 5652; // 12 -static const uint64_t SH_FLD_COMM_SEND_NACK = 5653; // 12 -static const uint64_t SH_FLD_COMPLETE = 5654; // 8 -static const uint64_t SH_FLD_COMPLETE_LEN = 5655; // 8 -static const uint64_t SH_FLD_COMPLEX_FAULT = 5656; // 1 -static const uint64_t SH_FLD_COMPLEX_FAULT_MASK = 5657; // 1 -static const uint64_t SH_FLD_COMPLEX_NOTIFY = 5658; // 1 -static const uint64_t SH_FLD_COMPLEX_NOTIFY_MASK = 5659; // 1 -static const uint64_t SH_FLD_COMPRESSED_RSP_ENA = 5660; // 6 -static const uint64_t SH_FLD_COMP_CNT_LIMIT = 5661; // 24 -static const uint64_t SH_FLD_COMP_CNT_LIMIT_LEN = 5662; // 24 -static const uint64_t SH_FLD_COMP_MASK = 5663; // 4 -static const uint64_t SH_FLD_COMP_MASK_LEN = 5664; // 4 -static const uint64_t SH_FLD_COND1_SEL_A = 5665; // 86 -static const uint64_t SH_FLD_COND1_SEL_A_LEN = 5666; // 86 -static const uint64_t SH_FLD_COND1_SEL_B = 5667; // 86 -static const uint64_t SH_FLD_COND1_SEL_B_LEN = 5668; // 86 -static const uint64_t SH_FLD_COND2_SEL_A = 5669; // 86 -static const uint64_t SH_FLD_COND2_SEL_A_LEN = 5670; // 86 -static const uint64_t SH_FLD_COND2_SEL_B = 5671; // 86 -static const uint64_t SH_FLD_COND2_SEL_B_LEN = 5672; // 86 -static const uint64_t SH_FLD_COND3_ENABLE_RESET = 5673; // 86 -static const uint64_t SH_FLD_COND_STARTUP_TEST_FAIL = 5674; // 1 -static const uint64_t SH_FLD_CONFIG = 5675; // 1 -static const uint64_t SH_FLD_CONFIG1_RESERVED0 = 5676; // 3 -static const uint64_t SH_FLD_CONFIG1_RESERVED1 = 5677; // 15 -static const uint64_t SH_FLD_CONFIG1_RESERVED1_LEN = 5678; // 3 -static const uint64_t SH_FLD_CONFIG1_RESERVED2 = 5679; // 15 -static const uint64_t SH_FLD_CONFIG1_RESERVED2_LEN = 5680; // 3 -static const uint64_t SH_FLD_CONFIG_0 = 5681; // 5 -static const uint64_t SH_FLD_CONFIG_0_LEN = 5682; // 5 -static const uint64_t SH_FLD_CONFIG_1 = 5683; // 5 -static const uint64_t SH_FLD_CONFIG_1_LEN = 5684; // 5 -static const uint64_t SH_FLD_CONFIG_ADDR = 5685; // 48 -static const uint64_t SH_FLD_CONFIG_ADDR_LEN = 5686; // 48 -static const uint64_t SH_FLD_CONFIG_ADR_BAR_MODE = 5687; // 15 -static const uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY = 5688; // 12 -static const uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN = 5689; // 12 -static const uint64_t SH_FLD_CONFIG_BRAZOS = 5690; // 1 -static const uint64_t SH_FLD_CONFIG_BRAZOS_MODE = 5691; // 15 -static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 5692; // 12 -static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 5693; // 12 -static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 5694; // 12 -static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 5695; // 12 -static const uint64_t SH_FLD_CONFIG_CHIP = 5696; // 48 -static const uint64_t SH_FLD_CONFIG_CHIP_LEN = 5697; // 48 -static const uint64_t SH_FLD_CONFIG_DCACHE_MODE = 5698; // 12 -static const uint64_t SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL = 5699; // 12 -static const uint64_t SH_FLD_CONFIG_DISABLE_G = 5700; // 12 -static const uint64_t SH_FLD_CONFIG_DISABLE_INJECT = 5701; // 12 -static const uint64_t SH_FLD_CONFIG_DISABLE_LN = 5702; // 12 -static const uint64_t SH_FLD_CONFIG_DISABLE_NN_RN = 5703; // 12 -static const uint64_t SH_FLD_CONFIG_DISABLE_PBM_ECC_COR = 5704; // 3 -static const uint64_t SH_FLD_CONFIG_DISABLE_VG_NOT_SYS = 5705; // 12 -static const uint64_t SH_FLD_CONFIG_ENABLE = 5706; // 48 -static const uint64_t SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC = 5707; // 12 -static const uint64_t SH_FLD_CONFIG_ENABLE_PBUS = 5708; // 12 -static const uint64_t SH_FLD_CONFIG_ENABLE_SNARF_CPM = 5709; // 12 -static const uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT = 5710; // 12 -static const uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN = 5711; // 12 -static const uint64_t SH_FLD_CONFIG_EVAPORATE_BY_LCO = 5712; // 12 -static const uint64_t SH_FLD_CONFIG_FORBID_MMIO_ATOMIC = 5713; // 12 -static const uint64_t SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 = 5714; // 12 -static const uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY = 5715; // 3 -static const uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN = 5716; // 3 -static const uint64_t SH_FLD_CONFIG_GPU0_ADDR = 5717; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_ADDR_LEN = 5718; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_CHIP = 5719; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_CHIP_LEN = 5720; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_ENABLE = 5721; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_GRANULE = 5722; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_GROUP = 5723; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_GROUP_LEN = 5724; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE = 5725; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE_LEN = 5726; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_MODE = 5727; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_MODE_LEN = 5728; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_RESERVED = 5729; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_SIZE = 5730; // 12 -static const uint64_t SH_FLD_CONFIG_GPU0_SIZE_LEN = 5731; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_ADDR = 5732; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_ADDR_LEN = 5733; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_CHIP = 5734; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_CHIP_LEN = 5735; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_ENABLE = 5736; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_GRANULE = 5737; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_GROUP = 5738; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_GROUP_LEN = 5739; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE = 5740; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE_LEN = 5741; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_MODE = 5742; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_MODE_LEN = 5743; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_RESERVED = 5744; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_SIZE = 5745; // 12 -static const uint64_t SH_FLD_CONFIG_GPU1_SIZE_LEN = 5746; // 12 -static const uint64_t SH_FLD_CONFIG_GROUP = 5747; // 48 -static const uint64_t SH_FLD_CONFIG_GROUP_LEN = 5748; // 48 -static const uint64_t SH_FLD_CONFIG_INC_PRI_MASK = 5749; // 12 -static const uint64_t SH_FLD_CONFIG_INC_PRI_MASK_LEN = 5750; // 12 -static const uint64_t SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 = 5751; // 3 -static const uint64_t SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 = 5752; // 3 -static const uint64_t SH_FLD_CONFIG_LEN = 5753; // 1 -static const uint64_t SH_FLD_CONFIG_MACH_CORRENAB = 5754; // 12 -static const uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE1 = 5755; // 12 -static const uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE2 = 5756; // 12 -static const uint64_t SH_FLD_CONFIG_MAX_MACHINES = 5757; // 12 -static const uint64_t SH_FLD_CONFIG_MAX_MACHINES_LEN = 5758; // 12 -static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR = 5759; // 12 -static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG = 5760; // 12 -static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR = 5761; // 12 -static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE = 5762; // 12 -static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA = 5763; // 12 -static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ = 5764; // 12 -static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_WRP = 5765; // 12 -static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_B = 5766; // 12 -static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_C = 5767; // 12 -static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM = 5768; // 12 -static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 5769; // 12 -static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_A = 5770; // 12 -static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_B = 5771; // 12 -static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_C = 5772; // 12 -static const uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ = 5773; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 5774; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 5775; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL = 5776; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN = 5777; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH1 = 5778; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH1_LEN = 5779; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH2 = 5780; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH2_LEN = 5781; // 3 -static const uint64_t SH_FLD_CONFIG_MRBGP_TRACK_ALL = 5782; // 12 -static const uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ = 5783; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 5784; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 5785; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL = 5786; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN = 5787; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH1 = 5788; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH1_LEN = 5789; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH2 = 5790; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH2_LEN = 5791; // 3 -static const uint64_t SH_FLD_CONFIG_MRBSP_TRACK_ALL = 5792; // 12 -static const uint64_t SH_FLD_CONFIG_OPT_SNOOP_CP = 5793; // 12 -static const uint64_t SH_FLD_CONFIG_P9P9_MODE = 5794; // 12 -static const uint64_t SH_FLD_CONFIG_PARITY = 5795; // 43 -static const uint64_t SH_FLD_CONFIG_PCKT_BLK_PRB = 5796; // 12 -static const uint64_t SH_FLD_CONFIG_PRB0 = 5797; // 24 -static const uint64_t SH_FLD_CONFIG_PRB0_LEN = 5798; // 24 -static const uint64_t SH_FLD_CONFIG_PRB1 = 5799; // 24 -static const uint64_t SH_FLD_CONFIG_PRB1_LEN = 5800; // 24 -static const uint64_t SH_FLD_CONFIG_PREALLOC2_PRB0 = 5801; // 12 -static const uint64_t SH_FLD_CONFIG_PREALLOC2_PRB1 = 5802; // 12 -static const uint64_t SH_FLD_CONFIG_PREALLOC2_REQ0 = 5803; // 12 -static const uint64_t SH_FLD_CONFIG_PREALLOC2_REQ1 = 5804; // 12 -static const uint64_t SH_FLD_CONFIG_PREALLOC2_XATS = 5805; // 12 -static const uint64_t SH_FLD_CONFIG_PWR0 = 5806; // 24 -static const uint64_t SH_FLD_CONFIG_PWR0_LEN = 5807; // 24 -static const uint64_t SH_FLD_CONFIG_PWR1 = 5808; // 24 -static const uint64_t SH_FLD_CONFIG_PWR1_LEN = 5809; // 24 -static const uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK = 5810; // 12 -static const uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 5811; // 12 -static const uint64_t SH_FLD_CONFIG_REQ0 = 5812; // 24 -static const uint64_t SH_FLD_CONFIG_REQ0_LEN = 5813; // 24 -static const uint64_t SH_FLD_CONFIG_REQ1 = 5814; // 24 -static const uint64_t SH_FLD_CONFIG_REQ1_LEN = 5815; // 24 -static const uint64_t SH_FLD_CONFIG_RESERVED4 = 5816; // 12 -static const uint64_t SH_FLD_CONFIG_RSI_CORRENAB = 5817; // 12 -static const uint64_t SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 5818; // 12 -static const uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE1 = 5819; // 12 -static const uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE2 = 5820; // 12 -static const uint64_t SH_FLD_CONFIG_RXO_CORRENAB = 5821; // 12 -static const uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE1 = 5822; // 12 -static const uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE2 = 5823; // 12 -static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_DATA = 5824; // 12 -static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN = 5825; // 12 -static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_POLL = 5826; // 12 -static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN = 5827; // 12 -static const uint64_t SH_FLD_CONFIG_SKIP_G = 5828; // 12 -static const uint64_t SH_FLD_CONFIG_SYNC_WAIT = 5829; // 1 -static const uint64_t SH_FLD_CONFIG_SYNC_WAIT_LEN = 5830; // 1 -static const uint64_t SH_FLD_CONFIG_XATS = 5831; // 24 -static const uint64_t SH_FLD_CONFIG_XATS_LEN = 5832; // 24 -static const uint64_t SH_FLD_CONFIRMED = 5833; // 64 -static const uint64_t SH_FLD_CONFLICT = 5834; // 2 -static const uint64_t SH_FLD_CONG = 5835; // 1 -static const uint64_t SH_FLD_CONG_LEN = 5836; // 1 -static const uint64_t SH_FLD_CONSEQ_PASS = 5837; // 8 -static const uint64_t SH_FLD_CONSEQ_PASS_LEN = 5838; // 8 -static const uint64_t SH_FLD_CONSUMED_BUF_COUNT = 5839; // 1 -static const uint64_t SH_FLD_CONSUMED_BUF_COUNT_LEN = 5840; // 1 -static const uint64_t SH_FLD_CONTENT = 5841; // 3 -static const uint64_t SH_FLD_CONTENT_LEN = 5842; // 3 -static const uint64_t SH_FLD_CONTINUOUS = 5843; // 4 -static const uint64_t SH_FLD_CONTROL = 5844; // 15 -static const uint64_t SH_FLD_CONTROL_ERR = 5845; // 12 -static const uint64_t SH_FLD_CONTROL_LEN = 5846; // 15 -static const uint64_t SH_FLD_CONTROL_N = 5847; // 2 -static const uint64_t SH_FLD_CONVERGED_END_COUNT = 5848; // 6 -static const uint64_t SH_FLD_CONVERGED_END_COUNT_LEN = 5849; // 6 -static const uint64_t SH_FLD_COPY_CKE_TO_SPARE_CKE = 5850; // 2 -static const uint64_t SH_FLD_COPY_LENGTH = 5851; // 2 -static const uint64_t SH_FLD_COPY_LENGTH_LEN = 5852; // 2 -static const uint64_t SH_FLD_CORE0_REQ_ACTIVE = 5853; // 12 -static const uint64_t SH_FLD_CORE1_REQ_ACTIVE = 5854; // 12 -static const uint64_t SH_FLD_COREID = 5855; // 1 -static const uint64_t SH_FLD_COREID_LEN = 5856; // 1 -static const uint64_t SH_FLD_CORES_ENABLED_0_23 = 5857; // 1 -static const uint64_t SH_FLD_CORES_ENABLED_0_23_LEN = 5858; // 1 -static const uint64_t SH_FLD_CORE_CHECKSTOP = 5859; // 12 -static const uint64_t SH_FLD_CORE_CONFIG = 5860; // 2 -static const uint64_t SH_FLD_CORE_CONFIG_LEN = 5861; // 2 -static const uint64_t SH_FLD_CORE_DROPOUT_ENABLE = 5862; // 12 -static const uint64_t SH_FLD_CORE_DROPOUT_ENABLE_LEN = 5863; // 12 -static const uint64_t SH_FLD_CORE_EXT_INTR = 5864; // 1 -static const uint64_t SH_FLD_CORE_LIMIT = 5865; // 24 -static const uint64_t SH_FLD_CORE_LIMIT_LEN = 5866; // 24 -static const uint64_t SH_FLD_CORE_OR_SNP_REQ_ACTIVE = 5867; // 12 -static const uint64_t SH_FLD_CORE_RAS0_TRIG_SEL = 5868; // 43 -static const uint64_t SH_FLD_CORE_RAS0_TRIG_SEL_LEN = 5869; // 43 -static const uint64_t SH_FLD_CORE_RAS1_TRIG_SEL = 5870; // 43 -static const uint64_t SH_FLD_CORE_RAS1_TRIG_SEL_LEN = 5871; // 43 -static const uint64_t SH_FLD_CORE_RESET = 5872; // 1 -static const uint64_t SH_FLD_CORE_STEP = 5873; // 1 -static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_ENABLE = 5874; // 1 -static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE = 5875; // 1 -static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_TRIGGER = 5876; // 1 -static const uint64_t SH_FLD_CORR_DIS_BR = 5877; // 3 -static const uint64_t SH_FLD_CORR_DIS_IR = 5878; // 3 -static const uint64_t SH_FLD_CORR_DIS_OR = 5879; // 3 -static const uint64_t SH_FLD_CORR_DIS_PR = 5880; // 3 -static const uint64_t SH_FLD_CORR_DIS_PT = 5881; // 3 -static const uint64_t SH_FLD_CORR_ERR = 5882; // 1 -static const uint64_t SH_FLD_COUNT = 5883; // 44 -static const uint64_t SH_FLD_COUNTER = 5884; // 43 -static const uint64_t SH_FLD_COUNTER0 = 5885; // 16 -static const uint64_t SH_FLD_COUNTER0_LEN = 5886; // 16 -static const uint64_t SH_FLD_COUNTER1 = 5887; // 16 -static const uint64_t SH_FLD_COUNTER1_LEN = 5888; // 16 -static const uint64_t SH_FLD_COUNTER2 = 5889; // 16 -static const uint64_t SH_FLD_COUNTER2_LEN = 5890; // 16 -static const uint64_t SH_FLD_COUNTER3 = 5891; // 16 -static const uint64_t SH_FLD_COUNTER3_LEN = 5892; // 16 -static const uint64_t SH_FLD_COUNTERA_0 = 5893; // 2 -static const uint64_t SH_FLD_COUNTERA_0_LEN = 5894; // 2 -static const uint64_t SH_FLD_COUNTERA_1 = 5895; // 2 -static const uint64_t SH_FLD_COUNTERA_1_LEN = 5896; // 2 -static const uint64_t SH_FLD_COUNTERA_2 = 5897; // 2 -static const uint64_t SH_FLD_COUNTERA_2_LEN = 5898; // 2 -static const uint64_t SH_FLD_COUNTERA_3 = 5899; // 2 -static const uint64_t SH_FLD_COUNTERA_3_LEN = 5900; // 2 -static const uint64_t SH_FLD_COUNTERB_0 = 5901; // 2 -static const uint64_t SH_FLD_COUNTERB_0_LEN = 5902; // 2 -static const uint64_t SH_FLD_COUNTERB_1 = 5903; // 2 -static const uint64_t SH_FLD_COUNTERB_1_LEN = 5904; // 2 -static const uint64_t SH_FLD_COUNTERB_2 = 5905; // 2 -static const uint64_t SH_FLD_COUNTERB_2_LEN = 5906; // 2 -static const uint64_t SH_FLD_COUNTERB_3 = 5907; // 2 -static const uint64_t SH_FLD_COUNTERB_3_LEN = 5908; // 2 -static const uint64_t SH_FLD_COUNTER_LEN = 5909; // 43 -static const uint64_t SH_FLD_COUNTER_LOAD_FLAG = 5910; // 2 -static const uint64_t SH_FLD_COUNTER_LOAD_VALUE = 5911; // 2 -static const uint64_t SH_FLD_COUNTER_LOAD_VALUE_LEN = 5912; // 2 -static const uint64_t SH_FLD_COUNTER_VALUE = 5913; // 1 -static const uint64_t SH_FLD_COUNTER_VALUE_LEN = 5914; // 1 -static const uint64_t SH_FLD_COUNT_0_47 = 5915; // 7 -static const uint64_t SH_FLD_COUNT_0_47_LEN = 5916; // 7 -static const uint64_t SH_FLD_COUNT_47 = 5917; // 1 -static const uint64_t SH_FLD_COUNT_47_LEN = 5918; // 1 -static const uint64_t SH_FLD_COUNT_LEN = 5919; // 44 -static const uint64_t SH_FLD_COUNT_STATE_MASK = 5920; // 43 -static const uint64_t SH_FLD_COURSE_DIR_FLUSH_FAILED = 5921; // 2 -static const uint64_t SH_FLD_CO_CRESP_ACK_DEAD = 5922; // 12 -static const uint64_t SH_FLD_CO_MACHINE_HANG = 5923; // 12 -static const uint64_t SH_FLD_CO_PROT_ERR_CHK_DIS = 5924; // 1 -static const uint64_t SH_FLD_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR = 5925; // 12 -static const uint64_t SH_FLD_CO_SM_CTL_ERR_DET = 5926; // 1 -static const uint64_t SH_FLD_CO_TIMEOUT_CHK_DIS = 5927; // 1 -static const uint64_t SH_FLD_CO_TIMEOUT_ERR_DET = 5928; // 1 -static const uint64_t SH_FLD_CO_UNSOLICITED_CRESP = 5929; // 12 -static const uint64_t SH_FLD_CP = 5930; // 2 -static const uint64_t SH_FLD_CP0_LXSTOP_ERR_DET = 5931; // 1 -static const uint64_t SH_FLD_CP1_LXSTOP_ERR_DET = 5932; // 1 -static const uint64_t SH_FLD_CPG = 5933; // 8 -static const uint64_t SH_FLD_CPHA = 5934; // 1 -static const uint64_t SH_FLD_CPISEL = 5935; // 20 -static const uint64_t SH_FLD_CPISEL_LEN = 5936; // 20 -static const uint64_t SH_FLD_CPI_TYPE = 5937; // 12 -static const uint64_t SH_FLD_CPI_TYPE_LEN = 5938; // 12 -static const uint64_t SH_FLD_CPLITE = 5939; // 2 -static const uint64_t SH_FLD_CPLITE_LEN = 5940; // 2 -static const uint64_t SH_FLD_CPLTMASK0 = 5941; // 43 -static const uint64_t SH_FLD_CPLTMASK0_LEN = 5942; // 43 -static const uint64_t SH_FLD_CPLT_DCTRL = 5943; // 43 -static const uint64_t SH_FLD_CPLT_RCTRL = 5944; // 43 -static const uint64_t SH_FLD_CPM_CAL_SET = 5945; // 43 -static const uint64_t SH_FLD_CPOL = 5946; // 1 -static const uint64_t SH_FLD_CPS = 5947; // 1 -static const uint64_t SH_FLD_CPS_LEN = 5948; // 1 -static const uint64_t SH_FLD_CP_LEN = 5949; // 2 -static const uint64_t SH_FLD_CP_RETRY_THRESH = 5950; // 4 -static const uint64_t SH_FLD_CP_RETRY_THRESH_LEN = 5951; // 4 -static const uint64_t SH_FLD_CQ_CERR_BIT10 = 5952; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT11 = 5953; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT12 = 5954; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT13 = 5955; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT14 = 5956; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT15 = 5957; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT16 = 5958; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT17 = 5959; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT18 = 5960; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT19 = 5961; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT20 = 5962; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT21 = 5963; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT22 = 5964; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT23 = 5965; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT24 = 5966; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT25 = 5967; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT26 = 5968; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT27 = 5969; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT28 = 5970; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT29 = 5971; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT30 = 5972; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT31 = 5973; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT32 = 5974; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT33 = 5975; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT34 = 5976; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT35 = 5977; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT36 = 5978; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT37 = 5979; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT38 = 5980; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT39 = 5981; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT4 = 5982; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT5 = 5983; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT6 = 5984; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT7 = 5985; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT8 = 5986; // 1 -static const uint64_t SH_FLD_CQ_CERR_BIT9 = 5987; // 1 -static const uint64_t SH_FLD_CQ_CERR_RESET = 5988; // 1 -static const uint64_t SH_FLD_CQ_DRAIN_THRESHOLD = 5989; // 1 -static const uint64_t SH_FLD_CQ_DRAIN_THRESHOLD_LEN = 5990; // 1 -static const uint64_t SH_FLD_CQ_ECC_CE_ERROR = 5991; // 2 -static const uint64_t SH_FLD_CQ_ECC_SUE_ERROR = 5992; // 2 -static const uint64_t SH_FLD_CQ_ECC_UE_ERROR = 5993; // 2 -static const uint64_t SH_FLD_CQ_FILL_THRESHOLD = 5994; // 1 -static const uint64_t SH_FLD_CQ_FILL_THRESHOLD_LEN = 5995; // 1 -static const uint64_t SH_FLD_CQ_LFSR_RESEED_EN = 5996; // 1 -static const uint64_t SH_FLD_CQ_LOGIC_HW_ERROR = 5997; // 2 -static const uint64_t SH_FLD_CQ_PB_LINK_ABORT = 5998; // 2 -static const uint64_t SH_FLD_CQ_PB_MASTER_FSM_HANG = 5999; // 2 -static const uint64_t SH_FLD_CQ_PB_OB_CE_ERROR = 6000; // 2 -static const uint64_t SH_FLD_CQ_PB_OB_UE_ERROR = 6001; // 2 -static const uint64_t SH_FLD_CQ_PB_PARITY_ERROR = 6002; // 2 -static const uint64_t SH_FLD_CQ_PB_RD_ADDR_ERROR = 6003; // 2 -static const uint64_t SH_FLD_CQ_PB_RD_LINK_ERROR = 6004; // 2 -static const uint64_t SH_FLD_CQ_PB_WR_ADDR_ERROR = 6005; // 2 -static const uint64_t SH_FLD_CQ_PB_WR_LINK_ERROR = 6006; // 2 -static const uint64_t SH_FLD_CQ_READ_RTY_RATIO = 6007; // 1 -static const uint64_t SH_FLD_CQ_READ_RTY_RATIO_LEN = 6008; // 1 -static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI = 6009; // 1 -static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN = 6010; // 1 -static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO = 6011; // 1 -static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN = 6012; // 1 -static const uint64_t SH_FLD_CQ_TRACE_INT_DATA_HI = 6013; // 1 -static const uint64_t SH_FLD_CQ_TRACE_INT_DATA_LO = 6014; // 1 -static const uint64_t SH_FLD_CQ_TRACE_INT_TRIG_01 = 6015; // 1 -static const uint64_t SH_FLD_CQ_TRACE_INT_TRIG_23 = 6016; // 1 -static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01 = 6017; // 1 -static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN = 6018; // 1 -static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23 = 6019; // 1 -static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN = 6020; // 1 -static const uint64_t SH_FLD_CR0_ATAG_PERR = 6021; // 1 -static const uint64_t SH_FLD_CR0_TTAG_PERR = 6022; // 1 -static const uint64_t SH_FLD_CR1_ATAG_PERR = 6023; // 1 -static const uint64_t SH_FLD_CR1_TTAG_PERR = 6024; // 1 -static const uint64_t SH_FLD_CR2_ATAG_PERR = 6025; // 1 -static const uint64_t SH_FLD_CR2_TTAG_PERR = 6026; // 1 -static const uint64_t SH_FLD_CR3_ATAG_PERR = 6027; // 1 -static const uint64_t SH_FLD_CR3_TTAG_PERR = 6028; // 1 -static const uint64_t SH_FLD_CRB_ECC_SUE = 6029; // 1 -static const uint64_t SH_FLD_CRB_ECC_UE = 6030; // 1 -static const uint64_t SH_FLD_CRB_READS_ENBL = 6031; // 1 -static const uint64_t SH_FLD_CRB_READS_HALTED = 6032; // 1 -static const uint64_t SH_FLD_CRC_LANE_ID = 6033; // 5 -static const uint64_t SH_FLD_CRC_MODE = 6034; // 2 -static const uint64_t SH_FLD_CRD_INIT_REQUEST = 6035; // 1 -static const uint64_t SH_FLD_CRD_REQUEST = 6036; // 1 -static const uint64_t SH_FLD_CREDIT_CUR = 6037; // 36 -static const uint64_t SH_FLD_CREDIT_CUR_LEN = 6038; // 36 -static const uint64_t SH_FLD_CREDIT_MAX = 6039; // 36 -static const uint64_t SH_FLD_CREDIT_MAX_LEN = 6040; // 36 -static const uint64_t SH_FLD_CREDIT_RCV_CUR = 6041; // 12 -static const uint64_t SH_FLD_CREDIT_RCV_CUR_LEN = 6042; // 12 -static const uint64_t SH_FLD_CREDIT_RCV_UPD = 6043; // 12 -static const uint64_t SH_FLD_CREDIT_SEND = 6044; // 36 -static const uint64_t SH_FLD_CREDIT_SEND_LEN = 6045; // 36 -static const uint64_t SH_FLD_CREDIT_TIMEOUT_ERRHOLD = 6046; // 2 -static const uint64_t SH_FLD_CREDIT_UPD = 6047; // 36 -static const uint64_t SH_FLD_CREDIT_UPDATE_PENDING = 6048; // 6 -static const uint64_t SH_FLD_CREQ0 = 6049; // 12 -static const uint64_t SH_FLD_CREQ1 = 6050; // 12 -static const uint64_t SH_FLD_CREQ_AE_ALWAYS = 6051; // 6 -static const uint64_t SH_FLD_CREQ_BE_128 = 6052; // 6 -static const uint64_t SH_FLD_CRESP = 6053; // 24 -static const uint64_t SH_FLD_CRESP_0_4 = 6054; // 1 -static const uint64_t SH_FLD_CRESP_0_4_LEN = 6055; // 1 -static const uint64_t SH_FLD_CRESP_ADDR = 6056; // 2 -static const uint64_t SH_FLD_CRESP_ADDR_ERROR = 6057; // 2 -static const uint64_t SH_FLD_CRESP_ERROR = 6058; // 2 -static const uint64_t SH_FLD_CRESP_HANG = 6059; // 1 -static const uint64_t SH_FLD_CRESP_LEN = 6060; // 24 -static const uint64_t SH_FLD_CRITICAL_INTERRUPT = 6061; // 1 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_A = 6062; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN = 6063; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B = 6064; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN = 6065; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_A = 6066; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_A_LEN = 6067; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_B = 6068; // 86 -static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_B_LEN = 6069; // 86 -static const uint64_t SH_FLD_CR_ATAG_PAR = 6070; // 1 -static const uint64_t SH_FLD_CR_TTAG_PAR = 6071; // 1 -static const uint64_t SH_FLD_CS = 6072; // 6 -static const uint64_t SH_FLD_CS0_INIT_CAL_VALUE = 6073; // 8 -static const uint64_t SH_FLD_CS1_INIT_CAL_VALUE = 6074; // 8 -static const uint64_t SH_FLD_CS2_INIT_CAL_VALUE = 6075; // 8 -static const uint64_t SH_FLD_CS3_INIT_CAL_VALUE = 6076; // 8 -static const uint64_t SH_FLD_CS4_INIT_CAL_VALUE = 6077; // 8 -static const uint64_t SH_FLD_CS5_INIT_CAL_VALUE = 6078; // 8 -static const uint64_t SH_FLD_CS6_INIT_CAL_VALUE = 6079; // 8 -static const uint64_t SH_FLD_CS7_INIT_CAL_VALUE = 6080; // 8 -static const uint64_t SH_FLD_CSEL = 6081; // 10 -static const uint64_t SH_FLD_CSEL_LEN = 6082; // 10 -static const uint64_t SH_FLD_CS_LEN = 6083; // 6 -static const uint64_t SH_FLD_CTL = 6084; // 1 -static const uint64_t SH_FLD_CTLE_GAIN_MAX = 6085; // 6 -static const uint64_t SH_FLD_CTLE_GAIN_MAX_LEN = 6086; // 6 -static const uint64_t SH_FLD_CTLE_UPDATE_MODE = 6087; // 6 -static const uint64_t SH_FLD_CTLR_HP_THRESH = 6088; // 3 -static const uint64_t SH_FLD_CTLR_HP_THRESH_LEN = 6089; // 3 -static const uint64_t SH_FLD_CTLW_HP_THRESH = 6090; // 3 -static const uint64_t SH_FLD_CTLW_HP_THRESH_LEN = 6091; // 3 -static const uint64_t SH_FLD_CTL_ARRAY_CE = 6092; // 1 -static const uint64_t SH_FLD_CTL_ARRAY_UE = 6093; // 1 -static const uint64_t SH_FLD_CTL_CLKDIST_PDWN = 6094; // 6 -static const uint64_t SH_FLD_CTL_FWD_PROGRESS_ERR = 6095; // 1 -static const uint64_t SH_FLD_CTL_LEN = 6096; // 1 -static const uint64_t SH_FLD_CTL_LOGIC_ERR = 6097; // 1 -static const uint64_t SH_FLD_CTL_MMIO_ST_DATA_UE = 6098; // 1 -static const uint64_t SH_FLD_CTL_NVL_CFG_ERR = 6099; // 1 -static const uint64_t SH_FLD_CTL_NVL_FATAL_ERR = 6100; // 1 -static const uint64_t SH_FLD_CTL_PBUS_CONFIG_ERR = 6101; // 1 -static const uint64_t SH_FLD_CTL_PBUS_FATAL_ERR = 6102; // 1 -static const uint64_t SH_FLD_CTL_PBUS_PERR = 6103; // 1 -static const uint64_t SH_FLD_CTL_PBUS_RECOV_ERR = 6104; // 1 -static const uint64_t SH_FLD_CTL_PEF = 6105; // 1 -static const uint64_t SH_FLD_CTL_PEST_DIS = 6106; // 1 -static const uint64_t SH_FLD_CTL_RING_ERR = 6107; // 1 -static const uint64_t SH_FLD_CTL_RSVD_15 = 6108; // 1 -static const uint64_t SH_FLD_CTL_SM_0 = 6109; // 6 -static const uint64_t SH_FLD_CTL_SM_1 = 6110; // 6 -static const uint64_t SH_FLD_CTL_SM_2 = 6111; // 6 -static const uint64_t SH_FLD_CTL_SM_3 = 6112; // 6 -static const uint64_t SH_FLD_CTL_SM_4 = 6113; // 6 -static const uint64_t SH_FLD_CTL_SM_5 = 6114; // 6 -static const uint64_t SH_FLD_CTL_SM_6 = 6115; // 6 -static const uint64_t SH_FLD_CTL_SM_7 = 6116; // 6 -static const uint64_t SH_FLD_CTL_TICK = 6117; // 12 -static const uint64_t SH_FLD_CTL_TICK_LEN = 6118; // 12 -static const uint64_t SH_FLD_CTL_TRACE_EN = 6119; // 1 -static const uint64_t SH_FLD_CTL_TRACE_SEL = 6120; // 1 -static const uint64_t SH_FLD_CTR = 6121; // 8 -static const uint64_t SH_FLD_CTRLR_PERR_ESR = 6122; // 1 -static const uint64_t SH_FLD_CTRL_BUSY = 6123; // 1 -static const uint64_t SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC = 6124; // 43 -static const uint64_t SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC = 6125; // 43 -static const uint64_t SH_FLD_CTRL_CC_DCTEST_DC = 6126; // 43 -static const uint64_t SH_FLD_CTRL_CC_FLUSHMODE_INH_DC = 6127; // 43 -static const uint64_t SH_FLD_CTRL_CC_FORCE_ALIGN_DC = 6128; // 43 -static const uint64_t SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 6129; // 43 -static const uint64_t SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC = 6130; // 43 -static const uint64_t SH_FLD_CTRL_CC_OTP_PRGMODE_DC = 6131; // 43 -static const uint64_t SH_FLD_CTRL_CC_PIN_LBIST_DC = 6132; // 43 -static const uint64_t SH_FLD_CTRL_CC_SCAN_PROTECT_DC = 6133; // 43 -static const uint64_t SH_FLD_CTRL_CC_SDIS_DC_N = 6134; // 43 -static const uint64_t SH_FLD_CTRL_CC_SSS_CALIBRATE_DC = 6135; // 43 -static const uint64_t SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 6136; // 43 -static const uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC = 6137; // 43 -static const uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN = 6138; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC = 6139; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN = 6140; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC = 6141; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN = 6142; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC = 6143; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN = 6144; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC = 6145; // 43 -static const uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN = 6146; // 43 -static const uint64_t SH_FLD_CTRL_PARITY = 6147; // 43 -static const uint64_t SH_FLD_CTR_VREF_COUNTER_RESET_VAL = 6148; // 8 -static const uint64_t SH_FLD_CTR_VREF_COUNTER_RESET_VAL_LEN = 6149; // 8 -static const uint64_t SH_FLD_CT_COMPARE_VECTOR = 6150; // 2 -static const uint64_t SH_FLD_CT_COMPARE_VECTOR_LEN = 6151; // 2 -static const uint64_t SH_FLD_CURRENT_OPCG_MODE = 6152; // 43 -static const uint64_t SH_FLD_CURRENT_OPCG_MODE_LEN = 6153; // 43 -static const uint64_t SH_FLD_CUR_RD_ADDR = 6154; // 6 -static const uint64_t SH_FLD_CUR_RD_ADDR_LEN = 6155; // 6 -static const uint64_t SH_FLD_CUSTOM_INIT_WRITE = 6156; // 8 -static const uint64_t SH_FLD_CUSTOM_RD = 6157; // 8 -static const uint64_t SH_FLD_CUSTOM_WR = 6158; // 8 -static const uint64_t SH_FLD_CW_MIRROR = 6159; // 8 -static const uint64_t SH_FLD_CW_TYPE = 6160; // 12 -static const uint64_t SH_FLD_CW_TYPE_LEN = 6161; // 12 -static const uint64_t SH_FLD_CXACQPB_MUX_ECC_CE_ERRHOLD = 6162; // 2 -static const uint64_t SH_FLD_CXACQPB_MUX_ECC_UE_ERRHOLD = 6163; // 2 -static const uint64_t SH_FLD_CYCLECNT = 6164; // 3 -static const uint64_t SH_FLD_CYCLECNT_LEN = 6165; // 3 -static const uint64_t SH_FLD_CYCLES = 6166; // 12 -static const uint64_t SH_FLD_CYCLES_LEN = 6167; // 12 -static const uint64_t SH_FLD_CYCLE_COUNT = 6168; // 24 -static const uint64_t SH_FLD_CYCLE_COUNT_LEN = 6169; // 24 -static const uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA = 6170; // 2 -static const uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA_LEN = 6171; // 2 -static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 6172; // 4 -static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 6173; // 4 -static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 6174; // 4 -static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 6175; // 4 -static const uint64_t SH_FLD_DACTEST_HLMT = 6176; // 6 -static const uint64_t SH_FLD_DACTEST_HLMT_LEN = 6177; // 6 -static const uint64_t SH_FLD_DACTEST_LLMT = 6178; // 6 -static const uint64_t SH_FLD_DACTEST_LLMT_LEN = 6179; // 6 -static const uint64_t SH_FLD_DACTEST_RESET = 6180; // 6 -static const uint64_t SH_FLD_DACTEST_START = 6181; // 6 -static const uint64_t SH_FLD_DAC_BO_CFG = 6182; // 6 -static const uint64_t SH_FLD_DAC_BO_CFG_LEN = 6183; // 6 -static const uint64_t SH_FLD_DARN_ADDR_ERR = 6184; // 12 -static const uint64_t SH_FLD_DARN_DATA_TIMEOUT = 6185; // 12 -static const uint64_t SH_FLD_DARN_EN_ERR = 6186; // 12 -static const uint64_t SH_FLD_DAT0 = 6187; // 1 -static const uint64_t SH_FLD_DAT0_LEN = 6188; // 1 -static const uint64_t SH_FLD_DAT1 = 6189; // 1 -static const uint64_t SH_FLD_DAT1_LEN = 6190; // 1 -static const uint64_t SH_FLD_DATA = 6191; // 437 -static const uint64_t SH_FLD_DATA0 = 6192; // 6 -static const uint64_t SH_FLD_DATA0_LEN = 6193; // 6 -static const uint64_t SH_FLD_DATA1 = 6194; // 6 -static const uint64_t SH_FLD_DATA1_LEN = 6195; // 6 -static const uint64_t SH_FLD_DATA2 = 6196; // 6 -static const uint64_t SH_FLD_DATA2_LEN = 6197; // 6 -static const uint64_t SH_FLD_DATA_0_63 = 6198; // 2 -static const uint64_t SH_FLD_DATA_0_63_LEN = 6199; // 2 -static const uint64_t SH_FLD_DATA_64_79 = 6200; // 2 -static const uint64_t SH_FLD_DATA_64_79_LEN = 6201; // 2 -static const uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG = 6202; // 1 -static const uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG_LEN = 6203; // 1 -static const uint64_t SH_FLD_DATA_BUFFER = 6204; // 43 -static const uint64_t SH_FLD_DATA_COMPARE_BURST_SEL = 6205; // 2 -static const uint64_t SH_FLD_DATA_COMPARE_BURST_SEL_LEN = 6206; // 2 -static const uint64_t SH_FLD_DATA_DLY = 6207; // 1 -static const uint64_t SH_FLD_DATA_DLY_LEN = 6208; // 1 -static const uint64_t SH_FLD_DATA_HANG_DETECTED = 6209; // 2 -static const uint64_t SH_FLD_DATA_HANG_POLL_SCALE = 6210; // 2 -static const uint64_t SH_FLD_DATA_HANG_POLL_SCALE_LEN = 6211; // 2 -static const uint64_t SH_FLD_DATA_LEN = 6212; // 437 -static const uint64_t SH_FLD_DATA_MUX4_1MODE = 6213; // 8 -static const uint64_t SH_FLD_DATA_PARITY_ERR = 6214; // 4 -static const uint64_t SH_FLD_DATA_PIPE_CLR_ON_READ_MODE = 6215; // 6 -static const uint64_t SH_FLD_DATA_POISON_SUE_ENA = 6216; // 6 -static const uint64_t SH_FLD_DATA_POLL_PULSE_DIV = 6217; // 12 -static const uint64_t SH_FLD_DATA_POLL_PULSE_DIV_LEN = 6218; // 12 -static const uint64_t SH_FLD_DATA_REG0 = 6219; // 8 -static const uint64_t SH_FLD_DATA_REG0_LEN = 6220; // 8 -static const uint64_t SH_FLD_DATA_REG1 = 6221; // 8 -static const uint64_t SH_FLD_DATA_REG1_LEN = 6222; // 8 -static const uint64_t SH_FLD_DATA_REG_0_31 = 6223; // 1 -static const uint64_t SH_FLD_DATA_REG_0_31_LEN = 6224; // 1 -static const uint64_t SH_FLD_DATA_REQUEST_0 = 6225; // 4 -static const uint64_t SH_FLD_DATA_REQUEST_1 = 6226; // 2 -static const uint64_t SH_FLD_DATA_REQUEST_2 = 6227; // 2 -static const uint64_t SH_FLD_DATA_REQUEST_3 = 6228; // 2 -static const uint64_t SH_FLD_DATA_ROUTE_ERROR = 6229; // 2 -static const uint64_t SH_FLD_DATA_RTAG_P = 6230; // 12 -static const uint64_t SH_FLD_DATA_V_LT = 6231; // 43 -static const uint64_t SH_FLD_DAT_ARR_ECC_CORR_ENA = 6232; // 6 -static const uint64_t SH_FLD_DAT_ARR_ECC_SUE_ENA = 6233; // 6 -static const uint64_t SH_FLD_DAT_BUFFER_PAR_ERR = 6234; // 4 -static const uint64_t SH_FLD_DAT_CREG_PERR = 6235; // 1 -static const uint64_t SH_FLD_DAT_DATA_BE_CE = 6236; // 1 -static const uint64_t SH_FLD_DAT_DATA_BE_PERR = 6237; // 1 -static const uint64_t SH_FLD_DAT_DATA_BE_SUE = 6238; // 1 -static const uint64_t SH_FLD_DAT_DATA_BE_UE = 6239; // 1 -static const uint64_t SH_FLD_DAT_LOGIC_ERR = 6240; // 1 -static const uint64_t SH_FLD_DAT_PBRX_SUE = 6241; // 1 -static const uint64_t SH_FLD_DAT_RSVD_10 = 6242; // 1 -static const uint64_t SH_FLD_DAT_RSVD_9 = 6243; // 1 -static const uint64_t SH_FLD_DAT_RTAG_PERR = 6244; // 1 -static const uint64_t SH_FLD_DAT_STATE_PERR = 6245; // 1 -static const uint64_t SH_FLD_DBG_BUS0_STG0_SEL = 6246; // 2 -static const uint64_t SH_FLD_DBG_BUS0_STG0_SEL_LEN = 6247; // 2 -static const uint64_t SH_FLD_DBG_BUS1_STG0_SEL = 6248; // 2 -static const uint64_t SH_FLD_DBG_BUS1_STG0_SEL_LEN = 6249; // 2 -static const uint64_t SH_FLD_DBG_BUS_BIT = 6250; // 8 -static const uint64_t SH_FLD_DBG_CC_ERROR = 6251; // 1 -static const uint64_t SH_FLD_DBG_CHIPLET_IS_ALIGNED = 6252; // 1 -static const uint64_t SH_FLD_DBG_CLR_MAX_HANG_STAGE = 6253; // 3 -static const uint64_t SH_FLD_DBG_CMD = 6254; // 1 -static const uint64_t SH_FLD_DBG_CMD_LEN = 6255; // 1 -static const uint64_t SH_FLD_DBG_CTL_REG_PARITY_ERRHOLD = 6256; // 2 -static const uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE = 6257; // 1 -static const uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE_LEN = 6258; // 1 -static const uint64_t SH_FLD_DBG_HALT = 6259; // 1 -static const uint64_t SH_FLD_DBG_LAST_OPCG_MODE = 6260; // 1 -static const uint64_t SH_FLD_DBG_LAST_OPCG_MODE_LEN = 6261; // 1 -static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS0 = 6262; // 1 -static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS0_LEN = 6263; // 1 -static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS1 = 6264; // 1 -static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS1_LEN = 6265; // 1 -static const uint64_t SH_FLD_DBG_OPCG_IP = 6266; // 1 -static const uint64_t SH_FLD_DBG_PARANOIA_TEST_ENABLE_CHANGE = 6267; // 1 -static const uint64_t SH_FLD_DBG_PARANOIA_VITL_CLKOFF_CHANGE = 6268; // 1 -static const uint64_t SH_FLD_DBG_PARITY_ERROR = 6269; // 1 -static const uint64_t SH_FLD_DBG_PCB_ERROR = 6270; // 1 -static const uint64_t SH_FLD_DBG_PCB_IDLE = 6271; // 1 -static const uint64_t SH_FLD_DBG_PCB_REQUEST_SINCE_RESET = 6272; // 1 -static const uint64_t SH_FLD_DBG_PROTOCOL_ERROR = 6273; // 1 -static const uint64_t SH_FLD_DBG_REQ = 6274; // 1 -static const uint64_t SH_FLD_DBG_RESET_EP = 6275; // 1 -static const uint64_t SH_FLD_DBG_SECURITY_DEBUG_MODE = 6276; // 1 -static const uint64_t SH_FLD_DBG_SEL_IN = 6277; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWCTL_DEBUG = 6278; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 = 6279; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 = 6280; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 = 6281; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 = 6282; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 = 6283; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 = 6284; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 = 6285; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 = 6286; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 = 6287; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 = 6288; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 = 6289; // 8 -static const uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 = 6290; // 8 -static const uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 = 6291; // 8 -static const uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 = 6292; // 8 -static const uint64_t SH_FLD_DBG_SEL_WDF = 6293; // 8 -static const uint64_t SH_FLD_DBG_SEL_WDFMGR_DEBUG = 6294; // 8 -static const uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_0 = 6295; // 8 -static const uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_1 = 6296; // 8 -static const uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_0 = 6297; // 8 -static const uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_1 = 6298; // 8 -static const uint64_t SH_FLD_DBG_SPARE = 6299; // 8 -static const uint64_t SH_FLD_DBG_SPARE_LEN = 6300; // 8 -static const uint64_t SH_FLD_DBG_SPARE_MCA = 6301; // 8 -static const uint64_t SH_FLD_DBG_SPARE_MCA_LEN = 6302; // 8 -static const uint64_t SH_FLD_DBG_SPARE_NEST = 6303; // 8 -static const uint64_t SH_FLD_DBG_SPARE_NEST_LEN = 6304; // 8 -static const uint64_t SH_FLD_DBG_STATE = 6305; // 1 -static const uint64_t SH_FLD_DBG_STATE_LEN = 6306; // 1 -static const uint64_t SH_FLD_DBG_TEST_ENABLE = 6307; // 1 -static const uint64_t SH_FLD_DBG_TP_TPFSI_ACK = 6308; // 1 -static const uint64_t SH_FLD_DBG_UNCONDITIONAL_EVENT = 6309; // 1 -static const uint64_t SH_FLD_DBG_VITL_CLKOFF = 6310; // 1 -static const uint64_t SH_FLD_DBLERR = 6311; // 2 -static const uint64_t SH_FLD_DCACHE_ERR = 6312; // 4 -static const uint64_t SH_FLD_DCACHE_TAG_ADDR = 6313; // 4 -static const uint64_t SH_FLD_DCACHE_TAG_ADDR_LEN = 6314; // 4 -static const uint64_t SH_FLD_DCLKSEL = 6315; // 6 -static const uint64_t SH_FLD_DCLKSEL_LEN = 6316; // 6 -static const uint64_t SH_FLD_DCOMP_ENABLE = 6317; // 1 -static const uint64_t SH_FLD_DCOMP_ENGINE_BUSY = 6318; // 1 -static const uint64_t SH_FLD_DCOMP_ERR = 6319; // 1 -static const uint64_t SH_FLD_DCO_DECR = 6320; // 6 -static const uint64_t SH_FLD_DCO_INCR = 6321; // 6 -static const uint64_t SH_FLD_DCO_OVERRIDE = 6322; // 6 -static const uint64_t SH_FLD_DCU_RNW = 6323; // 1 -static const uint64_t SH_FLD_DCU_TIMEOUT_ERROR = 6324; // 1 -static const uint64_t SH_FLD_DC_CALIBRATE_DONE = 6325; // 4 -static const uint64_t SH_FLD_DC_ENABLE_CM_COARSE_CAL = 6326; // 6 -static const uint64_t SH_FLD_DC_ENABLE_CM_FINE_CAL = 6327; // 6 -static const uint64_t SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 6328; // 6 -static const uint64_t SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 6329; // 6 -static const uint64_t SH_FLD_DC_ENABLE_DAC_H1_CAL = 6330; // 4 -static const uint64_t SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL = 6331; // 4 -static const uint64_t SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 6332; // 6 -static const uint64_t SH_FLD_DD2_FIX_DIS = 6333; // 8 -static const uint64_t SH_FLD_DDC_CFG = 6334; // 120 -static const uint64_t SH_FLD_DDC_CFG_LEN = 6335; // 120 -static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM = 6336; // 72 -static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN = 6337; // 72 -static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP = 6338; // 72 -static const uint64_t SH_FLD_DDR0 = 6339; // 24 -static const uint64_t SH_FLD_DDR01_PARITY_ERR = 6340; // 16 -static const uint64_t SH_FLD_DDR0_CALIBRATION_ERROR = 6341; // 16 -static const uint64_t SH_FLD_DDR0_FSM_CKSTP = 6342; // 16 -static const uint64_t SH_FLD_DDR0_FSM_ERR = 6343; // 16 -static const uint64_t SH_FLD_DDR0_LEN = 6344; // 24 -static const uint64_t SH_FLD_DDR0_PARITY_CKSTP = 6345; // 16 -static const uint64_t SH_FLD_DDR0_PARITY_ERR = 6346; // 16 -static const uint64_t SH_FLD_DDR1 = 6347; // 24 -static const uint64_t SH_FLD_DDR1_CALIBRATION_ERROR = 6348; // 16 -static const uint64_t SH_FLD_DDR1_FSM_CKSTP = 6349; // 16 -static const uint64_t SH_FLD_DDR1_FSM_ERR = 6350; // 16 -static const uint64_t SH_FLD_DDR1_LEN = 6351; // 24 -static const uint64_t SH_FLD_DDR1_PARITY_CKSTP = 6352; // 16 -static const uint64_t SH_FLD_DDR1_PARITY_ERR = 6353; // 16 -static const uint64_t SH_FLD_DDR4_CMD_SIG_REDUCTION = 6354; // 8 -static const uint64_t SH_FLD_DDR4_IPW_LOOP_DIS = 6355; // 8 -static const uint64_t SH_FLD_DDR4_LATENCY_SW = 6356; // 8 -static const uint64_t SH_FLD_DDR4_VLEVEL_BANK_GROUP = 6357; // 8 -static const uint64_t SH_FLD_DDR_ACTN = 6358; // 64 -static const uint64_t SH_FLD_DDR_ADDRESS = 6359; // 8 -static const uint64_t SH_FLD_DDR_ADDRESS_0 = 6360; // 2 -static const uint64_t SH_FLD_DDR_ADDRESS_0_13 = 6361; // 62 -static const uint64_t SH_FLD_DDR_ADDRESS_0_13_LEN = 6362; // 62 -static const uint64_t SH_FLD_DDR_ADDRESS_0_LEN = 6363; // 2 -static const uint64_t SH_FLD_DDR_ADDRESS_14 = 6364; // 62 -static const uint64_t SH_FLD_DDR_ADDRESS_15 = 6365; // 62 -static const uint64_t SH_FLD_DDR_ADDRESS_16 = 6366; // 62 -static const uint64_t SH_FLD_DDR_ADDRESS_17 = 6367; // 62 -static const uint64_t SH_FLD_DDR_BANK_0_1 = 6368; // 64 -static const uint64_t SH_FLD_DDR_BANK_0_1_LEN = 6369; // 64 -static const uint64_t SH_FLD_DDR_BANK_2 = 6370; // 64 -static const uint64_t SH_FLD_DDR_BANK_GROUP_0 = 6371; // 64 -static const uint64_t SH_FLD_DDR_BANK_GROUP_1 = 6372; // 64 -static const uint64_t SH_FLD_DDR_CALIBRATION_ENABLE = 6373; // 64 -static const uint64_t SH_FLD_DDR_CAL_RANK = 6374; // 64 -static const uint64_t SH_FLD_DDR_CAL_RANK_LEN = 6375; // 64 -static const uint64_t SH_FLD_DDR_CAL_RESET_TIMEOUT = 6376; // 16 -static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT = 6377; // 2 -static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN = 6378; // 2 -static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT = 6379; // 2 -static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 6380; // 2 -static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_ERR = 6381; // 16 -static const uint64_t SH_FLD_DDR_CAL_TYPE = 6382; // 64 -static const uint64_t SH_FLD_DDR_CAL_TYPE_LEN = 6383; // 64 -static const uint64_t SH_FLD_DDR_CID_0_1 = 6384; // 64 -static const uint64_t SH_FLD_DDR_CID_0_1_LEN = 6385; // 64 -static const uint64_t SH_FLD_DDR_CID_2 = 6386; // 64 -static const uint64_t SH_FLD_DDR_CKE = 6387; // 64 -static const uint64_t SH_FLD_DDR_CKE_LEN = 6388; // 64 -static const uint64_t SH_FLD_DDR_CSN_0_1 = 6389; // 64 -static const uint64_t SH_FLD_DDR_CSN_0_1_LEN = 6390; // 64 -static const uint64_t SH_FLD_DDR_CSN_2_3 = 6391; // 64 -static const uint64_t SH_FLD_DDR_CSN_2_3_LEN = 6392; // 64 -static const uint64_t SH_FLD_DDR_IF_SM_1HOT = 6393; // 8 -static const uint64_t SH_FLD_DDR_MBA_EVENT_N = 6394; // 16 -static const uint64_t SH_FLD_DDR_ODT = 6395; // 64 -static const uint64_t SH_FLD_DDR_ODT_LEN = 6396; // 64 -static const uint64_t SH_FLD_DDR_PARITY = 6397; // 64 -static const uint64_t SH_FLD_DDR_PARITY_ENABLE = 6398; // 2 -static const uint64_t SH_FLD_DDR_RESETN = 6399; // 64 -static const uint64_t SH_FLD_DEAD = 6400; // 43 -static const uint64_t SH_FLD_DEBUG = 6401; // 2 -static const uint64_t SH_FLD_DEBUG0_CONFIG_P = 6402; // 1 -static const uint64_t SH_FLD_DEBUG1_CONFIG_P = 6403; // 1 -static const uint64_t SH_FLD_DEBUGGER = 6404; // 25 -static const uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS = 6405; // 1 -static const uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 6406; // 1 -static const uint64_t SH_FLD_DEBUG_BUS_0_63 = 6407; // 4 -static const uint64_t SH_FLD_DEBUG_BUS_0_63_LEN = 6408; // 4 -static const uint64_t SH_FLD_DEBUG_BUS_64_87 = 6409; // 4 -static const uint64_t SH_FLD_DEBUG_BUS_64_87_LEN = 6410; // 4 -static const uint64_t SH_FLD_DEBUG_BUS_SEL = 6411; // 8 -static const uint64_t SH_FLD_DEBUG_BUS_SEL2 = 6412; // 8 -static const uint64_t SH_FLD_DEBUG_BUS_SEL2_LEN = 6413; // 8 -static const uint64_t SH_FLD_DEBUG_BUS_SEL_LEN = 6414; // 8 -static const uint64_t SH_FLD_DEBUG_LEN = 6415; // 2 -static const uint64_t SH_FLD_DEBUG_OCI_MODE = 6416; // 1 -static const uint64_t SH_FLD_DEBUG_OCI_MODE_LEN = 6417; // 1 -static const uint64_t SH_FLD_DEBUG_PB_NOT_OCI = 6418; // 1 -static const uint64_t SH_FLD_DEBUG_TRIGGER = 6419; // 25 -static const uint64_t SH_FLD_DECONFIGURED_INTR = 6420; // 24 -static const uint64_t SH_FLD_DECOUPLE_EDGE_A = 6421; // 48 -static const uint64_t SH_FLD_DECOUPLE_EDGE_B = 6422; // 48 -static const uint64_t SH_FLD_DEC_EXIT_ENABLE = 6423; // 96 -static const uint64_t SH_FLD_DEF_VALUES = 6424; // 8 -static const uint64_t SH_FLD_DEF_VALUES_LEN = 6425; // 8 -static const uint64_t SH_FLD_DEGLITCH_CLK_DLY = 6426; // 1 -static const uint64_t SH_FLD_DEGLITCH_CLK_DLY_LEN = 6427; // 1 -static const uint64_t SH_FLD_DEGLITCH_DATA_DLY = 6428; // 1 -static const uint64_t SH_FLD_DEGLITCH_DATA_DLY_LEN = 6429; // 1 -static const uint64_t SH_FLD_DELAY = 6430; // 1 -static const uint64_t SH_FLD_DELAY1_ID = 6431; // 12 -static const uint64_t SH_FLD_DELAY1_ID_LEN = 6432; // 12 -static const uint64_t SH_FLD_DELAY1_VALID = 6433; // 12 -static const uint64_t SH_FLD_DELAY2_ID = 6434; // 12 -static const uint64_t SH_FLD_DELAY2_ID_LEN = 6435; // 12 -static const uint64_t SH_FLD_DELAY2_VALID = 6436; // 12 -static const uint64_t SH_FLD_DELAY3_ID = 6437; // 12 -static const uint64_t SH_FLD_DELAY3_ID_LEN = 6438; // 12 -static const uint64_t SH_FLD_DELAY3_VALID = 6439; // 12 -static const uint64_t SH_FLD_DELAY4_ID = 6440; // 12 -static const uint64_t SH_FLD_DELAY4_ID_LEN = 6441; // 12 -static const uint64_t SH_FLD_DELAY4_VALID = 6442; // 12 -static const uint64_t SH_FLD_DELAY5_ID = 6443; // 12 -static const uint64_t SH_FLD_DELAY5_ID_LEN = 6444; // 12 -static const uint64_t SH_FLD_DELAY5_VALID = 6445; // 12 -static const uint64_t SH_FLD_DELAY6_ID = 6446; // 12 -static const uint64_t SH_FLD_DELAY6_ID_LEN = 6447; // 12 -static const uint64_t SH_FLD_DELAY6_VALID = 6448; // 12 -static const uint64_t SH_FLD_DELAY7_ID = 6449; // 12 -static const uint64_t SH_FLD_DELAY7_ID_LEN = 6450; // 12 -static const uint64_t SH_FLD_DELAY7_VALID = 6451; // 12 -static const uint64_t SH_FLD_DELAY8_ID = 6452; // 12 -static const uint64_t SH_FLD_DELAY8_ID_LEN = 6453; // 12 -static const uint64_t SH_FLD_DELAY8_VALID = 6454; // 12 -static const uint64_t SH_FLD_DELAYED_PAR = 6455; // 8 -static const uint64_t SH_FLD_DELAYG = 6456; // 32 -static const uint64_t SH_FLD_DELAYG_LEN = 6457; // 32 -static const uint64_t SH_FLD_DELAY_ADJUST_DISABLE = 6458; // 1 -static const uint64_t SH_FLD_DELAY_ADJUST_VALUE = 6459; // 1 -static const uint64_t SH_FLD_DELAY_ADJUST_VALUE_LEN = 6460; // 1 -static const uint64_t SH_FLD_DELAY_AFTER_BLOCK = 6461; // 24 -static const uint64_t SH_FLD_DELAY_DISABLE = 6462; // 1 -static const uint64_t SH_FLD_DELAY_LCLKR = 6463; // 43 -static const uint64_t SH_FLD_DELAY_LEN = 6464; // 1 -static const uint64_t SH_FLD_DELAY_LINE_CTL_OVERRIDE = 6465; // 8 -static const uint64_t SH_FLD_DEQUEUED_EOT_FLAG = 6466; // 1 -static const uint64_t SH_FLD_DESKEW_BUMP_AFTER = 6467; // 4 -static const uint64_t SH_FLD_DESKEW_DONE = 6468; // 4 -static const uint64_t SH_FLD_DESKEW_FAILED = 6469; // 4 -static const uint64_t SH_FLD_DESKEW_MAXSKEW_GRP = 6470; // 4 -static const uint64_t SH_FLD_DESKEW_MAXSKEW_GRP_LEN = 6471; // 4 -static const uint64_t SH_FLD_DESKEW_MAX_LIMIT = 6472; // 4 -static const uint64_t SH_FLD_DESKEW_MAX_LIMIT_LEN = 6473; // 4 -static const uint64_t SH_FLD_DESKEW_MINSKEW_GRP = 6474; // 4 -static const uint64_t SH_FLD_DESKEW_MINSKEW_GRP_LEN = 6475; // 4 -static const uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL = 6476; // 4 -static const uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 6477; // 4 -static const uint64_t SH_FLD_DESKEW_RATE = 6478; // 8 -static const uint64_t SH_FLD_DESKEW_SEQ_GCRMSG = 6479; // 4 -static const uint64_t SH_FLD_DESKEW_SEQ_GCRMSG_LEN = 6480; // 4 -static const uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG = 6481; // 4 -static const uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG_LEN = 6482; // 4 -static const uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG = 6483; // 4 -static const uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG_LEN = 6484; // 4 -static const uint64_t SH_FLD_DEST = 6485; // 1 -static const uint64_t SH_FLD_DEST0 = 6486; // 24 -static const uint64_t SH_FLD_DEST0_LEN = 6487; // 24 -static const uint64_t SH_FLD_DEST1 = 6488; // 24 -static const uint64_t SH_FLD_DEST1_LEN = 6489; // 24 -static const uint64_t SH_FLD_DEST_CHIPID = 6490; // 1 -static const uint64_t SH_FLD_DEST_CHIPID_LEN = 6491; // 1 -static const uint64_t SH_FLD_DEST_GROUPID = 6492; // 1 -static const uint64_t SH_FLD_DEST_GROUPID_LEN = 6493; // 1 -static const uint64_t SH_FLD_DEST_LEN = 6494; // 1 -static const uint64_t SH_FLD_DETAIL = 6495; // 2 -static const uint64_t SH_FLD_DETAIL_LEN = 6496; // 2 -static const uint64_t SH_FLD_DEVICE = 6497; // 1 -static const uint64_t SH_FLD_DEVICE_ADDRESS_0 = 6498; // 2 -static const uint64_t SH_FLD_DEVICE_ADDRESS_0_LEN = 6499; // 2 -static const uint64_t SH_FLD_DEVICE_ADDRESS_1 = 6500; // 1 -static const uint64_t SH_FLD_DEVICE_ADDRESS_1_LEN = 6501; // 1 -static const uint64_t SH_FLD_DEVICE_ADDRESS_2 = 6502; // 1 -static const uint64_t SH_FLD_DEVICE_ADDRESS_2_LEN = 6503; // 1 -static const uint64_t SH_FLD_DEVICE_ADDRESS_3 = 6504; // 1 -static const uint64_t SH_FLD_DEVICE_ADDRESS_3_LEN = 6505; // 1 -static const uint64_t SH_FLD_DEVICE_ID = 6506; // 4 -static const uint64_t SH_FLD_DEVICE_ID_LEN = 6507; // 4 -static const uint64_t SH_FLD_DFE12_EN = 6508; // 4 -static const uint64_t SH_FLD_DFEHISPD_EN = 6509; // 4 -static const uint64_t SH_FLD_DFE_CA_CFG = 6510; // 6 -static const uint64_t SH_FLD_DFE_CA_CFG_LEN = 6511; // 6 -static const uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX = 6512; // 6 -static const uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX_LEN = 6513; // 6 -static const uint64_t SH_FLD_DFE_FORCE_LOAD_SEED = 6514; // 72 -static const uint64_t SH_FLD_DFE_HTAP_CFG = 6515; // 4 -static const uint64_t SH_FLD_DFE_HTAP_CFG_LEN = 6516; // 4 -static const uint64_t SH_FLD_DFE_INIT_TIMEOUT = 6517; // 4 -static const uint64_t SH_FLD_DFE_INIT_TIMEOUT_LEN = 6518; // 4 -static const uint64_t SH_FLD_DFE_RECAL_TIMEOUT = 6519; // 4 -static const uint64_t SH_FLD_DFE_RECAL_TIMEOUT_LEN = 6520; // 4 -static const uint64_t SH_FLD_DFREEZE = 6521; // 9 -static const uint64_t SH_FLD_DFREEZE_LEN = 6522; // 9 -static const uint64_t SH_FLD_DFS_SM_ERRHOLD = 6523; // 2 -static const uint64_t SH_FLD_DGD_AE_ALWAYS = 6524; // 6 -static const uint64_t SH_FLD_DGD_BE_128 = 6525; // 6 -static const uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING = 6526; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN = 6527; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_SEED0 = 6528; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_SEED0_LEN = 6529; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_SEED1 = 6530; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_SEED1_LEN = 6531; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_SEED2 = 6532; // 2 -static const uint64_t SH_FLD_DGEN_RNDD_SEED2_LEN = 6533; // 2 -static const uint64_t SH_FLD_DIAG_0 = 6534; // 2 -static const uint64_t SH_FLD_DIAG_1 = 6535; // 1 -static const uint64_t SH_FLD_DIAG_2 = 6536; // 1 -static const uint64_t SH_FLD_DIAG_3 = 6537; // 1 -static const uint64_t SH_FLD_DIB01_ERR = 6538; // 4 -static const uint64_t SH_FLD_DIB01_SPARE = 6539; // 1 -static const uint64_t SH_FLD_DIB01_SPARE_LEN = 6540; // 1 -static const uint64_t SH_FLD_DIB23_ERR = 6541; // 4 -static const uint64_t SH_FLD_DIB45_ERR = 6542; // 4 -static const uint64_t SH_FLD_DIB67_ERR = 6543; // 2 -static const uint64_t SH_FLD_DIB67_SPARE = 6544; // 1 -static const uint64_t SH_FLD_DIB67_SPARE_LEN = 6545; // 1 -static const uint64_t SH_FLD_DIGITAL_EYE = 6546; // 8 -static const uint64_t SH_FLD_DIRECT_BRIDGE_SOURCE = 6547; // 1 -static const uint64_t SH_FLD_DIR_CE_DETECTED = 6548; // 12 -static const uint64_t SH_FLD_DIR_PERR_CHK_DIS = 6549; // 2 -static const uint64_t SH_FLD_DIR_SBCE_REPAIR_FAILED = 6550; // 12 -static const uint64_t SH_FLD_DIR_STUCK_BIT_CE = 6551; // 12 -static const uint64_t SH_FLD_DIR_UE_DETECTED = 6552; // 12 -static const uint64_t SH_FLD_DISABLE = 6553; // 2 -static const uint64_t SH_FLD_DISABLED = 6554; // 47 -static const uint64_t SH_FLD_DISABLED_LEN = 6555; // 4 -static const uint64_t SH_FLD_DISABLE_1 = 6556; // 1 -static const uint64_t SH_FLD_DISABLE_1_LEN = 6557; // 1 -static const uint64_t SH_FLD_DISABLE_2 = 6558; // 1 -static const uint64_t SH_FLD_DISABLE_2K_SPEC_FILTER = 6559; // 4 -static const uint64_t SH_FLD_DISABLE_2N_MODE = 6560; // 2 -static const uint64_t SH_FLD_DISABLE_2TO12_CLEAR = 6561; // 4 -static const uint64_t SH_FLD_DISABLE_2_LEN = 6562; // 1 -static const uint64_t SH_FLD_DISABLE_ALL_SPEC_OPS = 6563; // 4 -static const uint64_t SH_FLD_DISABLE_ARY_CLK_DURING_FILL = 6564; // 43 -static const uint64_t SH_FLD_DISABLE_BAD_LANE_COUNT = 6565; // 2 -static const uint64_t SH_FLD_DISABLE_BANK_PDWN = 6566; // 2 -static const uint64_t SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW = 6567; // 4 -static const uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH = 6568; // 4 -static const uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 6569; // 4 -static const uint64_t SH_FLD_DISABLE_CHARB_BYPASS = 6570; // 4 -static const uint64_t SH_FLD_DISABLE_CHECKIN_HANG_TIMER = 6571; // 1 -static const uint64_t SH_FLD_DISABLE_CHECKOUT_HANG_TIMER = 6572; // 1 -static const uint64_t SH_FLD_DISABLE_CHECKSTOP = 6573; // 1 -static const uint64_t SH_FLD_DISABLE_CI = 6574; // 4 -static const uint64_t SH_FLD_DISABLE_CI_LEN = 6575; // 4 -static const uint64_t SH_FLD_DISABLE_CLEAR_BAD_LANE_COUNT = 6576; // 2 -static const uint64_t SH_FLD_DISABLE_COMMAND_BYPASS = 6577; // 4 -static const uint64_t SH_FLD_DISABLE_COMMAND_BYPASS_LEN = 6578; // 4 -static const uint64_t SH_FLD_DISABLE_COMPRESSION = 6579; // 90 -static const uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS = 6580; // 4 -static const uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN = 6581; // 4 -static const uint64_t SH_FLD_DISABLE_CRC_ECC_FP_BYPASS = 6582; // 4 -static const uint64_t SH_FLD_DISABLE_DROPABLE = 6583; // 8 -static const uint64_t SH_FLD_DISABLE_ECC = 6584; // 1 -static const uint64_t SH_FLD_DISABLE_ECC_ARRAY_CHK = 6585; // 2 -static const uint64_t SH_FLD_DISABLE_ECC_ARRAY_CORRECTION = 6586; // 2 -static const uint64_t SH_FLD_DISABLE_ECC_CHK = 6587; // 1 -static const uint64_t SH_FLD_DISABLE_ECC_CORRECTION = 6588; // 1 -static const uint64_t SH_FLD_DISABLE_ECC_COR_GXC_PSI = 6589; // 1 -static const uint64_t SH_FLD_DISABLE_ECC_COR_RXRF_PSI = 6590; // 1 -static const uint64_t SH_FLD_DISABLE_ECC_COR_TXRF_PSI = 6591; // 1 -static const uint64_t SH_FLD_DISABLE_ERR_CMD = 6592; // 1 -static const uint64_t SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES = 6593; // 1 -static const uint64_t SH_FLD_DISABLE_EXTRA_HASH_ACCESSES = 6594; // 1 -static const uint64_t SH_FLD_DISABLE_FAR_HISTORY = 6595; // 1 -static const uint64_t SH_FLD_DISABLE_FASTPATH = 6596; // 4 -static const uint64_t SH_FLD_DISABLE_FENCE_RESET = 6597; // 4 -static const uint64_t SH_FLD_DISABLE_FLOW_SCOPE = 6598; // 1 -static const uint64_t SH_FLD_DISABLE_FP_COMMAND_BYPASS = 6599; // 4 -static const uint64_t SH_FLD_DISABLE_FP_M_BIT = 6600; // 4 -static const uint64_t SH_FLD_DISABLE_G = 6601; // 1 -static const uint64_t SH_FLD_DISABLE_G_RD = 6602; // 1 -static const uint64_t SH_FLD_DISABLE_G_WR = 6603; // 1 -static const uint64_t SH_FLD_DISABLE_H1_CLEAR = 6604; // 6 -static const uint64_t SH_FLD_DISABLE_HIGH_PRIORITY = 6605; // 4 -static const uint64_t SH_FLD_DISABLE_HIGH_PRIORITY_LEN = 6606; // 4 -static const uint64_t SH_FLD_DISABLE_HIT_UNDER_BARRIER = 6607; // 1 -static const uint64_t SH_FLD_DISABLE_HTM_CMD = 6608; // 1 -static const uint64_t SH_FLD_DISABLE_INJECT = 6609; // 1 -static const uint64_t SH_FLD_DISABLE_LFSR = 6610; // 1 -static const uint64_t SH_FLD_DISABLE_LINK_FAIL_COUNT = 6611; // 2 -static const uint64_t SH_FLD_DISABLE_LN = 6612; // 1 -static const uint64_t SH_FLD_DISABLE_LN_RD = 6613; // 1 -static const uint64_t SH_FLD_DISABLE_LN_WR = 6614; // 1 -static const uint64_t SH_FLD_DISABLE_LPC_CMDS = 6615; // 3 -static const uint64_t SH_FLD_DISABLE_MDI0 = 6616; // 4 -static const uint64_t SH_FLD_DISABLE_MDI0_LEN = 6617; // 4 -static const uint64_t SH_FLD_DISABLE_MEMCTL_CAL = 6618; // 8 -static const uint64_t SH_FLD_DISABLE_NEAR_HISTORY = 6619; // 1 -static const uint64_t SH_FLD_DISABLE_NN_RD = 6620; // 1 -static const uint64_t SH_FLD_DISABLE_NN_RN = 6621; // 1 -static const uint64_t SH_FLD_DISABLE_NN_WR = 6622; // 1 -static const uint64_t SH_FLD_DISABLE_PARITY_CHECKER = 6623; // 8 -static const uint64_t SH_FLD_DISABLE_PCB_ITR = 6624; // 43 -static const uint64_t SH_FLD_DISABLE_PERFMON_RESET_ON_START = 6625; // 4 -static const uint64_t SH_FLD_DISABLE_PMISC = 6626; // 9 -static const uint64_t SH_FLD_DISABLE_PMU_SNOOPING = 6627; // 1 -static const uint64_t SH_FLD_DISABLE_PROMOTE = 6628; // 1 -static const uint64_t SH_FLD_DISABLE_PTAG_IN_AIBTAG = 6629; // 1 -static const uint64_t SH_FLD_DISABLE_RCMD_CLKGATE = 6630; // 3 -static const uint64_t SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 6631; // 4 -static const uint64_t SH_FLD_DISABLE_RETRY_LOST_CLAIM = 6632; // 4 -static const uint64_t SH_FLD_DISABLE_SHARD_PRESP_ABORT = 6633; // 4 -static const uint64_t SH_FLD_DISABLE_SL_ECC = 6634; // 5 -static const uint64_t SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT = 6635; // 4 -static const uint64_t SH_FLD_DISABLE_SPEC_OP = 6636; // 4 -static const uint64_t SH_FLD_DISABLE_SPEC_OP_LEN = 6637; // 4 -static const uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE = 6638; // 4 -static const uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN = 6639; // 4 -static const uint64_t SH_FLD_DISABLE_STICKINESS = 6640; // 43 -static const uint64_t SH_FLD_DISABLE_TIMEOUT = 6641; // 1 -static const uint64_t SH_FLD_DISABLE_TIMEOUT_AND_RETRY = 6642; // 1 -static const uint64_t SH_FLD_DISABLE_TOD_CMD = 6643; // 1 -static const uint64_t SH_FLD_DISABLE_TRACE_CMD = 6644; // 1 -static const uint64_t SH_FLD_DISABLE_VG_NOT_SYS = 6645; // 1 -static const uint64_t SH_FLD_DISABLE_VG_RD = 6646; // 1 -static const uint64_t SH_FLD_DISABLE_VG_WR = 6647; // 1 -static const uint64_t SH_FLD_DISABLE_WRP = 6648; // 1 -static const uint64_t SH_FLD_DISABLE_XSCOM_CMD = 6649; // 1 -static const uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT = 6650; // 1 -static const uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN = 6651; // 1 -static const uint64_t SH_FLD_DISP_DEBUG_SEL = 6652; // 8 -static const uint64_t SH_FLD_DISP_DEBUG_SEL_LEN = 6653; // 8 -static const uint64_t SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE = 6654; // 1 -static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_DISABLE = 6655; // 1 -static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 6656; // 1 -static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER = 6657; // 1 -static const uint64_t SH_FLD_DIS_AIB_IN_ECC_CORRECTION = 6658; // 1 -static const uint64_t SH_FLD_DIS_ARX_DAT_CORR = 6659; // 1 -static const uint64_t SH_FLD_DIS_ARX_DAT_CORR_LEN = 6660; // 1 -static const uint64_t SH_FLD_DIS_ARX_ECC_CORRECTION = 6661; // 1 -static const uint64_t SH_FLD_DIS_ARX_TAG_CORR = 6662; // 1 -static const uint64_t SH_FLD_DIS_ATX_AT_CORR = 6663; // 1 -static const uint64_t SH_FLD_DIS_ATX_BAR_CORR = 6664; // 1 -static const uint64_t SH_FLD_DIS_ATX_CMD_CORR = 6665; // 1 -static const uint64_t SH_FLD_DIS_AT_SRAM_ECC_CORRECTION = 6666; // 1 -static const uint64_t SH_FLD_DIS_AVX_CORR = 6667; // 1 -static const uint64_t SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION = 6668; // 1 -static const uint64_t SH_FLD_DIS_CHGRATE_COUNT = 6669; // 1 -static const uint64_t SH_FLD_DIS_CPM_BUBBLE_CORR = 6670; // 43 -static const uint64_t SH_FLD_DIS_CRESP_CORR = 6671; // 1 -static const uint64_t SH_FLD_DIS_CTRLBUF_ECC_CORRECTION = 6672; // 1 -static const uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION = 6673; // 4 -static const uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION_LEN = 6674; // 4 -static const uint64_t SH_FLD_DIS_DMA_W = 6675; // 1 -static const uint64_t SH_FLD_DIS_DROPABLE_HP = 6676; // 8 -static const uint64_t SH_FLD_DIS_ECCCHK = 6677; // 1 -static const uint64_t SH_FLD_DIS_ECCCHK_CLO = 6678; // 1 -static const uint64_t SH_FLD_DIS_ECCCHK_IN = 6679; // 1 -static const uint64_t SH_FLD_DIS_ECCCHK_LDO = 6680; // 1 -static const uint64_t SH_FLD_DIS_ECCCHK_STO = 6681; // 1 -static const uint64_t SH_FLD_DIS_ECCCHK_WRO = 6682; // 1 -static const uint64_t SH_FLD_DIS_GLOB_SCOM = 6683; // 2 -static const uint64_t SH_FLD_DIS_IRQ_ECC_CORRECTION = 6684; // 1 -static const uint64_t SH_FLD_DIS_LD_ECC_CORRECTION = 6685; // 1 -static const uint64_t SH_FLD_DIS_MASTER_RD_PIPE = 6686; // 1 -static const uint64_t SH_FLD_DIS_MASTER_WR_PIPE = 6687; // 1 -static const uint64_t SH_FLD_DIS_MMIO_LDST_CORR = 6688; // 1 -static const uint64_t SH_FLD_DIS_MMIO_RSP_CORR = 6689; // 1 -static const uint64_t SH_FLD_DIS_MSTID_MATCH_PREF_INV = 6690; // 1 -static const uint64_t SH_FLD_DIS_NCNP = 6691; // 1 -static const uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION = 6692; // 1 -static const uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN = 6693; // 1 -static const uint64_t SH_FLD_DIS_REARB = 6694; // 1 -static const uint64_t SH_FLD_DIS_RECOVERY = 6695; // 24 -static const uint64_t SH_FLD_DIS_REREQUEST_TO = 6696; // 1 -static const uint64_t SH_FLD_DIS_SLAVE_RDPIPE = 6697; // 1 -static const uint64_t SH_FLD_DIS_SLAVE_WRPIPE = 6698; // 1 -static const uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION = 6699; // 4 -static const uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION_LEN = 6700; // 2 -static const uint64_t SH_FLD_DIS_SYND_TALLYING = 6701; // 4 -static const uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION = 6702; // 4 -static const uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION_LEN = 6703; // 4 -static const uint64_t SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION = 6704; // 1 -static const uint64_t SH_FLD_DIS_TRACE_EXTRA = 6705; // 1 -static const uint64_t SH_FLD_DIS_TRACE_STALL = 6706; // 1 -static const uint64_t SH_FLD_DIS_VRQ_QUEUE_CORR = 6707; // 1 -static const uint64_t SH_FLD_DIS_WRITE_GATHER = 6708; // 4 -static const uint64_t SH_FLD_DIVIDER_MODE = 6709; // 12 -static const uint64_t SH_FLD_DIVIDER_MODE_LEN = 6710; // 12 -static const uint64_t SH_FLD_DIVSELB = 6711; // 10 -static const uint64_t SH_FLD_DIVSELB_LEN = 6712; // 10 -static const uint64_t SH_FLD_DIVSELFB = 6713; // 10 -static const uint64_t SH_FLD_DIVSELFB_LEN = 6714; // 10 -static const uint64_t SH_FLD_DIV_PARITY = 6715; // 43 -static const uint64_t SH_FLD_DLL = 6716; // 8 -static const uint64_t SH_FLD_DLL_CLOCK_GATE = 6717; // 8 -static const uint64_t SH_FLD_DL_RETURN_P0 = 6718; // 43 -static const uint64_t SH_FLD_DL_RETURN_WDATA_PARITY = 6719; // 43 -static const uint64_t SH_FLD_DMAP_MODE_EN = 6720; // 2 -static const uint64_t SH_FLD_DMA_CH0_IDLE = 6721; // 1 -static const uint64_t SH_FLD_DMA_CH1_IDLE = 6722; // 1 -static const uint64_t SH_FLD_DMA_CH2_IDLE = 6723; // 1 -static const uint64_t SH_FLD_DMA_CH3_IDLE = 6724; // 1 -static const uint64_t SH_FLD_DMA_CH4_IDLE = 6725; // 1 -static const uint64_t SH_FLD_DMA_CRBARRAY_ACTION = 6726; // 1 -static const uint64_t SH_FLD_DMA_CRBARRAY_ENA = 6727; // 1 -static const uint64_t SH_FLD_DMA_CRBARRAY_SELECT = 6728; // 1 -static const uint64_t SH_FLD_DMA_CRBARRAY_TYPE = 6729; // 1 -static const uint64_t SH_FLD_DMA_EGRARRAY_ACTION = 6730; // 1 -static const uint64_t SH_FLD_DMA_EGRARRAY_ENA = 6731; // 1 -static const uint64_t SH_FLD_DMA_EGRARRAY_SELECT = 6732; // 1 -static const uint64_t SH_FLD_DMA_EGRARRAY_SELECT_LEN = 6733; // 1 -static const uint64_t SH_FLD_DMA_EGRARRAY_TYPE = 6734; // 1 -static const uint64_t SH_FLD_DMA_INGARRAY_ACTION = 6735; // 1 -static const uint64_t SH_FLD_DMA_INGARRAY_ENA = 6736; // 1 -static const uint64_t SH_FLD_DMA_INGARRAY_SELECT = 6737; // 1 -static const uint64_t SH_FLD_DMA_INGARRAY_SELECT_LEN = 6738; // 1 -static const uint64_t SH_FLD_DMA_INGARRAY_TYPE = 6739; // 1 -static const uint64_t SH_FLD_DMA_INWR_ACTION = 6740; // 1 -static const uint64_t SH_FLD_DMA_INWR_ENA = 6741; // 1 -static const uint64_t SH_FLD_DMA_INWR_TYPE = 6742; // 1 -static const uint64_t SH_FLD_DMA_MUX_SELECT = 6743; // 1 -static const uint64_t SH_FLD_DMA_MUX_SELECT_LEN = 6744; // 1 -static const uint64_t SH_FLD_DMA_OUTWR_ACTION = 6745; // 1 -static const uint64_t SH_FLD_DMA_OUTWR_ENA = 6746; // 1 -static const uint64_t SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA = 6747; // 1 -static const uint64_t SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA = 6748; // 1 -static const uint64_t SH_FLD_DMA_OUTWR_TYPE = 6749; // 1 -static const uint64_t SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT = 6750; // 1 -static const uint64_t SH_FLD_DMA_PART_WR_NOT_INJ = 6751; // 1 -static const uint64_t SH_FLD_DMA_RD_DISABLE_GROUP = 6752; // 2 -static const uint64_t SH_FLD_DMA_RD_DISABLE_LN = 6753; // 2 -static const uint64_t SH_FLD_DMA_RD_DISABLE_NN_RN = 6754; // 2 -static const uint64_t SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS = 6755; // 2 -static const uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK = 6756; // 2 -static const uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN = 6757; // 2 -static const uint64_t SH_FLD_DMA_RD_VG_RST_TMASK = 6758; // 1 -static const uint64_t SH_FLD_DMA_RD_VG_RST_TMASK_LEN = 6759; // 1 -static const uint64_t SH_FLD_DMA_READ = 6760; // 3 -static const uint64_t SH_FLD_DMA_READ_LEN = 6761; // 3 -static const uint64_t SH_FLD_DMA_STOPPED_STATE = 6762; // 32 -static const uint64_t SH_FLD_DMA_STOPPED_STATE_LEN = 6763; // 16 -static const uint64_t SH_FLD_DMA_TIMER_ENBL = 6764; // 1 -static const uint64_t SH_FLD_DMA_TIMER_REF_DIV = 6765; // 1 -static const uint64_t SH_FLD_DMA_TIMER_REF_DIV_LEN = 6766; // 1 -static const uint64_t SH_FLD_DMA_WRITE = 6767; // 3 -static const uint64_t SH_FLD_DMA_WRITE_LEN = 6768; // 2 -static const uint64_t SH_FLD_DMA_WR_DISABLE_GROUP = 6769; // 2 -static const uint64_t SH_FLD_DMA_WR_DISABLE_LN = 6770; // 2 -static const uint64_t SH_FLD_DMA_WR_DISABLE_NN_RN = 6771; // 2 -static const uint64_t SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS = 6772; // 2 -static const uint64_t SH_FLD_DMA_WR_NOT_INJ = 6773; // 1 -static const uint64_t SH_FLD_DMA_WR_NOT_INJECT = 6774; // 1 -static const uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK = 6775; // 2 -static const uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN = 6776; // 2 -static const uint64_t SH_FLD_DMA_WR_VG_RST_TMASK = 6777; // 1 -static const uint64_t SH_FLD_DMA_WR_VG_RST_TMASK_LEN = 6778; // 1 -static const uint64_t SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG = 6779; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_EMPTY = 6780; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT = 6781; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN = 6782; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS = 6783; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN = 6784; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_FULL = 6785; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS = 6786; // 1 -static const uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN = 6787; // 1 -static const uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SBE = 6788; // 1 -static const uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SP = 6789; // 1 -static const uint64_t SH_FLD_DOB01_CE = 6790; // 4 -static const uint64_t SH_FLD_DOB01_ERR = 6791; // 4 -static const uint64_t SH_FLD_DOB01_SUE = 6792; // 4 -static const uint64_t SH_FLD_DOB01_UE = 6793; // 4 -static const uint64_t SH_FLD_DOB23_CE = 6794; // 4 -static const uint64_t SH_FLD_DOB23_ERR = 6795; // 4 -static const uint64_t SH_FLD_DOB23_SUE = 6796; // 4 -static const uint64_t SH_FLD_DOB23_UE = 6797; // 4 -static const uint64_t SH_FLD_DOB45_CE = 6798; // 4 -static const uint64_t SH_FLD_DOB45_ERR = 6799; // 4 -static const uint64_t SH_FLD_DOB45_SUE = 6800; // 4 -static const uint64_t SH_FLD_DOB45_UE = 6801; // 4 -static const uint64_t SH_FLD_DOB67_CE = 6802; // 2 -static const uint64_t SH_FLD_DOB67_ERR = 6803; // 2 -static const uint64_t SH_FLD_DOB67_SUE = 6804; // 2 -static const uint64_t SH_FLD_DOB67_UE = 6805; // 2 -static const uint64_t SH_FLD_DONE = 6806; // 31 -static const uint64_t SH_FLD_DOORBELL0_C0 = 6807; // 12 -static const uint64_t SH_FLD_DOORBELL0_C1 = 6808; // 12 -static const uint64_t SH_FLD_DOORBELL1_C0 = 6809; // 12 -static const uint64_t SH_FLD_DOORBELL1_C1 = 6810; // 12 -static const uint64_t SH_FLD_DOORBELL2_C0 = 6811; // 12 -static const uint64_t SH_FLD_DOORBELL2_C1 = 6812; // 12 -static const uint64_t SH_FLD_DOORBELL3_C0 = 6813; // 12 -static const uint64_t SH_FLD_DOORBELL3_C1 = 6814; // 12 -static const uint64_t SH_FLD_DOUBLE_EPSILON_LENGTH = 6815; // 4 -static const uint64_t SH_FLD_DO_DR = 6816; // 1 -static const uint64_t SH_FLD_DO_IR = 6817; // 1 -static const uint64_t SH_FLD_DO_TAP_RESET = 6818; // 1 -static const uint64_t SH_FLD_DPLL_DCO_EMPTY = 6819; // 6 -static const uint64_t SH_FLD_DPLL_DCO_FULL = 6820; // 6 -static const uint64_t SH_FLD_DPLL_DYN_FMIN = 6821; // 6 -static const uint64_t SH_FLD_DPLL_INT = 6822; // 6 -static const uint64_t SH_FLD_DPLL_TEST_SEL = 6823; // 43 -static const uint64_t SH_FLD_DPLL_TEST_SEL_LEN = 6824; // 43 -static const uint64_t SH_FLD_DP_DLL_CAL_ERROR = 6825; // 8 -static const uint64_t SH_FLD_DP_DLL_CAL_ERROR_FINE = 6826; // 8 -static const uint64_t SH_FLD_DP_ERROR = 6827; // 8 -static const uint64_t SH_FLD_DP_ERROR_FINE = 6828; // 8 -static const uint64_t SH_FLD_DP_GOOD = 6829; // 8 -static const uint64_t SH_FLD_DQS = 6830; // 8 -static const uint64_t SH_FLD_DQS_ALIGN = 6831; // 8 -static const uint64_t SH_FLD_DQ_SEL_LANE = 6832; // 8 -static const uint64_t SH_FLD_DQ_SEL_LANE_LEN = 6833; // 8 -static const uint64_t SH_FLD_DQ_SEL_QUAD = 6834; // 8 -static const uint64_t SH_FLD_DQ_SEL_QUAD_LEN = 6835; // 8 -static const uint64_t SH_FLD_DRAM_ABIST_DONE_DC = 6836; // 43 -static const uint64_t SH_FLD_DROOP_CHAR_MODE = 6837; // 12 -static const uint64_t SH_FLD_DROOP_NOTIFY_ENABLE = 6838; // 12 -static const uint64_t SH_FLD_DROOP_PROFILE_TYPE = 6839; // 12 -static const uint64_t SH_FLD_DROOP_PROFILE_TYPE_LEN = 6840; // 12 -static const uint64_t SH_FLD_DROOP_PROTECT_DATA = 6841; // 6 -static const uint64_t SH_FLD_DROOP_PROTECT_DATA_LEN = 6842; // 6 -static const uint64_t SH_FLD_DROOP_SAMPLE_RATE = 6843; // 12 -static const uint64_t SH_FLD_DROOP_SAMPLE_RATE_LEN = 6844; // 12 -static const uint64_t SH_FLD_DROOP_TIMER_MODE = 6845; // 12 -static const uint64_t SH_FLD_DROPOUT_CHAR_MODE = 6846; // 12 -static const uint64_t SH_FLD_DROPOUT_DETECT = 6847; // 12 -static const uint64_t SH_FLD_DROPOUT_EVENT_THRESHOLD = 6848; // 12 -static const uint64_t SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN = 6849; // 12 -static const uint64_t SH_FLD_DROPOUT_INAROW_THRESHOLD = 6850; // 12 -static const uint64_t SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN = 6851; // 12 -static const uint64_t SH_FLD_DROPOUT_NOTIFY_ENABLE = 6852; // 12 -static const uint64_t SH_FLD_DROPOUT_SAMPLE = 6853; // 12 -static const uint64_t SH_FLD_DROPOUT_SAMPLE_LEN = 6854; // 12 -static const uint64_t SH_FLD_DROPOUT_SAMPLE_RATE = 6855; // 12 -static const uint64_t SH_FLD_DROPOUT_SAMPLE_RATE_LEN = 6856; // 12 -static const uint64_t SH_FLD_DROPOUT_TIMER_MODE = 6857; // 12 -static const uint64_t SH_FLD_DROP_COUNTER_FULL = 6858; // 4 -static const uint64_t SH_FLD_DROP_MASK_0_5 = 6859; // 1 -static const uint64_t SH_FLD_DROP_MASK_0_5_LEN = 6860; // 1 -static const uint64_t SH_FLD_DROP_PLS_DIV00 = 6861; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV00_LEN = 6862; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV01 = 6863; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV01_LEN = 6864; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV10 = 6865; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV10_LEN = 6866; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV11 = 6867; // 8 -static const uint64_t SH_FLD_DROP_PLS_DIV11_LEN = 6868; // 8 -static const uint64_t SH_FLD_DROP_PRIORITY_MASK = 6869; // 12 -static const uint64_t SH_FLD_DROP_PRIORITY_MASK_LEN = 6870; // 12 -static const uint64_t SH_FLD_DROP_PRIORITY_MODE = 6871; // 2 -static const uint64_t SH_FLD_DROP_PRI_DMA = 6872; // 1 -static const uint64_t SH_FLD_DROP_PRI_HPC_READ = 6873; // 1 -static const uint64_t SH_FLD_DROP_PRI_INTRP = 6874; // 1 -static const uint64_t SH_FLD_DRTM_REQ = 6875; // 5 -static const uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG = 6876; // 4 -static const uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN = 6877; // 4 -static const uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG = 6878; // 6 -static const uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN = 6879; // 6 -static const uint64_t SH_FLD_DRV_PATTERN_EN = 6880; // 1 -static const uint64_t SH_FLD_DSC1_ABORT_1 = 6881; // 1 -static const uint64_t SH_FLD_DSC1_DATA_COUNT = 6882; // 1 -static const uint64_t SH_FLD_DSC1_DATA_COUNT_1B = 6883; // 1 -static const uint64_t SH_FLD_DSC1_DATA_COUNT_1B_LEN = 6884; // 1 -static const uint64_t SH_FLD_DSC1_DATA_COUNT_LEN = 6885; // 1 -static const uint64_t SH_FLD_DSC1_HEADER_COUNT = 6886; // 1 -static const uint64_t SH_FLD_DSC1_HEADER_COUNT_1B = 6887; // 1 -static const uint64_t SH_FLD_DSC1_HEADER_COUNT_1B_LEN = 6888; // 1 -static const uint64_t SH_FLD_DSC1_HEADER_COUNT_LEN = 6889; // 1 -static const uint64_t SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING = 6890; // 1 -static const uint64_t SH_FLD_DSC1_PERMISSION_TO_SEND_1 = 6891; // 1 -static const uint64_t SH_FLD_DSC1_PIB_SLAVE_PENDING = 6892; // 1 -static const uint64_t SH_FLD_DSC1_UNUSED_24 = 6893; // 1 -static const uint64_t SH_FLD_DSC1_UNUSED_27 = 6894; // 1 -static const uint64_t SH_FLD_DSC1_XDN_1 = 6895; // 1 -static const uint64_t SH_FLD_DSC1_XUP_1 = 6896; // 1 -static const uint64_t SH_FLD_DSC2_ABORT_2 = 6897; // 1 -static const uint64_t SH_FLD_DSC2_DATA_COUNT = 6898; // 1 -static const uint64_t SH_FLD_DSC2_DATA_COUNT_2B = 6899; // 1 -static const uint64_t SH_FLD_DSC2_DATA_COUNT_2B_LEN = 6900; // 1 -static const uint64_t SH_FLD_DSC2_DATA_COUNT_LEN = 6901; // 1 -static const uint64_t SH_FLD_DSC2_HEADER_COUNT = 6902; // 1 -static const uint64_t SH_FLD_DSC2_HEADER_COUNT_2B = 6903; // 1 -static const uint64_t SH_FLD_DSC2_HEADER_COUNT_2B_LEN = 6904; // 1 -static const uint64_t SH_FLD_DSC2_HEADER_COUNT_LEN = 6905; // 1 -static const uint64_t SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING = 6906; // 1 -static const uint64_t SH_FLD_DSC2_PERMISSION_TO_SEND_2 = 6907; // 1 -static const uint64_t SH_FLD_DSC2_PIB_SLAVE_PENDING = 6908; // 1 -static const uint64_t SH_FLD_DSC2_UNUSED_24 = 6909; // 1 -static const uint64_t SH_FLD_DSC2_UNUSED_27 = 6910; // 1 -static const uint64_t SH_FLD_DSC2_XDN_2 = 6911; // 1 -static const uint64_t SH_FLD_DSC2_XUP_2 = 6912; // 1 -static const uint64_t SH_FLD_DSM_CMD_PE_HOLD_OUT = 6913; // 8 -static const uint64_t SH_FLD_DSM_PE = 6914; // 8 -static const uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL = 6915; // 4 -static const uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN = 6916; // 4 -static const uint64_t SH_FLD_DS_TIMEOUT_SEL = 6917; // 4 -static const uint64_t SH_FLD_DS_TIMEOUT_SEL_LEN = 6918; // 4 -static const uint64_t SH_FLD_DTS_ENABLE_L1 = 6919; // 43 -static const uint64_t SH_FLD_DTS_ENABLE_L1_LEN = 6920; // 43 -static const uint64_t SH_FLD_DTS_READ_SEL = 6921; // 43 -static const uint64_t SH_FLD_DTS_READ_SEL_LEN = 6922; // 43 -static const uint64_t SH_FLD_DTS_SAMPLE_ENA = 6923; // 43 -static const uint64_t SH_FLD_DTS_TRIGGER = 6924; // 43 -static const uint64_t SH_FLD_DTS_TRIGGER_SEL = 6925; // 43 -static const uint64_t SH_FLD_DW0_ERR_TYPE = 6926; // 16 -static const uint64_t SH_FLD_DW0_ERR_TYPE_LEN = 6927; // 16 -static const uint64_t SH_FLD_DW0_SYNDROME = 6928; // 16 -static const uint64_t SH_FLD_DW0_SYNDROME_LEN = 6929; // 16 -static const uint64_t SH_FLD_DW1_ERR_TYPE = 6930; // 16 -static const uint64_t SH_FLD_DW1_ERR_TYPE_LEN = 6931; // 16 -static const uint64_t SH_FLD_DW1_SYNDROME = 6932; // 16 -static const uint64_t SH_FLD_DW1_SYNDROME_LEN = 6933; // 16 -static const uint64_t SH_FLD_DW2_ERR_TYPE = 6934; // 16 -static const uint64_t SH_FLD_DW2_ERR_TYPE_LEN = 6935; // 16 -static const uint64_t SH_FLD_DW2_SYNDROME = 6936; // 16 -static const uint64_t SH_FLD_DW2_SYNDROME_LEN = 6937; // 16 -static const uint64_t SH_FLD_DW3_ERR_TYPE = 6938; // 16 -static const uint64_t SH_FLD_DW3_ERR_TYPE_LEN = 6939; // 16 -static const uint64_t SH_FLD_DW3_SYNDROME = 6940; // 16 -static const uint64_t SH_FLD_DW3_SYNDROME_LEN = 6941; // 16 -static const uint64_t SH_FLD_DW_TYPE = 6942; // 12 -static const uint64_t SH_FLD_DW_TYPE_LEN = 6943; // 12 -static const uint64_t SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED = 6944; // 8 -static const uint64_t SH_FLD_DYNAMIC_REPAIR_ERROR = 6945; // 8 -static const uint64_t SH_FLD_DYNAMIC_SPARE_DEPLOYED = 6946; // 8 -static const uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT = 6947; // 8 -static const uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT_LEN = 6948; // 8 -static const uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 6949; // 8 -static const uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 6950; // 8 -static const uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL = 6951; // 4 -static const uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 6952; // 4 -static const uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 6953; // 8 -static const uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 6954; // 8 -static const uint64_t SH_FLD_DYN_RECAL_SUSPEND = 6955; // 4 -static const uint64_t SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG = 6956; // 4 -static const uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX = 6957; // 4 -static const uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN = 6958; // 4 -static const uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX = 6959; // 4 -static const uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN = 6960; // 4 -static const uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR1 = 6961; // 4 -static const uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR2 = 6962; // 4 -static const uint64_t SH_FLD_DYN_RPR_COMPLETE_GCRMSG = 6963; // 4 -static const uint64_t SH_FLD_DYN_RPR_DISABLE = 6964; // 4 -static const uint64_t SH_FLD_DYN_RPR_DISABLE2 = 6965; // 4 -static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 6966; // 4 -static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 6967; // 4 -static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 6968; // 4 -static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 6969; // 4 -static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION = 6970; // 4 -static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN = 6971; // 4 -static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE = 6972; // 4 -static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 6973; // 4 -static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION = 6974; // 4 -static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN = 6975; // 4 -static const uint64_t SH_FLD_DYN_RPR_IP_GCRMSG = 6976; // 4 -static const uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG = 6977; // 4 -static const uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN = 6978; // 4 -static const uint64_t SH_FLD_DYN_RPR_REQ_GCRMSG = 6979; // 4 -static const uint64_t SH_FLD_DYN_RPR_REQ_MANUAL = 6980; // 4 -static const uint64_t SH_FLD_DYN_RPR_SM_MANUAL = 6981; // 4 -static const uint64_t SH_FLD_DYN_ST_FREQ_MULT = 6982; // 2 -static const uint64_t SH_FLD_DYN_ST_FREQ_MULT_LEN = 6983; // 1 -static const uint64_t SH_FLD_DYN_ST_MODE_EN = 6984; // 1 -static const uint64_t SH_FLD_DYN_ST_MODE_HANGP_EN = 6985; // 1 -static const uint64_t SH_FLD_DYN_ST_MODE_THRESHOLD = 6986; // 2 -static const uint64_t SH_FLD_DYN_ST_MODE_THRESHOLD_LEN = 6987; // 2 -static const uint64_t SH_FLD_D_BIT_MAP = 6988; // 8 -static const uint64_t SH_FLD_D_BIT_MAP_LEN = 6989; // 8 -static const uint64_t SH_FLD_EAINJ = 6990; // 1 -static const uint64_t SH_FLD_EARLY_REQ = 6991; // 8 -static const uint64_t SH_FLD_EARLY_REQ_ERR_MASK = 6992; // 8 -static const uint64_t SH_FLD_EARLY_REQ_SOURCE = 6993; // 8 -static const uint64_t SH_FLD_EARLY_REQ_SOURCE_LEN = 6994; // 8 -static const uint64_t SH_FLD_EA_RANGE_CHK_DIS = 6995; // 1 -static const uint64_t SH_FLD_EBUS_ENABLE_0_15 = 6996; // 1 -static const uint64_t SH_FLD_EBUS_ENABLE_0_15_LEN = 6997; // 1 -static const uint64_t SH_FLD_ECC = 6998; // 3 -static const uint64_t SH_FLD_ECCCHK_DISABLE_0 = 6999; // 1 -static const uint64_t SH_FLD_ECCCHK_DISABLE_1 = 7000; // 1 -static const uint64_t SH_FLD_ECCCHK_DISABLE_2 = 7001; // 1 -static const uint64_t SH_FLD_ECCCHK_DISABLE_3 = 7002; // 1 -static const uint64_t SH_FLD_ECCGEN = 7003; // 8 -static const uint64_t SH_FLD_ECC_CE = 7004; // 3 -static const uint64_t SH_FLD_ECC_CHK_DISABLE = 7005; // 1 -static const uint64_t SH_FLD_ECC_CLEAR = 7006; // 2 -static const uint64_t SH_FLD_ECC_CONFIG_ERROR_0 = 7007; // 1 -static const uint64_t SH_FLD_ECC_CONFIG_ERROR_1 = 7008; // 1 -static const uint64_t SH_FLD_ECC_CONFIG_ERROR_2 = 7009; // 1 -static const uint64_t SH_FLD_ECC_CONFIG_ERROR_3 = 7010; // 1 -static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_0 = 7011; // 1 -static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_1 = 7012; // 1 -static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_2 = 7013; // 1 -static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_3 = 7014; // 1 -static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_FACES = 7015; // 1 -static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_PIB = 7016; // 1 -static const uint64_t SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 7017; // 8 -static const uint64_t SH_FLD_ECC_CORRECT_DIS = 7018; // 16 -static const uint64_t SH_FLD_ECC_CTL_AF_PERR = 7019; // 8 -static const uint64_t SH_FLD_ECC_CTL_CMPMODE_ERR = 7020; // 8 -static const uint64_t SH_FLD_ECC_CTL_PCTL_PERR = 7021; // 8 -static const uint64_t SH_FLD_ECC_CTL_RPTR_PERR = 7022; // 8 -static const uint64_t SH_FLD_ECC_CTL_SCH_PERR = 7023; // 8 -static const uint64_t SH_FLD_ECC_CTL_TCHN_PERR = 7024; // 8 -static const uint64_t SH_FLD_ECC_CTL_TGST_PERR = 7025; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT = 7026; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT_LEN = 7027; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_ENABLE = 7028; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT = 7029; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT_LEN = 7030; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT = 7031; // 8 -static const uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT_LEN = 7032; // 8 -static const uint64_t SH_FLD_ECC_DETECT_DIS = 7033; // 16 -static const uint64_t SH_FLD_ECC_ENABLE = 7034; // 6 -static const uint64_t SH_FLD_ECC_ENABLE_0 = 7035; // 1 -static const uint64_t SH_FLD_ECC_ENABLE_1 = 7036; // 1 -static const uint64_t SH_FLD_ECC_ENABLE_2 = 7037; // 1 -static const uint64_t SH_FLD_ECC_ENABLE_3 = 7038; // 1 -static const uint64_t SH_FLD_ECC_ERROR_ADDR = 7039; // 2 -static const uint64_t SH_FLD_ECC_ERROR_ADDR_LEN = 7040; // 2 -static const uint64_t SH_FLD_ECC_ERROR_COUNT = 7041; // 2 -static const uint64_t SH_FLD_ECC_ERROR_COUNT_LEN = 7042; // 2 -static const uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL = 7043; // 4 -static const uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN = 7044; // 4 -static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA = 7045; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ = 7046; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP = 7047; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED = 7048; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN = 7049; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL = 7050; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN = 7051; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SELECTION = 7052; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SELECTION_LEN = 7053; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA = 7054; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ = 7055; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL = 7056; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP = 7057; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED = 7058; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN = 7059; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA = 7060; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ = 7061; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL = 7062; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN = 7063; // 1 -static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP = 7064; // 1 -static const uint64_t SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 7065; // 8 -static const uint64_t SH_FLD_ECC_INJECT_ERR = 7066; // 16 -static const uint64_t SH_FLD_ECC_INJECT_TYPE = 7067; // 16 -static const uint64_t SH_FLD_ECC_LEN = 7068; // 3 -static const uint64_t SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 7069; // 2 -static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_0 = 7070; // 8 -static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_1 = 7071; // 8 -static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_2 = 7072; // 8 -static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_3 = 7073; // 8 -static const uint64_t SH_FLD_ECC_SYNDROME = 7074; // 2 -static const uint64_t SH_FLD_ECC_SYNDROME_LEN = 7075; // 2 -static const uint64_t SH_FLD_ECC_S_BIT_ERROR = 7076; // 1 -static const uint64_t SH_FLD_ECC_UE = 7077; // 3 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_0 = 7078; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_1 = 7079; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_2 = 7080; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_3 = 7081; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_FACES = 7082; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_PIB = 7083; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERR_FACES = 7084; // 1 -static const uint64_t SH_FLD_ECC_UNCORRECTED_ERR_PIB = 7085; // 1 -static const uint64_t SH_FLD_ECC_WAT_ACTION_SELECT = 7086; // 8 -static const uint64_t SH_FLD_ECC_WAT_ENABLE = 7087; // 8 -static const uint64_t SH_FLD_ECC_WAT_SOURCE = 7088; // 8 -static const uint64_t SH_FLD_ECC_WAT_SOURCE_LEN = 7089; // 8 -static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE = 7090; // 8 -static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN = 7091; // 8 -static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT = 7092; // 8 -static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 7093; // 8 -static const uint64_t SH_FLD_ECHO_DELAY_CYCLES = 7094; // 2 -static const uint64_t SH_FLD_ECHO_DELAY_CYCLES_LEN = 7095; // 2 -static const uint64_t SH_FLD_ECRESP_HASH_MODE = 7096; // 4 -static const uint64_t SH_FLD_EDGE_TRIGGER_MODE1 = 7097; // 86 -static const uint64_t SH_FLD_EDGE_TRIGGER_MODE2 = 7098; // 86 -static const uint64_t SH_FLD_EDPL_LANE_ID = 7099; // 5 -static const uint64_t SH_FLD_EDPL_RATE = 7100; // 5 -static const uint64_t SH_FLD_EDPL_RATE_LEN = 7101; // 5 -static const uint64_t SH_FLD_EDR = 7102; // 21 -static const uint64_t SH_FLD_EDRAM_PGATE = 7103; // 6 -static const uint64_t SH_FLD_EDRAM_SEQUENCE = 7104; // 6 -static const uint64_t SH_FLD_EDR_LEN = 7105; // 21 -static const uint64_t SH_FLD_EFTCOMP_MAX_INRD = 7106; // 1 -static const uint64_t SH_FLD_EFTCOMP_MAX_INRD_LEN = 7107; // 1 -static const uint64_t SH_FLD_EFTDECOMP_MAX_INRD = 7108; // 1 -static const uint64_t SH_FLD_EFTDECOMP_MAX_INRD_LEN = 7109; // 1 -static const uint64_t SH_FLD_EFT_COMP_PREFETCH_ENABLE = 7110; // 1 -static const uint64_t SH_FLD_EFT_DECOMP_PREFETCH_ENABLE = 7111; // 1 -static const uint64_t SH_FLD_EFT_MUX_SELECT = 7112; // 1 -static const uint64_t SH_FLD_EFT_MUX_SELECT_LEN = 7113; // 1 -static const uint64_t SH_FLD_EFT_SPBC_ENABLE = 7114; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT10 = 7115; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT11 = 7116; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT4 = 7117; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT5 = 7118; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT6 = 7119; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT7 = 7120; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT8 = 7121; // 1 -static const uint64_t SH_FLD_EG_CERR_BIT9 = 7122; // 1 -static const uint64_t SH_FLD_EG_CERR_RESET = 7123; // 1 -static const uint64_t SH_FLD_EG_CERR_UNUSEDBITS = 7124; // 1 -static const uint64_t SH_FLD_EG_CERR_UNUSEDBITS_LEN = 7125; // 1 -static const uint64_t SH_FLD_EG_ECC_CE_ERROR = 7126; // 2 -static const uint64_t SH_FLD_EG_ECC_SUE_ERROR = 7127; // 2 -static const uint64_t SH_FLD_EG_ECC_UE_ERROR = 7128; // 2 -static const uint64_t SH_FLD_EG_LOGIC_HW_ERROR = 7129; // 2 -static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI = 7130; // 1 -static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN = 7131; // 1 -static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO = 7132; // 1 -static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN = 7133; // 1 -static const uint64_t SH_FLD_EG_TRACE_INT_DATA_HI = 7134; // 2 -static const uint64_t SH_FLD_EG_TRACE_INT_DATA_LO = 7135; // 2 -static const uint64_t SH_FLD_EG_TRACE_INT_TRIG_01 = 7136; // 2 -static const uint64_t SH_FLD_EG_TRACE_INT_TRIG_23 = 7137; // 2 -static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01 = 7138; // 1 -static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN = 7139; // 1 -static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23 = 7140; // 1 -static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN = 7141; // 1 -static const uint64_t SH_FLD_EICR_PE = 7142; // 8 -static const uint64_t SH_FLD_ELEVEN_LANE_MODE = 7143; // 2 -static const uint64_t SH_FLD_EMERGENCY_M = 7144; // 8 -static const uint64_t SH_FLD_EMERGENCY_M_LEN = 7145; // 8 -static const uint64_t SH_FLD_EMERGENCY_N = 7146; // 8 -static const uint64_t SH_FLD_EMERGENCY_N_LEN = 7147; // 8 -static const uint64_t SH_FLD_EMERGENCY_THROTTLE = 7148; // 16 -static const uint64_t SH_FLD_EMER_THROTTLE_IP = 7149; // 8 -static const uint64_t SH_FLD_EN = 7150; // 53 -static const uint64_t SH_FLD_ENA = 7151; // 1 -static const uint64_t SH_FLD_ENABLE = 7152; // 259 -static const uint64_t SH_FLD_ENABLE_0 = 7153; // 5 -static const uint64_t SH_FLD_ENABLE_0_7 = 7154; // 1 -static const uint64_t SH_FLD_ENABLE_0_7_LEN = 7155; // 1 -static const uint64_t SH_FLD_ENABLE_0_LEN = 7156; // 5 -static const uint64_t SH_FLD_ENABLE_1 = 7157; // 5 -static const uint64_t SH_FLD_ENABLE_1_LEN = 7158; // 5 -static const uint64_t SH_FLD_ENABLE_2 = 7159; // 5 -static const uint64_t SH_FLD_ENABLE_2_LEN = 7160; // 5 -static const uint64_t SH_FLD_ENABLE_3 = 7161; // 5 -static const uint64_t SH_FLD_ENABLE_3_LEN = 7162; // 5 -static const uint64_t SH_FLD_ENABLE_4 = 7163; // 5 -static const uint64_t SH_FLD_ENABLE_4_LEN = 7164; // 5 -static const uint64_t SH_FLD_ENABLE_5 = 7165; // 5 -static const uint64_t SH_FLD_ENABLE_5_LEN = 7166; // 5 -static const uint64_t SH_FLD_ENABLE_6 = 7167; // 5 -static const uint64_t SH_FLD_ENABLE_64_128B_READ = 7168; // 4 -static const uint64_t SH_FLD_ENABLE_6_LEN = 7169; // 5 -static const uint64_t SH_FLD_ENABLE_7 = 7170; // 5 -static const uint64_t SH_FLD_ENABLE_7_LEN = 7171; // 5 -static const uint64_t SH_FLD_ENABLE_AGGRESSIVE_BUSY = 7172; // 8 -static const uint64_t SH_FLD_ENABLE_APO_HANG = 7173; // 4 -static const uint64_t SH_FLD_ENABLE_AUX_PORT_UNUSED = 7174; // 2 -static const uint64_t SH_FLD_ENABLE_BER_TEST = 7175; // 4 -static const uint64_t SH_FLD_ENABLE_BUSY_COUNTERS = 7176; // 8 -static const uint64_t SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 7177; // 4 -static const uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND = 7178; // 4 -static const uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND = 7179; // 4 -static const uint64_t SH_FLD_ENABLE_CENTAUR_SYNC = 7180; // 4 -static const uint64_t SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND = 7181; // 4 -static const uint64_t SH_FLD_ENABLE_CLEAN = 7182; // 8 -static const uint64_t SH_FLD_ENABLE_CLIB_HANG = 7183; // 4 -static const uint64_t SH_FLD_ENABLE_CLR_ERR_CMD = 7184; // 1 -static const uint64_t SH_FLD_ENABLE_CM_COARSE_CAL = 7185; // 6 -static const uint64_t SH_FLD_ENABLE_CM_FINE_CAL = 7186; // 6 -static const uint64_t SH_FLD_ENABLE_CQ_PMU_COUNTING = 7187; // 1 -static const uint64_t SH_FLD_ENABLE_CQ_TRACE = 7188; // 1 -static const uint64_t SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY = 7189; // 4 -static const uint64_t SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 7190; // 6 -static const uint64_t SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 7191; // 6 -static const uint64_t SH_FLD_ENABLE_CTLE_COARSE_CAL = 7192; // 6 -static const uint64_t SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL = 7193; // 2 -static const uint64_t SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY = 7194; // 4 -static const uint64_t SH_FLD_ENABLE_DAC_H1_CAL = 7195; // 6 -static const uint64_t SH_FLD_ENABLE_DAC_H1_TO_A_CAL = 7196; // 4 -static const uint64_t SH_FLD_ENABLE_DDC = 7197; // 6 -static const uint64_t SH_FLD_ENABLE_DEBUG_BUS = 7198; // 1 -static const uint64_t SH_FLD_ENABLE_DFE_H1_CAL = 7199; // 6 -static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_CAL = 7200; // 4 -static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP = 7201; // 4 -static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 7202; // 4 -static const uint64_t SH_FLD_ENABLE_DFE_H6_H12_FAST_MODE = 7203; // 4 -static const uint64_t SH_FLD_ENABLE_DFE_VOLTAGE_MODE = 7204; // 4 -static const uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 7205; // 4 -static const uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 7206; // 4 -static const uint64_t SH_FLD_ENABLE_DONE_SIGNALING = 7207; // 4 -static const uint64_t SH_FLD_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS = 7208; // 6 -static const uint64_t SH_FLD_ENABLE_DYNAMIC_PF_USAGE = 7209; // 8 -static const uint64_t SH_FLD_ENABLE_DYNAMIC_WR_USAGE = 7210; // 8 -static const uint64_t SH_FLD_ENABLE_EG_PMU_COUNTING = 7211; // 1 -static const uint64_t SH_FLD_ENABLE_EG_TRACE = 7212; // 1 -static const uint64_t SH_FLD_ENABLE_EMER_THROTTLE = 7213; // 4 -static const uint64_t SH_FLD_ENABLE_ENABLE_CRESP_PE = 7214; // 4 -static const uint64_t SH_FLD_ENABLE_ERR_INJ = 7215; // 5 -static const uint64_t SH_FLD_ENABLE_FINAL_L2U_ADJ = 7216; // 4 -static const uint64_t SH_FLD_ENABLE_FIR_HOST_ATTN = 7217; // 4 -static const uint64_t SH_FLD_ENABLE_FIR_SPEC_ATTN = 7218; // 4 -static const uint64_t SH_FLD_ENABLE_FMAX_TARGET = 7219; // 6 -static const uint64_t SH_FLD_ENABLE_FMIN_TARGET = 7220; // 6 -static const uint64_t SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 7221; // 6 -static const uint64_t SH_FLD_ENABLE_GCR_OFL_BUFF = 7222; // 4 -static const uint64_t SH_FLD_ENABLE_GLB_PULSE = 7223; // 1 -static const uint64_t SH_FLD_ENABLE_GLOBAL_RUN = 7224; // 2 -static const uint64_t SH_FLD_ENABLE_H1AP_TWEAK = 7225; // 6 -static const uint64_t SH_FLD_ENABLE_HW_ERROR_RECOVERY = 7226; // 5 -static const uint64_t SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL = 7227; // 6 -static const uint64_t SH_FLD_ENABLE_IN_PMU_COUNTING = 7228; // 1 -static const uint64_t SH_FLD_ENABLE_IN_TRACE = 7229; // 1 -static const uint64_t SH_FLD_ENABLE_IPOLL_AND_DMA = 7230; // 3 -static const uint64_t SH_FLD_ENABLE_JUMP_PROTECT = 7231; // 6 -static const uint64_t SH_FLD_ENABLE_JUMP_TARGET_UPDATE = 7232; // 6 -static const uint64_t SH_FLD_ENABLE_LEN = 7233; // 47 -static const uint64_t SH_FLD_ENABLE_MEMORY_BACKING = 7234; // 6 -static const uint64_t SH_FLD_ENABLE_MIRROR_HANG = 7235; // 4 -static const uint64_t SH_FLD_ENABLE_NONMIRROR_HANG = 7236; // 4 -static const uint64_t SH_FLD_ENABLE_OP_HIT_ERROR = 7237; // 4 -static const uint64_t SH_FLD_ENABLE_PARITY_CHECK = 7238; // 3 -static const uint64_t SH_FLD_ENABLE_PB_SWITCH_AB = 7239; // 1 -static const uint64_t SH_FLD_ENABLE_PB_SWITCH_CD = 7240; // 1 -static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_EXTREME_DROOP = 7241; // 6 -static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS = 7242; // 6 -static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT = 7243; // 6 -static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_LARGE_DROOP = 7244; // 6 -static const uint64_t SH_FLD_ENABLE_PECE = 7245; // 24 -static const uint64_t SH_FLD_ENABLE_PFETS_UPON_IVRM_DROPOUT = 7246; // 6 -static const uint64_t SH_FLD_ENABLE_PF_DROP_CMDLIST = 7247; // 4 -static const uint64_t SH_FLD_ENABLE_PF_DROP_SRQ = 7248; // 4 -static const uint64_t SH_FLD_ENABLE_PREFETCH_PROMOTE = 7249; // 4 -static const uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC = 7250; // 8 -static const uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN = 7251; // 8 -static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TOD = 7252; // 1 -static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER = 7253; // 1 -static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 7254; // 1 -static const uint64_t SH_FLD_ENABLE_REDUCE_SPEC = 7255; // 24 -static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_DISP = 7256; // 8 -static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_NSQ = 7257; // 8 -static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_SQ = 7258; // 8 -static const uint64_t SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS = 7259; // 3 -static const uint64_t SH_FLD_ENABLE_REMAP = 7260; // 1 -static const uint64_t SH_FLD_ENABLE_RESULT_CHECK = 7261; // 4 -static const uint64_t SH_FLD_ENABLE_RG_PMU_COUNTING = 7262; // 1 -static const uint64_t SH_FLD_ENABLE_RG_TRACE = 7263; // 1 -static const uint64_t SH_FLD_ENABLE_SCRD_FR_RXRF = 7264; // 1 -static const uint64_t SH_FLD_ENABLE_SCWR_TO_RXRF = 7265; // 1 -static const uint64_t SH_FLD_ENABLE_SCWR_TO_TXRF = 7266; // 1 -static const uint64_t SH_FLD_ENABLE_STREAMING_MODE = 7267; // 2 -static const uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG0 = 7268; // 1 -static const uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG1 = 7269; // 1 -static const uint64_t SH_FLD_ENABLE_TTYPE_DECODE = 7270; // 2 -static const uint64_t SH_FLD_ENABLE_VGA_AMAX_MODE = 7271; // 6 -static const uint64_t SH_FLD_ENABLE_VGA_CAL = 7272; // 6 -static const uint64_t SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL = 7273; // 2 -static const uint64_t SH_FLD_ENABLE_VITL_ALIGN_CHECK = 7274; // 43 -static const uint64_t SH_FLD_ENABLE_WAT = 7275; // 4 -static const uint64_t SH_FLD_ENABLE_WC_TRACE = 7276; // 1 -static const uint64_t SH_FLD_ENABLE_ZCAL = 7277; // 8 -static const uint64_t SH_FLD_ENA_COARSE_RD = 7278; // 8 -static const uint64_t SH_FLD_ENA_CUSTOM_RD = 7279; // 8 -static const uint64_t SH_FLD_ENA_CUSTOM_WR = 7280; // 8 -static const uint64_t SH_FLD_ENA_DIGITAL_EYE = 7281; // 8 -static const uint64_t SH_FLD_ENA_DQS_ALIGN = 7282; // 16 -static const uint64_t SH_FLD_ENA_INITIAL_COARSE_WR = 7283; // 8 -static const uint64_t SH_FLD_ENA_INITIAL_PAT_WR = 7284; // 8 -static const uint64_t SH_FLD_ENA_RANK = 7285; // 8 -static const uint64_t SH_FLD_ENA_RANK_LEN = 7286; // 8 -static const uint64_t SH_FLD_ENA_RANK_PAIR = 7287; // 16 -static const uint64_t SH_FLD_ENA_RANK_PAIR_LEN = 7288; // 16 -static const uint64_t SH_FLD_ENA_RDCLK_ALIGN = 7289; // 16 -static const uint64_t SH_FLD_ENA_READ_CTR = 7290; // 16 -static const uint64_t SH_FLD_ENA_SYSCLK_ALIGN = 7291; // 8 -static const uint64_t SH_FLD_ENA_WRITE_CTR = 7292; // 8 -static const uint64_t SH_FLD_ENA_WR_LEVEL = 7293; // 8 -static const uint64_t SH_FLD_ENA_ZCAL = 7294; // 8 -static const uint64_t SH_FLD_ENC_BUS_LANE2RPR_MANUAL = 7295; // 4 -static const uint64_t SH_FLD_ENC_BUS_LANE2RPR_MANUAL_LEN = 7296; // 4 -static const uint64_t SH_FLD_END = 7297; // 100 -static const uint64_t SH_FLD_ENDABLE_PMU_CNT_RESET = 7298; // 1 -static const uint64_t SH_FLD_ENDPOINTS = 7299; // 1 -static const uint64_t SH_FLD_END_LANE_ID = 7300; // 8 -static const uint64_t SH_FLD_END_LANE_ID_LEN = 7301; // 8 -static const uint64_t SH_FLD_END_LEN = 7302; // 36 -static const uint64_t SH_FLD_ENH_MODE_0 = 7303; // 1 -static const uint64_t SH_FLD_ENH_MODE_1 = 7304; // 1 -static const uint64_t SH_FLD_ENH_MODE_2 = 7305; // 1 -static const uint64_t SH_FLD_ENH_MODE_3 = 7306; // 1 -static const uint64_t SH_FLD_ENOP = 7307; // 43 -static const uint64_t SH_FLD_ENOP_FORCE_SG = 7308; // 43 -static const uint64_t SH_FLD_ENOP_LEN = 7309; // 43 -static const uint64_t SH_FLD_ENOP_WAIT = 7310; // 43 -static const uint64_t SH_FLD_ENOP_WAIT_LEN = 7311; // 43 -static const uint64_t SH_FLD_ENTRIES = 7312; // 1 -static const uint64_t SH_FLD_ENTRIES_LEN = 7313; // 1 -static const uint64_t SH_FLD_ENTRY = 7314; // 3 -static const uint64_t SH_FLD_ENTRY_LEN = 7315; // 3 -static const uint64_t SH_FLD_ENTRY_SEL_0_5 = 7316; // 1 -static const uint64_t SH_FLD_ENTRY_SEL_0_5_LEN = 7317; // 1 -static const uint64_t SH_FLD_EN_64_128_PB_READ = 7318; // 8 -static const uint64_t SH_FLD_EN_ALT_CR = 7319; // 8 -static const uint64_t SH_FLD_EN_ALT_ECR_ERR = 7320; // 8 -static const uint64_t SH_FLD_EN_ALT_ECR_NO_ERR = 7321; // 8 -static const uint64_t SH_FLD_EN_ATTN = 7322; // 24 -static const uint64_t SH_FLD_EN_CHARB_CMD_STALL = 7323; // 8 -static const uint64_t SH_FLD_EN_CHARB_MERGE_STALL = 7324; // 8 -static const uint64_t SH_FLD_EN_CHARB_RRQ_STALL = 7325; // 8 -static const uint64_t SH_FLD_EN_CHARB_STALL = 7326; // 4 -static const uint64_t SH_FLD_EN_CHARB_WRQ_STALL = 7327; // 8 -static const uint64_t SH_FLD_EN_DBG = 7328; // 4 -static const uint64_t SH_FLD_EN_DROP_PLS_F_FULL = 7329; // 8 -static const uint64_t SH_FLD_EN_EVENT_COUNT = 7330; // 1 -static const uint64_t SH_FLD_EN_FULL_SPEED = 7331; // 16 -static const uint64_t SH_FLD_EN_INSTRUC_TRACE = 7332; // 24 -static const uint64_t SH_FLD_EN_INTR_ADDR = 7333; // 16 -static const uint64_t SH_FLD_EN_MARKER_ACK = 7334; // 1 -static const uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION = 7335; // 1 -static const uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN = 7336; // 1 -static const uint64_t SH_FLD_EN_PF_CONF_RETRY = 7337; // 8 -static const uint64_t SH_FLD_EN_POLL_BACKOFF = 7338; // 1 -static const uint64_t SH_FLD_EN_RANDOM_BACKOFF = 7339; // 1 -static const uint64_t SH_FLD_EN_RESET_DD2_FIX_DIS = 7340; // 8 -static const uint64_t SH_FLD_EN_RESET_WR_DELAY_WL = 7341; // 8 -static const uint64_t SH_FLD_EN_RISCTRACE = 7342; // 1 -static const uint64_t SH_FLD_EN_SECOND_WRBUF = 7343; // 1 -static const uint64_t SH_FLD_EN_SLV_FAIRNESS = 7344; // 1 -static const uint64_t SH_FLD_EN_SPEC_CILD_EQD = 7345; // 1 -static const uint64_t SH_FLD_EN_SPEC_CILD_IVE = 7346; // 1 -static const uint64_t SH_FLD_EN_SPEC_CILD_VPC_HW = 7347; // 1 -static const uint64_t SH_FLD_EN_SPEC_CILD_VPC_SW = 7348; // 1 -static const uint64_t SH_FLD_EN_TRACE_EXTRA = 7349; // 16 -static const uint64_t SH_FLD_EN_TRACE_FULL_IVA = 7350; // 1 -static const uint64_t SH_FLD_EN_TRACE_STALL = 7351; // 16 -static const uint64_t SH_FLD_EN_WAIT_CYCLES = 7352; // 16 -static const uint64_t SH_FLD_EN_WT4CR_EPS_ON_LCO = 7353; // 12 -static const uint64_t SH_FLD_EN_WT4CR_EXTENDED_MODE = 7354; // 12 -static const uint64_t SH_FLD_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD = 7355; // 2 -static const uint64_t SH_FLD_EPOCH_TEST_VECTOR = 7356; // 2 -static const uint64_t SH_FLD_EPOCH_TEST_VECTOR_LEN = 7357; // 2 -static const uint64_t SH_FLD_EPOCH_VALUE = 7358; // 2 -static const uint64_t SH_FLD_EPOCH_VALUE_LEN = 7359; // 2 -static const uint64_t SH_FLD_EPS_CNT_USE_DIVIDER_EN = 7360; // 12 -static const uint64_t SH_FLD_EPS_DIVIDER_MODE = 7361; // 12 -static const uint64_t SH_FLD_EPS_DIVIDER_MODE_LEN = 7362; // 12 -static const uint64_t SH_FLD_EPS_MODE_SEL = 7363; // 12 -static const uint64_t SH_FLD_EPS_STEP_MODE = 7364; // 12 -static const uint64_t SH_FLD_EPS_STEP_MODE_LEN = 7365; // 12 -static const uint64_t SH_FLD_EQC_CILOAD = 7366; // 1 -static const uint64_t SH_FLD_EQC_CILOAD_LEN = 7367; // 1 -static const uint64_t SH_FLD_EQC_CISTORE = 7368; // 1 -static const uint64_t SH_FLD_EQC_CISTORE_LEN = 7369; // 1 -static const uint64_t SH_FLD_EQC_DMA = 7370; // 1 -static const uint64_t SH_FLD_EQC_DMA_LEN = 7371; // 1 -static const uint64_t SH_FLD_EQC_EOI_EQP = 7372; // 1 -static const uint64_t SH_FLD_EQC_EOI_EQP_LEN = 7373; // 1 -static const uint64_t SH_FLD_EQC_EOI_ESBE = 7374; // 1 -static const uint64_t SH_FLD_EQC_EOI_ESBE_LEN = 7375; // 1 -static const uint64_t SH_FLD_EQD_BLOCK = 7376; // 1 -static const uint64_t SH_FLD_EQD_BLOCK_LEN = 7377; // 1 -static const uint64_t SH_FLD_EQD_DMA_READ = 7378; // 1 -static const uint64_t SH_FLD_EQD_DMA_READ_LEN = 7379; // 1 -static const uint64_t SH_FLD_EQD_DMA_WRITE = 7380; // 1 -static const uint64_t SH_FLD_EQD_DMA_WRITE_LEN = 7381; // 1 -static const uint64_t SH_FLD_EQD_INDEX = 7382; // 1 -static const uint64_t SH_FLD_EQD_INDEX_LEN = 7383; // 1 -static const uint64_t SH_FLD_EQ_POST = 7384; // 1 -static const uint64_t SH_FLD_EQ_POST_LEN = 7385; // 1 -static const uint64_t SH_FLD_ERAT_ARRAY_CE = 7386; // 1 -static const uint64_t SH_FLD_ERAT_ARRAY_PE = 7387; // 1 -static const uint64_t SH_FLD_ERAT_ARRAY_SUE = 7388; // 1 -static const uint64_t SH_FLD_ERAT_ARRAY_UE = 7389; // 1 -static const uint64_t SH_FLD_ERAT_CICO_HANG = 7390; // 1 -static const uint64_t SH_FLD_ERAT_CNTRL_ERR = 7391; // 1 -static const uint64_t SH_FLD_ERAT_DATA_POLL_SCALE = 7392; // 1 -static const uint64_t SH_FLD_ERAT_DATA_POLL_SCALE_LEN = 7393; // 1 -static const uint64_t SH_FLD_ERAT_LOCAL_CSTOP = 7394; // 1 -static const uint64_t SH_FLD_ERAT_MUX_SELECT = 7395; // 1 -static const uint64_t SH_FLD_ERAT_MUX_SELECT_LEN = 7396; // 1 -static const uint64_t SH_FLD_ERR = 7397; // 24 -static const uint64_t SH_FLD_ERR0_REG_DP16 = 7398; // 8 -static const uint64_t SH_FLD_ERR0_REG_DP16_LEN = 7399; // 8 -static const uint64_t SH_FLD_ERR1_REG_DP16 = 7400; // 8 -static const uint64_t SH_FLD_ERR1_REG_DP16_LEN = 7401; // 8 -static const uint64_t SH_FLD_ERR4_REG_DP16 = 7402; // 8 -static const uint64_t SH_FLD_ERR4_REG_DP16_LEN = 7403; // 8 -static const uint64_t SH_FLD_ERR5_REG_DP16 = 7404; // 8 -static const uint64_t SH_FLD_ERR5_REG_DP16_LEN = 7405; // 8 -static const uint64_t SH_FLD_ERROR = 7406; // 121 -static const uint64_t SH_FLD_ERRORS = 7407; // 43 -static const uint64_t SH_FLD_ERRORS_LEN = 7408; // 43 -static const uint64_t SH_FLD_ERROR_0 = 7409; // 1 -static const uint64_t SH_FLD_ERROR_1 = 7410; // 1 -static const uint64_t SH_FLD_ERROR_2 = 7411; // 1 -static const uint64_t SH_FLD_ERROR_3 = 7412; // 1 -static const uint64_t SH_FLD_ERROR_4 = 7413; // 1 -static const uint64_t SH_FLD_ERROR_5 = 7414; // 1 -static const uint64_t SH_FLD_ERROR_ADDR = 7415; // 4 -static const uint64_t SH_FLD_ERROR_ADDRESS = 7416; // 2 -static const uint64_t SH_FLD_ERROR_ADDRESS_LEN = 7417; // 2 -static const uint64_t SH_FLD_ERROR_ADDR_LEN = 7418; // 4 -static const uint64_t SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK = 7419; // 90 -static const uint64_t SH_FLD_ERROR_COARSE_RD = 7420; // 8 -static const uint64_t SH_FLD_ERROR_CONFIG = 7421; // 6 -static const uint64_t SH_FLD_ERROR_CONFIG0 = 7422; // 4 -static const uint64_t SH_FLD_ERROR_CONFIG0_LEN = 7423; // 4 -static const uint64_t SH_FLD_ERROR_CONFIG_LEN = 7424; // 6 -static const uint64_t SH_FLD_ERROR_COUNT_0 = 7425; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_0_LEN = 7426; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_1 = 7427; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_10 = 7428; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_10_LEN = 7429; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_11 = 7430; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_11_LEN = 7431; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_1_LEN = 7432; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_2 = 7433; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_2_LEN = 7434; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_3 = 7435; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_3_LEN = 7436; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_4 = 7437; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_4_LEN = 7438; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_5 = 7439; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_5_LEN = 7440; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_6 = 7441; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_6_LEN = 7442; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_7 = 7443; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_7_LEN = 7444; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_8 = 7445; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_8_LEN = 7446; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_9 = 7447; // 10 -static const uint64_t SH_FLD_ERROR_COUNT_9_LEN = 7448; // 10 -static const uint64_t SH_FLD_ERROR_CUSTOM_RD = 7449; // 8 -static const uint64_t SH_FLD_ERROR_CUSTOM_WR = 7450; // 8 -static const uint64_t SH_FLD_ERROR_DIGITAL_EYE = 7451; // 8 -static const uint64_t SH_FLD_ERROR_DQS_ALIGN = 7452; // 8 -static const uint64_t SH_FLD_ERROR_INITIAL_COARSE_WR = 7453; // 8 -static const uint64_t SH_FLD_ERROR_INITIAL_PAT_WRITE = 7454; // 8 -static const uint64_t SH_FLD_ERROR_INJECT = 7455; // 1 -static const uint64_t SH_FLD_ERROR_INJECT_ENABLE = 7456; // 1 -static const uint64_t SH_FLD_ERROR_INJECT_LEN = 7457; // 1 -static const uint64_t SH_FLD_ERROR_LEN = 7458; // 23 -static const uint64_t SH_FLD_ERROR_MASK = 7459; // 43 -static const uint64_t SH_FLD_ERROR_MASK_LEN = 7460; // 43 -static const uint64_t SH_FLD_ERROR_PULSE_OR_LEVEL = 7461; // 24 -static const uint64_t SH_FLD_ERROR_RATE = 7462; // 10 -static const uint64_t SH_FLD_ERROR_RATE_LEN = 7463; // 10 -static const uint64_t SH_FLD_ERROR_RDCLK_ALIGN = 7464; // 8 -static const uint64_t SH_FLD_ERROR_READ_CTR = 7465; // 8 -static const uint64_t SH_FLD_ERROR_RECOVERY_COMPLETE = 7466; // 2 -static const uint64_t SH_FLD_ERROR_RECOVERY_INITIATED = 7467; // 2 -static const uint64_t SH_FLD_ERROR_STATE = 7468; // 4 -static const uint64_t SH_FLD_ERROR_VREF = 7469; // 8 -static const uint64_t SH_FLD_ERROR_WRITE_CTR = 7470; // 8 -static const uint64_t SH_FLD_ERROR_WR_LEVEL = 7471; // 8 -static const uint64_t SH_FLD_ERRS = 7472; // 256 -static const uint64_t SH_FLD_ERRS_INJ = 7473; // 4 -static const uint64_t SH_FLD_ERRS_INJ_LEN = 7474; // 4 -static const uint64_t SH_FLD_ERRS_LEN = 7475; // 140 -static const uint64_t SH_FLD_ERR_ADDR_BEYOND_RANGE = 7476; // 1 -static const uint64_t SH_FLD_ERR_ADDR_OVERLAP = 7477; // 1 -static const uint64_t SH_FLD_ERR_BRK0 = 7478; // 1 -static const uint64_t SH_FLD_ERR_BRK0_LEN = 7479; // 1 -static const uint64_t SH_FLD_ERR_BRK1 = 7480; // 1 -static const uint64_t SH_FLD_ERR_BRK1_LEN = 7481; // 1 -static const uint64_t SH_FLD_ERR_BRK2 = 7482; // 1 -static const uint64_t SH_FLD_ERR_BRK2_LEN = 7483; // 1 -static const uint64_t SH_FLD_ERR_BRK3 = 7484; // 1 -static const uint64_t SH_FLD_ERR_BRK3_LEN = 7485; // 1 -static const uint64_t SH_FLD_ERR_BRK4 = 7486; // 1 -static const uint64_t SH_FLD_ERR_BRK4_LEN = 7487; // 1 -static const uint64_t SH_FLD_ERR_BRK5 = 7488; // 1 -static const uint64_t SH_FLD_ERR_BRK5_LEN = 7489; // 1 -static const uint64_t SH_FLD_ERR_CMD_OVERRUN = 7490; // 1 -static const uint64_t SH_FLD_ERR_CQ = 7491; // 16 -static const uint64_t SH_FLD_ERR_CQ_LEN = 7492; // 16 -static const uint64_t SH_FLD_ERR_DETAIL = 7493; // 16 -static const uint64_t SH_FLD_ERR_DETAIL_LEN = 7494; // 16 -static const uint64_t SH_FLD_ERR_FSM_DP16 = 7495; // 8 -static const uint64_t SH_FLD_ERR_FSM_DP16_LEN = 7496; // 8 -static const uint64_t SH_FLD_ERR_INJ = 7497; // 252 -static const uint64_t SH_FLD_ERR_INJ_ACTION = 7498; // 2 -static const uint64_t SH_FLD_ERR_INJ_ARRAY_SEL = 7499; // 2 -static const uint64_t SH_FLD_ERR_INJ_ARRAY_SEL_LEN = 7500; // 2 -static const uint64_t SH_FLD_ERR_INJ_A_BER_SEL = 7501; // 6 -static const uint64_t SH_FLD_ERR_INJ_A_BER_SEL_LEN = 7502; // 6 -static const uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL = 7503; // 6 -static const uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL_LEN = 7504; // 6 -static const uint64_t SH_FLD_ERR_INJ_A_ENABLE = 7505; // 116 -static const uint64_t SH_FLD_ERR_INJ_A_FINE_SEL = 7506; // 6 -static const uint64_t SH_FLD_ERR_INJ_A_FINE_SEL_LEN = 7507; // 6 -static const uint64_t SH_FLD_ERR_INJ_B_BER_SEL = 7508; // 6 -static const uint64_t SH_FLD_ERR_INJ_B_BER_SEL_LEN = 7509; // 6 -static const uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL = 7510; // 6 -static const uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL_LEN = 7511; // 6 -static const uint64_t SH_FLD_ERR_INJ_B_ENABLE = 7512; // 116 -static const uint64_t SH_FLD_ERR_INJ_B_FINE_SEL = 7513; // 6 -static const uint64_t SH_FLD_ERR_INJ_B_FINE_SEL_LEN = 7514; // 6 -static const uint64_t SH_FLD_ERR_INJ_CLOCK_ENABLE = 7515; // 6 -static const uint64_t SH_FLD_ERR_INJ_ENABLE = 7516; // 8 -static const uint64_t SH_FLD_ERR_INJ_LEN = 7517; // 136 -static const uint64_t SH_FLD_ERR_INJ_SLS_ALL_CMD = 7518; // 4 -static const uint64_t SH_FLD_ERR_INJ_SLS_CMD = 7519; // 4 -static const uint64_t SH_FLD_ERR_INJ_SLS_CMD_LEN = 7520; // 4 -static const uint64_t SH_FLD_ERR_INJ_SLS_MODE = 7521; // 4 -static const uint64_t SH_FLD_ERR_INJ_SLS_RECAL = 7522; // 4 -static const uint64_t SH_FLD_ERR_INJ_STATUS = 7523; // 2 -static const uint64_t SH_FLD_ERR_INJ_TYPE = 7524; // 2 -static const uint64_t SH_FLD_ERR_LVL = 7525; // 16 -static const uint64_t SH_FLD_ERR_LVL_LEN = 7526; // 16 -static const uint64_t SH_FLD_ERR_RSVD0 = 7527; // 16 -static const uint64_t SH_FLD_ERR_RSVD0_LEN = 7528; // 16 -static const uint64_t SH_FLD_ERR_SET0 = 7529; // 8 -static const uint64_t SH_FLD_ERR_SET1 = 7530; // 8 -static const uint64_t SH_FLD_ERR_SET2 = 7531; // 8 -static const uint64_t SH_FLD_ERR_SET3 = 7532; // 8 -static const uint64_t SH_FLD_ERR_SET4 = 7533; // 8 -static const uint64_t SH_FLD_ERR_SET5 = 7534; // 8 -static const uint64_t SH_FLD_ERR_VLD = 7535; // 16 -static const uint64_t SH_FLD_ESB_OR_LSI_INTERRUPTS = 7536; // 1 -static const uint64_t SH_FLD_ESC1_PRIORITY = 7537; // 1 -static const uint64_t SH_FLD_ESC1_PRIORITY_LEN = 7538; // 1 -static const uint64_t SH_FLD_ESC1_RSD = 7539; // 1 -static const uint64_t SH_FLD_ESC1_RSD_LEN = 7540; // 1 -static const uint64_t SH_FLD_ESC2_PRIORITY = 7541; // 1 -static const uint64_t SH_FLD_ESC2_PRIORITY_LEN = 7542; // 1 -static const uint64_t SH_FLD_ESC2_RSD = 7543; // 1 -static const uint64_t SH_FLD_ESC2_RSD_LEN = 7544; // 1 -static const uint64_t SH_FLD_ESCAPE_ADDRESS = 7545; // 1 -static const uint64_t SH_FLD_ESCAPE_ADDRESS_LEN = 7546; // 1 -static const uint64_t SH_FLD_ESR_RSVD_19 = 7547; // 1 -static const uint64_t SH_FLD_EVENT = 7548; // 6 -static const uint64_t SH_FLD_EVENT0 = 7549; // 21 -static const uint64_t SH_FLD_EVENT0_COUNTER = 7550; // 8 -static const uint64_t SH_FLD_EVENT0_COUNTER_LEN = 7551; // 8 -static const uint64_t SH_FLD_EVENT0_LEN = 7552; // 21 -static const uint64_t SH_FLD_EVENT0_SEL = 7553; // 2 -static const uint64_t SH_FLD_EVENT1 = 7554; // 21 -static const uint64_t SH_FLD_EVENT1_COUNTER = 7555; // 8 -static const uint64_t SH_FLD_EVENT1_COUNTER_LEN = 7556; // 8 -static const uint64_t SH_FLD_EVENT1_LEN = 7557; // 21 -static const uint64_t SH_FLD_EVENT1_SEL = 7558; // 2 -static const uint64_t SH_FLD_EVENT1_SEL_LEN = 7559; // 2 -static const uint64_t SH_FLD_EVENT2 = 7560; // 21 -static const uint64_t SH_FLD_EVENT2HALT_DELAY = 7561; // 1 -static const uint64_t SH_FLD_EVENT2HALT_DELAY_LEN = 7562; // 1 -static const uint64_t SH_FLD_EVENT2HALT_EN = 7563; // 1 -static const uint64_t SH_FLD_EVENT2HALT_EN_LEN = 7564; // 1 -static const uint64_t SH_FLD_EVENT2HALT_GPE0 = 7565; // 1 -static const uint64_t SH_FLD_EVENT2HALT_GPE1 = 7566; // 1 -static const uint64_t SH_FLD_EVENT2HALT_GPE2 = 7567; // 1 -static const uint64_t SH_FLD_EVENT2HALT_GPE3 = 7568; // 1 -static const uint64_t SH_FLD_EVENT2HALT_HALT_STATE = 7569; // 1 -static const uint64_t SH_FLD_EVENT2HALT_MODE = 7570; // 1 -static const uint64_t SH_FLD_EVENT2HALT_MODE_LEN = 7571; // 1 -static const uint64_t SH_FLD_EVENT2HALT_OCC = 7572; // 1 -static const uint64_t SH_FLD_EVENT2_COUNTER = 7573; // 8 -static const uint64_t SH_FLD_EVENT2_COUNTER_LEN = 7574; // 8 -static const uint64_t SH_FLD_EVENT2_LEN = 7575; // 21 -static const uint64_t SH_FLD_EVENT2_SEL = 7576; // 2 -static const uint64_t SH_FLD_EVENT2_SEL_LEN = 7577; // 2 -static const uint64_t SH_FLD_EVENT3 = 7578; // 21 -static const uint64_t SH_FLD_EVENT3_COUNTER = 7579; // 8 -static const uint64_t SH_FLD_EVENT3_COUNTER_LEN = 7580; // 8 -static const uint64_t SH_FLD_EVENT3_LEN = 7581; // 21 -static const uint64_t SH_FLD_EVENT3_SEL = 7582; // 2 -static const uint64_t SH_FLD_EVENT3_SEL_LEN = 7583; // 2 -static const uint64_t SH_FLD_EVENTCNT = 7584; // 3 -static const uint64_t SH_FLD_EVENTCNT_LEN = 7585; // 3 -static const uint64_t SH_FLD_EVENT_BUS_EN = 7586; // 4 -static const uint64_t SH_FLD_EVENT_BUS_ENABLE = 7587; // 4 -static const uint64_t SH_FLD_EVENT_BUS_EN_LEN = 7588; // 4 -static const uint64_t SH_FLD_EVENT_BUS_SELECTS = 7589; // 12 -static const uint64_t SH_FLD_EVENT_BUS_SELECTS_LEN = 7590; // 12 -static const uint64_t SH_FLD_EVENT_LEN = 7591; // 6 -static const uint64_t SH_FLD_EVENT_MUX_SELECTS = 7592; // 24 -static const uint64_t SH_FLD_EVENT_MUX_SELECTS_LEN = 7593; // 24 -static const uint64_t SH_FLD_EXACT_RESET_C3_ON_TO = 7594; // 86 -static const uint64_t SH_FLD_EXACT_TO_MODE = 7595; // 86 -static const uint64_t SH_FLD_EXBIST_MODE = 7596; // 6 -static const uint64_t SH_FLD_EXIT_1 = 7597; // 128 -static const uint64_t SH_FLD_EXIT_CRITERION_A_N = 7598; // 96 -static const uint64_t SH_FLD_EXTADDR = 7599; // 6 -static const uint64_t SH_FLD_EXTADDR_LEN = 7600; // 6 -static const uint64_t SH_FLD_EXTERNAL_ERROR = 7601; // 1 -static const uint64_t SH_FLD_EXTERNAL_TRAP = 7602; // 2 -static const uint64_t SH_FLD_EXTERNAL_TRAP_MASK = 7603; // 1 -static const uint64_t SH_FLD_EXTERNAL_XSTOP = 7604; // 4 -static const uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2 = 7605; // 1 -static const uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2_LEN = 7606; // 1 -static const uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3 = 7607; // 1 -static const uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3_LEN = 7608; // 1 -static const uint64_t SH_FLD_EXTREME_DROOP_EVENT_CTR = 7609; // 12 -static const uint64_t SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN = 7610; // 12 -static const uint64_t SH_FLD_EXTREME_EVENT_THRESHOLD = 7611; // 12 -static const uint64_t SH_FLD_EXTREME_EVENT_THRESHOLD_LEN = 7612; // 12 -static const uint64_t SH_FLD_EXT_EBB_EXIT_ENABLE = 7613; // 96 -static const uint64_t SH_FLD_EXT_EXIT_ENABLE = 7614; // 96 -static const uint64_t SH_FLD_EXT_INTERRUPT = 7615; // 1 -static const uint64_t SH_FLD_EXT_RESUME_EXIT_ENABLE = 7616; // 96 -static const uint64_t SH_FLD_EXT_TRIG_ON_FREEZE = 7617; // 43 -static const uint64_t SH_FLD_EXT_TRIG_ON_STOP = 7618; // 43 -static const uint64_t SH_FLD_EYE_OPT_DONE = 7619; // 4 -static const uint64_t SH_FLD_EYE_OPT_FAILED = 7620; // 4 -static const uint64_t SH_FLD_E_BIST_EN = 7621; // 2 -static const uint64_t SH_FLD_E_CONTROLS = 7622; // 48 -static const uint64_t SH_FLD_E_CONTROLS_LEN = 7623; // 48 -static const uint64_t SH_FLD_E_CTLE_COARSE = 7624; // 48 -static const uint64_t SH_FLD_E_CTLE_COARSE_LEN = 7625; // 48 -static const uint64_t SH_FLD_E_CTLE_GAIN = 7626; // 48 -static const uint64_t SH_FLD_E_CTLE_GAIN_LEN = 7627; // 48 -static const uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN = 7628; // 48 -static const uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN = 7629; // 48 -static const uint64_t SH_FLD_E_INTEG_COARSE_GAIN = 7630; // 48 -static const uint64_t SH_FLD_E_INTEG_COARSE_GAIN_LEN = 7631; // 48 -static const uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN = 7632; // 48 -static const uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN = 7633; // 48 -static const uint64_t SH_FLD_E_OFFSET = 7634; // 48 -static const uint64_t SH_FLD_E_OFFSET_E = 7635; // 48 -static const uint64_t SH_FLD_E_OFFSET_E_LEN = 7636; // 48 -static const uint64_t SH_FLD_E_OFFSET_LEN = 7637; // 48 -static const uint64_t SH_FLD_E_TARG_MIN = 7638; // 1 -static const uint64_t SH_FLD_E_TARG_MIN_LEN = 7639; // 1 -static const uint64_t SH_FLD_FACTOR = 7640; // 24 -static const uint64_t SH_FLD_FACTOR_LEN = 7641; // 24 -static const uint64_t SH_FLD_FAIL = 7642; // 4 -static const uint64_t SH_FLD_FAILED = 7643; // 8 -static const uint64_t SH_FLD_FAILED_LEN = 7644; // 8 -static const uint64_t SH_FLD_FAILED_LINK_ON_INTERRUPT = 7645; // 1 -static const uint64_t SH_FLD_FAILING_OPB_MASTER_ACT = 7646; // 3 -static const uint64_t SH_FLD_FAILING_OPB_MASTER_ACT_LEN = 7647; // 3 -static const uint64_t SH_FLD_FAILING_OPB_MASTER_FRST = 7648; // 3 -static const uint64_t SH_FLD_FAILING_OPB_MASTER_FRST_LEN = 7649; // 3 -static const uint64_t SH_FLD_FAIL_RCD = 7650; // 2 -static const uint64_t SH_FLD_FAIL_REG = 7651; // 1 -static const uint64_t SH_FLD_FAIL_REG_LEN = 7652; // 1 -static const uint64_t SH_FLD_FAIL_TYPE = 7653; // 2 -static const uint64_t SH_FLD_FAIL_TYPE_LEN = 7654; // 2 -static const uint64_t SH_FLD_FARB_CAL_RECVFSM_1HOT = 7655; // 8 -static const uint64_t SH_FLD_FARB_CMD_PE_HOLD_OUT = 7656; // 8 -static const uint64_t SH_FLD_FARB_PE = 7657; // 8 -static const uint64_t SH_FLD_FARR = 7658; // 43 -static const uint64_t SH_FLD_FASTPATH_LIMIT = 7659; // 8 -static const uint64_t SH_FLD_FASTPATH_LIMIT_LEN = 7660; // 8 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 = 7661; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN = 7662; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 = 7663; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN = 7664; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 = 7665; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN = 7666; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 = 7667; // 1 -static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN = 7668; // 1 -static const uint64_t SH_FLD_FAST_SB_LOOKUP_DISABLE = 7669; // 1 -static const uint64_t SH_FLD_FAST_SIM_CNTR = 7670; // 8 -static const uint64_t SH_FLD_FATAL_CNFG_HOLD_OUT = 7671; // 2 -static const uint64_t SH_FLD_FBC = 7672; // 2 -static const uint64_t SH_FLD_FBC_ADDRESS = 7673; // 1 -static const uint64_t SH_FLD_FBC_ADDRESS_ERROR = 7674; // 1 -static const uint64_t SH_FLD_FBC_ADDRESS_LEN = 7675; // 1 -static const uint64_t SH_FLD_FBC_ADDR_DONE = 7676; // 1 -static const uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT = 7677; // 1 -static const uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 7678; // 1 -static const uint64_t SH_FLD_FBC_AUTOINC_ERROR = 7679; // 1 -static const uint64_t SH_FLD_FBC_AUTO_INC = 7680; // 1 -static const uint64_t SH_FLD_FBC_AXTYPE = 7681; // 1 -static const uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT = 7682; // 1 -static const uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 7683; // 1 -static const uint64_t SH_FLD_FBC_BUS0_STG0_SEL = 7684; // 1 -static const uint64_t SH_FLD_FBC_BUS0_STG0_SEL_LEN = 7685; // 1 -static const uint64_t SH_FLD_FBC_BUS0_STG1_SEL = 7686; // 1 -static const uint64_t SH_FLD_FBC_BUS0_STG2_SEL = 7687; // 1 -static const uint64_t SH_FLD_FBC_BUS1_STG0_SEL = 7688; // 1 -static const uint64_t SH_FLD_FBC_BUS1_STG0_SEL_LEN = 7689; // 1 -static const uint64_t SH_FLD_FBC_BUS1_STG1_SEL = 7690; // 1 -static const uint64_t SH_FLD_FBC_BUS1_STG2_SEL = 7691; // 1 -static const uint64_t SH_FLD_FBC_CLEAR_STATUS = 7692; // 1 -static const uint64_t SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS = 7693; // 1 -static const uint64_t SH_FLD_FBC_COMMAND_ERROR = 7694; // 1 -static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_CE_DET = 7695; // 1 -static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_SUE_DET = 7696; // 1 -static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_UE_DET = 7697; // 1 -static const uint64_t SH_FLD_FBC_CRESP_VALUE = 7698; // 1 -static const uint64_t SH_FLD_FBC_CRESP_VALUE_LEN = 7699; // 1 -static const uint64_t SH_FLD_FBC_DATA_DONE = 7700; // 1 -static const uint64_t SH_FLD_FBC_DATA_ONLY = 7701; // 1 -static const uint64_t SH_FLD_FBC_DIN_ECC_CHK_DIS = 7702; // 1 -static const uint64_t SH_FLD_FBC_DISABLE = 7703; // 1 -static const uint64_t SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT = 7704; // 1 -static const uint64_t SH_FLD_FBC_DROP_PRIORITY = 7705; // 1 -static const uint64_t SH_FLD_FBC_DROP_PRIORITY_MAX = 7706; // 1 -static const uint64_t SH_FLD_FBC_ECC_CE = 7707; // 1 -static const uint64_t SH_FLD_FBC_ECC_SUE = 7708; // 1 -static const uint64_t SH_FLD_FBC_ECC_UE = 7709; // 1 -static const uint64_t SH_FLD_FBC_INV_AMORT_DIS = 7710; // 1 -static const uint64_t SH_FLD_FBC_LEN = 7711; // 2 -static const uint64_t SH_FLD_FBC_LFSR_DIS = 7712; // 1 -static const uint64_t SH_FLD_FBC_LOCKED = 7713; // 1 -static const uint64_t SH_FLD_FBC_LOCK_ID = 7714; // 1 -static const uint64_t SH_FLD_FBC_LOCK_ID_LEN = 7715; // 1 -static const uint64_t SH_FLD_FBC_LXSTOP_ERR_DET = 7716; // 1 -static const uint64_t SH_FLD_FBC_OVERRUN_ERROR = 7717; // 1 -static const uint64_t SH_FLD_FBC_OVERWRITE_PBINIT = 7718; // 1 -static const uint64_t SH_FLD_FBC_PBINIT_MISSING = 7719; // 1 -static const uint64_t SH_FLD_FBC_PB_DATA_HANG_ERR = 7720; // 1 -static const uint64_t SH_FLD_FBC_PB_OP_HANG_ERR = 7721; // 1 -static const uint64_t SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR = 7722; // 1 -static const uint64_t SH_FLD_FBC_PB_UNEXPECT_DATA_ERR = 7723; // 1 -static const uint64_t SH_FLD_FBC_PIB_DIRECT = 7724; // 1 -static const uint64_t SH_FLD_FBC_PIB_DIRECT_DONE = 7725; // 1 -static const uint64_t SH_FLD_FBC_PIB_ERROR = 7726; // 1 -static const uint64_t SH_FLD_FBC_PIB_ERROR_LEN = 7727; // 1 -static const uint64_t SH_FLD_FBC_RESET = 7728; // 1 -static const uint64_t SH_FLD_FBC_RESET_FSM = 7729; // 1 -static const uint64_t SH_FLD_FBC_RNW = 7730; // 1 -static const uint64_t SH_FLD_FBC_SCOPE = 7731; // 1 -static const uint64_t SH_FLD_FBC_SCOPE_LEN = 7732; // 1 -static const uint64_t SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS = 7733; // 1 -static const uint64_t SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS = 7734; // 1 -static const uint64_t SH_FLD_FBC_START_OP = 7735; // 1 -static const uint64_t SH_FLD_FBC_TSIZE = 7736; // 1 -static const uint64_t SH_FLD_FBC_TSIZE_LEN = 7737; // 1 -static const uint64_t SH_FLD_FBC_TTYPE = 7738; // 1 -static const uint64_t SH_FLD_FBC_TTYPE_LEN = 7739; // 1 -static const uint64_t SH_FLD_FBC_WAIT_CMD_ARBIT = 7740; // 1 -static const uint64_t SH_FLD_FBC_WAIT_PIB_DIRECT = 7741; // 1 -static const uint64_t SH_FLD_FBC_WAIT_RESP = 7742; // 1 -static const uint64_t SH_FLD_FBC_WITH_PBINIT_LOW_WAIT = 7743; // 1 -static const uint64_t SH_FLD_FBC_WITH_POST_INIT = 7744; // 1 -static const uint64_t SH_FLD_FBC_WITH_PRE_QUIESCE = 7745; // 1 -static const uint64_t SH_FLD_FBC_WITH_TM_QUIESCE = 7746; // 1 -static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_CE_DET = 7747; // 1 -static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_SUE_DET = 7748; // 1 -static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_UE_DET = 7749; // 1 -static const uint64_t SH_FLD_FBC_XLAT_ECC_CHK_DIS = 7750; // 1 -static const uint64_t SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS = 7751; // 1 -static const uint64_t SH_FLD_FBC_XLAT_PROT_ERR_DET = 7752; // 1 -static const uint64_t SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS = 7753; // 1 -static const uint64_t SH_FLD_FBC_XLAT_TIMEOUT_DET = 7754; // 1 -static const uint64_t SH_FLD_FENCE = 7755; // 4 -static const uint64_t SH_FLD_FENCE0 = 7756; // 15 -static const uint64_t SH_FLD_FENCE0_DC = 7757; // 3 -static const uint64_t SH_FLD_FENCE0_LEN = 7758; // 15 -static const uint64_t SH_FLD_FENCE1 = 7759; // 15 -static const uint64_t SH_FLD_FENCE1_DC = 7760; // 3 -static const uint64_t SH_FLD_FENCE1_LEN = 7761; // 15 -static const uint64_t SH_FLD_FENCE2_DC = 7762; // 3 -static const uint64_t SH_FLD_FENCE3_DC = 7763; // 3 -static const uint64_t SH_FLD_FENCE4_DC = 7764; // 3 -static const uint64_t SH_FLD_FENCE5_DC = 7765; // 3 -static const uint64_t SH_FLD_FENCE6_DC = 7766; // 3 -static const uint64_t SH_FLD_FENCE_EISR = 7767; // 24 -static const uint64_t SH_FLD_FENCE_EN = 7768; // 43 -static const uint64_t SH_FLD_FENCE_GX_INTERFACE = 7769; // 1 -static const uint64_t SH_FLD_FENCE_IO_INTERFACE = 7770; // 1 -static const uint64_t SH_FLD_FENCE_TLBIE = 7771; // 12 -static const uint64_t SH_FLD_FFE_BOOST_EN = 7772; // 6 -static const uint64_t SH_FLD_FF_BYPASS = 7773; // 6 -static const uint64_t SH_FLD_FF_SLEWRATE = 7774; // 6 -static const uint64_t SH_FLD_FF_SLEWRATE_LEN = 7775; // 6 -static const uint64_t SH_FLD_FGAT_0 = 7776; // 2 -static const uint64_t SH_FLD_FGAT_1 = 7777; // 1 -static const uint64_t SH_FLD_FGAT_2 = 7778; // 1 -static const uint64_t SH_FLD_FGAT_3 = 7779; // 1 -static const uint64_t SH_FLD_FIELD = 7780; // 9 -static const uint64_t SH_FLD_FIELD_LEN = 7781; // 9 -static const uint64_t SH_FLD_FIFO_BITS_READ0_0 = 7782; // 3 -static const uint64_t SH_FLD_FIFO_BITS_READ0_0_LEN = 7783; // 3 -static const uint64_t SH_FLD_FIFO_BITS_READ0_1 = 7784; // 2 -static const uint64_t SH_FLD_FIFO_BITS_READ0_1_LEN = 7785; // 2 -static const uint64_t SH_FLD_FIFO_BITS_READ0_2 = 7786; // 2 -static const uint64_t SH_FLD_FIFO_BITS_READ0_2_LEN = 7787; // 2 -static const uint64_t SH_FLD_FIFO_BITS_READ0_3 = 7788; // 2 -static const uint64_t SH_FLD_FIFO_BITS_READ0_3_LEN = 7789; // 2 -static const uint64_t SH_FLD_FIFO_DLY_CFG = 7790; // 120 -static const uint64_t SH_FLD_FIFO_DLY_CFG_LEN = 7791; // 120 -static const uint64_t SH_FLD_FIFO_EMPTY = 7792; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT = 7793; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_0 = 7794; // 2 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_0_LEN = 7795; // 2 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_1 = 7796; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_1_LEN = 7797; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_2 = 7798; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_2_LEN = 7799; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_3 = 7800; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_3_LEN = 7801; // 1 -static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_LEN = 7802; // 1 -static const uint64_t SH_FLD_FIFO_EOT_FLAGS = 7803; // 1 -static const uint64_t SH_FLD_FIFO_EOT_FLAGS_LEN = 7804; // 1 -static const uint64_t SH_FLD_FIFO_FINAL_L2U_DLY = 7805; // 4 -static const uint64_t SH_FLD_FIFO_FINAL_L2U_DLY_LEN = 7806; // 4 -static const uint64_t SH_FLD_FIFO_FULL = 7807; // 7 -static const uint64_t SH_FLD_FIFO_HALF_WIDTH_MODE = 7808; // 140 -static const uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY = 7809; // 4 -static const uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY_LEN = 7810; // 4 -static const uint64_t SH_FLD_FIFO_L2U_DLY = 7811; // 188 -static const uint64_t SH_FLD_FIFO_L2U_DLY_LEN = 7812; // 188 -static const uint64_t SH_FLD_FIFO_VALID_FLAGS = 7813; // 1 -static const uint64_t SH_FLD_FIFO_VALID_FLAGS_LEN = 7814; // 1 -static const uint64_t SH_FLD_FILTDIVSEL = 7815; // 3 -static const uint64_t SH_FLD_FILTDIVSEL_LEN = 7816; // 3 -static const uint64_t SH_FLD_FILTER = 7817; // 2 -static const uint64_t SH_FLD_FILTER_LEN = 7818; // 2 -static const uint64_t SH_FLD_FILTER_MODE = 7819; // 6 -static const uint64_t SH_FLD_FILTER_MODE_LEN = 7820; // 6 -static const uint64_t SH_FLD_FINAL_VDM_DATA01 = 7821; // 12 -static const uint64_t SH_FLD_FINAL_VDM_DATA01_LEN = 7822; // 12 -static const uint64_t SH_FLD_FINE_CAL_STEP_SIZE = 7823; // 8 -static const uint64_t SH_FLD_FINE_CAL_STEP_SIZE_LEN = 7824; // 8 -static const uint64_t SH_FLD_FIR = 7825; // 48 -static const uint64_t SH_FLD_FIR0_CR0_ATAG_PERR = 7826; // 12 -static const uint64_t SH_FLD_FIR0_CR0_TTAG_PERR = 7827; // 12 -static const uint64_t SH_FLD_FIR0_CR1_ATAG_PERR = 7828; // 12 -static const uint64_t SH_FLD_FIR0_CR1_TTAG_PERR = 7829; // 12 -static const uint64_t SH_FLD_FIR0_CR2_ATAG_PERR = 7830; // 12 -static const uint64_t SH_FLD_FIR0_CR2_TTAG_PERR = 7831; // 12 -static const uint64_t SH_FLD_FIR0_CR3_ATAG_PERR = 7832; // 12 -static const uint64_t SH_FLD_FIR0_CR3_TTAG_PERR = 7833; // 12 -static const uint64_t SH_FLD_FIR0_ILLEGAL_STORE_SIZE = 7834; // 12 -static const uint64_t SH_FLD_FIR0_IMA_FSM_TIMEOUT = 7835; // 12 -static const uint64_t SH_FLD_FIR0_LD_AMO_SEQ = 7836; // 12 -static const uint64_t SH_FLD_FIR0_OVERFLOW = 7837; // 12 -static const uint64_t SH_FLD_FIR0_PBARB_TRASHMODE = 7838; // 12 -static const uint64_t SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT = 7839; // 12 -static const uint64_t SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT = 7840; // 12 -static const uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 = 7841; // 12 -static const uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 = 7842; // 12 -static const uint64_t SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 = 7843; // 12 -static const uint64_t SH_FLD_FIR0_PURGE_LVL_ERR1 = 7844; // 12 -static const uint64_t SH_FLD_FIR0_PURGE_LVL_ERR2 = 7845; // 12 -static const uint64_t SH_FLD_FIR0_SNP0_ADDR_PERR = 7846; // 12 -static const uint64_t SH_FLD_FIR0_SNP0_TTAG_PERR = 7847; // 12 -static const uint64_t SH_FLD_FIR0_SNP1_ADDR_PERR = 7848; // 12 -static const uint64_t SH_FLD_FIR0_SNP1_TTAG_PERR = 7849; // 12 -static const uint64_t SH_FLD_FIR0_TLB_DATA_PAR = 7850; // 12 -static const uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_ABCD = 7851; // 12 -static const uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_EFGH = 7852; // 12 -static const uint64_t SH_FLD_FIR14_B01_BOTH_ACTIVE = 7853; // 12 -static const uint64_t SH_FLD_FIR14_B0_SD_DIR_MULT_HIT = 7854; // 12 -static const uint64_t SH_FLD_FIR14_B1_SD_DIR_MULT_HIT = 7855; // 12 -static const uint64_t SH_FLD_FIR14_B2_SD_DIR_MULT_HIT = 7856; // 12 -static const uint64_t SH_FLD_FIR14_B3_SD_DIR_MULT_HIT = 7857; // 12 -static const uint64_t SH_FLD_FIR14_BAD_FP_MATE = 7858; // 12 -static const uint64_t SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP = 7859; // 12 -static const uint64_t SH_FLD_FIR14_CR0_ATAG_PERR = 7860; // 12 -static const uint64_t SH_FLD_FIR14_CR0_TTAG_PERR = 7861; // 12 -static const uint64_t SH_FLD_FIR14_CR1_ATAG_PERR = 7862; // 12 -static const uint64_t SH_FLD_FIR14_CR1_TTAG_PERR = 7863; // 12 -static const uint64_t SH_FLD_FIR14_CR2_ATAG_PERR = 7864; // 12 -static const uint64_t SH_FLD_FIR14_CR2_TTAG_PERR = 7865; // 12 -static const uint64_t SH_FLD_FIR14_CR3_ATAG_PERR = 7866; // 12 -static const uint64_t SH_FLD_FIR14_CR3_TTAG_PERR = 7867; // 12 -static const uint64_t SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 7868; // 12 -static const uint64_t SH_FLD_FIR14_DW_SET_SI_BY_MACH = 7869; // 12 -static const uint64_t SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE = 7870; // 12 -static const uint64_t SH_FLD_FIR14_IFU_MULT_REQ = 7871; // 12 -static const uint64_t SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN = 7872; // 12 -static const uint64_t SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE = 7873; // 12 -static const uint64_t SH_FLD_FIR14_L3PF_MACH_DONE = 7874; // 12 -static const uint64_t SH_FLD_FIR14_L3PF_REQ = 7875; // 12 -static const uint64_t SH_FLD_FIR14_LSU_TAG_REUSE = 7876; // 12 -static const uint64_t SH_FLD_FIR14_NCCTL_RLD_BARRIER = 7877; // 12 -static const uint64_t SH_FLD_FIR14_NCCTL_SNP = 7878; // 12 -static const uint64_t SH_FLD_FIR14_NCCTL_SYNC = 7879; // 12 -static const uint64_t SH_FLD_FIR14_NCCTL_TLBIE_ACK = 7880; // 12 -static const uint64_t SH_FLD_FIR14_NCCTL_VSYNC = 7881; // 12 -static const uint64_t SH_FLD_FIR14_NCU_TID_DONE = 7882; // 12 -static const uint64_t SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW = 7883; // 12 -static const uint64_t SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ = 7884; // 12 -static const uint64_t SH_FLD_FIR14_PD_DIR_MULT_HIT = 7885; // 12 -static const uint64_t SH_FLD_FIR14_PHANTOM_B01_REQ = 7886; // 12 -static const uint64_t SH_FLD_FIR14_RCMD0_ADDR_PERR = 7887; // 12 -static const uint64_t SH_FLD_FIR14_RCMD0_TTAG_PERR = 7888; // 12 -static const uint64_t SH_FLD_FIR14_RCMD1_ADDR_PERR = 7889; // 12 -static const uint64_t SH_FLD_FIR14_RCMD1_TTAG_PERR = 7890; // 12 -static const uint64_t SH_FLD_FIR14_RCMD2_ADDR_PERR = 7891; // 12 -static const uint64_t SH_FLD_FIR14_RCMD2_TTAG_PERR = 7892; // 12 -static const uint64_t SH_FLD_FIR14_RCMD3_ADDR_PERR = 7893; // 12 -static const uint64_t SH_FLD_FIR14_RCMD3_TTAG_PERR = 7894; // 12 -static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 7895; // 12 -static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 7896; // 12 -static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 7897; // 12 -static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 7898; // 12 -static const uint64_t SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 7899; // 12 -static const uint64_t SH_FLD_FIR14_RC_PBBUS_SFSTAT = 7900; // 12 -static const uint64_t SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 7901; // 12 -static const uint64_t SH_FLD_FIR14_RC_UNEXP_F2_DATA = 7902; // 12 -static const uint64_t SH_FLD_FIR14_RC_UNEXP_PURG_HIT = 7903; // 12 -static const uint64_t SH_FLD_FIR14_RVCTL = 7904; // 12 -static const uint64_t SH_FLD_FIR14_SRCTL0_BAD_HPC = 7905; // 12 -static const uint64_t SH_FLD_FIR14_SRCTL1_BAD_HPC = 7906; // 12 -static const uint64_t SH_FLD_FIR14_SRCTL2_BAD_HPC = 7907; // 12 -static const uint64_t SH_FLD_FIR14_SRCTL3_BAD_HPC = 7908; // 12 -static const uint64_t SH_FLD_FIR14_STQ_COMING = 7909; // 12 -static const uint64_t SH_FLD_FIR14_STQ_OVERFLOW = 7910; // 12 -static const uint64_t SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV = 7911; // 12 -static const uint64_t SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 7912; // 12 -static const uint64_t SH_FLD_FIR14_XLT_QUEUE_OVRFLW = 7913; // 12 -static const uint64_t SH_FLD_FIR14_XPF_MULT_REQ = 7914; // 12 -static const uint64_t SH_FLD_FIR19_LD_TGT_NODAL_DINC = 7915; // 12 -static const uint64_t SH_FLD_FIR19_ST_TGT_NODAL_DINC = 7916; // 12 -static const uint64_t SH_FLD_FIR1_MASTER_SEQ_ID_PAR = 7917; // 12 -static const uint64_t SH_FLD_FIR1_RSVD_37 = 7918; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_38 = 7919; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_39 = 7920; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_40 = 7921; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_41 = 7922; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_42 = 7923; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_43 = 7924; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_44 = 7925; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_45 = 7926; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_46 = 7927; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_47 = 7928; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_48 = 7929; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_49 = 7930; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_50 = 7931; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_51 = 7932; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_52 = 7933; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_53 = 7934; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_54 = 7935; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_55 = 7936; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_56 = 7937; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_57 = 7938; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_58 = 7939; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_59 = 7940; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_60 = 7941; // 1 -static const uint64_t SH_FLD_FIR1_RSVD_61 = 7942; // 1 -static const uint64_t SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY = 7943; // 12 -static const uint64_t SH_FLD_FIR1_TLBIE_BAD_OP = 7944; // 12 -static const uint64_t SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 7945; // 12 -static const uint64_t SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 7946; // 12 -static const uint64_t SH_FLD_FIR9_PEC_PHASE3_TIMEOUT = 7947; // 12 -static const uint64_t SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 7948; // 12 -static const uint64_t SH_FLD_FIR9_PEC_PHASE4_SAME = 7949; // 12 -static const uint64_t SH_FLD_FIR9_PEC_PHASE5_TIMEOUT = 7950; // 12 -static const uint64_t SH_FLD_FIRMWARE_FAULT = 7951; // 1 -static const uint64_t SH_FLD_FIRMWARE_NOTIFY = 7952; // 1 -static const uint64_t SH_FLD_FIRST_ERROR = 7953; // 3 -static const uint64_t SH_FLD_FIRST_ERROR_CAPTURED = 7954; // 1 -static const uint64_t SH_FLD_FIRST_ERROR_DECODE = 7955; // 1 -static const uint64_t SH_FLD_FIRST_ERROR_DECODE_LEN = 7956; // 1 -static const uint64_t SH_FLD_FIRST_ERROR_INFO = 7957; // 1 -static const uint64_t SH_FLD_FIRST_ERROR_INFO_LEN = 7958; // 1 -static const uint64_t SH_FLD_FIRST_ERROR_LEN = 7959; // 3 -static const uint64_t SH_FLD_FIRST_ERROR_SPARE = 7960; // 1 -static const uint64_t SH_FLD_FIRST_ERROR_SPARE_LEN = 7961; // 1 -static const uint64_t SH_FLD_FIR_ACTION0 = 7962; // 17 -static const uint64_t SH_FLD_FIR_ACTION0_LEN = 7963; // 17 -static const uint64_t SH_FLD_FIR_ACTION1 = 7964; // 17 -static const uint64_t SH_FLD_FIR_ACTION1_LEN = 7965; // 17 -static const uint64_t SH_FLD_FIR_LEN = 7966; // 48 -static const uint64_t SH_FLD_FIR_MASK = 7967; // 20 -static const uint64_t SH_FLD_FIR_MASK_LEN = 7968; // 20 -static const uint64_t SH_FLD_FIR_PARITY_ERR = 7969; // 16 -static const uint64_t SH_FLD_FIR_PARITY_ERR2 = 7970; // 1 -static const uint64_t SH_FLD_FIR_PARITY_ERR2_MASK = 7971; // 1 -static const uint64_t SH_FLD_FIR_PARITY_ERR_DUP = 7972; // 14 -static const uint64_t SH_FLD_FIR_PARITY_ERR_DUP_MASK = 7973; // 1 -static const uint64_t SH_FLD_FIR_PARITY_ERR_MASK = 7974; // 2 -static const uint64_t SH_FLD_FIR_RESET = 7975; // 6 -static const uint64_t SH_FLD_FIR_TRIGGER = 7976; // 17 -static const uint64_t SH_FLD_FIT_SEL = 7977; // 17 -static const uint64_t SH_FLD_FIT_SEL_LEN = 7978; // 17 -static const uint64_t SH_FLD_FLAG_DMD = 7979; // 1 -static const uint64_t SH_FLD_FLAG_FENCE = 7980; // 1 -static const uint64_t SH_FLD_FLAG_MAP = 7981; // 1 -static const uint64_t SH_FLD_FLAG_OTHER = 7982; // 1 -static const uint64_t SH_FLD_FLAG_PREF = 7983; // 1 -static const uint64_t SH_FLD_FLUSH_ALIGN_OVR = 7984; // 43 -static const uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP = 7985; // 2 -static const uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN = 7986; // 2 -static const uint64_t SH_FLD_FLUSH_IC = 7987; // 24 -static const uint64_t SH_FLD_FLUSH_SCAN_N = 7988; // 43 -static const uint64_t SH_FLD_FLUSH_SUE_STATE_MAP = 7989; // 2 -static const uint64_t SH_FLD_FLUSH_SUE_STATE_MAP_LEN = 7990; // 2 -static const uint64_t SH_FLD_FMAX = 7991; // 6 -static const uint64_t SH_FLD_FMAX_LEN = 7992; // 6 -static const uint64_t SH_FLD_FMIN = 7993; // 6 -static const uint64_t SH_FLD_FMIN_LEN = 7994; // 6 -static const uint64_t SH_FLD_FMR00_TRAINED = 7995; // 4 -static const uint64_t SH_FLD_FMR01_TRAINED = 7996; // 4 -static const uint64_t SH_FLD_FMR02_TRAINED = 7997; // 4 -static const uint64_t SH_FLD_FMR03_TRAINED = 7998; // 4 -static const uint64_t SH_FLD_FMR04_TRAINED = 7999; // 4 -static const uint64_t SH_FLD_FMR05_TRAINED = 8000; // 4 -static const uint64_t SH_FLD_FMR06_TRAINED = 8001; // 2 -static const uint64_t SH_FLD_FMR07_TRAINED = 8002; // 2 -static const uint64_t SH_FLD_FMULT = 8003; // 6 -static const uint64_t SH_FLD_FMULT_LEN = 8004; // 6 -static const uint64_t SH_FLD_FORCE_ALL_RINGS = 8005; // 43 -static const uint64_t SH_FLD_FORCE_ANY_BAR_ACTIVE = 8006; // 4 -static const uint64_t SH_FLD_FORCE_ANY_CL_ACTIVE = 8007; // 4 -static const uint64_t SH_FLD_FORCE_BYPASS = 8008; // 1 -static const uint64_t SH_FLD_FORCE_CL_INJECT = 8009; // 1 -static const uint64_t SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR = 8010; // 5 -static const uint64_t SH_FLD_FORCE_DOUBLE_BIT_ERR = 8011; // 1 -static const uint64_t SH_FLD_FORCE_DROOP_DATA = 8012; // 6 -static const uint64_t SH_FLD_FORCE_DROOP_DATA_LEN = 8013; // 6 -static const uint64_t SH_FLD_FORCE_ECC_CE = 8014; // 2 -static const uint64_t SH_FLD_FORCE_ECC_SEL = 8015; // 1 -static const uint64_t SH_FLD_FORCE_ECC_SEL_0_1 = 8016; // 1 -static const uint64_t SH_FLD_FORCE_ECC_SEL_0_1_LEN = 8017; // 1 -static const uint64_t SH_FLD_FORCE_ECC_UE = 8018; // 2 -static const uint64_t SH_FLD_FORCE_FSAFE = 8019; // 6 -static const uint64_t SH_FLD_FORCE_MAX_SCOPE_INTRP = 8020; // 1 -static const uint64_t SH_FLD_FORCE_MPR = 8021; // 8 -static const uint64_t SH_FLD_FORCE_MP_IPL = 8022; // 2 -static const uint64_t SH_FLD_FORCE_ON_CLK_GATE = 8023; // 8 -static const uint64_t SH_FLD_FORCE_PR_INJECT = 8024; // 1 -static const uint64_t SH_FLD_FORCE_QUIESCE = 8025; // 2 -static const uint64_t SH_FLD_FORCE_RESERVED = 8026; // 8 -static const uint64_t SH_FLD_FORCE_RESET = 8027; // 1 -static const uint64_t SH_FLD_FORCE_SFSTAT_ACTIVE = 8028; // 4 -static const uint64_t SH_FLD_FORCE_SINGLE_BIT_ECC_ERR = 8029; // 5 -static const uint64_t SH_FLD_FORCE_SINGLE_BIT_ERR = 8030; // 1 -static const uint64_t SH_FLD_FORCE_TEST = 8031; // 43 -static const uint64_t SH_FLD_FORCE_TEST_MODE = 8032; // 86 -static const uint64_t SH_FLD_FORCE_THRES_ACT = 8033; // 43 -static const uint64_t SH_FLD_FORCE_VG_SYS_INTRP = 8034; // 1 -static const uint64_t SH_FLD_FOREIGN_LINK_HANG_ERROR = 8035; // 4 -static const uint64_t SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 = 8036; // 2 -static const uint64_t SH_FLD_FP0_DISABLE_CMD_COMPRESSION = 8037; // 2 -static const uint64_t SH_FLD_FP0_DISABLE_GATHERING = 8038; // 2 -static const uint64_t SH_FLD_FP0_DISABLE_PRSP_COMPRESSION = 8039; // 2 -static const uint64_t SH_FLD_FP0_FMR_DISABLE = 8040; // 2 -static const uint64_t SH_FLD_FP0_FMR_SPARE = 8041; // 2 -static const uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT = 8042; // 2 -static const uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN = 8043; // 2 -static const uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT = 8044; // 2 -static const uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN = 8045; // 2 -static const uint64_t SH_FLD_FP0_PRS_DISABLE = 8046; // 2 -static const uint64_t SH_FLD_FP0_PRS_SPARE = 8047; // 2 -static const uint64_t SH_FLD_FP0_PRS_SPARE_LEN = 8048; // 2 -static const uint64_t SH_FLD_FP0_RUN_AFTER_FRAME_ERROR = 8049; // 2 -static const uint64_t SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 = 8050; // 2 -static const uint64_t SH_FLD_FP1_DISABLE_CMD_COMPRESSION = 8051; // 2 -static const uint64_t SH_FLD_FP1_DISABLE_GATHERING = 8052; // 2 -static const uint64_t SH_FLD_FP1_DISABLE_PRSP_COMPRESSION = 8053; // 2 -static const uint64_t SH_FLD_FP1_FMR_DISABLE = 8054; // 2 -static const uint64_t SH_FLD_FP1_FMR_SPARE = 8055; // 2 -static const uint64_t SH_FLD_FP1_FMR_SPARE_LEN = 8056; // 2 -static const uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT = 8057; // 2 -static const uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN = 8058; // 2 -static const uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT = 8059; // 2 -static const uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN = 8060; // 2 -static const uint64_t SH_FLD_FP1_PRS_DISABLE = 8061; // 2 -static const uint64_t SH_FLD_FP1_PRS_SPARE = 8062; // 2 -static const uint64_t SH_FLD_FP1_PRS_SPARE_LEN = 8063; // 2 -static const uint64_t SH_FLD_FP1_RUN_AFTER_FRAME_ERROR = 8064; // 2 -static const uint64_t SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 = 8065; // 2 -static const uint64_t SH_FLD_FP2_DISABLE_CMD_COMPRESSION = 8066; // 2 -static const uint64_t SH_FLD_FP2_DISABLE_GATHERING = 8067; // 2 -static const uint64_t SH_FLD_FP2_DISABLE_PRSP_COMPRESSION = 8068; // 2 -static const uint64_t SH_FLD_FP2_FMR_DISABLE = 8069; // 2 -static const uint64_t SH_FLD_FP2_FMR_SPARE = 8070; // 2 -static const uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT = 8071; // 2 -static const uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN = 8072; // 2 -static const uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT = 8073; // 2 -static const uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN = 8074; // 2 -static const uint64_t SH_FLD_FP2_PRS_DISABLE = 8075; // 2 -static const uint64_t SH_FLD_FP2_PRS_SPARE = 8076; // 2 -static const uint64_t SH_FLD_FP2_PRS_SPARE_LEN = 8077; // 2 -static const uint64_t SH_FLD_FP2_RUN_AFTER_FRAME_ERROR = 8078; // 2 -static const uint64_t SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 = 8079; // 2 -static const uint64_t SH_FLD_FP3_DISABLE_CMD_COMPRESSION = 8080; // 2 -static const uint64_t SH_FLD_FP3_DISABLE_GATHERING = 8081; // 2 -static const uint64_t SH_FLD_FP3_DISABLE_PRSP_COMPRESSION = 8082; // 2 -static const uint64_t SH_FLD_FP3_FMR_DISABLE = 8083; // 2 -static const uint64_t SH_FLD_FP3_FMR_SPARE = 8084; // 2 -static const uint64_t SH_FLD_FP3_FMR_SPARE_LEN = 8085; // 2 -static const uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT = 8086; // 2 -static const uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN = 8087; // 2 -static const uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT = 8088; // 2 -static const uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN = 8089; // 2 -static const uint64_t SH_FLD_FP3_PRS_DISABLE = 8090; // 2 -static const uint64_t SH_FLD_FP3_PRS_SPARE = 8091; // 2 -static const uint64_t SH_FLD_FP3_PRS_SPARE_LEN = 8092; // 2 -static const uint64_t SH_FLD_FP3_RUN_AFTER_FRAME_ERROR = 8093; // 2 -static const uint64_t SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 = 8094; // 2 -static const uint64_t SH_FLD_FP4_DISABLE_CMD_COMPRESSION = 8095; // 2 -static const uint64_t SH_FLD_FP4_DISABLE_GATHERING = 8096; // 2 -static const uint64_t SH_FLD_FP4_DISABLE_PRSP_COMPRESSION = 8097; // 2 -static const uint64_t SH_FLD_FP4_FMR_DISABLE = 8098; // 2 -static const uint64_t SH_FLD_FP4_FMR_SPARE = 8099; // 2 -static const uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT = 8100; // 2 -static const uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN = 8101; // 2 -static const uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT = 8102; // 2 -static const uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN = 8103; // 2 -static const uint64_t SH_FLD_FP4_PRS_DISABLE = 8104; // 2 -static const uint64_t SH_FLD_FP4_PRS_SPARE = 8105; // 2 -static const uint64_t SH_FLD_FP4_PRS_SPARE_LEN = 8106; // 2 -static const uint64_t SH_FLD_FP4_RUN_AFTER_FRAME_ERROR = 8107; // 2 -static const uint64_t SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 = 8108; // 2 -static const uint64_t SH_FLD_FP5_DISABLE_CMD_COMPRESSION = 8109; // 2 -static const uint64_t SH_FLD_FP5_DISABLE_GATHERING = 8110; // 2 -static const uint64_t SH_FLD_FP5_DISABLE_PRSP_COMPRESSION = 8111; // 2 -static const uint64_t SH_FLD_FP5_FMR_DISABLE = 8112; // 2 -static const uint64_t SH_FLD_FP5_FMR_SPARE = 8113; // 2 -static const uint64_t SH_FLD_FP5_FMR_SPARE_LEN = 8114; // 2 -static const uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT = 8115; // 2 -static const uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN = 8116; // 2 -static const uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT = 8117; // 2 -static const uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN = 8118; // 2 -static const uint64_t SH_FLD_FP5_PRS_DISABLE = 8119; // 2 -static const uint64_t SH_FLD_FP5_PRS_SPARE = 8120; // 2 -static const uint64_t SH_FLD_FP5_PRS_SPARE_LEN = 8121; // 2 -static const uint64_t SH_FLD_FP5_RUN_AFTER_FRAME_ERROR = 8122; // 2 -static const uint64_t SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 = 8123; // 1 -static const uint64_t SH_FLD_FP6_DISABLE_CMD_COMPRESSION = 8124; // 1 -static const uint64_t SH_FLD_FP6_DISABLE_GATHERING = 8125; // 1 -static const uint64_t SH_FLD_FP6_DISABLE_PRSP_COMPRESSION = 8126; // 1 -static const uint64_t SH_FLD_FP6_FMR_DISABLE = 8127; // 1 -static const uint64_t SH_FLD_FP6_FMR_SPARE = 8128; // 1 -static const uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT = 8129; // 1 -static const uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN = 8130; // 1 -static const uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT = 8131; // 1 -static const uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN = 8132; // 1 -static const uint64_t SH_FLD_FP6_PRS_DISABLE = 8133; // 1 -static const uint64_t SH_FLD_FP6_PRS_SPARE = 8134; // 1 -static const uint64_t SH_FLD_FP6_PRS_SPARE_LEN = 8135; // 1 -static const uint64_t SH_FLD_FP6_RUN_AFTER_FRAME_ERROR = 8136; // 1 -static const uint64_t SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 = 8137; // 1 -static const uint64_t SH_FLD_FP7_DISABLE_CMD_COMPRESSION = 8138; // 1 -static const uint64_t SH_FLD_FP7_DISABLE_GATHERING = 8139; // 1 -static const uint64_t SH_FLD_FP7_DISABLE_PRSP_COMPRESSION = 8140; // 1 -static const uint64_t SH_FLD_FP7_FMR_DISABLE = 8141; // 1 -static const uint64_t SH_FLD_FP7_FMR_SPARE = 8142; // 1 -static const uint64_t SH_FLD_FP7_FMR_SPARE_LEN = 8143; // 1 -static const uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT = 8144; // 1 -static const uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN = 8145; // 1 -static const uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT = 8146; // 1 -static const uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN = 8147; // 1 -static const uint64_t SH_FLD_FP7_PRS_DISABLE = 8148; // 1 -static const uint64_t SH_FLD_FP7_PRS_SPARE = 8149; // 1 -static const uint64_t SH_FLD_FP7_PRS_SPARE_LEN = 8150; // 1 -static const uint64_t SH_FLD_FP7_RUN_AFTER_FRAME_ERROR = 8151; // 1 -static const uint64_t SH_FLD_FRAC1 = 8152; // 3 -static const uint64_t SH_FLD_FRAC1_LEN = 8153; // 3 -static const uint64_t SH_FLD_FRAC2 = 8154; // 3 -static const uint64_t SH_FLD_FRAC2_LEN = 8155; // 3 -static const uint64_t SH_FLD_FRAMER00_ATTN = 8156; // 4 -static const uint64_t SH_FLD_FRAMER01_ATTN = 8157; // 4 -static const uint64_t SH_FLD_FRAMER02_ATTN = 8158; // 4 -static const uint64_t SH_FLD_FRAMER03_ATTN = 8159; // 4 -static const uint64_t SH_FLD_FRAMER04_ATTN = 8160; // 4 -static const uint64_t SH_FLD_FRAMER05_ATTN = 8161; // 4 -static const uint64_t SH_FLD_FRAMER06_ATTN = 8162; // 2 -static const uint64_t SH_FLD_FRAMER07_ATTN = 8163; // 2 -static const uint64_t SH_FLD_FRAME_CAP_ADDR = 8164; // 10 -static const uint64_t SH_FLD_FRAME_CAP_ADDR_LEN = 8165; // 10 -static const uint64_t SH_FLD_FRAME_CAP_INST = 8166; // 10 -static const uint64_t SH_FLD_FRAME_CAP_SYN = 8167; // 10 -static const uint64_t SH_FLD_FRAME_CAP_SYN_LEN = 8168; // 10 -static const uint64_t SH_FLD_FRAME_CAP_VALID = 8169; // 10 -static const uint64_t SH_FLD_FRAME_COUNT = 8170; // 8 -static const uint64_t SH_FLD_FRAME_COUNT_LEN = 8171; // 8 -static const uint64_t SH_FLD_FRAME_SIZE = 8172; // 1 -static const uint64_t SH_FLD_FRAME_SIZE_LEN = 8173; // 1 -static const uint64_t SH_FLD_FREE = 8174; // 12 -static const uint64_t SH_FLD_FREEZE = 8175; // 10 -static const uint64_t SH_FLD_FREEZEMODE = 8176; // 9 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR1 = 8177; // 1 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR2 = 8178; // 1 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR3 = 8179; // 1 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR4 = 8180; // 1 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR5 = 8181; // 1 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR6 = 8182; // 1 -static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR7 = 8183; // 1 -static const uint64_t SH_FLD_FREEZE_ON_OVERFLOW = 8184; // 2 -static const uint64_t SH_FLD_FREEZE_SEL = 8185; // 43 -static const uint64_t SH_FLD_FREE_USAGE = 8186; // 2 -static const uint64_t SH_FLD_FREE_USAGE_10E = 8187; // 43 -static const uint64_t SH_FLD_FREE_USAGE_11E = 8188; // 43 -static const uint64_t SH_FLD_FREE_USAGE_12D = 8189; // 11 -static const uint64_t SH_FLD_FREE_USAGE_12E = 8190; // 38 -static const uint64_t SH_FLD_FREE_USAGE_13D = 8191; // 12 -static const uint64_t SH_FLD_FREE_USAGE_13E = 8192; // 38 -static const uint64_t SH_FLD_FREE_USAGE_14D = 8193; // 12 -static const uint64_t SH_FLD_FREE_USAGE_14E = 8194; // 40 -static const uint64_t SH_FLD_FREE_USAGE_15D = 8195; // 12 -static const uint64_t SH_FLD_FREE_USAGE_15E = 8196; // 40 -static const uint64_t SH_FLD_FREE_USAGE_16D = 8197; // 30 -static const uint64_t SH_FLD_FREE_USAGE_16E = 8198; // 40 -static const uint64_t SH_FLD_FREE_USAGE_17D = 8199; // 32 -static const uint64_t SH_FLD_FREE_USAGE_17E = 8200; // 40 -static const uint64_t SH_FLD_FREE_USAGE_18D = 8201; // 39 -static const uint64_t SH_FLD_FREE_USAGE_18E = 8202; // 40 -static const uint64_t SH_FLD_FREE_USAGE_19D = 8203; // 40 -static const uint64_t SH_FLD_FREE_USAGE_19E = 8204; // 40 -static const uint64_t SH_FLD_FREE_USAGE_20D = 8205; // 40 -static const uint64_t SH_FLD_FREE_USAGE_20E = 8206; // 41 -static const uint64_t SH_FLD_FREE_USAGE_21D = 8207; // 40 -static const uint64_t SH_FLD_FREE_USAGE_21E = 8208; // 43 -static const uint64_t SH_FLD_FREE_USAGE_22D = 8209; // 40 -static const uint64_t SH_FLD_FREE_USAGE_22E = 8210; // 43 -static const uint64_t SH_FLD_FREE_USAGE_23D = 8211; // 40 -static const uint64_t SH_FLD_FREE_USAGE_23E = 8212; // 43 -static const uint64_t SH_FLD_FREE_USAGE_24D = 8213; // 40 -static const uint64_t SH_FLD_FREE_USAGE_25D = 8214; // 40 -static const uint64_t SH_FLD_FREE_USAGE_26D = 8215; // 41 -static const uint64_t SH_FLD_FREE_USAGE_27D = 8216; // 41 -static const uint64_t SH_FLD_FREE_USAGE_28D = 8217; // 39 -static const uint64_t SH_FLD_FREE_USAGE_29D = 8218; // 39 -static const uint64_t SH_FLD_FREE_USAGE_30D = 8219; // 39 -static const uint64_t SH_FLD_FREE_USAGE_31D = 8220; // 41 -static const uint64_t SH_FLD_FREE_USAGE_44C = 8221; // 43 -static const uint64_t SH_FLD_FREE_USAGE_45C = 8222; // 43 -static const uint64_t SH_FLD_FREE_USAGE_46C = 8223; // 43 -static const uint64_t SH_FLD_FREE_USAGE_47C = 8224; // 43 -static const uint64_t SH_FLD_FREE_USAGE_48A = 8225; // 43 -static const uint64_t SH_FLD_FREE_USAGE_49A = 8226; // 43 -static const uint64_t SH_FLD_FREE_USAGE_50A = 8227; // 43 -static const uint64_t SH_FLD_FREE_USAGE_51A = 8228; // 43 -static const uint64_t SH_FLD_FREE_USAGE_52A = 8229; // 43 -static const uint64_t SH_FLD_FREE_USAGE_53A = 8230; // 43 -static const uint64_t SH_FLD_FREE_USAGE_54A = 8231; // 43 -static const uint64_t SH_FLD_FREE_USAGE_55A = 8232; // 43 -static const uint64_t SH_FLD_FREE_USAGE_56A = 8233; // 43 -static const uint64_t SH_FLD_FREE_USAGE_57A = 8234; // 43 -static const uint64_t SH_FLD_FREE_USAGE_58A = 8235; // 43 -static const uint64_t SH_FLD_FREE_USAGE_59A = 8236; // 43 -static const uint64_t SH_FLD_FREE_USAGE_60A = 8237; // 43 -static const uint64_t SH_FLD_FREE_USAGE_61A = 8238; // 43 -static const uint64_t SH_FLD_FREE_USAGE_62A = 8239; // 43 -static const uint64_t SH_FLD_FREE_USAGE_63A = 8240; // 43 -static const uint64_t SH_FLD_FREE_USAGE_6A = 8241; // 43 -static const uint64_t SH_FLD_FREE_USAGE_7A = 8242; // 43 -static const uint64_t SH_FLD_FREE_USAGE_9A = 8243; // 43 -static const uint64_t SH_FLD_FREQIN_AVG = 8244; // 6 -static const uint64_t SH_FLD_FREQIN_AVG_LEN = 8245; // 6 -static const uint64_t SH_FLD_FREQIN_MAX = 8246; // 6 -static const uint64_t SH_FLD_FREQIN_MAX_LEN = 8247; // 6 -static const uint64_t SH_FLD_FREQIN_MIN = 8248; // 6 -static const uint64_t SH_FLD_FREQIN_MIN_LEN = 8249; // 6 -static const uint64_t SH_FLD_FREQOUT = 8250; // 6 -static const uint64_t SH_FLD_FREQOUT_AVG = 8251; // 6 -static const uint64_t SH_FLD_FREQOUT_AVG_LEN = 8252; // 6 -static const uint64_t SH_FLD_FREQOUT_LEN = 8253; // 6 -static const uint64_t SH_FLD_FREQOUT_MAX = 8254; // 6 -static const uint64_t SH_FLD_FREQOUT_MAX_LEN = 8255; // 6 -static const uint64_t SH_FLD_FREQOUT_MIN = 8256; // 6 -static const uint64_t SH_FLD_FREQOUT_MIN_LEN = 8257; // 6 -static const uint64_t SH_FLD_FREQUENCY_REFERENCE = 8258; // 24 -static const uint64_t SH_FLD_FREQUENCY_REFERENCE_LEN = 8259; // 24 -static const uint64_t SH_FLD_FREQ_CHANGE = 8260; // 6 -static const uint64_t SH_FLD_FREQ_LCL_SAMPLE_EN = 8261; // 12 -static const uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD = 8262; // 24 -static const uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN = 8263; // 24 -static const uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD = 8264; // 24 -static const uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN = 8265; // 24 -static const uint64_t SH_FLD_FRZ_COUNT_ON_FRZ = 8266; // 43 -static const uint64_t SH_FLD_FSAFE = 8267; // 6 -static const uint64_t SH_FLD_FSAFE_ACTIVE = 8268; // 6 -static const uint64_t SH_FLD_FSAFE_LEN = 8269; // 6 -static const uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR = 8270; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN = 8271; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_0_ENABLE = 8272; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_1_ENABLE = 8273; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_2_ENABLE = 8274; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_3_ENABLE = 8275; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_4_ENABLE = 8276; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_5_ENABLE = 8277; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_6_ENABLE = 8278; // 1 -static const uint64_t SH_FLD_FSI_A_MST_0_PORT_7_ENABLE = 8279; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR = 8280; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN = 8281; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_PORT_0_ENABLE = 8282; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_PORT_1_ENABLE = 8283; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_PORT_2_ENABLE = 8284; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_PORT_3_ENABLE = 8285; // 1 -static const uint64_t SH_FLD_FSI_A_MST_1_PORT_4_ENABLE = 8286; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR = 8287; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN = 8288; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_0_ENABLE = 8289; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_1_ENABLE = 8290; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_2_ENABLE = 8291; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_3_ENABLE = 8292; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_4_ENABLE = 8293; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_5_ENABLE = 8294; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_6_ENABLE = 8295; // 1 -static const uint64_t SH_FLD_FSI_B_MST_0_PORT_7_ENABLE = 8296; // 1 -static const uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD = 8297; // 3 -static const uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD_LEN = 8298; // 3 -static const uint64_t SH_FLD_FSI_CC_VSB_CBS_REQ = 8299; // 3 -static const uint64_t SH_FLD_FSI_SCRATCH_PAD1 = 8300; // 1 -static const uint64_t SH_FLD_FSI_SCRATCH_PAD1_LEN = 8301; // 1 -static const uint64_t SH_FLD_FSI_SCRATCH_PAD2 = 8302; // 1 -static const uint64_t SH_FLD_FSI_SCRATCH_PAD2_LEN = 8303; // 1 -static const uint64_t SH_FLD_FSI_SCRATCH_PAD3 = 8304; // 1 -static const uint64_t SH_FLD_FSI_SCRATCH_PAD3_LEN = 8305; // 1 -static const uint64_t SH_FLD_FSMJ_EVENT = 8306; // 2 -static const uint64_t SH_FLD_FSMJ_EVENT_LEN = 8307; // 2 -static const uint64_t SH_FLD_FSMJ_EVENT_SEL = 8308; // 2 -static const uint64_t SH_FLD_FSMJ_EVENT_SEL_LEN = 8309; // 2 -static const uint64_t SH_FLD_FSMJ_FSM = 8310; // 2 -static const uint64_t SH_FLD_FSMJ_FSM_LEN = 8311; // 2 -static const uint64_t SH_FLD_FSMJ_FSM_SEL = 8312; // 2 -static const uint64_t SH_FLD_FSMJ_FSM_SEL_LEN = 8313; // 2 -static const uint64_t SH_FLD_FSM_DATA02 = 8314; // 1 -static const uint64_t SH_FLD_FSM_ERR = 8315; // 5 -static const uint64_t SH_FLD_FSM_ERROR = 8316; // 1 -static const uint64_t SH_FLD_FSM_PARITY_ERROR = 8317; // 3 -static const uint64_t SH_FLD_FSM_PERR = 8318; // 1 -static const uint64_t SH_FLD_FSM_PRESENT_STATE = 8319; // 1 -static const uint64_t SH_FLD_FSM_PRESENT_STATE_LEN = 8320; // 1 -static const uint64_t SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8321; // 43 -static const uint64_t SH_FLD_FSM_SYNC_ENABLE = 8322; // 1 -static const uint64_t SH_FLD_FSM_TRIGGER = 8323; // 2 -static const uint64_t SH_FLD_FSP_ACCESS_TRUSTED_SPACE = 8324; // 4 -static const uint64_t SH_FLD_FSP_CMD_ENABLE = 8325; // 1 -static const uint64_t SH_FLD_FSP_ECC_ERR_CE = 8326; // 4 -static const uint64_t SH_FLD_FSP_ECC_ERR_UE = 8327; // 4 -static const uint64_t SH_FLD_FSP_ERR_RSP_ENABLE = 8328; // 1 -static const uint64_t SH_FLD_FSP_INBOUND_ACTIVE = 8329; // 1 -static const uint64_t SH_FLD_FSP_INTERRUPT = 8330; // 1 -static const uint64_t SH_FLD_FSP_INT_ENABLE = 8331; // 1 -static const uint64_t SH_FLD_FSP_INV_READ = 8332; // 1 -static const uint64_t SH_FLD_FSP_LINK_ACTIVE = 8333; // 1 -static const uint64_t SH_FLD_FSP_MMIO_ENABLE = 8334; // 1 -static const uint64_t SH_FLD_FSP_MMIO_MASK = 8335; // 1 -static const uint64_t SH_FLD_FSP_MMIO_MASK_LEN = 8336; // 1 -static const uint64_t SH_FLD_FSP_OUTBOUND_ACTIVE = 8337; // 1 -static const uint64_t SH_FLD_FSP_RESET = 8338; // 1 -static const uint64_t SH_FLD_FSP_SPECIAL_WKUP = 8339; // 30 -static const uint64_t SH_FLD_FSP_TCE_ENABLE = 8340; // 1 -static const uint64_t SH_FLD_FULL = 8341; // 2 -static const uint64_t SH_FLD_FULLMASK = 8342; // 1 -static const uint64_t SH_FLD_FULLMASK_LEN = 8343; // 1 -static const uint64_t SH_FLD_FULL_WRITEBACK_ENABLE = 8344; // 6 -static const uint64_t SH_FLD_FUNC = 8345; // 43 -static const uint64_t SH_FLD_FUNCTION = 8346; // 6 -static const uint64_t SH_FLD_FUNCTION_LEN = 8347; // 6 -static const uint64_t SH_FLD_FUNC_MODE_DONE = 8348; // 4 -static const uint64_t SH_FLD_FUSED_CORE_MODE = 8349; // 24 -static const uint64_t SH_FLD_FW0 = 8350; // 1 -static const uint64_t SH_FLD_FW0_MASK = 8351; // 1 -static const uint64_t SH_FLD_FW1 = 8352; // 1 -static const uint64_t SH_FLD_FW1_MASK = 8353; // 1 -static const uint64_t SH_FLD_FWD_PROG_RATE2 = 8354; // 12 -static const uint64_t SH_FLD_FWD_PROG_RATE2_LEN = 8355; // 12 -static const uint64_t SH_FLD_FWMSX_PE = 8356; // 8 -static const uint64_t SH_FLD_FWMSX_PE_LEN = 8357; // 8 -static const uint64_t SH_FLD_FW_RD_WR = 8358; // 8 -static const uint64_t SH_FLD_FW_RD_WR_LEN = 8359; // 8 -static const uint64_t SH_FLD_FW_WR_RD = 8360; // 8 -static const uint64_t SH_FLD_FW_WR_RD_LEN = 8361; // 8 -static const uint64_t SH_FLD_F_READ = 8362; // 43 -static const uint64_t SH_FLD_F_SKITTER_READ_MASK = 8363; // 43 -static const uint64_t SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL = 8364; // 4 -static const uint64_t SH_FLD_GCR_HANG_DET_SEL = 8365; // 4 -static const uint64_t SH_FLD_GCR_HANG_DET_SEL_LEN = 8366; // 4 -static const uint64_t SH_FLD_GCR_HANG_ERROR_INJ = 8367; // 4 -static const uint64_t SH_FLD_GCR_HANG_ERROR_MASK = 8368; // 4 -static const uint64_t SH_FLD_GCR_TEST = 8369; // 4 -static const uint64_t SH_FLD_GENERAL_TIMEOUT = 8370; // 43 -static const uint64_t SH_FLD_GENERATE_MPIPL_SEQUENCE = 8371; // 4 -static const uint64_t SH_FLD_GLB_BRCST = 8372; // 43 -static const uint64_t SH_FLD_GLB_BRCST_LEN = 8373; // 43 -static const uint64_t SH_FLD_GLOBAL_EP_RESET_DC = 8374; // 3 -static const uint64_t SH_FLD_GLOBAL_PHY_OFFSET = 8375; // 8 -static const uint64_t SH_FLD_GLOBAL_PHY_OFFSET_LEN = 8376; // 8 -static const uint64_t SH_FLD_GLOBAL_RUN_MODE = 8377; // 2 -static const uint64_t SH_FLD_GO = 8378; // 43 -static const uint64_t SH_FLD_GO2 = 8379; // 43 -static const uint64_t SH_FLD_GOTO_CMD = 8380; // 64 -static const uint64_t SH_FLD_GOTO_CMD_LEN = 8381; // 64 -static const uint64_t SH_FLD_GP = 8382; // 2 -static const uint64_t SH_FLD_GPE0_ERROR = 8383; // 2 -static const uint64_t SH_FLD_GPE0_ERROR_MASK = 8384; // 1 -static const uint64_t SH_FLD_GPE0_HALTED = 8385; // 1 -static const uint64_t SH_FLD_GPE0_HALTED_MASK = 8386; // 1 -static const uint64_t SH_FLD_GPE0_OCISLV_ERR = 8387; // 2 -static const uint64_t SH_FLD_GPE0_OCISLV_ERR_LEN = 8388; // 1 -static const uint64_t SH_FLD_GPE0_OCISLV_ERR_MASK = 8389; // 1 -static const uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT = 8390; // 1 -static const uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT_MASK = 8391; // 1 -static const uint64_t SH_FLD_GPE1_ERROR = 8392; // 2 -static const uint64_t SH_FLD_GPE1_ERROR_MASK = 8393; // 1 -static const uint64_t SH_FLD_GPE1_HALTED = 8394; // 1 -static const uint64_t SH_FLD_GPE1_HALTED_MASK = 8395; // 1 -static const uint64_t SH_FLD_GPE1_OCISLV_ERR = 8396; // 2 -static const uint64_t SH_FLD_GPE1_OCISLV_ERR_LEN = 8397; // 1 -static const uint64_t SH_FLD_GPE1_OCISLV_ERR_MASK = 8398; // 1 -static const uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT = 8399; // 1 -static const uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT_MASK = 8400; // 1 -static const uint64_t SH_FLD_GPE2_ERROR = 8401; // 2 -static const uint64_t SH_FLD_GPE2_ERROR_MASK = 8402; // 1 -static const uint64_t SH_FLD_GPE2_HALTED = 8403; // 1 -static const uint64_t SH_FLD_GPE2_HALTED_MASK = 8404; // 1 -static const uint64_t SH_FLD_GPE2_OCISLV_ERR = 8405; // 2 -static const uint64_t SH_FLD_GPE2_OCISLV_ERR_LEN = 8406; // 1 -static const uint64_t SH_FLD_GPE2_OCISLV_ERR_MASK = 8407; // 1 -static const uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT = 8408; // 1 -static const uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT_MASK = 8409; // 1 -static const uint64_t SH_FLD_GPE3_ERROR = 8410; // 2 -static const uint64_t SH_FLD_GPE3_ERROR_MASK = 8411; // 1 -static const uint64_t SH_FLD_GPE3_HALTED = 8412; // 1 -static const uint64_t SH_FLD_GPE3_HALTED_MASK = 8413; // 1 -static const uint64_t SH_FLD_GPE3_OCISLV_ERR = 8414; // 2 -static const uint64_t SH_FLD_GPE3_OCISLV_ERR_LEN = 8415; // 1 -static const uint64_t SH_FLD_GPE3_OCISLV_ERR_MASK = 8416; // 1 -static const uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT = 8417; // 1 -static const uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT_MASK = 8418; // 1 -static const uint64_t SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 8419; // 3 -static const uint64_t SH_FLD_GRANTED_PACKET = 8420; // 30 -static const uint64_t SH_FLD_GRANTED_PACKET_LEN = 8421; // 30 -static const uint64_t SH_FLD_GRANTED_SOURCE = 8422; // 30 -static const uint64_t SH_FLD_GRANTED_SOURCE_LEN = 8423; // 30 -static const uint64_t SH_FLD_GROUP = 8424; // 9 -static const uint64_t SH_FLD_GROUPING = 8425; // 8 -static const uint64_t SH_FLD_GROUPING_LEN = 8426; // 8 -static const uint64_t SH_FLD_GROUP_BASE_ADDRESS = 8427; // 8 -static const uint64_t SH_FLD_GROUP_BASE_ADDRESS_LEN = 8428; // 8 -static const uint64_t SH_FLD_GROUP_EPSILON = 8429; // 8 -static const uint64_t SH_FLD_GROUP_EPSILON_LEN = 8430; // 8 -static const uint64_t SH_FLD_GROUP_LEN = 8431; // 9 -static const uint64_t SH_FLD_GROUP_SEL_0_4 = 8432; // 1 -static const uint64_t SH_FLD_GROUP_SEL_0_4_LEN = 8433; // 1 -static const uint64_t SH_FLD_GROUP_SIZE = 8434; // 8 -static const uint64_t SH_FLD_GROUP_SIZE_LEN = 8435; // 8 -static const uint64_t SH_FLD_GRPSEL = 8436; // 2 -static const uint64_t SH_FLD_GRPSEL_LEN = 8437; // 2 -static const uint64_t SH_FLD_GRP_BASE = 8438; // 8 -static const uint64_t SH_FLD_GRP_BASE_LEN = 8439; // 8 -static const uint64_t SH_FLD_GRP_MBR_ID = 8440; // 8 -static const uint64_t SH_FLD_GRP_SIZE = 8441; // 8 -static const uint64_t SH_FLD_GRP_SIZE_LEN = 8442; // 8 -static const uint64_t SH_FLD_GUESS_WAIT_TIME = 8443; // 8 -static const uint64_t SH_FLD_GUESS_WAIT_TIME_LEN = 8444; // 8 -static const uint64_t SH_FLD_GUEST_PREF_PGSZ = 8445; // 1 -static const uint64_t SH_FLD_GUEST_PREF_PGSZ_LEN = 8446; // 1 -static const uint64_t SH_FLD_GX = 8447; // 2 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN0 = 8448; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN1 = 8449; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN10 = 8450; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN11 = 8451; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN2 = 8452; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN3 = 8453; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN4 = 8454; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN5 = 8455; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN6 = 8456; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN7 = 8457; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN8 = 8458; // 43 -static const uint64_t SH_FLD_GXSTP0_TRIG_IN9 = 8459; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN0 = 8460; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN1 = 8461; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN10 = 8462; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN11 = 8463; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN2 = 8464; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN3 = 8465; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN4 = 8466; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN5 = 8467; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN6 = 8468; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN7 = 8469; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN8 = 8470; // 43 -static const uint64_t SH_FLD_GXSTP1_TRIG_IN9 = 8471; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN0 = 8472; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN1 = 8473; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN10 = 8474; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN11 = 8475; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN2 = 8476; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN3 = 8477; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN4 = 8478; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN5 = 8479; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN6 = 8480; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN7 = 8481; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN8 = 8482; // 43 -static const uint64_t SH_FLD_GXSTP2_TRIG_IN9 = 8483; // 43 -static const uint64_t SH_FLD_GXSTP_IN0 = 8484; // 43 -static const uint64_t SH_FLD_GXSTP_IN1 = 8485; // 43 -static const uint64_t SH_FLD_GXSTP_IN10 = 8486; // 43 -static const uint64_t SH_FLD_GXSTP_IN11 = 8487; // 43 -static const uint64_t SH_FLD_GXSTP_IN2 = 8488; // 43 -static const uint64_t SH_FLD_GXSTP_IN3 = 8489; // 43 -static const uint64_t SH_FLD_GXSTP_IN4 = 8490; // 43 -static const uint64_t SH_FLD_GXSTP_IN5 = 8491; // 43 -static const uint64_t SH_FLD_GXSTP_IN6 = 8492; // 43 -static const uint64_t SH_FLD_GXSTP_IN7 = 8493; // 43 -static const uint64_t SH_FLD_GXSTP_IN8 = 8494; // 43 -static const uint64_t SH_FLD_GXSTP_IN9 = 8495; // 43 -static const uint64_t SH_FLD_GX_ENABLE_OVERWRITE = 8496; // 1 -static const uint64_t SH_FLD_GX_LEN = 8497; // 2 -static const uint64_t SH_FLD_GZIPCOMP_MAX_INRD = 8498; // 1 -static const uint64_t SH_FLD_GZIPCOMP_MAX_INRD_LEN = 8499; // 1 -static const uint64_t SH_FLD_GZIPDECOMP_MAX_INRD = 8500; // 1 -static const uint64_t SH_FLD_GZIPDECOMP_MAX_INRD_LEN = 8501; // 1 -static const uint64_t SH_FLD_GZIP_COMP_PREFETCH_ENABLE = 8502; // 1 -static const uint64_t SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE = 8503; // 1 -static const uint64_t SH_FLD_GZIP_FC_SELECT = 8504; // 1 -static const uint64_t SH_FLD_GZIP_FC_SELECT_LEN = 8505; // 1 -static const uint64_t SH_FLD_GZIP_LATENCY_CFG = 8506; // 1 -static const uint64_t SH_FLD_GZIP_MUX_SELECT = 8507; // 1 -static const uint64_t SH_FLD_GZIP_MUX_SELECT_LEN = 8508; // 1 -static const uint64_t SH_FLD_H1AP_CFG = 8509; // 6 -static const uint64_t SH_FLD_H1AP_CFG_LEN = 8510; // 6 -static const uint64_t SH_FLD_HALTED = 8511; // 1 -static const uint64_t SH_FLD_HALT_INPUT = 8512; // 1 -static const uint64_t SH_FLD_HALT_ON_TRIG = 8513; // 17 -static const uint64_t SH_FLD_HALT_ON_XSTOP = 8514; // 17 -static const uint64_t SH_FLD_HALT_ROTATION = 8515; // 8 -static const uint64_t SH_FLD_HANG_DATA_SCALE = 8516; // 5 -static const uint64_t SH_FLD_HANG_DATA_SCALE_LEN = 8517; // 5 -static const uint64_t SH_FLD_HANG_ON_ACK_DEAD = 8518; // 1 -static const uint64_t SH_FLD_HANG_ON_ADDR_ERROR = 8519; // 1 -static const uint64_t SH_FLD_HANG_PE_SCALE = 8520; // 3 -static const uint64_t SH_FLD_HANG_PE_SCALE_LEN = 8521; // 3 -static const uint64_t SH_FLD_HANG_PIB_RESET = 8522; // 1 -static const uint64_t SH_FLD_HANG_PLS_MULT = 8523; // 1 -static const uint64_t SH_FLD_HANG_PLS_MULT_LEN = 8524; // 1 -static const uint64_t SH_FLD_HANG_POLL_ENABLE = 8525; // 2 -static const uint64_t SH_FLD_HANG_POLL_PULSE_DIV = 8526; // 24 -static const uint64_t SH_FLD_HANG_POLL_PULSE_DIV_LEN = 8527; // 24 -static const uint64_t SH_FLD_HANG_POLL_SCALE = 8528; // 7 -static const uint64_t SH_FLD_HANG_POLL_SCALE_LEN = 8529; // 7 -static const uint64_t SH_FLD_HANG_RECOVERY_GTE_LEVEL1 = 8530; // 2 -static const uint64_t SH_FLD_HANG_RECOVERY_LIMIT_ERROR = 8531; // 2 -static const uint64_t SH_FLD_HANG_RESET = 8532; // 1 -static const uint64_t SH_FLD_HANG_SHM_SCALE = 8533; // 2 -static const uint64_t SH_FLD_HANG_SHM_SCALE_LEN = 8534; // 2 -static const uint64_t SH_FLD_HANG_SM_ON_ARE = 8535; // 2 -static const uint64_t SH_FLD_HANG_SM_ON_LINK_FAIL = 8536; // 2 -static const uint64_t SH_FLD_HARD_CE_COUNT = 8537; // 2 -static const uint64_t SH_FLD_HARD_CE_COUNT_LEN = 8538; // 2 -static const uint64_t SH_FLD_HARD_MCE_COUNT = 8539; // 2 -static const uint64_t SH_FLD_HARD_MCE_COUNT_LEN = 8540; // 2 -static const uint64_t SH_FLD_HARD_NCE_ETE_ATTN = 8541; // 2 -static const uint64_t SH_FLD_HASH_LPID_DIS = 8542; // 1 -static const uint64_t SH_FLD_HASH_PID_DIS = 8543; // 1 -static const uint64_t SH_FLD_HASH_SIZE_MASK = 8544; // 1 -static const uint64_t SH_FLD_HASH_SIZE_MASK_LEN = 8545; // 1 -static const uint64_t SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS = 8546; // 4 -static const uint64_t SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS = 8547; // 4 -static const uint64_t SH_FLD_HB_ERROR = 8548; // 1 -static const uint64_t SH_FLD_HB_MALF_MASK = 8549; // 1 -static const uint64_t SH_FLD_HDICE = 8550; // 96 -static const uint64_t SH_FLD_HDR_ARR_ECC_CORR_ENA = 8551; // 6 -static const uint64_t SH_FLD_HDR_ARR_ECC_SUE_ENA = 8552; // 6 -static const uint64_t SH_FLD_HI = 8553; // 1 -static const uint64_t SH_FLD_HIGH = 8554; // 1 -static const uint64_t SH_FLD_HIGH_IDLE_COUNT = 8555; // 8 -static const uint64_t SH_FLD_HIGH_IDLE_COUNT_LEN = 8556; // 8 -static const uint64_t SH_FLD_HIGH_IDLE_THRESHOLD = 8557; // 8 -static const uint64_t SH_FLD_HIGH_IDLE_THRESHOLD_LEN = 8558; // 8 -static const uint64_t SH_FLD_HIGH_LEN = 8559; // 1 -static const uint64_t SH_FLD_HILE = 8560; // 24 -static const uint64_t SH_FLD_HIRES_FMAX = 8561; // 6 -static const uint64_t SH_FLD_HIRES_FMAX_LEN = 8562; // 6 -static const uint64_t SH_FLD_HIRES_FMIN = 8563; // 6 -static const uint64_t SH_FLD_HIRES_FMIN_LEN = 8564; // 6 -static const uint64_t SH_FLD_HIRES_FMULT = 8565; // 6 -static const uint64_t SH_FLD_HIRES_FMULT_LEN = 8566; // 6 -static const uint64_t SH_FLD_HIRES_FREQIN_AVG = 8567; // 6 -static const uint64_t SH_FLD_HIRES_FREQIN_AVG_LEN = 8568; // 6 -static const uint64_t SH_FLD_HIRES_FREQIN_MAX = 8569; // 6 -static const uint64_t SH_FLD_HIRES_FREQIN_MAX_LEN = 8570; // 6 -static const uint64_t SH_FLD_HIRES_FREQIN_MIN = 8571; // 6 -static const uint64_t SH_FLD_HIRES_FREQIN_MIN_LEN = 8572; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT = 8573; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_AVG = 8574; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_AVG_LEN = 8575; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_LEN = 8576; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_MAX = 8577; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_MAX_LEN = 8578; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_MIN = 8579; // 6 -static const uint64_t SH_FLD_HIRES_FREQOUT_MIN_LEN = 8580; // 6 -static const uint64_t SH_FLD_HIST = 8581; // 6 -static const uint64_t SH_FLD_HISTORY_PRBS_POWER_UP = 8582; // 72 -static const uint64_t SH_FLD_HIST_ADDRESS = 8583; // 1 -static const uint64_t SH_FLD_HIST_ADDRESS_LEN = 8584; // 1 -static const uint64_t SH_FLD_HIST_DONE = 8585; // 1 -static const uint64_t SH_FLD_HIST_FREEZE_HISTORY = 8586; // 1 -static const uint64_t SH_FLD_HIST_LEN = 8587; // 6 -static const uint64_t SH_FLD_HIST_MANUAL_MODE_EN = 8588; // 1 -static const uint64_t SH_FLD_HIST_MASK = 8589; // 1 -static const uint64_t SH_FLD_HIST_MASK_LEN = 8590; // 1 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT = 8591; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE = 8592; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN = 8593; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LEN = 8594; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE = 8595; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN = 8596; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_VALID = 8597; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH = 8598; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE = 8599; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN = 8600; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LEN = 8601; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE = 8602; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN = 8603; // 6 -static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_VALID = 8604; // 6 -static const uint64_t SH_FLD_HIST_RESERVED = 8605; // 1 -static const uint64_t SH_FLD_HIST_RESERVED_LEN = 8606; // 1 -static const uint64_t SH_FLD_HIST_RESET_HISTORY = 8607; // 1 -static const uint64_t SH_FLD_HIST_START_NOT_STOP = 8608; // 1 -static const uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT = 8609; // 1 -static const uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT_LEN = 8610; // 1 -static const uint64_t SH_FLD_HIST_TRACE_TRAFFIC = 8611; // 1 -static const uint64_t SH_FLD_HI_ENABLE = 8612; // 2 -static const uint64_t SH_FLD_HI_FIXED_WINDOW_MODE = 8613; // 2 -static const uint64_t SH_FLD_HI_PRESCALE_MODE = 8614; // 2 -static const uint64_t SH_FLD_HI_SELECT = 8615; // 2 -static const uint64_t SH_FLD_HI_SELECT_LEN = 8616; // 2 -static const uint64_t SH_FLD_HMI_ACTIVE = 8617; // 1 -static const uint64_t SH_FLD_HMI_EXIT_ENABLE = 8618; // 96 -static const uint64_t SH_FLD_HMI_REQUEST_C0 = 8619; // 12 -static const uint64_t SH_FLD_HMI_REQUEST_C1 = 8620; // 12 -static const uint64_t SH_FLD_HOLD = 8621; // 2 -static const uint64_t SH_FLD_HOLD_0 = 8622; // 8 -static const uint64_t SH_FLD_HOLD_0_48 = 8623; // 1 -static const uint64_t SH_FLD_HOLD_0_48_LEN = 8624; // 1 -static const uint64_t SH_FLD_HOLD_1 = 8625; // 8 -static const uint64_t SH_FLD_HOLD_ADDRESS = 8626; // 90 -static const uint64_t SH_FLD_HOLD_ADDRESS_LEN = 8627; // 90 -static const uint64_t SH_FLD_HOLD_DBGTRIG_SEL = 8628; // 43 -static const uint64_t SH_FLD_HOLD_DBGTRIG_SEL_LEN = 8629; // 43 -static const uint64_t SH_FLD_HOLD_LEN = 8630; // 2 -static const uint64_t SH_FLD_HOLD_SAMPLE = 8631; // 43 -static const uint64_t SH_FLD_HOLD_SAMPLE_WITH_TRIGGER = 8632; // 43 -static const uint64_t SH_FLD_HOLE0_LOWER_ADDRESS = 8633; // 8 -static const uint64_t SH_FLD_HOLE0_LOWER_ADDRESS_LEN = 8634; // 8 -static const uint64_t SH_FLD_HOLE0_UPPER_ADDRESS = 8635; // 8 -static const uint64_t SH_FLD_HOLE0_UPPER_ADDRESS_LEN = 8636; // 8 -static const uint64_t SH_FLD_HOLE0_VALID = 8637; // 8 -static const uint64_t SH_FLD_HOLE1_LOWER_ADDRESS = 8638; // 8 -static const uint64_t SH_FLD_HOLE1_LOWER_ADDRESS_LEN = 8639; // 8 -static const uint64_t SH_FLD_HOLE1_UPPER_ADDRESS = 8640; // 8 -static const uint64_t SH_FLD_HOLE1_UPPER_ADDRESS_LEN = 8641; // 8 -static const uint64_t SH_FLD_HOLE1_VALID = 8642; // 8 -static const uint64_t SH_FLD_HOST_PREF_PGSZ = 8643; // 1 -static const uint64_t SH_FLD_HOST_PREF_PGSZ_LEN = 8644; // 1 -static const uint64_t SH_FLD_HRMOR = 8645; // 1 -static const uint64_t SH_FLD_HRMOR_LEN = 8646; // 1 -static const uint64_t SH_FLD_HSSCALERR = 8647; // 6 -static const uint64_t SH_FLD_HSSPLLAERR = 8648; // 6 -static const uint64_t SH_FLD_HSSPLLBERR = 8649; // 6 -static const uint64_t SH_FLD_HS_PROBE_TOP_SEL = 8650; // 8 -static const uint64_t SH_FLD_HTB_EXTEST = 8651; // 43 -static const uint64_t SH_FLD_HTB_INTEST = 8652; // 43 -static const uint64_t SH_FLD_HTMCO_STATUS_ADDR_ERROR = 8653; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_BUF_WAIT = 8654; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_COMPLETE = 8655; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_CRESP_OV = 8656; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_ENABLE = 8657; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_FLUSH = 8658; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_INIT = 8659; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_PAUSED = 8660; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_PREREQ = 8661; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_PURGE_DONE = 8662; // 24 -static const uint64_t SH_FLD_HTMCO_STATUS_PURGE_IN_PROG = 8663; // 24 -static const uint64_t SH_FLD_HTMCO_STATUS_READY = 8664; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_REPAIR = 8665; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_SPARE = 8666; // 2 -static const uint64_t SH_FLD_HTMCO_STATUS_SPARE_LEN = 8667; // 2 -static const uint64_t SH_FLD_HTMCO_STATUS_STAMP = 8668; // 26 -static const uint64_t SH_FLD_HTMCO_STATUS_TRACING = 8669; // 26 -static const uint64_t SH_FLD_HTMSC = 8670; // 24 -static const uint64_t SH_FLD_HTMSC_ALLOC = 8671; // 26 -static const uint64_t SH_FLD_HTMSC_BASE = 8672; // 26 -static const uint64_t SH_FLD_HTMSC_BASE_LEN = 8673; // 26 -static const uint64_t SH_FLD_HTMSC_CAPTURE = 8674; // 26 -static const uint64_t SH_FLD_HTMSC_CAPTURE_LEN = 8675; // 26 -static const uint64_t SH_FLD_HTMSC_CHIP0_STOP = 8676; // 24 -static const uint64_t SH_FLD_HTMSC_CHIP1_STOP = 8677; // 24 -static const uint64_t SH_FLD_HTMSC_CONTENT_SEL = 8678; // 26 -static const uint64_t SH_FLD_HTMSC_CONTENT_SEL_LEN = 8679; // 26 -static const uint64_t SH_FLD_HTMSC_COUNT = 8680; // 24 -static const uint64_t SH_FLD_HTMSC_COUNT_LEN = 8681; // 24 -static const uint64_t SH_FLD_HTMSC_CRESPFILT_INVERT = 8682; // 2 -static const uint64_t SH_FLD_HTMSC_CRESP_MASK = 8683; // 2 -static const uint64_t SH_FLD_HTMSC_CRESP_MASK_LEN = 8684; // 2 -static const uint64_t SH_FLD_HTMSC_CRESP_PAT = 8685; // 2 -static const uint64_t SH_FLD_HTMSC_CRESP_PAT_LEN = 8686; // 2 -static const uint64_t SH_FLD_HTMSC_DBG0_STOP = 8687; // 26 -static const uint64_t SH_FLD_HTMSC_DBG1_STOP = 8688; // 26 -static const uint64_t SH_FLD_HTMSC_DD1EQUIV = 8689; // 24 -static const uint64_t SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR = 8690; // 2 -static const uint64_t SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE = 8691; // 2 -static const uint64_t SH_FLD_HTMSC_DIS_GROUP = 8692; // 24 -static const uint64_t SH_FLD_HTMSC_DIS_OPER_HANG = 8693; // 2 -static const uint64_t SH_FLD_HTMSC_DIS_RETRY_BACKOFF = 8694; // 2 -static const uint64_t SH_FLD_HTMSC_DIS_STALL = 8695; // 24 -static const uint64_t SH_FLD_HTMSC_DIS_TSTAMP = 8696; // 26 -static const uint64_t SH_FLD_HTMSC_ENABLE = 8697; // 26 -static const uint64_t SH_FLD_HTMSC_ENABLE_SPLIT_CORE = 8698; // 24 -static const uint64_t SH_FLD_HTMSC_ERROR = 8699; // 24 -static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0 = 8700; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN = 8701; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1 = 8702; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN = 8703; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2 = 8704; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN = 8705; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0 = 8706; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN = 8707; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1 = 8708; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN = 8709; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2 = 8710; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN = 8711; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3 = 8712; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN = 8713; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4 = 8714; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN = 8715; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5 = 8716; // 2 -static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN = 8717; // 2 -static const uint64_t SH_FLD_HTMSC_FSM = 8718; // 24 -static const uint64_t SH_FLD_HTMSC_FSM_LEN = 8719; // 24 -static const uint64_t SH_FLD_HTMSC_INVERT = 8720; // 2 -static const uint64_t SH_FLD_HTMSC_LEN = 8721; // 24 -static const uint64_t SH_FLD_HTMSC_MARK = 8722; // 26 -static const uint64_t SH_FLD_HTMSC_MARKERS_ONLY = 8723; // 26 -static const uint64_t SH_FLD_HTMSC_MARK_LEN = 8724; // 26 -static const uint64_t SH_FLD_HTMSC_MARK_TYPE = 8725; // 26 -static const uint64_t SH_FLD_HTMSC_MARK_TYPE_LEN = 8726; // 26 -static const uint64_t SH_FLD_HTMSC_MARK_VALID = 8727; // 26 -static const uint64_t SH_FLD_HTMSC_MASK = 8728; // 4 -static const uint64_t SH_FLD_HTMSC_MASK_LEN = 8729; // 4 -static const uint64_t SH_FLD_HTMSC_MTSPR_MARK = 8730; // 24 -static const uint64_t SH_FLD_HTMSC_MTSPR_TRIG = 8731; // 24 -static const uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO = 8732; // 2 -static const uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN = 8733; // 2 -static const uint64_t SH_FLD_HTMSC_OTHER_DBG0_STOP = 8734; // 2 -static const uint64_t SH_FLD_HTMSC_PAT = 8735; // 4 -static const uint64_t SH_FLD_HTMSC_PAT_LEN = 8736; // 4 -static const uint64_t SH_FLD_HTMSC_PAUSE = 8737; // 26 -static const uint64_t SH_FLD_HTMSC_PDBAR_ERROR = 8738; // 24 -static const uint64_t SH_FLD_HTMSC_PRIORITY = 8739; // 26 -static const uint64_t SH_FLD_HTMSC_RESERVED = 8740; // 24 -static const uint64_t SH_FLD_HTMSC_RESERVED_LEN = 8741; // 24 -static const uint64_t SH_FLD_HTMSC_RESET = 8742; // 26 -static const uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT = 8743; // 2 -static const uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT_LEN = 8744; // 2 -static const uint64_t SH_FLD_HTMSC_RUN_STOP = 8745; // 26 -static const uint64_t SH_FLD_HTMSC_SCOPE = 8746; // 50 -static const uint64_t SH_FLD_HTMSC_SCOPE_LEN = 8747; // 50 -static const uint64_t SH_FLD_HTMSC_SINGLE_TSTAMP = 8748; // 26 -static const uint64_t SH_FLD_HTMSC_SIZE = 8749; // 26 -static const uint64_t SH_FLD_HTMSC_SIZE_LEN = 8750; // 26 -static const uint64_t SH_FLD_HTMSC_SIZE_SMALL = 8751; // 26 -static const uint64_t SH_FLD_HTMSC_SPARE = 8752; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE0 = 8753; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE1012 = 8754; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE1012_LEN = 8755; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE1112 = 8756; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE1112_LEN = 8757; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE1415 = 8758; // 26 -static const uint64_t SH_FLD_HTMSC_SPARE1415_LEN = 8759; // 26 -static const uint64_t SH_FLD_HTMSC_SPARE16 = 8760; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE23 = 8761; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE2TO4 = 8762; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE2TO4_LEN = 8763; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE3 = 8764; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE4043 = 8765; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE4043_LEN = 8766; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE67 = 8767; // 2 -static const uint64_t SH_FLD_HTMSC_SPARE67_LEN = 8768; // 2 -static const uint64_t SH_FLD_HTMSC_SPARES = 8769; // 24 -static const uint64_t SH_FLD_HTMSC_SPARES_LEN = 8770; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE_1TO2 = 8771; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE_1TO2_LEN = 8772; // 24 -static const uint64_t SH_FLD_HTMSC_SPARE_LEN = 8773; // 24 -static const uint64_t SH_FLD_HTMSC_START = 8774; // 26 -static const uint64_t SH_FLD_HTMSC_STOP = 8775; // 26 -static const uint64_t SH_FLD_HTMSC_STOP_ALT = 8776; // 26 -static const uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE = 8777; // 2 -static const uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN = 8778; // 2 -static const uint64_t SH_FLD_HTMSC_TRACE_ACTIVE = 8779; // 24 -static const uint64_t SH_FLD_HTMSC_TRIG = 8780; // 26 -static const uint64_t SH_FLD_HTMSC_TRIG_LEN = 8781; // 26 -static const uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK = 8782; // 2 -static const uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK_LEN = 8783; // 2 -static const uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT = 8784; // 2 -static const uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT_LEN = 8785; // 2 -static const uint64_t SH_FLD_HTMSC_VGTARGET = 8786; // 26 -static const uint64_t SH_FLD_HTMSC_VGTARGET_LEN = 8787; // 26 -static const uint64_t SH_FLD_HTMSC_WRAP = 8788; // 26 -static const uint64_t SH_FLD_HTMSC_WRITETOIO = 8789; // 2 -static const uint64_t SH_FLD_HTMSC_XSTOP_STOP = 8790; // 26 -static const uint64_t SH_FLD_HTM_CMD_OVERRUN = 8791; // 1 -static const uint64_t SH_FLD_HTM_GPE_SRC_SEL = 8792; // 1 -static const uint64_t SH_FLD_HTM_GPE_SRC_SEL_LEN = 8793; // 1 -static const uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS = 8794; // 1 -static const uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN = 8795; // 1 -static const uint64_t SH_FLD_HTM_QUEUE_LIMIT = 8796; // 12 -static const uint64_t SH_FLD_HTM_QUEUE_LIMIT_LEN = 8797; // 12 -static const uint64_t SH_FLD_HTM_SRC_SEL = 8798; // 1 -static const uint64_t SH_FLD_HTM_SRC_SEL_LEN = 8799; // 1 -static const uint64_t SH_FLD_HTM_STOP = 8800; // 1 -static const uint64_t SH_FLD_HTM_TRACE_MODE = 8801; // 1 -static const uint64_t SH_FLD_HUC = 8802; // 1 -static const uint64_t SH_FLD_HUC_LEN = 8803; // 1 -static const uint64_t SH_FLD_HUT = 8804; // 1 -static const uint64_t SH_FLD_HUT_LEN = 8805; // 1 -static const uint64_t SH_FLD_HWCTRL = 8806; // 2 -static const uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER = 8807; // 1 -static const uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN = 8808; // 1 -static const uint64_t SH_FLD_HWCTRL_CPHA = 8809; // 1 -static const uint64_t SH_FLD_HWCTRL_CPOL = 8810; // 1 -static const uint64_t SH_FLD_HWCTRL_DEVICE = 8811; // 1 -static const uint64_t SH_FLD_HWCTRL_FRAME_SIZE = 8812; // 1 -static const uint64_t SH_FLD_HWCTRL_FRAME_SIZE_LEN = 8813; // 1 -static const uint64_t SH_FLD_HWCTRL_FSM_ENABLE = 8814; // 1 -static const uint64_t SH_FLD_HWCTRL_FSM_ERR = 8815; // 1 -static const uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY = 8816; // 1 -static const uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN = 8817; // 1 -static const uint64_t SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES = 8818; // 1 -static const uint64_t SH_FLD_HWCTRL_IN_COUNT = 8819; // 1 -static const uint64_t SH_FLD_HWCTRL_IN_COUNT_LEN = 8820; // 1 -static const uint64_t SH_FLD_HWCTRL_IN_DELAY = 8821; // 1 -static const uint64_t SH_FLD_HWCTRL_IN_DELAY_LEN = 8822; // 1 -static const uint64_t SH_FLD_HWCTRL_LEN = 8823; // 2 -static const uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES = 8824; // 1 -static const uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES_LEN = 8825; // 1 -static const uint64_t SH_FLD_HWCTRL_ONGOING = 8826; // 1 -static const uint64_t SH_FLD_HWCTRL_OUT_COUNT = 8827; // 1 -static const uint64_t SH_FLD_HWCTRL_OUT_COUNT_LEN = 8828; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA0 = 8829; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA0_LEN = 8830; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA1 = 8831; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA1_LEN = 8832; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA2 = 8833; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA2_LEN = 8834; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA3 = 8835; // 1 -static const uint64_t SH_FLD_HWCTRL_RDATA3_LEN = 8836; // 1 -static const uint64_t SH_FLD_HWCTRL_START_SAMPLING = 8837; // 1 -static const uint64_t SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 8838; // 1 -static const uint64_t SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 8839; // 1 -static const uint64_t SH_FLD_HWD = 8840; // 1 -static const uint64_t SH_FLD_HWD_0 = 8841; // 1 -static const uint64_t SH_FLD_HWD_0_LEN = 8842; // 1 -static const uint64_t SH_FLD_HWD_10 = 8843; // 1 -static const uint64_t SH_FLD_HWD_10_LEN = 8844; // 1 -static const uint64_t SH_FLD_HWD_11 = 8845; // 1 -static const uint64_t SH_FLD_HWD_11_LEN = 8846; // 1 -static const uint64_t SH_FLD_HWD_12 = 8847; // 1 -static const uint64_t SH_FLD_HWD_12_LEN = 8848; // 1 -static const uint64_t SH_FLD_HWD_13 = 8849; // 1 -static const uint64_t SH_FLD_HWD_13_LEN = 8850; // 1 -static const uint64_t SH_FLD_HWD_14 = 8851; // 1 -static const uint64_t SH_FLD_HWD_14_LEN = 8852; // 1 -static const uint64_t SH_FLD_HWD_15 = 8853; // 1 -static const uint64_t SH_FLD_HWD_15_LEN = 8854; // 1 -static const uint64_t SH_FLD_HWD_2 = 8855; // 1 -static const uint64_t SH_FLD_HWD_2_LEN = 8856; // 1 -static const uint64_t SH_FLD_HWD_3 = 8857; // 1 -static const uint64_t SH_FLD_HWD_3_LEN = 8858; // 1 -static const uint64_t SH_FLD_HWD_4 = 8859; // 1 -static const uint64_t SH_FLD_HWD_4_LEN = 8860; // 1 -static const uint64_t SH_FLD_HWD_5 = 8861; // 1 -static const uint64_t SH_FLD_HWD_5_LEN = 8862; // 1 -static const uint64_t SH_FLD_HWD_6 = 8863; // 1 -static const uint64_t SH_FLD_HWD_6_LEN = 8864; // 1 -static const uint64_t SH_FLD_HWD_7 = 8865; // 1 -static const uint64_t SH_FLD_HWD_7_LEN = 8866; // 1 -static const uint64_t SH_FLD_HWD_8 = 8867; // 1 -static const uint64_t SH_FLD_HWD_8_LEN = 8868; // 1 -static const uint64_t SH_FLD_HWD_9 = 8869; // 1 -static const uint64_t SH_FLD_HWD_9_LEN = 8870; // 1 -static const uint64_t SH_FLD_HWD_LEN = 8871; // 1 -static const uint64_t SH_FLD_HWD_PRIORITY = 8872; // 1 -static const uint64_t SH_FLD_HWD_PRIORITY_LEN = 8873; // 1 -static const uint64_t SH_FLD_HWD_RSD = 8874; // 1 -static const uint64_t SH_FLD_HWD_RSD_LEN = 8875; // 1 -static const uint64_t SH_FLD_HWMSX_PE = 8876; // 8 -static const uint64_t SH_FLD_HWMSX_PE_LEN = 8877; // 8 -static const uint64_t SH_FLD_HW_CONTROL_ERROR = 8878; // 12 -static const uint64_t SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 8879; // 12 -static const uint64_t SH_FLD_HW_PARITY_ERROR = 8880; // 2 -static const uint64_t SH_FLD_HYPERVISOR = 8881; // 4 -static const uint64_t SH_FLD_HYP_BLOCK = 8882; // 24 -static const uint64_t SH_FLD_HYP_BLOCK_LEN = 8883; // 24 -static const uint64_t SH_FLD_HYP_RECOURCE_ERR = 8884; // 96 -static const uint64_t SH_FLD_HYP_SPECIAL_WKUP = 8885; // 30 -static const uint64_t SH_FLD_HYP_VIRT_EXIT_ENABLE = 8886; // 96 -static const uint64_t SH_FLD_I2CM_ECC_ERRORS = 8887; // 1 -static const uint64_t SH_FLD_I2CM_ECC_ERRORS_LEN = 8888; // 1 -static const uint64_t SH_FLD_I2CM_I2C_ERRORS = 8889; // 1 -static const uint64_t SH_FLD_I2CM_I2C_ERRORS_LEN = 8890; // 1 -static const uint64_t SH_FLD_I2CM_INTER = 8891; // 1 -static const uint64_t SH_FLD_I2CM_INTR_STATUS = 8892; // 1 -static const uint64_t SH_FLD_I2CM_INTR_STATUS_LEN = 8893; // 1 -static const uint64_t SH_FLD_I2CM_PIB_ERRORS = 8894; // 1 -static const uint64_t SH_FLD_I2CM_PIB_ERRORS_LEN = 8895; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0 = 8896; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN = 8897; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1 = 8898; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN = 8899; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2 = 8900; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN = 8901; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3 = 8902; // 1 -static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN = 8903; // 1 -static const uint64_t SH_FLD_I2CM_TPM_DECONFIG_PROTECT = 8904; // 1 -static const uint64_t SH_FLD_I2C_BUS_HELD_MODE_ENABLE = 8905; // 1 -static const uint64_t SH_FLD_I2C_SPEED_MUX = 8906; // 1 -static const uint64_t SH_FLD_I2C_SPEED_MUX_LEN = 8907; // 1 -static const uint64_t SH_FLD_I2C_TIMEOUT_VALUE = 8908; // 1 -static const uint64_t SH_FLD_I2C_TIMEOUT_VALUE_LEN = 8909; // 1 -static const uint64_t SH_FLD_IBUF_ABANK = 8910; // 3 -static const uint64_t SH_FLD_IBUF_ABANK_LEN = 8911; // 3 -static const uint64_t SH_FLD_IBUF_AIDX = 8912; // 3 -static const uint64_t SH_FLD_IBUF_AIDX_LEN = 8913; // 3 -static const uint64_t SH_FLD_IBUF_RSRC = 8914; // 3 -static const uint64_t SH_FLD_IBUF_RSRC_LEN = 8915; // 3 -static const uint64_t SH_FLD_IBUF_WSRC = 8916; // 3 -static const uint64_t SH_FLD_IBUF_WSRC_LEN = 8917; // 3 -static const uint64_t SH_FLD_IBWR_MASK = 8918; // 3 -static const uint64_t SH_FLD_IBWR_MASK_LEN = 8919; // 3 -static const uint64_t SH_FLD_ICACHE_ERR = 8920; // 21 -static const uint64_t SH_FLD_ICACHE_PARITY_ERROR_INJECT = 8921; // 24 -static const uint64_t SH_FLD_ICACHE_TAG_ADDR = 8922; // 21 -static const uint64_t SH_FLD_ICACHE_TAG_ADDR_LEN = 8923; // 21 -static const uint64_t SH_FLD_ICACHE_VALID = 8924; // 21 -static const uint64_t SH_FLD_ICACHE_VALID_LEN = 8925; // 21 -static const uint64_t SH_FLD_ICE_COUNT = 8926; // 2 -static const uint64_t SH_FLD_ICE_COUNT_LEN = 8927; // 2 -static const uint64_t SH_FLD_ICE_ETE_ATTN = 8928; // 2 -static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_IN = 8929; // 12 -static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN = 8930; // 12 -static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_OUT = 8931; // 12 -static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN = 8932; // 12 -static const uint64_t SH_FLD_ICS_INVALID_STATE = 8933; // 1 -static const uint64_t SH_FLD_ICU_RNW = 8934; // 1 -static const uint64_t SH_FLD_ICU_TIMEOUT_ERROR = 8935; // 1 -static const uint64_t SH_FLD_ID = 8936; // 131 -static const uint64_t SH_FLD_IDIAL = 8937; // 35 -static const uint64_t SH_FLD_IDIAL_AMO_ADDR = 8938; // 3 -static const uint64_t SH_FLD_IDIAL_ATS = 8939; // 1 -static const uint64_t SH_FLD_IDIAL_ATS_ESR_MSK = 8940; // 1 -static const uint64_t SH_FLD_IDIAL_ATS_ESR_MSK_LEN = 8941; // 1 -static const uint64_t SH_FLD_IDIAL_ATS_FER_MSK = 8942; // 1 -static const uint64_t SH_FLD_IDIAL_ATS_FER_MSK_LEN = 8943; // 1 -static const uint64_t SH_FLD_IDIAL_ATS_LEN = 8944; // 1 -static const uint64_t SH_FLD_IDIAL_BBRD = 8945; // 3 -static const uint64_t SH_FLD_IDIAL_BBRD_LEN = 8946; // 3 -static const uint64_t SH_FLD_IDIAL_BBUF_RDWR = 8947; // 3 -static const uint64_t SH_FLD_IDIAL_BR_CE = 8948; // 3 -static const uint64_t SH_FLD_IDIAL_BR_CE_LEN = 8949; // 3 -static const uint64_t SH_FLD_IDIAL_BR_SUE = 8950; // 3 -static const uint64_t SH_FLD_IDIAL_BR_SUE_LEN = 8951; // 3 -static const uint64_t SH_FLD_IDIAL_BR_UE = 8952; // 3 -static const uint64_t SH_FLD_IDIAL_BR_UE_LEN = 8953; // 3 -static const uint64_t SH_FLD_IDIAL_CNTL_ERRP = 8954; // 1 -static const uint64_t SH_FLD_IDIAL_CONFIG1 = 8955; // 3 -static const uint64_t SH_FLD_IDIAL_COUNT0 = 8956; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT0_LEN = 8957; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT1 = 8958; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT1_LEN = 8959; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT2 = 8960; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT2_LEN = 8961; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT3 = 8962; // 9 -static const uint64_t SH_FLD_IDIAL_COUNT3_LEN = 8963; // 9 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_0 = 8964; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_1 = 8965; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_2 = 8966; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_3 = 8967; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_4 = 8968; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_5 = 8969; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_6 = 8970; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_7 = 8971; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_0 = 8972; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_1 = 8973; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_2 = 8974; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_3 = 8975; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_4 = 8976; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_5 = 8977; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_6 = 8978; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_7 = 8979; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_0 = 8980; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_1 = 8981; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_2 = 8982; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_3 = 8983; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_0 = 8984; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_1 = 8985; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_2 = 8986; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_3 = 8987; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_4 = 8988; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_5 = 8989; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_6 = 8990; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_7 = 8991; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_0 = 8992; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_1 = 8993; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_2 = 8994; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_3 = 8995; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_4 = 8996; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_5 = 8997; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_6 = 8998; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_7 = 8999; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_0 = 9000; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_1 = 9001; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_10 = 9002; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_11 = 9003; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_12 = 9004; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_13 = 9005; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_14 = 9006; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_15 = 9007; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_2 = 9008; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_3 = 9009; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_4 = 9010; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_5 = 9011; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_6 = 9012; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_7 = 9013; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_8 = 9014; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_9 = 9015; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_0 = 9016; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_1 = 9017; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_10 = 9018; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_11 = 9019; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_12 = 9020; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_13 = 9021; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_14 = 9022; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_15 = 9023; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_16 = 9024; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_17 = 9025; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_18 = 9026; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_19 = 9027; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_2 = 9028; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_20 = 9029; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_21 = 9030; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_22 = 9031; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_23 = 9032; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_3 = 9033; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_4 = 9034; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_5 = 9035; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_6 = 9036; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_7 = 9037; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_8 = 9038; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_9 = 9039; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_0 = 9040; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_1 = 9041; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_2 = 9042; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_3 = 9043; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_4 = 9044; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_5 = 9045; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_6 = 9046; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_7 = 9047; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_0 = 9048; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_1 = 9049; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_2 = 9050; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_3 = 9051; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_4 = 9052; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_5 = 9053; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_6 = 9054; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_7 = 9055; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_0 = 9056; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_1 = 9057; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_2 = 9058; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_3 = 9059; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_4 = 9060; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_5 = 9061; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_6 = 9062; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_7 = 9063; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_0 = 9064; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_1 = 9065; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_2 = 9066; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_3 = 9067; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_4 = 9068; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_5 = 9069; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_6 = 9070; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_7 = 9071; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_0 = 9072; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_1 = 9073; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_2 = 9074; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_3 = 9075; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_0 = 9076; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_1 = 9077; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_2 = 9078; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_3 = 9079; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_0 = 9080; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_1 = 9081; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_2 = 9082; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_3 = 9083; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_0 = 9084; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_1 = 9085; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_2 = 9086; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_3 = 9087; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_0 = 9088; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_1 = 9089; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_2 = 9090; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_3 = 9091; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_0 = 9092; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_1 = 9093; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_2 = 9094; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_3 = 9095; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_4 = 9096; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_5 = 9097; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_6 = 9098; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_7 = 9099; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_0 = 9100; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_1 = 9101; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_2 = 9102; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_3 = 9103; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_4 = 9104; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_5 = 9105; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_6 = 9106; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_7 = 9107; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_0 = 9108; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_1 = 9109; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_2 = 9110; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_3 = 9111; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_0 = 9112; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_1 = 9113; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_2 = 9114; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_3 = 9115; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_4 = 9116; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_5 = 9117; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_6 = 9118; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_7 = 9119; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_0 = 9120; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_1 = 9121; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_2 = 9122; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_3 = 9123; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_4 = 9124; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_5 = 9125; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_6 = 9126; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_7 = 9127; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_0 = 9128; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_1 = 9129; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_10 = 9130; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_11 = 9131; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_12 = 9132; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_13 = 9133; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_14 = 9134; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_15 = 9135; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_2 = 9136; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_3 = 9137; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_4 = 9138; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_5 = 9139; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_6 = 9140; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_7 = 9141; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_8 = 9142; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_9 = 9143; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_0 = 9144; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_1 = 9145; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_10 = 9146; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_11 = 9147; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_12 = 9148; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_13 = 9149; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_14 = 9150; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_15 = 9151; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_16 = 9152; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_17 = 9153; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_18 = 9154; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_19 = 9155; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_2 = 9156; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_20 = 9157; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_21 = 9158; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_22 = 9159; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_23 = 9160; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_3 = 9161; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_4 = 9162; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_5 = 9163; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_6 = 9164; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_7 = 9165; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_8 = 9166; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_9 = 9167; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_0 = 9168; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_1 = 9169; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_2 = 9170; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_3 = 9171; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_4 = 9172; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_5 = 9173; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_6 = 9174; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_7 = 9175; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_0 = 9176; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_1 = 9177; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_2 = 9178; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_3 = 9179; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_4 = 9180; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_5 = 9181; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_6 = 9182; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_7 = 9183; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_0 = 9184; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_1 = 9185; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_2 = 9186; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_3 = 9187; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_4 = 9188; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_5 = 9189; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_6 = 9190; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_7 = 9191; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_0 = 9192; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_1 = 9193; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_2 = 9194; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_3 = 9195; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_4 = 9196; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_5 = 9197; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_6 = 9198; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_7 = 9199; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_0 = 9200; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_1 = 9201; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_2 = 9202; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_3 = 9203; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_0 = 9204; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_1 = 9205; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_2 = 9206; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_3 = 9207; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_0 = 9208; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_1 = 9209; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_2 = 9210; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_3 = 9211; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_0 = 9212; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_1 = 9213; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_2 = 9214; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_3 = 9215; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_0 = 9216; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_1 = 9217; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_2 = 9218; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_3 = 9219; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_0 = 9220; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_1 = 9221; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_2 = 9222; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_3 = 9223; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_4 = 9224; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_5 = 9225; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_6 = 9226; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_7 = 9227; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_0 = 9228; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_1 = 9229; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_2 = 9230; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_3 = 9231; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_4 = 9232; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_5 = 9233; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_6 = 9234; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_7 = 9235; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_0 = 9236; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_1 = 9237; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_2 = 9238; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_3 = 9239; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_0 = 9240; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_1 = 9241; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_2 = 9242; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_3 = 9243; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_4 = 9244; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_5 = 9245; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_6 = 9246; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_7 = 9247; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_0 = 9248; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_1 = 9249; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_2 = 9250; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_3 = 9251; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_4 = 9252; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_5 = 9253; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_6 = 9254; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_7 = 9255; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_0 = 9256; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_1 = 9257; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_10 = 9258; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_11 = 9259; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_12 = 9260; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_13 = 9261; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_14 = 9262; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_15 = 9263; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_2 = 9264; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_3 = 9265; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_4 = 9266; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_5 = 9267; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_6 = 9268; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_7 = 9269; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_8 = 9270; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_9 = 9271; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_0 = 9272; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_1 = 9273; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_10 = 9274; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_11 = 9275; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_12 = 9276; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_13 = 9277; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_14 = 9278; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_15 = 9279; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_16 = 9280; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_17 = 9281; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_18 = 9282; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_19 = 9283; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_2 = 9284; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_20 = 9285; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_21 = 9286; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_22 = 9287; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_23 = 9288; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_3 = 9289; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_4 = 9290; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_5 = 9291; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_6 = 9292; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_7 = 9293; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_8 = 9294; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_9 = 9295; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_0 = 9296; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_1 = 9297; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_2 = 9298; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_3 = 9299; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_4 = 9300; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_5 = 9301; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_6 = 9302; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_7 = 9303; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_0 = 9304; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_1 = 9305; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_2 = 9306; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_3 = 9307; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_4 = 9308; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_5 = 9309; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_6 = 9310; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_7 = 9311; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_0 = 9312; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_1 = 9313; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_2 = 9314; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_3 = 9315; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_4 = 9316; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_5 = 9317; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_6 = 9318; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_7 = 9319; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_0 = 9320; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_1 = 9321; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_2 = 9322; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_3 = 9323; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_4 = 9324; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_5 = 9325; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_6 = 9326; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_7 = 9327; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_0 = 9328; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_1 = 9329; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_2 = 9330; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_3 = 9331; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_0 = 9332; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_1 = 9333; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_2 = 9334; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_3 = 9335; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_0 = 9336; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_1 = 9337; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_2 = 9338; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_3 = 9339; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_0 = 9340; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_1 = 9341; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_2 = 9342; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_3 = 9343; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_0 = 9344; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_1 = 9345; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_2 = 9346; // 3 -static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_3 = 9347; // 3 -static const uint64_t SH_FLD_IDIAL_DEBUG0_CONFIG = 9348; // 3 -static const uint64_t SH_FLD_IDIAL_DEBUG1_CONFIG = 9349; // 3 -static const uint64_t SH_FLD_IDIAL_EA = 9350; // 2 -static const uint64_t SH_FLD_IDIAL_EA_LEN = 9351; // 2 -static const uint64_t SH_FLD_IDIAL_ECC_CONFIG = 9352; // 3 -static const uint64_t SH_FLD_IDIAL_ERRINJ = 9353; // 3 -static const uint64_t SH_FLD_IDIAL_IBAR_ERRP = 9354; // 1 -static const uint64_t SH_FLD_IDIAL_IBRD = 9355; // 3 -static const uint64_t SH_FLD_IDIAL_IBRD_LEN = 9356; // 3 -static const uint64_t SH_FLD_IDIAL_IBUF_CTL_PIPE = 9357; // 3 -static const uint64_t SH_FLD_IDIAL_IBUF_RDWR = 9358; // 3 -static const uint64_t SH_FLD_IDIAL_IBUF_STATE = 9359; // 3 -static const uint64_t SH_FLD_IDIAL_IBUF_WARB = 9360; // 3 -static const uint64_t SH_FLD_IDIAL_IBUF_WRITE = 9361; // 3 -static const uint64_t SH_FLD_IDIAL_INHIBIT_CONFIG = 9362; // 3 -static const uint64_t SH_FLD_IDIAL_IR_CE = 9363; // 3 -static const uint64_t SH_FLD_IDIAL_IR_CE_LEN = 9364; // 3 -static const uint64_t SH_FLD_IDIAL_IR_SUE = 9365; // 3 -static const uint64_t SH_FLD_IDIAL_IR_SUE_LEN = 9366; // 3 -static const uint64_t SH_FLD_IDIAL_IR_UE = 9367; // 3 -static const uint64_t SH_FLD_IDIAL_IR_UE_LEN = 9368; // 3 -static const uint64_t SH_FLD_IDIAL_ISSYNC = 9369; // 1 -static const uint64_t SH_FLD_IDIAL_ISSYNC_LEN = 9370; // 1 -static const uint64_t SH_FLD_IDIAL_LEN = 9371; // 35 -static const uint64_t SH_FLD_IDIAL_MISC_STATE = 9372; // 3 -static const uint64_t SH_FLD_IDIAL_MM_LOCAL_XSTOP = 9373; // 1 -static const uint64_t SH_FLD_IDIAL_MRG_IR_PIPE = 9374; // 3 -static const uint64_t SH_FLD_IDIAL_MRG_OR_PIPE = 9375; // 3 -static const uint64_t SH_FLD_IDIAL_MRG_STATE = 9376; // 3 -static const uint64_t SH_FLD_IDIAL_NDL0_NOSTALL = 9377; // 1 -static const uint64_t SH_FLD_IDIAL_NDL0_STALL = 9378; // 1 -static const uint64_t SH_FLD_IDIAL_NDL1_NOSTALL = 9379; // 1 -static const uint64_t SH_FLD_IDIAL_NDL1_STALL = 9380; // 1 -static const uint64_t SH_FLD_IDIAL_NDL2_NOSTALL = 9381; // 1 -static const uint64_t SH_FLD_IDIAL_NDL2_STALL = 9382; // 1 -static const uint64_t SH_FLD_IDIAL_NDL3_NOSTALL = 9383; // 1 -static const uint64_t SH_FLD_IDIAL_NDL3_STALL = 9384; // 1 -static const uint64_t SH_FLD_IDIAL_NDL4_NOSTALL = 9385; // 1 -static const uint64_t SH_FLD_IDIAL_NDL4_STALL = 9386; // 1 -static const uint64_t SH_FLD_IDIAL_NDL5_NOSTALL = 9387; // 1 -static const uint64_t SH_FLD_IDIAL_NDL5_STALL = 9388; // 1 -static const uint64_t SH_FLD_IDIAL_OBRD = 9389; // 3 -static const uint64_t SH_FLD_IDIAL_OBRD_LEN = 9390; // 3 -static const uint64_t SH_FLD_IDIAL_OBUF_RDWR = 9391; // 3 -static const uint64_t SH_FLD_IDIAL_OBUF_STATE = 9392; // 3 -static const uint64_t SH_FLD_IDIAL_OR_CE = 9393; // 3 -static const uint64_t SH_FLD_IDIAL_OR_CE_LEN = 9394; // 3 -static const uint64_t SH_FLD_IDIAL_OR_SUE = 9395; // 3 -static const uint64_t SH_FLD_IDIAL_OR_SUE_LEN = 9396; // 3 -static const uint64_t SH_FLD_IDIAL_OR_UE = 9397; // 3 -static const uint64_t SH_FLD_IDIAL_OR_UE_LEN = 9398; // 3 -static const uint64_t SH_FLD_IDIAL_PAR = 9399; // 1 -static const uint64_t SH_FLD_IDIAL_PAR_LEN = 9400; // 1 -static const uint64_t SH_FLD_IDIAL_PBRX_RTAG = 9401; // 6 -static const uint64_t SH_FLD_IDIAL_PBTX_AMO = 9402; // 3 -static const uint64_t SH_FLD_IDIAL_PBTX_AMO_LEN = 9403; // 3 -static const uint64_t SH_FLD_IDIAL_PBTX_PIPE = 9404; // 3 -static const uint64_t SH_FLD_IDIAL_PBTX_STATE = 9405; // 3 -static const uint64_t SH_FLD_IDIAL_PC = 9406; // 2 -static const uint64_t SH_FLD_IDIAL_PC_LEN = 9407; // 2 -static const uint64_t SH_FLD_IDIAL_PE = 9408; // 2 -static const uint64_t SH_FLD_IDIAL_PE_LEN = 9409; // 2 -static const uint64_t SH_FLD_IDIAL_PR_CE = 9410; // 3 -static const uint64_t SH_FLD_IDIAL_PR_CE_LEN = 9411; // 3 -static const uint64_t SH_FLD_IDIAL_PR_SUE = 9412; // 3 -static const uint64_t SH_FLD_IDIAL_PR_SUE_LEN = 9413; // 3 -static const uint64_t SH_FLD_IDIAL_PR_UE = 9414; // 3 -static const uint64_t SH_FLD_IDIAL_PR_UE_LEN = 9415; // 3 -static const uint64_t SH_FLD_IDIAL_PT_CE = 9416; // 3 -static const uint64_t SH_FLD_IDIAL_PT_CE_LEN = 9417; // 3 -static const uint64_t SH_FLD_IDIAL_PT_SUE = 9418; // 3 -static const uint64_t SH_FLD_IDIAL_PT_SUE_LEN = 9419; // 3 -static const uint64_t SH_FLD_IDIAL_PT_UE = 9420; // 3 -static const uint64_t SH_FLD_IDIAL_PT_UE_LEN = 9421; // 3 -static const uint64_t SH_FLD_IDIAL_RA = 9422; // 2 -static const uint64_t SH_FLD_IDIAL_RA_LEN = 9423; // 2 -static const uint64_t SH_FLD_IDIAL_RING_ERRP = 9424; // 1 -static const uint64_t SH_FLD_IDIAL_RNW = 9425; // 1 -static const uint64_t SH_FLD_IDIAL_RQIN_OVF = 9426; // 3 -static const uint64_t SH_FLD_IDIAL_RQIN_OVF_LEN = 9427; // 3 -static const uint64_t SH_FLD_IDIAL_RQIN_STATE = 9428; // 3 -static const uint64_t SH_FLD_IDIAL_RSVD0 = 9429; // 4 -static const uint64_t SH_FLD_IDIAL_RSVD0_LEN = 9430; // 4 -static const uint64_t SH_FLD_IDIAL_RSVD1 = 9431; // 2 -static const uint64_t SH_FLD_IDIAL_RSVD1_LEN = 9432; // 2 -static const uint64_t SH_FLD_IDIAL_SCOMDAA_ERRP = 9433; // 1 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_0 = 9434; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_1 = 9435; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_2 = 9436; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_3 = 9437; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_0 = 9438; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_1 = 9439; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_2 = 9440; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_3 = 9441; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_0 = 9442; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_1 = 9443; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_2 = 9444; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_3 = 9445; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_0 = 9446; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_1 = 9447; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_2 = 9448; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_3 = 9449; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_4 = 9450; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_5 = 9451; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_6 = 9452; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_7 = 9453; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_0 = 9454; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_1 = 9455; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_10 = 9456; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_11 = 9457; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_12 = 9458; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_13 = 9459; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_14 = 9460; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_15 = 9461; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_2 = 9462; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_3 = 9463; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_4 = 9464; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_5 = 9465; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_6 = 9466; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_7 = 9467; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_8 = 9468; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_9 = 9469; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_0 = 9470; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_1 = 9471; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_10 = 9472; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_11 = 9473; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_12 = 9474; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_13 = 9475; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_14 = 9476; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_15 = 9477; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_16 = 9478; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_17 = 9479; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_18 = 9480; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_19 = 9481; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_2 = 9482; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_20 = 9483; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_21 = 9484; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_22 = 9485; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_23 = 9486; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_24 = 9487; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_25 = 9488; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_26 = 9489; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_27 = 9490; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_28 = 9491; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_29 = 9492; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_3 = 9493; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_30 = 9494; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_31 = 9495; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_32 = 9496; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_33 = 9497; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_34 = 9498; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_35 = 9499; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_36 = 9500; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_37 = 9501; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_38 = 9502; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_39 = 9503; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_4 = 9504; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_40 = 9505; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_41 = 9506; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_42 = 9507; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_43 = 9508; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_44 = 9509; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_45 = 9510; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_46 = 9511; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_47 = 9512; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_48 = 9513; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_49 = 9514; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_5 = 9515; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_50 = 9516; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_51 = 9517; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_52 = 9518; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_53 = 9519; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_54 = 9520; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_55 = 9521; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_56 = 9522; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_57 = 9523; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_58 = 9524; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_59 = 9525; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_6 = 9526; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_60 = 9527; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_61 = 9528; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_62 = 9529; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_63 = 9530; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_7 = 9531; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_8 = 9532; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_9 = 9533; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_0 = 9534; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_1 = 9535; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_10 = 9536; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_11 = 9537; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_12 = 9538; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_13 = 9539; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_14 = 9540; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_15 = 9541; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_16 = 9542; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_17 = 9543; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_18 = 9544; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_19 = 9545; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_2 = 9546; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_20 = 9547; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_21 = 9548; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_22 = 9549; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_23 = 9550; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_24 = 9551; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_25 = 9552; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_26 = 9553; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_27 = 9554; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_28 = 9555; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_29 = 9556; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_3 = 9557; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_30 = 9558; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_31 = 9559; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_4 = 9560; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_5 = 9561; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_6 = 9562; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_7 = 9563; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_8 = 9564; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_9 = 9565; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_0 = 9566; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_1 = 9567; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_10 = 9568; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_11 = 9569; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_2 = 9570; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_3 = 9571; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_4 = 9572; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_5 = 9573; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_6 = 9574; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_7 = 9575; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_8 = 9576; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_9 = 9577; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_0 = 9578; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_1 = 9579; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_10 = 9580; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_11 = 9581; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_2 = 9582; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_3 = 9583; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_4 = 9584; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_5 = 9585; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_6 = 9586; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_7 = 9587; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_8 = 9588; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_9 = 9589; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_0 = 9590; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_1 = 9591; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_2 = 9592; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_3 = 9593; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_4 = 9594; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_5 = 9595; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_6 = 9596; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_7 = 9597; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_0 = 9598; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_1 = 9599; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_2 = 9600; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_3 = 9601; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_4 = 9602; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_5 = 9603; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_6 = 9604; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_7 = 9605; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_0 = 9606; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_1 = 9607; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_2 = 9608; // 12 -static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_3 = 9609; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_0 = 9610; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_1 = 9611; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_2 = 9612; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_3 = 9613; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_0 = 9614; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_1 = 9615; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_2 = 9616; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_3 = 9617; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_0 = 9618; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_1 = 9619; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_2 = 9620; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_3 = 9621; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_0 = 9622; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_1 = 9623; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_2 = 9624; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_3 = 9625; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_4 = 9626; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_5 = 9627; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_6 = 9628; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_7 = 9629; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_0 = 9630; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_1 = 9631; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_10 = 9632; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_11 = 9633; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_12 = 9634; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_13 = 9635; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_14 = 9636; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_15 = 9637; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_2 = 9638; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_3 = 9639; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_4 = 9640; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_5 = 9641; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_6 = 9642; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_7 = 9643; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_8 = 9644; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_9 = 9645; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_0 = 9646; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_1 = 9647; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_10 = 9648; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_11 = 9649; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_12 = 9650; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_13 = 9651; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_14 = 9652; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_15 = 9653; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_16 = 9654; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_17 = 9655; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_18 = 9656; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_19 = 9657; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_2 = 9658; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_20 = 9659; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_21 = 9660; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_22 = 9661; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_23 = 9662; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_24 = 9663; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_25 = 9664; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_26 = 9665; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_27 = 9666; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_28 = 9667; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_29 = 9668; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_3 = 9669; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_30 = 9670; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_31 = 9671; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_32 = 9672; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_33 = 9673; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_34 = 9674; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_35 = 9675; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_36 = 9676; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_37 = 9677; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_38 = 9678; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_39 = 9679; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_4 = 9680; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_40 = 9681; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_41 = 9682; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_42 = 9683; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_43 = 9684; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_44 = 9685; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_45 = 9686; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_46 = 9687; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_47 = 9688; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_48 = 9689; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_49 = 9690; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_5 = 9691; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_50 = 9692; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_51 = 9693; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_52 = 9694; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_53 = 9695; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_54 = 9696; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_55 = 9697; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_56 = 9698; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_57 = 9699; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_58 = 9700; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_59 = 9701; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_6 = 9702; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_60 = 9703; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_61 = 9704; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_62 = 9705; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_63 = 9706; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_7 = 9707; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_8 = 9708; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_9 = 9709; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_0 = 9710; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_1 = 9711; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_10 = 9712; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_11 = 9713; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_12 = 9714; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_13 = 9715; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_14 = 9716; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_15 = 9717; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_16 = 9718; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_17 = 9719; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_18 = 9720; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_19 = 9721; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_2 = 9722; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_20 = 9723; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_21 = 9724; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_22 = 9725; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_23 = 9726; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_24 = 9727; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_25 = 9728; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_26 = 9729; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_27 = 9730; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_28 = 9731; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_29 = 9732; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_3 = 9733; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_30 = 9734; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_31 = 9735; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_4 = 9736; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_5 = 9737; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_6 = 9738; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_7 = 9739; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_8 = 9740; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_9 = 9741; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_0 = 9742; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_1 = 9743; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_10 = 9744; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_11 = 9745; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_2 = 9746; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_3 = 9747; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_4 = 9748; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_5 = 9749; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_6 = 9750; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_7 = 9751; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_8 = 9752; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_9 = 9753; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_0 = 9754; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_1 = 9755; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_10 = 9756; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_11 = 9757; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_2 = 9758; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_3 = 9759; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_4 = 9760; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_5 = 9761; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_6 = 9762; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_7 = 9763; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_8 = 9764; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_9 = 9765; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_0 = 9766; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_1 = 9767; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_2 = 9768; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_3 = 9769; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_4 = 9770; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_5 = 9771; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_6 = 9772; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_7 = 9773; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_0 = 9774; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_1 = 9775; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_2 = 9776; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_3 = 9777; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_4 = 9778; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_5 = 9779; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_6 = 9780; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_7 = 9781; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_0 = 9782; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_1 = 9783; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_2 = 9784; // 12 -static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_3 = 9785; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_0 = 9786; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_1 = 9787; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_2 = 9788; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_3 = 9789; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_0 = 9790; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_1 = 9791; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_2 = 9792; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_3 = 9793; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_0 = 9794; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_1 = 9795; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_2 = 9796; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_3 = 9797; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_0 = 9798; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_1 = 9799; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_2 = 9800; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_3 = 9801; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_4 = 9802; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_5 = 9803; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_6 = 9804; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_7 = 9805; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_0 = 9806; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_1 = 9807; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_10 = 9808; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_11 = 9809; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_12 = 9810; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_13 = 9811; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_14 = 9812; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_15 = 9813; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_2 = 9814; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_3 = 9815; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_4 = 9816; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_5 = 9817; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_6 = 9818; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_7 = 9819; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_8 = 9820; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_9 = 9821; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_0 = 9822; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_1 = 9823; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_10 = 9824; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_11 = 9825; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_12 = 9826; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_13 = 9827; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_14 = 9828; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_15 = 9829; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_16 = 9830; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_17 = 9831; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_18 = 9832; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_19 = 9833; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_2 = 9834; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_20 = 9835; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_21 = 9836; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_22 = 9837; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_23 = 9838; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_24 = 9839; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_25 = 9840; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_26 = 9841; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_27 = 9842; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_28 = 9843; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_29 = 9844; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_3 = 9845; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_30 = 9846; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_31 = 9847; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_32 = 9848; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_33 = 9849; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_34 = 9850; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_35 = 9851; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_36 = 9852; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_37 = 9853; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_38 = 9854; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_39 = 9855; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_4 = 9856; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_40 = 9857; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_41 = 9858; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_42 = 9859; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_43 = 9860; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_44 = 9861; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_45 = 9862; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_46 = 9863; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_47 = 9864; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_48 = 9865; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_49 = 9866; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_5 = 9867; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_50 = 9868; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_51 = 9869; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_52 = 9870; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_53 = 9871; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_54 = 9872; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_55 = 9873; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_56 = 9874; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_57 = 9875; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_58 = 9876; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_59 = 9877; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_6 = 9878; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_60 = 9879; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_61 = 9880; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_62 = 9881; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_63 = 9882; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_7 = 9883; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_8 = 9884; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_9 = 9885; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_0 = 9886; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_1 = 9887; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_10 = 9888; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_11 = 9889; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_12 = 9890; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_13 = 9891; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_14 = 9892; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_15 = 9893; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_16 = 9894; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_17 = 9895; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_18 = 9896; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_19 = 9897; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_2 = 9898; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_20 = 9899; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_21 = 9900; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_22 = 9901; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_23 = 9902; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_24 = 9903; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_25 = 9904; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_26 = 9905; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_27 = 9906; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_28 = 9907; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_29 = 9908; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_3 = 9909; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_30 = 9910; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_31 = 9911; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_4 = 9912; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_5 = 9913; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_6 = 9914; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_7 = 9915; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_8 = 9916; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_9 = 9917; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_0 = 9918; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_1 = 9919; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_10 = 9920; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_11 = 9921; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_2 = 9922; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_3 = 9923; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_4 = 9924; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_5 = 9925; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_6 = 9926; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_7 = 9927; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_8 = 9928; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_9 = 9929; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_0 = 9930; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_1 = 9931; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_10 = 9932; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_11 = 9933; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_2 = 9934; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_3 = 9935; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_4 = 9936; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_5 = 9937; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_6 = 9938; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_7 = 9939; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_8 = 9940; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_9 = 9941; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_0 = 9942; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_1 = 9943; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_2 = 9944; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_3 = 9945; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_4 = 9946; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_5 = 9947; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_6 = 9948; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_7 = 9949; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_0 = 9950; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_1 = 9951; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_2 = 9952; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_3 = 9953; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_4 = 9954; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_5 = 9955; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_6 = 9956; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_7 = 9957; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_0 = 9958; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_1 = 9959; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_2 = 9960; // 12 -static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_3 = 9961; // 12 -static const uint64_t SH_FLD_IDIAL_TAG = 9962; // 1 -static const uint64_t SH_FLD_IDIAL_TAG_LEN = 9963; // 1 -static const uint64_t SH_FLD_IDIAL_VLD = 9964; // 1 -static const uint64_t SH_FLD_IDIR_ERROR_INJECT = 9965; // 24 -static const uint64_t SH_FLD_IDLE = 9966; // 2 -static const uint64_t SH_FLD_IDLES = 9967; // 64 -static const uint64_t SH_FLD_IDLES_LEN = 9968; // 64 -static const uint64_t SH_FLD_IDLE_INDICATION = 9969; // 1 -static const uint64_t SH_FLD_IDLE_PAT_ACTN = 9970; // 2 -static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13 = 9971; // 2 -static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN = 9972; // 2 -static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_14 = 9973; // 2 -static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_15 = 9974; // 2 -static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_16 = 9975; // 2 -static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_17 = 9976; // 2 -static const uint64_t SH_FLD_IDLE_PAT_BANK_0_1 = 9977; // 2 -static const uint64_t SH_FLD_IDLE_PAT_BANK_0_1_LEN = 9978; // 2 -static const uint64_t SH_FLD_IDLE_PAT_BANK_2 = 9979; // 2 -static const uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_0 = 9980; // 2 -static const uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_1 = 9981; // 2 -static const uint64_t SH_FLD_IDLE_PAT_PARITY = 9982; // 2 -static const uint64_t SH_FLD_IDR_LCL_SAMPLE_EN = 9983; // 12 -static const uint64_t SH_FLD_ID_LEN = 9984; // 129 -static const uint64_t SH_FLD_IERAT_EA_INJECT = 9985; // 24 -static const uint64_t SH_FLD_IERAT_RA_INJECT = 9986; // 24 -static const uint64_t SH_FLD_IFC_REG_CERR0 = 9987; // 1 -static const uint64_t SH_FLD_IFC_REG_CERR1 = 9988; // 1 -static const uint64_t SH_FLD_IFC_REG_CERR2 = 9989; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR0 = 9990; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR1 = 9991; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR2 = 9992; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR3 = 9993; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR4 = 9994; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR5 = 9995; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR6 = 9996; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR7 = 9997; // 1 -static const uint64_t SH_FLD_IFC_REG_ERR8 = 9998; // 1 -static const uint64_t SH_FLD_IFREQ = 9999; // 1 -static const uint64_t SH_FLD_IGNORE_PECE = 10000; // 12 -static const uint64_t SH_FLD_ILLEGAL_CACHE_OP = 10001; // 1 -static const uint64_t SH_FLD_ILLEGAL_CACHE_OP_MASK = 10002; // 1 -static const uint64_t SH_FLD_ILLEGAL_LPC_BAR_ACCESS = 10003; // 4 -static const uint64_t SH_FLD_ILL_CRESP = 10004; // 1 -static const uint64_t SH_FLD_IMA_ACK_DEAD = 10005; // 12 -static const uint64_t SH_FLD_IMA_CRESP_ADDR_ERR = 10006; // 12 -static const uint64_t SH_FLD_IMM_FREEZE = 10007; // 43 -static const uint64_t SH_FLD_IN = 10008; // 264 -static const uint64_t SH_FLD_IN0 = 10009; // 339 -static const uint64_t SH_FLD_IN1 = 10010; // 296 -static const uint64_t SH_FLD_IN10 = 10011; // 208 -static const uint64_t SH_FLD_IN11 = 10012; // 208 -static const uint64_t SH_FLD_IN11_LEN = 10013; // 3 -static const uint64_t SH_FLD_IN12 = 10014; // 162 -static const uint64_t SH_FLD_IN12_LEN = 10015; // 6 -static const uint64_t SH_FLD_IN13 = 10016; // 156 -static const uint64_t SH_FLD_IN13_LEN = 10017; // 12 -static const uint64_t SH_FLD_IN14 = 10018; // 144 -static const uint64_t SH_FLD_IN14_LEN = 10019; // 3 -static const uint64_t SH_FLD_IN15 = 10020; // 141 -static const uint64_t SH_FLD_IN16 = 10021; // 141 -static const uint64_t SH_FLD_IN17 = 10022; // 141 -static const uint64_t SH_FLD_IN17_LEN = 10023; // 6 -static const uint64_t SH_FLD_IN18 = 10024; // 135 -static const uint64_t SH_FLD_IN18_LEN = 10025; // 3 -static const uint64_t SH_FLD_IN19 = 10026; // 132 -static const uint64_t SH_FLD_IN2 = 10027; // 296 -static const uint64_t SH_FLD_IN20 = 10028; // 132 -static const uint64_t SH_FLD_IN21 = 10029; // 132 -static const uint64_t SH_FLD_IN21_LEN = 10030; // 3 -static const uint64_t SH_FLD_IN22 = 10031; // 129 -static const uint64_t SH_FLD_IN23 = 10032; // 43 -static const uint64_t SH_FLD_IN24 = 10033; // 43 -static const uint64_t SH_FLD_IN25 = 10034; // 43 -static const uint64_t SH_FLD_IN26 = 10035; // 129 -static const uint64_t SH_FLD_IN27 = 10036; // 43 -static const uint64_t SH_FLD_IN28 = 10037; // 43 -static const uint64_t SH_FLD_IN29 = 10038; // 43 -static const uint64_t SH_FLD_IN3 = 10039; // 296 -static const uint64_t SH_FLD_IN30 = 10040; // 43 -static const uint64_t SH_FLD_IN31 = 10041; // 43 -static const uint64_t SH_FLD_IN32 = 10042; // 43 -static const uint64_t SH_FLD_IN33 = 10043; // 43 -static const uint64_t SH_FLD_IN34 = 10044; // 43 -static const uint64_t SH_FLD_IN35 = 10045; // 43 -static const uint64_t SH_FLD_IN36 = 10046; // 43 -static const uint64_t SH_FLD_IN37 = 10047; // 43 -static const uint64_t SH_FLD_IN38 = 10048; // 43 -static const uint64_t SH_FLD_IN39 = 10049; // 43 -static const uint64_t SH_FLD_IN3_LEN = 10050; // 1 -static const uint64_t SH_FLD_IN4 = 10051; // 338 -static const uint64_t SH_FLD_IN40 = 10052; // 43 -static const uint64_t SH_FLD_IN41 = 10053; // 43 -static const uint64_t SH_FLD_IN4_LEN = 10054; // 1 -static const uint64_t SH_FLD_IN5 = 10055; // 337 -static const uint64_t SH_FLD_IN5_LEN = 10056; // 78 -static const uint64_t SH_FLD_IN6 = 10057; // 260 -static const uint64_t SH_FLD_IN6_LEN = 10058; // 3 -static const uint64_t SH_FLD_IN7 = 10059; // 257 -static const uint64_t SH_FLD_IN7_LEN = 10060; // 9 -static const uint64_t SH_FLD_IN8 = 10061; // 248 -static const uint64_t SH_FLD_IN8_LEN = 10062; // 3 -static const uint64_t SH_FLD_IN9 = 10063; // 245 -static const uint64_t SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE = 10064; // 4 -static const uint64_t SH_FLD_INBD_ARRAY_ECC_CE = 10065; // 2 -static const uint64_t SH_FLD_INBD_ARRAY_ECC_UE = 10066; // 2 -static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_CE = 10067; // 1 -static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_SUE = 10068; // 1 -static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_UE = 10069; // 1 -static const uint64_t SH_FLD_INCLUDE_TRAFFIC = 10070; // 1 -static const uint64_t SH_FLD_INCOMING_PB_PARITY_ERR = 10071; // 2 -static const uint64_t SH_FLD_INDEX = 10072; // 1 -static const uint64_t SH_FLD_INDEX_LEN = 10073; // 1 -static const uint64_t SH_FLD_INDIRECT_BRIDGE_0_SOURCE = 10074; // 1 -static const uint64_t SH_FLD_INDIRECT_BRIDGE_1_SOURCE = 10075; // 1 -static const uint64_t SH_FLD_INDIRECT_BRIDGE_2_SOURCE = 10076; // 1 -static const uint64_t SH_FLD_INDIRECT_BRIDGE_3_SOURCE = 10077; // 1 -static const uint64_t SH_FLD_INDIRECT_MODE = 10078; // 2 -static const uint64_t SH_FLD_INDIR_THRDID = 10079; // 4 -static const uint64_t SH_FLD_INDIR_THRDID_LEN = 10080; // 4 -static const uint64_t SH_FLD_INDIR_VLD = 10081; // 4 -static const uint64_t SH_FLD_INEX = 10082; // 43 -static const uint64_t SH_FLD_INFINITE_MODE = 10083; // 43 -static const uint64_t SH_FLD_INFO = 10084; // 43 -static const uint64_t SH_FLD_INFORMATION = 10085; // 8 -static const uint64_t SH_FLD_INFORMATION_LEN = 10086; // 8 -static const uint64_t SH_FLD_INFO_CAPTURED = 10087; // 4 -static const uint64_t SH_FLD_INH0_TICK = 10088; // 12 -static const uint64_t SH_FLD_INH0_TICK_LEN = 10089; // 12 -static const uint64_t SH_FLD_INH1_TICK = 10090; // 12 -static const uint64_t SH_FLD_INH1_TICK_LEN = 10091; // 12 -static const uint64_t SH_FLD_INIT = 10092; // 1 -static const uint64_t SH_FLD_INITIAL_COARSE_WR = 10093; // 8 -static const uint64_t SH_FLD_INITIAL_PAT_WRITE = 10094; // 8 -static const uint64_t SH_FLD_INIT_DONE_DL_MASK = 10095; // 2 -static const uint64_t SH_FLD_INIT_REQUEST = 10096; // 1 -static const uint64_t SH_FLD_INIT_TIMER = 10097; // 1 -static const uint64_t SH_FLD_INIT_TIMER_LEN = 10098; // 1 -static const uint64_t SH_FLD_INIT_TMR_CFG = 10099; // 72 -static const uint64_t SH_FLD_INIT_TMR_CFG_LEN = 10100; // 72 -static const uint64_t SH_FLD_INJ = 10101; // 1 -static const uint64_t SH_FLD_INJECT_1HOT_SM_ERROR = 10102; // 8 -static const uint64_t SH_FLD_INJECT_ENABLE = 10103; // 1 -static const uint64_t SH_FLD_INJECT_ERR = 10104; // 12 -static const uint64_t SH_FLD_INJECT_FIR_ERR0 = 10105; // 8 -static const uint64_t SH_FLD_INJECT_FIR_ERR1 = 10106; // 8 -static const uint64_t SH_FLD_INJECT_FIR_ERR2 = 10107; // 8 -static const uint64_t SH_FLD_INJECT_FIR_ERR3 = 10108; // 8 -static const uint64_t SH_FLD_INJECT_FIR_ERR4 = 10109; // 8 -static const uint64_t SH_FLD_INJECT_MODE = 10110; // 2 -static const uint64_t SH_FLD_INJECT_MODE_LEN = 10111; // 2 -static const uint64_t SH_FLD_INJECT_TYPE = 10112; // 2 -static const uint64_t SH_FLD_INJECT_TYPE_LEN = 10113; // 2 -static const uint64_t SH_FLD_INJ_LEN = 10114; // 1 -static const uint64_t SH_FLD_INOP = 10115; // 43 -static const uint64_t SH_FLD_INOP_FORCE_SG = 10116; // 43 -static const uint64_t SH_FLD_INOP_LEN = 10117; // 43 -static const uint64_t SH_FLD_INOP_WAIT = 10118; // 43 -static const uint64_t SH_FLD_INOP_WAIT_LEN = 10119; // 43 -static const uint64_t SH_FLD_INPROG_WR_ERR = 10120; // 1 -static const uint64_t SH_FLD_INRD_DONE_ERR = 10121; // 1 -static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK = 10122; // 43 -static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO = 10123; // 43 -static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN = 10124; // 43 -static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN = 10125; // 43 -static const uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL = 10126; // 43 -static const uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 10127; // 43 -static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT = 10128; // 43 -static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN = 10129; // 43 -static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR = 10130; // 43 -static const uint64_t SH_FLD_INST1_COND3_ENABLE = 10131; // 43 -static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_BANK = 10132; // 43 -static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO = 10133; // 43 -static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO_LEN = 10134; // 43 -static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_WAITN = 10135; // 43 -static const uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL = 10136; // 43 -static const uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN = 10137; // 43 -static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_BANK = 10138; // 43 -static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO = 10139; // 43 -static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO_LEN = 10140; // 43 -static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_WAITN = 10141; // 43 -static const uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL = 10142; // 43 -static const uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN = 10143; // 43 -static const uint64_t SH_FLD_INST1_SLOW_LFSR_MODE = 10144; // 43 -static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK = 10145; // 43 -static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO = 10146; // 43 -static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN = 10147; // 43 -static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN = 10148; // 43 -static const uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL = 10149; // 43 -static const uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 10150; // 43 -static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT = 10151; // 43 -static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN = 10152; // 43 -static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR = 10153; // 43 -static const uint64_t SH_FLD_INST2_COND3_ENABLE = 10154; // 43 -static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_BANK = 10155; // 43 -static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO = 10156; // 43 -static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO_LEN = 10157; // 43 -static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_WAITN = 10158; // 43 -static const uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL = 10159; // 43 -static const uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN = 10160; // 43 -static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_BANK = 10161; // 43 -static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO = 10162; // 43 -static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO_LEN = 10163; // 43 -static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_WAITN = 10164; // 43 -static const uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL = 10165; // 43 -static const uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN = 10166; // 43 -static const uint64_t SH_FLD_INST2_SLOW_LFSR_MODE = 10167; // 43 -static const uint64_t SH_FLD_INST3_COND3_ENABLE = 10168; // 43 -static const uint64_t SH_FLD_INST3_SLOW_LFSR_MODE = 10169; // 43 -static const uint64_t SH_FLD_INST4_COND3_ENABLE = 10170; // 43 -static const uint64_t SH_FLD_INST4_SLOW_LFSR_MODE = 10171; // 43 -static const uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA = 10172; // 12 -static const uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA_LEN = 10173; // 12 -static const uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA = 10174; // 12 -static const uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA_LEN = 10175; // 12 -static const uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA = 10176; // 12 -static const uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA_LEN = 10177; // 12 -static const uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA = 10178; // 12 -static const uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA_LEN = 10179; // 12 -static const uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA = 10180; // 12 -static const uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA_LEN = 10181; // 12 -static const uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY = 10182; // 12 -static const uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN = 10183; // 12 -static const uint64_t SH_FLD_INSTR0_BUSYCNT_RUNNING = 10184; // 1 -static const uint64_t SH_FLD_INSTR0_CYCLECNT_RUNNING = 10185; // 1 -static const uint64_t SH_FLD_INSTR0_MODE = 10186; // 1 -static const uint64_t SH_FLD_INSTR0_MODE_LEN = 10187; // 1 -static const uint64_t SH_FLD_INSTR0_RESET = 10188; // 1 -static const uint64_t SH_FLD_INSTR0_START = 10189; // 1 -static const uint64_t SH_FLD_INSTR0_STOP = 10190; // 1 -static const uint64_t SH_FLD_INSTR0_STOPPED_ON_ERROR = 10191; // 1 -static const uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT = 10192; // 1 -static const uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN = 10193; // 1 -static const uint64_t SH_FLD_INSTR0_STOP_TIMER_EN = 10194; // 1 -static const uint64_t SH_FLD_INSTR1_BUSYCNT_RUNNING = 10195; // 1 -static const uint64_t SH_FLD_INSTR1_CYCLECNT_RUNNING = 10196; // 1 -static const uint64_t SH_FLD_INSTR1_MODE = 10197; // 1 -static const uint64_t SH_FLD_INSTR1_MODE_LEN = 10198; // 1 -static const uint64_t SH_FLD_INSTR1_RESET = 10199; // 1 -static const uint64_t SH_FLD_INSTR1_START = 10200; // 1 -static const uint64_t SH_FLD_INSTR1_STOP = 10201; // 1 -static const uint64_t SH_FLD_INSTR1_STOPPED_ON_ERROR = 10202; // 1 -static const uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT = 10203; // 1 -static const uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN = 10204; // 1 -static const uint64_t SH_FLD_INSTR1_STOP_TIMER_EN = 10205; // 1 -static const uint64_t SH_FLD_INSTR2_BUSYCNT_RUNNING = 10206; // 1 -static const uint64_t SH_FLD_INSTR2_CYCLECNT_RUNNING = 10207; // 1 -static const uint64_t SH_FLD_INSTR2_MODE = 10208; // 1 -static const uint64_t SH_FLD_INSTR2_MODE_LEN = 10209; // 1 -static const uint64_t SH_FLD_INSTR2_RESET = 10210; // 1 -static const uint64_t SH_FLD_INSTR2_START = 10211; // 1 -static const uint64_t SH_FLD_INSTR2_STOP = 10212; // 1 -static const uint64_t SH_FLD_INSTR2_STOPPED_ON_ERROR = 10213; // 1 -static const uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT = 10214; // 1 -static const uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN = 10215; // 1 -static const uint64_t SH_FLD_INSTR2_STOP_TIMER_EN = 10216; // 1 -static const uint64_t SH_FLD_INST_CYCLE_SAMPLE = 10217; // 12 -static const uint64_t SH_FLD_INST_CYCLE_SAMPLE_LEN = 10218; // 12 -static const uint64_t SH_FLD_INTERCME_DIRECT_IN_0 = 10219; // 12 -static const uint64_t SH_FLD_INTERCME_DIRECT_IN_1_2 = 10220; // 12 -static const uint64_t SH_FLD_INTERCME_DIRECT_IN_1_2_LEN = 10221; // 12 -static const uint64_t SH_FLD_INTERMITTENT_CE_COUNT = 10222; // 2 -static const uint64_t SH_FLD_INTERMITTENT_CE_COUNT_LEN = 10223; // 2 -static const uint64_t SH_FLD_INTERMITTENT_MCE_COUNT = 10224; // 2 -static const uint64_t SH_FLD_INTERMITTENT_MCE_COUNT_LEN = 10225; // 2 -static const uint64_t SH_FLD_INTERNAL = 10226; // 14 -static const uint64_t SH_FLD_INTERNAL_ERR = 10227; // 1 -static const uint64_t SH_FLD_INTERNAL_ERROR = 10228; // 5 -static const uint64_t SH_FLD_INTERNAL_ERR_MASK = 10229; // 1 -static const uint64_t SH_FLD_INTERNAL_FSM_ERROR = 10230; // 2 -static const uint64_t SH_FLD_INTERNAL_LEN = 10231; // 14 -static const uint64_t SH_FLD_INTERNAL_PARITY_ERROR = 10232; // 6 -static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR = 10233; // 32 -static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR_CLONE = 10234; // 8 -static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR_COPY = 10235; // 24 -static const uint64_t SH_FLD_INTERNAL_STATE_VECTOR = 10236; // 1 -static const uint64_t SH_FLD_INTERNAL_STATE_VECTOR_LEN = 10237; // 1 -static const uint64_t SH_FLD_INTERRUPT = 10238; // 3 -static const uint64_t SH_FLD_INTERRUPT0_ADDRESS_ERROR = 10239; // 4 -static const uint64_t SH_FLD_INTERRUPT1 = 10240; // 1 -static const uint64_t SH_FLD_INTERRUPT1_ADDRESS_ERROR = 10241; // 4 -static const uint64_t SH_FLD_INTERRUPT1_LEN = 10242; // 1 -static const uint64_t SH_FLD_INTERRUPT2 = 10243; // 1 -static const uint64_t SH_FLD_INTERRUPT2_ADDRESS_ERROR = 10244; // 4 -static const uint64_t SH_FLD_INTERRUPT2_LEN = 10245; // 1 -static const uint64_t SH_FLD_INTERRUPT3 = 10246; // 1 -static const uint64_t SH_FLD_INTERRUPT3_ADDRESS_ERROR = 10247; // 4 -static const uint64_t SH_FLD_INTERRUPT3_LEN = 10248; // 1 -static const uint64_t SH_FLD_INTERRUPT4 = 10249; // 1 -static const uint64_t SH_FLD_INTERRUPT4_ADDRESS_ERROR = 10250; // 4 -static const uint64_t SH_FLD_INTERRUPT4_LEN = 10251; // 1 -static const uint64_t SH_FLD_INTERRUPT5_ADDRESS_ERROR = 10252; // 4 -static const uint64_t SH_FLD_INTERRUPT_00 = 10253; // 1 -static const uint64_t SH_FLD_INTERRUPT_01 = 10254; // 1 -static const uint64_t SH_FLD_INTERRUPT_02 = 10255; // 1 -static const uint64_t SH_FLD_INTERRUPT_03 = 10256; // 1 -static const uint64_t SH_FLD_INTERRUPT_04 = 10257; // 1 -static const uint64_t SH_FLD_INTERRUPT_05 = 10258; // 1 -static const uint64_t SH_FLD_INTERRUPT_06 = 10259; // 1 -static const uint64_t SH_FLD_INTERRUPT_07 = 10260; // 1 -static const uint64_t SH_FLD_INTERRUPT_08 = 10261; // 1 -static const uint64_t SH_FLD_INTERRUPT_09 = 10262; // 1 -static const uint64_t SH_FLD_INTERRUPT_10 = 10263; // 1 -static const uint64_t SH_FLD_INTERRUPT_11 = 10264; // 1 -static const uint64_t SH_FLD_INTERRUPT_12 = 10265; // 1 -static const uint64_t SH_FLD_INTERRUPT_13 = 10266; // 1 -static const uint64_t SH_FLD_INTERRUPT_14 = 10267; // 1 -static const uint64_t SH_FLD_INTERRUPT_15 = 10268; // 1 -static const uint64_t SH_FLD_INTERRUPT_16 = 10269; // 1 -static const uint64_t SH_FLD_INTERRUPT_17 = 10270; // 1 -static const uint64_t SH_FLD_INTERRUPT_18 = 10271; // 1 -static const uint64_t SH_FLD_INTERRUPT_19 = 10272; // 1 -static const uint64_t SH_FLD_INTERRUPT_20 = 10273; // 1 -static const uint64_t SH_FLD_INTERRUPT_21 = 10274; // 1 -static const uint64_t SH_FLD_INTERRUPT_22 = 10275; // 1 -static const uint64_t SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE = 10276; // 4 -static const uint64_t SH_FLD_INTERRUPT_CONDITION_PENDING = 10277; // 1 -static const uint64_t SH_FLD_INTERRUPT_DISABLE = 10278; // 1 -static const uint64_t SH_FLD_INTERRUPT_DISABLE_LEN = 10279; // 1 -static const uint64_t SH_FLD_INTERRUPT_EDGE_POL_N = 10280; // 2 -static const uint64_t SH_FLD_INTERRUPT_EDGE_POL_N_LEN = 10281; // 2 -static const uint64_t SH_FLD_INTERRUPT_ENABLED = 10282; // 1 -static const uint64_t SH_FLD_INTERRUPT_FROM_ERROR = 10283; // 4 -static const uint64_t SH_FLD_INTERRUPT_FROM_FSP = 10284; // 4 -static const uint64_t SH_FLD_INTERRUPT_INPUT = 10285; // 12 -static const uint64_t SH_FLD_INTERRUPT_INPUT_LEN = 10286; // 12 -static const uint64_t SH_FLD_INTERRUPT_MASK = 10287; // 12 -static const uint64_t SH_FLD_INTERRUPT_MASK_LEN = 10288; // 12 -static const uint64_t SH_FLD_INTERRUPT_MASK_N = 10289; // 2 -static const uint64_t SH_FLD_INTERRUPT_MASK_N_LEN = 10290; // 2 -static const uint64_t SH_FLD_INTERRUPT_POLARITY = 10291; // 12 -static const uint64_t SH_FLD_INTERRUPT_POLARITY_LEN = 10292; // 12 -static const uint64_t SH_FLD_INTERRUPT_ROUTE_A_N = 10293; // 6 -static const uint64_t SH_FLD_INTERRUPT_ROUTE_A_N_LEN = 10294; // 6 -static const uint64_t SH_FLD_INTERRUPT_S0 = 10295; // 1 -static const uint64_t SH_FLD_INTERRUPT_S1 = 10296; // 1 -static const uint64_t SH_FLD_INTERRUPT_SENT = 10297; // 1 -static const uint64_t SH_FLD_INTERRUPT_TYPE = 10298; // 12 -static const uint64_t SH_FLD_INTERRUPT_TYPE_LEN = 10299; // 12 -static const uint64_t SH_FLD_INTERRUPT_TYPE_N = 10300; // 2 -static const uint64_t SH_FLD_INTERRUPT_TYPE_N_LEN = 10301; // 2 -static const uint64_t SH_FLD_INTER_FRAME_DELAY = 10302; // 1 -static const uint64_t SH_FLD_INTER_FRAME_DELAY_LEN = 10303; // 1 -static const uint64_t SH_FLD_INTQ_BAD_CRESP = 10304; // 1 -static const uint64_t SH_FLD_INTQ_FSM_PERR = 10305; // 1 -static const uint64_t SH_FLD_INTQ_OP_HANG = 10306; // 1 -static const uint64_t SH_FLD_INTQ_OVERFLOW = 10307; // 1 -static const uint64_t SH_FLD_INTR0 = 10308; // 5 -static const uint64_t SH_FLD_INTR1 = 10309; // 5 -static const uint64_t SH_FLD_INTR_GRANTED = 10310; // 30 -static const uint64_t SH_FLD_INT_0 = 10311; // 4 -static const uint64_t SH_FLD_INT_0_LEN = 10312; // 4 -static const uint64_t SH_FLD_INT_1 = 10313; // 2 -static const uint64_t SH_FLD_INT_1_LEN = 10314; // 2 -static const uint64_t SH_FLD_INT_2 = 10315; // 2 -static const uint64_t SH_FLD_INT_2_LEN = 10316; // 2 -static const uint64_t SH_FLD_INT_3 = 10317; // 2 -static const uint64_t SH_FLD_INT_3_LEN = 10318; // 2 -static const uint64_t SH_FLD_INT_CNTR_REF = 10319; // 1 -static const uint64_t SH_FLD_INT_CNTR_REF_LEN = 10320; // 1 -static const uint64_t SH_FLD_INT_CURRENT_STATE = 10321; // 6 -static const uint64_t SH_FLD_INT_CURRENT_STATE_LEN = 10322; // 6 -static const uint64_t SH_FLD_INT_ENA = 10323; // 1 -static const uint64_t SH_FLD_INT_ENABLE_ENC = 10324; // 6 -static const uint64_t SH_FLD_INT_ENABLE_ENC_LEN = 10325; // 6 -static const uint64_t SH_FLD_INT_GOTO_STATE = 10326; // 6 -static const uint64_t SH_FLD_INT_GOTO_STATE_LEN = 10327; // 6 -static const uint64_t SH_FLD_INT_MODE = 10328; // 6 -static const uint64_t SH_FLD_INT_MODE_LEN = 10329; // 6 -static const uint64_t SH_FLD_INT_NCE_ETE_ATTN = 10330; // 2 -static const uint64_t SH_FLD_INT_NEXT_STATE = 10331; // 6 -static const uint64_t SH_FLD_INT_NEXT_STATE_LEN = 10332; // 6 -static const uint64_t SH_FLD_INT_RETURN_STATE = 10333; // 6 -static const uint64_t SH_FLD_INT_RETURN_STATE_LEN = 10334; // 6 -static const uint64_t SH_FLD_INT_RX_FSM = 10335; // 43 -static const uint64_t SH_FLD_INT_STATE_ERR = 10336; // 1 -static const uint64_t SH_FLD_INT_TX_FSM = 10337; // 43 -static const uint64_t SH_FLD_INT_TYPE = 10338; // 43 -static const uint64_t SH_FLD_INVALIDATE_ADDRESS = 10339; // 1 -static const uint64_t SH_FLD_INVALIDATE_ADDRESS_LEN = 10340; // 1 -static const uint64_t SH_FLD_INVALIDATE_ALL = 10341; // 1 -static const uint64_t SH_FLD_INVALIDATE_ONE = 10342; // 1 -static const uint64_t SH_FLD_INVALIDATE_PE_NUMBER = 10343; // 1 -static const uint64_t SH_FLD_INVALIDATE_PE_NUMBER_LEN = 10344; // 1 -static const uint64_t SH_FLD_INVALID_ADDRESS = 10345; // 12 -static const uint64_t SH_FLD_INVALID_ADDRESS_ALIGNMENT = 10346; // 4 -static const uint64_t SH_FLD_INVALID_ADDRESS_MASK = 10347; // 8 -static const uint64_t SH_FLD_INVALID_CMD_0 = 10348; // 4 -static const uint64_t SH_FLD_INVALID_CMD_1 = 10349; // 2 -static const uint64_t SH_FLD_INVALID_CMD_2 = 10350; // 2 -static const uint64_t SH_FLD_INVALID_CMD_3 = 10351; // 2 -static const uint64_t SH_FLD_INVALID_COMMAND = 10352; // 4 -static const uint64_t SH_FLD_INVALID_CRESP = 10353; // 4 -static const uint64_t SH_FLD_INVALID_CRESP_ERR = 10354; // 1 -static const uint64_t SH_FLD_INVALID_CRESP_ERROR = 10355; // 2 -static const uint64_t SH_FLD_INVALID_MAINT_ADDRESS = 10356; // 4 -static const uint64_t SH_FLD_INVALID_MAINT_ADDRESS_LEN = 10357; // 2 -static const uint64_t SH_FLD_INVALID_REQTYPE = 10358; // 16 -static const uint64_t SH_FLD_INVALID_REQTYPE_ERR_MASK = 10359; // 8 -static const uint64_t SH_FLD_INVALID_REQTYPE_LEN = 10360; // 8 -static const uint64_t SH_FLD_INVALID_REQ_SOURCE = 10361; // 8 -static const uint64_t SH_FLD_INVALID_REQ_SOURCE_LEN = 10362; // 8 -static const uint64_t SH_FLD_INVALID_STATE_RECOV = 10363; // 1 -static const uint64_t SH_FLD_INVALID_STATE_UNRECOV = 10364; // 1 -static const uint64_t SH_FLD_INVALID_TRANSFER_SIZE = 10365; // 4 -static const uint64_t SH_FLD_INVALID_TTYPE = 10366; // 4 -static const uint64_t SH_FLD_INVAL_IODA_TBL_SEL_ESR = 10367; // 1 -static const uint64_t SH_FLD_INVERTED_VDM_DATA = 10368; // 6 -static const uint64_t SH_FLD_INVERTED_VDM_DATA_LEN = 10369; // 6 -static const uint64_t SH_FLD_INVLD_CMD_ERR = 10370; // 1 -static const uint64_t SH_FLD_INVLD_PRGM_ERR = 10371; // 1 -static const uint64_t SH_FLD_INV_PROT_ERR_CHK_DIS = 10372; // 1 -static const uint64_t SH_FLD_INV_SH_ERROR_RATE = 10373; // 2 -static const uint64_t SH_FLD_INV_SH_ERROR_RATE_LEN = 10374; // 2 -static const uint64_t SH_FLD_INV_SINGLE_THREAD_EN = 10375; // 1 -static const uint64_t SH_FLD_INV_SM_CTL_ERR_DET = 10376; // 1 -static const uint64_t SH_FLD_INV_TIMEOUT_CHK_DIS = 10377; // 1 -static const uint64_t SH_FLD_INV_TIMEOUT_ERR_DET = 10378; // 1 -static const uint64_t SH_FLD_IN_BAD_OP_ERR = 10379; // 2 -static const uint64_t SH_FLD_IN_CERR_BIT10 = 10380; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT11 = 10381; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT12 = 10382; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT13 = 10383; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT14 = 10384; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT15 = 10385; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT16 = 10386; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT17 = 10387; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT18 = 10388; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT19 = 10389; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT20 = 10390; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT21 = 10391; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT22 = 10392; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT23 = 10393; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT24 = 10394; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT25 = 10395; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT26 = 10396; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT27 = 10397; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT28 = 10398; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT29 = 10399; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT30 = 10400; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT31 = 10401; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT4 = 10402; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT5 = 10403; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT6 = 10404; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT7 = 10405; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT8 = 10406; // 1 -static const uint64_t SH_FLD_IN_CERR_BIT9 = 10407; // 1 -static const uint64_t SH_FLD_IN_CERR_RESET = 10408; // 1 -static const uint64_t SH_FLD_IN_COUNT1 = 10409; // 1 -static const uint64_t SH_FLD_IN_COUNT1_LEN = 10410; // 1 -static const uint64_t SH_FLD_IN_COUNT2 = 10411; // 1 -static const uint64_t SH_FLD_IN_COUNT2_LEN = 10412; // 1 -static const uint64_t SH_FLD_IN_DELAY1 = 10413; // 1 -static const uint64_t SH_FLD_IN_DELAY1_LEN = 10414; // 1 -static const uint64_t SH_FLD_IN_DELAY2 = 10415; // 1 -static const uint64_t SH_FLD_IN_DELAY2_LEN = 10416; // 1 -static const uint64_t SH_FLD_IN_ECC_CE_ERROR = 10417; // 2 -static const uint64_t SH_FLD_IN_ECC_SUE_ERROR = 10418; // 2 -static const uint64_t SH_FLD_IN_ECC_UE_ERROR = 10419; // 2 -static const uint64_t SH_FLD_IN_LEN = 10420; // 264 -static const uint64_t SH_FLD_IN_LOGIC_HW_ERROR = 10421; // 2 -static const uint64_t SH_FLD_IN_MASTER_MODE = 10422; // 43 -static const uint64_t SH_FLD_IN_PARITY_ERROR = 10423; // 2 -static const uint64_t SH_FLD_IN_PROG = 10424; // 1 -static const uint64_t SH_FLD_IN_PROG_LEN = 10425; // 1 -static const uint64_t SH_FLD_IN_SEQ_ERR = 10426; // 2 -static const uint64_t SH_FLD_IN_SEQ_PERR = 10427; // 2 -static const uint64_t SH_FLD_IN_SLAVE_MODE = 10428; // 43 -static const uint64_t SH_FLD_IN_SNP_ADDR_PERR = 10429; // 2 -static const uint64_t SH_FLD_IN_SNP_TTAG_PERR = 10430; // 2 -static const uint64_t SH_FLD_IN_SW_CAST_ERROR = 10431; // 2 -static const uint64_t SH_FLD_IN_TIMEOUT = 10432; // 2 -static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI = 10433; // 1 -static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN = 10434; // 1 -static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO = 10435; // 1 -static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN = 10436; // 1 -static const uint64_t SH_FLD_IN_TRACE_INT_DATA_HI = 10437; // 1 -static const uint64_t SH_FLD_IN_TRACE_INT_DATA_LO = 10438; // 1 -static const uint64_t SH_FLD_IN_TRACE_INT_TRIG_01 = 10439; // 1 -static const uint64_t SH_FLD_IN_TRACE_INT_TRIG_23 = 10440; // 1 -static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01 = 10441; // 1 -static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN = 10442; // 1 -static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23 = 10443; // 1 -static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN = 10444; // 1 -static const uint64_t SH_FLD_IOCLK_SLIP = 10445; // 72 -static const uint64_t SH_FLD_IOCLK_SLIP_LEN = 10446; // 72 -static const uint64_t SH_FLD_IOCLK_SLIP_STROBE = 10447; // 72 -static const uint64_t SH_FLD_IODA_ADDR_PERR_ESR = 10448; // 1 -static const uint64_t SH_FLD_IOE01_IS_LOGICAL_PAIR = 10449; // 1 -static const uint64_t SH_FLD_IOE23_IS_LOGICAL_PAIR = 10450; // 1 -static const uint64_t SH_FLD_IOE45_IS_LOGICAL_PAIR = 10451; // 1 -static const uint64_t SH_FLD_IOO01_IS_LOGICAL_PAIR = 10452; // 1 -static const uint64_t SH_FLD_IOO23_IS_LOGICAL_PAIR = 10453; // 1 -static const uint64_t SH_FLD_IOO45_IS_LOGICAL_PAIR = 10454; // 1 -static const uint64_t SH_FLD_IOO67_IS_LOGICAL_PAIR = 10455; // 1 -static const uint64_t SH_FLD_IORESET = 10456; // 107 -static const uint64_t SH_FLD_IORESET_HARD_BUS0 = 10457; // 4 -static const uint64_t SH_FLD_IOVALID = 10458; // 1 -static const uint64_t SH_FLD_IOVALID_10D = 10459; // 16 -static const uint64_t SH_FLD_IOVALID_11D = 10460; // 16 -static const uint64_t SH_FLD_IOVALID_4D = 10461; // 8 -static const uint64_t SH_FLD_IOVALID_5D = 10462; // 9 -static const uint64_t SH_FLD_IOVALID_6D = 10463; // 16 -static const uint64_t SH_FLD_IOVALID_7D = 10464; // 16 -static const uint64_t SH_FLD_IOVALID_8D = 10465; // 16 -static const uint64_t SH_FLD_IOVALID_9D = 10466; // 16 -static const uint64_t SH_FLD_IP = 10467; // 4 -static const uint64_t SH_FLD_IPB = 10468; // 1 -static const uint64_t SH_FLD_IPB_LEN = 10469; // 1 -static const uint64_t SH_FLD_IPI = 10470; // 1 -static const uint64_t SH_FLD_IPI0_HI_PRIORITY = 10471; // 1 -static const uint64_t SH_FLD_IPI0_LO_PRIORITY = 10472; // 1 -static const uint64_t SH_FLD_IPI1_HI_PRIORITY = 10473; // 1 -static const uint64_t SH_FLD_IPI1_LO_PRIORITY = 10474; // 1 -static const uint64_t SH_FLD_IPI2_HI_PRIORITY = 10475; // 1 -static const uint64_t SH_FLD_IPI2_LO_PRIORITY = 10476; // 1 -static const uint64_t SH_FLD_IPI3_HI_PRIORITY = 10477; // 1 -static const uint64_t SH_FLD_IPI3_LO_PRIORITY = 10478; // 1 -static const uint64_t SH_FLD_IPI4_HI_PRIORITY = 10479; // 1 -static const uint64_t SH_FLD_IPI4_LO_PRIORITY = 10480; // 1 -static const uint64_t SH_FLD_IPI_LEN = 10481; // 1 -static const uint64_t SH_FLD_IPI_PRIORITY = 10482; // 1 -static const uint64_t SH_FLD_IPI_PRIORITY_LEN = 10483; // 1 -static const uint64_t SH_FLD_IPI_RSD = 10484; // 1 -static const uint64_t SH_FLD_IPI_RSD_LEN = 10485; // 1 -static const uint64_t SH_FLD_IPOLL_0 = 10486; // 1 -static const uint64_t SH_FLD_IPOLL_1 = 10487; // 1 -static const uint64_t SH_FLD_IPOLL_2 = 10488; // 1 -static const uint64_t SH_FLD_IPOLL_3 = 10489; // 1 -static const uint64_t SH_FLD_IPOLL_4 = 10490; // 1 -static const uint64_t SH_FLD_IPOLL_5 = 10491; // 1 -static const uint64_t SH_FLD_IPW_SIDEAB_SEL = 10492; // 8 -static const uint64_t SH_FLD_IPW_WR_WR = 10493; // 8 -static const uint64_t SH_FLD_IPW_WR_WR_LEN = 10494; // 8 -static const uint64_t SH_FLD_IQSPD_CFG = 10495; // 4 -static const uint64_t SH_FLD_IQSPD_CFG_LEN = 10496; // 4 -static const uint64_t SH_FLD_IR = 10497; // 21 -static const uint64_t SH_FLD_IREF_BYPASS = 10498; // 2 -static const uint64_t SH_FLD_IREF_PDWN_B = 10499; // 2 -static const uint64_t SH_FLD_IREF_RES_DAC = 10500; // 2 -static const uint64_t SH_FLD_IREF_RES_DAC_LEN = 10501; // 2 -static const uint64_t SH_FLD_IRQ = 10502; // 1 -static const uint64_t SH_FLD_IRQENA = 10503; // 1 -static const uint64_t SH_FLD_IRQ_LEN = 10504; // 1 -static const uint64_t SH_FLD_IRQ_TRACE_ENABLE = 10505; // 1 -static const uint64_t SH_FLD_IR_DR_EQ0_ERR = 10506; // 1 -static const uint64_t SH_FLD_IR_LEN = 10507; // 21 -static const uint64_t SH_FLD_IS = 10508; // 8 -static const uint64_t SH_FLD_IS_ACTIVE_MASTER = 10509; // 1 -static const uint64_t SH_FLD_IS_BACKUP_MASTER = 10510; // 1 -static const uint64_t SH_FLD_IS_LEN = 10511; // 8 -static const uint64_t SH_FLD_IS_PRIMARY = 10512; // 1 -static const uint64_t SH_FLD_IS_RUNNING = 10513; // 2 -static const uint64_t SH_FLD_IS_SECONDARY = 10514; // 1 -static const uint64_t SH_FLD_IS_SLAVE = 10515; // 1 -static const uint64_t SH_FLD_IS_SPECIAL = 10516; // 1 -static const uint64_t SH_FLD_ITUNE = 10517; // 4 -static const uint64_t SH_FLD_ITUNE_LEN = 10518; // 4 -static const uint64_t SH_FLD_IVC = 10519; // 1 -static const uint64_t SH_FLD_IVC_INTF_DISABLE = 10520; // 6 -static const uint64_t SH_FLD_IVC_LEN = 10521; // 1 -static const uint64_t SH_FLD_IVE_BLOCK = 10522; // 1 -static const uint64_t SH_FLD_IVE_BLOCK_LEN = 10523; // 1 -static const uint64_t SH_FLD_IVE_INDEX = 10524; // 1 -static const uint64_t SH_FLD_IVE_INDEX_LEN = 10525; // 1 -static const uint64_t SH_FLD_IVPR = 10526; // 5 -static const uint64_t SH_FLD_IVPR_LEN = 10527; // 5 -static const uint64_t SH_FLD_IVRM_BYPASS_B = 10528; // 30 -static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY = 10529; // 6 -static const uint64_t SH_FLD_IVRM_IVID = 10530; // 30 -static const uint64_t SH_FLD_IVRM_IVID_LEN = 10531; // 30 -static const uint64_t SH_FLD_IVRM_LOCAL_CONTROL = 10532; // 24 -static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE = 10533; // 30 -static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN = 10534; // 30 -static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE = 10535; // 30 -static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN = 10536; // 30 -static const uint64_t SH_FLD_IVRM_POWERON = 10537; // 30 -static const uint64_t SH_FLD_IVRM_PVREF_ERROR = 10538; // 1 -static const uint64_t SH_FLD_IVRM_UREG_TEST_EN = 10539; // 24 -static const uint64_t SH_FLD_IVRM_UREG_TEST_ID = 10540; // 24 -static const uint64_t SH_FLD_IVRM_UREG_TEST_ID_LEN = 10541; // 24 -static const uint64_t SH_FLD_IVRM_VID_DONE = 10542; // 30 -static const uint64_t SH_FLD_IVRM_VID_VALID = 10543; // 30 -static const uint64_t SH_FLD_IVRM_VREG_SLOW_DC = 10544; // 30 -static const uint64_t SH_FLD_I_DELAY_ADJUST_RATIO = 10545; // 1 -static const uint64_t SH_FLD_I_DELAY_ADJUST_RATIO_LEN = 10546; // 1 -static const uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT = 10547; // 1 -static const uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 10548; // 1 -static const uint64_t SH_FLD_I_PATH_DELAY_ADJUST = 10549; // 1 -static const uint64_t SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY = 10550; // 4 -static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD = 10551; // 1 -static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 10552; // 1 -static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 10553; // 1 -static const uint64_t SH_FLD_I_PATH_DELAY_VALUE = 10554; // 2 -static const uint64_t SH_FLD_I_PATH_DELAY_VALUE_LEN = 10555; // 2 -static const uint64_t SH_FLD_I_PATH_FSM_STATE_PARITY = 10556; // 4 -static const uint64_t SH_FLD_I_PATH_STATE = 10557; // 1 -static const uint64_t SH_FLD_I_PATH_STATE_LEN = 10558; // 1 -static const uint64_t SH_FLD_I_PATH_STEP_CHECK = 10559; // 4 -static const uint64_t SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 10560; // 1 -static const uint64_t SH_FLD_I_PATH_STEP_CHECK_VALID = 10561; // 1 -static const uint64_t SH_FLD_I_PATH_SYNC_CHECK = 10562; // 4 -static const uint64_t SH_FLD_I_PATH_SYNC_CHECK_DISABLE = 10563; // 1 -static const uint64_t SH_FLD_I_PATH_TIME_OVERFLOW = 10564; // 3 -static const uint64_t SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 10565; // 1 -static const uint64_t SH_FLD_I_PATH_TIME_PARITY = 10566; // 4 -static const uint64_t SH_FLD_JITTER_EPSILON = 10567; // 8 -static const uint64_t SH_FLD_JITTER_EPSILON_LEN = 10568; // 8 -static const uint64_t SH_FLD_JTAGACC_CERRPT = 10569; // 1 -static const uint64_t SH_FLD_JTAGACC_CERRPT_LEN = 10570; // 1 -static const uint64_t SH_FLD_JTAGACC_ERR = 10571; // 1 -static const uint64_t SH_FLD_JTAGACC_ERR_MASK = 10572; // 1 -static const uint64_t SH_FLD_JTAG_INPROG = 10573; // 1 -static const uint64_t SH_FLD_JTAG_INSTR = 10574; // 1 -static const uint64_t SH_FLD_JTAG_INSTR_LEN = 10575; // 1 -static const uint64_t SH_FLD_JTAG_SRC_SEL = 10576; // 1 -static const uint64_t SH_FLD_JTAG_TDI = 10577; // 1 -static const uint64_t SH_FLD_JTAG_TDI_LEN = 10578; // 1 -static const uint64_t SH_FLD_JTAG_TDO = 10579; // 1 -static const uint64_t SH_FLD_JTAG_TDO_LEN = 10580; // 1 -static const uint64_t SH_FLD_JTAG_TRST_B = 10581; // 1 -static const uint64_t SH_FLD_KEEP_MS_MODE = 10582; // 43 -static const uint64_t SH_FLD_KPRIME = 10583; // 8 -static const uint64_t SH_FLD_L = 10584; // 8 -static const uint64_t SH_FLD_L2 = 10585; // 12 -static const uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C0 = 10586; // 12 -static const uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C1 = 10587; // 12 -static const uint64_t SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET = 10588; // 6 -static const uint64_t SH_FLD_L2_EX0_CLKGLM_SEL = 10589; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_OVERRIDE = 10590; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE = 10591; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN = 10592; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN = 10593; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_SPARE0 = 10594; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH = 10595; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN = 10596; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SW_OVERRIDE = 10597; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK = 10598; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN = 10599; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SW_SPARE1 = 10600; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SYNC = 10601; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SYNC_DONE = 10602; // 6 -static const uint64_t SH_FLD_L2_EX0_CLK_SYNC_ENABLE = 10603; // 6 -static const uint64_t SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET = 10604; // 6 -static const uint64_t SH_FLD_L2_EX1_CLKGLM_SEL = 10605; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_OVERRIDE = 10606; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE = 10607; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN = 10608; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN = 10609; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_SPARE0 = 10610; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH = 10611; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN = 10612; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SW_OVERRIDE = 10613; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK = 10614; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN = 10615; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SW_SPARE1 = 10616; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SYNC = 10617; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SYNC_DONE = 10618; // 6 -static const uint64_t SH_FLD_L2_EX1_CLK_SYNC_ENABLE = 10619; // 6 -static const uint64_t SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 = 10620; // 12 -static const uint64_t SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 10621; // 12 -static const uint64_t SH_FLD_L2_LEN = 10622; // 12 -static const uint64_t SH_FLD_L2_PURGE = 10623; // 12 -static const uint64_t SH_FLD_L2_PURGE_ABORT = 10624; // 12 -static const uint64_t SH_FLD_L2_PURGE_DONE = 10625; // 24 -static const uint64_t SH_FLD_L2_STEP_MODE = 10626; // 12 -static const uint64_t SH_FLD_L2_STEP_MODE_LEN = 10627; // 12 -static const uint64_t SH_FLD_L2_STOPPED = 10628; // 1 -static const uint64_t SH_FLD_L2_STOPPED_LEN = 10629; // 1 -static const uint64_t SH_FLD_L3 = 10630; // 24 -static const uint64_t SH_FLD_L3CERRS_CFG_DCACHE_CAPP = 10631; // 12 -static const uint64_t SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS = 10632; // 12 -static const uint64_t SH_FLD_L3CICTL_CI_OVERRUN_CK = 10633; // 12 -static const uint64_t SH_FLD_L3CORTR_NO_LCO_TGTS = 10634; // 12 -static const uint64_t SH_FLD_L3L2CTL_PF_OVERRUN_CK = 10635; // 12 -static const uint64_t SH_FLD_L3L2CTL_RD_OVERRUN_CK = 10636; // 12 -static const uint64_t SH_FLD_L3PBEXCA0_OVERFLOW = 10637; // 12 -static const uint64_t SH_FLD_L3PBEXCA0_UNDERFLOW = 10638; // 12 -static const uint64_t SH_FLD_L3PBEXCA1_OVERFLOW = 10639; // 12 -static const uint64_t SH_FLD_L3PBEXCA1_UNDERFLOW = 10640; // 12 -static const uint64_t SH_FLD_L3SDRTL0_BAD_HPC = 10641; // 12 -static const uint64_t SH_FLD_L3SDRTL0_CACHE_INHIBIT = 10642; // 12 -static const uint64_t SH_FLD_L3SDRTL1_BAD_HPC = 10643; // 12 -static const uint64_t SH_FLD_L3SDRTL1_CACHE_INHIBIT = 10644; // 12 -static const uint64_t SH_FLD_L3SDRTL2_BAD_HPC = 10645; // 12 -static const uint64_t SH_FLD_L3SDRTL2_CACHE_INHIBIT = 10646; // 12 -static const uint64_t SH_FLD_L3SDRTL3_BAD_HPC = 10647; // 12 -static const uint64_t SH_FLD_L3SDRTL3_CACHE_INHIBIT = 10648; // 12 -static const uint64_t SH_FLD_L3XMEMA0_CRW_DIR_HIT = 10649; // 12 -static const uint64_t SH_FLD_L3XMEMA0_DW_DIR_HIT = 10650; // 12 -static const uint64_t SH_FLD_L3XMEMA1_CRW_DIR_HIT = 10651; // 12 -static const uint64_t SH_FLD_L3XMEMA1_DW_DIR_HIT = 10652; // 12 -static const uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME = 10653; // 12 -static const uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME_LEN = 10654; // 12 -static const uint64_t SH_FLD_L3_1ST_BEAT_UE = 10655; // 12 -static const uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME = 10656; // 12 -static const uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME_LEN = 10657; // 12 -static const uint64_t SH_FLD_L3_2ND_BEAT_UE = 10658; // 12 -static const uint64_t SH_FLD_L3_ABORT = 10659; // 12 -static const uint64_t SH_FLD_L3_ADDR_HANG_DETECTED = 10660; // 12 -static const uint64_t SH_FLD_L3_ADDR_HASH_EN_CFG = 10661; // 12 -static const uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR = 10662; // 12 -static const uint64_t SH_FLD_L3_BANK = 10663; // 12 -static const uint64_t SH_FLD_L3_BANK_LEN = 10664; // 12 -static const uint64_t SH_FLD_L3_BUSY_ERR = 10665; // 36 -static const uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 10666; // 12 -static const uint64_t SH_FLD_L3_CAC_RD_SUE_DET = 10667; // 12 -static const uint64_t SH_FLD_L3_CAC_RD_UE_DET = 10668; // 12 -static const uint64_t SH_FLD_L3_CAC_TYPE = 10669; // 12 -static const uint64_t SH_FLD_L3_CAC_TYPE_LEN = 10670; // 12 -static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 = 10671; // 12 -static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB = 10672; // 12 -static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 10673; // 12 -static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB = 10674; // 12 -static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 = 10675; // 12 -static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB = 10676; // 12 -static const uint64_t SH_FLD_L3_CFG = 10677; // 36 -static const uint64_t SH_FLD_L3_CFG_LEN = 10678; // 12 -static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE = 10679; // 6 -static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_EN = 10680; // 6 -static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_LEN = 10681; // 6 -static const uint64_t SH_FLD_L3_CLK_SB_SPARE0 = 10682; // 6 -static const uint64_t SH_FLD_L3_CLK_SB_STRENGTH = 10683; // 6 -static const uint64_t SH_FLD_L3_CLK_SB_STRENGTH_LEN = 10684; // 6 -static const uint64_t SH_FLD_L3_COLUMN_MD_CFG = 10685; // 12 -static const uint64_t SH_FLD_L3_COLUMN_MD_CFG_LEN = 10686; // 12 -static const uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG = 10687; // 12 -static const uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN = 10688; // 12 -static const uint64_t SH_FLD_L3_CP_UTIL_EN_DC = 10689; // 12 -static const uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL = 10690; // 12 -static const uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL_LEN = 10691; // 12 -static const uint64_t SH_FLD_L3_CP_UTIL_SEL_DC = 10692; // 12 -static const uint64_t SH_FLD_L3_CP_UTIL_SEL_DC_LEN = 10693; // 12 -static const uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV = 10694; // 12 -static const uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN = 10695; // 12 -static const uint64_t SH_FLD_L3_DIR_ADDR = 10696; // 24 -static const uint64_t SH_FLD_L3_DIR_ADDR_LEN = 10697; // 24 -static const uint64_t SH_FLD_L3_DIR_RD_CE_DET = 10698; // 12 -static const uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR = 10699; // 12 -static const uint64_t SH_FLD_L3_DIR_RD_UE_DET = 10700; // 12 -static const uint64_t SH_FLD_L3_DIR_TYPE = 10701; // 12 -static const uint64_t SH_FLD_L3_DISABLED_CFG = 10702; // 12 -static const uint64_t SH_FLD_L3_DMAP_CI_EN_CFG = 10703; // 12 -static const uint64_t SH_FLD_L3_DRAM_ERROR = 10704; // 12 -static const uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL = 10705; // 12 -static const uint64_t SH_FLD_L3_DW = 10706; // 12 -static const uint64_t SH_FLD_L3_DW_LEN = 10707; // 12 -static const uint64_t SH_FLD_L3_DYN_LCO_BLK_DIS_CFG = 10708; // 12 -static const uint64_t SH_FLD_L3_EDRAM_ENABLE0 = 10709; // 43 -static const uint64_t SH_FLD_L3_EDRAM_ENABLE1 = 10710; // 43 -static const uint64_t SH_FLD_L3_EDRAM_PGATE_ERR = 10711; // 6 -static const uint64_t SH_FLD_L3_EDRAM_SEQ_ERR = 10712; // 6 -static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL = 10713; // 6 -static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN = 10714; // 6 -static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE = 10715; // 6 -static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE_LEN = 10716; // 6 -static const uint64_t SH_FLD_L3_EX0_EDRAM_UNLOCKED = 10717; // 6 -static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL = 10718; // 6 -static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN = 10719; // 6 -static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE = 10720; // 6 -static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE_LEN = 10721; // 6 -static const uint64_t SH_FLD_L3_EX1_EDRAM_UNLOCKED = 10722; // 6 -static const uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV = 10723; // 12 -static const uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN = 10724; // 12 -static const uint64_t SH_FLD_L3_HW_CONTROL_ERR = 10725; // 12 -static const uint64_t SH_FLD_L3_LCO_ADDR_TGT_ENABLE = 10726; // 12 -static const uint64_t SH_FLD_L3_LCO_ENABLE_CFG = 10727; // 12 -static const uint64_t SH_FLD_L3_LCO_RTY_LIMIT_DISABLE = 10728; // 12 -static const uint64_t SH_FLD_L3_LCO_TARGET_GROUP = 10729; // 12 -static const uint64_t SH_FLD_L3_LCO_TARGET_ID = 10730; // 12 -static const uint64_t SH_FLD_L3_LCO_TARGET_ID_LEN = 10731; // 12 -static const uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS = 10732; // 12 -static const uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS_LEN = 10733; // 12 -static const uint64_t SH_FLD_L3_LEN = 10734; // 24 -static const uint64_t SH_FLD_L3_LINE_DEL_CE_DONE = 10735; // 12 -static const uint64_t SH_FLD_L3_LINE_DEL_ON_ALL_CE = 10736; // 24 -static const uint64_t SH_FLD_L3_LINE_DEL_ON_NEXT_CE = 10737; // 24 -static const uint64_t SH_FLD_L3_LRU_ERROR = 10738; // 12 -static const uint64_t SH_FLD_L3_LRU_INVAL_CNT = 10739; // 12 -static const uint64_t SH_FLD_L3_MACH_HANG_DETECTED = 10740; // 12 -static const uint64_t SH_FLD_L3_MEMBER = 10741; // 24 -static const uint64_t SH_FLD_L3_MEMBER_LEN = 10742; // 24 -static const uint64_t SH_FLD_L3_NO_ALLOCATE_ACTIVE = 10743; // 12 -static const uint64_t SH_FLD_L3_NO_ALLOCATE_EN = 10744; // 12 -static const uint64_t SH_FLD_L3_PB_MAST_RD_ACK_DEAD = 10745; // 12 -static const uint64_t SH_FLD_L3_PB_MAST_RD_ADDR_ERR = 10746; // 12 -static const uint64_t SH_FLD_L3_PB_MAST_WR_ACK_DEAD = 10747; // 12 -static const uint64_t SH_FLD_L3_PB_MAST_WR_ADDR_ERR = 10748; // 12 -static const uint64_t SH_FLD_L3_PPE_RD_CE_DET = 10749; // 12 -static const uint64_t SH_FLD_L3_PPE_RD_SUE_DET = 10750; // 12 -static const uint64_t SH_FLD_L3_PPE_RD_UE_DET = 10751; // 12 -static const uint64_t SH_FLD_L3_RA = 10752; // 12 -static const uint64_t SH_FLD_L3_RA_LEN = 10753; // 12 -static const uint64_t SH_FLD_L3_RDSN_LINEDEL_UE_EN = 10754; // 12 -static const uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR = 10755; // 12 -static const uint64_t SH_FLD_L3_REQ = 10756; // 36 -static const uint64_t SH_FLD_L3_SCOM_CINJ_LCO_DIS = 10757; // 12 -static const uint64_t SH_FLD_L3_SCOM_INIT = 10758; // 12 -static const uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE = 10759; // 12 -static const uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR = 10760; // 12 -static const uint64_t SH_FLD_L3_SCOM_QUIESCE_REFRESH = 10761; // 12 -static const uint64_t SH_FLD_L3_SINGLE_CAC = 10762; // 12 -static const uint64_t SH_FLD_L3_SINGLE_DIR = 10763; // 12 -static const uint64_t SH_FLD_L3_SINGLE_LRU = 10764; // 12 -static const uint64_t SH_FLD_L3_SNP_CACHE_INHIBIT_ERR = 10765; // 12 -static const uint64_t SH_FLD_L3_SOLID_CAC = 10766; // 12 -static const uint64_t SH_FLD_L3_SOLID_DIR = 10767; // 12 -static const uint64_t SH_FLD_L3_SOLID_LRU = 10768; // 12 -static const uint64_t SH_FLD_L3_SPARE0 = 10769; // 12 -static const uint64_t SH_FLD_L3_SPARE1 = 10770; // 12 -static const uint64_t SH_FLD_L3_SPARE2 = 10771; // 12 -static const uint64_t SH_FLD_L3_SPARE3 = 10772; // 24 -static const uint64_t SH_FLD_L3_SPARE5 = 10773; // 12 -static const uint64_t SH_FLD_L3_SPARE6 = 10774; // 12 -static const uint64_t SH_FLD_L3_SPARE7 = 10775; // 12 -static const uint64_t SH_FLD_L3_STOPPED = 10776; // 1 -static const uint64_t SH_FLD_L3_STOPPED_LEN = 10777; // 1 -static const uint64_t SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL = 10778; // 12 -static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR = 10779; // 12 -static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN = 10780; // 12 -static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR = 10781; // 12 -static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN = 10782; // 12 -static const uint64_t SH_FLD_L3_TTYPE = 10783; // 24 -static const uint64_t SH_FLD_L3_TTYPE_LEN = 10784; // 24 -static const uint64_t SH_FLD_L3_UTIL_MON_BITS = 10785; // 12 -static const uint64_t SH_FLD_L3_UTIL_MON_BITS_LEN = 10786; // 12 -static const uint64_t SH_FLD_L3_VAL = 10787; // 12 -static const uint64_t SH_FLD_LANE00 = 10788; // 4 -static const uint64_t SH_FLD_LANE00_LEN = 10789; // 4 -static const uint64_t SH_FLD_LANE01 = 10790; // 4 -static const uint64_t SH_FLD_LANE01_LEN = 10791; // 4 -static const uint64_t SH_FLD_LANE02 = 10792; // 4 -static const uint64_t SH_FLD_LANE02_LEN = 10793; // 4 -static const uint64_t SH_FLD_LANE03 = 10794; // 4 -static const uint64_t SH_FLD_LANE03_LEN = 10795; // 4 -static const uint64_t SH_FLD_LANE04 = 10796; // 4 -static const uint64_t SH_FLD_LANE04_LEN = 10797; // 4 -static const uint64_t SH_FLD_LANE05 = 10798; // 4 -static const uint64_t SH_FLD_LANE05_LEN = 10799; // 4 -static const uint64_t SH_FLD_LANE06 = 10800; // 4 -static const uint64_t SH_FLD_LANE06_LEN = 10801; // 4 -static const uint64_t SH_FLD_LANE07 = 10802; // 4 -static const uint64_t SH_FLD_LANE07_LEN = 10803; // 4 -static const uint64_t SH_FLD_LANE08 = 10804; // 4 -static const uint64_t SH_FLD_LANE08_LEN = 10805; // 4 -static const uint64_t SH_FLD_LANE09 = 10806; // 4 -static const uint64_t SH_FLD_LANE09_LEN = 10807; // 4 -static const uint64_t SH_FLD_LANE10 = 10808; // 4 -static const uint64_t SH_FLD_LANE10_LEN = 10809; // 4 -static const uint64_t SH_FLD_LANE11 = 10810; // 4 -static const uint64_t SH_FLD_LANE11_LEN = 10811; // 4 -static const uint64_t SH_FLD_LANE_ANA_PDWN = 10812; // 120 -static const uint64_t SH_FLD_LANE_BAD_VEC_0_15 = 10813; // 4 -static const uint64_t SH_FLD_LANE_BAD_VEC_0_15_LEN = 10814; // 4 -static const uint64_t SH_FLD_LANE_BAD_VEC_16_23 = 10815; // 4 -static const uint64_t SH_FLD_LANE_BAD_VEC_16_23_LEN = 10816; // 4 -static const uint64_t SH_FLD_LANE_BIST_ACTVITY_DET = 10817; // 116 -static const uint64_t SH_FLD_LANE_BIST_ERR = 10818; // 116 -static const uint64_t SH_FLD_LANE_DIG_PDWN = 10819; // 120 -static const uint64_t SH_FLD_LANE_DISABLED = 10820; // 48 -static const uint64_t SH_FLD_LANE_DISABLED_VEC_0_15 = 10821; // 8 -static const uint64_t SH_FLD_LANE_DISABLED_VEC_0_15_LEN = 10822; // 8 -static const uint64_t SH_FLD_LANE_DISABLED_VEC_16_23 = 10823; // 8 -static const uint64_t SH_FLD_LANE_DISABLED_VEC_16_23_LEN = 10824; // 8 -static const uint64_t SH_FLD_LANE_INVALID = 10825; // 72 -static const uint64_t SH_FLD_LANE_INVERT = 10826; // 190 -static const uint64_t SH_FLD_LANE_PDWN = 10827; // 116 -static const uint64_t SH_FLD_LANE_QUIESCE = 10828; // 117 -static const uint64_t SH_FLD_LANE_QUIESCE_LEN = 10829; // 117 -static const uint64_t SH_FLD_LANE_SCRAMBLE_DISABLE = 10830; // 140 -static const uint64_t SH_FLD_LARGER_DROOP_EVENT_CTR = 10831; // 12 -static const uint64_t SH_FLD_LARGER_DROOP_EVENT_CTR_LEN = 10832; // 12 -static const uint64_t SH_FLD_LARGE_EVENT_PROFILE_CTR = 10833; // 12 -static const uint64_t SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN = 10834; // 12 -static const uint64_t SH_FLD_LARGE_EVENT_THRESHOLD = 10835; // 12 -static const uint64_t SH_FLD_LARGE_EVENT_THRESHOLD_LEN = 10836; // 12 -static const uint64_t SH_FLD_LAST_BANK = 10837; // 90 -static const uint64_t SH_FLD_LAST_BANK_LEN = 10838; // 90 -static const uint64_t SH_FLD_LAST_BANK_VALID = 10839; // 90 -static const uint64_t SH_FLD_LAST_OPCG_MODE = 10840; // 43 -static const uint64_t SH_FLD_LAST_OPCG_MODE_LEN = 10841; // 43 -static const uint64_t SH_FLD_LATCANCEL = 10842; // 15 -static const uint64_t SH_FLD_LATCANCEL_LEN = 10843; // 15 -static const uint64_t SH_FLD_LATENCY = 10844; // 6 -static const uint64_t SH_FLD_LATENCY_LEN = 10845; // 6 -static const uint64_t SH_FLD_LATE_LAUNCH_PRIMARY = 10846; // 1 -static const uint64_t SH_FLD_LATE_LAUNCH_SECONDARY = 10847; // 1 -static const uint64_t SH_FLD_LATFINISH = 10848; // 15 -static const uint64_t SH_FLD_LATFINISH_LEN = 10849; // 15 -static const uint64_t SH_FLD_LATSTART = 10850; // 15 -static const uint64_t SH_FLD_LATSTART_LEN = 10851; // 15 -static const uint64_t SH_FLD_LAT_THRESHA = 10852; // 8 -static const uint64_t SH_FLD_LAT_THRESHA_LEN = 10853; // 8 -static const uint64_t SH_FLD_LAT_THRESHB = 10854; // 8 -static const uint64_t SH_FLD_LAT_THRESHB_LEN = 10855; // 8 -static const uint64_t SH_FLD_LAT_THRESHC = 10856; // 8 -static const uint64_t SH_FLD_LAT_THRESHC_LEN = 10857; // 8 -static const uint64_t SH_FLD_LBIST = 10858; // 43 -static const uint64_t SH_FLD_LBIST_SKITTER_CTL = 10859; // 43 -static const uint64_t SH_FLD_LBIST_SKITTER_CTL_LEN = 10860; // 43 -static const uint64_t SH_FLD_LBUS_CLOCK_DIVIDER = 10861; // 2 -static const uint64_t SH_FLD_LBUS_CLOCK_DIVIDER_LEN = 10862; // 2 -static const uint64_t SH_FLD_LBUS_PARITY_ERR1_0 = 10863; // 12 -static const uint64_t SH_FLD_LBUS_PARITY_ERR1_1 = 10864; // 12 -static const uint64_t SH_FLD_LBUS_PARITY_ERR1_2 = 10865; // 12 -static const uint64_t SH_FLD_LBUS_PARITY_ERR1_3 = 10866; // 12 -static const uint64_t SH_FLD_LBUS_PARITY_ERROR_0 = 10867; // 4 -static const uint64_t SH_FLD_LBUS_PARITY_ERROR_1 = 10868; // 2 -static const uint64_t SH_FLD_LBUS_PARITY_ERROR_2 = 10869; // 2 -static const uint64_t SH_FLD_LBUS_PARITY_ERROR_3 = 10870; // 2 -static const uint64_t SH_FLD_LCK_STATUS_PARITY_ERROR = 10871; // 3 -static const uint64_t SH_FLD_LCL_FIRST_GRPSCAN_ENA = 10872; // 1 -static const uint64_t SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA = 10873; // 1 -static const uint64_t SH_FLD_LCO_CRED_MASK = 10874; // 1 -static const uint64_t SH_FLD_LCO_CRED_MASK_LEN = 10875; // 1 -static const uint64_t SH_FLD_LCO_TARG_CONFIG = 10876; // 1 -static const uint64_t SH_FLD_LCO_TARG_CONFIG_LEN = 10877; // 1 -static const uint64_t SH_FLD_LCO_TARG_MIN = 10878; // 1 -static const uint64_t SH_FLD_LCO_TARG_MIN_LEN = 10879; // 1 -static const uint64_t SH_FLD_LD = 10880; // 96 -static const uint64_t SH_FLD_LDQ_DATA_HANG = 10881; // 1 -static const uint64_t SH_FLD_LDQ_EQD_MAX_0_4 = 10882; // 1 -static const uint64_t SH_FLD_LDQ_EQD_MAX_0_4_LEN = 10883; // 1 -static const uint64_t SH_FLD_LDQ_EQD_MIN_0_4 = 10884; // 1 -static const uint64_t SH_FLD_LDQ_EQD_MIN_0_4_LEN = 10885; // 1 -static const uint64_t SH_FLD_LDQ_FSM_PERR = 10886; // 1 -static const uint64_t SH_FLD_LDQ_IVE_MAX_0_4 = 10887; // 1 -static const uint64_t SH_FLD_LDQ_IVE_MAX_0_4_LEN = 10888; // 1 -static const uint64_t SH_FLD_LDQ_IVE_MIN_0_4 = 10889; // 1 -static const uint64_t SH_FLD_LDQ_IVE_MIN_0_4_LEN = 10890; // 1 -static const uint64_t SH_FLD_LDQ_REG_MAX_0_4 = 10891; // 1 -static const uint64_t SH_FLD_LDQ_REG_MAX_0_4_LEN = 10892; // 1 -static const uint64_t SH_FLD_LDQ_REG_MIN_0_4 = 10893; // 1 -static const uint64_t SH_FLD_LDQ_REG_MIN_0_4_LEN = 10894; // 1 -static const uint64_t SH_FLD_LDQ_REG_ORDER_ALL = 10895; // 1 -static const uint64_t SH_FLD_LDQ_THR_MAX_0_4 = 10896; // 1 -static const uint64_t SH_FLD_LDQ_THR_MAX_0_4_LEN = 10897; // 1 -static const uint64_t SH_FLD_LDQ_THR_MIN_0_4 = 10898; // 1 -static const uint64_t SH_FLD_LDQ_THR_MIN_0_4_LEN = 10899; // 1 -static const uint64_t SH_FLD_LDQ_VPC_MAX_0_4 = 10900; // 1 -static const uint64_t SH_FLD_LDQ_VPC_MAX_0_4_LEN = 10901; // 1 -static const uint64_t SH_FLD_LDQ_VPC_MIN_0_4 = 10902; // 1 -static const uint64_t SH_FLD_LDQ_VPC_MIN_0_4_LEN = 10903; // 1 -static const uint64_t SH_FLD_LD_ACK_DEAD = 10904; // 12 -static const uint64_t SH_FLD_LD_ADDR_ERR = 10905; // 12 -static const uint64_t SH_FLD_LD_CLASS_CMD_ADDR_ERR = 10906; // 4 -static const uint64_t SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 10907; // 4 -static const uint64_t SH_FLD_LD_ECC_CE = 10908; // 1 -static const uint64_t SH_FLD_LD_ECC_UE = 10909; // 1 -static const uint64_t SH_FLD_LD_UNLD_DLY = 10910; // 1 -static const uint64_t SH_FLD_LD_UNLD_DLY_LEN = 10911; // 1 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_0 = 10912; // 2 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_0_LEN = 10913; // 2 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_1 = 10914; // 1 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_1_LEN = 10915; // 1 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_2 = 10916; // 1 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_2_LEN = 10917; // 1 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_3 = 10918; // 1 -static const uint64_t SH_FLD_LENGTH_IN_BYTES_3_LEN = 10919; // 1 -static const uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N = 10920; // 96 -static const uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN = 10921; // 96 -static const uint64_t SH_FLD_LFIR_IN = 10922; // 43 -static const uint64_t SH_FLD_LFIR_IN_LEN = 10923; // 43 -static const uint64_t SH_FLD_LFIR_RECOV_ERR = 10924; // 43 -static const uint64_t SH_FLD_LFREQ = 10925; // 1 -static const uint64_t SH_FLD_LFREQ0 = 10926; // 24 -static const uint64_t SH_FLD_LFREQ0_LEN = 10927; // 24 -static const uint64_t SH_FLD_LFREQ1 = 10928; // 24 -static const uint64_t SH_FLD_LFREQ1_LEN = 10929; // 24 -static const uint64_t SH_FLD_LFREQ_LEN = 10930; // 1 -static const uint64_t SH_FLD_LFSR = 10931; // 5 -static const uint64_t SH_FLD_LFSR_ARB_MODE = 10932; // 3 -static const uint64_t SH_FLD_LFSR_DIS = 10933; // 1 -static const uint64_t SH_FLD_LFSR_FAIRNESS_MASK = 10934; // 1 -static const uint64_t SH_FLD_LFSR_FAIRNESS_MASK_LEN = 10935; // 1 -static const uint64_t SH_FLD_LFSR_LEN = 10936; // 5 -static const uint64_t SH_FLD_LIMIT = 10937; // 2 -static const uint64_t SH_FLD_LIMIT_LEN = 10938; // 2 -static const uint64_t SH_FLD_LIM_PS = 10939; // 1 -static const uint64_t SH_FLD_LINEAR_WINDOW_BAR = 10940; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_BAR_LEN = 10941; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_BASE = 10942; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_BASE_LEN = 10943; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_ENABLE = 10944; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_MASK = 10945; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_MASK_LEN = 10946; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_REGION = 10947; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_REGION_LEN = 10948; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_SCRESP = 10949; // 4 -static const uint64_t SH_FLD_LINEAR_WINDOW_SCRESP_LEN = 10950; // 4 -static const uint64_t SH_FLD_LINK00_HI = 10951; // 2 -static const uint64_t SH_FLD_LINK00_HI_LEN = 10952; // 2 -static const uint64_t SH_FLD_LINK00_LO = 10953; // 2 -static const uint64_t SH_FLD_LINK00_LO_LEN = 10954; // 2 -static const uint64_t SH_FLD_LINK01_CAPP_MODE = 10955; // 1 -static const uint64_t SH_FLD_LINK01_DIB_VC_LIMIT = 10956; // 2 -static const uint64_t SH_FLD_LINK01_DIB_VC_LIMIT_LEN = 10957; // 2 -static const uint64_t SH_FLD_LINK01_HI = 10958; // 2 -static const uint64_t SH_FLD_LINK01_HI_LEN = 10959; // 2 -static const uint64_t SH_FLD_LINK01_HRB_INIT_STATE = 10960; // 1 -static const uint64_t SH_FLD_LINK01_LO = 10961; // 2 -static const uint64_t SH_FLD_LINK01_LO_LEN = 10962; // 2 -static const uint64_t SH_FLD_LINK02_HI = 10963; // 2 -static const uint64_t SH_FLD_LINK02_HI_LEN = 10964; // 2 -static const uint64_t SH_FLD_LINK02_LO = 10965; // 2 -static const uint64_t SH_FLD_LINK02_LO_LEN = 10966; // 2 -static const uint64_t SH_FLD_LINK03_HI = 10967; // 2 -static const uint64_t SH_FLD_LINK03_HI_LEN = 10968; // 2 -static const uint64_t SH_FLD_LINK03_LO = 10969; // 2 -static const uint64_t SH_FLD_LINK03_LO_LEN = 10970; // 2 -static const uint64_t SH_FLD_LINK04_HI = 10971; // 2 -static const uint64_t SH_FLD_LINK04_HI_LEN = 10972; // 2 -static const uint64_t SH_FLD_LINK04_LO = 10973; // 2 -static const uint64_t SH_FLD_LINK04_LO_LEN = 10974; // 2 -static const uint64_t SH_FLD_LINK05_HI = 10975; // 2 -static const uint64_t SH_FLD_LINK05_HI_LEN = 10976; // 2 -static const uint64_t SH_FLD_LINK05_LO = 10977; // 2 -static const uint64_t SH_FLD_LINK05_LO_LEN = 10978; // 2 -static const uint64_t SH_FLD_LINK06_HI = 10979; // 1 -static const uint64_t SH_FLD_LINK06_HI_LEN = 10980; // 1 -static const uint64_t SH_FLD_LINK06_LO = 10981; // 1 -static const uint64_t SH_FLD_LINK06_LO_LEN = 10982; // 1 -static const uint64_t SH_FLD_LINK07_HI = 10983; // 1 -static const uint64_t SH_FLD_LINK07_HI_LEN = 10984; // 1 -static const uint64_t SH_FLD_LINK07_LO = 10985; // 1 -static const uint64_t SH_FLD_LINK07_LO_LEN = 10986; // 1 -static const uint64_t SH_FLD_LINK0_ACK_QUEUE_OVERFLOW = 10987; // 4 -static const uint64_t SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW = 10988; // 4 -static const uint64_t SH_FLD_LINK0_COMMAND = 10989; // 5 -static const uint64_t SH_FLD_LINK0_COMMAND_LEN = 10990; // 5 -static const uint64_t SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR = 10991; // 10 -static const uint64_t SH_FLD_LINK0_CRC_ERROR = 10992; // 10 -static const uint64_t SH_FLD_LINK0_CURRENT_STATE = 10993; // 5 -static const uint64_t SH_FLD_LINK0_CURRENT_STATE_LEN = 10994; // 5 -static const uint64_t SH_FLD_LINK0_DESKEW_ERROR = 10995; // 4 -static const uint64_t SH_FLD_LINK0_DESKEW_OVERFLOW = 10996; // 4 -static const uint64_t SH_FLD_LINK0_DOB_LIMIT = 10997; // 1 -static const uint64_t SH_FLD_LINK0_DOB_LIMIT_LEN = 10998; // 1 -static const uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT = 10999; // 2 -static const uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT_LEN = 11000; // 2 -static const uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT = 11001; // 2 -static const uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT_LEN = 11002; // 2 -static const uint64_t SH_FLD_LINK0_ELEVEN_LANE_SHIFT = 11003; // 2 -static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND = 11004; // 5 -static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LANES = 11005; // 5 -static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN = 11006; // 5 -static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LEN = 11007; // 5 -static const uint64_t SH_FLD_LINK0_HOLD_PATT_A = 11008; // 2 -static const uint64_t SH_FLD_LINK0_HOLD_PATT_B = 11009; // 2 -static const uint64_t SH_FLD_LINK0_IGNORE_FENCE = 11010; // 2 -static const uint64_t SH_FLD_LINK0_IGNORE_PHY = 11011; // 2 -static const uint64_t SH_FLD_LINK0_INTERNAL_ERROR = 11012; // 10 -static const uint64_t SH_FLD_LINK0_INVALID_BLOCK = 11013; // 4 -static const uint64_t SH_FLD_LINK0_LOSS_BLOCK_ALIGN = 11014; // 4 -static const uint64_t SH_FLD_LINK0_MAX_PKT_TIMER = 11015; // 5 -static const uint64_t SH_FLD_LINK0_MAX_PKT_TIMER_LEN = 11016; // 5 -static const uint64_t SH_FLD_LINK0_NAK_RECEIVED = 11017; // 10 -static const uint64_t SH_FLD_LINK0_NPU_ERROR = 11018; // 4 -static const uint64_t SH_FLD_LINK0_NUM_REPLAY = 11019; // 4 -static const uint64_t SH_FLD_LINK0_OLL_ENABLED = 11020; // 2 -static const uint64_t SH_FLD_LINK0_OPTICS_IRQ = 11021; // 2 -static const uint64_t SH_FLD_LINK0_OPTICS_RST_B = 11022; // 2 -static const uint64_t SH_FLD_LINK0_OP_IRQ = 11023; // 4 -static const uint64_t SH_FLD_LINK0_PHY_TRAINING = 11024; // 2 -static const uint64_t SH_FLD_LINK0_PRBS_SELECT_ERROR = 11025; // 4 -static const uint64_t SH_FLD_LINK0_PRIOR_STATE = 11026; // 5 -static const uint64_t SH_FLD_LINK0_PRIOR_STATE_LEN = 11027; // 5 -static const uint64_t SH_FLD_LINK0_REPLAY_BUFFER_FULL = 11028; // 10 -static const uint64_t SH_FLD_LINK0_REPLAY_THRESHOLD = 11029; // 10 -static const uint64_t SH_FLD_LINK0_RETRAIN_THRESHOLD = 11030; // 4 -static const uint64_t SH_FLD_LINK0_ROUND_TRIP = 11031; // 5 -static const uint64_t SH_FLD_LINK0_ROUND_TRIP_LEN = 11032; // 5 -static const uint64_t SH_FLD_LINK0_ROUND_TRIP_VALID = 11033; // 5 -static const uint64_t SH_FLD_LINK0_RUN_LANE_DISABLE = 11034; // 2 -static const uint64_t SH_FLD_LINK0_RUN_LANE_OVERRIDE = 11035; // 2 -static const uint64_t SH_FLD_LINK0_RX_LANE_SWAP = 11036; // 2 -static const uint64_t SH_FLD_LINK0_SL_ECC_CORRECTABLE = 11037; // 10 -static const uint64_t SH_FLD_LINK0_SL_ECC_THRESHOLD = 11038; // 10 -static const uint64_t SH_FLD_LINK0_SL_ECC_UE = 11039; // 10 -static const uint64_t SH_FLD_LINK0_SPARE = 11040; // 1 -static const uint64_t SH_FLD_LINK0_SPARE_DONE = 11041; // 10 -static const uint64_t SH_FLD_LINK0_SPARE_LEN = 11042; // 1 -static const uint64_t SH_FLD_LINK0_STARTUP = 11043; // 5 -static const uint64_t SH_FLD_LINK0_SW_RETRAIN = 11044; // 4 -static const uint64_t SH_FLD_LINK0_TCOMPLETE_BAD = 11045; // 10 -static const uint64_t SH_FLD_LINK0_TOD_LATENCY = 11046; // 5 -static const uint64_t SH_FLD_LINK0_TOD_LATENCY_LEN = 11047; // 5 -static const uint64_t SH_FLD_LINK0_TOO_MANY_CRC_ERRORS = 11048; // 10 -static const uint64_t SH_FLD_LINK0_TRAINED = 11049; // 10 -static const uint64_t SH_FLD_LINK0_TRAINING = 11050; // 2 -static const uint64_t SH_FLD_LINK0_TRAINING_FAILED = 11051; // 10 -static const uint64_t SH_FLD_LINK0_TRAINING_SET_RECEIVED = 11052; // 4 -static const uint64_t SH_FLD_LINK0_TX_LANE_SWAP = 11053; // 2 -static const uint64_t SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR = 11054; // 10 -static const uint64_t SH_FLD_LINK0_UNRECOVERABLE_ERROR = 11055; // 10 -static const uint64_t SH_FLD_LINK1_ACK_QUEUE_OVERFLOW = 11056; // 4 -static const uint64_t SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW = 11057; // 4 -static const uint64_t SH_FLD_LINK1_COMMAND = 11058; // 5 -static const uint64_t SH_FLD_LINK1_COMMAND_LEN = 11059; // 5 -static const uint64_t SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR = 11060; // 10 -static const uint64_t SH_FLD_LINK1_CRC_ERROR = 11061; // 10 -static const uint64_t SH_FLD_LINK1_CURRENT_STATE = 11062; // 5 -static const uint64_t SH_FLD_LINK1_CURRENT_STATE_LEN = 11063; // 5 -static const uint64_t SH_FLD_LINK1_DESKEW_ERROR = 11064; // 4 -static const uint64_t SH_FLD_LINK1_DESKEW_OVERFLOW = 11065; // 4 -static const uint64_t SH_FLD_LINK1_DOB_LIMIT = 11066; // 1 -static const uint64_t SH_FLD_LINK1_DOB_LIMIT_LEN = 11067; // 1 -static const uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT = 11068; // 2 -static const uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT_LEN = 11069; // 2 -static const uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT = 11070; // 2 -static const uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT_LEN = 11071; // 2 -static const uint64_t SH_FLD_LINK1_ELEVEN_LANE_SHIFT = 11072; // 2 -static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND = 11073; // 5 -static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LANES = 11074; // 5 -static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN = 11075; // 5 -static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LEN = 11076; // 5 -static const uint64_t SH_FLD_LINK1_HOLD_PATT_A = 11077; // 2 -static const uint64_t SH_FLD_LINK1_HOLD_PATT_B = 11078; // 2 -static const uint64_t SH_FLD_LINK1_IGNORE_FENCE = 11079; // 2 -static const uint64_t SH_FLD_LINK1_IGNORE_PHY = 11080; // 2 -static const uint64_t SH_FLD_LINK1_INTERNAL_ERROR = 11081; // 10 -static const uint64_t SH_FLD_LINK1_INVALID_BLOCK = 11082; // 4 -static const uint64_t SH_FLD_LINK1_LOSS_BLOCK_ALIGN = 11083; // 4 -static const uint64_t SH_FLD_LINK1_MAX_PKT_TIMER = 11084; // 5 -static const uint64_t SH_FLD_LINK1_MAX_PKT_TIMER_LEN = 11085; // 5 -static const uint64_t SH_FLD_LINK1_NAK_RECEIVED = 11086; // 10 -static const uint64_t SH_FLD_LINK1_NPU_ERROR = 11087; // 4 -static const uint64_t SH_FLD_LINK1_NUM_REPLAY = 11088; // 4 -static const uint64_t SH_FLD_LINK1_OLL_ENABLED = 11089; // 2 -static const uint64_t SH_FLD_LINK1_OPTICS_IRQ = 11090; // 2 -static const uint64_t SH_FLD_LINK1_OPTICS_RST_B = 11091; // 2 -static const uint64_t SH_FLD_LINK1_OP_IRQ = 11092; // 4 -static const uint64_t SH_FLD_LINK1_PHY_TRAINING = 11093; // 2 -static const uint64_t SH_FLD_LINK1_PRBS_SELECT_ERROR = 11094; // 4 -static const uint64_t SH_FLD_LINK1_PRIOR_STATE = 11095; // 5 -static const uint64_t SH_FLD_LINK1_PRIOR_STATE_LEN = 11096; // 5 -static const uint64_t SH_FLD_LINK1_REPLAY_BUFFER_FULL = 11097; // 10 -static const uint64_t SH_FLD_LINK1_REPLAY_THRESHOLD = 11098; // 10 -static const uint64_t SH_FLD_LINK1_RETRAIN_THRESHOLD = 11099; // 4 -static const uint64_t SH_FLD_LINK1_ROUND_TRIP = 11100; // 5 -static const uint64_t SH_FLD_LINK1_ROUND_TRIP_LEN = 11101; // 5 -static const uint64_t SH_FLD_LINK1_ROUND_TRIP_VALID = 11102; // 5 -static const uint64_t SH_FLD_LINK1_RUN_LANE_DISABLE = 11103; // 2 -static const uint64_t SH_FLD_LINK1_RUN_LANE_OVERRIDE = 11104; // 2 -static const uint64_t SH_FLD_LINK1_RX_LANE_SWAP = 11105; // 2 -static const uint64_t SH_FLD_LINK1_SL_ECC_CORRECTABLE = 11106; // 10 -static const uint64_t SH_FLD_LINK1_SL_ECC_THRESHOLD = 11107; // 10 -static const uint64_t SH_FLD_LINK1_SL_ECC_UE = 11108; // 10 -static const uint64_t SH_FLD_LINK1_SPARE = 11109; // 1 -static const uint64_t SH_FLD_LINK1_SPARE_DONE = 11110; // 10 -static const uint64_t SH_FLD_LINK1_SPARE_LEN = 11111; // 1 -static const uint64_t SH_FLD_LINK1_STARTUP = 11112; // 5 -static const uint64_t SH_FLD_LINK1_SW_RETRAIN = 11113; // 4 -static const uint64_t SH_FLD_LINK1_TCOMPLETE_BAD = 11114; // 10 -static const uint64_t SH_FLD_LINK1_TOD_LATENCY = 11115; // 5 -static const uint64_t SH_FLD_LINK1_TOD_LATENCY_LEN = 11116; // 5 -static const uint64_t SH_FLD_LINK1_TOO_MANY_CRC_ERRORS = 11117; // 10 -static const uint64_t SH_FLD_LINK1_TRAINED = 11118; // 10 -static const uint64_t SH_FLD_LINK1_TRAINING = 11119; // 2 -static const uint64_t SH_FLD_LINK1_TRAINING_FAILED = 11120; // 10 -static const uint64_t SH_FLD_LINK1_TRAINING_SET_RECEIVED = 11121; // 4 -static const uint64_t SH_FLD_LINK1_TX_LANE_SWAP = 11122; // 2 -static const uint64_t SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR = 11123; // 10 -static const uint64_t SH_FLD_LINK1_UNRECOVERABLE_ERROR = 11124; // 10 -static const uint64_t SH_FLD_LINK23_DIB_VC_LIMIT = 11125; // 2 -static const uint64_t SH_FLD_LINK23_DIB_VC_LIMIT_LEN = 11126; // 2 -static const uint64_t SH_FLD_LINK2_DOB_LIMIT = 11127; // 2 -static const uint64_t SH_FLD_LINK2_DOB_LIMIT_LEN = 11128; // 2 -static const uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT = 11129; // 2 -static const uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT_LEN = 11130; // 2 -static const uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT = 11131; // 2 -static const uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT_LEN = 11132; // 2 -static const uint64_t SH_FLD_LINK3_DOB_LIMIT = 11133; // 2 -static const uint64_t SH_FLD_LINK3_DOB_LIMIT_LEN = 11134; // 2 -static const uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT = 11135; // 2 -static const uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT_LEN = 11136; // 2 -static const uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT = 11137; // 2 -static const uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT_LEN = 11138; // 2 -static const uint64_t SH_FLD_LINK45_DIB_VC_LIMIT = 11139; // 2 -static const uint64_t SH_FLD_LINK45_DIB_VC_LIMIT_LEN = 11140; // 2 -static const uint64_t SH_FLD_LINK4_DOB_LIMIT = 11141; // 2 -static const uint64_t SH_FLD_LINK4_DOB_LIMIT_LEN = 11142; // 2 -static const uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT = 11143; // 2 -static const uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT_LEN = 11144; // 2 -static const uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT = 11145; // 2 -static const uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT_LEN = 11146; // 2 -static const uint64_t SH_FLD_LINK5_DOB_LIMIT = 11147; // 2 -static const uint64_t SH_FLD_LINK5_DOB_LIMIT_LEN = 11148; // 2 -static const uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT = 11149; // 2 -static const uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT_LEN = 11150; // 2 -static const uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT = 11151; // 2 -static const uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT_LEN = 11152; // 2 -static const uint64_t SH_FLD_LINK67_CAPP_MODE = 11153; // 1 -static const uint64_t SH_FLD_LINK67_DIB_VC_LIMIT = 11154; // 1 -static const uint64_t SH_FLD_LINK67_DIB_VC_LIMIT_LEN = 11155; // 1 -static const uint64_t SH_FLD_LINK67_HRB_INIT_STATE = 11156; // 1 -static const uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT = 11157; // 1 -static const uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT_LEN = 11158; // 1 -static const uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT = 11159; // 1 -static const uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT_LEN = 11160; // 1 -static const uint64_t SH_FLD_LINK6_SPARE = 11161; // 1 -static const uint64_t SH_FLD_LINK6_SPARE_LEN = 11162; // 1 -static const uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT = 11163; // 1 -static const uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT_LEN = 11164; // 1 -static const uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT = 11165; // 1 -static const uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT_LEN = 11166; // 1 -static const uint64_t SH_FLD_LINK7_SPARE = 11167; // 1 -static const uint64_t SH_FLD_LINK7_SPARE_LEN = 11168; // 1 -static const uint64_t SH_FLD_LINKS01_TOD_ENABLE = 11169; // 1 -static const uint64_t SH_FLD_LINKS23_TOD_ENABLE = 11170; // 1 -static const uint64_t SH_FLD_LINKS45_TOD_ENABLE = 11171; // 1 -static const uint64_t SH_FLD_LINKS67_TOD_ENABLE = 11172; // 1 -static const uint64_t SH_FLD_LINKX_NPU_ERROR = 11173; // 4 -static const uint64_t SH_FLD_LINK_AVP_MODE = 11174; // 2 -static const uint64_t SH_FLD_LINK_CAP_CRC = 11175; // 10 -static const uint64_t SH_FLD_LINK_CAP_CRC_LANE = 11176; // 10 -static const uint64_t SH_FLD_LINK_CAP_CRC_LANE_LEN = 11177; // 10 -static const uint64_t SH_FLD_LINK_CAP_CRC_LEN = 11178; // 10 -static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED1 = 11179; // 6 -static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED1_LEN = 11180; // 6 -static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED2 = 11181; // 6 -static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED2_LEN = 11182; // 6 -static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED3 = 11183; // 6 -static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED3_LEN = 11184; // 6 -static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN0 = 11185; // 10 -static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN0_LEN = 11186; // 10 -static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN1 = 11187; // 10 -static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN1_LEN = 11188; // 10 -static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN2 = 11189; // 4 -static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN2_LEN = 11190; // 4 -static const uint64_t SH_FLD_LINK_CAP_VALID = 11191; // 6 -static const uint64_t SH_FLD_LINK_FAIL_DURATION = 11192; // 2 -static const uint64_t SH_FLD_LINK_FAIL_DURATION_LEN = 11193; // 2 -static const uint64_t SH_FLD_LINK_FAIL_MAX = 11194; // 2 -static const uint64_t SH_FLD_LINK_FAIL_MAX_LEN = 11195; // 2 -static const uint64_t SH_FLD_LINK_PAIR = 11196; // 5 -static const uint64_t SH_FLD_LINUX_TRIG_MODE = 11197; // 1 -static const uint64_t SH_FLD_LISTEN_TO_PULSE_DIS = 11198; // 43 -static const uint64_t SH_FLD_LNK_RSP_PKT_DISCARDED_ERRHOLD = 11199; // 2 -static const uint64_t SH_FLD_LO = 11200; // 1 -static const uint64_t SH_FLD_LOAD_CI_BUFF = 11201; // 2 -static const uint64_t SH_FLD_LOAD_RSVD_VALUES = 11202; // 8 -static const uint64_t SH_FLD_LOCALITY_4_ACCESS = 11203; // 1 -static const uint64_t SH_FLD_LOCAL_HANG_COMP = 11204; // 4 -static const uint64_t SH_FLD_LOCAL_HANG_COMP_LEN = 11205; // 4 -static const uint64_t SH_FLD_LOCAL_HIGH_PRIORITY = 11206; // 4 -static const uint64_t SH_FLD_LOCAL_HIGH_PRIORITY_LEN = 11207; // 4 -static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE = 11208; // 5 -static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN = 11209; // 5 -static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID = 11210; // 5 -static const uint64_t SH_FLD_LOCAL_LATENCY_LONGER_LINK = 11211; // 5 -static const uint64_t SH_FLD_LOCAL_LOW_PRIORITY = 11212; // 4 -static const uint64_t SH_FLD_LOCAL_LOW_PRIORITY_LEN = 11213; // 4 -static const uint64_t SH_FLD_LOCAL_NODE_EPSILON = 11214; // 8 -static const uint64_t SH_FLD_LOCAL_NODE_EPSILON_LEN = 11215; // 8 -static const uint64_t SH_FLD_LOCAL_QUIESCE_ACHIEVED = 11216; // 1 -static const uint64_t SH_FLD_LOCK = 11217; // 16 -static const uint64_t SH_FLD_LOCKED = 11218; // 4 -static const uint64_t SH_FLD_LOCKED_FSM_RESET_ONGOING = 11219; // 1 -static const uint64_t SH_FLD_LOCKED_FSM_STATE = 11220; // 1 -static const uint64_t SH_FLD_LOCKED_FSM_STATE_LEN = 11221; // 1 -static const uint64_t SH_FLD_LOCKED_LEN = 11222; // 4 -static const uint64_t SH_FLD_LOCKED_PIBM_ADDR = 11223; // 1 -static const uint64_t SH_FLD_LOCKED_PIBM_ADDR_LEN = 11224; // 1 -static const uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS = 11225; // 1 -static const uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN = 11226; // 1 -static const uint64_t SH_FLD_LOCK_PCB_ON_ERR = 11227; // 12 -static const uint64_t SH_FLD_LOCK_SEL = 11228; // 6 -static const uint64_t SH_FLD_LOFF_AMP_EN = 11229; // 6 -static const uint64_t SH_FLD_LOG = 11230; // 1 -static const uint64_t SH_FLD_LOG_FULL = 11231; // 8 -static const uint64_t SH_FLD_LOG_LEN = 11232; // 1 -static const uint64_t SH_FLD_LOG_POINTER = 11233; // 8 -static const uint64_t SH_FLD_LOG_POINTER_LEN = 11234; // 8 -static const uint64_t SH_FLD_LOOP_BREAK_MODE = 11235; // 64 -static const uint64_t SH_FLD_LOOP_BREAK_MODE_LEN = 11236; // 64 -static const uint64_t SH_FLD_LOOP_COUNT = 11237; // 43 -static const uint64_t SH_FLD_LOOP_COUNT_LEN = 11238; // 43 -static const uint64_t SH_FLD_LOW = 11239; // 1 -static const uint64_t SH_FLD_LOW_IDLE_COUNT = 11240; // 8 -static const uint64_t SH_FLD_LOW_IDLE_COUNT_LEN = 11241; // 8 -static const uint64_t SH_FLD_LOW_IDLE_THRESHOLD = 11242; // 8 -static const uint64_t SH_FLD_LOW_IDLE_THRESHOLD_LEN = 11243; // 8 -static const uint64_t SH_FLD_LOW_LATENCY = 11244; // 8 -static const uint64_t SH_FLD_LOW_LEN = 11245; // 1 -static const uint64_t SH_FLD_LOW_ORDER_STEP_VALUE = 11246; // 1 -static const uint64_t SH_FLD_LOW_ORDER_STEP_VALUE_LEN = 11247; // 1 -static const uint64_t SH_FLD_LOW_PROBE_TRACE_GATE = 11248; // 8 -static const uint64_t SH_FLD_LO_ENABLE = 11249; // 2 -static const uint64_t SH_FLD_LO_FIXED_WINDOW_MODE = 11250; // 2 -static const uint64_t SH_FLD_LO_PRESCALE_MODE = 11251; // 2 -static const uint64_t SH_FLD_LO_SELECT = 11252; // 2 -static const uint64_t SH_FLD_LO_SELECT_LEN = 11253; // 2 -static const uint64_t SH_FLD_LP = 11254; // 8 -static const uint64_t SH_FLD_LPARID = 11255; // 24 -static const uint64_t SH_FLD_LPARID_LEN = 11256; // 24 -static const uint64_t SH_FLD_LPARSHORT = 11257; // 272 -static const uint64_t SH_FLD_LPARSHORT_LEN = 11258; // 272 -static const uint64_t SH_FLD_LPCR_BOT = 11259; // 16 -static const uint64_t SH_FLD_LPCR_ISL = 11260; // 16 -static const uint64_t SH_FLD_LPCR_PS = 11261; // 16 -static const uint64_t SH_FLD_LPCR_PS_LEN = 11262; // 16 -static const uint64_t SH_FLD_LPCR_SC = 11263; // 16 -static const uint64_t SH_FLD_LPCR_TC = 11264; // 16 -static const uint64_t SH_FLD_LPCTH = 11265; // 3 -static const uint64_t SH_FLD_LPCTH_LEN = 11266; // 3 -static const uint64_t SH_FLD_LPC_MODE = 11267; // 2 -static const uint64_t SH_FLD_LPC_MODE_LEN = 11268; // 2 -static const uint64_t SH_FLD_LPID = 11269; // 9 -static const uint64_t SH_FLD_LPID_LEN = 11270; // 9 -static const uint64_t SH_FLD_LPID_MASK = 11271; // 1 -static const uint64_t SH_FLD_LPID_MASK_LEN = 11272; // 1 -static const uint64_t SH_FLD_LP_CNT_THRESH = 11273; // 6 -static const uint64_t SH_FLD_LP_CNT_THRESH_LEN = 11274; // 6 -static const uint64_t SH_FLD_LP_LEN = 11275; // 8 -static const uint64_t SH_FLD_LP_MAX_CRED_THRESH = 11276; // 6 -static const uint64_t SH_FLD_LP_MAX_CRED_THRESH_LEN = 11277; // 6 -static const uint64_t SH_FLD_LP_MIN_CRED_THRESH = 11278; // 6 -static const uint64_t SH_FLD_LP_MIN_CRED_THRESH_LEN = 11279; // 6 -static const uint64_t SH_FLD_LP_MODE_ENABLE = 11280; // 6 -static const uint64_t SH_FLD_LP_ONLY_MODE = 11281; // 6 -static const uint64_t SH_FLD_LP_TIMER_TICK_CONFIG = 11282; // 6 -static const uint64_t SH_FLD_LP_TIMER_TICK_CONFIG_LEN = 11283; // 6 -static const uint64_t SH_FLD_LRDIMM = 11284; // 2 -static const uint64_t SH_FLD_LRDIMM_CONTEXT = 11285; // 8 -static const uint64_t SH_FLD_LRDIMM_LEN = 11286; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD1 = 11287; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD10 = 11288; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD10_LEN = 11289; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD11 = 11290; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD11_LEN = 11291; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD12 = 11292; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD12_LEN = 11293; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD13 = 11294; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD13_LEN = 11295; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD14 = 11296; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD14_LEN = 11297; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD15 = 11298; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD15_LEN = 11299; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD1_LEN = 11300; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD2 = 11301; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD2_LEN = 11302; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD3 = 11303; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD3_LEN = 11304; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD4 = 11305; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD4_LEN = 11306; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD5 = 11307; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD5_LEN = 11308; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD6 = 11309; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD6_LEN = 11310; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD7 = 11311; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD7_LEN = 11312; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD8 = 11313; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD8_LEN = 11314; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD9 = 11315; // 2 -static const uint64_t SH_FLD_LRDIMM_WORD9_LEN = 11316; // 2 -static const uint64_t SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED = 11317; // 12 -static const uint64_t SH_FLD_LRU_PERR_CHK_DIS = 11318; // 2 -static const uint64_t SH_FLD_LRU_READ_ERROR_DETECTED = 11319; // 12 -static const uint64_t SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA = 11320; // 1 -static const uint64_t SH_FLD_LTE_EN = 11321; // 4 -static const uint64_t SH_FLD_LUC = 11322; // 1 -static const uint64_t SH_FLD_LUC_LEN = 11323; // 1 -static const uint64_t SH_FLD_LUT = 11324; // 1 -static const uint64_t SH_FLD_LUT_LEN = 11325; // 1 -static const uint64_t SH_FLD_LVDIR_EN = 11326; // 12 -static const uint64_t SH_FLD_LVDIR_PERR = 11327; // 12 -static const uint64_t SH_FLD_LVLTRANS_FENCE = 11328; // 43 -static const uint64_t SH_FLD_M = 11329; // 1 -static const uint64_t SH_FLD_M0_BIT_MAP = 11330; // 8 -static const uint64_t SH_FLD_M0_BIT_MAP_LEN = 11331; // 8 -static const uint64_t SH_FLD_M0_PRIORITY = 11332; // 1 -static const uint64_t SH_FLD_M0_PRIORITY_LEN = 11333; // 1 -static const uint64_t SH_FLD_M0_PRIORITY_SEL = 11334; // 1 -static const uint64_t SH_FLD_M1HC0A = 11335; // 1 -static const uint64_t SH_FLD_M1HC0A_LEN = 11336; // 1 -static const uint64_t SH_FLD_M1HC0B = 11337; // 1 -static const uint64_t SH_FLD_M1HC0B_LEN = 11338; // 1 -static const uint64_t SH_FLD_M1HC1A = 11339; // 1 -static const uint64_t SH_FLD_M1HC1A_LEN = 11340; // 1 -static const uint64_t SH_FLD_M1HC1B = 11341; // 1 -static const uint64_t SH_FLD_M1HC1B_LEN = 11342; // 1 -static const uint64_t SH_FLD_M1HC2A = 11343; // 1 -static const uint64_t SH_FLD_M1HC2A_LEN = 11344; // 1 -static const uint64_t SH_FLD_M1HC2B = 11345; // 1 -static const uint64_t SH_FLD_M1HC2B_LEN = 11346; // 1 -static const uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_ERROR = 11347; // 1 -static const uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_PENDING = 11348; // 1 -static const uint64_t SH_FLD_M1SASIM1_ENABLE_XUP = 11349; // 1 -static const uint64_t SH_FLD_M1_BIT_MAP = 11350; // 8 -static const uint64_t SH_FLD_M1_BIT_MAP_LEN = 11351; // 8 -static const uint64_t SH_FLD_M1_PRIORITY = 11352; // 1 -static const uint64_t SH_FLD_M1_PRIORITY_LEN = 11353; // 1 -static const uint64_t SH_FLD_M1_PRIORITY_SEL = 11354; // 1 -static const uint64_t SH_FLD_M2HC0A = 11355; // 1 -static const uint64_t SH_FLD_M2HC0A_LEN = 11356; // 1 -static const uint64_t SH_FLD_M2HC0B = 11357; // 1 -static const uint64_t SH_FLD_M2HC0B_LEN = 11358; // 1 -static const uint64_t SH_FLD_M2HC1A = 11359; // 1 -static const uint64_t SH_FLD_M2HC1A_LEN = 11360; // 1 -static const uint64_t SH_FLD_M2HC1B = 11361; // 1 -static const uint64_t SH_FLD_M2HC1B_LEN = 11362; // 1 -static const uint64_t SH_FLD_M2HC2A = 11363; // 1 -static const uint64_t SH_FLD_M2HC2A_LEN = 11364; // 1 -static const uint64_t SH_FLD_M2HC2B = 11365; // 1 -static const uint64_t SH_FLD_M2HC2B_LEN = 11366; // 1 -static const uint64_t SH_FLD_M2_PRIORITY = 11367; // 1 -static const uint64_t SH_FLD_M2_PRIORITY_LEN = 11368; // 1 -static const uint64_t SH_FLD_M2_PRIORITY_SEL = 11369; // 1 -static const uint64_t SH_FLD_M3_PRIORITY = 11370; // 1 -static const uint64_t SH_FLD_M3_PRIORITY_LEN = 11371; // 1 -static const uint64_t SH_FLD_M3_PRIORITY_SEL = 11372; // 1 -static const uint64_t SH_FLD_M4_PRIORITY = 11373; // 1 -static const uint64_t SH_FLD_M4_PRIORITY_LEN = 11374; // 1 -static const uint64_t SH_FLD_M5_PRIORITY = 11375; // 1 -static const uint64_t SH_FLD_M5_PRIORITY_LEN = 11376; // 1 -static const uint64_t SH_FLD_M5_PRIORITY_SEL = 11377; // 1 -static const uint64_t SH_FLD_M6_PRIORITY = 11378; // 1 -static const uint64_t SH_FLD_M6_PRIORITY_LEN = 11379; // 1 -static const uint64_t SH_FLD_M7_PRIORITY = 11380; // 1 -static const uint64_t SH_FLD_M7_PRIORITY_LEN = 11381; // 1 -static const uint64_t SH_FLD_M7_PRIORITY_SEL = 11382; // 1 -static const uint64_t SH_FLD_MAGIC_COOKIE = 11383; // 1 -static const uint64_t SH_FLD_MAGIC_COOKIE_LEN = 11384; // 1 -static const uint64_t SH_FLD_MAINLINE_AUE = 11385; // 8 -static const uint64_t SH_FLD_MAINLINE_IAUE = 11386; // 8 -static const uint64_t SH_FLD_MAINLINE_IMPE = 11387; // 8 -static const uint64_t SH_FLD_MAINLINE_IRCD = 11388; // 8 -static const uint64_t SH_FLD_MAINLINE_IUE = 11389; // 8 -static const uint64_t SH_FLD_MAINLINE_MCE = 11390; // 8 -static const uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7 = 11391; // 8 -static const uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN = 11392; // 8 -static const uint64_t SH_FLD_MAINLINE_NCE = 11393; // 8 -static const uint64_t SH_FLD_MAINLINE_RCD = 11394; // 8 -static const uint64_t SH_FLD_MAINLINE_SCE = 11395; // 8 -static const uint64_t SH_FLD_MAINLINE_SUE = 11396; // 8 -static const uint64_t SH_FLD_MAINLINE_TCE = 11397; // 8 -static const uint64_t SH_FLD_MAINLINE_UE = 11398; // 8 -static const uint64_t SH_FLD_MAINTENANCE_AUE = 11399; // 8 -static const uint64_t SH_FLD_MAINTENANCE_IAUE = 11400; // 8 -static const uint64_t SH_FLD_MAINTENANCE_IMPE = 11401; // 8 -static const uint64_t SH_FLD_MAINTENANCE_IRCD = 11402; // 8 -static const uint64_t SH_FLD_MAINTENANCE_IUE = 11403; // 8 -static const uint64_t SH_FLD_MAINTENANCE_MCE = 11404; // 8 -static const uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 = 11405; // 8 -static const uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 11406; // 8 -static const uint64_t SH_FLD_MAINTENANCE_NCE = 11407; // 8 -static const uint64_t SH_FLD_MAINTENANCE_RCD = 11408; // 8 -static const uint64_t SH_FLD_MAINTENANCE_SCE = 11409; // 8 -static const uint64_t SH_FLD_MAINTENANCE_SUE = 11410; // 8 -static const uint64_t SH_FLD_MAINTENANCE_TCE = 11411; // 8 -static const uint64_t SH_FLD_MAINTENANCE_UE = 11412; // 8 -static const uint64_t SH_FLD_MAINT_CCS_PE_HOLD_OUT = 11413; // 2 -static const uint64_t SH_FLD_MAIN_SLICE_EN_ENC = 11414; // 1 -static const uint64_t SH_FLD_MAIN_SLICE_EN_ENC_LEN = 11415; // 1 -static const uint64_t SH_FLD_MAJOR = 11416; // 1 -static const uint64_t SH_FLD_MAJOR_LEN = 11417; // 1 -static const uint64_t SH_FLD_MALFUNCTION_ALERT = 11418; // 96 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP0 = 11419; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP0_LEN = 11420; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP1 = 11421; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP10 = 11422; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP10_LEN = 11423; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP11 = 11424; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP11_LEN = 11425; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP12 = 11426; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP12_LEN = 11427; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP13 = 11428; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP13_LEN = 11429; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP14 = 11430; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP14_LEN = 11431; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP15 = 11432; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP15_LEN = 11433; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP1_LEN = 11434; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP2 = 11435; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP2_LEN = 11436; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP3 = 11437; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP3_LEN = 11438; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP4 = 11439; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP4_LEN = 11440; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP5 = 11441; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP5_LEN = 11442; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP6 = 11443; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP6_LEN = 11444; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP7 = 11445; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP7_LEN = 11446; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP8 = 11447; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP8_LEN = 11448; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP9 = 11449; // 1 -static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP9_LEN = 11450; // 1 -static const uint64_t SH_FLD_MANUAL_CLR_PB_STOP = 11451; // 1 -static const uint64_t SH_FLD_MANUAL_PB_SWITCH_ABCD = 11452; // 1 -static const uint64_t SH_FLD_MANUAL_RECAL_LANE = 11453; // 6 -static const uint64_t SH_FLD_MANUAL_RECAL_LANE_LEN = 11454; // 6 -static const uint64_t SH_FLD_MANUAL_RECAL_REQUEST = 11455; // 6 -static const uint64_t SH_FLD_MANUAL_SET_PB_STOP = 11456; // 1 -static const uint64_t SH_FLD_MAP_ERR_INJ_PEND = 11457; // 1 -static const uint64_t SH_FLD_MAP_REG_CERR0 = 11458; // 1 -static const uint64_t SH_FLD_MAP_REG_CERR1 = 11459; // 1 -static const uint64_t SH_FLD_MAP_REG_ERR0 = 11460; // 1 -static const uint64_t SH_FLD_MAP_REG_ERR1 = 11461; // 1 -static const uint64_t SH_FLD_MAP_REG_ERR2 = 11462; // 1 -static const uint64_t SH_FLD_MAP_REG_ERR3 = 11463; // 1 -static const uint64_t SH_FLD_MAP_REG_ERR4 = 11464; // 1 -static const uint64_t SH_FLD_MARGINPD_SEL = 11465; // 6 -static const uint64_t SH_FLD_MARGINPD_SEL_LEN = 11466; // 6 -static const uint64_t SH_FLD_MARGINPU_SEL = 11467; // 6 -static const uint64_t SH_FLD_MARGINPU_SEL_LEN = 11468; // 6 -static const uint64_t SH_FLD_MARK = 11469; // 64 -static const uint64_t SH_FLD_MARK_LEN = 11470; // 64 -static const uint64_t SH_FLD_MASK = 11471; // 69 -static const uint64_t SH_FLD_MASKA = 11472; // 90 -static const uint64_t SH_FLD_MASKA_LEN = 11473; // 90 -static const uint64_t SH_FLD_MASKB = 11474; // 90 -static const uint64_t SH_FLD_MASKB_LEN = 11475; // 90 -static const uint64_t SH_FLD_MASKC = 11476; // 90 -static const uint64_t SH_FLD_MASKC_LEN = 11477; // 90 -static const uint64_t SH_FLD_MASKD = 11478; // 90 -static const uint64_t SH_FLD_MASKD_LEN = 11479; // 90 -static const uint64_t SH_FLD_MASK_AGV_DISABLE_MODE = 11480; // 2 -static const uint64_t SH_FLD_MASK_B = 11481; // 129 -static const uint64_t SH_FLD_MASK_LEN = 11482; // 61 -static const uint64_t SH_FLD_MASK_PURGE_INTERFACE = 11483; // 12 -static const uint64_t SH_FLD_MASK_TOGGLE_ENABLE = 11484; // 1 -static const uint64_t SH_FLD_MASTER = 11485; // 8 -static const uint64_t SH_FLD_MASTERID = 11486; // 6 -static const uint64_t SH_FLD_MASTERID_LEN = 11487; // 6 -static const uint64_t SH_FLD_MASTER_ARRAY_CE = 11488; // 4 -static const uint64_t SH_FLD_MASTER_ARRAY_UE = 11489; // 4 -static const uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV = 11490; // 12 -static const uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 11491; // 12 -static const uint64_t SH_FLD_MASTER_ERROR_CODE = 11492; // 1 -static const uint64_t SH_FLD_MASTER_ERROR_CODE_LEN = 11493; // 1 -static const uint64_t SH_FLD_MASTER_IDLE = 11494; // 1 -static const uint64_t SH_FLD_MASTER_MODE = 11495; // 47 -static const uint64_t SH_FLD_MASTER_RECOVERABLE_ERROR = 11496; // 4 -static const uint64_t SH_FLD_MASTER_RESPONSE_BIT = 11497; // 1 -static const uint64_t SH_FLD_MASTER_SYS_XSTOP_ERROR = 11498; // 4 -static const uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV = 11499; // 12 -static const uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 11500; // 12 -static const uint64_t SH_FLD_MATCH = 11501; // 12 -static const uint64_t SH_FLD_MATCHA_MUXSEL = 11502; // 90 -static const uint64_t SH_FLD_MATCHA_MUXSEL_LEN = 11503; // 90 -static const uint64_t SH_FLD_MATCHB_MUXSEL = 11504; // 90 -static const uint64_t SH_FLD_MATCHB_MUXSEL_LEN = 11505; // 90 -static const uint64_t SH_FLD_MATCHC_MUXSEL = 11506; // 90 -static const uint64_t SH_FLD_MATCHC_MUXSEL_LEN = 11507; // 90 -static const uint64_t SH_FLD_MATCHD_MUXSEL = 11508; // 90 -static const uint64_t SH_FLD_MATCHD_MUXSEL_LEN = 11509; // 90 -static const uint64_t SH_FLD_MATCH_LEN = 11510; // 12 -static const uint64_t SH_FLD_MATCH_NOT_MODE = 11511; // 90 -static const uint64_t SH_FLD_MATCH_NOT_MODE_LEN = 11512; // 90 -static const uint64_t SH_FLD_MAXCYCLECNT = 11513; // 3 -static const uint64_t SH_FLD_MAXCYCLECNT_LEN = 11514; // 3 -static const uint64_t SH_FLD_MAX_BAD_LANES = 11515; // 4 -static const uint64_t SH_FLD_MAX_BAD_LANES_LEN = 11516; // 4 -static const uint64_t SH_FLD_MAX_BER_CHECK_COUNT = 11517; // 4 -static const uint64_t SH_FLD_MAX_BER_CHECK_COUNT_LEN = 11518; // 4 -static const uint64_t SH_FLD_MAX_CRD_TO_CQ = 11519; // 6 -static const uint64_t SH_FLD_MAX_CRD_TO_CQ_LEN = 11520; // 6 -static const uint64_t SH_FLD_MAX_CRD_TO_PC = 11521; // 6 -static const uint64_t SH_FLD_MAX_CRD_TO_PC_LEN = 11522; // 6 -static const uint64_t SH_FLD_MAX_CYCLE_SAMPLE = 11523; // 12 -static const uint64_t SH_FLD_MAX_CYCLE_SAMPLE_LEN = 11524; // 12 -static const uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED = 11525; // 3 -static const uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN = 11526; // 3 -static const uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 11527; // 2 -static const uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 11528; // 2 -static const uint64_t SH_FLD_MAX_OUTSTANDING = 11529; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD = 11530; // 2 -static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN = 11531; // 2 -static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE = 11532; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN = 11533; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EOI = 11534; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EOI_LEN = 11535; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH = 11536; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN = 11537; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE = 11538; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN = 11539; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EQP = 11540; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_EQP_LEN = 11541; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH = 11542; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN = 11543; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE = 11544; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN = 11545; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH = 11546; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN = 11547; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_LEN = 11548; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP = 11549; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 11550; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI = 11551; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN = 11552; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT = 11553; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN = 11554; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC = 11555; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN = 11556; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH = 11557; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN = 11558; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_WB = 11559; // 1 -static const uint64_t SH_FLD_MAX_OUTSTANDING_WB_LEN = 11560; // 1 -static const uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4 = 11561; // 1 -static const uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4_LEN = 11562; // 1 -static const uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4 = 11563; // 1 -static const uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4_LEN = 11564; // 1 -static const uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4 = 11565; // 1 -static const uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4_LEN = 11566; // 1 -static const uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N = 11567; // 96 -static const uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN = 11568; // 96 -static const uint64_t SH_FLD_MAX_PTAG_IN_USE = 11569; // 7 -static const uint64_t SH_FLD_MAX_PTAG_IN_USE_LEN = 11570; // 7 -static const uint64_t SH_FLD_MAX_TIMEOUT = 11571; // 10 -static const uint64_t SH_FLD_MAX_TIMEOUT_LEN = 11572; // 10 -static const uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO = 11573; // 4 -static const uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO_LEN = 11574; // 4 -static const uint64_t SH_FLD_MB00_SPATTN = 11575; // 4 -static const uint64_t SH_FLD_MB01_SPATTN = 11576; // 4 -static const uint64_t SH_FLD_MB10_SPATTN = 11577; // 4 -static const uint64_t SH_FLD_MB11_SPATTN = 11578; // 4 -static const uint64_t SH_FLD_MB20_SPATTN = 11579; // 4 -static const uint64_t SH_FLD_MB21_SPATTN = 11580; // 4 -static const uint64_t SH_FLD_MB30_SPATTN = 11581; // 4 -static const uint64_t SH_FLD_MB31_SPATTN = 11582; // 4 -static const uint64_t SH_FLD_MB40_SPATTN = 11583; // 4 -static const uint64_t SH_FLD_MB41_SPATTN = 11584; // 4 -static const uint64_t SH_FLD_MB50_SPATTN = 11585; // 4 -static const uint64_t SH_FLD_MB51_SPATTN = 11586; // 4 -static const uint64_t SH_FLD_MB60_SPATTN = 11587; // 2 -static const uint64_t SH_FLD_MB61_SPATTN = 11588; // 2 -static const uint64_t SH_FLD_MB70_SPATTN = 11589; // 2 -static const uint64_t SH_FLD_MB71_SPATTN = 11590; // 2 -static const uint64_t SH_FLD_MBACALFIRQ_PORT_FAIL = 11591; // 8 -static const uint64_t SH_FLD_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 11592; // 8 -static const uint64_t SH_FLD_MBASE = 11593; // 12 -static const uint64_t SH_FLD_MBASE_LEN = 11594; // 12 -static const uint64_t SH_FLD_MBA_NONRECOVERABLE_ERROR = 11595; // 16 -static const uint64_t SH_FLD_MBA_RECOVERABLE_ERROR = 11596; // 16 -static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 11597; // 8 -static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN = 11598; // 8 -static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 11599; // 8 -static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 11600; // 8 -static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 11601; // 8 -static const uint64_t SH_FLD_MBA_WRD_MODE_RESERVED_4 = 11602; // 8 -static const uint64_t SH_FLD_MBOX0 = 11603; // 1 -static const uint64_t SH_FLD_MBOX0_LEN = 11604; // 1 -static const uint64_t SH_FLD_MBOX1 = 11605; // 1 -static const uint64_t SH_FLD_MBOX1_LEN = 11606; // 1 -static const uint64_t SH_FLD_MBOX2 = 11607; // 1 -static const uint64_t SH_FLD_MBOX2_LEN = 11608; // 1 -static const uint64_t SH_FLD_MBOX3 = 11609; // 1 -static const uint64_t SH_FLD_MBOX3_LEN = 11610; // 1 -static const uint64_t SH_FLD_MBOX4 = 11611; // 1 -static const uint64_t SH_FLD_MBOX4_LEN = 11612; // 1 -static const uint64_t SH_FLD_MBOX5 = 11613; // 1 -static const uint64_t SH_FLD_MBOX5_LEN = 11614; // 1 -static const uint64_t SH_FLD_MBOX6 = 11615; // 1 -static const uint64_t SH_FLD_MBOX6_LEN = 11616; // 1 -static const uint64_t SH_FLD_MBOX7 = 11617; // 1 -static const uint64_t SH_FLD_MBOX7_LEN = 11618; // 1 -static const uint64_t SH_FLD_MBR_DIS = 11619; // 2 -static const uint64_t SH_FLD_MBR_DIS_LEN = 11620; // 2 -static const uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE = 11621; // 8 -static const uint64_t SH_FLD_MBSECCQ_DATA_INVERSION = 11622; // 8 -static const uint64_t SH_FLD_MBSECCQ_DATA_INVERSION_LEN = 11623; // 8 -static const uint64_t SH_FLD_MBSECCQ_DELAY_NONBYPASS = 11624; // 8 -static const uint64_t SH_FLD_MBSECCQ_DELAY_VALID_1X = 11625; // 8 -static const uint64_t SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE = 11626; // 8 -static const uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 11627; // 8 -static const uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 11628; // 8 -static const uint64_t SH_FLD_MBSECCQ_DISABLE_MPE_CONFIRM = 11629; // 8 -static const uint64_t SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 11630; // 8 -static const uint64_t SH_FLD_MBSECCQ_DISABLE_UE_RETRY = 11631; // 8 -static const uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY = 11632; // 8 -static const uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 11633; // 8 -static const uint64_t SH_FLD_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 11634; // 8 -static const uint64_t SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION = 11635; // 8 -static const uint64_t SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 11636; // 8 -static const uint64_t SH_FLD_MBSECCQ_ENABLE_TCE_CORRECTION = 11637; // 8 -static const uint64_t SH_FLD_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 11638; // 8 -static const uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE = 11639; // 8 -static const uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN = 11640; // 8 -static const uint64_t SH_FLD_MBSECCQ_HWMARK_EXIT1 = 11641; // 8 -static const uint64_t SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE = 11642; // 8 -static const uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 11643; // 8 -static const uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 11644; // 8 -static const uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY = 11645; // 8 -static const uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN = 11646; // 8 -static const uint64_t SH_FLD_MBSECCQ_RESERVED_33_39 = 11647; // 8 -static const uint64_t SH_FLD_MBSECCQ_RESERVED_33_39_LEN = 11648; // 8 -static const uint64_t SH_FLD_MBSECCQ_RESERVED_5 = 11649; // 8 -static const uint64_t SH_FLD_MBSECCQ_USE_ADDRESS_HASH = 11650; // 8 -static const uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY = 11651; // 8 -static const uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 11652; // 8 -static const uint64_t SH_FLD_MB_BAD_ADDR = 11653; // 2 -static const uint64_t SH_FLD_MB_BAD_WRITE = 11654; // 2 -static const uint64_t SH_FLD_MB_CORRUPT = 11655; // 2 -static const uint64_t SH_FLD_MB_LINK_DOWN = 11656; // 2 -static const uint64_t SH_FLD_MB_LINK_ID = 11657; // 2 -static const uint64_t SH_FLD_MB_LINK_ID_LEN = 11658; // 2 -static const uint64_t SH_FLD_MB_RESET = 11659; // 2 -static const uint64_t SH_FLD_MB_SENT = 11660; // 2 -static const uint64_t SH_FLD_MB_SPARE = 11661; // 2 -static const uint64_t SH_FLD_MB_SPARE_LEN = 11662; // 2 -static const uint64_t SH_FLD_MB_VALID = 11663; // 2 -static const uint64_t SH_FLD_MB_WR_NOT_RD = 11664; // 2 -static const uint64_t SH_FLD_MCA_DBG_SEL_IN = 11665; // 8 -static const uint64_t SH_FLD_MCA_DBG_SEL_WRT = 11666; // 8 -static const uint64_t SH_FLD_MCBAGEN_PE_HOLD_OUT = 11667; // 2 -static const uint64_t SH_FLD_MCBCM_PE = 11668; // 8 -static const uint64_t SH_FLD_MCBCNTL_PE_HOLD_OUT = 11669; // 2 -static const uint64_t SH_FLD_MCBCNTL_PORT_SEL = 11670; // 2 -static const uint64_t SH_FLD_MCBCNTL_PORT_SEL_LEN = 11671; // 2 -static const uint64_t SH_FLD_MCBDGEN_PE_HOLD_OUT = 11672; // 2 -static const uint64_t SH_FLD_MCBERR_SCOM_PE_HOLD_OUT = 11673; // 2 -static const uint64_t SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC = 11674; // 2 -static const uint64_t SH_FLD_MCBIST_CCS_SUBTEST_DONE = 11675; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 11676; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 11677; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 11678; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME = 11679; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN = 11680; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 11681; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE = 11682; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL = 11683; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 11684; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 11685; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 11686; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 11687; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE = 11688; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN = 11689; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DONE = 11690; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ECC_MODE = 11691; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE = 11692; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN = 11693; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 11694; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE = 11695; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL = 11696; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 11697; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 11698; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 11699; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 11700; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE = 11701; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN = 11702; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DONE = 11703; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ECC_MODE = 11704; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE = 11705; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN = 11706; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 11707; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE = 11708; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL = 11709; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 11710; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 11711; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 11712; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 11713; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE = 11714; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN = 11715; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DONE = 11716; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ECC_MODE = 11717; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE = 11718; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN = 11719; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 11720; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE = 11721; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL = 11722; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 11723; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 11724; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 11725; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 11726; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE = 11727; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN = 11728; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DONE = 11729; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ECC_MODE = 11730; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE = 11731; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN = 11732; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 11733; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE = 11734; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL = 11735; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 11736; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 11737; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 11738; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 11739; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE = 11740; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN = 11741; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DONE = 11742; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ECC_MODE = 11743; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE = 11744; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN = 11745; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 11746; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE = 11747; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL = 11748; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 11749; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 11750; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 11751; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 11752; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE = 11753; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN = 11754; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DONE = 11755; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ECC_MODE = 11756; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE = 11757; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN = 11758; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 11759; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE = 11760; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL = 11761; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 11762; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 11763; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 11764; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 11765; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE = 11766; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN = 11767; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DONE = 11768; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ECC_MODE = 11769; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE = 11770; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN = 11771; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 11772; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE = 11773; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL = 11774; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 11775; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 11776; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 11777; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 11778; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE = 11779; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN = 11780; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DONE = 11781; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ECC_MODE = 11782; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE = 11783; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN = 11784; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 11785; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE = 11786; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL = 11787; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 11788; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 11789; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 11790; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 11791; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE = 11792; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN = 11793; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DONE = 11794; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ECC_MODE = 11795; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE = 11796; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN = 11797; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 11798; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE = 11799; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL = 11800; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 11801; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 11802; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 11803; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 11804; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE = 11805; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN = 11806; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DONE = 11807; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ECC_MODE = 11808; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE = 11809; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN = 11810; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 11811; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE = 11812; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL = 11813; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 11814; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 11815; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 11816; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 11817; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE = 11818; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN = 11819; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DONE = 11820; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ECC_MODE = 11821; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE = 11822; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN = 11823; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 11824; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE = 11825; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL = 11826; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 11827; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 11828; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 11829; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 11830; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE = 11831; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN = 11832; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DONE = 11833; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ECC_MODE = 11834; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE = 11835; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN = 11836; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 11837; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE = 11838; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL = 11839; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 11840; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 11841; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 11842; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 11843; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE = 11844; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN = 11845; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DONE = 11846; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ECC_MODE = 11847; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE = 11848; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN = 11849; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 11850; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE = 11851; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL = 11852; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 11853; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 11854; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 11855; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 11856; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE = 11857; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN = 11858; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DONE = 11859; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ECC_MODE = 11860; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE = 11861; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN = 11862; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 11863; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE = 11864; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL = 11865; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 11866; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 11867; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 11868; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 11869; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE = 11870; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN = 11871; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DONE = 11872; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ECC_MODE = 11873; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE = 11874; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN = 11875; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 11876; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE = 11877; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL = 11878; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 11879; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 11880; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 11881; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 11882; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE = 11883; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN = 11884; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DONE = 11885; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ECC_MODE = 11886; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE = 11887; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN = 11888; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 11889; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE = 11890; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL = 11891; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 11892; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 11893; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 11894; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 11895; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE = 11896; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN = 11897; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DONE = 11898; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ECC_MODE = 11899; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE = 11900; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN = 11901; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 11902; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE = 11903; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL = 11904; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 11905; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 11906; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 11907; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 11908; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE = 11909; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN = 11910; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DONE = 11911; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ECC_MODE = 11912; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE = 11913; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN = 11914; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 11915; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE = 11916; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL = 11917; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 11918; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 11919; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 11920; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 11921; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE = 11922; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN = 11923; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DONE = 11924; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ECC_MODE = 11925; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE = 11926; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN = 11927; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 11928; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE = 11929; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL = 11930; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 11931; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 11932; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 11933; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 11934; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE = 11935; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN = 11936; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DONE = 11937; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ECC_MODE = 11938; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE = 11939; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN = 11940; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 11941; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE = 11942; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL = 11943; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 11944; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 11945; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 11946; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 11947; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE = 11948; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN = 11949; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DONE = 11950; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ECC_MODE = 11951; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE = 11952; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN = 11953; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 11954; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE = 11955; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL = 11956; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 11957; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 11958; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 11959; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 11960; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE = 11961; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN = 11962; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DONE = 11963; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ECC_MODE = 11964; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE = 11965; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN = 11966; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 11967; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE = 11968; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL = 11969; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 11970; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 11971; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 11972; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 11973; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE = 11974; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN = 11975; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DONE = 11976; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ECC_MODE = 11977; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE = 11978; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN = 11979; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 11980; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE = 11981; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL = 11982; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 11983; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 11984; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 11985; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 11986; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE = 11987; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN = 11988; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DONE = 11989; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ECC_MODE = 11990; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE = 11991; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN = 11992; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 11993; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE = 11994; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL = 11995; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 11996; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 11997; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 11998; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 11999; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE = 12000; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN = 12001; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DONE = 12002; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ECC_MODE = 12003; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE = 12004; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN = 12005; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 12006; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE = 12007; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL = 12008; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 12009; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 12010; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 12011; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 12012; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE = 12013; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN = 12014; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DONE = 12015; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ECC_MODE = 12016; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE = 12017; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN = 12018; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 12019; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE = 12020; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL = 12021; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 12022; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 12023; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 12024; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 12025; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE = 12026; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN = 12027; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DONE = 12028; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ECC_MODE = 12029; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE = 12030; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN = 12031; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 12032; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE = 12033; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL = 12034; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 12035; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 12036; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 12037; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 12038; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE = 12039; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN = 12040; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DONE = 12041; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ECC_MODE = 12042; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE = 12043; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN = 12044; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 12045; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE = 12046; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL = 12047; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 12048; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 12049; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 12050; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 12051; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE = 12052; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN = 12053; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DONE = 12054; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ECC_MODE = 12055; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE = 12056; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN = 12057; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 12058; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE = 12059; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL = 12060; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 12061; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 12062; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 12063; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 12064; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE = 12065; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN = 12066; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DONE = 12067; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ECC_MODE = 12068; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE = 12069; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN = 12070; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 12071; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE = 12072; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL = 12073; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 12074; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 12075; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 12076; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 12077; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE = 12078; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN = 12079; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DONE = 12080; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ECC_MODE = 12081; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE = 12082; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN = 12083; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 12084; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE = 12085; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL = 12086; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 12087; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 12088; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 12089; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 12090; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE = 12091; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN = 12092; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DONE = 12093; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ECC_MODE = 12094; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE = 12095; // 2 -static const uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN = 12096; // 2 -static const uint64_t SH_FLD_MCBIST_DATA_ERROR = 12097; // 2 -static const uint64_t SH_FLD_MCBIST_FSM_INJ_MODE = 12098; // 2 -static const uint64_t SH_FLD_MCBIST_FSM_INJ_REG = 12099; // 2 -static const uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK = 12100; // 8 -static const uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN = 12101; // 8 -static const uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 12102; // 2 -static const uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 12103; // 2 -static const uint64_t SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR = 12104; // 8 -static const uint64_t SH_FLD_MCBIST_PROGRAM_COMPLETE = 12105; // 2 -static const uint64_t SH_FLD_MCBIST_SUBTEST_IP = 12106; // 2 -static const uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR = 12107; // 2 -static const uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 12108; // 2 -static const uint64_t SH_FLD_MCBIST_TRAP_CE_ENABLE = 12109; // 8 -static const uint64_t SH_FLD_MCBIST_TRAP_MPE_ENABLE = 12110; // 8 -static const uint64_t SH_FLD_MCBIST_TRAP_NONSTOP = 12111; // 8 -static const uint64_t SH_FLD_MCBIST_TRAP_UE_ENABLE = 12112; // 8 -static const uint64_t SH_FLD_MCB_CNTLQ_PE_HOLD_OUT = 12113; // 2 -static const uint64_t SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT = 12114; // 2 -static const uint64_t SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 12115; // 2 -static const uint64_t SH_FLD_MCD_ACK_DEAD_CRESP_ERR = 12116; // 2 -static const uint64_t SH_FLD_MCD_ARRAY_ECC_CE_ERR = 12117; // 2 -static const uint64_t SH_FLD_MCD_ARRAY_ECC_UE_ERR = 12118; // 2 -static const uint64_t SH_FLD_MCD_CHICKEN_SWITCH = 12119; // 2 -static const uint64_t SH_FLD_MCD_CL_PROBE_PB_HANG_ERR = 12120; // 2 -static const uint64_t SH_FLD_MCD_CRESP_ADDR_ERR = 12121; // 2 -static const uint64_t SH_FLD_MCD_PB_ADDR_PARITY_ERR = 12122; // 2 -static const uint64_t SH_FLD_MCD_SCOM_ERR = 12123; // 2 -static const uint64_t SH_FLD_MCD_SCOM_ERR_DUP = 12124; // 2 -static const uint64_t SH_FLD_MCD_SM_OR_CASE_ERR = 12125; // 2 -static const uint64_t SH_FLD_MCD_TTAG_PARITY_ERR = 12126; // 2 -static const uint64_t SH_FLD_MCD_UNSOLICITED_CRESP_ERR = 12127; // 2 -static const uint64_t SH_FLD_MCD_UPDATE_ERR = 12128; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL0_COUNT = 12129; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL0_COUNT_LEN = 12130; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL1_COUNT = 12131; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL1_COUNT_LEN = 12132; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL2_COUNT = 12133; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL2_COUNT_LEN = 12134; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL3_COUNT = 12135; // 2 -static const uint64_t SH_FLD_MCE_SYMBOL3_COUNT_LEN = 12136; // 2 -static const uint64_t SH_FLD_MCMD = 12137; // 24 -static const uint64_t SH_FLD_MCMD_LEN = 12138; // 24 -static const uint64_t SH_FLD_MCMODE0_64B_WR_IS_PWRT = 12139; // 4 -static const uint64_t SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS = 12140; // 4 -static const uint64_t SH_FLD_MCS01_TC_0_FIR_HOST_ATTN = 12141; // 1 -static const uint64_t SH_FLD_MCS01_TC_1_FIR_HOST_ATTN = 12142; // 1 -static const uint64_t SH_FLD_MCS23_TC_0_FIR_HOST_ATTN = 12143; // 1 -static const uint64_t SH_FLD_MCS23_TC_1_FIR_HOST_ATTN = 12144; // 1 -static const uint64_t SH_FLD_MCS_RESET_KEEPER = 12145; // 4 -static const uint64_t SH_FLD_MCS_WAT0 = 12146; // 4 -static const uint64_t SH_FLD_MCS_WAT1 = 12147; // 4 -static const uint64_t SH_FLD_MCS_WAT2 = 12148; // 4 -static const uint64_t SH_FLD_MCS_WAT3 = 12149; // 4 -static const uint64_t SH_FLD_MCWATDATA0 = 12150; // 4 -static const uint64_t SH_FLD_MCWATDATA0_LEN = 12151; // 4 -static const uint64_t SH_FLD_MC_CHANNELS_PER_GROUP = 12152; // 4 -static const uint64_t SH_FLD_MC_CHANNELS_PER_GROUP_LEN = 12153; // 4 -static const uint64_t SH_FLD_MC_FP_MATE_CMD_ERR0 = 12154; // 12 -static const uint64_t SH_FLD_MC_FP_MATE_CMD_ERR1 = 12155; // 12 -static const uint64_t SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR = 12156; // 4 -static const uint64_t SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR = 12157; // 4 -static const uint64_t SH_FLD_MC_TC_0_FIR_HOST_ATTN = 12158; // 3 -static const uint64_t SH_FLD_MC_TC_1_FIR_HOST_ATTN = 12159; // 3 -static const uint64_t SH_FLD_MC_TC_2_FIR_HOST_ATTN = 12160; // 3 -static const uint64_t SH_FLD_MC_TC_3_FIR_HOST_ATTN = 12161; // 3 -static const uint64_t SH_FLD_MC_TC_4_FIR_HOST_ATTN = 12162; // 3 -static const uint64_t SH_FLD_MC_TC_5_FIR_HOST_ATTN = 12163; // 3 -static const uint64_t SH_FLD_MC_TC_6_FIR_HOST_ATTN = 12164; // 3 -static const uint64_t SH_FLD_MC_TC_7_FIR_HOST_ATTN = 12165; // 3 -static const uint64_t SH_FLD_MC_TC_8_FIR_HOST_ATTN = 12166; // 2 -static const uint64_t SH_FLD_MD5_LATENCY_CFG = 12167; // 1 -static const uint64_t SH_FLD_MDI_0 = 12168; // 8 -static const uint64_t SH_FLD_MDI_1 = 12169; // 8 -static const uint64_t SH_FLD_MED_IDLE_COUNT = 12170; // 8 -static const uint64_t SH_FLD_MED_IDLE_COUNT_LEN = 12171; // 8 -static const uint64_t SH_FLD_MED_IDLE_THRESHOLD = 12172; // 8 -static const uint64_t SH_FLD_MED_IDLE_THRESHOLD_LEN = 12173; // 8 -static const uint64_t SH_FLD_MEGAMOUTH = 12174; // 24 -static const uint64_t SH_FLD_MEM = 12175; // 26 -static const uint64_t SH_FLD_MEMCTL_CIC_FAST = 12176; // 8 -static const uint64_t SH_FLD_MEMCTL_CTRN_IGNORE = 12177; // 8 -static const uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP = 12178; // 4 -static const uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 12179; // 4 -static const uint64_t SH_FLD_MEMORY_TYPE = 12180; // 8 -static const uint64_t SH_FLD_MEMORY_TYPE_LEN = 12181; // 8 -static const uint64_t SH_FLD_MEM_ADDR = 12182; // 21 -static const uint64_t SH_FLD_MEM_ADDR_LEN = 12183; // 21 -static const uint64_t SH_FLD_MEM_BUSY = 12184; // 21 -static const uint64_t SH_FLD_MEM_BYTE_ENABLE = 12185; // 21 -static const uint64_t SH_FLD_MEM_BYTE_ENABLE_LEN = 12186; // 21 -static const uint64_t SH_FLD_MEM_DATAOP_PENDING = 12187; // 21 -static const uint64_t SH_FLD_MEM_ERROR = 12188; // 21 -static const uint64_t SH_FLD_MEM_ERROR_LEN = 12189; // 21 -static const uint64_t SH_FLD_MEM_HIGH_PRIORITY = 12190; // 4 -static const uint64_t SH_FLD_MEM_HIGH_PRIORITY_LEN = 12191; // 4 -static const uint64_t SH_FLD_MEM_IFETCH_PENDING = 12192; // 21 -static const uint64_t SH_FLD_MEM_IMPRECISE_ERROR_PENDING = 12193; // 21 -static const uint64_t SH_FLD_MEM_LEN = 12194; // 26 -static const uint64_t SH_FLD_MEM_LINE_MODE = 12195; // 21 -static const uint64_t SH_FLD_MEM_LOW_PRIORITY = 12196; // 4 -static const uint64_t SH_FLD_MEM_LOW_PRIORITY_LEN = 12197; // 4 -static const uint64_t SH_FLD_MEM_R_NW = 12198; // 21 -static const uint64_t SH_FLD_MEM_SIZE = 12199; // 6 -static const uint64_t SH_FLD_MEM_SIZE_LEN = 12200; // 6 -static const uint64_t SH_FLD_MERGE_CAPACITY_LIMIT = 12201; // 12 -static const uint64_t SH_FLD_MERGE_CAPACITY_LIMIT_LEN = 12202; // 12 -static const uint64_t SH_FLD_MESSAGE_BITS0 = 12203; // 15 -static const uint64_t SH_FLD_MESSAGE_BITS0_LEN = 12204; // 15 -static const uint64_t SH_FLD_MESSAGE_BITS1 = 12205; // 15 -static const uint64_t SH_FLD_MESSAGE_BITS1_LEN = 12206; // 15 -static const uint64_t SH_FLD_MESSAGE_BITS2 = 12207; // 12 -static const uint64_t SH_FLD_MESSAGE_BITS2_LEN = 12208; // 12 -static const uint64_t SH_FLD_MESSAGE_BITS3 = 12209; // 12 -static const uint64_t SH_FLD_MESSAGE_BITS3_LEN = 12210; // 12 -static const uint64_t SH_FLD_MESSAGE_BITS4 = 12211; // 12 -static const uint64_t SH_FLD_MESSAGE_BITS4_LEN = 12212; // 12 -static const uint64_t SH_FLD_MGR_CREDIT = 12213; // 3 -static const uint64_t SH_FLD_MGR_CREDIT_LEN = 12214; // 3 -static const uint64_t SH_FLD_MIB_GPIO = 12215; // 13 -static const uint64_t SH_FLD_MIB_GPIO_LEN = 12216; // 13 -static const uint64_t SH_FLD_MID_CARE_MASK = 12217; // 4 -static const uint64_t SH_FLD_MID_CARE_MASK_LEN = 12218; // 4 -static const uint64_t SH_FLD_MID_MATCH_VALUE = 12219; // 4 -static const uint64_t SH_FLD_MID_MATCH_VALUE_LEN = 12220; // 4 -static const uint64_t SH_FLD_MIG_REG = 12221; // 1 -static const uint64_t SH_FLD_MIG_REG_LEN = 12222; // 1 -static const uint64_t SH_FLD_MINCYCLECNT = 12223; // 3 -static const uint64_t SH_FLD_MINCYCLECNT_LEN = 12224; // 3 -static const uint64_t SH_FLD_MINIKERF = 12225; // 2 -static const uint64_t SH_FLD_MINIKERF_LEN = 12226; // 2 -static const uint64_t SH_FLD_MINOR = 12227; // 1 -static const uint64_t SH_FLD_MINOR_LEN = 12228; // 1 -static const uint64_t SH_FLD_MIN_CYCLE_SAMPLE = 12229; // 12 -static const uint64_t SH_FLD_MIN_CYCLE_SAMPLE_LEN = 12230; // 12 -static const uint64_t SH_FLD_MIN_EYE_HEIGHT = 12231; // 6 -static const uint64_t SH_FLD_MIN_EYE_HEIGHT_LEN = 12232; // 6 -static const uint64_t SH_FLD_MIN_EYE_WIDTH = 12233; // 6 -static const uint64_t SH_FLD_MIN_EYE_WIDTH_LEN = 12234; // 6 -static const uint64_t SH_FLD_MIRROR_ACTION_OCCURRED = 12235; // 4 -static const uint64_t SH_FLD_MISC = 12236; // 10 -static const uint64_t SH_FLD_MISC_BUS0BYTE0 = 12237; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE0_LEN = 12238; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE1 = 12239; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE10 = 12240; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE10_LEN = 12241; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE1_LEN = 12242; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE2 = 12243; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE2_LEN = 12244; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE3 = 12245; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE3_LEN = 12246; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE4 = 12247; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE4_LEN = 12248; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE5 = 12249; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE5_LEN = 12250; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE6 = 12251; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE6_LEN = 12252; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE7 = 12253; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE7_LEN = 12254; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE8 = 12255; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE8_LEN = 12256; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE9 = 12257; // 1 -static const uint64_t SH_FLD_MISC_BUS0BYTE9_LEN = 12258; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE0 = 12259; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE0_LEN = 12260; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE1 = 12261; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE10 = 12262; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE10_LEN = 12263; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE1_LEN = 12264; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE2 = 12265; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE2_LEN = 12266; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE3 = 12267; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE3_LEN = 12268; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE4 = 12269; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE4_LEN = 12270; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE5 = 12271; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE5_LEN = 12272; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE6 = 12273; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE6_LEN = 12274; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE7 = 12275; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE7_LEN = 12276; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE8 = 12277; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE8_LEN = 12278; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE9 = 12279; // 1 -static const uint64_t SH_FLD_MISC_BUS1BYTE9_LEN = 12280; // 1 -static const uint64_t SH_FLD_MISC_CFG = 12281; // 6 -static const uint64_t SH_FLD_MISC_CFG_LEN = 12282; // 6 -static const uint64_t SH_FLD_MISC_CTL_4VS64 = 12283; // 1 -static const uint64_t SH_FLD_MISC_CTL_ACCEPT_PASTE = 12284; // 1 -static const uint64_t SH_FLD_MISC_CTL_CAM_INVAL_DONE = 12285; // 1 -static const uint64_t SH_FLD_MISC_CTL_CAM_LOCATION = 12286; // 1 -static const uint64_t SH_FLD_MISC_CTL_CAM_LOCATION_LEN = 12287; // 1 -static const uint64_t SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT = 12288; // 1 -static const uint64_t SH_FLD_MISC_CTL_ENABLE_WRMON = 12289; // 1 -static const uint64_t SH_FLD_MISC_CTL_HMI_ACTIVE = 12290; // 1 -static const uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL = 12291; // 1 -static const uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC = 12292; // 1 -static const uint64_t SH_FLD_MISC_CTL_PREFETCH_DISABLE = 12293; // 1 -static const uint64_t SH_FLD_MISC_CTL_QUIESCE_REQUEST = 12294; // 1 -static const uint64_t SH_FLD_MISC_CTL_RG_IS_IDLE = 12295; // 1 -static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS = 12296; // 1 -static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS2 = 12297; // 1 -static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS_LEN = 12298; // 1 -static const uint64_t SH_FLD_MISC_CTRL_PERR = 12299; // 1 -static const uint64_t SH_FLD_MISC_DA_ADDR_PERR = 12300; // 1 -static const uint64_t SH_FLD_MISC_DA_OP = 12301; // 1 -static const uint64_t SH_FLD_MISC_INT_RA_PERR = 12302; // 1 -static const uint64_t SH_FLD_MISC_LEN = 12303; // 10 -static const uint64_t SH_FLD_MISC_LENGTH = 12304; // 1 -static const uint64_t SH_FLD_MISC_LENGTH_LEN = 12305; // 1 -static const uint64_t SH_FLD_MISC_LENR = 12306; // 1 -static const uint64_t SH_FLD_MISC_LENR_LEN = 12307; // 1 -static const uint64_t SH_FLD_MISC_NMMU_ERR = 12308; // 1 -static const uint64_t SH_FLD_MISC_RESYNC_OSC_FROM = 12309; // 1 -static const uint64_t SH_FLD_MISC_RING_ERR = 12310; // 1 -static const uint64_t SH_FLD_MISC_RNW = 12311; // 1 -static const uint64_t SH_FLD_MISC_RSVD = 12312; // 1 -static const uint64_t SH_FLD_MISC_RSVD_LEN = 12313; // 1 -static const uint64_t SH_FLD_MISR_A_VAL = 12314; // 43 -static const uint64_t SH_FLD_MISR_A_VAL_LEN = 12315; // 43 -static const uint64_t SH_FLD_MISR_B_VAL = 12316; // 43 -static const uint64_t SH_FLD_MISR_B_VAL_LEN = 12317; // 43 -static const uint64_t SH_FLD_MISR_INIT_WAIT = 12318; // 43 -static const uint64_t SH_FLD_MISR_INIT_WAIT_LEN = 12319; // 43 -static const uint64_t SH_FLD_MISR_MODE = 12320; // 43 -static const uint64_t SH_FLD_MLC_ACCESS_ERR_ESR = 12321; // 1 -static const uint64_t SH_FLD_MMIO = 12322; // 15 -static const uint64_t SH_FLD_MMIOSD = 12323; // 1 -static const uint64_t SH_FLD_MMIO_BAR_PE = 12324; // 1 -static const uint64_t SH_FLD_MMIO_CTL_ACTYPE = 12325; // 1 -static const uint64_t SH_FLD_MMIO_CTL_COMP = 12326; // 1 -static const uint64_t SH_FLD_MMIO_CTL_INIT = 12327; // 1 -static const uint64_t SH_FLD_MMIO_CTL_OFFSET = 12328; // 1 -static const uint64_t SH_FLD_MMIO_CTL_OFFSET_LEN = 12329; // 1 -static const uint64_t SH_FLD_MMIO_CTL_OPTYPE = 12330; // 1 -static const uint64_t SH_FLD_MMIO_CTL_OP_ERR = 12331; // 1 -static const uint64_t SH_FLD_MMIO_CTL_UNUSED = 12332; // 1 -static const uint64_t SH_FLD_MMIO_CTL_UNUSED_LEN = 12333; // 1 -static const uint64_t SH_FLD_MMIO_CTL_WINID = 12334; // 1 -static const uint64_t SH_FLD_MMIO_CTL_WINID_LEN = 12335; // 1 -static const uint64_t SH_FLD_MMIO_DATA = 12336; // 1 -static const uint64_t SH_FLD_MMIO_DATA_LEN = 12337; // 1 -static const uint64_t SH_FLD_MMIO_ECC = 12338; // 1 -static const uint64_t SH_FLD_MMIO_ECC_LEN = 12339; // 1 -static const uint64_t SH_FLD_MMIO_HYP_RD_ADDR_ERR = 12340; // 2 -static const uint64_t SH_FLD_MMIO_HYP_WR_ADDR_ERR = 12341; // 2 -static const uint64_t SH_FLD_MMIO_LDST_TIMEOUT = 12342; // 1 -static const uint64_t SH_FLD_MMIO_LDST_TIMEOUT_LEN = 12343; // 1 -static const uint64_t SH_FLD_MMIO_NON8B_HYP_ERR = 12344; // 2 -static const uint64_t SH_FLD_MMIO_NON8B_OS_ERR = 12345; // 2 -static const uint64_t SH_FLD_MMIO_OS_RD_ADDR_ERR = 12346; // 2 -static const uint64_t SH_FLD_MMIO_OS_WR_ADDR_ERR = 12347; // 2 -static const uint64_t SH_FLD_MMIO_PG_REG_ACCESS = 12348; // 4 -static const uint64_t SH_FLD_MMIO_REQUEST_TIMEOUT = 12349; // 6 -static const uint64_t SH_FLD_MMR = 12350; // 1 -static const uint64_t SH_FLD_MMR_LEN = 12351; // 1 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00 = 12352; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN = 12353; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01 = 12354; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN = 12355; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02 = 12356; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN = 12357; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03 = 12358; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN = 12359; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04 = 12360; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN = 12361; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05 = 12362; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN = 12363; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06 = 12364; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN = 12365; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07 = 12366; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN = 12367; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08 = 12368; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN = 12369; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09 = 12370; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN = 12371; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10 = 12372; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN = 12373; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11 = 12374; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN = 12375; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12 = 12376; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN = 12377; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13 = 12378; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN = 12379; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14 = 12380; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN = 12381; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15 = 12382; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN = 12383; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16 = 12384; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN = 12385; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17 = 12386; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN = 12387; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18 = 12388; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN = 12389; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19 = 12390; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN = 12391; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20 = 12392; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN = 12393; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21 = 12394; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN = 12395; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22 = 12396; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN = 12397; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23 = 12398; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN = 12399; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24 = 12400; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN = 12401; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25 = 12402; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN = 12403; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26 = 12404; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN = 12405; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27 = 12406; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN = 12407; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28 = 12408; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN = 12409; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29 = 12410; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN = 12411; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30 = 12412; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN = 12413; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31 = 12414; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN = 12415; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32 = 12416; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN = 12417; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33 = 12418; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN = 12419; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34 = 12420; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN = 12421; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35 = 12422; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN = 12423; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36 = 12424; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN = 12425; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37 = 12426; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN = 12427; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38 = 12428; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN = 12429; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39 = 12430; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN = 12431; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40 = 12432; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN = 12433; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41 = 12434; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN = 12435; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42 = 12436; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN = 12437; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43 = 12438; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN = 12439; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44 = 12440; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN = 12441; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45 = 12442; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN = 12443; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46 = 12444; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN = 12445; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47 = 12446; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN = 12447; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48 = 12448; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN = 12449; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49 = 12450; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN = 12451; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50 = 12452; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN = 12453; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51 = 12454; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN = 12455; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52 = 12456; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN = 12457; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53 = 12458; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN = 12459; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54 = 12460; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN = 12461; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55 = 12462; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN = 12463; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56 = 12464; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN = 12465; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57 = 12466; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN = 12467; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58 = 12468; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN = 12469; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59 = 12470; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN = 12471; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60 = 12472; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN = 12473; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61 = 12474; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN = 12475; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62 = 12476; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN = 12477; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63 = 12478; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN = 12479; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64 = 12480; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN = 12481; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65 = 12482; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN = 12483; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66 = 12484; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN = 12485; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67 = 12486; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN = 12487; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68 = 12488; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN = 12489; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69 = 12490; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN = 12491; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70 = 12492; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN = 12493; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71 = 12494; // 2 -static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN = 12495; // 2 -static const uint64_t SH_FLD_MODE = 12496; // 153 -static const uint64_t SH_FLD_MODEREG_SPRC_LT0_SEL = 12497; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT1_SEL = 12498; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT2_SEL = 12499; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT3_SEL = 12500; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT4_SEL = 12501; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT5_SEL = 12502; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT6_SEL = 12503; // 24 -static const uint64_t SH_FLD_MODEREG_SPRC_LT7_SEL = 12504; // 24 -static const uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ = 12505; // 24 -static const uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ_LEN = 12506; // 24 -static const uint64_t SH_FLD_MODE_128K_VP = 12507; // 1 -static const uint64_t SH_FLD_MODE_LEN = 12508; // 151 -static const uint64_t SH_FLD_MODE_REGISTER_0_VALUE = 12509; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_0_VALUE_LEN = 12510; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_1_VALUE = 12511; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_1_VALUE_LEN = 12512; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_2_VALUE = 12513; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_2_VALUE_LEN = 12514; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_3_VALUE = 12515; // 64 -static const uint64_t SH_FLD_MODE_REGISTER_3_VALUE_LEN = 12516; // 64 -static const uint64_t SH_FLD_MODE_SEL = 12517; // 12 -static const uint64_t SH_FLD_MON = 12518; // 12 -static const uint64_t SH_FLD_MON_LEN = 12519; // 12 -static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS = 12520; // 1 -static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 12521; // 1 -static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN = 12522; // 1 -static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ID = 12523; // 1 -static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ID_LEN = 12524; // 1 -static const uint64_t SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 12525; // 1 -static const uint64_t SH_FLD_MPR_PAGE = 12526; // 8 -static const uint64_t SH_FLD_MPR_PAGE_LEN = 12527; // 8 -static const uint64_t SH_FLD_MPR_PATTERN_BIT = 12528; // 8 -static const uint64_t SH_FLD_MPSS_DIS = 12529; // 1 -static const uint64_t SH_FLD_MPW1 = 12530; // 43 -static const uint64_t SH_FLD_MPW2 = 12531; // 43 -static const uint64_t SH_FLD_MPW3 = 12532; // 43 -static const uint64_t SH_FLD_MRBGP = 12533; // 15 -static const uint64_t SH_FLD_MRBGP_LEN = 12534; // 15 -static const uint64_t SH_FLD_MRBSP = 12535; // 15 -static const uint64_t SH_FLD_MRBSP_LEN = 12536; // 15 -static const uint64_t SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR = 12537; // 6 -static const uint64_t SH_FLD_MRG_BBRD_NBUF = 12538; // 3 -static const uint64_t SH_FLD_MRG_BBRD_NBUF_LEN = 12539; // 3 -static const uint64_t SH_FLD_MRG_COMMON_FATAL_ERROR = 12540; // 6 -static const uint64_t SH_FLD_MRG_CR_DIS = 12541; // 3 -static const uint64_t SH_FLD_MRG_CTLW_CR_DIS = 12542; // 3 -static const uint64_t SH_FLD_MRG_ECC_CORRECTABLE_ERROR = 12543; // 6 -static const uint64_t SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR = 12544; // 6 -static const uint64_t SH_FLD_MRG_IBRD_NBUF = 12545; // 3 -static const uint64_t SH_FLD_MRG_IBRD_NBUF_LEN = 12546; // 3 -static const uint64_t SH_FLD_MRG_IBWR_NBUF = 12547; // 3 -static const uint64_t SH_FLD_MRG_IBWR_NBUF_LEN = 12548; // 3 -static const uint64_t SH_FLD_MRG_MRT_ERROR = 12549; // 6 -static const uint64_t SH_FLD_MRG_OBRD_NBUF = 12550; // 3 -static const uint64_t SH_FLD_MRG_OBRD_NBUF_LEN = 12551; // 3 -static const uint64_t SH_FLD_MRG_PBTX_NBUF = 12552; // 3 -static const uint64_t SH_FLD_MRG_PBTX_NBUF_LEN = 12553; // 3 -static const uint64_t SH_FLD_MRG_RDBF_NBUF = 12554; // 3 -static const uint64_t SH_FLD_MRG_RDBF_NBUF_LEN = 12555; // 3 -static const uint64_t SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR = 12556; // 6 -static const uint64_t SH_FLD_MRS_CMD_DQ_OFF = 12557; // 8 -static const uint64_t SH_FLD_MRS_CMD_DQ_OFF_LEN = 12558; // 8 -static const uint64_t SH_FLD_MRS_CMD_DQ_ON = 12559; // 8 -static const uint64_t SH_FLD_MRS_CMD_DQ_ON_LEN = 12560; // 8 -static const uint64_t SH_FLD_MRT_ERR_NOT_VALID = 12561; // 1 -static const uint64_t SH_FLD_MRT_ERR_PSIZE = 12562; // 1 -static const uint64_t SH_FLD_MR_MASK_EN = 12563; // 8 -static const uint64_t SH_FLD_MR_MASK_EN_LEN = 12564; // 8 -static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 12565; // 1 -static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 12566; // 1 -static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 12567; // 1 -static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 12568; // 1 -static const uint64_t SH_FLD_MSADES_CLEAR_1 = 12569; // 1 -static const uint64_t SH_FLD_MSADES_CLEAR_2 = 12570; // 1 -static const uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 12571; // 1 -static const uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 12572; // 1 -static const uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 12573; // 1 -static const uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 12574; // 1 -static const uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_1 = 12575; // 1 -static const uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_2 = 12576; // 1 -static const uint64_t SH_FLD_MSADES_UNUSED_15_12 = 12577; // 1 -static const uint64_t SH_FLD_MSADES_UNUSED_15_12_LEN = 12578; // 1 -static const uint64_t SH_FLD_MSADES_UNUSED_31_28 = 12579; // 1 -static const uint64_t SH_FLD_MSADES_UNUSED_31_28_LEN = 12580; // 1 -static const uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_1 = 12581; // 1 -static const uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_2 = 12582; // 1 -static const uint64_t SH_FLD_MSADI_PIB_ERROR_1 = 12583; // 1 -static const uint64_t SH_FLD_MSADI_PIB_ERROR_2 = 12584; // 1 -static const uint64_t SH_FLD_MSADI_PIB_PENDING_1 = 12585; // 1 -static const uint64_t SH_FLD_MSADI_PIB_PENDING_2 = 12586; // 1 -static const uint64_t SH_FLD_MSADI_UNUSED_31_11 = 12587; // 4 -static const uint64_t SH_FLD_MSADI_UNUSED_31_11_LEN = 12588; // 4 -static const uint64_t SH_FLD_MSADI_UNUSED_7_3 = 12589; // 1 -static const uint64_t SH_FLD_MSADI_UNUSED_7_3_LEN = 12590; // 1 -static const uint64_t SH_FLD_MSADI_XUP_1 = 12591; // 1 -static const uint64_t SH_FLD_MSADI_XUP_2 = 12592; // 1 -static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 12593; // 1 -static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 12594; // 1 -static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 12595; // 1 -static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 12596; // 1 -static const uint64_t SH_FLD_MSBDES_CLEAR_1 = 12597; // 1 -static const uint64_t SH_FLD_MSBDES_CLEAR_2 = 12598; // 1 -static const uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 12599; // 1 -static const uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 12600; // 1 -static const uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 12601; // 1 -static const uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 12602; // 1 -static const uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 = 12603; // 1 -static const uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 = 12604; // 1 -static const uint64_t SH_FLD_MSBDES_UNUSED_15_12 = 12605; // 1 -static const uint64_t SH_FLD_MSBDES_UNUSED_15_12_LEN = 12606; // 1 -static const uint64_t SH_FLD_MSBDES_UNUSED_31_28 = 12607; // 1 -static const uint64_t SH_FLD_MSBDES_UNUSED_31_28_LEN = 12608; // 1 -static const uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 = 12609; // 1 -static const uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 = 12610; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT = 12611; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT_2 = 12612; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR = 12613; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 = 12614; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING = 12615; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 = 12616; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_XDN = 12617; // 1 -static const uint64_t SH_FLD_MSBDIM1_ENABLE_XDN_2 = 12618; // 1 -static const uint64_t SH_FLD_MSBDI_LBUS_ERROR_1 = 12619; // 1 -static const uint64_t SH_FLD_MSBDI_LBUS_ERROR_2 = 12620; // 1 -static const uint64_t SH_FLD_MSBDI_LBUS_PENDING_1 = 12621; // 1 -static const uint64_t SH_FLD_MSBDI_LBUS_PENDING_2 = 12622; // 1 -static const uint64_t SH_FLD_MSBDI_XDN_1 = 12623; // 1 -static const uint64_t SH_FLD_MSBDI_XDN_2 = 12624; // 1 -static const uint64_t SH_FLD_MSBSWAP = 12625; // 4 -static const uint64_t SH_FLD_MSC_BUS0_STG0_SEL = 12626; // 1 -static const uint64_t SH_FLD_MSC_BUS0_STG0_SEL_LEN = 12627; // 1 -static const uint64_t SH_FLD_MSC_BUS0_STG1_SEL = 12628; // 1 -static const uint64_t SH_FLD_MSC_BUS0_STG2_SEL = 12629; // 1 -static const uint64_t SH_FLD_MSC_BUS1_STG0_SEL = 12630; // 1 -static const uint64_t SH_FLD_MSC_BUS1_STG0_SEL_LEN = 12631; // 1 -static const uint64_t SH_FLD_MSC_BUS1_STG1_SEL = 12632; // 1 -static const uint64_t SH_FLD_MSC_BUS1_STG2_SEL = 12633; // 1 -static const uint64_t SH_FLD_MSG_ADDR_ERR = 12634; // 12 -static const uint64_t SH_FLD_MSK = 12635; // 5 -static const uint64_t SH_FLD_MSK_LEN = 12636; // 5 -static const uint64_t SH_FLD_MSM_CURR_STATE_0 = 12637; // 2 -static const uint64_t SH_FLD_MSM_CURR_STATE_0_LEN = 12638; // 2 -static const uint64_t SH_FLD_MSM_CURR_STATE_1 = 12639; // 1 -static const uint64_t SH_FLD_MSM_CURR_STATE_1_LEN = 12640; // 1 -static const uint64_t SH_FLD_MSM_CURR_STATE_2 = 12641; // 1 -static const uint64_t SH_FLD_MSM_CURR_STATE_2_LEN = 12642; // 1 -static const uint64_t SH_FLD_MSM_CURR_STATE_3 = 12643; // 1 -static const uint64_t SH_FLD_MSM_CURR_STATE_3_LEN = 12644; // 1 -static const uint64_t SH_FLD_MSR_DR = 12645; // 256 -static const uint64_t SH_FLD_MSR_HV = 12646; // 256 -static const uint64_t SH_FLD_MSR_PE = 12647; // 8 -static const uint64_t SH_FLD_MSR_PR = 12648; // 256 -static const uint64_t SH_FLD_MSR_SF = 12649; // 256 -static const uint64_t SH_FLD_MSR_TA = 12650; // 256 -static const uint64_t SH_FLD_MSR_US = 12651; // 256 -static const uint64_t SH_FLD_MSR_UV = 12652; // 256 -static const uint64_t SH_FLD_MST_DIS_ABUSPAREN = 12653; // 1 -static const uint64_t SH_FLD_MST_DIS_BEPAREN = 12654; // 1 -static const uint64_t SH_FLD_MST_DIS_RDDBUSPAR = 12655; // 1 -static const uint64_t SH_FLD_MST_DIS_WRDBUSPAREN = 12656; // 1 -static const uint64_t SH_FLD_MST_SPARE = 12657; // 1 -static const uint64_t SH_FLD_MS_GROUP_CHIP = 12658; // 2 -static const uint64_t SH_FLD_MS_GROUP_CHIP_LEN = 12659; // 2 -static const uint64_t SH_FLD_MS_WAT_DEBUG_CONFIG_REG_ERROR = 12660; // 4 -static const uint64_t SH_FLD_MULTICAST1 = 12661; // 43 -static const uint64_t SH_FLD_MULTICAST1_LEN = 12662; // 43 -static const uint64_t SH_FLD_MULTICAST2 = 12663; // 43 -static const uint64_t SH_FLD_MULTICAST2_LEN = 12664; // 43 -static const uint64_t SH_FLD_MULTICAST3 = 12665; // 43 -static const uint64_t SH_FLD_MULTICAST3_LEN = 12666; // 43 -static const uint64_t SH_FLD_MULTICAST4 = 12667; // 43 -static const uint64_t SH_FLD_MULTICAST4_LEN = 12668; // 43 -static const uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER = 12669; // 2 -static const uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER_LEN = 12670; // 2 -static const uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER = 12671; // 1 -static const uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 12672; // 1 -static const uint64_t SH_FLD_MULTIHIT_CHK_DIS = 12673; // 1 -static const uint64_t SH_FLD_MULTIPLE_BAR = 12674; // 4 -static const uint64_t SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED = 12675; // 12 -static const uint64_t SH_FLD_MULTIPLE_REQ = 12676; // 8 -static const uint64_t SH_FLD_MULTIPLE_REQ_SOURCE = 12677; // 8 -static const uint64_t SH_FLD_MULTIPLE_REQ_SOURCE_LEN = 12678; // 8 -static const uint64_t SH_FLD_MULT_REQ_ERR_MASK = 12679; // 8 -static const uint64_t SH_FLD_MUOP_ERROR_1 = 12680; // 4 -static const uint64_t SH_FLD_MUOP_ERROR_2 = 12681; // 4 -static const uint64_t SH_FLD_MUOP_ERROR_3 = 12682; // 4 -static const uint64_t SH_FLD_MUXEN = 12683; // 4 -static const uint64_t SH_FLD_MUXSEL = 12684; // 4 -static const uint64_t SH_FLD_MUXSEL_LEN = 12685; // 4 -static const uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE = 12686; // 1 -static const uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN = 12687; // 1 -static const uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE = 12688; // 1 -static const uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN = 12689; // 1 -static const uint64_t SH_FLD_M_CPS_ENABLE = 12690; // 1 -static const uint64_t SH_FLD_M_PATH_0_OSC_NOT_VALID = 12691; // 1 -static const uint64_t SH_FLD_M_PATH_0_PARITY = 12692; // 4 -static const uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 12693; // 1 -static const uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 12694; // 1 -static const uint64_t SH_FLD_M_PATH_0_STEP_CHECK = 12695; // 4 -static const uint64_t SH_FLD_M_PATH_0_STEP_CHECK_VALID = 12696; // 1 -static const uint64_t SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 12697; // 1 -static const uint64_t SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 12698; // 1 -static const uint64_t SH_FLD_M_PATH_1_OSC_NOT_VALID = 12699; // 1 -static const uint64_t SH_FLD_M_PATH_1_PARITY = 12700; // 4 -static const uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 12701; // 1 -static const uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 12702; // 1 -static const uint64_t SH_FLD_M_PATH_1_STEP_CHECK = 12703; // 4 -static const uint64_t SH_FLD_M_PATH_1_STEP_CHECK_VALID = 12704; // 1 -static const uint64_t SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 12705; // 1 -static const uint64_t SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 12706; // 1 -static const uint64_t SH_FLD_M_PATH_CLOCK_OFF_ENABLE = 12707; // 1 -static const uint64_t SH_FLD_M_PATH_SELECT = 12708; // 1 -static const uint64_t SH_FLD_M_PATH_SWITCH_TRIGGER = 12709; // 1 -static const uint64_t SH_FLD_N0DGD = 12710; // 12 -static const uint64_t SH_FLD_N0REQ = 12711; // 12 -static const uint64_t SH_FLD_N0RSP = 12712; // 12 -static const uint64_t SH_FLD_N1DGD = 12713; // 12 -static const uint64_t SH_FLD_N1REQ = 12714; // 12 -static const uint64_t SH_FLD_N1RSP = 12715; // 12 -static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_0 = 12716; // 4 -static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_1 = 12717; // 2 -static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_2 = 12718; // 2 -static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_3 = 12719; // 2 -static const uint64_t SH_FLD_NB_CLEAN_SLOT = 12720; // 6 -static const uint64_t SH_FLD_NB_CLEAN_SLOT_LEN = 12721; // 6 -static const uint64_t SH_FLD_NB_WRITE_SLOT = 12722; // 6 -static const uint64_t SH_FLD_NB_WRITE_SLOT_LEN = 12723; // 6 -static const uint64_t SH_FLD_NCU_POWERBUS_DATA_TIMEOUT = 12724; // 12 -static const uint64_t SH_FLD_NCU_PURGE = 12725; // 12 -static const uint64_t SH_FLD_NCU_PURGE_ABORT = 12726; // 12 -static const uint64_t SH_FLD_NCU_PURGE_DONE = 12727; // 24 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH = 12728; // 1 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN = 12729; // 1 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE = 12730; // 1 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN = 12731; // 1 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE = 12732; // 1 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN = 12733; // 1 -static const uint64_t SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN = 12734; // 1 -static const uint64_t SH_FLD_NCU_TLBIE_QUIESCE = 12735; // 12 -static const uint64_t SH_FLD_NDL = 12736; // 6 -static const uint64_t SH_FLD_NDLMUX_BRK0TO2 = 12737; // 1 -static const uint64_t SH_FLD_NDLMUX_BRK0TO2_LEN = 12738; // 1 -static const uint64_t SH_FLD_NDL_BRK0_NOSTALL = 12739; // 1 -static const uint64_t SH_FLD_NDL_BRK0_STALL = 12740; // 1 -static const uint64_t SH_FLD_NDL_BRK1_NOSTALL = 12741; // 1 -static const uint64_t SH_FLD_NDL_BRK1_STALL = 12742; // 1 -static const uint64_t SH_FLD_NDL_BRK2_NOSTALL = 12743; // 1 -static const uint64_t SH_FLD_NDL_BRK2_STALL = 12744; // 1 -static const uint64_t SH_FLD_NDL_BRK3_NOSTALL = 12745; // 1 -static const uint64_t SH_FLD_NDL_BRK3_STALL = 12746; // 1 -static const uint64_t SH_FLD_NDL_BRK4_NOSTALL = 12747; // 1 -static const uint64_t SH_FLD_NDL_BRK4_STALL = 12748; // 1 -static const uint64_t SH_FLD_NDL_BRK5_NOSTALL = 12749; // 1 -static const uint64_t SH_FLD_NDL_BRK5_STALL = 12750; // 1 -static const uint64_t SH_FLD_NDL_LEN = 12751; // 6 -static const uint64_t SH_FLD_NDL_PRI_PARITY_ENA = 12752; // 6 -static const uint64_t SH_FLD_NDL_RX_PARITY_ENA = 12753; // 6 -static const uint64_t SH_FLD_NDL_TX_PARITY_ENA = 12754; // 6 -static const uint64_t SH_FLD_NEAR_NODAL_EPSILON = 12755; // 8 -static const uint64_t SH_FLD_NEAR_NODAL_EPSILON_LEN = 12756; // 8 -static const uint64_t SH_FLD_NEST_DBG_SEL_IN = 12757; // 8 -static const uint64_t SH_FLD_NEST_DBG_SEL_WRT = 12758; // 8 -static const uint64_t SH_FLD_NEST_LIMIT = 12759; // 24 -static const uint64_t SH_FLD_NEST_LIMIT_LEN = 12760; // 24 -static const uint64_t SH_FLD_NETWORK_RESET_OCCURRED = 12761; // 30 -static const uint64_t SH_FLD_NEXT_CAL_LANE_SEL = 12762; // 68 -static const uint64_t SH_FLD_NEXT_RANK = 12763; // 8 -static const uint64_t SH_FLD_NEXT_RANK_LEN = 12764; // 8 -static const uint64_t SH_FLD_NEXT_RANK_PAIR = 12765; // 8 -static const uint64_t SH_FLD_NEXT_RANK_PAIR_LEN = 12766; // 8 -static const uint64_t SH_FLD_NFIRACTION0 = 12767; // 9 -static const uint64_t SH_FLD_NFIRACTION0_LEN = 12768; // 9 -static const uint64_t SH_FLD_NFIRACTION1 = 12769; // 9 -static const uint64_t SH_FLD_NFIRACTION1_LEN = 12770; // 9 -static const uint64_t SH_FLD_NFIRMASK = 12771; // 9 -static const uint64_t SH_FLD_NFIRMASK_LEN = 12772; // 9 -static const uint64_t SH_FLD_NFIRNFIR = 12773; // 9 -static const uint64_t SH_FLD_NFIRNFIR_LEN = 12774; // 9 -static const uint64_t SH_FLD_NMCMD = 12775; // 6 -static const uint64_t SH_FLD_NMCMD_LEN = 12776; // 6 -static const uint64_t SH_FLD_NMEXCMD = 12777; // 6 -static const uint64_t SH_FLD_NMEXCMD_LEN = 12778; // 6 -static const uint64_t SH_FLD_NMMU = 12779; // 3 -static const uint64_t SH_FLD_NMMU_LOCAL_XSTOP = 12780; // 1 -static const uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS = 12781; // 4 -static const uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS_LEN = 12782; // 4 -static const uint64_t SH_FLD_NONZERO_CSB_CC = 12783; // 1 -static const uint64_t SH_FLD_NOTIFY_FAILED_ERR = 12784; // 2 -static const uint64_t SH_FLD_NOT_TRIGGER_MODE1 = 12785; // 86 -static const uint64_t SH_FLD_NOT_TRIGGER_MODE2 = 12786; // 86 -static const uint64_t SH_FLD_NOT_USED_0 = 12787; // 2 -static const uint64_t SH_FLD_NOT_USED_0_LEN = 12788; // 2 -static const uint64_t SH_FLD_NOT_USED_1 = 12789; // 1 -static const uint64_t SH_FLD_NOT_USED_1_LEN = 12790; // 1 -static const uint64_t SH_FLD_NOT_USED_2 = 12791; // 1 -static const uint64_t SH_FLD_NOT_USED_2_LEN = 12792; // 1 -static const uint64_t SH_FLD_NOT_USED_3 = 12793; // 1 -static const uint64_t SH_FLD_NOT_USED_3_LEN = 12794; // 1 -static const uint64_t SH_FLD_NO_WAIT_ON_CLK_CMD = 12795; // 43 -static const uint64_t SH_FLD_NPU_LXSTOP_ERR_DET = 12796; // 1 -static const uint64_t SH_FLD_NPU_TRANSPORT_SWAP = 12797; // 2 -static const uint64_t SH_FLD_NR_OF_FRAMES = 12798; // 1 -static const uint64_t SH_FLD_NSEG_MAIN_EN = 12799; // 6 -static const uint64_t SH_FLD_NSEG_MAIN_EN_LEN = 12800; // 6 -static const uint64_t SH_FLD_NSEG_MARGINPD_EN = 12801; // 6 -static const uint64_t SH_FLD_NSEG_MARGINPD_EN_LEN = 12802; // 6 -static const uint64_t SH_FLD_NSEG_MARGINPU_EN = 12803; // 6 -static const uint64_t SH_FLD_NSEG_MARGINPU_EN_LEN = 12804; // 6 -static const uint64_t SH_FLD_NSEG_POST_EN = 12805; // 2 -static const uint64_t SH_FLD_NSEG_POST_EN_LEN = 12806; // 2 -static const uint64_t SH_FLD_NSEG_POST_SEL = 12807; // 2 -static const uint64_t SH_FLD_NSEG_POST_SEL_LEN = 12808; // 2 -static const uint64_t SH_FLD_NSEG_PRE_EN = 12809; // 6 -static const uint64_t SH_FLD_NSEG_PRE_EN_LEN = 12810; // 6 -static const uint64_t SH_FLD_NSEG_PRE_SEL = 12811; // 6 -static const uint64_t SH_FLD_NSEG_PRE_SEL_LEN = 12812; // 6 -static const uint64_t SH_FLD_NSL_FILL_COUNT = 12813; // 43 -static const uint64_t SH_FLD_NSL_FILL_COUNT_LEN = 12814; // 43 -static const uint64_t SH_FLD_NSQ_LFSR_CNTL = 12815; // 8 -static const uint64_t SH_FLD_NSQ_LFSR_CNTL_LEN = 12816; // 8 -static const uint64_t SH_FLD_NTLR_PAUSE_THRESH = 12817; // 3 -static const uint64_t SH_FLD_NTLR_PAUSE_THRESH_LEN = 12818; // 3 -static const uint64_t SH_FLD_NTLW_PAUSE_THRESH = 12819; // 3 -static const uint64_t SH_FLD_NTLW_PAUSE_THRESH_LEN = 12820; // 3 -static const uint64_t SH_FLD_NTL_0 = 12821; // 48 -static const uint64_t SH_FLD_NTL_1 = 12822; // 48 -static const uint64_t SH_FLD_NTL_10 = 12823; // 48 -static const uint64_t SH_FLD_NTL_11 = 12824; // 48 -static const uint64_t SH_FLD_NTL_12 = 12825; // 48 -static const uint64_t SH_FLD_NTL_13 = 12826; // 48 -static const uint64_t SH_FLD_NTL_14 = 12827; // 48 -static const uint64_t SH_FLD_NTL_15 = 12828; // 48 -static const uint64_t SH_FLD_NTL_16 = 12829; // 48 -static const uint64_t SH_FLD_NTL_17 = 12830; // 48 -static const uint64_t SH_FLD_NTL_18 = 12831; // 48 -static const uint64_t SH_FLD_NTL_19 = 12832; // 48 -static const uint64_t SH_FLD_NTL_2 = 12833; // 48 -static const uint64_t SH_FLD_NTL_20 = 12834; // 48 -static const uint64_t SH_FLD_NTL_21 = 12835; // 48 -static const uint64_t SH_FLD_NTL_22 = 12836; // 48 -static const uint64_t SH_FLD_NTL_23 = 12837; // 48 -static const uint64_t SH_FLD_NTL_24 = 12838; // 48 -static const uint64_t SH_FLD_NTL_25 = 12839; // 48 -static const uint64_t SH_FLD_NTL_26 = 12840; // 48 -static const uint64_t SH_FLD_NTL_27 = 12841; // 48 -static const uint64_t SH_FLD_NTL_28 = 12842; // 48 -static const uint64_t SH_FLD_NTL_29 = 12843; // 48 -static const uint64_t SH_FLD_NTL_3 = 12844; // 48 -static const uint64_t SH_FLD_NTL_30 = 12845; // 48 -static const uint64_t SH_FLD_NTL_31 = 12846; // 48 -static const uint64_t SH_FLD_NTL_32 = 12847; // 48 -static const uint64_t SH_FLD_NTL_33 = 12848; // 48 -static const uint64_t SH_FLD_NTL_34 = 12849; // 48 -static const uint64_t SH_FLD_NTL_35 = 12850; // 48 -static const uint64_t SH_FLD_NTL_36 = 12851; // 48 -static const uint64_t SH_FLD_NTL_37 = 12852; // 48 -static const uint64_t SH_FLD_NTL_38 = 12853; // 48 -static const uint64_t SH_FLD_NTL_39 = 12854; // 48 -static const uint64_t SH_FLD_NTL_4 = 12855; // 48 -static const uint64_t SH_FLD_NTL_40 = 12856; // 48 -static const uint64_t SH_FLD_NTL_41 = 12857; // 48 -static const uint64_t SH_FLD_NTL_42 = 12858; // 48 -static const uint64_t SH_FLD_NTL_43 = 12859; // 48 -static const uint64_t SH_FLD_NTL_44 = 12860; // 48 -static const uint64_t SH_FLD_NTL_45 = 12861; // 48 -static const uint64_t SH_FLD_NTL_46 = 12862; // 48 -static const uint64_t SH_FLD_NTL_47 = 12863; // 48 -static const uint64_t SH_FLD_NTL_48 = 12864; // 48 -static const uint64_t SH_FLD_NTL_49 = 12865; // 48 -static const uint64_t SH_FLD_NTL_5 = 12866; // 48 -static const uint64_t SH_FLD_NTL_50 = 12867; // 48 -static const uint64_t SH_FLD_NTL_51 = 12868; // 48 -static const uint64_t SH_FLD_NTL_52 = 12869; // 48 -static const uint64_t SH_FLD_NTL_53 = 12870; // 48 -static const uint64_t SH_FLD_NTL_54 = 12871; // 48 -static const uint64_t SH_FLD_NTL_55 = 12872; // 48 -static const uint64_t SH_FLD_NTL_56 = 12873; // 48 -static const uint64_t SH_FLD_NTL_57 = 12874; // 48 -static const uint64_t SH_FLD_NTL_58 = 12875; // 48 -static const uint64_t SH_FLD_NTL_59 = 12876; // 48 -static const uint64_t SH_FLD_NTL_6 = 12877; // 48 -static const uint64_t SH_FLD_NTL_60 = 12878; // 48 -static const uint64_t SH_FLD_NTL_61 = 12879; // 48 -static const uint64_t SH_FLD_NTL_62 = 12880; // 48 -static const uint64_t SH_FLD_NTL_63 = 12881; // 48 -static const uint64_t SH_FLD_NTL_7 = 12882; // 48 -static const uint64_t SH_FLD_NTL_8 = 12883; // 48 -static const uint64_t SH_FLD_NTL_9 = 12884; // 48 -static const uint64_t SH_FLD_NTL_ARRAY_CE = 12885; // 1 -static const uint64_t SH_FLD_NTL_ARRAY_DATA_SUE = 12886; // 1 -static const uint64_t SH_FLD_NTL_ARRAY_DATA_UE = 12887; // 1 -static const uint64_t SH_FLD_NTL_ARRAY_HDR_UE = 12888; // 1 -static const uint64_t SH_FLD_NTL_LMD_POISON = 12889; // 1 -static const uint64_t SH_FLD_NTL_LOGIC_ERR = 12890; // 1 -static const uint64_t SH_FLD_NTL_NVL_CONFIG_ERR = 12891; // 1 -static const uint64_t SH_FLD_NTL_NVL_CRC_ERR = 12892; // 1 -static const uint64_t SH_FLD_NTL_NVL_DATA_PERR = 12893; // 1 -static const uint64_t SH_FLD_NTL_NVL_FLIT_PERR = 12894; // 1 -static const uint64_t SH_FLD_NTL_NVL_PKT_MALFOR = 12895; // 1 -static const uint64_t SH_FLD_NTL_NVL_PKT_UNSUPPORTED = 12896; // 1 -static const uint64_t SH_FLD_NTL_PRI_ERR = 12897; // 1 -static const uint64_t SH_FLD_NTL_RESET = 12898; // 6 -static const uint64_t SH_FLD_NTL_RESET_LEN = 12899; // 6 -static const uint64_t SH_FLD_NTTM_MODE = 12900; // 2 -static const uint64_t SH_FLD_NTTM_RW_DATA_DLY = 12901; // 2 -static const uint64_t SH_FLD_NTTM_RW_DATA_DLY_LEN = 12902; // 2 -static const uint64_t SH_FLD_NULL_MSR_LP = 12903; // 46 -static const uint64_t SH_FLD_NULL_MSR_SIBRC = 12904; // 46 -static const uint64_t SH_FLD_NULL_MSR_SIBRC_LEN = 12905; // 46 -static const uint64_t SH_FLD_NULL_MSR_WE = 12906; // 46 -static const uint64_t SH_FLD_NUM_BLOCKS = 12907; // 12 -static const uint64_t SH_FLD_NUM_BLOCKS_LEN = 12908; // 12 -static const uint64_t SH_FLD_NUM_CLEAN = 12909; // 8 -static const uint64_t SH_FLD_NUM_CLEAN_LEN = 12910; // 8 -static const uint64_t SH_FLD_NUM_CL_ACTIVE = 12911; // 8 -static const uint64_t SH_FLD_NUM_CL_ACTIVE_LEN = 12912; // 8 -static const uint64_t SH_FLD_NUM_HA_RSVD = 12913; // 8 -static const uint64_t SH_FLD_NUM_HA_RSVD_LEN = 12914; // 8 -static const uint64_t SH_FLD_NUM_HA_RSVD_SEL = 12915; // 8 -static const uint64_t SH_FLD_NUM_HA_RSVD_SEL_LEN = 12916; // 8 -static const uint64_t SH_FLD_NUM_HPC_RD_RSVD = 12917; // 8 -static const uint64_t SH_FLD_NUM_HPC_RD_RSVD_LEN = 12918; // 8 -static const uint64_t SH_FLD_NUM_HTM_RSVD = 12919; // 8 -static const uint64_t SH_FLD_NUM_HTM_RSVD_LEN = 12920; // 8 -static const uint64_t SH_FLD_NUM_HTM_RSVD_SEL = 12921; // 8 -static const uint64_t SH_FLD_NUM_HTM_RSVD_SEL_LEN = 12922; // 8 -static const uint64_t SH_FLD_NUM_RMW_BUF = 12923; // 8 -static const uint64_t SH_FLD_NUM_RMW_BUF_LEN = 12924; // 8 -static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD = 12925; // 8 -static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_LEN = 12926; // 8 -static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL = 12927; // 8 -static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN = 12928; // 8 -static const uint64_t SH_FLD_NUM_VALID_SAMPLES = 12929; // 8 -static const uint64_t SH_FLD_NUM_VALID_SAMPLES_LEN = 12930; // 8 -static const uint64_t SH_FLD_NV0_NPU_ENABLED = 12931; // 2 -static const uint64_t SH_FLD_NV1_NPU_ENABLED = 12932; // 2 -static const uint64_t SH_FLD_NV2_NPU_ENABLED = 12933; // 2 -static const uint64_t SH_FLD_NVBE = 12934; // 24 -static const uint64_t SH_FLD_NVDGD0 = 12935; // 3 -static const uint64_t SH_FLD_NVDGD1 = 12936; // 3 -static const uint64_t SH_FLD_NVREQ0 = 12937; // 3 -static const uint64_t SH_FLD_NVREQ1 = 12938; // 3 -static const uint64_t SH_FLD_NVRS0 = 12939; // 3 -static const uint64_t SH_FLD_NVRS1 = 12940; // 3 -static const uint64_t SH_FLD_NV_RESP_RATE1 = 12941; // 12 -static const uint64_t SH_FLD_NV_RESP_RATE1_LEN = 12942; // 12 -static const uint64_t SH_FLD_NV_RESP_RATE2 = 12943; // 12 -static const uint64_t SH_FLD_NV_RESP_RATE2_LEN = 12944; // 12 -static const uint64_t SH_FLD_NX0_LXSTOP_ERR_DET = 12945; // 1 -static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ACTION = 12946; // 1 -static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ENABLE = 12947; // 1 -static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT = 12948; // 1 -static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN = 12949; // 1 -static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_TYPE = 12950; // 1 -static const uint64_t SH_FLD_NXCQ_HANG_SM_ON_ARE = 12951; // 1 -static const uint64_t SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL = 12952; // 1 -static const uint64_t SH_FLD_NXCQ_INJECT_MODE = 12953; // 2 -static const uint64_t SH_FLD_NXCQ_INJECT_MODE_LEN = 12954; // 2 -static const uint64_t SH_FLD_NXCQ_INJECT_TYPE = 12955; // 2 -static const uint64_t SH_FLD_NXCQ_INJECT_TYPE_LEN = 12956; // 2 -static const uint64_t SH_FLD_NXCQ_PBCQ_ARRAY = 12957; // 2 -static const uint64_t SH_FLD_NXCQ_PBCQ_ARRAY_LEN = 12958; // 2 -static const uint64_t SH_FLD_NXCQ_PBCQ_INJECT_ENABLE = 12959; // 2 -static const uint64_t SH_FLD_NXCQ_RNG_INJECT_ACTION = 12960; // 1 -static const uint64_t SH_FLD_NXCQ_RNG_INJECT_ENABLE = 12961; // 1 -static const uint64_t SH_FLD_NXCQ_TRACE_CNTL = 12962; // 2 -static const uint64_t SH_FLD_NXCQ_TRACE_CNTL_LEN = 12963; // 2 -static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_CE_ERRHOLD = 12964; // 2 -static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD = 12965; // 2 -static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_UE_ERRHOLD = 12966; // 2 -static const uint64_t SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD = 12967; // 2 -static const uint64_t SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD = 12968; // 2 -static const uint64_t SH_FLD_NX_DATA_RTAG_PARITY_ERRHOLD = 12969; // 2 -static const uint64_t SH_FLD_NX_FREEZE_MODES = 12970; // 2 -static const uint64_t SH_FLD_NX_FREEZE_MODES_LEN = 12971; // 2 -static const uint64_t SH_FLD_NX_LOCAL_XSTOP = 12972; // 2 -static const uint64_t SH_FLD_NX_RAND_NUM_GEN_LOCK = 12973; // 1 -static const uint64_t SH_FLD_O = 12974; // 1 -static const uint64_t SH_FLD_O2SCMD_A_N_RESERVED_0 = 12975; // 4 -static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_1 = 12976; // 4 -static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 = 12977; // 4 -static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN = 12978; // 4 -static const uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4 = 12979; // 4 -static const uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4_LEN = 12980; // 4 -static const uint64_t SH_FLD_O2SST_A_N_RESERVED_6 = 12981; // 4 -static const uint64_t SH_FLD_O2S_BRIDGE_ENABLE_A_N = 12982; // 4 -static const uint64_t SH_FLD_O2S_CLEAR_STICKY_BITS_A_N = 12983; // 4 -static const uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N = 12984; // 4 -static const uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN = 12985; // 4 -static const uint64_t SH_FLD_O2S_CPHA_A_N = 12986; // 4 -static const uint64_t SH_FLD_O2S_CPOL_A_N = 12987; // 4 -static const uint64_t SH_FLD_O2S_FRAME_SIZE_A_N = 12988; // 4 -static const uint64_t SH_FLD_O2S_FRAME_SIZE_A_N_LEN = 12989; // 4 -static const uint64_t SH_FLD_O2S_FSM_ERR_A_N = 12990; // 4 -static const uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N = 12991; // 4 -static const uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN = 12992; // 4 -static const uint64_t SH_FLD_O2S_IN_COUNT1_A_N = 12993; // 4 -static const uint64_t SH_FLD_O2S_IN_COUNT1_A_N_LEN = 12994; // 4 -static const uint64_t SH_FLD_O2S_IN_COUNT2_A_N = 12995; // 4 -static const uint64_t SH_FLD_O2S_IN_COUNT2_A_N_LEN = 12996; // 4 -static const uint64_t SH_FLD_O2S_IN_DELAY1_A_N = 12997; // 4 -static const uint64_t SH_FLD_O2S_IN_DELAY1_A_N_LEN = 12998; // 4 -static const uint64_t SH_FLD_O2S_IN_DELAY2_A_N = 12999; // 4 -static const uint64_t SH_FLD_O2S_IN_DELAY2_A_N_LEN = 13000; // 4 -static const uint64_t SH_FLD_O2S_NR_OF_FRAMES_A_N = 13001; // 4 -static const uint64_t SH_FLD_O2S_ONGOING_A_N = 13002; // 4 -static const uint64_t SH_FLD_O2S_OUT_COUNT1_A_N = 13003; // 4 -static const uint64_t SH_FLD_O2S_OUT_COUNT1_A_N_LEN = 13004; // 4 -static const uint64_t SH_FLD_O2S_OUT_COUNT2_A_N = 13005; // 4 -static const uint64_t SH_FLD_O2S_OUT_COUNT2_A_N_LEN = 13006; // 4 -static const uint64_t SH_FLD_O2S_RDATA_A_N = 13007; // 4 -static const uint64_t SH_FLD_O2S_RDATA_A_N_LEN = 13008; // 4 -static const uint64_t SH_FLD_O2S_WDATA_A_N = 13009; // 4 -static const uint64_t SH_FLD_O2S_WDATA_A_N_LEN = 13010; // 4 -static const uint64_t SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 13011; // 4 -static const uint64_t SH_FLD_OBUF_ABANK = 13012; // 3 -static const uint64_t SH_FLD_OBUF_ABANK_LEN = 13013; // 3 -static const uint64_t SH_FLD_OBUF_AIDX = 13014; // 3 -static const uint64_t SH_FLD_OBUF_AIDX_LEN = 13015; // 3 -static const uint64_t SH_FLD_OBUF_RSRC = 13016; // 3 -static const uint64_t SH_FLD_OBUF_RSRC_LEN = 13017; // 3 -static const uint64_t SH_FLD_OBUF_WSRC = 13018; // 3 -static const uint64_t SH_FLD_OBUF_WSRC_LEN = 13019; // 3 -static const uint64_t SH_FLD_OBWR_MASK = 13020; // 3 -static const uint64_t SH_FLD_OBWR_MASK_LEN = 13021; // 3 -static const uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY = 13022; // 1 -static const uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY_MASK = 13023; // 1 -static const uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR = 13024; // 1 -static const uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR_MASK = 13025; // 1 -static const uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT = 13026; // 1 -static const uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT_MASK = 13027; // 1 -static const uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR = 13028; // 1 -static const uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR_MASK = 13029; // 1 -static const uint64_t SH_FLD_OCB_ERROR = 13030; // 1 -static const uint64_t SH_FLD_OCB_ERROR_MASK = 13031; // 1 -static const uint64_t SH_FLD_OCB_IDC0_ERROR = 13032; // 1 -static const uint64_t SH_FLD_OCB_IDC0_ERROR_MASK = 13033; // 1 -static const uint64_t SH_FLD_OCB_IDC1_ERROR = 13034; // 1 -static const uint64_t SH_FLD_OCB_IDC1_ERROR_MASK = 13035; // 1 -static const uint64_t SH_FLD_OCB_IDC2_ERROR = 13036; // 1 -static const uint64_t SH_FLD_OCB_IDC2_ERROR_MASK = 13037; // 1 -static const uint64_t SH_FLD_OCB_IDC3_ERROR = 13038; // 1 -static const uint64_t SH_FLD_OCB_IDC3_ERROR_MASK = 13039; // 1 -static const uint64_t SH_FLD_OCB_OCISLV_ERR = 13040; // 1 -static const uint64_t SH_FLD_OCB_OCISLV_ERR_LEN = 13041; // 1 -static const uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR = 13042; // 1 -static const uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR_MASK = 13043; // 1 -static const uint64_t SH_FLD_OCC_ACTION_SET = 13044; // 1 -static const uint64_t SH_FLD_OCC_ACTION_SET_LEN = 13045; // 1 -static const uint64_t SH_FLD_OCC_ERROR = 13046; // 1 -static const uint64_t SH_FLD_OCC_FLAGS = 13047; // 1 -static const uint64_t SH_FLD_OCC_FLAGS_LEN = 13048; // 1 -static const uint64_t SH_FLD_OCC_HEARTBEAT_COUNT = 13049; // 7 -static const uint64_t SH_FLD_OCC_HEARTBEAT_COUNT_LEN = 13050; // 7 -static const uint64_t SH_FLD_OCC_HEARTBEAT_EN = 13051; // 1 -static const uint64_t SH_FLD_OCC_HEARTBEAT_ENABLE = 13052; // 6 -static const uint64_t SH_FLD_OCC_HEARTBEAT_LOSS = 13053; // 6 -static const uint64_t SH_FLD_OCC_HEARTBEAT_LOST = 13054; // 12 -static const uint64_t SH_FLD_OCC_MALF_ALERT = 13055; // 1 -static const uint64_t SH_FLD_OCC_SCRATCH_N = 13056; // 3 -static const uint64_t SH_FLD_OCC_SCRATCH_N_LEN = 13057; // 3 -static const uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR = 13058; // 1 -static const uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN = 13059; // 1 -static const uint64_t SH_FLD_OCC_SPECIAL_WKUP = 13060; // 30 -static const uint64_t SH_FLD_OCC_STRM0_PULL = 13061; // 1 -static const uint64_t SH_FLD_OCC_STRM0_PUSH = 13062; // 1 -static const uint64_t SH_FLD_OCC_STRM1_PULL = 13063; // 1 -static const uint64_t SH_FLD_OCC_STRM1_PUSH = 13064; // 1 -static const uint64_t SH_FLD_OCC_STRM2_PULL = 13065; // 1 -static const uint64_t SH_FLD_OCC_STRM2_PUSH = 13066; // 1 -static const uint64_t SH_FLD_OCC_STRM3_PULL = 13067; // 1 -static const uint64_t SH_FLD_OCC_STRM3_PUSH = 13068; // 1 -static const uint64_t SH_FLD_OCC_TIMER0 = 13069; // 1 -static const uint64_t SH_FLD_OCC_TIMER1 = 13070; // 1 -static const uint64_t SH_FLD_OCC_TRACE_MUX_SEL = 13071; // 1 -static const uint64_t SH_FLD_OCC_TRACE_MUX_SEL_LEN = 13072; // 1 -static const uint64_t SH_FLD_OCICFG_RESERVED_20 = 13073; // 1 -static const uint64_t SH_FLD_OCICFG_RESERVED_23 = 13074; // 1 -static const uint64_t SH_FLD_OCISLV_FAIRNESS_MASK = 13075; // 1 -static const uint64_t SH_FLD_OCISLV_FAIRNESS_MASK_LEN = 13076; // 1 -static const uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV = 13077; // 1 -static const uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV_LEN = 13078; // 1 -static const uint64_t SH_FLD_OCI_APAR_ERR = 13079; // 1 -static const uint64_t SH_FLD_OCI_APAR_ERR_MASK = 13080; // 1 -static const uint64_t SH_FLD_OCI_ARB_RESET = 13081; // 1 -static const uint64_t SH_FLD_OCI_BAD_REG_ADDR = 13082; // 1 -static const uint64_t SH_FLD_OCI_BAD_REG_ADDR_MASK = 13083; // 1 -static const uint64_t SH_FLD_OCI_ERR_INJ_CE_UE = 13084; // 1 -static const uint64_t SH_FLD_OCI_ERR_INJ_DCU = 13085; // 1 -static const uint64_t SH_FLD_OCI_ERR_INJ_ICU = 13086; // 1 -static const uint64_t SH_FLD_OCI_ERR_INJ_SINGL_CONT = 13087; // 1 -static const uint64_t SH_FLD_OCI_HI_BUS_MODE = 13088; // 1 -static const uint64_t SH_FLD_OCI_M0_FLCK = 13089; // 1 -static const uint64_t SH_FLD_OCI_M0_OEAR_LOCK = 13090; // 1 -static const uint64_t SH_FLD_OCI_M0_RW_STATUS = 13091; // 1 -static const uint64_t SH_FLD_OCI_M0_TIMEOUT_ERROR = 13092; // 1 -static const uint64_t SH_FLD_OCI_M1_FLCK = 13093; // 1 -static const uint64_t SH_FLD_OCI_M1_OEAR_LOCK = 13094; // 1 -static const uint64_t SH_FLD_OCI_M1_RW_STATUS = 13095; // 1 -static const uint64_t SH_FLD_OCI_M1_TIMEOUT_ERROR = 13096; // 1 -static const uint64_t SH_FLD_OCI_M2_FLCK = 13097; // 1 -static const uint64_t SH_FLD_OCI_M2_OEAR_LOCK = 13098; // 1 -static const uint64_t SH_FLD_OCI_M2_RW_STATUS = 13099; // 1 -static const uint64_t SH_FLD_OCI_M2_TIMEOUT_ERROR = 13100; // 1 -static const uint64_t SH_FLD_OCI_M3_FLCK = 13101; // 1 -static const uint64_t SH_FLD_OCI_M3_OEAR_LOCK = 13102; // 1 -static const uint64_t SH_FLD_OCI_M3_RW_STATUS = 13103; // 1 -static const uint64_t SH_FLD_OCI_M3_TIMEOUT_ERROR = 13104; // 1 -static const uint64_t SH_FLD_OCI_M4_FLCK = 13105; // 1 -static const uint64_t SH_FLD_OCI_M4_OEAR_LOCK = 13106; // 1 -static const uint64_t SH_FLD_OCI_M4_RW_STATUS = 13107; // 1 -static const uint64_t SH_FLD_OCI_M4_TIMEOUT_ERROR = 13108; // 1 -static const uint64_t SH_FLD_OCI_M5_FLCK = 13109; // 1 -static const uint64_t SH_FLD_OCI_M5_OEAR_LOCK = 13110; // 1 -static const uint64_t SH_FLD_OCI_M5_RW_STATUS = 13111; // 1 -static const uint64_t SH_FLD_OCI_M5_TIMEOUT_ERROR = 13112; // 1 -static const uint64_t SH_FLD_OCI_M6_FLCK = 13113; // 1 -static const uint64_t SH_FLD_OCI_M6_OEAR_LOCK = 13114; // 1 -static const uint64_t SH_FLD_OCI_M6_RW_STATUS = 13115; // 1 -static const uint64_t SH_FLD_OCI_M6_TIMEOUT_ERROR = 13116; // 1 -static const uint64_t SH_FLD_OCI_M7_FLCK = 13117; // 1 -static const uint64_t SH_FLD_OCI_M7_OEAR_LOCK = 13118; // 1 -static const uint64_t SH_FLD_OCI_M7_RW_STATUS = 13119; // 1 -static const uint64_t SH_FLD_OCI_M7_TIMEOUT_ERROR = 13120; // 1 -static const uint64_t SH_FLD_OCI_MARKER_SPACE = 13121; // 1 -static const uint64_t SH_FLD_OCI_MARKER_SPACE_LEN = 13122; // 1 -static const uint64_t SH_FLD_OCI_PRIORITY_MODE = 13123; // 1 -static const uint64_t SH_FLD_OCI_PRIORITY_ORDER = 13124; // 1 -static const uint64_t SH_FLD_OCI_PRIORITY_ORDER_LEN = 13125; // 1 -static const uint64_t SH_FLD_OCI_READ_DATA_PARITY = 13126; // 4 -static const uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL = 13127; // 1 -static const uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN = 13128; // 1 -static const uint64_t SH_FLD_OCI_REGION = 13129; // 4 -static const uint64_t SH_FLD_OCI_REGION_LEN = 13130; // 4 -static const uint64_t SH_FLD_OCI_SLAVE_ERROR = 13131; // 4 -static const uint64_t SH_FLD_OCI_SLAVE_INIT = 13132; // 1 -static const uint64_t SH_FLD_OCI_SLAVE_INIT_MASK = 13133; // 1 -static const uint64_t SH_FLD_OCI_TIMEOUT = 13134; // 4 -static const uint64_t SH_FLD_OCI_TIMEOUT_ADDR = 13135; // 1 -static const uint64_t SH_FLD_OCI_TIMEOUT_ADDR_LEN = 13136; // 1 -static const uint64_t SH_FLD_OCI_TRACE_MUX_SEL = 13137; // 1 -static const uint64_t SH_FLD_OCI_TRACE_MUX_SEL_LEN = 13138; // 1 -static const uint64_t SH_FLD_OCI_WRITE_PIPELINE_CONTROL = 13139; // 1 -static const uint64_t SH_FLD_OCI_WRPAR_ERR = 13140; // 1 -static const uint64_t SH_FLD_OCI_WRPAR_ERR_MASK = 13141; // 1 -static const uint64_t SH_FLD_OCR_DBG_HALT = 13142; // 1 -static const uint64_t SH_FLD_OCTANT_SELECT = 13143; // 2 -static const uint64_t SH_FLD_OCTANT_SELECT_LEN = 13144; // 2 -static const uint64_t SH_FLD_OFFSET = 13145; // 15 -static const uint64_t SH_FLD_OFFSET_LEN = 13146; // 15 -static const uint64_t SH_FLD_OFF_INIT_CFG = 13147; // 6 -static const uint64_t SH_FLD_OFF_INIT_CFG_LEN = 13148; // 6 -static const uint64_t SH_FLD_OFF_INIT_TIMEOUT = 13149; // 6 -static const uint64_t SH_FLD_OFF_INIT_TIMEOUT_LEN = 13150; // 6 -static const uint64_t SH_FLD_OFF_RECAL_CFG = 13151; // 6 -static const uint64_t SH_FLD_OFF_RECAL_CFG_LEN = 13152; // 6 -static const uint64_t SH_FLD_OFF_RECAL_TIMEOUT = 13153; // 6 -static const uint64_t SH_FLD_OFF_RECAL_TIMEOUT_LEN = 13154; // 6 -static const uint64_t SH_FLD_OJCFG_DBG_HALT = 13155; // 1 -static const uint64_t SH_FLD_OJCFG_JTAG_SRC_SEL = 13156; // 1 -static const uint64_t SH_FLD_OJCFG_JTAG_TRST_B = 13157; // 1 -static const uint64_t SH_FLD_OJCFG_RUN_TCK = 13158; // 1 -static const uint64_t SH_FLD_OJCFG_TCK_WIDTH = 13159; // 1 -static const uint64_t SH_FLD_OJCFG_TCK_WIDTH_LEN = 13160; // 1 -static const uint64_t SH_FLD_OJIC_DO_DR = 13161; // 1 -static const uint64_t SH_FLD_OJIC_DO_IR = 13162; // 1 -static const uint64_t SH_FLD_OJIC_DO_TAP_RESET = 13163; // 1 -static const uint64_t SH_FLD_OJIC_JTAG_INSTR = 13164; // 1 -static const uint64_t SH_FLD_OJIC_JTAG_INSTR_LEN = 13165; // 1 -static const uint64_t SH_FLD_OJIC_WR_VALID = 13166; // 1 -static const uint64_t SH_FLD_OJSTAT_FSM_ERROR = 13167; // 1 -static const uint64_t SH_FLD_OJSTAT_INPROG_WR_ERR = 13168; // 1 -static const uint64_t SH_FLD_OJSTAT_IR_DR_EQ0_ERR = 13169; // 1 -static const uint64_t SH_FLD_OJSTAT_JTAG_INPROG = 13170; // 1 -static const uint64_t SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR = 13171; // 1 -static const uint64_t SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR = 13172; // 1 -static const uint64_t SH_FLD_OJSTAT_TRST_B_EQ0_ERR = 13173; // 1 -static const uint64_t SH_FLD_ONESHOT0 = 13174; // 24 -static const uint64_t SH_FLD_ONESHOT1 = 13175; // 24 -static const uint64_t SH_FLD_ONE_PPC = 13176; // 24 -static const uint64_t SH_FLD_ONGOING = 13177; // 1 -static const uint64_t SH_FLD_ONL = 13178; // 96 -static const uint64_t SH_FLD_OOB_MUX = 13179; // 3 -static const uint64_t SH_FLD_OPB_ERROR = 13180; // 4 -static const uint64_t SH_FLD_OPB_MASTER_HANG_TIMEOUT = 13181; // 4 -static const uint64_t SH_FLD_OPB_PARITY_ERROR = 13182; // 3 -static const uint64_t SH_FLD_OPB_TIMEOUT = 13183; // 4 -static const uint64_t SH_FLD_OPCG_IP = 13184; // 43 -static const uint64_t SH_FLD_OPCODE = 13185; // 1 -static const uint64_t SH_FLD_OPCODE_LEN = 13186; // 1 -static const uint64_t SH_FLD_OPER = 13187; // 1 -static const uint64_t SH_FLD_OPER_LEN = 13188; // 1 -static const uint64_t SH_FLD_OPTION_PREVENT_SBE_START = 13189; // 1 -static const uint64_t SH_FLD_OPTION_SKIP_SCAN0_CLOCKSTART = 13190; // 1 -static const uint64_t SH_FLD_OPT_UNUSED1 = 13191; // 2 -static const uint64_t SH_FLD_OPT_UNUSED1_LEN = 13192; // 2 -static const uint64_t SH_FLD_OPT_UNUSED2 = 13193; // 2 -static const uint64_t SH_FLD_OPT_UNUSED3 = 13194; // 2 -static const uint64_t SH_FLD_OPT_UNUSED3_LEN = 13195; // 2 -static const uint64_t SH_FLD_OPT_UNUSED4 = 13196; // 2 -static const uint64_t SH_FLD_OPT_UNUSED5 = 13197; // 2 -static const uint64_t SH_FLD_OPT_UNUSED5_LEN = 13198; // 2 -static const uint64_t SH_FLD_OSC = 13199; // 4 -static const uint64_t SH_FLD_OSCILLATOR = 13200; // 1 -static const uint64_t SH_FLD_OSCILLATOR_LEN = 13201; // 1 -static const uint64_t SH_FLD_OSCSWITCH_CNTL0_DC = 13202; // 3 -static const uint64_t SH_FLD_OSCSWITCH_CNTL0_DC_LEN = 13203; // 3 -static const uint64_t SH_FLD_OSCSWITCH_CNTL1_DC = 13204; // 3 -static const uint64_t SH_FLD_OSCSWITCH_CNTL1_DC_LEN = 13205; // 3 -static const uint64_t SH_FLD_OSCSWITCH_INTERRUPT = 13206; // 4 -static const uint64_t SH_FLD_OSC_LEN = 13207; // 4 -static const uint64_t SH_FLD_OSC_SWITCH = 13208; // 4 -static const uint64_t SH_FLD_OS_STATUS_DISABLE_A_N = 13209; // 96 -static const uint64_t SH_FLD_OTHER_SCOM_SAT = 13210; // 1 -static const uint64_t SH_FLD_OTP = 13211; // 1 -static const uint64_t SH_FLD_OTP_LEN = 13212; // 1 -static const uint64_t SH_FLD_OTR_SPECIAL_WKUP = 13213; // 30 -static const uint64_t SH_FLD_OUT = 13214; // 1 -static const uint64_t SH_FLD_OUTER_LOOP_CNT = 13215; // 8 -static const uint64_t SH_FLD_OUTER_LOOP_CNT_LEN = 13216; // 8 -static const uint64_t SH_FLD_OUTWR_INRD_ECC_CE = 13217; // 1 -static const uint64_t SH_FLD_OUTWR_INRD_ECC_SUE = 13218; // 1 -static const uint64_t SH_FLD_OUTWR_INRD_ECC_UE = 13219; // 1 -static const uint64_t SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR = 13220; // 6 -static const uint64_t SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR = 13221; // 6 -static const uint64_t SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR = 13222; // 6 -static const uint64_t SH_FLD_OUT_COUNT1 = 13223; // 1 -static const uint64_t SH_FLD_OUT_COUNT1_LEN = 13224; // 1 -static const uint64_t SH_FLD_OUT_COUNT2 = 13225; // 1 -static const uint64_t SH_FLD_OUT_COUNT2_LEN = 13226; // 1 -static const uint64_t SH_FLD_OUT_LEN = 13227; // 1 -static const uint64_t SH_FLD_OUT_RRB_SOURCED_ERROR = 13228; // 6 -static const uint64_t SH_FLD_OVERFLOW_CHECKSTOP = 13229; // 2 -static const uint64_t SH_FLD_OVERFLOW_ERR = 13230; // 43 -static const uint64_t SH_FLD_OVERFLOW_ERROR = 13231; // 2 -static const uint64_t SH_FLD_OVERFLOW_MASK = 13232; // 43 -static const uint64_t SH_FLD_OVERRIDE_EN = 13233; // 24 -static const uint64_t SH_FLD_OVERRIDE_PBINIT_ERR_CMD = 13234; // 1 -static const uint64_t SH_FLD_OVERRIDE_PBINIT_HTM_CMD = 13235; // 1 -static const uint64_t SH_FLD_OVERRIDE_PBINIT_TOD_CMD = 13236; // 1 -static const uint64_t SH_FLD_OVERRIDE_PBINIT_TRACE_CMD = 13237; // 1 -static const uint64_t SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD = 13238; // 1 -static const uint64_t SH_FLD_OVERRUN = 13239; // 8 -static const uint64_t SH_FLD_OVER_OR_UNDERRUN_ERR = 13240; // 1 -static const uint64_t SH_FLD_OVR_PM = 13241; // 1 -static const uint64_t SH_FLD_OWN_ID_THIS_SLAVE = 13242; // 2 -static const uint64_t SH_FLD_OWN_ID_THIS_SLAVE_LEN = 13243; // 2 -static const uint64_t SH_FLD_P0_BACK2BACK_MODE_ENA = 13244; // 1 -static const uint64_t SH_FLD_P0_BACK2BACK_MODE_ENA_LEN = 13245; // 1 -static const uint64_t SH_FLD_P0_IS_IDLE = 13246; // 4 -static const uint64_t SH_FLD_P1_IS_IDLE = 13247; // 4 -static const uint64_t SH_FLD_P9_TO_P9_MODE = 13248; // 6 -static const uint64_t SH_FLD_PACE = 13249; // 2 -static const uint64_t SH_FLD_PACE_LEN = 13250; // 2 -static const uint64_t SH_FLD_PACE_RATE = 13251; // 1 -static const uint64_t SH_FLD_PACE_RATE_LEN = 13252; // 1 -static const uint64_t SH_FLD_PACING_ALLOW_0 = 13253; // 2 -static const uint64_t SH_FLD_PACING_ALLOW_1 = 13254; // 1 -static const uint64_t SH_FLD_PACING_ALLOW_2 = 13255; // 1 -static const uint64_t SH_FLD_PACING_ALLOW_3 = 13256; // 1 -static const uint64_t SH_FLD_PACKET_DELAY_LIMIT = 13257; // 5 -static const uint64_t SH_FLD_PACKET_DELAY_LIMIT_LEN = 13258; // 5 -static const uint64_t SH_FLD_PAGE_OFFSET_CFG = 13259; // 1 -static const uint64_t SH_FLD_PAGE_OFFSET_CFG_LEN = 13260; // 1 -static const uint64_t SH_FLD_PAGE_SIZE_64K = 13261; // 4 -static const uint64_t SH_FLD_PAGE_SIZE_64K_PC = 13262; // 1 -static const uint64_t SH_FLD_PAGE_SIZE_64K_VC = 13263; // 1 -static const uint64_t SH_FLD_PAIR0_QUA = 13264; // 8 -static const uint64_t SH_FLD_PAIR0_QUA_LEN = 13265; // 8 -static const uint64_t SH_FLD_PAIR0_QUA_V = 13266; // 8 -static const uint64_t SH_FLD_PAIR0_TER = 13267; // 8 -static const uint64_t SH_FLD_PAIR0_TER_LEN = 13268; // 8 -static const uint64_t SH_FLD_PAIR0_TER_V = 13269; // 8 -static const uint64_t SH_FLD_PAIR1_PRI = 13270; // 8 -static const uint64_t SH_FLD_PAIR1_PRI_LEN = 13271; // 8 -static const uint64_t SH_FLD_PAIR1_PRI_V = 13272; // 8 -static const uint64_t SH_FLD_PAIR1_QUA = 13273; // 8 -static const uint64_t SH_FLD_PAIR1_QUA_LEN = 13274; // 8 -static const uint64_t SH_FLD_PAIR1_QUA_V = 13275; // 8 -static const uint64_t SH_FLD_PAIR1_SEC = 13276; // 8 -static const uint64_t SH_FLD_PAIR1_SEC_LEN = 13277; // 8 -static const uint64_t SH_FLD_PAIR1_SEC_V = 13278; // 8 -static const uint64_t SH_FLD_PAIR1_TER = 13279; // 8 -static const uint64_t SH_FLD_PAIR1_TER_LEN = 13280; // 8 -static const uint64_t SH_FLD_PAIR1_TER_V = 13281; // 8 -static const uint64_t SH_FLD_PAIR2_PRI = 13282; // 8 -static const uint64_t SH_FLD_PAIR2_PRI_LEN = 13283; // 8 -static const uint64_t SH_FLD_PAIR2_PRI_V = 13284; // 8 -static const uint64_t SH_FLD_PAIR2_QUA = 13285; // 8 -static const uint64_t SH_FLD_PAIR2_QUA_LEN = 13286; // 8 -static const uint64_t SH_FLD_PAIR2_QUA_V = 13287; // 8 -static const uint64_t SH_FLD_PAIR2_SEC = 13288; // 8 -static const uint64_t SH_FLD_PAIR2_SEC_LEN = 13289; // 8 -static const uint64_t SH_FLD_PAIR2_SEC_V = 13290; // 8 -static const uint64_t SH_FLD_PAIR2_TER = 13291; // 8 -static const uint64_t SH_FLD_PAIR2_TER_LEN = 13292; // 8 -static const uint64_t SH_FLD_PAIR2_TER_V = 13293; // 8 -static const uint64_t SH_FLD_PAIR3_PRI = 13294; // 8 -static const uint64_t SH_FLD_PAIR3_PRI_LEN = 13295; // 8 -static const uint64_t SH_FLD_PAIR3_PRI_V = 13296; // 8 -static const uint64_t SH_FLD_PAIR3_SEC = 13297; // 8 -static const uint64_t SH_FLD_PAIR3_SEC_LEN = 13298; // 8 -static const uint64_t SH_FLD_PAIR3_SEC_V = 13299; // 8 -static const uint64_t SH_FLD_PAPR_INBOUND_INJECT_ERROR = 13300; // 6 -static const uint64_t SH_FLD_PAPR_OUTBOUND_INJECT_ERROR = 13301; // 6 -static const uint64_t SH_FLD_PARALLEL_ADDR_INVALID = 13302; // 43 -static const uint64_t SH_FLD_PARALLEL_READ_NVLD = 13303; // 43 -static const uint64_t SH_FLD_PARALLEL_WRITE_NVLD = 13304; // 43 -static const uint64_t SH_FLD_PARANOIA_TEST_ENABLE_CHANGE = 13305; // 43 -static const uint64_t SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE = 13306; // 43 -static const uint64_t SH_FLD_PARITY = 13307; // 45 -static const uint64_t SH_FLD_PARITY_CHECK = 13308; // 1 -static const uint64_t SH_FLD_PARITY_ERR = 13309; // 4 -static const uint64_t SH_FLD_PARITY_ERR2 = 13310; // 3 -static const uint64_t SH_FLD_PARITY_ERROR = 13311; // 51 -static const uint64_t SH_FLD_PARITY_ERROR_SUE_ENA = 13312; // 6 -static const uint64_t SH_FLD_PARITY_ON_INTERFACE_MACHINE = 13313; // 43 -static const uint64_t SH_FLD_PARITY_ON_P2S_MACHINE = 13314; // 43 -static const uint64_t SH_FLD_PARSER00_ATTN = 13315; // 4 -static const uint64_t SH_FLD_PARSER01_ATTN = 13316; // 4 -static const uint64_t SH_FLD_PARSER02_ATTN = 13317; // 4 -static const uint64_t SH_FLD_PARSER03_ATTN = 13318; // 4 -static const uint64_t SH_FLD_PARSER04_ATTN = 13319; // 4 -static const uint64_t SH_FLD_PARSER05_ATTN = 13320; // 4 -static const uint64_t SH_FLD_PARSER06_ATTN = 13321; // 2 -static const uint64_t SH_FLD_PARSER07_ATTN = 13322; // 2 -static const uint64_t SH_FLD_PART_0 = 13323; // 2 -static const uint64_t SH_FLD_PART_0_LEN = 13324; // 2 -static const uint64_t SH_FLD_PART_1 = 13325; // 2 -static const uint64_t SH_FLD_PART_10 = 13326; // 2 -static const uint64_t SH_FLD_PART_10_LEN = 13327; // 2 -static const uint64_t SH_FLD_PART_11 = 13328; // 2 -static const uint64_t SH_FLD_PART_11_LEN = 13329; // 2 -static const uint64_t SH_FLD_PART_12 = 13330; // 2 -static const uint64_t SH_FLD_PART_12_LEN = 13331; // 2 -static const uint64_t SH_FLD_PART_13 = 13332; // 2 -static const uint64_t SH_FLD_PART_13_LEN = 13333; // 2 -static const uint64_t SH_FLD_PART_14 = 13334; // 2 -static const uint64_t SH_FLD_PART_14_LEN = 13335; // 2 -static const uint64_t SH_FLD_PART_15 = 13336; // 2 -static const uint64_t SH_FLD_PART_15_LEN = 13337; // 2 -static const uint64_t SH_FLD_PART_16 = 13338; // 2 -static const uint64_t SH_FLD_PART_16_LEN = 13339; // 2 -static const uint64_t SH_FLD_PART_17 = 13340; // 2 -static const uint64_t SH_FLD_PART_17_LEN = 13341; // 2 -static const uint64_t SH_FLD_PART_18 = 13342; // 2 -static const uint64_t SH_FLD_PART_18_LEN = 13343; // 2 -static const uint64_t SH_FLD_PART_19 = 13344; // 2 -static const uint64_t SH_FLD_PART_19_LEN = 13345; // 2 -static const uint64_t SH_FLD_PART_1_LEN = 13346; // 2 -static const uint64_t SH_FLD_PART_2 = 13347; // 2 -static const uint64_t SH_FLD_PART_20 = 13348; // 2 -static const uint64_t SH_FLD_PART_20_LEN = 13349; // 2 -static const uint64_t SH_FLD_PART_21 = 13350; // 2 -static const uint64_t SH_FLD_PART_21_LEN = 13351; // 2 -static const uint64_t SH_FLD_PART_22 = 13352; // 2 -static const uint64_t SH_FLD_PART_22_LEN = 13353; // 2 -static const uint64_t SH_FLD_PART_23 = 13354; // 2 -static const uint64_t SH_FLD_PART_23_LEN = 13355; // 2 -static const uint64_t SH_FLD_PART_24 = 13356; // 2 -static const uint64_t SH_FLD_PART_24_LEN = 13357; // 2 -static const uint64_t SH_FLD_PART_25 = 13358; // 2 -static const uint64_t SH_FLD_PART_25_LEN = 13359; // 2 -static const uint64_t SH_FLD_PART_26 = 13360; // 2 -static const uint64_t SH_FLD_PART_26_LEN = 13361; // 2 -static const uint64_t SH_FLD_PART_27 = 13362; // 2 -static const uint64_t SH_FLD_PART_27_LEN = 13363; // 2 -static const uint64_t SH_FLD_PART_28 = 13364; // 2 -static const uint64_t SH_FLD_PART_28_LEN = 13365; // 2 -static const uint64_t SH_FLD_PART_29 = 13366; // 2 -static const uint64_t SH_FLD_PART_29_LEN = 13367; // 2 -static const uint64_t SH_FLD_PART_2_LEN = 13368; // 2 -static const uint64_t SH_FLD_PART_3 = 13369; // 2 -static const uint64_t SH_FLD_PART_30 = 13370; // 2 -static const uint64_t SH_FLD_PART_30_LEN = 13371; // 2 -static const uint64_t SH_FLD_PART_31 = 13372; // 2 -static const uint64_t SH_FLD_PART_31_LEN = 13373; // 2 -static const uint64_t SH_FLD_PART_32 = 13374; // 2 -static const uint64_t SH_FLD_PART_32_LEN = 13375; // 2 -static const uint64_t SH_FLD_PART_33 = 13376; // 2 -static const uint64_t SH_FLD_PART_33_LEN = 13377; // 2 -static const uint64_t SH_FLD_PART_34 = 13378; // 2 -static const uint64_t SH_FLD_PART_34_LEN = 13379; // 2 -static const uint64_t SH_FLD_PART_35 = 13380; // 2 -static const uint64_t SH_FLD_PART_35_LEN = 13381; // 2 -static const uint64_t SH_FLD_PART_36 = 13382; // 2 -static const uint64_t SH_FLD_PART_36_LEN = 13383; // 2 -static const uint64_t SH_FLD_PART_37 = 13384; // 2 -static const uint64_t SH_FLD_PART_37_LEN = 13385; // 2 -static const uint64_t SH_FLD_PART_38 = 13386; // 2 -static const uint64_t SH_FLD_PART_38_LEN = 13387; // 2 -static const uint64_t SH_FLD_PART_39 = 13388; // 2 -static const uint64_t SH_FLD_PART_39_LEN = 13389; // 2 -static const uint64_t SH_FLD_PART_3_LEN = 13390; // 2 -static const uint64_t SH_FLD_PART_4 = 13391; // 2 -static const uint64_t SH_FLD_PART_40 = 13392; // 2 -static const uint64_t SH_FLD_PART_40_LEN = 13393; // 2 -static const uint64_t SH_FLD_PART_41 = 13394; // 2 -static const uint64_t SH_FLD_PART_41_LEN = 13395; // 2 -static const uint64_t SH_FLD_PART_42 = 13396; // 2 -static const uint64_t SH_FLD_PART_42_LEN = 13397; // 2 -static const uint64_t SH_FLD_PART_43 = 13398; // 2 -static const uint64_t SH_FLD_PART_43_LEN = 13399; // 2 -static const uint64_t SH_FLD_PART_44 = 13400; // 2 -static const uint64_t SH_FLD_PART_44_LEN = 13401; // 2 -static const uint64_t SH_FLD_PART_45 = 13402; // 2 -static const uint64_t SH_FLD_PART_45_LEN = 13403; // 2 -static const uint64_t SH_FLD_PART_46 = 13404; // 2 -static const uint64_t SH_FLD_PART_46_LEN = 13405; // 2 -static const uint64_t SH_FLD_PART_47 = 13406; // 2 -static const uint64_t SH_FLD_PART_47_LEN = 13407; // 2 -static const uint64_t SH_FLD_PART_48 = 13408; // 2 -static const uint64_t SH_FLD_PART_48_LEN = 13409; // 2 -static const uint64_t SH_FLD_PART_49 = 13410; // 2 -static const uint64_t SH_FLD_PART_49_LEN = 13411; // 2 -static const uint64_t SH_FLD_PART_4_LEN = 13412; // 2 -static const uint64_t SH_FLD_PART_5 = 13413; // 2 -static const uint64_t SH_FLD_PART_50 = 13414; // 2 -static const uint64_t SH_FLD_PART_50_LEN = 13415; // 2 -static const uint64_t SH_FLD_PART_51 = 13416; // 2 -static const uint64_t SH_FLD_PART_51_LEN = 13417; // 2 -static const uint64_t SH_FLD_PART_52 = 13418; // 2 -static const uint64_t SH_FLD_PART_52_LEN = 13419; // 2 -static const uint64_t SH_FLD_PART_53 = 13420; // 2 -static const uint64_t SH_FLD_PART_53_LEN = 13421; // 2 -static const uint64_t SH_FLD_PART_54 = 13422; // 2 -static const uint64_t SH_FLD_PART_54_LEN = 13423; // 2 -static const uint64_t SH_FLD_PART_55 = 13424; // 2 -static const uint64_t SH_FLD_PART_55_LEN = 13425; // 2 -static const uint64_t SH_FLD_PART_56 = 13426; // 2 -static const uint64_t SH_FLD_PART_56_LEN = 13427; // 2 -static const uint64_t SH_FLD_PART_57 = 13428; // 2 -static const uint64_t SH_FLD_PART_57_LEN = 13429; // 2 -static const uint64_t SH_FLD_PART_58 = 13430; // 2 -static const uint64_t SH_FLD_PART_58_LEN = 13431; // 2 -static const uint64_t SH_FLD_PART_59 = 13432; // 2 -static const uint64_t SH_FLD_PART_59_LEN = 13433; // 2 -static const uint64_t SH_FLD_PART_5_LEN = 13434; // 2 -static const uint64_t SH_FLD_PART_6 = 13435; // 2 -static const uint64_t SH_FLD_PART_60 = 13436; // 2 -static const uint64_t SH_FLD_PART_60_LEN = 13437; // 2 -static const uint64_t SH_FLD_PART_61 = 13438; // 2 -static const uint64_t SH_FLD_PART_61_LEN = 13439; // 2 -static const uint64_t SH_FLD_PART_62 = 13440; // 2 -static const uint64_t SH_FLD_PART_62_LEN = 13441; // 2 -static const uint64_t SH_FLD_PART_63 = 13442; // 2 -static const uint64_t SH_FLD_PART_63_LEN = 13443; // 2 -static const uint64_t SH_FLD_PART_6_LEN = 13444; // 2 -static const uint64_t SH_FLD_PART_7 = 13445; // 2 -static const uint64_t SH_FLD_PART_7_LEN = 13446; // 2 -static const uint64_t SH_FLD_PART_8 = 13447; // 2 -static const uint64_t SH_FLD_PART_8_LEN = 13448; // 2 -static const uint64_t SH_FLD_PART_9 = 13449; // 2 -static const uint64_t SH_FLD_PART_9_LEN = 13450; // 2 -static const uint64_t SH_FLD_PAR_17_MASK = 13451; // 8 -static const uint64_t SH_FLD_PAR_ERR_ONLY = 13452; // 8 -static const uint64_t SH_FLD_PAR_INVERT = 13453; // 8 -static const uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_HI = 13454; // 1 -static const uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_LO = 13455; // 1 -static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_HI = 13456; // 1 -static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_LO = 13457; // 1 -static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 = 13458; // 1 -static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 = 13459; // 1 -static const uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_HI = 13460; // 1 -static const uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_LO = 13461; // 1 -static const uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_01 = 13462; // 1 -static const uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_23 = 13463; // 1 -static const uint64_t SH_FLD_PASTE_ADDR_ALIGN = 13464; // 1 -static const uint64_t SH_FLD_PASTE_REJECT = 13465; // 1 -static const uint64_t SH_FLD_PATTERNA = 13466; // 90 -static const uint64_t SH_FLD_PATTERNA_LEN = 13467; // 90 -static const uint64_t SH_FLD_PATTERNB = 13468; // 90 -static const uint64_t SH_FLD_PATTERNB_LEN = 13469; // 90 -static const uint64_t SH_FLD_PATTERNC = 13470; // 90 -static const uint64_t SH_FLD_PATTERNC_LEN = 13471; // 90 -static const uint64_t SH_FLD_PATTERND = 13472; // 90 -static const uint64_t SH_FLD_PATTERND_LEN = 13473; // 90 -static const uint64_t SH_FLD_PATTERN_CHECK_EN = 13474; // 1 -static const uint64_t SH_FLD_PATTERN_SEL = 13475; // 2 -static const uint64_t SH_FLD_PATTERN_SEL_LEN = 13476; // 2 -static const uint64_t SH_FLD_PAYLOAD = 13477; // 1 -static const uint64_t SH_FLD_PAYLOAD_LEN = 13478; // 1 -static const uint64_t SH_FLD_PBASE = 13479; // 4 -static const uint64_t SH_FLD_PBASE_LEN = 13480; // 4 -static const uint64_t SH_FLD_PBAX_EN = 13481; // 1 -static const uint64_t SH_FLD_PBAX_OCC_PUSH0 = 13482; // 1 -static const uint64_t SH_FLD_PBAX_OCC_PUSH1 = 13483; // 1 -static const uint64_t SH_FLD_PBAX_OCC_SEND_ATTN = 13484; // 1 -static const uint64_t SH_FLD_PBA_BCDE_ATTN = 13485; // 1 -static const uint64_t SH_FLD_PBA_BCUE_ATTN = 13486; // 1 -static const uint64_t SH_FLD_PBA_ERROR = 13487; // 1 -static const uint64_t SH_FLD_PBA_REGION = 13488; // 1 -static const uint64_t SH_FLD_PBA_REGION_LEN = 13489; // 1 -static const uint64_t SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH = 13490; // 1 -static const uint64_t SH_FLD_PBCFG_0_EPSILON = 13491; // 1 -static const uint64_t SH_FLD_PBCFG_0_EPSILON_LEN = 13492; // 1 -static const uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT = 13493; // 1 -static const uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN = 13494; // 1 -static const uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT = 13495; // 1 -static const uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 13496; // 1 -static const uint64_t SH_FLD_PBCFG_0_INJ_ARRAY_SEL = 13497; // 1 -static const uint64_t SH_FLD_PBCFG_0_INJ_CE = 13498; // 1 -static const uint64_t SH_FLD_PBCFG_0_INJ_FREQ = 13499; // 1 -static const uint64_t SH_FLD_PBCFG_0_INJ_SUE = 13500; // 1 -static const uint64_t SH_FLD_PBCFG_0_INJ_UE = 13501; // 1 -static const uint64_t SH_FLD_PBCFG_0_UNUSED1 = 13502; // 1 -static const uint64_t SH_FLD_PBCFG_0_UNUSED1_LEN = 13503; // 1 -static const uint64_t SH_FLD_PBCFG_0_UNUSED2 = 13504; // 1 -static const uint64_t SH_FLD_PBCFG_0_UNUSED2_LEN = 13505; // 1 -static const uint64_t SH_FLD_PBCFG_1_UNUSED1 = 13506; // 1 -static const uint64_t SH_FLD_PBCFG_1_UNUSED1_LEN = 13507; // 1 -static const uint64_t SH_FLD_PBCFG_1_UNUSED2 = 13508; // 1 -static const uint64_t SH_FLD_PBCFG_1_UNUSED2_LEN = 13509; // 1 -static const uint64_t SH_FLD_PBCQ_CNTRL_LOGIC_ERR = 13510; // 1 -static const uint64_t SH_FLD_PBDATA_HANG = 13511; // 1 -static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR0 = 13512; // 12 -static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR1 = 13513; // 12 -static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR2 = 13514; // 12 -static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR0 = 13515; // 12 -static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR1 = 13516; // 12 -static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR2 = 13517; // 12 -static const uint64_t SH_FLD_PBIEQ00_PBH_HW1_ERROR = 13518; // 2 -static const uint64_t SH_FLD_PBIEQ00_PBH_HW2_ERROR = 13519; // 2 -static const uint64_t SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR = 13520; // 2 -static const uint64_t SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR = 13521; // 2 -static const uint64_t SH_FLD_PBIEQ01_PBH_HW1_ERROR = 13522; // 2 -static const uint64_t SH_FLD_PBIEQ01_PBH_HW2_ERROR = 13523; // 2 -static const uint64_t SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR = 13524; // 2 -static const uint64_t SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR = 13525; // 2 -static const uint64_t SH_FLD_PBIEQ02_PBH_HW1_ERROR = 13526; // 2 -static const uint64_t SH_FLD_PBIEQ02_PBH_HW2_ERROR = 13527; // 2 -static const uint64_t SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR = 13528; // 2 -static const uint64_t SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR = 13529; // 2 -static const uint64_t SH_FLD_PBIEQ03_PBH_HW1_ERROR = 13530; // 2 -static const uint64_t SH_FLD_PBIEQ03_PBH_HW2_ERROR = 13531; // 2 -static const uint64_t SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR = 13532; // 2 -static const uint64_t SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR = 13533; // 2 -static const uint64_t SH_FLD_PBIEQ04_PBH_HW1_ERROR = 13534; // 2 -static const uint64_t SH_FLD_PBIEQ04_PBH_HW2_ERROR = 13535; // 2 -static const uint64_t SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR = 13536; // 2 -static const uint64_t SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR = 13537; // 2 -static const uint64_t SH_FLD_PBIEQ05_PBH_HW1_ERROR = 13538; // 2 -static const uint64_t SH_FLD_PBIEQ05_PBH_HW2_ERROR = 13539; // 2 -static const uint64_t SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR = 13540; // 2 -static const uint64_t SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR = 13541; // 2 -static const uint64_t SH_FLD_PBI_DEBUG_SEL = 13542; // 4 -static const uint64_t SH_FLD_PBI_DEBUG_SEL_LEN = 13543; // 4 -static const uint64_t SH_FLD_PBI_IDLE = 13544; // 1 -static const uint64_t SH_FLD_PBI_INTERNAL_HANG = 13545; // 1 -static const uint64_t SH_FLD_PBI_MUX_SELECT = 13546; // 1 -static const uint64_t SH_FLD_PBI_MUX_SELECT_LEN = 13547; // 1 -static const uint64_t SH_FLD_PBI_PE = 13548; // 2 -static const uint64_t SH_FLD_PBI_WRITE_IDLE = 13549; // 2 -static const uint64_t SH_FLD_PBLN = 13550; // 15 -static const uint64_t SH_FLD_PBM_STATE = 13551; // 3 -static const uint64_t SH_FLD_PBM_STATE_LEN = 13552; // 3 -static const uint64_t SH_FLD_PBNNG = 13553; // 15 -static const uint64_t SH_FLD_PBREQ_BCE_MAX_PRIORITY = 13554; // 1 -static const uint64_t SH_FLD_PBREQ_DATA_HANG_DIV = 13555; // 1 -static const uint64_t SH_FLD_PBREQ_DATA_HANG_DIV_LEN = 13556; // 1 -static const uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK = 13557; // 1 -static const uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN = 13558; // 1 -static const uint64_t SH_FLD_PBREQ_EVENT_MUX = 13559; // 1 -static const uint64_t SH_FLD_PBREQ_EVENT_MUX_LEN = 13560; // 1 -static const uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV = 13561; // 1 -static const uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV_LEN = 13562; // 1 -static const uint64_t SH_FLD_PBREQ_EXIT_ON_HANG = 13563; // 1 -static const uint64_t SH_FLD_PBREQ_EXIT_ON_HANG_PBAX = 13564; // 1 -static const uint64_t SH_FLD_PBREQ_OPER_HANG_DIV = 13565; // 1 -static const uint64_t SH_FLD_PBREQ_OPER_HANG_DIV_LEN = 13566; // 1 -static const uint64_t SH_FLD_PBREQ_SLVFW_MAX_PRIORITY = 13567; // 1 -static const uint64_t SH_FLD_PBRNVG = 13568; // 15 -static const uint64_t SH_FLD_PBRS = 13569; // 3 -static const uint64_t SH_FLD_PBRSP = 13570; // 12 -static const uint64_t SH_FLD_PBRX_MASK = 13571; // 3 -static const uint64_t SH_FLD_PBRX_MASK_LEN = 13572; // 3 -static const uint64_t SH_FLD_PBRX_RTAG = 13573; // 3 -static const uint64_t SH_FLD_PBRX_RTAG_LEN = 13574; // 3 -static const uint64_t SH_FLD_PBTX_AMO_IGNORE_XUE = 13575; // 3 -static const uint64_t SH_FLD_PBTX_DELAY_BDONE = 13576; // 3 -static const uint64_t SH_FLD_PBTX_EARLY_AFTAG = 13577; // 3 -static const uint64_t SH_FLD_PBTX_FLIP_IMIN_BIG = 13578; // 3 -static const uint64_t SH_FLD_PBTX_FLIP_IMIN_LITTLE = 13579; // 3 -static const uint64_t SH_FLD_PBTX_REDUCE_RTAG = 13580; // 3 -static const uint64_t SH_FLD_PBUS_CMD_HANG = 13581; // 2 -static const uint64_t SH_FLD_PBUS_ECC_CE = 13582; // 2 -static const uint64_t SH_FLD_PBUS_ECC_SUE = 13583; // 2 -static const uint64_t SH_FLD_PBUS_ECC_UE = 13584; // 2 -static const uint64_t SH_FLD_PBUS_LINK_ABORT = 13585; // 2 -static const uint64_t SH_FLD_PBUS_LOAD_LINK_ERR = 13586; // 2 -static const uint64_t SH_FLD_PBUS_MISC_HW = 13587; // 2 -static const uint64_t SH_FLD_PBUS_READ_ARE = 13588; // 2 -static const uint64_t SH_FLD_PBUS_STORE_LINK_ERR = 13589; // 2 -static const uint64_t SH_FLD_PBUS_WRITE_ARE = 13590; // 2 -static const uint64_t SH_FLD_PBUS_XLAT_ECC_SUE = 13591; // 1 -static const uint64_t SH_FLD_PBUS_XLAT_ECC_UE = 13592; // 1 -static const uint64_t SH_FLD_PBXMIT_DXMIT_SEQ_ERRHOLD = 13593; // 2 -static const uint64_t SH_FLD_PBXMIT_MSGQ_SEQ_ERRHOLD = 13594; // 2 -static const uint64_t SH_FLD_PB_ACKDEAD_FW_RD = 13595; // 1 -static const uint64_t SH_FLD_PB_ACKDEAD_FW_RD_MASK = 13596; // 1 -static const uint64_t SH_FLD_PB_ACKDEAD_FW_WR = 13597; // 1 -static const uint64_t SH_FLD_PB_ACKDEAD_FW_WR_MASK = 13598; // 1 -static const uint64_t SH_FLD_PB_ADDR_PARITY = 13599; // 2 -static const uint64_t SH_FLD_PB_BADCRESP = 13600; // 1 -static const uint64_t SH_FLD_PB_BADCRESP_MASK = 13601; // 1 -static const uint64_t SH_FLD_PB_BAR_RESET = 13602; // 1 -static const uint64_t SH_FLD_PB_CE_FW = 13603; // 1 -static const uint64_t SH_FLD_PB_CE_FW_MASK = 13604; // 1 -static const uint64_t SH_FLD_PB_DATA_TIME_OUT = 13605; // 4 -static const uint64_t SH_FLD_PB_ECC_CE = 13606; // 1 -static const uint64_t SH_FLD_PB_ECC_ERR_CE = 13607; // 4 -static const uint64_t SH_FLD_PB_ECC_ERR_SUE = 13608; // 4 -static const uint64_t SH_FLD_PB_ECC_ERR_UE = 13609; // 4 -static const uint64_t SH_FLD_PB_ECC_SUE = 13610; // 1 -static const uint64_t SH_FLD_PB_ECC_UE = 13611; // 1 -static const uint64_t SH_FLD_PB_NOCI_EVENT_SEL = 13612; // 1 -static const uint64_t SH_FLD_PB_OFFSET = 13613; // 2 -static const uint64_t SH_FLD_PB_OFFSET_LEN = 13614; // 2 -static const uint64_t SH_FLD_PB_OPERTO = 13615; // 1 -static const uint64_t SH_FLD_PB_OPERTO_MASK = 13616; // 1 -static const uint64_t SH_FLD_PB_OP_HANG_ERR = 13617; // 1 -static const uint64_t SH_FLD_PB_PARITY_ERR = 13618; // 1 -static const uint64_t SH_FLD_PB_PARITY_ERROR = 13619; // 5 -static const uint64_t SH_FLD_PB_PARITY_ERR_MASK = 13620; // 1 -static const uint64_t SH_FLD_PB_PURGE_DONE_LVL = 13621; // 6 -static const uint64_t SH_FLD_PB_PURGE_PLS = 13622; // 6 -static const uint64_t SH_FLD_PB_RCMDX_CI_ERR1 = 13623; // 1 -static const uint64_t SH_FLD_PB_RCMDX_CI_ERR2 = 13624; // 1 -static const uint64_t SH_FLD_PB_RCMDX_CI_ERR3 = 13625; // 1 -static const uint64_t SH_FLD_PB_RDADRERR_FW = 13626; // 1 -static const uint64_t SH_FLD_PB_RDADRERR_FW_MASK = 13627; // 1 -static const uint64_t SH_FLD_PB_RDDATATO_FW = 13628; // 1 -static const uint64_t SH_FLD_PB_RDDATATO_FW_MASK = 13629; // 1 -static const uint64_t SH_FLD_PB_STOP = 13630; // 1 -static const uint64_t SH_FLD_PB_SUE_FW = 13631; // 1 -static const uint64_t SH_FLD_PB_SUE_FW_MASK = 13632; // 1 -static const uint64_t SH_FLD_PB_UE_FW = 13633; // 1 -static const uint64_t SH_FLD_PB_UE_FW_MASK = 13634; // 1 -static const uint64_t SH_FLD_PB_UNEXPCRESP = 13635; // 1 -static const uint64_t SH_FLD_PB_UNEXPCRESP_MASK = 13636; // 1 -static const uint64_t SH_FLD_PB_UNEXPDATA = 13637; // 1 -static const uint64_t SH_FLD_PB_UNEXPDATA_MASK = 13638; // 1 -static const uint64_t SH_FLD_PB_WRADRERR_FW = 13639; // 1 -static const uint64_t SH_FLD_PB_WRADRERR_FW_MASK = 13640; // 1 -static const uint64_t SH_FLD_PB_X0_FIR_ERR = 13641; // 2 -static const uint64_t SH_FLD_PB_X1_FIR_ERR = 13642; // 2 -static const uint64_t SH_FLD_PB_X2_FIR_ERR = 13643; // 2 -static const uint64_t SH_FLD_PB_X3_FIR_ERR = 13644; // 2 -static const uint64_t SH_FLD_PB_X4_FIR_ERR = 13645; // 2 -static const uint64_t SH_FLD_PB_X5_FIR_ERR = 13646; // 2 -static const uint64_t SH_FLD_PB_X6_FIR_ERR = 13647; // 2 -static const uint64_t SH_FLD_PB_XLAT_DATA_SUE = 13648; // 1 -static const uint64_t SH_FLD_PB_XLAT_DATA_UE = 13649; // 1 -static const uint64_t SH_FLD_PCB = 13650; // 3 -static const uint64_t SH_FLD_PCBMUX_GRANT_C0 = 13651; // 12 -static const uint64_t SH_FLD_PCBMUX_GRANT_C1 = 13652; // 12 -static const uint64_t SH_FLD_PCBMUX_REQ_C0 = 13653; // 12 -static const uint64_t SH_FLD_PCBMUX_REQ_C1 = 13654; // 12 -static const uint64_t SH_FLD_PCBQ_N_INFO = 13655; // 24 -static const uint64_t SH_FLD_PCBQ_N_INFO_LEN = 13656; // 24 -static const uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 13657; // 43 -static const uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 13658; // 43 -static const uint64_t SH_FLD_PCB_ADDRESS_PARITY = 13659; // 43 -static const uint64_t SH_FLD_PCB_COMMAND_PARITY = 13660; // 43 -static const uint64_t SH_FLD_PCB_EP_RESET = 13661; // 43 -static const uint64_t SH_FLD_PCB_ERROR = 13662; // 43 -static const uint64_t SH_FLD_PCB_FSM = 13663; // 43 -static const uint64_t SH_FLD_PCB_IDLE = 13664; // 43 -static const uint64_t SH_FLD_PCB_INTERFACE = 13665; // 43 -static const uint64_t SH_FLD_PCB_INTERRUPT_PROTOCOL = 13666; // 30 -static const uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N = 13667; // 144 -static const uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN = 13668; // 144 -static const uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N = 13669; // 12 -static const uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN = 13670; // 12 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_0 = 13671; // 8 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_1 = 13672; // 8 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_10 = 13673; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_11 = 13674; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_12 = 13675; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_13 = 13676; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_14 = 13677; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_15 = 13678; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_16 = 13679; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_17 = 13680; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_18 = 13681; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_19 = 13682; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_2 = 13683; // 8 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_20 = 13684; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_21 = 13685; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_22 = 13686; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_23 = 13687; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_3 = 13688; // 8 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_4 = 13689; // 8 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_5 = 13690; // 8 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_6 = 13691; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_7 = 13692; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_8 = 13693; // 6 -static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_9 = 13694; // 6 -static const uint64_t SH_FLD_PCB_LEN = 13695; // 2 -static const uint64_t SH_FLD_PCB_MASK = 13696; // 43 -static const uint64_t SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 13697; // 43 -static const uint64_t SH_FLD_PCB_REQUEST_SINCE_RESET = 13698; // 43 -static const uint64_t SH_FLD_PCB_RESET_DC = 13699; // 3 -static const uint64_t SH_FLD_PCB_TMP = 13700; // 1 -static const uint64_t SH_FLD_PCB_TMP_LEN = 13701; // 1 -static const uint64_t SH_FLD_PCB_WDATA_PARITY = 13702; // 43 -static const uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C0 = 13703; // 12 -static const uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C1 = 13704; // 12 -static const uint64_t SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS = 13705; // 6 -static const uint64_t SH_FLD_PCIE_REQUEST_ACCESS_ERROR = 13706; // 6 -static const uint64_t SH_FLD_PCLKDIFSEL = 13707; // 10 -static const uint64_t SH_FLD_PCLKSEL = 13708; // 14 -static const uint64_t SH_FLD_PCLKSEL_LEN = 13709; // 14 -static const uint64_t SH_FLD_PC_CAL_PCFSM_1HOT = 13710; // 8 -static const uint64_t SH_FLD_PC_CRD_AVAIL_PERR = 13711; // 1 -static const uint64_t SH_FLD_PC_CRD_PERR = 13712; // 1 -static const uint64_t SH_FLD_PC_DISABLE_DROOP = 13713; // 24 -static const uint64_t SH_FLD_PC_ERR_STATUS0 = 13714; // 8 -static const uint64_t SH_FLD_PC_ERR_STATUS0_LEN = 13715; // 8 -static const uint64_t SH_FLD_PC_FATAL_ERROR_0_2 = 13716; // 1 -static const uint64_t SH_FLD_PC_FATAL_ERROR_0_2_LEN = 13717; // 1 -static const uint64_t SH_FLD_PC_FUSED_CORE_MODE = 13718; // 12 -static const uint64_t SH_FLD_PC_INFO_ERROR_0_2 = 13719; // 1 -static const uint64_t SH_FLD_PC_INFO_ERROR_0_2_LEN = 13720; // 1 -static const uint64_t SH_FLD_PC_INIT_CAL_ERR = 13721; // 8 -static const uint64_t SH_FLD_PC_INIT_CAL_ERR_LEN = 13722; // 8 -static const uint64_t SH_FLD_PC_INSTR_RUNNING_C0 = 13723; // 12 -static const uint64_t SH_FLD_PC_INSTR_RUNNING_C1 = 13724; // 12 -static const uint64_t SH_FLD_PC_INTR_PENDING_C0 = 13725; // 24 -static const uint64_t SH_FLD_PC_INTR_PENDING_C1 = 13726; // 24 -static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C0 = 13727; // 12 -static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C0_LEN = 13728; // 12 -static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C1 = 13729; // 12 -static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C1_LEN = 13730; // 12 -static const uint64_t SH_FLD_PC_PE = 13731; // 8 -static const uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C0 = 13732; // 24 -static const uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C1 = 13733; // 24 -static const uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3 = 13734; // 1 -static const uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN = 13735; // 1 -static const uint64_t SH_FLD_PC_RECOV_ERROR_0_2 = 13736; // 1 -static const uint64_t SH_FLD_PC_RECOV_ERROR_0_2_LEN = 13737; // 1 -static const uint64_t SH_FLD_PC_SLICE_EN_ENC = 13738; // 1 -static const uint64_t SH_FLD_PC_SLICE_EN_ENC_LEN = 13739; // 1 -static const uint64_t SH_FLD_PC_TEST = 13740; // 1 -static const uint64_t SH_FLD_PC_TP_TRIG_SEL = 13741; // 43 -static const uint64_t SH_FLD_PC_TP_TRIG_SEL_LEN = 13742; // 43 -static const uint64_t SH_FLD_PC_UNMASKED_ATTN_C0 = 13743; // 12 -static const uint64_t SH_FLD_PC_UNMASKED_ATTN_C1 = 13744; // 12 -static const uint64_t SH_FLD_PDWN = 13745; // 5 -static const uint64_t SH_FLD_PDWN_LITE = 13746; // 140 -static const uint64_t SH_FLD_PDWN_LITE_CONTROLS = 13747; // 72 -static const uint64_t SH_FLD_PDWN_LITE_CONTROLS_LEN = 13748; // 72 -static const uint64_t SH_FLD_PDWN_LITE_DISABLE = 13749; // 8 -static const uint64_t SH_FLD_PE = 13750; // 45 -static const uint64_t SH_FLD_PE0_CXA_LINKDOWN_ERRHOLD = 13751; // 2 -static const uint64_t SH_FLD_PE1_CXA_LINKDOWN_ERRHOLD = 13752; // 2 -static const uint64_t SH_FLD_PEAK_ENABLE_DAC_CFG = 13753; // 4 -static const uint64_t SH_FLD_PEAK_INIT_CFG = 13754; // 6 -static const uint64_t SH_FLD_PEAK_INIT_CFG_LEN = 13755; // 6 -static const uint64_t SH_FLD_PEAK_INIT_TIMEOUT = 13756; // 6 -static const uint64_t SH_FLD_PEAK_INIT_TIMEOUT_LEN = 13757; // 6 -static const uint64_t SH_FLD_PEAK_RECAL_CFG = 13758; // 6 -static const uint64_t SH_FLD_PEAK_RECAL_CFG_LEN = 13759; // 6 -static const uint64_t SH_FLD_PEAK_RECAL_TIMEOUT = 13760; // 6 -static const uint64_t SH_FLD_PEAK_RECAL_TIMEOUT_LEN = 13761; // 6 -static const uint64_t SH_FLD_PEAK_TUNE = 13762; // 4 -static const uint64_t SH_FLD_PECE_C_N_T0 = 13763; // 24 -static const uint64_t SH_FLD_PECE_C_N_T0_LEN = 13764; // 24 -static const uint64_t SH_FLD_PECE_C_N_T1 = 13765; // 24 -static const uint64_t SH_FLD_PECE_C_N_T1_LEN = 13766; // 24 -static const uint64_t SH_FLD_PECE_C_N_T2 = 13767; // 24 -static const uint64_t SH_FLD_PECE_C_N_T2_LEN = 13768; // 24 -static const uint64_t SH_FLD_PECE_C_N_T3 = 13769; // 24 -static const uint64_t SH_FLD_PECE_C_N_T3_LEN = 13770; // 24 -static const uint64_t SH_FLD_PECE_DECR = 13771; // 96 -static const uint64_t SH_FLD_PECE_DHDES = 13772; // 96 -static const uint64_t SH_FLD_PECE_DPDES = 13773; // 96 -static const uint64_t SH_FLD_PECE_HMAINT = 13774; // 96 -static const uint64_t SH_FLD_PECE_HYPV = 13775; // 96 -static const uint64_t SH_FLD_PECE_INTR_DISABLED = 13776; // 24 -static const uint64_t SH_FLD_PECE_OS_EXT = 13777; // 96 -static const uint64_t SH_FLD_PEEK_DATA1_0 = 13778; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_0_LEN = 13779; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_1 = 13780; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_1_LEN = 13781; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_2 = 13782; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_2_LEN = 13783; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_3 = 13784; // 12 -static const uint64_t SH_FLD_PEEK_DATA1_3_LEN = 13785; // 12 -static const uint64_t SH_FLD_PEND = 13786; // 8 -static const uint64_t SH_FLD_PENDING_SOURCE = 13787; // 30 -static const uint64_t SH_FLD_PENDING_SOURCE_LEN = 13788; // 30 -static const uint64_t SH_FLD_PERFMON_COUNTER = 13789; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_1 = 13790; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_1_LEN = 13791; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_2 = 13792; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_2_LEN = 13793; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_3 = 13794; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_3_LEN = 13795; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_4 = 13796; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_4_LEN = 13797; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_5 = 13798; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_5_LEN = 13799; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_6 = 13800; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_6_LEN = 13801; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_7 = 13802; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_7_LEN = 13803; // 5 -static const uint64_t SH_FLD_PERFMON_COUNTER_LEN = 13804; // 5 -static const uint64_t SH_FLD_PERFORM_RDCLK_ALIGN = 13805; // 8 -static const uint64_t SH_FLD_PERFTRACE_ENABLE = 13806; // 5 -static const uint64_t SH_FLD_PERFTRACE_FIXED_WINDOW = 13807; // 5 -static const uint64_t SH_FLD_PERFTRACE_MODE = 13808; // 5 -static const uint64_t SH_FLD_PERFTRACE_MODE_LEN = 13809; // 5 -static const uint64_t SH_FLD_PERFTRACE_PRESCALE = 13810; // 5 -static const uint64_t SH_FLD_PERF_CASCADE = 13811; // 1 -static const uint64_t SH_FLD_PERF_CASCADE_LEN = 13812; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_CASCADE = 13813; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_CASCADE_LEN = 13814; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_DISABLE_PMISC = 13815; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_ENABLE = 13816; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_EVENTS = 13817; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_EVENTS_LEN = 13818; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_FREEZEMODE = 13819; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0 = 13820; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0_LEN = 13821; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1 = 13822; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1_LEN = 13823; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2 = 13824; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2_LEN = 13825; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3 = 13826; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3_LEN = 13827; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PMISC_MODE = 13828; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0 = 13829; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN = 13830; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1 = 13831; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN = 13832; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2 = 13833; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN = 13834; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3 = 13835; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN = 13836; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_RESETMODE = 13837; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_SPARE = 13838; // 1 -static const uint64_t SH_FLD_PERF_CONFIG_SPARE_LEN = 13839; // 1 -static const uint64_t SH_FLD_PERF_DISABLE_PMISC = 13840; // 1 -static const uint64_t SH_FLD_PERF_ENABLE = 13841; // 2 -static const uint64_t SH_FLD_PERF_EVENT0 = 13842; // 1 -static const uint64_t SH_FLD_PERF_EVENT0_LEN = 13843; // 1 -static const uint64_t SH_FLD_PERF_EVENT1 = 13844; // 1 -static const uint64_t SH_FLD_PERF_EVENT1_LEN = 13845; // 1 -static const uint64_t SH_FLD_PERF_EVENT2 = 13846; // 1 -static const uint64_t SH_FLD_PERF_EVENT2_LEN = 13847; // 1 -static const uint64_t SH_FLD_PERF_EVENT3 = 13848; // 1 -static const uint64_t SH_FLD_PERF_EVENT3_LEN = 13849; // 1 -static const uint64_t SH_FLD_PERF_FREEZEMODE = 13850; // 1 -static const uint64_t SH_FLD_PERF_PE_MASK = 13851; // 1 -static const uint64_t SH_FLD_PERF_PE_MATCH = 13852; // 1 -static const uint64_t SH_FLD_PERF_PE_MATCH_LEN = 13853; // 1 -static const uint64_t SH_FLD_PERF_PMISC_MODE = 13854; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C0 = 13855; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C0_LEN = 13856; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C1 = 13857; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C1_LEN = 13858; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C2 = 13859; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C2_LEN = 13860; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C3 = 13861; // 1 -static const uint64_t SH_FLD_PERF_PRESCALE_C3_LEN = 13862; // 1 -static const uint64_t SH_FLD_PERF_RESETMODE = 13863; // 1 -static const uint64_t SH_FLD_PERF_THRESH = 13864; // 8 -static const uint64_t SH_FLD_PERF_THRESH_LEN = 13865; // 8 -static const uint64_t SH_FLD_PERIODIC = 13866; // 56 -static const uint64_t SH_FLD_PERIODIC_CAL_REQ_EN = 13867; // 8 -static const uint64_t SH_FLD_PERIODIC_LEN = 13868; // 56 -static const uint64_t SH_FLD_PERSIST = 13869; // 8 -static const uint64_t SH_FLD_PERSIST_LEN = 13870; // 8 -static const uint64_t SH_FLD_PERV = 13871; // 215 -static const uint64_t SH_FLD_PERVASIVE_CAPT = 13872; // 6 -static const uint64_t SH_FLD_PER_ABORT = 13873; // 8 -static const uint64_t SH_FLD_PER_DUTY_CYCLE_SW = 13874; // 8 -static const uint64_t SH_FLD_PER_REPEAT_COUNT = 13875; // 8 -static const uint64_t SH_FLD_PER_REPEAT_COUNT_LEN = 13876; // 8 -static const uint64_t SH_FLD_PE_ADR_BAR_MODE = 13877; // 3 -static const uint64_t SH_FLD_PE_BLOCK_CQPB_PB_INIT = 13878; // 3 -static const uint64_t SH_FLD_PE_CAPP = 13879; // 3 -static const uint64_t SH_FLD_PE_CAPP_APC_ENG = 13880; // 3 -static const uint64_t SH_FLD_PE_CAPP_APC_ENG_LEN = 13881; // 3 -static const uint64_t SH_FLD_PE_CAPP_EN = 13882; // 3 -static const uint64_t SH_FLD_PE_CAPP_LEN = 13883; // 3 -static const uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG = 13884; // 3 -static const uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN = 13885; // 3 -static const uint64_t SH_FLD_PE_CAPP_P8_MODE = 13886; // 3 -static const uint64_t SH_FLD_PE_CHANNEL_STREAMING_EN = 13887; // 3 -static const uint64_t SH_FLD_PE_CONSTANT_EINJ = 13888; // 3 -static const uint64_t SH_FLD_PE_CQ_ECC_INJECT_ENABLE = 13889; // 3 -static const uint64_t SH_FLD_PE_CQ_PAR_INJECT_ENABLE = 13890; // 3 -static const uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY = 13891; // 3 -static const uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY_LEN = 13892; // 3 -static const uint64_t SH_FLD_PE_CQ_SRAM_ARRAY = 13893; // 3 -static const uint64_t SH_FLD_PE_CQ_SRAM_ARRAY_LEN = 13894; // 3 -static const uint64_t SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION = 13895; // 3 -static const uint64_t SH_FLD_PE_DISABLE_INJ_ON_RESEND = 13896; // 3 -static const uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP = 13897; // 3 -static const uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE = 13898; // 3 -static const uint64_t SH_FLD_PE_DISABLE_INTWR_VG = 13899; // 3 -static const uint64_t SH_FLD_PE_DISABLE_MC_PREFETCH = 13900; // 3 -static const uint64_t SH_FLD_PE_DISABLE_OOO_MODE = 13901; // 3 -static const uint64_t SH_FLD_PE_DISABLE_PCI_CLK_CHECK = 13902; // 3 -static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_GROUP = 13903; // 3 -static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_NODAL = 13904; // 3 -static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_RNNN = 13905; // 3 -static const uint64_t SH_FLD_PE_DISABLE_RD_VG = 13906; // 3 -static const uint64_t SH_FLD_PE_DISABLE_TCE_ARBITRATION = 13907; // 3 -static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP = 13908; // 3 -static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL = 13909; // 3 -static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN = 13910; // 3 -static const uint64_t SH_FLD_PE_DISABLE_TCE_VG = 13911; // 3 -static const uint64_t SH_FLD_PE_DISABLE_WR_SCOPE_GROUP = 13912; // 3 -static const uint64_t SH_FLD_PE_DISABLE_WR_VG = 13913; // 3 -static const uint64_t SH_FLD_PE_DROPPACECOUNT = 13914; // 3 -static const uint64_t SH_FLD_PE_DROPPACECOUNT_LEN = 13915; // 3 -static const uint64_t SH_FLD_PE_DROPPACEINC = 13916; // 3 -static const uint64_t SH_FLD_PE_DROPPACEINC_LEN = 13917; // 3 -static const uint64_t SH_FLD_PE_DROPPRIORITYMASK = 13918; // 3 -static const uint64_t SH_FLD_PE_DROPPRIORITYMASK_LEN = 13919; // 3 -static const uint64_t SH_FLD_PE_ECC_INJECT_TYPE = 13920; // 3 -static const uint64_t SH_FLD_PE_ECC_INJECT_TYPE_LEN = 13921; // 3 -static const uint64_t SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY = 13922; // 3 -static const uint64_t SH_FLD_PE_ENABLE_DMAR_IOPACING = 13923; // 3 -static const uint64_t SH_FLD_PE_ENABLE_DMAW_IOPACING = 13924; // 3 -static const uint64_t SH_FLD_PE_ENABLE_ENH_FLOW = 13925; // 3 -static const uint64_t SH_FLD_PE_ENABLE_IO_CMD_PACING = 13926; // 3 -static const uint64_t SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 13927; // 3 -static const uint64_t SH_FLD_PE_ENABLE_RD_SKIP_GROUP = 13928; // 3 -static const uint64_t SH_FLD_PE_ENABLE_TCE_SKIP_GROUP = 13929; // 3 -static const uint64_t SH_FLD_PE_ENHANCED_PEER2PEER_MODDE = 13930; // 9 -static const uint64_t SH_FLD_PE_ETU_RESET = 13931; // 9 -static const uint64_t SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 13932; // 3 -static const uint64_t SH_FLD_PE_HANG_SM_ON_ARE = 13933; // 3 -static const uint64_t SH_FLD_PE_IGNORE_SFSTAT = 13934; // 3 -static const uint64_t SH_FLD_PE_INBOUND_ACTIVE = 13935; // 9 -static const uint64_t SH_FLD_PE_INT_BAR = 13936; // 9 -static const uint64_t SH_FLD_PE_INT_BAR_EN = 13937; // 9 -static const uint64_t SH_FLD_PE_INT_BAR_LEN = 13938; // 9 -static const uint64_t SH_FLD_PE_ISMB_ERROR_INJECT = 13939; // 3 -static const uint64_t SH_FLD_PE_ISMB_ERROR_INJECT_LEN = 13940; // 3 -static const uint64_t SH_FLD_PE_LEN = 13941; // 45 -static const uint64_t SH_FLD_PE_MMIO_BAR0 = 13942; // 9 -static const uint64_t SH_FLD_PE_MMIO_BAR0_EN = 13943; // 9 -static const uint64_t SH_FLD_PE_MMIO_BAR0_LEN = 13944; // 9 -static const uint64_t SH_FLD_PE_MMIO_BAR1 = 13945; // 9 -static const uint64_t SH_FLD_PE_MMIO_BAR1_EN = 13946; // 9 -static const uint64_t SH_FLD_PE_MMIO_BAR1_LEN = 13947; // 9 -static const uint64_t SH_FLD_PE_MMIO_MASK0 = 13948; // 9 -static const uint64_t SH_FLD_PE_MMIO_MASK0_LEN = 13949; // 9 -static const uint64_t SH_FLD_PE_MMIO_MASK1 = 13950; // 9 -static const uint64_t SH_FLD_PE_MMIO_MASK1_LEN = 13951; // 9 -static const uint64_t SH_FLD_PE_OSMB_DATASTART_MODE = 13952; // 3 -static const uint64_t SH_FLD_PE_OSMB_DATASTART_MODE_LEN = 13953; // 3 -static const uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE = 13954; // 3 -static const uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN = 13955; // 3 -static const uint64_t SH_FLD_PE_OSMB_EARLY_START = 13956; // 3 -static const uint64_t SH_FLD_PE_OSMB_EARLY_START_LEN = 13957; // 3 -static const uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT = 13958; // 3 -static const uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN = 13959; // 3 -static const uint64_t SH_FLD_PE_OUTBOUND_ACTIVE = 13960; // 9 -static const uint64_t SH_FLD_PE_PCIE_CLK_TRACE_EN = 13961; // 3 -static const uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL = 13962; // 3 -static const uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN = 13963; // 3 -static const uint64_t SH_FLD_PE_PEER2PEER_MODDE = 13964; // 9 -static const uint64_t SH_FLD_PE_PERFMON_EN = 13965; // 3 -static const uint64_t SH_FLD_PE_PERFMON_EN_LEN = 13966; // 3 -static const uint64_t SH_FLD_PE_PERFMON_READ_TYPE = 13967; // 3 -static const uint64_t SH_FLD_PE_PERFMON_READ_TYPE_LEN = 13968; // 3 -static const uint64_t SH_FLD_PE_PHB_BAR = 13969; // 9 -static const uint64_t SH_FLD_PE_PHB_BAR_EN = 13970; // 9 -static const uint64_t SH_FLD_PE_PHB_BAR_LEN = 13971; // 9 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE0 = 13972; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE0_LEN = 13973; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE1 = 13974; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE1_LEN = 13975; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE2 = 13976; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE2_LEN = 13977; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE3 = 13978; // 3 -static const uint64_t SH_FLD_PE_PMON_MUX_BYTE3_LEN = 13979; // 3 -static const uint64_t SH_FLD_PE_QFIFO_HOLD_MODE = 13980; // 3 -static const uint64_t SH_FLD_PE_QFIFO_HOLD_MODE_LEN = 13981; // 3 -static const uint64_t SH_FLD_PE_RD_TIMEOUT_MASK = 13982; // 3 -static const uint64_t SH_FLD_PE_RD_TIMEOUT_MASK_LEN = 13983; // 3 -static const uint64_t SH_FLD_PE_RD_WRITE_ORDERING = 13984; // 3 -static const uint64_t SH_FLD_PE_RD_WRITE_ORDERING_LEN = 13985; // 3 -static const uint64_t SH_FLD_PE_RTYDROPDIVIDER = 13986; // 3 -static const uint64_t SH_FLD_PE_RTYDROPDIVIDER_LEN = 13987; // 3 -static const uint64_t SH_FLD_PE_SELECT_ETU_TRACE = 13988; // 3 -static const uint64_t SH_FLD_PE_STOP_STATE_SIGNALED = 13989; // 6 -static const uint64_t SH_FLD_PE_STQ_ALLOCATION = 13990; // 3 -static const uint64_t SH_FLD_PE_TX_RESP_HWM = 13991; // 3 -static const uint64_t SH_FLD_PE_TX_RESP_HWM_LEN = 13992; // 3 -static const uint64_t SH_FLD_PE_TX_RESP_LWM = 13993; // 3 -static const uint64_t SH_FLD_PE_TX_RESP_LWM_LEN = 13994; // 3 -static const uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE = 13995; // 3 -static const uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN = 13996; // 3 -static const uint64_t SH_FLD_PE_WR_STRICT_ORDER_MODE = 13997; // 3 -static const uint64_t SH_FLD_PE_WR_TIMEOUT_MASK = 13998; // 3 -static const uint64_t SH_FLD_PE_WR_TIMEOUT_MASK_LEN = 13999; // 3 -static const uint64_t SH_FLD_PFD360SEL = 14000; // 4 -static const uint64_t SH_FLD_PFET_SEQ_PROGRAM = 14001; // 30 -static const uint64_t SH_FLD_PFIRACTION0 = 14002; // 9 -static const uint64_t SH_FLD_PFIRACTION0_LEN = 14003; // 9 -static const uint64_t SH_FLD_PFIRACTION1 = 14004; // 9 -static const uint64_t SH_FLD_PFIRACTION1_LEN = 14005; // 9 -static const uint64_t SH_FLD_PFIRMASK = 14006; // 9 -static const uint64_t SH_FLD_PFIRMASK_LEN = 14007; // 9 -static const uint64_t SH_FLD_PFIRPFIR = 14008; // 9 -static const uint64_t SH_FLD_PFIRPFIR_LEN = 14009; // 9 -static const uint64_t SH_FLD_PFREQ0 = 14010; // 24 -static const uint64_t SH_FLD_PFREQ0_LEN = 14011; // 24 -static const uint64_t SH_FLD_PFREQ1 = 14012; // 24 -static const uint64_t SH_FLD_PFREQ1_LEN = 14013; // 24 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH0 = 14014; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH0_LEN = 14015; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH1 = 14016; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH1_LEN = 14017; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH2 = 14018; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH2_LEN = 14019; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH3 = 14020; // 8 -static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH3_LEN = 14021; // 8 -static const uint64_t SH_FLD_PF_DROP_CNT_THRESH = 14022; // 4 -static const uint64_t SH_FLD_PF_DROP_CNT_THRESH_LEN = 14023; // 4 -static const uint64_t SH_FLD_PF_DROP_VALUE0 = 14024; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE0_LEN = 14025; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE1 = 14026; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE1_LEN = 14027; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE2 = 14028; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE2_LEN = 14029; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE3 = 14030; // 8 -static const uint64_t SH_FLD_PF_DROP_VALUE3_LEN = 14031; // 8 -static const uint64_t SH_FLD_PF_MACHINE_HANG = 14032; // 12 -static const uint64_t SH_FLD_PF_MACHINE_W4DT_HANG = 14033; // 12 -static const uint64_t SH_FLD_PF_PROMOTE_ASYNC_IF = 14034; // 8 -static const uint64_t SH_FLD_PF_PROMOTE_ERR_INJ = 14035; // 8 -static const uint64_t SH_FLD_PF_UNSOLICITED_CRESP = 14036; // 12 -static const uint64_t SH_FLD_PF_UNSOLICITED_DATA = 14037; // 12 -static const uint64_t SH_FLD_PGMIGR1_BAR = 14038; // 1 -static const uint64_t SH_FLD_PGMIGR1_BAR_LEN = 14039; // 1 -static const uint64_t SH_FLD_PGMIGR1_PGSZ = 14040; // 1 -static const uint64_t SH_FLD_PGMIGR1_PGSZ_LEN = 14041; // 1 -static const uint64_t SH_FLD_PGMIGR1_VAL = 14042; // 1 -static const uint64_t SH_FLD_PGMIGR2_BAR = 14043; // 1 -static const uint64_t SH_FLD_PGMIGR2_BAR_LEN = 14044; // 1 -static const uint64_t SH_FLD_PGMIGR2_PGSZ = 14045; // 1 -static const uint64_t SH_FLD_PGMIGR2_PGSZ_LEN = 14046; // 1 -static const uint64_t SH_FLD_PGMIGR2_VAL = 14047; // 1 -static const uint64_t SH_FLD_PGMIGR3_BAR = 14048; // 1 -static const uint64_t SH_FLD_PGMIGR3_BAR_LEN = 14049; // 1 -static const uint64_t SH_FLD_PGMIGR3_PGSZ = 14050; // 1 -static const uint64_t SH_FLD_PGMIGR3_PGSZ_LEN = 14051; // 1 -static const uint64_t SH_FLD_PGMIGR3_VAL = 14052; // 1 -static const uint64_t SH_FLD_PGMIGR4_BAR = 14053; // 1 -static const uint64_t SH_FLD_PGMIGR4_BAR_LEN = 14054; // 1 -static const uint64_t SH_FLD_PGMIGR4_PGSZ = 14055; // 1 -static const uint64_t SH_FLD_PGMIGR4_PGSZ_LEN = 14056; // 1 -static const uint64_t SH_FLD_PGMIGR4_VAL = 14057; // 1 -static const uint64_t SH_FLD_PGMIGR5_BAR = 14058; // 1 -static const uint64_t SH_FLD_PGMIGR5_BAR_LEN = 14059; // 1 -static const uint64_t SH_FLD_PGMIGR5_PGSZ = 14060; // 1 -static const uint64_t SH_FLD_PGMIGR5_PGSZ_LEN = 14061; // 1 -static const uint64_t SH_FLD_PGMIGR5_VAL = 14062; // 1 -static const uint64_t SH_FLD_PGMIGR6_BAR = 14063; // 1 -static const uint64_t SH_FLD_PGMIGR6_BAR_LEN = 14064; // 1 -static const uint64_t SH_FLD_PGMIGR6_PGSZ = 14065; // 1 -static const uint64_t SH_FLD_PGMIGR6_PGSZ_LEN = 14066; // 1 -static const uint64_t SH_FLD_PGMIGR6_VAL = 14067; // 1 -static const uint64_t SH_FLD_PGMIGR7_BAR = 14068; // 1 -static const uint64_t SH_FLD_PGMIGR7_BAR_LEN = 14069; // 1 -static const uint64_t SH_FLD_PGMIGR7_PGSZ = 14070; // 1 -static const uint64_t SH_FLD_PGMIGR7_PGSZ_LEN = 14071; // 1 -static const uint64_t SH_FLD_PGMIGR7_VAL = 14072; // 1 -static const uint64_t SH_FLD_PGOFFIRSTLS = 14073; // 1 -static const uint64_t SH_FLD_PGOFFIRSTLS_LEN = 14074; // 1 -static const uint64_t SH_FLD_PGOFNEXTLS = 14075; // 1 -static const uint64_t SH_FLD_PGOFNEXTLS_LEN = 14076; // 1 -static const uint64_t SH_FLD_PGOOD_TIMEOUT_SEL = 14077; // 4 -static const uint64_t SH_FLD_PGOOD_TIMEOUT_SEL_LEN = 14078; // 4 -static const uint64_t SH_FLD_PG_MIG_DISABLED_ERR = 14079; // 2 -static const uint64_t SH_FLD_PG_MIG_SIZE_MISMATCH_ERR = 14080; // 2 -static const uint64_t SH_FLD_PHASEFB = 14081; // 4 -static const uint64_t SH_FLD_PHASEFB_LEN = 14082; // 4 -static const uint64_t SH_FLD_PHBCSR_SPARE = 14083; // 1 -static const uint64_t SH_FLD_PHB_FILTER_CNTL = 14084; // 2 -static const uint64_t SH_FLD_PHB_FILTER_CNTL_LEN = 14085; // 2 -static const uint64_t SH_FLD_PHB_LINK_DOWN = 14086; // 4 -static const uint64_t SH_FLD_PHY = 14087; // 6 -static const uint64_t SH_FLD_PHYP_SCOPE = 14088; // 1 -static const uint64_t SH_FLD_PHY_LEN = 14089; // 6 -static const uint64_t SH_FLD_PHY_PARITY_HOLD_OUT = 14090; // 8 -static const uint64_t SH_FLD_PIB2PCB_DC = 14091; // 3 -static const uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID = 14092; // 1 -static const uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN = 14093; // 1 -static const uint64_t SH_FLD_PIB_0 = 14094; // 2 -static const uint64_t SH_FLD_PIB_0_LEN = 14095; // 2 -static const uint64_t SH_FLD_PIB_1 = 14096; // 2 -static const uint64_t SH_FLD_PIB_1_LEN = 14097; // 2 -static const uint64_t SH_FLD_PIB_2 = 14098; // 2 -static const uint64_t SH_FLD_PIB_2_LEN = 14099; // 2 -static const uint64_t SH_FLD_PIB_3 = 14100; // 2 -static const uint64_t SH_FLD_PIB_3_LEN = 14101; // 2 -static const uint64_t SH_FLD_PIB_ABORT = 14102; // 2 -static const uint64_t SH_FLD_PIB_ADDR = 14103; // 2 -static const uint64_t SH_FLD_PIB_ADDR_LEN = 14104; // 2 -static const uint64_t SH_FLD_PIB_ADDR_P = 14105; // 1 -static const uint64_t SH_FLD_PIB_ADDR_P_ERR = 14106; // 1 -static const uint64_t SH_FLD_PIB_BUSY = 14107; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0 = 14108; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0_LEN = 14109; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1 = 14110; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1_LEN = 14111; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2 = 14112; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2_LEN = 14113; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3 = 14114; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3_LEN = 14115; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 = 14116; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 = 14117; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 = 14118; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 = 14119; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_0 = 14120; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_1 = 14121; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_2 = 14122; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_3 = 14123; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 = 14124; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 = 14125; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 = 14126; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 = 14127; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 = 14128; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 = 14129; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 = 14130; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 = 14131; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 = 14132; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 = 14133; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 = 14134; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 = 14135; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0 = 14136; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN = 14137; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1 = 14138; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN = 14139; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2 = 14140; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN = 14141; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3 = 14142; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN = 14143; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0 = 14144; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN = 14145; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1 = 14146; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN = 14147; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2 = 14148; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN = 14149; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3 = 14150; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN = 14151; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0 = 14152; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN = 14153; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1 = 14154; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN = 14155; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2 = 14156; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN = 14157; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3 = 14158; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN = 14159; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0 = 14160; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN = 14161; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1 = 14162; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN = 14163; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2 = 14164; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN = 14165; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3 = 14166; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN = 14167; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0 = 14168; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN = 14169; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1 = 14170; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN = 14171; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2 = 14172; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN = 14173; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3 = 14174; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN = 14175; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 = 14176; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 14177; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 = 14178; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 14179; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 = 14180; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 14181; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 = 14182; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 14183; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0 = 14184; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0_LEN = 14185; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1 = 14186; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1_LEN = 14187; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2 = 14188; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2_LEN = 14189; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3 = 14190; // 1 -static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3_LEN = 14191; // 1 -static const uint64_t SH_FLD_PIB_COMPONENT_BUSY = 14192; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_0 = 14193; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_0_LEN = 14194; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_1 = 14195; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_1_LEN = 14196; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_2 = 14197; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_2_LEN = 14198; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_3 = 14199; // 1 -static const uint64_t SH_FLD_PIB_DATA0TO7_3_LEN = 14200; // 1 -static const uint64_t SH_FLD_PIB_DATAOP_PENDING = 14201; // 1 -static const uint64_t SH_FLD_PIB_DATA_P = 14202; // 1 -static const uint64_t SH_FLD_PIB_DATA_P_ERR = 14203; // 1 -static const uint64_t SH_FLD_PIB_ERROR_CODE = 14204; // 1 -static const uint64_t SH_FLD_PIB_ERROR_CODE_LEN = 14205; // 1 -static const uint64_t SH_FLD_PIB_FSM_STATE = 14206; // 1 -static const uint64_t SH_FLD_PIB_FSM_STATE_LEN = 14207; // 1 -static const uint64_t SH_FLD_PIB_HANG = 14208; // 1 -static const uint64_t SH_FLD_PIB_IFETCH_PENDING = 14209; // 1 -static const uint64_t SH_FLD_PIB_IMPRECISE_ERROR_PENDING = 14210; // 1 -static const uint64_t SH_FLD_PIB_MASTER_REQUEST = 14211; // 4 -static const uint64_t SH_FLD_PIB_MASTER_RSP_INFO = 14212; // 4 -static const uint64_t SH_FLD_PIB_MASTER_RSP_INFO_LEN = 14213; // 4 -static const uint64_t SH_FLD_PIB_RESET_DURING_PIB_ACCESS = 14214; // 4 -static const uint64_t SH_FLD_PIB_RESPONSE_INFO = 14215; // 1 -static const uint64_t SH_FLD_PIB_RESPONSE_INFO_LEN = 14216; // 1 -static const uint64_t SH_FLD_PIB_RSP_INFO = 14217; // 1 -static const uint64_t SH_FLD_PIB_RSP_INFO_LEN = 14218; // 1 -static const uint64_t SH_FLD_PIB_R_NW = 14219; // 1 -static const uint64_t SH_FLD_PIB_SLAVE_ADDR_INVALID = 14220; // 4 -static const uint64_t SH_FLD_PIB_SLAVE_ADDR_PARITY = 14221; // 4 -static const uint64_t SH_FLD_PIB_SLAVE_DATA_PARITY = 14222; // 4 -static const uint64_t SH_FLD_PIB_SLAVE_READ_INVALID = 14223; // 4 -static const uint64_t SH_FLD_PIB_SLAVE_WRITE_INVALID = 14224; // 4 -static const uint64_t SH_FLD_PID = 14225; // 273 -static const uint64_t SH_FLD_PID_LEN = 14226; // 273 -static const uint64_t SH_FLD_PID_MASK = 14227; // 1 -static const uint64_t SH_FLD_PID_MASK_LEN = 14228; // 1 -static const uint64_t SH_FLD_PIPELINE_ENABLE = 14229; // 1 -static const uint64_t SH_FLD_PIPE_COUNTER = 14230; // 1 -static const uint64_t SH_FLD_PIPE_COUNTER_LEN = 14231; // 1 -static const uint64_t SH_FLD_PIPE_MARGIN = 14232; // 48 -static const uint64_t SH_FLD_PIPE_SEL = 14233; // 120 -static const uint64_t SH_FLD_PIPE_SEL_LEN = 14234; // 48 -static const uint64_t SH_FLD_PI_ECC_CE = 14235; // 1 -static const uint64_t SH_FLD_PI_ECC_SUE = 14236; // 1 -static const uint64_t SH_FLD_PI_ECC_UE = 14237; // 1 -static const uint64_t SH_FLD_PLBARB_LOCKERR = 14238; // 1 -static const uint64_t SH_FLD_PLLCVHOLD = 14239; // 6 -static const uint64_t SH_FLD_PLLFMAX = 14240; // 6 -static const uint64_t SH_FLD_PLLFMIN = 14241; // 6 -static const uint64_t SH_FLD_PLLFORCE_OUT_EN = 14242; // 43 -static const uint64_t SH_FLD_PLLLOCK = 14243; // 4 -static const uint64_t SH_FLD_PLLLOCK_0_FILTER_PLL_NEST = 14244; // 1 -static const uint64_t SH_FLD_PLLLOCK_1_FILTER_PLL_MC = 14245; // 1 -static const uint64_t SH_FLD_PLLLOCK_2_XBUS = 14246; // 1 -static const uint64_t SH_FLD_PLLLOCK_3_NEST = 14247; // 1 -static const uint64_t SH_FLD_PLLREFSEL = 14248; // 3 -static const uint64_t SH_FLD_PLLREFSEL_LEN = 14249; // 3 -static const uint64_t SH_FLD_PLLRESET = 14250; // 6 -static const uint64_t SH_FLD_PLL_BNDY_BYPASS_EN = 14251; // 43 -static const uint64_t SH_FLD_PLL_BYPASS = 14252; // 43 -static const uint64_t SH_FLD_PLL_CLKIN_SEL = 14253; // 43 -static const uint64_t SH_FLD_PLL_DESTOUT = 14254; // 43 -static const uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL = 14255; // 4 -static const uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN = 14256; // 4 -static const uint64_t SH_FLD_PLL_REFCLKSEL_SCOM_EN = 14257; // 4 -static const uint64_t SH_FLD_PLL_RESET = 14258; // 43 -static const uint64_t SH_FLD_PLL_TEST_EN = 14259; // 43 -static const uint64_t SH_FLD_PLL_UNLOCK = 14260; // 43 -static const uint64_t SH_FLD_PLL_UNLOCK_LEN = 14261; // 43 -static const uint64_t SH_FLD_PL_ERR = 14262; // 6 -static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_EN = 14263; // 12 -static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM = 14264; // 12 -static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN = 14265; // 12 -static const uint64_t SH_FLD_PM03_SMT_ROTATION_DIS = 14266; // 12 -static const uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE = 14267; // 12 -static const uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN = 14268; // 12 -static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_EN = 14269; // 12 -static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM = 14270; // 12 -static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN = 14271; // 12 -static const uint64_t SH_FLD_PM47_SMT_ROTATION_DIS = 14272; // 12 -static const uint64_t SH_FLD_PMCM_THRESHOLD = 14273; // 24 -static const uint64_t SH_FLD_PMCM_THRESHOLD_LEN = 14274; // 24 -static const uint64_t SH_FLD_PMCR_OVERRIDE_EN = 14275; // 12 -static const uint64_t SH_FLD_PMCR_UPDATE_C0 = 14276; // 12 -static const uint64_t SH_FLD_PMCR_UPDATE_C1 = 14277; // 12 -static const uint64_t SH_FLD_PMC_ENABLE = 14278; // 1 -static const uint64_t SH_FLD_PMC_O2S_0A_ONGOING = 14279; // 1 -static const uint64_t SH_FLD_PMC_O2S_0B_ONGOING = 14280; // 1 -static const uint64_t SH_FLD_PMC_O2S_1A_ONGOING = 14281; // 1 -static const uint64_t SH_FLD_PMC_O2S_1B_ONGOING = 14282; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE0_PENDING = 14283; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE1_PENDING = 14284; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE2_PENDING = 14285; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE3_PENDING = 14286; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE4_PENDING = 14287; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE5_PENDING = 14288; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE6_PENDING = 14289; // 1 -static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE7_PENDING = 14290; // 1 -static const uint64_t SH_FLD_PMISC_CRESP_ADDR_ERR = 14291; // 12 -static const uint64_t SH_FLD_PMISC_MODE = 14292; // 9 -static const uint64_t SH_FLD_PMON_GROUP_SELECT = 14293; // 2 -static const uint64_t SH_FLD_PMON_GROUP_SELECT_LEN = 14294; // 2 -static const uint64_t SH_FLD_PMON_MUX_BYTE0_0_2 = 14295; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE0_0_2_LEN = 14296; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE1_0_2 = 14297; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE1_0_2_LEN = 14298; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE2_0_2 = 14299; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE2_0_2_LEN = 14300; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE3_0_2 = 14301; // 1 -static const uint64_t SH_FLD_PMON_MUX_BYTE3_0_2_LEN = 14302; // 1 -static const uint64_t SH_FLD_PMSR_OVERRIDE_EN = 14303; // 12 -static const uint64_t SH_FLD_PMU0145_EVENT0_MODE = 14304; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT0_MODE_LEN = 14305; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT1_MODE = 14306; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT1_MODE_LEN = 14307; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT2_MODE = 14308; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT2_MODE_LEN = 14309; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT3_MODE = 14310; // 2 -static const uint64_t SH_FLD_PMU0145_EVENT3_MODE_LEN = 14311; // 2 -static const uint64_t SH_FLD_PMU01_LINK_SELECT = 14312; // 2 -static const uint64_t SH_FLD_PMU0_ENABLE = 14313; // 2 -static const uint64_t SH_FLD_PMU0_SIZE = 14314; // 2 -static const uint64_t SH_FLD_PMU0_SIZE_LEN = 14315; // 2 -static const uint64_t SH_FLD_PMU1_ENABLE = 14316; // 2 -static const uint64_t SH_FLD_PMU1_SIZE = 14317; // 2 -static const uint64_t SH_FLD_PMU1_SIZE_LEN = 14318; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT0_MODE = 14319; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT0_MODE_LEN = 14320; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT1_MODE = 14321; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT1_MODE_LEN = 14322; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT2_MODE = 14323; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT2_MODE_LEN = 14324; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT3_MODE = 14325; // 2 -static const uint64_t SH_FLD_PMU2367_EVENT3_MODE_LEN = 14326; // 2 -static const uint64_t SH_FLD_PMU23_LINK_SELECT = 14327; // 2 -static const uint64_t SH_FLD_PMU2_ENABLE = 14328; // 2 -static const uint64_t SH_FLD_PMU2_SIZE = 14329; // 2 -static const uint64_t SH_FLD_PMU2_SIZE_LEN = 14330; // 2 -static const uint64_t SH_FLD_PMU3_ENABLE = 14331; // 2 -static const uint64_t SH_FLD_PMU3_SIZE = 14332; // 2 -static const uint64_t SH_FLD_PMU3_SIZE_LEN = 14333; // 2 -static const uint64_t SH_FLD_PMU45_LINK_SELECT = 14334; // 2 -static const uint64_t SH_FLD_PMU4_ENABLE = 14335; // 2 -static const uint64_t SH_FLD_PMU5_ENABLE = 14336; // 2 -static const uint64_t SH_FLD_PMU67_LINK_SELECT = 14337; // 2 -static const uint64_t SH_FLD_PMU6_ENABLE = 14338; // 2 -static const uint64_t SH_FLD_PMU7_ENABLE = 14339; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT = 14340; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 14341; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER0_ENABLE = 14342; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT = 14343; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN = 14344; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT = 14345; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT = 14346; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 14347; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER1_ENABLE = 14348; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT = 14349; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN = 14350; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT = 14351; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT = 14352; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 14353; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER2_ENABLE = 14354; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT = 14355; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN = 14356; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT = 14357; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT = 14358; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 14359; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER3_ENABLE = 14360; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT = 14361; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN = 14362; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT = 14363; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER_FREEZE_MODE = 14364; // 2 -static const uint64_t SH_FLD_PMUA_COUNTER_RESET_MODE = 14365; // 2 -static const uint64_t SH_FLD_PMUA_PORT_SELECT = 14366; // 2 -static const uint64_t SH_FLD_PMUA_PORT_SELECT_LEN = 14367; // 2 -static const uint64_t SH_FLD_PMUA_PRESCALER_SELECT = 14368; // 2 -static const uint64_t SH_FLD_PMUA_PRESCALER_SELECT_LEN = 14369; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT = 14370; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 14371; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER0_ENABLE = 14372; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT = 14373; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN = 14374; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT = 14375; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT = 14376; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 14377; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER1_ENABLE = 14378; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT = 14379; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN = 14380; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT = 14381; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT = 14382; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 14383; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER2_ENABLE = 14384; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT = 14385; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN = 14386; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT = 14387; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT = 14388; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 14389; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER3_ENABLE = 14390; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT = 14391; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN = 14392; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT = 14393; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER_FREEZE_MODE = 14394; // 2 -static const uint64_t SH_FLD_PMUB_COUNTER_RESET_MODE = 14395; // 2 -static const uint64_t SH_FLD_PMUB_PORT_SELECT = 14396; // 2 -static const uint64_t SH_FLD_PMUB_PORT_SELECT_LEN = 14397; // 2 -static const uint64_t SH_FLD_PMUB_PRESCALER_SELECT = 14398; // 2 -static const uint64_t SH_FLD_PMUB_PRESCALER_SELECT_LEN = 14399; // 2 -static const uint64_t SH_FLD_PMULET_FREEZE_MODE = 14400; // 7 -static const uint64_t SH_FLD_PMULET_RESET_MODE = 14401; // 2 -static const uint64_t SH_FLD_PMU_BUS_ENABLE = 14402; // 2 -static const uint64_t SH_FLD_PMU_BUS_ENABLE_LEN = 14403; // 2 -static const uint64_t SH_FLD_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD = 14404; // 2 -static const uint64_t SH_FLD_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD = 14405; // 2 -static const uint64_t SH_FLD_PMU_ENABLE = 14406; // 2 -static const uint64_t SH_FLD_PMU_EVENT_SEL_REG_PARITY_ERRHOLD = 14407; // 2 -static const uint64_t SH_FLD_PMU_SELECT_HIGH = 14408; // 2 -static const uint64_t SH_FLD_PMU_SELECT_HIGH_LEN = 14409; // 2 -static const uint64_t SH_FLD_PMU_SELECT_LOW = 14410; // 2 -static const uint64_t SH_FLD_PMU_SELECT_LOW_LEN = 14411; // 2 -static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0 = 14412; // 12 -static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 14413; // 12 -static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1 = 14414; // 12 -static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 14415; // 12 -static const uint64_t SH_FLD_PM_ENTRY_ACK_C0 = 14416; // 12 -static const uint64_t SH_FLD_PM_ENTRY_ACK_C0_ACTUAL = 14417; // 12 -static const uint64_t SH_FLD_PM_ENTRY_ACK_C1 = 14418; // 12 -static const uint64_t SH_FLD_PM_ENTRY_ACK_C1_ACTUAL = 14419; // 12 -static const uint64_t SH_FLD_PM_ERROR = 14420; // 6 -static const uint64_t SH_FLD_PM_EXIT_C0 = 14421; // 12 -static const uint64_t SH_FLD_PM_EXIT_C0_ACTUAL = 14422; // 12 -static const uint64_t SH_FLD_PM_EXIT_C1 = 14423; // 12 -static const uint64_t SH_FLD_PM_EXIT_C1_ACTUAL = 14424; // 12 -static const uint64_t SH_FLD_PM_STATE_ACTIVE_C0 = 14425; // 12 -static const uint64_t SH_FLD_PM_STATE_ACTIVE_C1 = 14426; // 12 -static const uint64_t SH_FLD_PM_STATE_ALL_HV_C0 = 14427; // 12 -static const uint64_t SH_FLD_PM_STATE_ALL_HV_C1 = 14428; // 12 -static const uint64_t SH_FLD_PM_STATE_C0 = 14429; // 12 -static const uint64_t SH_FLD_PM_STATE_C0_LEN = 14430; // 12 -static const uint64_t SH_FLD_PM_STATE_C1 = 14431; // 12 -static const uint64_t SH_FLD_PM_STATE_C1_LEN = 14432; // 12 -static const uint64_t SH_FLD_POCKET_ND_RATE1 = 14433; // 12 -static const uint64_t SH_FLD_POCKET_ND_RATE1_LEN = 14434; // 12 -static const uint64_t SH_FLD_POCKET_RATE1 = 14435; // 12 -static const uint64_t SH_FLD_POCKET_RATE1_LEN = 14436; // 12 -static const uint64_t SH_FLD_POCKET_RATE2 = 14437; // 12 -static const uint64_t SH_FLD_POCKET_RATE2_LEN = 14438; // 12 -static const uint64_t SH_FLD_POCKET_RATE3 = 14439; // 12 -static const uint64_t SH_FLD_POCKET_RATE3_LEN = 14440; // 12 -static const uint64_t SH_FLD_POD0 = 14441; // 50 -static const uint64_t SH_FLD_POD0_LEN = 14442; // 50 -static const uint64_t SH_FLD_POD1 = 14443; // 50 -static const uint64_t SH_FLD_POD10 = 14444; // 50 -static const uint64_t SH_FLD_POD10_LEN = 14445; // 50 -static const uint64_t SH_FLD_POD1_LEN = 14446; // 50 -static const uint64_t SH_FLD_POD2 = 14447; // 50 -static const uint64_t SH_FLD_POD2_LEN = 14448; // 50 -static const uint64_t SH_FLD_POD3 = 14449; // 50 -static const uint64_t SH_FLD_POD3_LEN = 14450; // 50 -static const uint64_t SH_FLD_POD4 = 14451; // 50 -static const uint64_t SH_FLD_POD4_LEN = 14452; // 50 -static const uint64_t SH_FLD_POD5 = 14453; // 50 -static const uint64_t SH_FLD_POD5_LEN = 14454; // 50 -static const uint64_t SH_FLD_POD6 = 14455; // 50 -static const uint64_t SH_FLD_POD6_LEN = 14456; // 50 -static const uint64_t SH_FLD_POD7 = 14457; // 50 -static const uint64_t SH_FLD_POD7_LEN = 14458; // 50 -static const uint64_t SH_FLD_POD8 = 14459; // 50 -static const uint64_t SH_FLD_POD8_LEN = 14460; // 50 -static const uint64_t SH_FLD_POD9 = 14461; // 50 -static const uint64_t SH_FLD_POD9_LEN = 14462; // 50 -static const uint64_t SH_FLD_POINTER = 14463; // 2 -static const uint64_t SH_FLD_POINTER_LEN = 14464; // 2 -static const uint64_t SH_FLD_POLLING_TIMEOUT_SEL = 14465; // 6 -static const uint64_t SH_FLD_POLLING_TIMEOUT_SEL_LEN = 14466; // 6 -static const uint64_t SH_FLD_POLL_BCST_RTY_MON = 14467; // 1 -static const uint64_t SH_FLD_POLL_DONE = 14468; // 1 -static const uint64_t SH_FLD_POOL = 14469; // 1 -static const uint64_t SH_FLD_POOL_LEN = 14470; // 1 -static const uint64_t SH_FLD_PORT0_ERROR_CODE = 14471; // 3 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_0 = 14472; // 1 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_0_LEN = 14473; // 1 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_1 = 14474; // 2 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_1_LEN = 14475; // 2 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_2 = 14476; // 3 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_2_LEN = 14477; // 3 -static const uint64_t SH_FLD_PORT0_ERROR_CODE_LEN = 14478; // 3 -static const uint64_t SH_FLD_PORT1_ERROR_CODE = 14479; // 3 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_0 = 14480; // 1 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_0_LEN = 14481; // 1 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_1 = 14482; // 2 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_1_LEN = 14483; // 2 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_2 = 14484; // 3 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_2_LEN = 14485; // 3 -static const uint64_t SH_FLD_PORT1_ERROR_CODE_LEN = 14486; // 3 -static const uint64_t SH_FLD_PORT2_ERROR_CODE = 14487; // 3 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_0 = 14488; // 1 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_0_LEN = 14489; // 1 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_1 = 14490; // 2 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_1_LEN = 14491; // 2 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_2 = 14492; // 3 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_2_LEN = 14493; // 3 -static const uint64_t SH_FLD_PORT2_ERROR_CODE_LEN = 14494; // 3 -static const uint64_t SH_FLD_PORT3_ERROR_CODE = 14495; // 3 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_0 = 14496; // 1 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_0_LEN = 14497; // 1 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_1 = 14498; // 2 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_1_LEN = 14499; // 2 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_2 = 14500; // 3 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_2_LEN = 14501; // 3 -static const uint64_t SH_FLD_PORT3_ERROR_CODE_LEN = 14502; // 3 -static const uint64_t SH_FLD_PORT4_ERROR_CODE = 14503; // 3 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_0 = 14504; // 1 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_0_LEN = 14505; // 1 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_1 = 14506; // 2 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_1_LEN = 14507; // 2 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_2 = 14508; // 3 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_2_LEN = 14509; // 3 -static const uint64_t SH_FLD_PORT4_ERROR_CODE_LEN = 14510; // 3 -static const uint64_t SH_FLD_PORT5_ERROR_CODE = 14511; // 3 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_0 = 14512; // 1 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_0_LEN = 14513; // 1 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_1 = 14514; // 2 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_1_LEN = 14515; // 2 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_2 = 14516; // 3 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_2_LEN = 14517; // 3 -static const uint64_t SH_FLD_PORT5_ERROR_CODE_LEN = 14518; // 3 -static const uint64_t SH_FLD_PORT6_ERROR_CODE = 14519; // 3 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_0 = 14520; // 1 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_0_LEN = 14521; // 1 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_1 = 14522; // 2 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_1_LEN = 14523; // 2 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_2 = 14524; // 3 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_2_LEN = 14525; // 3 -static const uint64_t SH_FLD_PORT6_ERROR_CODE_LEN = 14526; // 3 -static const uint64_t SH_FLD_PORT7_ERROR_CODE = 14527; // 3 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_0 = 14528; // 1 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_0_LEN = 14529; // 1 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_1 = 14530; // 2 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_1_LEN = 14531; // 2 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_2 = 14532; // 3 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_2_LEN = 14533; // 3 -static const uint64_t SH_FLD_PORT7_ERROR_CODE_LEN = 14534; // 3 -static const uint64_t SH_FLD_PORTPOWERDOWN = 14535; // 8 -static const uint64_t SH_FLD_PORTSEL = 14536; // 2 -static const uint64_t SH_FLD_PORTSEL_LEN = 14537; // 2 -static const uint64_t SH_FLD_PORT_0_ENABLE = 14538; // 1 -static const uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP = 14539; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 14540; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP = 14541; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 14542; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE = 14543; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP = 14544; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 14545; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 14546; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 14547; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE = 14548; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 14549; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14550; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE = 14551; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP = 14552; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 14553; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 14554; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 14555; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 14556; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14557; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP = 14558; // 2 -static const uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 14559; // 2 -static const uint64_t SH_FLD_PORT_1_ENABLE = 14560; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP = 14561; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 14562; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP = 14563; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 14564; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE = 14565; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP = 14566; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 14567; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 14568; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 14569; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE = 14570; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 14571; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14572; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE = 14573; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP = 14574; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 14575; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 14576; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 14577; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 14578; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14579; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP = 14580; // 2 -static const uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 14581; // 2 -static const uint64_t SH_FLD_PORT_2_ENABLE = 14582; // 3 -static const uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP = 14583; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 14584; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP = 14585; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 14586; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE = 14587; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP = 14588; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 14589; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 14590; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 14591; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE = 14592; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 14593; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14594; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE = 14595; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP = 14596; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 14597; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 14598; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 14599; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 14600; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14601; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP = 14602; // 2 -static const uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 14603; // 2 -static const uint64_t SH_FLD_PORT_3_ENABLE = 14604; // 3 -static const uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP = 14605; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 14606; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP = 14607; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 14608; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE = 14609; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP = 14610; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 14611; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 14612; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 14613; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE = 14614; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 14615; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14616; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE = 14617; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP = 14618; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 14619; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 14620; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 14621; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 14622; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14623; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP = 14624; // 2 -static const uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 14625; // 2 -static const uint64_t SH_FLD_PORT_4_ENABLE = 14626; // 3 -static const uint64_t SH_FLD_PORT_5_ENABLE = 14627; // 3 -static const uint64_t SH_FLD_PORT_6_ENABLE = 14628; // 3 -static const uint64_t SH_FLD_PORT_7_ENABLE = 14629; // 3 -static const uint64_t SH_FLD_PORT_ENABLE = 14630; // 3 -static const uint64_t SH_FLD_PORT_ERROR_RESET = 14631; // 1 -static const uint64_t SH_FLD_PORT_ERROR_RESET_1 = 14632; // 2 -static const uint64_t SH_FLD_PORT_ERROR_RESET_2 = 14633; // 3 -static const uint64_t SH_FLD_PORT_ERROR_RESET_3 = 14634; // 3 -static const uint64_t SH_FLD_PORT_ERROR_RESET_4 = 14635; // 3 -static const uint64_t SH_FLD_PORT_ERROR_RESET_5 = 14636; // 3 -static const uint64_t SH_FLD_PORT_ERROR_RESET_6 = 14637; // 3 -static const uint64_t SH_FLD_PORT_ERROR_RESET_7 = 14638; // 3 -static const uint64_t SH_FLD_PORT_FAIL = 14639; // 8 -static const uint64_t SH_FLD_PORT_GENERAL_RESET = 14640; // 1 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_1 = 14641; // 2 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_2 = 14642; // 3 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_3 = 14643; // 3 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_4 = 14644; // 3 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_5 = 14645; // 3 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_6 = 14646; // 3 -static const uint64_t SH_FLD_PORT_GENERAL_RESET_7 = 14647; // 3 -static const uint64_t SH_FLD_PORT_NUMBER_0 = 14648; // 2 -static const uint64_t SH_FLD_PORT_NUMBER_0_LEN = 14649; // 2 -static const uint64_t SH_FLD_PORT_NUMBER_1 = 14650; // 1 -static const uint64_t SH_FLD_PORT_NUMBER_1_LEN = 14651; // 1 -static const uint64_t SH_FLD_PORT_NUMBER_2 = 14652; // 1 -static const uint64_t SH_FLD_PORT_NUMBER_2_LEN = 14653; // 1 -static const uint64_t SH_FLD_PORT_NUMBER_3 = 14654; // 1 -static const uint64_t SH_FLD_PORT_NUMBER_3_LEN = 14655; // 1 -static const uint64_t SH_FLD_PORT_SEL = 14656; // 1 -static const uint64_t SH_FLD_PORT_SEL_LEN = 14657; // 1 -static const uint64_t SH_FLD_POWDN_DLY = 14658; // 30 -static const uint64_t SH_FLD_POWDN_DLY_LEN = 14659; // 30 -static const uint64_t SH_FLD_POWERBUS_DATA_HANG_ERROR = 14660; // 4 -static const uint64_t SH_FLD_POWERBUS_HANG_ERROR = 14661; // 4 -static const uint64_t SH_FLD_POWERBUS_INTERFACE_PE = 14662; // 4 -static const uint64_t SH_FLD_POWERBUS_MISC_ERROR = 14663; // 4 -static const uint64_t SH_FLD_POWERBUS_PROTOCOL_ERROR = 14664; // 4 -static const uint64_t SH_FLD_POWER_MANAGEMENT_INTERRUPT = 14665; // 1 -static const uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N = 14666; // 96 -static const uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N_LEN = 14667; // 96 -static const uint64_t SH_FLD_POWER_UP_CNTR_REF = 14668; // 1 -static const uint64_t SH_FLD_POWER_UP_CNTR_REF_LEN = 14669; // 1 -static const uint64_t SH_FLD_POWUP_DLY = 14670; // 30 -static const uint64_t SH_FLD_POWUP_DLY_LEN = 14671; // 30 -static const uint64_t SH_FLD_PPC405_CHIP_RESET = 14672; // 1 -static const uint64_t SH_FLD_PPC405_CHIP_RESET_MASK = 14673; // 1 -static const uint64_t SH_FLD_PPC405_CORE_RESET = 14674; // 1 -static const uint64_t SH_FLD_PPC405_CORE_RESET_MASK = 14675; // 1 -static const uint64_t SH_FLD_PPC405_DBGMSRWE = 14676; // 1 -static const uint64_t SH_FLD_PPC405_DBGMSRWE_MASK = 14677; // 1 -static const uint64_t SH_FLD_PPC405_DBGSTOPACK = 14678; // 1 -static const uint64_t SH_FLD_PPC405_DBGSTOPACK_MASK = 14679; // 1 -static const uint64_t SH_FLD_PPC405_HALT = 14680; // 1 -static const uint64_t SH_FLD_PPC405_SYSTEM_RESET = 14681; // 1 -static const uint64_t SH_FLD_PPC405_SYSTEM_RESET_MASK = 14682; // 1 -static const uint64_t SH_FLD_PPE_BREAKPOINT_ERROR = 14683; // 12 -static const uint64_t SH_FLD_PPE_DEBUG_TRIGGER = 14684; // 12 -static const uint64_t SH_FLD_PPE_EXTERNAL_ERROR = 14685; // 12 -static const uint64_t SH_FLD_PPE_GCR = 14686; // 4 -static const uint64_t SH_FLD_PPE_HALTED = 14687; // 12 -static const uint64_t SH_FLD_PPE_INTERNAL_ERROR = 14688; // 12 -static const uint64_t SH_FLD_PPE_PROGRESS_ERROR = 14689; // 12 -static const uint64_t SH_FLD_PPE_RD_ACK_DEAD = 14690; // 12 -static const uint64_t SH_FLD_PPE_RD_CRESP_ADDR_ERR = 14691; // 12 -static const uint64_t SH_FLD_PPE_WATCHDOG = 14692; // 12 -static const uint64_t SH_FLD_PPE_WR_ACK_DEAD = 14693; // 12 -static const uint64_t SH_FLD_PPE_WR_CRESP_ADDR_ERR = 14694; // 12 -static const uint64_t SH_FLD_PPE_XIRAMEDR_EDR = 14695; // 4 -static const uint64_t SH_FLD_PPE_XIRAMEDR_EDR_LEN = 14696; // 4 -static const uint64_t SH_FLD_PPE_XIRAMGA_IR = 14697; // 4 -static const uint64_t SH_FLD_PPE_XIRAMGA_IR_LEN = 14698; // 4 -static const uint64_t SH_FLD_PPE_XIRAMRA_SPRG0 = 14699; // 4 -static const uint64_t SH_FLD_PPE_XIRAMRA_SPRG0_LEN = 14700; // 4 -static const uint64_t SH_FLD_PPE_XIXCR_XCR = 14701; // 8 -static const uint64_t SH_FLD_PPE_XIXCR_XCR_LEN = 14702; // 8 -static const uint64_t SH_FLD_PPM_SPARE_OUT_C0 = 14703; // 12 -static const uint64_t SH_FLD_PPM_SPARE_OUT_C1 = 14704; // 12 -static const uint64_t SH_FLD_PPM_WRITE_DISABLE = 14705; // 24 -static const uint64_t SH_FLD_PPM_WRITE_OVERRIDE = 14706; // 24 -static const uint64_t SH_FLD_PQ_STATE = 14707; // 1 -static const uint64_t SH_FLD_PQ_STATE_LEN = 14708; // 1 -static const uint64_t SH_FLD_PRB0 = 14709; // 12 -static const uint64_t SH_FLD_PRB1 = 14710; // 12 -static const uint64_t SH_FLD_PRBS = 14711; // 2 -static const uint64_t SH_FLD_PRBS_CHECK_SYNC = 14712; // 72 -static const uint64_t SH_FLD_PRBS_INVERT = 14713; // 2 -static const uint64_t SH_FLD_PRBS_LEN = 14714; // 2 -static const uint64_t SH_FLD_PRBS_PHASE_SELECT = 14715; // 2 -static const uint64_t SH_FLD_PRBS_PHASE_SELECT_LEN = 14716; // 2 -static const uint64_t SH_FLD_PRBS_RXBIST_MODE = 14717; // 72 -static const uint64_t SH_FLD_PRBS_SCRAMBLE_MODE = 14718; // 144 -static const uint64_t SH_FLD_PRBS_SCRAMBLE_MODE_LEN = 14719; // 144 -static const uint64_t SH_FLD_PRBS_SEED_DDC = 14720; // 72 -static const uint64_t SH_FLD_PRBS_SEED_DFE = 14721; // 72 -static const uint64_t SH_FLD_PRBS_SEED_MODE = 14722; // 4 -static const uint64_t SH_FLD_PRBS_SEED_VALUE_0_15 = 14723; // 140 -static const uint64_t SH_FLD_PRBS_SEED_VALUE_0_15_LEN = 14724; // 140 -static const uint64_t SH_FLD_PRBS_SEED_VALUE_16_22 = 14725; // 140 -static const uint64_t SH_FLD_PRBS_SEED_VALUE_16_22_LEN = 14726; // 140 -static const uint64_t SH_FLD_PRBS_SLS_EXPECT = 14727; // 4 -static const uint64_t SH_FLD_PRBS_SLS_EXPECT_LEN = 14728; // 4 -static const uint64_t SH_FLD_PRBS_SYNC_MODE = 14729; // 72 -static const uint64_t SH_FLD_PRBS_TEST_DATA = 14730; // 120 -static const uint64_t SH_FLD_PRBS_TEST_DATA_LEN = 14731; // 120 -static const uint64_t SH_FLD_PRECISE_DIR_FLUSH_FAILED = 14732; // 2 -static const uint64_t SH_FLD_PRECISE_DIR_SIZE = 14733; // 2 -static const uint64_t SH_FLD_PRECISE_DIR_SIZE_LEN = 14734; // 2 -static const uint64_t SH_FLD_PRECLUDE = 14735; // 1 -static const uint64_t SH_FLD_PREF2DMD = 14736; // 1 -static const uint64_t SH_FLD_PREFETCH = 14737; // 6 -static const uint64_t SH_FLD_PREFETCH_CHANNEL_CNT = 14738; // 1 -static const uint64_t SH_FLD_PREFETCH_CHANNEL_CNT_LEN = 14739; // 1 -static const uint64_t SH_FLD_PREFETCH_DISABLE = 14740; // 6 -static const uint64_t SH_FLD_PREFETCH_DISTANCE = 14741; // 6 -static const uint64_t SH_FLD_PREFETCH_DISTANCE_LEN = 14742; // 6 -static const uint64_t SH_FLD_PREFETCH_LIMIT = 14743; // 8 -static const uint64_t SH_FLD_PREFETCH_LIMIT_LEN = 14744; // 8 -static const uint64_t SH_FLD_PREFEVOD = 14745; // 1 -static const uint64_t SH_FLD_PREF_DEPTH = 14746; // 1 -static const uint64_t SH_FLD_PREF_DEPTH_LEN = 14747; // 1 -static const uint64_t SH_FLD_PREF_THRSH0 = 14748; // 1 -static const uint64_t SH_FLD_PREF_THRSH0_LEN = 14749; // 1 -static const uint64_t SH_FLD_PREF_THRSH1 = 14750; // 1 -static const uint64_t SH_FLD_PREF_THRSH1_LEN = 14751; // 1 -static const uint64_t SH_FLD_PREF_THRSH2 = 14752; // 1 -static const uint64_t SH_FLD_PREF_THRSH2_LEN = 14753; // 1 -static const uint64_t SH_FLD_PREF_THRSH3 = 14754; // 1 -static const uint64_t SH_FLD_PREF_THRSH3_LEN = 14755; // 1 -static const uint64_t SH_FLD_PREF_TIMEOUT = 14756; // 1 -static const uint64_t SH_FLD_PREF_TIMEOUT_LEN = 14757; // 1 -static const uint64_t SH_FLD_PRESCALAR_SEL0 = 14758; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL0_LEN = 14759; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL1 = 14760; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL1_LEN = 14761; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL2 = 14762; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL2_LEN = 14763; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL3 = 14764; // 2 -static const uint64_t SH_FLD_PRESCALAR_SEL3_LEN = 14765; // 2 -static const uint64_t SH_FLD_PRESCALER_SEL = 14766; // 1 -static const uint64_t SH_FLD_PRESCALER_SEL_LEN = 14767; // 1 -static const uint64_t SH_FLD_PRESCALE_C0 = 14768; // 9 -static const uint64_t SH_FLD_PRESCALE_C0_LEN = 14769; // 9 -static const uint64_t SH_FLD_PRESCALE_C1 = 14770; // 9 -static const uint64_t SH_FLD_PRESCALE_C1_LEN = 14771; // 9 -static const uint64_t SH_FLD_PRESCALE_C2 = 14772; // 9 -static const uint64_t SH_FLD_PRESCALE_C2_LEN = 14773; // 9 -static const uint64_t SH_FLD_PRESCALE_C3 = 14774; // 9 -static const uint64_t SH_FLD_PRESCALE_C3_LEN = 14775; // 9 -static const uint64_t SH_FLD_PRESP_RTY_OTHER = 14776; // 2 -static const uint64_t SH_FLD_PREVENT_MTP_AT_DEM_IN_PIPE = 14777; // 1 -static const uint64_t SH_FLD_PRGM_ADDR = 14778; // 1 -static const uint64_t SH_FLD_PRGM_ADDR_LEN = 14779; // 1 -static const uint64_t SH_FLD_PRGSM_BUSY = 14780; // 24 -static const uint64_t SH_FLD_PRGSM_BUSY_ON_THIS = 14781; // 24 -static const uint64_t SH_FLD_PRG_BIT_LOCATION = 14782; // 1 -static const uint64_t SH_FLD_PRG_BIT_LOCATION_LEN = 14783; // 1 -static const uint64_t SH_FLD_PRI = 14784; // 8 -static const uint64_t SH_FLD_PRIORITY = 14785; // 18 -static const uint64_t SH_FLD_PRIORITY_ENABLE = 14786; // 6 -static const uint64_t SH_FLD_PRIORITY_LEN = 14787; // 6 -static const uint64_t SH_FLD_PRIORITY_LIMIT_0_3 = 14788; // 1 -static const uint64_t SH_FLD_PRIORITY_LIMIT_0_3_LEN = 14789; // 1 -static const uint64_t SH_FLD_PRIORITY_LPID = 14790; // 6 -static const uint64_t SH_FLD_PRIORITY_LPID_LEN = 14791; // 6 -static const uint64_t SH_FLD_PRIORITY_PID = 14792; // 6 -static const uint64_t SH_FLD_PRIORITY_PID_LEN = 14793; // 6 -static const uint64_t SH_FLD_PRIORITY_PRIMAX = 14794; // 3 -static const uint64_t SH_FLD_PRIORITY_PRIMAX_LEN = 14795; // 3 -static const uint64_t SH_FLD_PRIORITY_QUEUED = 14796; // 6 -static const uint64_t SH_FLD_PRIORITY_QUEUED_LEN = 14797; // 6 -static const uint64_t SH_FLD_PRIORITY_READ_OFFSET = 14798; // 6 -static const uint64_t SH_FLD_PRIORITY_READ_OFFSET_LEN = 14799; // 6 -static const uint64_t SH_FLD_PRIORITY_SIZE = 14800; // 6 -static const uint64_t SH_FLD_PRIORITY_SIZE_LEN = 14801; // 6 -static const uint64_t SH_FLD_PRIORITY_TID = 14802; // 6 -static const uint64_t SH_FLD_PRIORITY_TID_LEN = 14803; // 6 -static const uint64_t SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE = 14804; // 1 -static const uint64_t SH_FLD_PRI_LEN = 14805; // 8 -static const uint64_t SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE = 14806; // 1 -static const uint64_t SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE = 14807; // 1 -static const uint64_t SH_FLD_PRI_M_PATH_SELECT = 14808; // 2 -static const uint64_t SH_FLD_PRI_M_S_DRAWER_SELECT = 14809; // 2 -static const uint64_t SH_FLD_PRI_M_S_SELECT = 14810; // 2 -static const uint64_t SH_FLD_PRI_SEC_SELECT = 14811; // 1 -static const uint64_t SH_FLD_PRI_SEC_SELECT_LEN = 14812; // 1 -static const uint64_t SH_FLD_PRI_SELECT = 14813; // 1 -static const uint64_t SH_FLD_PRI_STATE_MACHINE_RESET = 14814; // 6 -static const uint64_t SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE = 14815; // 1 -static const uint64_t SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE = 14816; // 1 -static const uint64_t SH_FLD_PRI_S_PATH_SELECT = 14817; // 1 -static const uint64_t SH_FLD_PRI_V = 14818; // 8 -static const uint64_t SH_FLD_PROBE_0_TOGGLE_ENABLE = 14819; // 1 -static const uint64_t SH_FLD_PROBE_1_TOGGLE_ENABLE = 14820; // 1 -static const uint64_t SH_FLD_PROBE_2_TOGGLE_ENABLE = 14821; // 1 -static const uint64_t SH_FLD_PROBE_3_TOGGLE_ENABLE = 14822; // 1 -static const uint64_t SH_FLD_PROC_RCVY_AGAIN = 14823; // 96 -static const uint64_t SH_FLD_PROC_RCVY_DONE = 14824; // 96 -static const uint64_t SH_FLD_PROGRAM_ENABLE = 14825; // 1 -static const uint64_t SH_FLD_PROGRESS_ERROR = 14826; // 1 -static const uint64_t SH_FLD_PROG_REQ_DELAY = 14827; // 1 -static const uint64_t SH_FLD_PROG_REQ_DELAY_LEN = 14828; // 1 -static const uint64_t SH_FLD_PROTECTION_CHECK = 14829; // 1 -static const uint64_t SH_FLD_PROTOCOL = 14830; // 8 -static const uint64_t SH_FLD_PROTOCOL_CHECKSTOP = 14831; // 2 -static const uint64_t SH_FLD_PROTOCOL_ERROR = 14832; // 45 -static const uint64_t SH_FLD_PROTOCOL_LEN = 14833; // 8 -static const uint64_t SH_FLD_PROT_EX_SPARE0 = 14834; // 1 -static const uint64_t SH_FLD_PROT_EX_SPARE1 = 14835; // 1 -static const uint64_t SH_FLD_PROT_TP_SPARE0 = 14836; // 1 -static const uint64_t SH_FLD_PROT_TP_SPARE1 = 14837; // 1 -static const uint64_t SH_FLD_PROT_TP_SPARE2 = 14838; // 1 -static const uint64_t SH_FLD_PRPG_A_VAL = 14839; // 43 -static const uint64_t SH_FLD_PRPG_A_VAL_LEN = 14840; // 43 -static const uint64_t SH_FLD_PRPG_B_VAL = 14841; // 43 -static const uint64_t SH_FLD_PRPG_B_VAL_LEN = 14842; // 43 -static const uint64_t SH_FLD_PRPG_MODE = 14843; // 43 -static const uint64_t SH_FLD_PRPG_VALUE = 14844; // 43 -static const uint64_t SH_FLD_PRPG_VALUE_LEN = 14845; // 43 -static const uint64_t SH_FLD_PRPG_WEIGHTING = 14846; // 43 -static const uint64_t SH_FLD_PRPG_WEIGHTING_LEN = 14847; // 43 -static const uint64_t SH_FLD_PRS = 14848; // 8 -static const uint64_t SH_FLD_PRV_BUS0_STG2_SEL = 14849; // 1 -static const uint64_t SH_FLD_PRV_BUS1_STG2_SEL = 14850; // 1 -static const uint64_t SH_FLD_PR_BUMP_SL_1UI = 14851; // 120 -static const uint64_t SH_FLD_PR_BUMP_SR_1UI = 14852; // 120 -static const uint64_t SH_FLD_PR_BUMP_TO_CENTER = 14853; // 72 -static const uint64_t SH_FLD_PR_BUMP_TO_EDGE_A = 14854; // 120 -static const uint64_t SH_FLD_PR_BUMP_TO_EDGE_B = 14855; // 48 -static const uint64_t SH_FLD_PR_COARSE_MODE_EN = 14856; // 48 -static const uint64_t SH_FLD_PR_COARSE_MODE_TIMER_SEL = 14857; // 48 -static const uint64_t SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN = 14858; // 48 -static const uint64_t SH_FLD_PR_DATA_A_OFFSET = 14859; // 120 -static const uint64_t SH_FLD_PR_DATA_A_OFFSET_LEN = 14860; // 120 -static const uint64_t SH_FLD_PR_DATA_B_OFFSET = 14861; // 48 -static const uint64_t SH_FLD_PR_DATA_B_OFFSET_LEN = 14862; // 48 -static const uint64_t SH_FLD_PR_DDC_A = 14863; // 120 -static const uint64_t SH_FLD_PR_DDC_B = 14864; // 48 -static const uint64_t SH_FLD_PR_EDGE_TRACK_CNTL = 14865; // 120 -static const uint64_t SH_FLD_PR_EDGE_TRACK_CNTL_LEN = 14866; // 120 -static const uint64_t SH_FLD_PR_FW_INERTIA_AMT = 14867; // 48 -static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_COARSE = 14868; // 48 -static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN = 14869; // 48 -static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_LEN = 14870; // 48 -static const uint64_t SH_FLD_PR_FW_OFF = 14871; // 48 -static const uint64_t SH_FLD_PR_HALFRATE_MODE = 14872; // 48 -static const uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE = 14873; // 120 -static const uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN = 14874; // 120 -static const uint64_t SH_FLD_PR_INVALID_LOCK_COARSE_EN = 14875; // 48 -static const uint64_t SH_FLD_PR_INVALID_LOCK_FILTER_EN = 14876; // 120 -static const uint64_t SH_FLD_PR_IQ_RES_SEL = 14877; // 120 -static const uint64_t SH_FLD_PR_IQ_RES_SEL_LEN = 14878; // 120 -static const uint64_t SH_FLD_PR_LOCK_DONE = 14879; // 120 -static const uint64_t SH_FLD_PR_PHASE_STEP = 14880; // 120 -static const uint64_t SH_FLD_PR_PHASE_STEP_COARSE = 14881; // 48 -static const uint64_t SH_FLD_PR_PHASE_STEP_COARSE_LEN = 14882; // 48 -static const uint64_t SH_FLD_PR_PHASE_STEP_LEN = 14883; // 120 -static const uint64_t SH_FLD_PR_RESET = 14884; // 48 -static const uint64_t SH_FLD_PR_TRACE_DDC_SM = 14885; // 120 -static const uint64_t SH_FLD_PR_TRACE_DDC_SM_LEN = 14886; // 120 -static const uint64_t SH_FLD_PR_TRACE_DDC_STOP = 14887; // 120 -static const uint64_t SH_FLD_PR_TRACE_WOBBLE_SM = 14888; // 120 -static const uint64_t SH_FLD_PR_TRACE_WOBBLE_SM_LEN = 14889; // 120 -static const uint64_t SH_FLD_PR_TRACE_WOBBLE_STOP = 14890; // 120 -static const uint64_t SH_FLD_PR_USE_DFE_CLOCK_A = 14891; // 120 -static const uint64_t SH_FLD_PR_USE_DFE_CLOCK_B = 14892; // 48 -static const uint64_t SH_FLD_PR_WOBBLE_A = 14893; // 120 -static const uint64_t SH_FLD_PR_WOBBLE_B = 14894; // 48 -static const uint64_t SH_FLD_PR_WOBBLE_EDGE = 14895; // 48 -static const uint64_t SH_FLD_PSAVE_ANA_REQ_DIS = 14896; // 48 -static const uint64_t SH_FLD_PSAVE_DIG_REQ_DIS = 14897; // 48 -static const uint64_t SH_FLD_PSAVE_FENCE_ENABLE = 14898; // 4 -static const uint64_t SH_FLD_PSAVE_INVALID_STATE = 14899; // 6 -static const uint64_t SH_FLD_PSAVE_MODE_DISABLE = 14900; // 140 -static const uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL = 14901; // 4 -static const uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL_LEN = 14902; // 4 -static const uint64_t SH_FLD_PSAVE_REQ_DIS = 14903; // 48 -static const uint64_t SH_FLD_PSAVE_RESYNC_DISABLE = 14904; // 72 -static const uint64_t SH_FLD_PSAVE_TIMER_WAKEUP_MODE = 14905; // 4 -static const uint64_t SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE = 14906; // 8 -static const uint64_t SH_FLD_PSCR_OVERRIDE_EN = 14907; // 12 -static const uint64_t SH_FLD_PSEG_MAIN_EN = 14908; // 6 -static const uint64_t SH_FLD_PSEG_MAIN_EN_LEN = 14909; // 6 -static const uint64_t SH_FLD_PSEG_MARGINPD_EN = 14910; // 6 -static const uint64_t SH_FLD_PSEG_MARGINPD_EN_LEN = 14911; // 6 -static const uint64_t SH_FLD_PSEG_MARGINPU_EN = 14912; // 6 -static const uint64_t SH_FLD_PSEG_MARGINPU_EN_LEN = 14913; // 6 -static const uint64_t SH_FLD_PSEG_POST_EN = 14914; // 2 -static const uint64_t SH_FLD_PSEG_POST_EN_LEN = 14915; // 2 -static const uint64_t SH_FLD_PSEG_POST_SEL = 14916; // 2 -static const uint64_t SH_FLD_PSEG_POST_SEL_LEN = 14917; // 2 -static const uint64_t SH_FLD_PSEG_PRE_EN = 14918; // 6 -static const uint64_t SH_FLD_PSEG_PRE_EN_LEN = 14919; // 6 -static const uint64_t SH_FLD_PSEG_PRE_SEL = 14920; // 6 -static const uint64_t SH_FLD_PSEG_PRE_SEL_LEN = 14921; // 6 -static const uint64_t SH_FLD_PSIFSP_ACK_TIMEOUT = 14922; // 1 -static const uint64_t SH_FLD_PSIFSP_DMAR_OUTSTANDING = 14923; // 1 -static const uint64_t SH_FLD_PSIFSP_DMA_ADDR_ERR = 14924; // 1 -static const uint64_t SH_FLD_PSIFSP_DMA_ERR = 14925; // 1 -static const uint64_t SH_FLD_PSIFSP_INT_BUSY = 14926; // 1 -static const uint64_t SH_FLD_PSIFSP_INV_OP = 14927; // 1 -static const uint64_t SH_FLD_PSIFSP_LOAD_OUTSTANDING = 14928; // 1 -static const uint64_t SH_FLD_PSIFSP_MMIO_ADDR_ERR = 14929; // 1 -static const uint64_t SH_FLD_PSIFSP_MMIO_LENGTH_ERR = 14930; // 1 -static const uint64_t SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT = 14931; // 1 -static const uint64_t SH_FLD_PSIFSP_MMIO_TYPE_ERR = 14932; // 1 -static const uint64_t SH_FLD_PSIFSP_PAGE_FAULT = 14933; // 1 -static const uint64_t SH_FLD_PSIFSP_PERR = 14934; // 1 -static const uint64_t SH_FLD_PSIFSP_TCE_EXTENT_ERR = 14935; // 1 -static const uint64_t SH_FLD_PSIHB2FSP_INJ_CONST = 14936; // 1 -static const uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS = 14937; // 1 -static const uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN = 14938; // 1 -static const uint64_t SH_FLD_PSIHB2FSP_INJ_ONCE = 14939; // 1 -static const uint64_t SH_FLD_PSIHB2PB_INJ_CONST = 14940; // 1 -static const uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS = 14941; // 1 -static const uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN = 14942; // 1 -static const uint64_t SH_FLD_PSIHB2PB_INJ_ONCE = 14943; // 1 -static const uint64_t SH_FLD_PSIHBC_RESET = 14944; // 1 -static const uint64_t SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR = 14945; // 1 -static const uint64_t SH_FLD_PSIRFACC_RADDR_PCK = 14946; // 1 -static const uint64_t SH_FLD_PSIRFACC_RCTRL_PCK = 14947; // 1 -static const uint64_t SH_FLD_PSIRFACC_RDL_FSM_PCK = 14948; // 1 -static const uint64_t SH_FLD_PSIRFACC_RFSM_PCK = 14949; // 1 -static const uint64_t SH_FLD_PSIRFACC_RLINK_STATE_LT_02 = 14950; // 1 -static const uint64_t SH_FLD_PSIRFACC_RXSC_PCK = 14951; // 1 -static const uint64_t SH_FLD_PSIRFACC_TADDR_PCK = 14952; // 1 -static const uint64_t SH_FLD_PSIRFACC_TCTRL_PCK = 14953; // 1 -static const uint64_t SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK = 14954; // 1 -static const uint64_t SH_FLD_PSIRFACC_TDL_FSM_PCK = 14955; // 1 -static const uint64_t SH_FLD_PSIRFACC_TDL_RETRY_ERR = 14956; // 1 -static const uint64_t SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK = 14957; // 1 -static const uint64_t SH_FLD_PSIRFACC_TFSM_PCK = 14958; // 1 -static const uint64_t SH_FLD_PSIRFACC_TXSC_PCK = 14959; // 1 -static const uint64_t SH_FLD_PSIRXBFF_DATAO_PCK = 14960; // 1 -static const uint64_t SH_FLD_PSIRXBFF_DATA_PCK = 14961; // 1 -static const uint64_t SH_FLD_PSIRXBFF_RFC_PCK = 14962; // 1 -static const uint64_t SH_FLD_PSIRXEI_SHIFT_PCK = 14963; // 1 -static const uint64_t SH_FLD_PSIRXEI_TRANSMIT_PCK = 14964; // 1 -static const uint64_t SH_FLD_PSIRXINS_DATA_PCK = 14965; // 1 -static const uint64_t SH_FLD_PSIRXINS_OVERRUN = 14966; // 1 -static const uint64_t SH_FLD_PSIRXINS_RFGSHIFT_PCK = 14967; // 1 -static const uint64_t SH_FLD_PSIRXINS_RZRTMP_PCK = 14968; // 1 -static const uint64_t SH_FLD_PSIRXLC_CE_RF = 14969; // 1 -static const uint64_t SH_FLD_PSIRXLC_DATA_BUFF_PCK = 14970; // 1 -static const uint64_t SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N = 14971; // 1 -static const uint64_t SH_FLD_PSIRXLC_DATA_PCK = 14972; // 1 -static const uint64_t SH_FLD_PSIRXLC_FSM_PCK = 14973; // 1 -static const uint64_t SH_FLD_PSIRXLC_RADDR_PCK = 14974; // 1 -static const uint64_t SH_FLD_PSIRXLC_RCTRL_PCK = 14975; // 1 -static const uint64_t SH_FLD_PSIRXLC_UE_RF = 14976; // 1 -static const uint64_t SH_FLD_PSITXBFF_DATA_PCK = 14977; // 1 -static const uint64_t SH_FLD_PSITXBFF_TDO_PCK = 14978; // 1 -static const uint64_t SH_FLD_PSITXBFF_TFC_PCK = 14979; // 1 -static const uint64_t SH_FLD_PSITXEI_SHIFT_PCK = 14980; // 1 -static const uint64_t SH_FLD_PSITXEI_TRANSMIT_PCK = 14981; // 1 -static const uint64_t SH_FLD_PSITXINS_DATA_PCK = 14982; // 1 -static const uint64_t SH_FLD_PSITXINS_PARITY = 14983; // 1 -static const uint64_t SH_FLD_PSITXINS_TZRTMP_PCK = 14984; // 1 -static const uint64_t SH_FLD_PSITXINS_UNDERRUN = 14985; // 1 -static const uint64_t SH_FLD_PSITXLC_CE_GX_2N = 14986; // 1 -static const uint64_t SH_FLD_PSITXLC_CE_RF = 14987; // 1 -static const uint64_t SH_FLD_PSITXLC_DATA_BUFF_PCK = 14988; // 1 -static const uint64_t SH_FLD_PSITXLC_DATA_GXST2_PCK_2N = 14989; // 1 -static const uint64_t SH_FLD_PSITXLC_DATA_GXST3_PCK_2N = 14990; // 1 -static const uint64_t SH_FLD_PSITXLC_FSM_PCK = 14991; // 1 -static const uint64_t SH_FLD_PSITXLC_TADDR_PCK = 14992; // 1 -static const uint64_t SH_FLD_PSITXLC_TCTRL_PCK = 14993; // 1 -static const uint64_t SH_FLD_PSITXLC_TDO_PCK = 14994; // 1 -static const uint64_t SH_FLD_PSITXLC_UE_GX_2N = 14995; // 1 -static const uint64_t SH_FLD_PSITXLC_UE_RF = 14996; // 1 -static const uint64_t SH_FLD_PSI_ALERT1 = 14997; // 1 -static const uint64_t SH_FLD_PSI_ALERT2 = 14998; // 1 -static const uint64_t SH_FLD_PSI_LINK_ENABLE = 14999; // 1 -static const uint64_t SH_FLD_PSI_LINK_INACTIVE_TRANS = 15000; // 1 -static const uint64_t SH_FLD_PSI_RESERVED0 = 15001; // 2 -static const uint64_t SH_FLD_PSI_RESERVED1 = 15002; // 2 -static const uint64_t SH_FLD_PSI_RESERVED2 = 15003; // 2 -static const uint64_t SH_FLD_PSI_RESERVED3 = 15004; // 2 -static const uint64_t SH_FLD_PSI_RESERVED4 = 15005; // 2 -static const uint64_t SH_FLD_PSI_UE = 15006; // 1 -static const uint64_t SH_FLD_PSI_XMIT_ERROR = 15007; // 1 -static const uint64_t SH_FLD_PSL_CMD_SUE = 15008; // 4 -static const uint64_t SH_FLD_PSL_CMD_SUE_ERRHOLD = 15009; // 2 -static const uint64_t SH_FLD_PSL_CMD_UE = 15010; // 4 -static const uint64_t SH_FLD_PSL_CMD_UE_ERRHOLD = 15011; // 2 -static const uint64_t SH_FLD_PSL_CREDIT_TIMEOUT_ERR = 15012; // 4 -static const uint64_t SH_FLD_PSSBRIDGE_ONGOING = 15013; // 1 -static const uint64_t SH_FLD_PSS_HAM = 15014; // 3 -static const uint64_t SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK = 15015; // 1 -static const uint64_t SH_FLD_PSTATE_A_THRESHOLD = 15016; // 24 -static const uint64_t SH_FLD_PSTATE_A_THRESHOLD_LEN = 15017; // 24 -static const uint64_t SH_FLD_PSTATE_B_THRESHOLD = 15018; // 24 -static const uint64_t SH_FLD_PSTATE_B_THRESHOLD_LEN = 15019; // 24 -static const uint64_t SH_FLD_PS_SPARE1 = 15020; // 1 -static const uint64_t SH_FLD_PTAG_MAX_IN_USE = 15021; // 1 -static const uint64_t SH_FLD_PTAG_MAX_IN_USE_LEN = 15022; // 1 -static const uint64_t SH_FLD_PTCR = 15023; // 1 -static const uint64_t SH_FLD_PTCR_LEN = 15024; // 1 -static const uint64_t SH_FLD_PTSPARE6 = 15025; // 2 -static const uint64_t SH_FLD_PTSPARE7 = 15026; // 2 -static const uint64_t SH_FLD_PULL_EMPTY = 15027; // 4 -static const uint64_t SH_FLD_PULL_ENABLE = 15028; // 4 -static const uint64_t SH_FLD_PULL_FULL = 15029; // 4 -static const uint64_t SH_FLD_PULL_INTR_ACTION_0_1 = 15030; // 4 -static const uint64_t SH_FLD_PULL_INTR_ACTION_0_1_LEN = 15031; // 4 -static const uint64_t SH_FLD_PULL_LENGTH = 15032; // 4 -static const uint64_t SH_FLD_PULL_LENGTH_LEN = 15033; // 4 -static const uint64_t SH_FLD_PULL_READ_PTR = 15034; // 4 -static const uint64_t SH_FLD_PULL_READ_PTR_LEN = 15035; // 4 -static const uint64_t SH_FLD_PULL_READ_UNDERFLOW = 15036; // 4 -static const uint64_t SH_FLD_PULL_READ_UNDERFLOW_EN = 15037; // 4 -static const uint64_t SH_FLD_PULL_REGION = 15038; // 4 -static const uint64_t SH_FLD_PULL_REGION_LEN = 15039; // 4 -static const uint64_t SH_FLD_PULL_START = 15040; // 4 -static const uint64_t SH_FLD_PULL_START_LEN = 15041; // 4 -static const uint64_t SH_FLD_PULL_WRITE_OVERFLOW = 15042; // 4 -static const uint64_t SH_FLD_PULL_WRITE_PTR = 15043; // 4 -static const uint64_t SH_FLD_PULL_WRITE_PTR_LEN = 15044; // 4 -static const uint64_t SH_FLD_PULSE1_CNTR = 15045; // 1 -static const uint64_t SH_FLD_PULSE1_CNTR_LEN = 15046; // 1 -static const uint64_t SH_FLD_PULSE2_CNTR = 15047; // 1 -static const uint64_t SH_FLD_PULSE2_CNTR_LEN = 15048; // 1 -static const uint64_t SH_FLD_PULSE_DELAY = 15049; // 43 -static const uint64_t SH_FLD_PULSE_DELAY_LEN = 15050; // 43 -static const uint64_t SH_FLD_PULSE_DROOP_DATA = 15051; // 6 -static const uint64_t SH_FLD_PULSE_DROOP_DATA_LEN = 15052; // 6 -static const uint64_t SH_FLD_PULSE_DROOP_ENABLE = 15053; // 6 -static const uint64_t SH_FLD_PULSE_INPUT_SEL = 15054; // 43 -static const uint64_t SH_FLD_PUMP_MODE = 15055; // 1 -static const uint64_t SH_FLD_PUP_LITE_WAIT_SEL = 15056; // 4 -static const uint64_t SH_FLD_PUP_LITE_WAIT_SEL_LEN = 15057; // 4 -static const uint64_t SH_FLD_PUSH_EMPTY = 15058; // 6 -static const uint64_t SH_FLD_PUSH_ENABLE = 15059; // 6 -static const uint64_t SH_FLD_PUSH_FULL = 15060; // 6 -static const uint64_t SH_FLD_PUSH_INTR_ACTION_0_1 = 15061; // 6 -static const uint64_t SH_FLD_PUSH_INTR_ACTION_0_1_LEN = 15062; // 6 -static const uint64_t SH_FLD_PUSH_LENGTH = 15063; // 6 -static const uint64_t SH_FLD_PUSH_LENGTH_LEN = 15064; // 6 -static const uint64_t SH_FLD_PUSH_READ_PTR = 15065; // 6 -static const uint64_t SH_FLD_PUSH_READ_PTR_LEN = 15066; // 6 -static const uint64_t SH_FLD_PUSH_READ_UNDERFLOW = 15067; // 4 -static const uint64_t SH_FLD_PUSH_REGION = 15068; // 4 -static const uint64_t SH_FLD_PUSH_REGION_LEN = 15069; // 4 -static const uint64_t SH_FLD_PUSH_START = 15070; // 6 -static const uint64_t SH_FLD_PUSH_START_LEN = 15071; // 6 -static const uint64_t SH_FLD_PUSH_WRITE_OVERFLOW = 15072; // 4 -static const uint64_t SH_FLD_PUSH_WRITE_OVERFLOW_EN = 15073; // 4 -static const uint64_t SH_FLD_PUSH_WRITE_PTR = 15074; // 6 -static const uint64_t SH_FLD_PUSH_WRITE_PTR_LEN = 15075; // 6 -static const uint64_t SH_FLD_PU_BIT_ENABLES = 15076; // 1 -static const uint64_t SH_FLD_PU_BIT_ENABLES_LEN = 15077; // 1 -static const uint64_t SH_FLD_PU_CNTL_UNUSED = 15078; // 1 -static const uint64_t SH_FLD_PU_CNTL_UNUSED_LEN = 15079; // 1 -static const uint64_t SH_FLD_PU_COUNTS = 15080; // 8 -static const uint64_t SH_FLD_PU_COUNTS_LEN = 15081; // 8 -static const uint64_t SH_FLD_PVREF_ERROR_EN = 15082; // 1 -static const uint64_t SH_FLD_PVREF_ERROR_EN_LEN = 15083; // 1 -static const uint64_t SH_FLD_PVREF_ERROR_FINE = 15084; // 1 -static const uint64_t SH_FLD_PVREF_ERROR_GROSS = 15085; // 1 -static const uint64_t SH_FLD_PVREF_FAIL = 15086; // 12 -static const uint64_t SH_FLD_PVTN = 15087; // 8 -static const uint64_t SH_FLD_PVTNB = 15088; // 16 -static const uint64_t SH_FLD_PVTNL = 15089; // 8 -static const uint64_t SH_FLD_PVTNL_ENC = 15090; // 1 -static const uint64_t SH_FLD_PVTNL_ENC_LEN = 15091; // 1 -static const uint64_t SH_FLD_PVTNL_LEN = 15092; // 8 -static const uint64_t SH_FLD_PVTN_LEN = 15093; // 8 -static const uint64_t SH_FLD_PVTPB = 15094; // 16 -static const uint64_t SH_FLD_PVTPL = 15095; // 16 -static const uint64_t SH_FLD_PVTPL_ENC = 15096; // 1 -static const uint64_t SH_FLD_PVTPL_ENC_LEN = 15097; // 1 -static const uint64_t SH_FLD_PVTPL_LEN = 15098; // 16 -static const uint64_t SH_FLD_PVT_OVERRIDE = 15099; // 8 -static const uint64_t SH_FLD_PWR0 = 15100; // 12 -static const uint64_t SH_FLD_PWR1 = 15101; // 12 -static const uint64_t SH_FLD_QPPM_ONGOING = 15102; // 24 -static const uint64_t SH_FLD_QPPM_RDATA = 15103; // 24 -static const uint64_t SH_FLD_QPPM_RDATA_LEN = 15104; // 24 -static const uint64_t SH_FLD_QPPM_REG = 15105; // 24 -static const uint64_t SH_FLD_QPPM_REG_LEN = 15106; // 24 -static const uint64_t SH_FLD_QPPM_RNW = 15107; // 24 -static const uint64_t SH_FLD_QPPM_STATUS = 15108; // 24 -static const uint64_t SH_FLD_QPPM_STATUS_LEN = 15109; // 24 -static const uint64_t SH_FLD_QPPM_WDATA = 15110; // 24 -static const uint64_t SH_FLD_QPPM_WDATA_LEN = 15111; // 24 -static const uint64_t SH_FLD_QUA = 15112; // 8 -static const uint64_t SH_FLD_QUAD_CHECKSTOP = 15113; // 12 -static const uint64_t SH_FLD_QUAD_CLK_SB_OVERRIDE = 15114; // 24 -static const uint64_t SH_FLD_QUAD_CLK_SW_OVERRIDE = 15115; // 24 -static const uint64_t SH_FLD_QUAD_SEL = 15116; // 6 -static const uint64_t SH_FLD_QUAD_SEL_LEN = 15117; // 6 -static const uint64_t SH_FLD_QUAD_STOPPED = 15118; // 1 -static const uint64_t SH_FLD_QUAD_STOPPED_LEN = 15119; // 1 -static const uint64_t SH_FLD_QUA_LEN = 15120; // 8 -static const uint64_t SH_FLD_QUA_V = 15121; // 8 -static const uint64_t SH_FLD_QUEUED_RD_EN = 15122; // 12 -static const uint64_t SH_FLD_QUEUED_WR_EN = 15123; // 12 -static const uint64_t SH_FLD_QUEUE_DISABLE = 15124; // 6 -static const uint64_t SH_FLD_QUEUE_NOT_EMPTY = 15125; // 6 -static const uint64_t SH_FLD_QUIESCE = 15126; // 1 -static const uint64_t SH_FLD_QUIESCED = 15127; // 1 -static const uint64_t SH_FLD_QUIESCE_ACHEIVED = 15128; // 1 -static const uint64_t SH_FLD_QUIESCE_AUTO_RESET = 15129; // 1 -static const uint64_t SH_FLD_QUIESCE_DONE = 15130; // 2 -static const uint64_t SH_FLD_QUIESCE_FAILED = 15131; // 1 -static const uint64_t SH_FLD_QUIESCE_PB = 15132; // 1 -static const uint64_t SH_FLD_QUIESCE_REQUEST = 15133; // 1 -static const uint64_t SH_FLD_R = 15134; // 8 -static const uint64_t SH_FLD_R0_COUNT = 15135; // 12 -static const uint64_t SH_FLD_R0_COUNT_LEN = 15136; // 12 -static const uint64_t SH_FLD_R15_BIT_MAP = 15137; // 8 -static const uint64_t SH_FLD_R15_BIT_MAP_LEN = 15138; // 8 -static const uint64_t SH_FLD_R16_BIT_MAP = 15139; // 8 -static const uint64_t SH_FLD_R16_BIT_MAP_LEN = 15140; // 8 -static const uint64_t SH_FLD_R17_BIT_MAP = 15141; // 8 -static const uint64_t SH_FLD_R17_BIT_MAP_LEN = 15142; // 8 -static const uint64_t SH_FLD_R1_COUNT = 15143; // 12 -static const uint64_t SH_FLD_R1_COUNT_LEN = 15144; // 12 -static const uint64_t SH_FLD_R2_COUNT = 15145; // 12 -static const uint64_t SH_FLD_R2_COUNT_LEN = 15146; // 12 -static const uint64_t SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN = 15147; // 2 -static const uint64_t SH_FLD_RAND_ERROR_RATE = 15148; // 5 -static const uint64_t SH_FLD_RAND_ERROR_RATE_LEN = 15149; // 5 -static const uint64_t SH_FLD_RAND_EVENT = 15150; // 1 -static const uint64_t SH_FLD_RAND_EVENT_LEN = 15151; // 1 -static const uint64_t SH_FLD_RANGE = 15152; // 1 -static const uint64_t SH_FLD_RANGE_LEN = 15153; // 1 -static const uint64_t SH_FLD_RANK = 15154; // 8 -static const uint64_t SH_FLD_RANK_LEN = 15155; // 8 -static const uint64_t SH_FLD_RANK_OVERRIDE = 15156; // 8 -static const uint64_t SH_FLD_RANK_OVERRIDE_VALUE = 15157; // 8 -static const uint64_t SH_FLD_RANK_OVERRIDE_VALUE_LEN = 15158; // 8 -static const uint64_t SH_FLD_RANK_PAIR = 15159; // 8 -static const uint64_t SH_FLD_RANK_PAIR_LEN = 15160; // 8 -static const uint64_t SH_FLD_RANK_SM_1HOT = 15161; // 8 -static const uint64_t SH_FLD_RATE = 15162; // 14 -static const uint64_t SH_FLD_RATE_LEN = 15163; // 14 -static const uint64_t SH_FLD_RATIO = 15164; // 2 -static const uint64_t SH_FLD_RATIO_LEN = 15165; // 2 -static const uint64_t SH_FLD_RC = 15166; // 8 -static const uint64_t SH_FLD_RCDAT_RD_PARITY_ERR = 15167; // 12 -static const uint64_t SH_FLD_RCD_CAL_PARITY_ERROR = 15168; // 8 -static const uint64_t SH_FLD_RCD_PARITY_ERROR = 15169; // 16 -static const uint64_t SH_FLD_RCE_COUNT = 15170; // 2 -static const uint64_t SH_FLD_RCE_COUNT_LEN = 15171; // 2 -static const uint64_t SH_FLD_RCE_ETE_ATTN = 15172; // 2 -static const uint64_t SH_FLD_RCMD0_ADDR_PARITY_ERROR = 15173; // 2 -static const uint64_t SH_FLD_RCMD0_ADDR_PERR = 15174; // 1 -static const uint64_t SH_FLD_RCMD0_TTAG_PERR = 15175; // 1 -static const uint64_t SH_FLD_RCMD1_ADDR_PARITY_ERROR = 15176; // 2 -static const uint64_t SH_FLD_RCMD1_ADDR_PERR = 15177; // 1 -static const uint64_t SH_FLD_RCMD1_TTAG_PERR = 15178; // 1 -static const uint64_t SH_FLD_RCMD2_ADDR_PARITY_ERROR = 15179; // 2 -static const uint64_t SH_FLD_RCMD2_ADDR_PERR = 15180; // 1 -static const uint64_t SH_FLD_RCMD2_TTAG_PERR = 15181; // 1 -static const uint64_t SH_FLD_RCMD3_ADDR_PARITY_ERROR = 15182; // 2 -static const uint64_t SH_FLD_RCMD3_ADDR_PERR = 15183; // 1 -static const uint64_t SH_FLD_RCMD3_TTAG_PERR = 15184; // 1 -static const uint64_t SH_FLD_RCMD_ASYNC_IF = 15185; // 8 -static const uint64_t SH_FLD_RCMD_ERR_INJ = 15186; // 8 -static const uint64_t SH_FLD_RCS_RECOVERY_FAILED_ERRHOLD = 15187; // 2 -static const uint64_t SH_FLD_RCS_RECOVERY_TIMEOUT_ERRHOLD = 15188; // 2 -static const uint64_t SH_FLD_RCS_STATE_MACHINE_ERRHOLD = 15189; // 2 -static const uint64_t SH_FLD_RCTRL_CONFIG = 15190; // 8 -static const uint64_t SH_FLD_RCTRL_CONFIG_LEN = 15191; // 8 -static const uint64_t SH_FLD_RCTRL_DEBUG_SEL = 15192; // 4 -static const uint64_t SH_FLD_RCTRL_DEBUG_SEL_LEN = 15193; // 4 -static const uint64_t SH_FLD_RCTRL_WAT_ACTION_SEL = 15194; // 4 -static const uint64_t SH_FLD_RCTRL_WAT_ACTION_SEL_LEN = 15195; // 4 -static const uint64_t SH_FLD_RCVD_POISONED_CIST_DATA = 15196; // 1 -static const uint64_t SH_FLD_RCV_BRDCST_GROUP = 15197; // 1 -static const uint64_t SH_FLD_RCV_BRDCST_GROUP_LEN = 15198; // 1 -static const uint64_t SH_FLD_RCV_CAPTURE = 15199; // 1 -static const uint64_t SH_FLD_RCV_CAPTURE_LEN = 15200; // 1 -static const uint64_t SH_FLD_RCV_CHIPID = 15201; // 1 -static const uint64_t SH_FLD_RCV_CHIPID_LEN = 15202; // 1 -static const uint64_t SH_FLD_RCV_CREDIT_OVERFLOW_ENA = 15203; // 6 -static const uint64_t SH_FLD_RCV_DATATO_DIV = 15204; // 1 -static const uint64_t SH_FLD_RCV_DATATO_DIV_LEN = 15205; // 1 -static const uint64_t SH_FLD_RCV_ERROR = 15206; // 1 -static const uint64_t SH_FLD_RCV_GROUPID = 15207; // 1 -static const uint64_t SH_FLD_RCV_GROUPID_LEN = 15208; // 1 -static const uint64_t SH_FLD_RCV_IN_PROGRESS = 15209; // 1 -static const uint64_t SH_FLD_RCV_PB_OP_HANG_ERR = 15210; // 1 -static const uint64_t SH_FLD_RCV_RESERVATION_SET = 15211; // 1 -static const uint64_t SH_FLD_RCV_RESET = 15212; // 1 -static const uint64_t SH_FLD_RCV_TOD_STATE = 15213; // 1 -static const uint64_t SH_FLD_RCV_TOD_STATE_LEN = 15214; // 1 -static const uint64_t SH_FLD_RCV_TTAG_PARITY_ERR = 15215; // 1 -static const uint64_t SH_FLD_RCV_WRITE_IN_PROGRESS = 15216; // 1 -static const uint64_t SH_FLD_RC_ADDR_PAR = 15217; // 1 -static const uint64_t SH_FLD_RC_ENABLE_AUTO_RECAL = 15218; // 2 -static const uint64_t SH_FLD_RC_ENABLE_BER_TEST = 15219; // 4 -static const uint64_t SH_FLD_RC_ENABLE_CM_COARSE_CAL = 15220; // 6 -static const uint64_t SH_FLD_RC_ENABLE_CM_FINE_CAL = 15221; // 6 -static const uint64_t SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 15222; // 6 -static const uint64_t SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 15223; // 6 -static const uint64_t SH_FLD_RC_ENABLE_CTLE_COARSE_CAL = 15224; // 6 -static const uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 15225; // 2 -static const uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 15226; // 4 -static const uint64_t SH_FLD_RC_ENABLE_DAC_H1_CAL = 15227; // 6 -static const uint64_t SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL = 15228; // 4 -static const uint64_t SH_FLD_RC_ENABLE_DDC = 15229; // 6 -static const uint64_t SH_FLD_RC_ENABLE_DFE_H1_CAL = 15230; // 6 -static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_CAL = 15231; // 4 -static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP = 15232; // 4 -static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 15233; // 4 -static const uint64_t SH_FLD_RC_ENABLE_DFE_H6_H12_FAST_MODE = 15234; // 4 -static const uint64_t SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE = 15235; // 4 -static const uint64_t SH_FLD_RC_ENABLE_H1AP_TWEAK = 15236; // 6 -static const uint64_t SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 15237; // 6 -static const uint64_t SH_FLD_RC_ENABLE_RESULT_CHECK = 15238; // 4 -static const uint64_t SH_FLD_RC_ENABLE_VGA_AMAX_MODE = 15239; // 6 -static const uint64_t SH_FLD_RC_ENABLE_VGA_CAL = 15240; // 6 -static const uint64_t SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 15241; // 2 -static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 15242; // 12 -static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR = 15243; // 12 -static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP = 15244; // 12 -static const uint64_t SH_FLD_RC_MASK = 15245; // 8 -static const uint64_t SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 15246; // 12 -static const uint64_t SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 15247; // 12 -static const uint64_t SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 15248; // 12 -static const uint64_t SH_FLD_RC_POWERBUS_DATA_TIMEOUT = 15249; // 12 -static const uint64_t SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 15250; // 12 -static const uint64_t SH_FLD_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR = 15251; // 12 -static const uint64_t SH_FLD_RC_TTAG_PAR = 15252; // 1 -static const uint64_t SH_FLD_RDADDR_ARB_BAD_HAND = 15253; // 2 -static const uint64_t SH_FLD_RDATA = 15254; // 1 -static const uint64_t SH_FLD_RDATA_LEN = 15255; // 1 -static const uint64_t SH_FLD_RDCLK_ALIGN = 15256; // 8 -static const uint64_t SH_FLD_RDCMP = 15257; // 2 -static const uint64_t SH_FLD_RDCMP_LEN = 15258; // 2 -static const uint64_t SH_FLD_RDIV = 15259; // 14 -static const uint64_t SH_FLD_RDIV_LEN = 15260; // 10 -static const uint64_t SH_FLD_RDQ_ABORT_OP = 15261; // 1 -static const uint64_t SH_FLD_RDQ_ABORT_TRM = 15262; // 1 -static const uint64_t SH_FLD_RDQ_BAD_CRESP = 15263; // 1 -static const uint64_t SH_FLD_RDQ_DATA_HANG = 15264; // 1 -static const uint64_t SH_FLD_RDQ_FSM_PERR = 15265; // 1 -static const uint64_t SH_FLD_RDQ_OP_HANG = 15266; // 1 -static const uint64_t SH_FLD_RDQ_OVERFLOW = 15267; // 1 -static const uint64_t SH_FLD_RDWR_ACCESS_EN = 15268; // 2 -static const uint64_t SH_FLD_RDWR_ADDR = 15269; // 2 -static const uint64_t SH_FLD_RDWR_ADDR_LEN = 15270; // 2 -static const uint64_t SH_FLD_RDWR_OP_BUSY = 15271; // 1 -static const uint64_t SH_FLD_RDWR_RDWR_DATA = 15272; // 2 -static const uint64_t SH_FLD_RDWR_RDWR_DATA_LEN = 15273; // 2 -static const uint64_t SH_FLD_RDWR_READ_STATUS = 15274; // 2 -static const uint64_t SH_FLD_RDWR_REQ_PEND = 15275; // 2 -static const uint64_t SH_FLD_RDWR_UPDATE_ERROR = 15276; // 2 -static const uint64_t SH_FLD_RDWR_WRITE_MODE = 15277; // 2 -static const uint64_t SH_FLD_RDWR_WRITE_STATUS = 15278; // 2 -static const uint64_t SH_FLD_RDWR_WR_ENABLE = 15279; // 2 -static const uint64_t SH_FLD_RDX_BUS0_STG0_SEL = 15280; // 1 -static const uint64_t SH_FLD_RDX_BUS0_STG0_SEL_LEN = 15281; // 1 -static const uint64_t SH_FLD_RDX_BUS0_STG1_SEL = 15282; // 1 -static const uint64_t SH_FLD_RDX_BUS0_STG2_SEL = 15283; // 1 -static const uint64_t SH_FLD_RDX_BUS1_STG0_SEL = 15284; // 1 -static const uint64_t SH_FLD_RDX_BUS1_STG0_SEL_LEN = 15285; // 1 -static const uint64_t SH_FLD_RDX_BUS1_STG1_SEL = 15286; // 1 -static const uint64_t SH_FLD_RDX_BUS1_STG2_SEL = 15287; // 1 -static const uint64_t SH_FLD_RD_ADDR_0_7 = 15288; // 1 -static const uint64_t SH_FLD_RD_ADDR_0_7_LEN = 15289; // 1 -static const uint64_t SH_FLD_RD_CNTL = 15290; // 8 -static const uint64_t SH_FLD_RD_CNTL_MASK = 15291; // 8 -static const uint64_t SH_FLD_RD_DATA_COUNT = 15292; // 1 -static const uint64_t SH_FLD_RD_DATA_COUNT_LEN = 15293; // 1 -static const uint64_t SH_FLD_RD_DATA_PARITY_ERROR = 15294; // 3 -static const uint64_t SH_FLD_RD_ECC_CE = 15295; // 1 -static const uint64_t SH_FLD_RD_ECC_UE = 15296; // 1 -static const uint64_t SH_FLD_RD_GO_M_QOS = 15297; // 2 -static const uint64_t SH_FLD_RD_MACHINE_HANG = 15298; // 12 -static const uint64_t SH_FLD_RD_RST_INTRPT_FACES = 15299; // 1 -static const uint64_t SH_FLD_RD_RST_INTRPT_PIB = 15300; // 1 -static const uint64_t SH_FLD_RD_SCOPE = 15301; // 24 -static const uint64_t SH_FLD_RD_SCOPE_LEN = 15302; // 24 -static const uint64_t SH_FLD_RD_SLVNUM = 15303; // 6 -static const uint64_t SH_FLD_RD_SLVNUM_LEN = 15304; // 6 -static const uint64_t SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR = 15305; // 8 -static const uint64_t SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR = 15306; // 8 -static const uint64_t SH_FLD_READ_BUFFER_OVERFLOW_ERROR = 15307; // 8 -static const uint64_t SH_FLD_READ_COMPARE_REQUIRED = 15308; // 64 -static const uint64_t SH_FLD_READ_COMPLETE = 15309; // 1 -static const uint64_t SH_FLD_READ_CONTINUE_0 = 15310; // 2 -static const uint64_t SH_FLD_READ_CONTINUE_1 = 15311; // 1 -static const uint64_t SH_FLD_READ_CONTINUE_2 = 15312; // 1 -static const uint64_t SH_FLD_READ_CONTINUE_3 = 15313; // 1 -static const uint64_t SH_FLD_READ_CONTROL_OVERFLOW_ERROR = 15314; // 8 -static const uint64_t SH_FLD_READ_COUNT = 15315; // 8 -static const uint64_t SH_FLD_READ_COUNT_LEN = 15316; // 8 -static const uint64_t SH_FLD_READ_CRD_POOL = 15317; // 1 -static const uint64_t SH_FLD_READ_CRD_POOL_LEN = 15318; // 1 -static const uint64_t SH_FLD_READ_CTR = 15319; // 8 -static const uint64_t SH_FLD_READ_DEBUG_SELECT = 15320; // 8 -static const uint64_t SH_FLD_READ_DEBUG_SELECT_LEN = 15321; // 8 -static const uint64_t SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR = 15322; // 8 -static const uint64_t SH_FLD_READ_ENABLE = 15323; // 129 -static const uint64_t SH_FLD_READ_EPSILON_MODE = 15324; // 2 -static const uint64_t SH_FLD_READ_EPSILON_TIER0 = 15325; // 2 -static const uint64_t SH_FLD_READ_EPSILON_TIER0_LEN = 15326; // 2 -static const uint64_t SH_FLD_READ_EPSILON_TIER1 = 15327; // 2 -static const uint64_t SH_FLD_READ_EPSILON_TIER1_LEN = 15328; // 2 -static const uint64_t SH_FLD_READ_EPSILON_TIER2 = 15329; // 2 -static const uint64_t SH_FLD_READ_EPSILON_TIER2_LEN = 15330; // 2 -static const uint64_t SH_FLD_READ_ERR_INJECT0 = 15331; // 8 -static const uint64_t SH_FLD_READ_ERR_INJECT0_LEN = 15332; // 8 -static const uint64_t SH_FLD_READ_INVALID_FACES = 15333; // 1 -static const uint64_t SH_FLD_READ_INVALID_PIB = 15334; // 1 -static const uint64_t SH_FLD_READ_LATENCY_OFFSET = 15335; // 8 -static const uint64_t SH_FLD_READ_LATENCY_OFFSET_LEN = 15336; // 8 -static const uint64_t SH_FLD_READ_NOT_WRITE_0 = 15337; // 2 -static const uint64_t SH_FLD_READ_NOT_WRITE_1 = 15338; // 1 -static const uint64_t SH_FLD_READ_NOT_WRITE_2 = 15339; // 1 -static const uint64_t SH_FLD_READ_NOT_WRITE_3 = 15340; // 1 -static const uint64_t SH_FLD_READ_NVLD = 15341; // 1 -static const uint64_t SH_FLD_READ_OR_WRITE_DATA = 15342; // 64 -static const uint64_t SH_FLD_READ_OR_WRITE_DATA_LEN = 15343; // 64 -static const uint64_t SH_FLD_READ_PAR_NOT_SEQ = 15344; // 8 -static const uint64_t SH_FLD_READ_POOL = 15345; // 1 -static const uint64_t SH_FLD_READ_POOL_LEN = 15346; // 1 -static const uint64_t SH_FLD_READ_PREFETCH_CTL = 15347; // 4 -static const uint64_t SH_FLD_READ_PREFETCH_CTL_LEN = 15348; // 4 -static const uint64_t SH_FLD_READ_RESPONSE_DELAY_ENABLE = 15349; // 2 -static const uint64_t SH_FLD_READ_RST_INTERRUPT_FACES = 15350; // 1 -static const uint64_t SH_FLD_READ_RST_INTERRUPT_PIB = 15351; // 1 -static const uint64_t SH_FLD_READ_TTYPE = 15352; // 4 -static const uint64_t SH_FLD_RECAL_ABORT = 15353; // 48 -static const uint64_t SH_FLD_RECAL_ABORT_DL_MASK = 15354; // 2 -static const uint64_t SH_FLD_RECAL_DONE_DL_MASK = 15355; // 2 -static const uint64_t SH_FLD_RECAL_ERROR = 15356; // 8 -static const uint64_t SH_FLD_RECAL_LANE_TO_MONITOR = 15357; // 6 -static const uint64_t SH_FLD_RECAL_LANE_TO_MONITOR_LEN = 15358; // 6 -static const uint64_t SH_FLD_RECAL_MAX_SPARES_EXCEEDED = 15359; // 8 -static const uint64_t SH_FLD_RECAL_REQ = 15360; // 48 -static const uint64_t SH_FLD_RECAL_REQ_DL_MASK = 15361; // 2 -static const uint64_t SH_FLD_RECAL_SPARE_DEPLOYED = 15362; // 8 -static const uint64_t SH_FLD_RECEIVED = 15363; // 1 -static const uint64_t SH_FLD_RECEIVED_ERROR = 15364; // 1 -static const uint64_t SH_FLD_RECEIVER_MODE = 15365; // 3 -static const uint64_t SH_FLD_RECEIVER_MODE_LEN = 15366; // 3 -static const uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER = 15367; // 1 -static const uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 15368; // 1 -static const uint64_t SH_FLD_RECOVERABLE_ERROR = 15369; // 2 -static const uint64_t SH_FLD_RECOVERY_BLK = 15370; // 24 -static const uint64_t SH_FLD_RECOVERY_BLK_EXTEND = 15371; // 24 -static const uint64_t SH_FLD_RECOVERY_FAILED = 15372; // 6 -static const uint64_t SH_FLD_RECOVERY_HANG_DETECTED = 15373; // 2 -static const uint64_t SH_FLD_RECR_PE = 15374; // 8 -static const uint64_t SH_FLD_REC_ACK_DEAD_ERROR = 15375; // 2 -static const uint64_t SH_FLD_REC_LIMIT = 15376; // 24 -static const uint64_t SH_FLD_REC_LIMIT_LEN = 15377; // 24 -static const uint64_t SH_FLD_REC_PB_SM_ERROR_ERR = 15378; // 2 -static const uint64_t SH_FLD_REC_SM_ERROR_ERR = 15379; // 2 -static const uint64_t SH_FLD_REC_UPDATE_ERROR = 15380; // 2 -static const uint64_t SH_FLD_REDIS_PRIORITY = 15381; // 1 -static const uint64_t SH_FLD_REDIS_PRIORITY_LEN = 15382; // 1 -static const uint64_t SH_FLD_REDIS_RSD = 15383; // 1 -static const uint64_t SH_FLD_REDIS_RSD_LEN = 15384; // 1 -static const uint64_t SH_FLD_REFCLKSEL = 15385; // 4 -static const uint64_t SH_FLD_REFCLK_0_TERM_DIS_DC = 15386; // 3 -static const uint64_t SH_FLD_REFCLK_1_TERM_DIS_DC = 15387; // 3 -static const uint64_t SH_FLD_REFCLK_CLKMUX0_SEL = 15388; // 43 -static const uint64_t SH_FLD_REFCLK_CLKMUX1_SEL = 15389; // 43 -static const uint64_t SH_FLD_REFISINK = 15390; // 3 -static const uint64_t SH_FLD_REFISINK_LEN = 15391; // 3 -static const uint64_t SH_FLD_REFISRC = 15392; // 3 -static const uint64_t SH_FLD_REFISRC_LEN = 15393; // 3 -static const uint64_t SH_FLD_REFRESH_ALL_RANKS = 15394; // 8 -static const uint64_t SH_FLD_REFRESH_BLOCK_CONFIG = 15395; // 8 -static const uint64_t SH_FLD_REFRESH_BLOCK_CONFIG_LEN = 15396; // 8 -static const uint64_t SH_FLD_REFRESH_CONTROL = 15397; // 8 -static const uint64_t SH_FLD_REFRESH_CONTROL_LEN = 15398; // 8 -static const uint64_t SH_FLD_REFRESH_COUNT = 15399; // 8 -static const uint64_t SH_FLD_REFRESH_COUNT_LEN = 15400; // 8 -static const uint64_t SH_FLD_REFRESH_INTERVAL = 15401; // 8 -static const uint64_t SH_FLD_REFRESH_INTERVAL_LEN = 15402; // 8 -static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_EN = 15403; // 2 -static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 15404; // 2 -static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 15405; // 2 -static const uint64_t SH_FLD_REFRESH_OVERRUN = 15406; // 16 -static const uint64_t SH_FLD_REFVREG = 15407; // 3 -static const uint64_t SH_FLD_REFVREG_LEN = 15408; // 3 -static const uint64_t SH_FLD_REG = 15409; // 19 -static const uint64_t SH_FLD_REGF = 15410; // 43 -static const uint64_t SH_FLD_REGION = 15411; // 72 -static const uint64_t SH_FLD_REGION_LEN = 15412; // 72 -static const uint64_t SH_FLD_REGISTER = 15413; // 3 -static const uint64_t SH_FLD_REGISTER_LEN = 15414; // 3 -static const uint64_t SH_FLD_REGISTER_PE = 15415; // 4 -static const uint64_t SH_FLD_REGISTER_VALID = 15416; // 4 -static const uint64_t SH_FLD_REGS = 15417; // 1 -static const uint64_t SH_FLD_REGSEL = 15418; // 4 -static const uint64_t SH_FLD_REGSEL_LEN = 15419; // 4 -static const uint64_t SH_FLD_REGS_IORESET = 15420; // 48 -static const uint64_t SH_FLD_REGS_LEN = 15421; // 1 -static const uint64_t SH_FLD_REGS_ORDERING_TAG = 15422; // 1 -static const uint64_t SH_FLD_REGS_ORDERING_TAG_LEN = 15423; // 1 -static const uint64_t SH_FLD_REG_ADDR_LENGTH = 15424; // 1 -static const uint64_t SH_FLD_REG_ADDR_LENGTH_LEN = 15425; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_0 = 15426; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_0_LEN = 15427; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_1 = 15428; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_1_LEN = 15429; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_2 = 15430; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_2_LEN = 15431; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_3 = 15432; // 1 -static const uint64_t SH_FLD_REG_ADDR_LEN_3_LEN = 15433; // 1 -static const uint64_t SH_FLD_REG_DP16 = 15434; // 16 -static const uint64_t SH_FLD_REG_DP16_LEN = 15435; // 16 -static const uint64_t SH_FLD_REG_ENABLE = 15436; // 1 -static const uint64_t SH_FLD_REG_FIFO_SIZE_EQ_1 = 15437; // 1 -static const uint64_t SH_FLD_REG_LEN = 15438; // 19 -static const uint64_t SH_FLD_REG_UNUSED = 15439; // 1 -static const uint64_t SH_FLD_REG_UNUSED_LEN = 15440; // 1 -static const uint64_t SH_FLD_REG_WAKEUP_C0 = 15441; // 24 -static const uint64_t SH_FLD_REG_WAKEUP_C1 = 15442; // 24 -static const uint64_t SH_FLD_REINIT_CREDITS = 15443; // 1 -static const uint64_t SH_FLD_REJECTED_PASTE_CMD = 15444; // 2 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_ADD = 15445; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_AND = 15446; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_E = 15447; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15448; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U = 15449; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S = 15450; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U = 15451; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_U = 15452; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_OR = 15453; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_XOR = 15454; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_ADD = 15455; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_AND = 15456; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S = 15457; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U = 15458; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S = 15459; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U = 15460; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_OR = 15461; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_ARMW_XOR = 15462; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_INJ = 15463; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W = 15464; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W_HP = 15465; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_CL_RD_NC_F0 = 15466; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_DMA_PR_W = 15467; // 12 -static const uint64_t SH_FLD_RELAXED_CMD_PR_DMA_INJ = 15468; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED0 = 15469; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED0_LEN = 15470; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED1 = 15471; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED1_LEN = 15472; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED2 = 15473; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED2_LEN = 15474; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED3 = 15475; // 12 -static const uint64_t SH_FLD_RELAXED_RESERVED3_LEN = 15476; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE0_MASK = 15477; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE0_MASK_LEN = 15478; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE0_MATCH = 15479; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE0_MATCH_LEN = 15480; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE0_RDENA = 15481; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE0_WRENA = 15482; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE1_MASK = 15483; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE1_MASK_LEN = 15484; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE1_MATCH = 15485; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE1_MATCH_LEN = 15486; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE1_RDENA = 15487; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE1_WRENA = 15488; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE2_MASK = 15489; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE2_MASK_LEN = 15490; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE2_MATCH = 15491; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE2_MATCH_LEN = 15492; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE2_RDENA = 15493; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE2_WRENA = 15494; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE3_MASK = 15495; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE3_MASK_LEN = 15496; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE3_MATCH = 15497; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE3_MATCH_LEN = 15498; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE3_RDENA = 15499; // 12 -static const uint64_t SH_FLD_RELAXED_SOURCE3_WRENA = 15500; // 12 -static const uint64_t SH_FLD_RELAXED_WR = 15501; // 1 -static const uint64_t SH_FLD_RELAXED_WR_ORDERING = 15502; // 1 -static const uint64_t SH_FLD_REL_ASYNC_PARITY_ERROR = 15503; // 8 -static const uint64_t SH_FLD_REL_ASYNC_SEQUENCE_ERROR = 15504; // 8 -static const uint64_t SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR = 15505; // 8 -static const uint64_t SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR = 15506; // 8 -static const uint64_t SH_FLD_REMAINING_WORDS = 15507; // 1 -static const uint64_t SH_FLD_REMAINING_WORDS_LEN = 15508; // 1 -static const uint64_t SH_FLD_REMAP_DEST = 15509; // 1 -static const uint64_t SH_FLD_REMAP_DEST_LEN = 15510; // 1 -static const uint64_t SH_FLD_REMAP_SOURCE = 15511; // 1 -static const uint64_t SH_FLD_REMAP_SOURCE_LEN = 15512; // 1 -static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE = 15513; // 5 -static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN = 15514; // 5 -static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID = 15515; // 5 -static const uint64_t SH_FLD_REMOTE_LATENCY_LONGER_LINK = 15516; // 5 -static const uint64_t SH_FLD_REMOTE_NODAL_EPSILON = 15517; // 8 -static const uint64_t SH_FLD_REMOTE_NODAL_EPSILON_LEN = 15518; // 8 -static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION = 15519; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR = 15520; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN = 15521; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 15522; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 15523; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_DISABLE = 15524; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_ERROR_DISABLE = 15525; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX = 15526; // 1 -static const uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 15527; // 1 -static const uint64_t SH_FLD_REM_0 = 15528; // 6 -static const uint64_t SH_FLD_REM_0_LEN = 15529; // 6 -static const uint64_t SH_FLD_REM_1 = 15530; // 6 -static const uint64_t SH_FLD_REM_1_LEN = 15531; // 6 -static const uint64_t SH_FLD_REM_2 = 15532; // 6 -static const uint64_t SH_FLD_REM_2_LEN = 15533; // 6 -static const uint64_t SH_FLD_REM_3 = 15534; // 6 -static const uint64_t SH_FLD_REM_3_LEN = 15535; // 6 -static const uint64_t SH_FLD_REPAIR_DONE = 15536; // 4 -static const uint64_t SH_FLD_REPAIR_FAILED = 15537; // 4 -static const uint64_t SH_FLD_REPEAT_CMD_CNT = 15538; // 64 -static const uint64_t SH_FLD_REPEAT_CMD_CNT_LEN = 15539; // 64 -static const uint64_t SH_FLD_REPLAY_BUFFER_SIZE = 15540; // 2 -static const uint64_t SH_FLD_REPLAY_BUFFER_SIZE_LEN = 15541; // 2 -static const uint64_t SH_FLD_REPLAY_CAP_ADDR = 15542; // 10 -static const uint64_t SH_FLD_REPLAY_CAP_ADDR_LEN = 15543; // 10 -static const uint64_t SH_FLD_REPLAY_CAP_INST = 15544; // 10 -static const uint64_t SH_FLD_REPLAY_CAP_INST_LEN = 15545; // 4 -static const uint64_t SH_FLD_REPLAY_CAP_SYN = 15546; // 10 -static const uint64_t SH_FLD_REPLAY_CAP_SYN_LEN = 15547; // 10 -static const uint64_t SH_FLD_REPLAY_CAP_VALID = 15548; // 10 -static const uint64_t SH_FLD_REPORT_SL_CHKBIT_ERR = 15549; // 5 -static const uint64_t SH_FLD_REPR = 15550; // 43 -static const uint64_t SH_FLD_REPTEST_ENABLE = 15551; // 1 -static const uint64_t SH_FLD_REPTEST_MATCH_TH = 15552; // 1 -static const uint64_t SH_FLD_REPTEST_MATCH_TH_LEN = 15553; // 1 -static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 = 15554; // 1 -static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 15555; // 1 -static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 = 15556; // 1 -static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 15557; // 1 -static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH = 15558; // 1 -static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH_LEN = 15559; // 1 -static const uint64_t SH_FLD_REQ = 15560; // 43 -static const uint64_t SH_FLD_REQUEST = 15561; // 1 -static const uint64_t SH_FLD_REQUEST_LEN = 15562; // 1 -static const uint64_t SH_FLD_REQ_INTR_PAYLOAD = 15563; // 30 -static const uint64_t SH_FLD_REQ_INTR_PAYLOAD_LEN = 15564; // 30 -static const uint64_t SH_FLD_REQ_INTR_TYPE = 15565; // 30 -static const uint64_t SH_FLD_REQ_INTR_TYPE_LEN = 15566; // 30 -static const uint64_t SH_FLD_REQ_RESET_FR_SBE = 15567; // 1 -static const uint64_t SH_FLD_REQ_RESET_FR_SP = 15568; // 1 -static const uint64_t SH_FLD_RESERVATION_EN = 15569; // 1 -static const uint64_t SH_FLD_RESERVED = 15570; // 134 -static const uint64_t SH_FLD_RESERVED0 = 15571; // 9 -static const uint64_t SH_FLD_RESERVED0_3 = 15572; // 4 -static const uint64_t SH_FLD_RESERVED0_3_LEN = 15573; // 4 -static const uint64_t SH_FLD_RESERVED0_LEN = 15574; // 9 -static const uint64_t SH_FLD_RESERVED1 = 15575; // 267 -static const uint64_t SH_FLD_RESERVED12_15 = 15576; // 4 -static const uint64_t SH_FLD_RESERVED12_15_LEN = 15577; // 4 -static const uint64_t SH_FLD_RESERVED14 = 15578; // 4 -static const uint64_t SH_FLD_RESERVED15 = 15579; // 4 -static const uint64_t SH_FLD_RESERVED18 = 15580; // 4 -static const uint64_t SH_FLD_RESERVED19 = 15581; // 4 -static const uint64_t SH_FLD_RESERVED19_22 = 15582; // 4 -static const uint64_t SH_FLD_RESERVED19_22_LEN = 15583; // 4 -static const uint64_t SH_FLD_RESERVED19_31 = 15584; // 4 -static const uint64_t SH_FLD_RESERVED19_31_LEN = 15585; // 4 -static const uint64_t SH_FLD_RESERVED1_2 = 15586; // 4 -static const uint64_t SH_FLD_RESERVED1_2_LEN = 15587; // 4 -static const uint64_t SH_FLD_RESERVED1_LEN = 15588; // 248 -static const uint64_t SH_FLD_RESERVED2 = 15589; // 114 -static const uint64_t SH_FLD_RESERVED20 = 15590; // 16 -static const uint64_t SH_FLD_RESERVED21 = 15591; // 4 -static const uint64_t SH_FLD_RESERVED22 = 15592; // 4 -static const uint64_t SH_FLD_RESERVED22_31 = 15593; // 8 -static const uint64_t SH_FLD_RESERVED22_31_LEN = 15594; // 8 -static const uint64_t SH_FLD_RESERVED23 = 15595; // 4 -static const uint64_t SH_FLD_RESERVED25 = 15596; // 4 -static const uint64_t SH_FLD_RESERVED26 = 15597; // 4 -static const uint64_t SH_FLD_RESERVED27 = 15598; // 4 -static const uint64_t SH_FLD_RESERVED28 = 15599; // 4 -static const uint64_t SH_FLD_RESERVED28_31 = 15600; // 10 -static const uint64_t SH_FLD_RESERVED28_31_LEN = 15601; // 10 -static const uint64_t SH_FLD_RESERVED2_15 = 15602; // 4 -static const uint64_t SH_FLD_RESERVED2_15_LEN = 15603; // 4 -static const uint64_t SH_FLD_RESERVED2_LEN = 15604; // 54 -static const uint64_t SH_FLD_RESERVED3 = 15605; // 40 -static const uint64_t SH_FLD_RESERVED31 = 15606; // 8 -static const uint64_t SH_FLD_RESERVED36_47 = 15607; // 4 -static const uint64_t SH_FLD_RESERVED36_47_LEN = 15608; // 4 -static const uint64_t SH_FLD_RESERVED3_LEN = 15609; // 24 -static const uint64_t SH_FLD_RESERVED4 = 15610; // 18 -static const uint64_t SH_FLD_RESERVED4_LEN = 15611; // 6 -static const uint64_t SH_FLD_RESERVED52_55 = 15612; // 4 -static const uint64_t SH_FLD_RESERVED52_55_LEN = 15613; // 4 -static const uint64_t SH_FLD_RESERVED57_63 = 15614; // 4 -static const uint64_t SH_FLD_RESERVED57_63_LEN = 15615; // 4 -static const uint64_t SH_FLD_RESERVED6 = 15616; // 1 -static const uint64_t SH_FLD_RESERVED63 = 15617; // 4 -static const uint64_t SH_FLD_RESERVED8_9 = 15618; // 8 -static const uint64_t SH_FLD_RESERVED8_9_LEN = 15619; // 8 -static const uint64_t SH_FLD_RESERVED9 = 15620; // 16 -static const uint64_t SH_FLD_RESERVED_0 = 15621; // 6 -static const uint64_t SH_FLD_RESERVED_00 = 15622; // 1 -static const uint64_t SH_FLD_RESERVED_02 = 15623; // 1 -static const uint64_t SH_FLD_RESERVED_03 = 15624; // 1 -static const uint64_t SH_FLD_RESERVED_0_1 = 15625; // 17 -static const uint64_t SH_FLD_RESERVED_0_15 = 15626; // 1 -static const uint64_t SH_FLD_RESERVED_0_15_LEN = 15627; // 1 -static const uint64_t SH_FLD_RESERVED_0_17 = 15628; // 2 -static const uint64_t SH_FLD_RESERVED_0_17_LEN = 15629; // 2 -static const uint64_t SH_FLD_RESERVED_0_19 = 15630; // 6 -static const uint64_t SH_FLD_RESERVED_0_19_LEN = 15631; // 6 -static const uint64_t SH_FLD_RESERVED_0_1_LEN = 15632; // 17 -static const uint64_t SH_FLD_RESERVED_0_20 = 15633; // 5 -static const uint64_t SH_FLD_RESERVED_0_20_LEN = 15634; // 5 -static const uint64_t SH_FLD_RESERVED_0_25 = 15635; // 1 -static const uint64_t SH_FLD_RESERVED_0_25_LEN = 15636; // 1 -static const uint64_t SH_FLD_RESERVED_0_29 = 15637; // 1 -static const uint64_t SH_FLD_RESERVED_0_29_LEN = 15638; // 1 -static const uint64_t SH_FLD_RESERVED_0_3 = 15639; // 1 -static const uint64_t SH_FLD_RESERVED_0_31 = 15640; // 2 -static const uint64_t SH_FLD_RESERVED_0_31_LEN = 15641; // 2 -static const uint64_t SH_FLD_RESERVED_0_32 = 15642; // 1 -static const uint64_t SH_FLD_RESERVED_0_32_LEN = 15643; // 1 -static const uint64_t SH_FLD_RESERVED_0_3_LEN = 15644; // 1 -static const uint64_t SH_FLD_RESERVED_0_7 = 15645; // 24 -static const uint64_t SH_FLD_RESERVED_0_7_LEN = 15646; // 24 -static const uint64_t SH_FLD_RESERVED_1 = 15647; // 13 -static const uint64_t SH_FLD_RESERVED_10 = 15648; // 1 -static const uint64_t SH_FLD_RESERVED_10_11 = 15649; // 31 -static const uint64_t SH_FLD_RESERVED_10_11_LEN = 15650; // 31 -static const uint64_t SH_FLD_RESERVED_10_LEN = 15651; // 1 -static const uint64_t SH_FLD_RESERVED_11 = 15652; // 2 -static const uint64_t SH_FLD_RESERVED_11A = 15653; // 43 -static const uint64_t SH_FLD_RESERVED_11_12 = 15654; // 4 -static const uint64_t SH_FLD_RESERVED_11_12_LEN = 15655; // 4 -static const uint64_t SH_FLD_RESERVED_11_14 = 15656; // 4 -static const uint64_t SH_FLD_RESERVED_11_14_LEN = 15657; // 4 -static const uint64_t SH_FLD_RESERVED_11_15 = 15658; // 1 -static const uint64_t SH_FLD_RESERVED_11_15_LEN = 15659; // 1 -static const uint64_t SH_FLD_RESERVED_11_LEN = 15660; // 1 -static const uint64_t SH_FLD_RESERVED_12 = 15661; // 3 -static const uint64_t SH_FLD_RESERVED_12_13 = 15662; // 9 -static const uint64_t SH_FLD_RESERVED_12_13_LEN = 15663; // 9 -static const uint64_t SH_FLD_RESERVED_12_15 = 15664; // 25 -static const uint64_t SH_FLD_RESERVED_12_15_LEN = 15665; // 25 -static const uint64_t SH_FLD_RESERVED_12_16 = 15666; // 1 -static const uint64_t SH_FLD_RESERVED_12_16_LEN = 15667; // 1 -static const uint64_t SH_FLD_RESERVED_12_23 = 15668; // 1 -static const uint64_t SH_FLD_RESERVED_12_23_LEN = 15669; // 1 -static const uint64_t SH_FLD_RESERVED_13 = 15670; // 2 -static const uint64_t SH_FLD_RESERVED_13_15 = 15671; // 12 -static const uint64_t SH_FLD_RESERVED_13_15_LEN = 15672; // 12 -static const uint64_t SH_FLD_RESERVED_13_31 = 15673; // 2 -static const uint64_t SH_FLD_RESERVED_13_31_LEN = 15674; // 2 -static const uint64_t SH_FLD_RESERVED_13_34 = 15675; // 2 -static const uint64_t SH_FLD_RESERVED_13_34_LEN = 15676; // 2 -static const uint64_t SH_FLD_RESERVED_13_LEN = 15677; // 1 -static const uint64_t SH_FLD_RESERVED_14 = 15678; // 1 -static const uint64_t SH_FLD_RESERVED_14C = 15679; // 43 -static const uint64_t SH_FLD_RESERVED_14_LEN = 15680; // 1 -static const uint64_t SH_FLD_RESERVED_15 = 15681; // 10 -static const uint64_t SH_FLD_RESERVED_15C = 15682; // 43 -static const uint64_t SH_FLD_RESERVED_16 = 15683; // 8 -static const uint64_t SH_FLD_RESERVED_16_17 = 15684; // 4 -static const uint64_t SH_FLD_RESERVED_16_17_LEN = 15685; // 4 -static const uint64_t SH_FLD_RESERVED_16_18 = 15686; // 30 -static const uint64_t SH_FLD_RESERVED_16_18_LEN = 15687; // 30 -static const uint64_t SH_FLD_RESERVED_16_26 = 15688; // 1 -static const uint64_t SH_FLD_RESERVED_16_26_LEN = 15689; // 1 -static const uint64_t SH_FLD_RESERVED_16_27 = 15690; // 1 -static const uint64_t SH_FLD_RESERVED_16_27_LEN = 15691; // 1 -static const uint64_t SH_FLD_RESERVED_16_LEN = 15692; // 1 -static const uint64_t SH_FLD_RESERVED_17 = 15693; // 3 -static const uint64_t SH_FLD_RESERVED_17_19 = 15694; // 6 -static const uint64_t SH_FLD_RESERVED_17_19_LEN = 15695; // 6 -static const uint64_t SH_FLD_RESERVED_17_LEN = 15696; // 1 -static const uint64_t SH_FLD_RESERVED_18 = 15697; // 1 -static const uint64_t SH_FLD_RESERVED_18A = 15698; // 43 -static const uint64_t SH_FLD_RESERVED_18_19 = 15699; // 9 -static const uint64_t SH_FLD_RESERVED_18_19_LEN = 15700; // 9 -static const uint64_t SH_FLD_RESERVED_18_23 = 15701; // 10 -static const uint64_t SH_FLD_RESERVED_18_23_LEN = 15702; // 10 -static const uint64_t SH_FLD_RESERVED_18_29 = 15703; // 12 -static const uint64_t SH_FLD_RESERVED_18_29_LEN = 15704; // 12 -static const uint64_t SH_FLD_RESERVED_18_31 = 15705; // 2 -static const uint64_t SH_FLD_RESERVED_18_31_LEN = 15706; // 2 -static const uint64_t SH_FLD_RESERVED_18_LEN = 15707; // 1 -static const uint64_t SH_FLD_RESERVED_19 = 15708; // 2 -static const uint64_t SH_FLD_RESERVED_19A = 15709; // 43 -static const uint64_t SH_FLD_RESERVED_1_12 = 15710; // 4 -static const uint64_t SH_FLD_RESERVED_1_12_LEN = 15711; // 4 -static const uint64_t SH_FLD_RESERVED_1_2 = 15712; // 55 -static const uint64_t SH_FLD_RESERVED_1_2_LEN = 15713; // 55 -static const uint64_t SH_FLD_RESERVED_1_3 = 15714; // 1 -static const uint64_t SH_FLD_RESERVED_1_3_LEN = 15715; // 1 -static const uint64_t SH_FLD_RESERVED_1_5 = 15716; // 1 -static const uint64_t SH_FLD_RESERVED_1_5_LEN = 15717; // 1 -static const uint64_t SH_FLD_RESERVED_1_7 = 15718; // 3 -static const uint64_t SH_FLD_RESERVED_1_7_LEN = 15719; // 3 -static const uint64_t SH_FLD_RESERVED_2 = 15720; // 3 -static const uint64_t SH_FLD_RESERVED_20 = 15721; // 5 -static const uint64_t SH_FLD_RESERVED_20_21 = 15722; // 1 -static const uint64_t SH_FLD_RESERVED_20_21_LEN = 15723; // 1 -static const uint64_t SH_FLD_RESERVED_20_31 = 15724; // 1 -static const uint64_t SH_FLD_RESERVED_20_31_LEN = 15725; // 1 -static const uint64_t SH_FLD_RESERVED_20_LEN = 15726; // 1 -static const uint64_t SH_FLD_RESERVED_21 = 15727; // 8 -static const uint64_t SH_FLD_RESERVED_21_31 = 15728; // 1 -static const uint64_t SH_FLD_RESERVED_21_31_LEN = 15729; // 1 -static const uint64_t SH_FLD_RESERVED_22C = 15730; // 43 -static const uint64_t SH_FLD_RESERVED_22_31 = 15731; // 1 -static const uint64_t SH_FLD_RESERVED_22_31_LEN = 15732; // 1 -static const uint64_t SH_FLD_RESERVED_23 = 15733; // 4 -static const uint64_t SH_FLD_RESERVED_23C = 15734; // 43 -static const uint64_t SH_FLD_RESERVED_23_26 = 15735; // 8 -static const uint64_t SH_FLD_RESERVED_23_26_LEN = 15736; // 8 -static const uint64_t SH_FLD_RESERVED_23_63 = 15737; // 2 -static const uint64_t SH_FLD_RESERVED_23_63_LEN = 15738; // 2 -static const uint64_t SH_FLD_RESERVED_24 = 15739; // 5 -static const uint64_t SH_FLD_RESERVED_24_25 = 15740; // 7 -static const uint64_t SH_FLD_RESERVED_24_25_LEN = 15741; // 7 -static const uint64_t SH_FLD_RESERVED_24_26 = 15742; // 3 -static const uint64_t SH_FLD_RESERVED_24_26_LEN = 15743; // 3 -static const uint64_t SH_FLD_RESERVED_24_29 = 15744; // 1 -static const uint64_t SH_FLD_RESERVED_24_29_LEN = 15745; // 1 -static const uint64_t SH_FLD_RESERVED_24_31 = 15746; // 1 -static const uint64_t SH_FLD_RESERVED_24_31_LEN = 15747; // 1 -static const uint64_t SH_FLD_RESERVED_24_LEN = 15748; // 1 -static const uint64_t SH_FLD_RESERVED_25 = 15749; // 12 -static const uint64_t SH_FLD_RESERVED_25_26 = 15750; // 3 -static const uint64_t SH_FLD_RESERVED_25_26_LEN = 15751; // 3 -static const uint64_t SH_FLD_RESERVED_25_33 = 15752; // 8 -static const uint64_t SH_FLD_RESERVED_25_33_LEN = 15753; // 8 -static const uint64_t SH_FLD_RESERVED_26 = 15754; // 8 -static const uint64_t SH_FLD_RESERVED_26_49 = 15755; // 2 -static const uint64_t SH_FLD_RESERVED_26_49_LEN = 15756; // 2 -static const uint64_t SH_FLD_RESERVED_28 = 15757; // 5 -static const uint64_t SH_FLD_RESERVED_28_31 = 15758; // 64 -static const uint64_t SH_FLD_RESERVED_28_31_LEN = 15759; // 64 -static const uint64_t SH_FLD_RESERVED_28_LEN = 15760; // 2 -static const uint64_t SH_FLD_RESERVED_29_30 = 15761; // 8 -static const uint64_t SH_FLD_RESERVED_29_30_LEN = 15762; // 8 -static const uint64_t SH_FLD_RESERVED_29_31 = 15763; // 6 -static const uint64_t SH_FLD_RESERVED_29_31_LEN = 15764; // 6 -static const uint64_t SH_FLD_RESERVED_2E = 15765; // 43 -static const uint64_t SH_FLD_RESERVED_2_3 = 15766; // 4 -static const uint64_t SH_FLD_RESERVED_2_3_LEN = 15767; // 4 -static const uint64_t SH_FLD_RESERVED_2_9 = 15768; // 25 -static const uint64_t SH_FLD_RESERVED_2_9_LEN = 15769; // 25 -static const uint64_t SH_FLD_RESERVED_3 = 15770; // 9 -static const uint64_t SH_FLD_RESERVED_30 = 15771; // 1 -static const uint64_t SH_FLD_RESERVED_30C = 15772; // 43 -static const uint64_t SH_FLD_RESERVED_30_31 = 15773; // 13 -static const uint64_t SH_FLD_RESERVED_30_31_LEN = 15774; // 13 -static const uint64_t SH_FLD_RESERVED_31 = 15775; // 11 -static const uint64_t SH_FLD_RESERVED_31C = 15776; // 43 -static const uint64_t SH_FLD_RESERVED_31_LEN = 15777; // 2 -static const uint64_t SH_FLD_RESERVED_32 = 15778; // 28 -static const uint64_t SH_FLD_RESERVED_32_33 = 15779; // 6 -static const uint64_t SH_FLD_RESERVED_32_33_LEN = 15780; // 6 -static const uint64_t SH_FLD_RESERVED_32_34 = 15781; // 8 -static const uint64_t SH_FLD_RESERVED_32_34_LEN = 15782; // 8 -static const uint64_t SH_FLD_RESERVED_32_35 = 15783; // 3 -static const uint64_t SH_FLD_RESERVED_32_35_LEN = 15784; // 3 -static const uint64_t SH_FLD_RESERVED_32_39 = 15785; // 3 -static const uint64_t SH_FLD_RESERVED_32_39_LEN = 15786; // 3 -static const uint64_t SH_FLD_RESERVED_32_40 = 15787; // 10 -static const uint64_t SH_FLD_RESERVED_32_40_LEN = 15788; // 10 -static const uint64_t SH_FLD_RESERVED_32_44 = 15789; // 3 -static const uint64_t SH_FLD_RESERVED_32_44_LEN = 15790; // 3 -static const uint64_t SH_FLD_RESERVED_32_63 = 15791; // 8 -static const uint64_t SH_FLD_RESERVED_32_63_LEN = 15792; // 8 -static const uint64_t SH_FLD_RESERVED_33A = 15793; // 43 -static const uint64_t SH_FLD_RESERVED_33_39 = 15794; // 1 -static const uint64_t SH_FLD_RESERVED_33_39_LEN = 15795; // 1 -static const uint64_t SH_FLD_RESERVED_33_43 = 15796; // 1 -static const uint64_t SH_FLD_RESERVED_33_43_LEN = 15797; // 1 -static const uint64_t SH_FLD_RESERVED_33_63 = 15798; // 1 -static const uint64_t SH_FLD_RESERVED_33_63_LEN = 15799; // 1 -static const uint64_t SH_FLD_RESERVED_34 = 15800; // 1 -static const uint64_t SH_FLD_RESERVED_34A = 15801; // 43 -static const uint64_t SH_FLD_RESERVED_35 = 15802; // 1 -static const uint64_t SH_FLD_RESERVED_35A = 15803; // 43 -static const uint64_t SH_FLD_RESERVED_36_37 = 15804; // 8 -static const uint64_t SH_FLD_RESERVED_36_37_LEN = 15805; // 8 -static const uint64_t SH_FLD_RESERVED_36_39 = 15806; // 1 -static const uint64_t SH_FLD_RESERVED_36_39_LEN = 15807; // 1 -static const uint64_t SH_FLD_RESERVED_37 = 15808; // 1 -static const uint64_t SH_FLD_RESERVED_37_45 = 15809; // 1 -static const uint64_t SH_FLD_RESERVED_37_45_LEN = 15810; // 1 -static const uint64_t SH_FLD_RESERVED_37_56 = 15811; // 8 -static const uint64_t SH_FLD_RESERVED_37_56_LEN = 15812; // 8 -static const uint64_t SH_FLD_RESERVED_38 = 15813; // 1 -static const uint64_t SH_FLD_RESERVED_38A = 15814; // 43 -static const uint64_t SH_FLD_RESERVED_38_39 = 15815; // 24 -static const uint64_t SH_FLD_RESERVED_38_39_LEN = 15816; // 24 -static const uint64_t SH_FLD_RESERVED_38_41 = 15817; // 1 -static const uint64_t SH_FLD_RESERVED_38_41_LEN = 15818; // 1 -static const uint64_t SH_FLD_RESERVED_38_63 = 15819; // 2 -static const uint64_t SH_FLD_RESERVED_38_63_LEN = 15820; // 2 -static const uint64_t SH_FLD_RESERVED_39 = 15821; // 12 -static const uint64_t SH_FLD_RESERVED_39A = 15822; // 43 -static const uint64_t SH_FLD_RESERVED_39_47 = 15823; // 64 -static const uint64_t SH_FLD_RESERVED_39_47_LEN = 15824; // 64 -static const uint64_t SH_FLD_RESERVED_39_63 = 15825; // 4 -static const uint64_t SH_FLD_RESERVED_39_63_LEN = 15826; // 4 -static const uint64_t SH_FLD_RESERVED_3E = 15827; // 43 -static const uint64_t SH_FLD_RESERVED_3_9 = 15828; // 1 -static const uint64_t SH_FLD_RESERVED_3_9_LEN = 15829; // 1 -static const uint64_t SH_FLD_RESERVED_4 = 15830; // 10 -static const uint64_t SH_FLD_RESERVED_40 = 15831; // 35 -static const uint64_t SH_FLD_RESERVED_40_41 = 15832; // 9 -static const uint64_t SH_FLD_RESERVED_40_41_LEN = 15833; // 9 -static const uint64_t SH_FLD_RESERVED_40_42 = 15834; // 1 -static const uint64_t SH_FLD_RESERVED_40_42_LEN = 15835; // 1 -static const uint64_t SH_FLD_RESERVED_40_47 = 15836; // 2 -static const uint64_t SH_FLD_RESERVED_40_47_LEN = 15837; // 2 -static const uint64_t SH_FLD_RESERVED_41 = 15838; // 2 -static const uint64_t SH_FLD_RESERVED_41_42 = 15839; // 10 -static const uint64_t SH_FLD_RESERVED_41_42_LEN = 15840; // 10 -static const uint64_t SH_FLD_RESERVED_41_43 = 15841; // 2 -static const uint64_t SH_FLD_RESERVED_41_43_LEN = 15842; // 2 -static const uint64_t SH_FLD_RESERVED_41_63 = 15843; // 8 -static const uint64_t SH_FLD_RESERVED_41_63_LEN = 15844; // 8 -static const uint64_t SH_FLD_RESERVED_42 = 15845; // 2 -static const uint64_t SH_FLD_RESERVED_42A = 15846; // 43 -static const uint64_t SH_FLD_RESERVED_42C = 15847; // 43 -static const uint64_t SH_FLD_RESERVED_42_43 = 15848; // 12 -static const uint64_t SH_FLD_RESERVED_42_43_LEN = 15849; // 12 -static const uint64_t SH_FLD_RESERVED_42_47 = 15850; // 8 -static const uint64_t SH_FLD_RESERVED_42_47_LEN = 15851; // 8 -static const uint64_t SH_FLD_RESERVED_43 = 15852; // 2 -static const uint64_t SH_FLD_RESERVED_43A = 15853; // 43 -static const uint64_t SH_FLD_RESERVED_43C = 15854; // 43 -static const uint64_t SH_FLD_RESERVED_43_44 = 15855; // 2 -static const uint64_t SH_FLD_RESERVED_43_44_LEN = 15856; // 2 -static const uint64_t SH_FLD_RESERVED_44 = 15857; // 1 -static const uint64_t SH_FLD_RESERVED_44_46 = 15858; // 1 -static const uint64_t SH_FLD_RESERVED_44_46_LEN = 15859; // 1 -static const uint64_t SH_FLD_RESERVED_44_47 = 15860; // 1 -static const uint64_t SH_FLD_RESERVED_44_47_LEN = 15861; // 1 -static const uint64_t SH_FLD_RESERVED_45 = 15862; // 1 -static const uint64_t SH_FLD_RESERVED_46 = 15863; // 1 -static const uint64_t SH_FLD_RESERVED_47 = 15864; // 2 -static const uint64_t SH_FLD_RESERVED_47_48 = 15865; // 2 -static const uint64_t SH_FLD_RESERVED_47_48_LEN = 15866; // 2 -static const uint64_t SH_FLD_RESERVED_47_51 = 15867; // 1 -static const uint64_t SH_FLD_RESERVED_47_51_LEN = 15868; // 1 -static const uint64_t SH_FLD_RESERVED_48 = 15869; // 27 -static const uint64_t SH_FLD_RESERVED_48_49 = 15870; // 3 -static const uint64_t SH_FLD_RESERVED_48_49_LEN = 15871; // 3 -static const uint64_t SH_FLD_RESERVED_48_50 = 15872; // 2 -static const uint64_t SH_FLD_RESERVED_48_50_LEN = 15873; // 2 -static const uint64_t SH_FLD_RESERVED_48_63 = 15874; // 10 -static const uint64_t SH_FLD_RESERVED_48_63_LEN = 15875; // 10 -static const uint64_t SH_FLD_RESERVED_49_63 = 15876; // 8 -static const uint64_t SH_FLD_RESERVED_49_63_LEN = 15877; // 8 -static const uint64_t SH_FLD_RESERVED_4_5 = 15878; // 1 -static const uint64_t SH_FLD_RESERVED_4_5_LEN = 15879; // 1 -static const uint64_t SH_FLD_RESERVED_4_7 = 15880; // 32 -static const uint64_t SH_FLD_RESERVED_4_7_LEN = 15881; // 32 -static const uint64_t SH_FLD_RESERVED_4_LEN = 15882; // 1 -static const uint64_t SH_FLD_RESERVED_5 = 15883; // 2 -static const uint64_t SH_FLD_RESERVED_50 = 15884; // 4 -static const uint64_t SH_FLD_RESERVED_50_51 = 15885; // 3 -static const uint64_t SH_FLD_RESERVED_50_51_LEN = 15886; // 3 -static const uint64_t SH_FLD_RESERVED_50_63 = 15887; // 1 -static const uint64_t SH_FLD_RESERVED_50_63_LEN = 15888; // 1 -static const uint64_t SH_FLD_RESERVED_51 = 15889; // 16 -static const uint64_t SH_FLD_RESERVED_51_63 = 15890; // 9 -static const uint64_t SH_FLD_RESERVED_51_63_LEN = 15891; // 9 -static const uint64_t SH_FLD_RESERVED_52 = 15892; // 38 -static const uint64_t SH_FLD_RESERVED_52_55 = 15893; // 64 -static const uint64_t SH_FLD_RESERVED_52_55_LEN = 15894; // 64 -static const uint64_t SH_FLD_RESERVED_52_56 = 15895; // 8 -static const uint64_t SH_FLD_RESERVED_52_56_LEN = 15896; // 8 -static const uint64_t SH_FLD_RESERVED_53_54 = 15897; // 8 -static const uint64_t SH_FLD_RESERVED_53_54_LEN = 15898; // 8 -static const uint64_t SH_FLD_RESERVED_53_58 = 15899; // 2 -static const uint64_t SH_FLD_RESERVED_53_58_LEN = 15900; // 2 -static const uint64_t SH_FLD_RESERVED_53_63 = 15901; // 1 -static const uint64_t SH_FLD_RESERVED_53_63_LEN = 15902; // 1 -static const uint64_t SH_FLD_RESERVED_54_63 = 15903; // 8 -static const uint64_t SH_FLD_RESERVED_54_63_LEN = 15904; // 8 -static const uint64_t SH_FLD_RESERVED_55_63 = 15905; // 8 -static const uint64_t SH_FLD_RESERVED_55_63_LEN = 15906; // 8 -static const uint64_t SH_FLD_RESERVED_56 = 15907; // 32 -static const uint64_t SH_FLD_RESERVED_56_57 = 15908; // 2 -static const uint64_t SH_FLD_RESERVED_56_57_LEN = 15909; // 2 -static const uint64_t SH_FLD_RESERVED_56_58 = 15910; // 5 -static const uint64_t SH_FLD_RESERVED_56_58_LEN = 15911; // 5 -static const uint64_t SH_FLD_RESERVED_56_59 = 15912; // 1 -static const uint64_t SH_FLD_RESERVED_56_59_LEN = 15913; // 1 -static const uint64_t SH_FLD_RESERVED_56_63 = 15914; // 18 -static const uint64_t SH_FLD_RESERVED_56_63_LEN = 15915; // 18 -static const uint64_t SH_FLD_RESERVED_57 = 15916; // 24 -static const uint64_t SH_FLD_RESERVED_57_58 = 15917; // 2 -static const uint64_t SH_FLD_RESERVED_57_58_LEN = 15918; // 2 -static const uint64_t SH_FLD_RESERVED_57_59 = 15919; // 7 -static const uint64_t SH_FLD_RESERVED_57_59_LEN = 15920; // 7 -static const uint64_t SH_FLD_RESERVED_58 = 15921; // 1 -static const uint64_t SH_FLD_RESERVED_58_59 = 15922; // 1 -static const uint64_t SH_FLD_RESERVED_58_59_LEN = 15923; // 1 -static const uint64_t SH_FLD_RESERVED_58_63 = 15924; // 8 -static const uint64_t SH_FLD_RESERVED_58_63_LEN = 15925; // 8 -static const uint64_t SH_FLD_RESERVED_59 = 15926; // 1 -static const uint64_t SH_FLD_RESERVED_59_63 = 15927; // 8 -static const uint64_t SH_FLD_RESERVED_59_63_LEN = 15928; // 8 -static const uint64_t SH_FLD_RESERVED_5_15 = 15929; // 1 -static const uint64_t SH_FLD_RESERVED_5_15_LEN = 15930; // 1 -static const uint64_t SH_FLD_RESERVED_5_7 = 15931; // 1 -static const uint64_t SH_FLD_RESERVED_5_7_LEN = 15932; // 1 -static const uint64_t SH_FLD_RESERVED_5_LEN = 15933; // 1 -static const uint64_t SH_FLD_RESERVED_6 = 15934; // 2 -static const uint64_t SH_FLD_RESERVED_60 = 15935; // 24 -static const uint64_t SH_FLD_RESERVED_60_61 = 15936; // 8 -static const uint64_t SH_FLD_RESERVED_60_61_LEN = 15937; // 8 -static const uint64_t SH_FLD_RESERVED_60_63 = 15938; // 9 -static const uint64_t SH_FLD_RESERVED_60_63_LEN = 15939; // 9 -static const uint64_t SH_FLD_RESERVED_61 = 15940; // 24 -static const uint64_t SH_FLD_RESERVED_61_63 = 15941; // 18 -static const uint64_t SH_FLD_RESERVED_61_63_LEN = 15942; // 18 -static const uint64_t SH_FLD_RESERVED_62 = 15943; // 1 -static const uint64_t SH_FLD_RESERVED_62_63 = 15944; // 16 -static const uint64_t SH_FLD_RESERVED_62_63_LEN = 15945; // 16 -static const uint64_t SH_FLD_RESERVED_63 = 15946; // 20 -static const uint64_t SH_FLD_RESERVED_6C = 15947; // 43 -static const uint64_t SH_FLD_RESERVED_6E = 15948; // 43 -static const uint64_t SH_FLD_RESERVED_6_14 = 15949; // 2 -static const uint64_t SH_FLD_RESERVED_6_14_LEN = 15950; // 2 -static const uint64_t SH_FLD_RESERVED_6_7 = 15951; // 27 -static const uint64_t SH_FLD_RESERVED_6_7_LEN = 15952; // 27 -static const uint64_t SH_FLD_RESERVED_6_8 = 15953; // 12 -static const uint64_t SH_FLD_RESERVED_6_8_LEN = 15954; // 12 -static const uint64_t SH_FLD_RESERVED_7 = 15955; // 2 -static const uint64_t SH_FLD_RESERVED_7C = 15956; // 43 -static const uint64_t SH_FLD_RESERVED_7_9 = 15957; // 8 -static const uint64_t SH_FLD_RESERVED_7_9_LEN = 15958; // 8 -static const uint64_t SH_FLD_RESERVED_7_LEN = 15959; // 1 -static const uint64_t SH_FLD_RESERVED_8 = 15960; // 6 -static const uint64_t SH_FLD_RESERVED_8_10 = 15961; // 39 -static const uint64_t SH_FLD_RESERVED_8_10_LEN = 15962; // 39 -static const uint64_t SH_FLD_RESERVED_8_9 = 15963; // 6 -static const uint64_t SH_FLD_RESERVED_8_9_LEN = 15964; // 6 -static const uint64_t SH_FLD_RESERVED_8_LEN = 15965; // 1 -static const uint64_t SH_FLD_RESERVED_9 = 15966; // 27 -static const uint64_t SH_FLD_RESERVED_9_15 = 15967; // 2 -static const uint64_t SH_FLD_RESERVED_9_15_LEN = 15968; // 2 -static const uint64_t SH_FLD_RESERVED_9_26 = 15969; // 1 -static const uint64_t SH_FLD_RESERVED_9_26_LEN = 15970; // 1 -static const uint64_t SH_FLD_RESERVED_9_27 = 15971; // 1 -static const uint64_t SH_FLD_RESERVED_9_27_LEN = 15972; // 1 -static const uint64_t SH_FLD_RESERVED_FOR_ADDRESS = 15973; // 1 -static const uint64_t SH_FLD_RESERVED_FOR_ADDRESS_LEN = 15974; // 1 -static const uint64_t SH_FLD_RESERVED_FOR_CONFIGS = 15975; // 1 -static const uint64_t SH_FLD_RESERVED_FOR_CONFIGS_LEN = 15976; // 1 -static const uint64_t SH_FLD_RESERVED_FOR_ERRS = 15977; // 1 -static const uint64_t SH_FLD_RESERVED_FOR_ERRS_LEN = 15978; // 1 -static const uint64_t SH_FLD_RESERVED_ID_55C = 15979; // 43 -static const uint64_t SH_FLD_RESERVED_ID_61C = 15980; // 43 -static const uint64_t SH_FLD_RESERVED_ID_62C = 15981; // 43 -static const uint64_t SH_FLD_RESERVED_ID_63C = 15982; // 43 -static const uint64_t SH_FLD_RESERVED_LAST_LT = 15983; // 43 -static const uint64_t SH_FLD_RESERVED_LEN = 15984; // 76 -static const uint64_t SH_FLD_RESERVED_LT = 15985; // 43 -static const uint64_t SH_FLD_RESERVED_LT_LEN = 15986; // 43 -static const uint64_t SH_FLD_RESERVED_RING_LOCKING = 15987; // 43 -static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_35C = 15988; // 43 -static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_36C = 15989; // 43 -static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_37C = 15990; // 43 -static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_38C = 15991; // 43 -static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_39C = 15992; // 43 -static const uint64_t SH_FLD_RESERVE_11 = 15993; // 2 -static const uint64_t SH_FLD_RESERVE_39_52 = 15994; // 2 -static const uint64_t SH_FLD_RESERVE_39_52_LEN = 15995; // 2 -static const uint64_t SH_FLD_RESERVE_5_15 = 15996; // 2 -static const uint64_t SH_FLD_RESERVE_5_15_LEN = 15997; // 2 -static const uint64_t SH_FLD_RESET = 15998; // 27 -static const uint64_t SH_FLD_RESETMODE = 15999; // 9 -static const uint64_t SH_FLD_RESET_0 = 16000; // 8 -static const uint64_t SH_FLD_RESET_0_7 = 16001; // 1 -static const uint64_t SH_FLD_RESET_0_7_LEN = 16002; // 1 -static const uint64_t SH_FLD_RESET_1 = 16003; // 8 -static const uint64_t SH_FLD_RESET_C2TIMER_ON_C1 = 16004; // 86 -static const uint64_t SH_FLD_RESET_C3_ON_C0 = 16005; // 86 -static const uint64_t SH_FLD_RESET_C3_SELECT = 16006; // 86 -static const uint64_t SH_FLD_RESET_C3_SELECT_LEN = 16007; // 86 -static const uint64_t SH_FLD_RESET_EP = 16008; // 43 -static const uint64_t SH_FLD_RESET_ERROR_LOGS = 16009; // 2 -static const uint64_t SH_FLD_RESET_ERR_RPT = 16010; // 8 -static const uint64_t SH_FLD_RESET_IMPRECISE_QERR = 16011; // 12 -static const uint64_t SH_FLD_RESET_KEEPER = 16012; // 38 -static const uint64_t SH_FLD_RESET_LEN = 16013; // 2 -static const uint64_t SH_FLD_RESET_MODE = 16014; // 5 -static const uint64_t SH_FLD_RESET_ON_PARITY = 16015; // 1 -static const uint64_t SH_FLD_RESET_PIB = 16016; // 1 -static const uint64_t SH_FLD_RESET_RECOVER = 16017; // 8 -static const uint64_t SH_FLD_RESET_TOD_STATE = 16018; // 1 -static const uint64_t SH_FLD_RESET_TRAP_CNFG = 16019; // 2 -static const uint64_t SH_FLD_RESET_TRIG_SEL = 16020; // 43 -static const uint64_t SH_FLD_RESET_TRIG_SEL_LEN = 16021; // 43 -static const uint64_t SH_FLD_RESID_FE_LEN_0 = 16022; // 2 -static const uint64_t SH_FLD_RESID_FE_LEN_0_LEN = 16023; // 2 -static const uint64_t SH_FLD_RESID_FE_LEN_1 = 16024; // 1 -static const uint64_t SH_FLD_RESID_FE_LEN_1_LEN = 16025; // 1 -static const uint64_t SH_FLD_RESID_FE_LEN_2 = 16026; // 1 -static const uint64_t SH_FLD_RESID_FE_LEN_2_LEN = 16027; // 1 -static const uint64_t SH_FLD_RESID_FE_LEN_3 = 16028; // 1 -static const uint64_t SH_FLD_RESID_FE_LEN_3_LEN = 16029; // 1 -static const uint64_t SH_FLD_RESPONSE = 16030; // 1 -static const uint64_t SH_FLD_RESP_PKT_RCV = 16031; // 2 -static const uint64_t SH_FLD_RESSEL = 16032; // 4 -static const uint64_t SH_FLD_RESULT = 16033; // 1 -static const uint64_t SH_FLD_RESULT_AVAILABLE = 16034; // 2 -static const uint64_t SH_FLD_RESULT_LEN = 16035; // 1 -static const uint64_t SH_FLD_RESUME_FROM_PAUSE = 16036; // 2 -static const uint64_t SH_FLD_RETIRE = 16037; // 1 -static const uint64_t SH_FLD_RETRAIN_PERCAL_SW = 16038; // 8 -static const uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT = 16039; // 4 -static const uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT_LEN = 16040; // 4 -static const uint64_t SH_FLD_RETRY_VALUE = 16041; // 1 -static const uint64_t SH_FLD_RETRY_VALUE_LEN = 16042; // 1 -static const uint64_t SH_FLD_RETURNQ_ERR = 16043; // 4 -static const uint64_t SH_FLD_RETURN_GOOD_ON_COMP = 16044; // 24 -static const uint64_t SH_FLD_RG_CERR_BIT10 = 16045; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT11 = 16046; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT12 = 16047; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT13 = 16048; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT4 = 16049; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT5 = 16050; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT6 = 16051; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT7 = 16052; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT8 = 16053; // 1 -static const uint64_t SH_FLD_RG_CERR_BIT9 = 16054; // 1 -static const uint64_t SH_FLD_RG_CERR_RESET = 16055; // 1 -static const uint64_t SH_FLD_RG_CERR_UNUSED_BITS = 16056; // 1 -static const uint64_t SH_FLD_RG_CERR_UNUSED_BITS_LEN = 16057; // 1 -static const uint64_t SH_FLD_RG_ECC_CE_ERROR = 16058; // 2 -static const uint64_t SH_FLD_RG_ECC_SUE_ERROR = 16059; // 2 -static const uint64_t SH_FLD_RG_ECC_UE_ERROR = 16060; // 2 -static const uint64_t SH_FLD_RG_LOGIC_HW_ERROR = 16061; // 2 -static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI = 16062; // 1 -static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN = 16063; // 1 -static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO = 16064; // 1 -static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN = 16065; // 1 -static const uint64_t SH_FLD_RG_TRACE_INT_DATA_HI = 16066; // 1 -static const uint64_t SH_FLD_RG_TRACE_INT_DATA_LO = 16067; // 1 -static const uint64_t SH_FLD_RG_TRACE_INT_TRIG_01 = 16068; // 1 -static const uint64_t SH_FLD_RG_TRACE_INT_TRIG_23 = 16069; // 1 -static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01 = 16070; // 1 -static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN = 16071; // 1 -static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23 = 16072; // 1 -static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN = 16073; // 1 -static const uint64_t SH_FLD_RIC = 16074; // 8 -static const uint64_t SH_FLD_RIC_LEN = 16075; // 8 -static const uint64_t SH_FLD_RINGS = 16076; // 43 -static const uint64_t SH_FLD_RINGS_LEN = 16077; // 43 -static const uint64_t SH_FLD_RING_LOCKING = 16078; // 43 -static const uint64_t SH_FLD_RMA_BAR = 16079; // 1 -static const uint64_t SH_FLD_RMA_BAR_LEN = 16080; // 1 -static const uint64_t SH_FLD_RMA_BAR_MASK = 16081; // 1 -static const uint64_t SH_FLD_RMA_BAR_MASK_LEN = 16082; // 1 -static const uint64_t SH_FLD_RMT_FIRST_GRPSCAN_ENA = 16083; // 1 -static const uint64_t SH_FLD_RMW_BUF_THRESH = 16084; // 8 -static const uint64_t SH_FLD_RMW_BUF_THRESH_LEN = 16085; // 8 -static const uint64_t SH_FLD_RND_BACKOFF_ENABLE = 16086; // 2 -static const uint64_t SH_FLD_RNG0_BIST_FAIL = 16087; // 1 -static const uint64_t SH_FLD_RNG0_FAIL = 16088; // 1 -static const uint64_t SH_FLD_RNG0_INJ_CONTINOUS_ERROR = 16089; // 1 -static const uint64_t SH_FLD_RNG1_BIST_FAIL = 16090; // 1 -static const uint64_t SH_FLD_RNG1_FAIL = 16091; // 1 -static const uint64_t SH_FLD_RNG1_INJ_CONTINOUS_ERROR = 16092; // 1 -static const uint64_t SH_FLD_RNG_CNTRL_LOGIC_ERR = 16093; // 1 -static const uint64_t SH_FLD_RNG_FIRST_FAIL = 16094; // 1 -static const uint64_t SH_FLD_RNG_SECOND_FAIL = 16095; // 1 -static const uint64_t SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD = 16096; // 2 -static const uint64_t SH_FLD_RNW = 16097; // 15 -static const uint64_t SH_FLD_ROUTE_CHECKSTOP = 16098; // 2 -static const uint64_t SH_FLD_RPT = 16099; // 2 -static const uint64_t SH_FLD_RPT1 = 16100; // 1 -static const uint64_t SH_FLD_RPT1_LEN = 16101; // 1 -static const uint64_t SH_FLD_RPTHANG_SELECT = 16102; // 4 -static const uint64_t SH_FLD_RPTHANG_SELECT_LEN = 16103; // 4 -static const uint64_t SH_FLD_RPT_LEN = 16104; // 2 -static const uint64_t SH_FLD_RRDM_DLY = 16105; // 8 -static const uint64_t SH_FLD_RRDM_DLY_LEN = 16106; // 8 -static const uint64_t SH_FLD_RRN_BYPASS_ENABLE = 16107; // 1 -static const uint64_t SH_FLD_RRN_DATA = 16108; // 1 -static const uint64_t SH_FLD_RRN_DATA_LEN = 16109; // 1 -static const uint64_t SH_FLD_RROP_DLY = 16110; // 8 -static const uint64_t SH_FLD_RROP_DLY_LEN = 16111; // 8 -static const uint64_t SH_FLD_RRQ_CAPACITY_LIMIT = 16112; // 4 -static const uint64_t SH_FLD_RRQ_CAPACITY_LIMIT_LEN = 16113; // 4 -static const uint64_t SH_FLD_RRQ_HANG = 16114; // 8 -static const uint64_t SH_FLD_RRQ_PE = 16115; // 8 -static const uint64_t SH_FLD_RRSBG_DLY = 16116; // 8 -static const uint64_t SH_FLD_RRSBG_DLY_LEN = 16117; // 8 -static const uint64_t SH_FLD_RRSMDR_DLY = 16118; // 8 -static const uint64_t SH_FLD_RRSMDR_DLY_LEN = 16119; // 8 -static const uint64_t SH_FLD_RRSMSR_DLY = 16120; // 8 -static const uint64_t SH_FLD_RRSMSR_DLY_LEN = 16121; // 8 -static const uint64_t SH_FLD_RSB_BUS_LOGIC_ERROR = 16122; // 6 -static const uint64_t SH_FLD_RSB_DBG_FATAL_ERROR = 16123; // 6 -static const uint64_t SH_FLD_RSB_DBG_INF_ERROR = 16124; // 6 -static const uint64_t SH_FLD_RSB_ERR_FATAL_ERROR = 16125; // 6 -static const uint64_t SH_FLD_RSB_ERR_INF_ERROR = 16126; // 6 -static const uint64_t SH_FLD_RSB_FDA_FATAL_ERROR = 16127; // 6 -static const uint64_t SH_FLD_RSB_FDA_INF_ERROR = 16128; // 6 -static const uint64_t SH_FLD_RSB_FDB_FATAL_ERROR = 16129; // 6 -static const uint64_t SH_FLD_RSB_FDB_INF_ERROR = 16130; // 6 -static const uint64_t SH_FLD_RSB_REQUEST_ADDRESS_ERROR = 16131; // 6 -static const uint64_t SH_FLD_RSB_UVI_FATAL_ERROR = 16132; // 6 -static const uint64_t SH_FLD_RSB_UVI_INF_ERROR = 16133; // 6 -static const uint64_t SH_FLD_RSD_AT_MACRO = 16134; // 1 -static const uint64_t SH_FLD_RSD_AT_MACRO_LEN = 16135; // 1 -static const uint64_t SH_FLD_RSD_CRD_AT_MACRO = 16136; // 1 -static const uint64_t SH_FLD_RSD_CRD_AT_MACRO_LEN = 16137; // 1 -static const uint64_t SH_FLD_RSD_CRD_DMA_READ = 16138; // 1 -static const uint64_t SH_FLD_RSD_CRD_DMA_READ_LEN = 16139; // 1 -static const uint64_t SH_FLD_RSD_CRD_DMA_WRITE = 16140; // 1 -static const uint64_t SH_FLD_RSD_CRD_DMA_WRITE_LEN = 16141; // 1 -static const uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD = 16142; // 1 -static const uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 16143; // 1 -static const uint64_t SH_FLD_RSD_CRD_EQ_POST = 16144; // 1 -static const uint64_t SH_FLD_RSD_CRD_EQ_POST_LEN = 16145; // 1 -static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1 = 16146; // 1 -static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1_LEN = 16147; // 1 -static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2 = 16148; // 1 -static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2_LEN = 16149; // 1 -static const uint64_t SH_FLD_RSD_DMA_READ = 16150; // 1 -static const uint64_t SH_FLD_RSD_DMA_READ_LEN = 16151; // 1 -static const uint64_t SH_FLD_RSD_DMA_WRITE = 16152; // 1 -static const uint64_t SH_FLD_RSD_DMA_WRITE_LEN = 16153; // 1 -static const uint64_t SH_FLD_RSD_TCTXT_WRITE = 16154; // 1 -static const uint64_t SH_FLD_RSD_TCTXT_WRITE_LEN = 16155; // 1 -static const uint64_t SH_FLD_RSD_VPC_LD_RMT = 16156; // 1 -static const uint64_t SH_FLD_RSD_VPC_LD_RMT_LEN = 16157; // 1 -static const uint64_t SH_FLD_RSD_VPC_ST_RMT = 16158; // 1 -static const uint64_t SH_FLD_RSD_VPC_ST_RMT_LEN = 16159; // 1 -static const uint64_t SH_FLD_RSD_VPC_ST_RMT_VC = 16160; // 1 -static const uint64_t SH_FLD_RSD_VPC_ST_RMT_VC_LEN = 16161; // 1 -static const uint64_t SH_FLD_RSEL = 16162; // 10 -static const uint64_t SH_FLD_RSEL_LEN = 16163; // 10 -static const uint64_t SH_FLD_RSPOUT_CE_ESR = 16164; // 1 -static const uint64_t SH_FLD_RSPOUT_UE_ESR = 16165; // 1 -static const uint64_t SH_FLD_RSP_AE_ALWAYS = 16166; // 6 -static const uint64_t SH_FLD_RSP_CTL_CRED_SINGLE_ENA = 16167; // 6 -static const uint64_t SH_FLD_RSV17 = 16168; // 2 -static const uint64_t SH_FLD_RSV18 = 16169; // 2 -static const uint64_t SH_FLD_RSV19 = 16170; // 2 -static const uint64_t SH_FLD_RSV26 = 16171; // 2 -static const uint64_t SH_FLD_RSV27 = 16172; // 2 -static const uint64_t SH_FLD_RSV34 = 16173; // 2 -static const uint64_t SH_FLD_RSV35 = 16174; // 2 -static const uint64_t SH_FLD_RSV6 = 16175; // 2 -static const uint64_t SH_FLD_RSV7 = 16176; // 2 -static const uint64_t SH_FLD_RSVD = 16177; // 2 -static const uint64_t SH_FLD_RSVD0 = 16178; // 1 -static const uint64_t SH_FLD_RSVD0_LEN = 16179; // 1 -static const uint64_t SH_FLD_RSVD1 = 16180; // 1 -static const uint64_t SH_FLD_RSVD1_LEN = 16181; // 1 -static const uint64_t SH_FLD_RSVD_35_43 = 16182; // 8 -static const uint64_t SH_FLD_RSVD_35_43_LEN = 16183; // 8 -static const uint64_t SH_FLD_RSVD_LEN = 16184; // 1 -static const uint64_t SH_FLD_RTAGFLUSH_FAILED = 16185; // 2 -static const uint64_t SH_FLD_RTAG_PARITY = 16186; // 1 -static const uint64_t SH_FLD_RTAG_PERR = 16187; // 1 -static const uint64_t SH_FLD_RTIM_THOLD_FORCE = 16188; // 43 -static const uint64_t SH_FLD_RTT_WR0_NOM_VALUE = 16189; // 8 -static const uint64_t SH_FLD_RTT_WR0_NOM_VALUE_LEN = 16190; // 8 -static const uint64_t SH_FLD_RTT_WR1_NOM_VALUE = 16191; // 8 -static const uint64_t SH_FLD_RTT_WR1_NOM_VALUE_LEN = 16192; // 8 -static const uint64_t SH_FLD_RTT_WR2_NOM_VALUE = 16193; // 8 -static const uint64_t SH_FLD_RTT_WR2_NOM_VALUE_LEN = 16194; // 8 -static const uint64_t SH_FLD_RTT_WR3_NOM_VALUE = 16195; // 8 -static const uint64_t SH_FLD_RTT_WR3_NOM_VALUE_LEN = 16196; // 8 -static const uint64_t SH_FLD_RTT_WR4_NOM_VALUE = 16197; // 8 -static const uint64_t SH_FLD_RTT_WR4_NOM_VALUE_LEN = 16198; // 8 -static const uint64_t SH_FLD_RTT_WR5_NOM_VALUE = 16199; // 8 -static const uint64_t SH_FLD_RTT_WR5_NOM_VALUE_LEN = 16200; // 8 -static const uint64_t SH_FLD_RTT_WR6_NOM_VALUE = 16201; // 8 -static const uint64_t SH_FLD_RTT_WR6_NOM_VALUE_LEN = 16202; // 8 -static const uint64_t SH_FLD_RTT_WR7_NOM_VALUE = 16203; // 8 -static const uint64_t SH_FLD_RTT_WR7_NOM_VALUE_LEN = 16204; // 8 -static const uint64_t SH_FLD_RTY_COUNT = 16205; // 2 -static const uint64_t SH_FLD_RTY_COUNT_LEN = 16206; // 2 -static const uint64_t SH_FLD_RUNNING = 16207; // 92 -static const uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE = 16208; // 43 -static const uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN = 16209; // 43 -static const uint64_t SH_FLD_RUNN_MODE = 16210; // 43 -static const uint64_t SH_FLD_RUN_CHIPLET_SCAN0 = 16211; // 43 -static const uint64_t SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL = 16212; // 43 -static const uint64_t SH_FLD_RUN_DCCAL = 16213; // 48 -static const uint64_t SH_FLD_RUN_DYN_RECAL_TIMER = 16214; // 4 -static const uint64_t SH_FLD_RUN_LANE = 16215; // 48 -static const uint64_t SH_FLD_RUN_LANE_DL_MASK = 16216; // 2 -static const uint64_t SH_FLD_RUN_ON_CAPTURE_DR = 16217; // 43 -static const uint64_t SH_FLD_RUN_ON_UPDATE_DR = 16218; // 43 -static const uint64_t SH_FLD_RUN_SCAN0 = 16219; // 43 -static const uint64_t SH_FLD_RUN_STATE_MASK = 16220; // 43 -static const uint64_t SH_FLD_RUN_TCK = 16221; // 1 -static const uint64_t SH_FLD_RUN_TCK_EQ0_ERR = 16222; // 1 -static const uint64_t SH_FLD_RWDM_DLY = 16223; // 8 -static const uint64_t SH_FLD_RWDM_DLY_LEN = 16224; // 8 -static const uint64_t SH_FLD_RWSMDR_DLY = 16225; // 8 -static const uint64_t SH_FLD_RWSMDR_DLY_LEN = 16226; // 8 -static const uint64_t SH_FLD_RWSMSR_DLY = 16227; // 8 -static const uint64_t SH_FLD_RWSMSR_DLY_LEN = 16228; // 8 -static const uint64_t SH_FLD_RX = 16229; // 8 -static const uint64_t SH_FLD_RXAERR = 16230; // 6 -static const uint64_t SH_FLD_RXBERR = 16231; // 6 -static const uint64_t SH_FLD_RXCAL = 16232; // 116 -static const uint64_t SH_FLD_RXCERR = 16233; // 6 -static const uint64_t SH_FLD_RXDERR = 16234; // 6 -static const uint64_t SH_FLD_RXEERR = 16235; // 6 -static const uint64_t SH_FLD_RXFERR = 16236; // 6 -static const uint64_t SH_FLD_RXGERR = 16237; // 6 -static const uint64_t SH_FLD_RXHERR = 16238; // 6 -static const uint64_t SH_FLD_RXIERR = 16239; // 6 -static const uint64_t SH_FLD_RXJERR = 16240; // 6 -static const uint64_t SH_FLD_RXKERR = 16241; // 6 -static const uint64_t SH_FLD_RXLERR = 16242; // 6 -static const uint64_t SH_FLD_RXMERR = 16243; // 6 -static const uint64_t SH_FLD_RXNERR = 16244; // 6 -static const uint64_t SH_FLD_RXOERR = 16245; // 6 -static const uint64_t SH_FLD_RXPERR = 16246; // 6 -static const uint64_t SH_FLD_RX_BUS_WIDTH = 16247; // 4 -static const uint64_t SH_FLD_RX_BUS_WIDTH_LEN = 16248; // 4 -static const uint64_t SH_FLD_RX_BW = 16249; // 10 -static const uint64_t SH_FLD_RX_BW_LEN = 16250; // 10 -static const uint64_t SH_FLD_RX_PCB_DATA_P = 16251; // 1 -static const uint64_t SH_FLD_RX_PCB_DATA_P_ERR = 16252; // 1 -static const uint64_t SH_FLD_RX_SELECT = 16253; // 4 -static const uint64_t SH_FLD_RX_SELECT_LEN = 16254; // 4 -static const uint64_t SH_FLD_RX_TTYPE_0 = 16255; // 4 -static const uint64_t SH_FLD_RX_TTYPE_1 = 16256; // 4 -static const uint64_t SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE = 16257; // 1 -static const uint64_t SH_FLD_RX_TTYPE_2 = 16258; // 4 -static const uint64_t SH_FLD_RX_TTYPE_3 = 16259; // 4 -static const uint64_t SH_FLD_RX_TTYPE_4 = 16260; // 4 -static const uint64_t SH_FLD_RX_TTYPE_4_DATA_PARITY = 16261; // 4 -static const uint64_t SH_FLD_RX_TTYPE_5 = 16262; // 4 -static const uint64_t SH_FLD_RX_TTYPE_INVALID = 16263; // 4 -static const uint64_t SH_FLD_S0_BIT_MAP = 16264; // 8 -static const uint64_t SH_FLD_S0_BIT_MAP_LEN = 16265; // 8 -static const uint64_t SH_FLD_S1_BIT_MAP = 16266; // 8 -static const uint64_t SH_FLD_S1_BIT_MAP_LEN = 16267; // 8 -static const uint64_t SH_FLD_S2_BIT_MAP = 16268; // 8 -static const uint64_t SH_FLD_S2_BIT_MAP_LEN = 16269; // 8 -static const uint64_t SH_FLD_SACOLL = 16270; // 12 -static const uint64_t SH_FLD_SAFE_REFRESH_MODE = 16271; // 8 -static const uint64_t SH_FLD_SAMPLED_SMD_PIN = 16272; // 1 -static const uint64_t SH_FLD_SAMPLE_GUTS = 16273; // 43 -static const uint64_t SH_FLD_SAMPLE_GUTS_LEN = 16274; // 43 -static const uint64_t SH_FLD_SAMPLE_PULSE_CNT = 16275; // 43 -static const uint64_t SH_FLD_SAMPLE_PULSE_CNT_LEN = 16276; // 43 -static const uint64_t SH_FLD_SAMPLE_VALID = 16277; // 12 -static const uint64_t SH_FLD_SAMPTEST_ENABLE = 16278; // 1 -static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX = 16279; // 1 -static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN = 16280; // 1 -static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN = 16281; // 1 -static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN = 16282; // 1 -static const uint64_t SH_FLD_SAMPTEST_RRN_ENABLE = 16283; // 1 -static const uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE = 16284; // 1 -static const uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE_LEN = 16285; // 1 -static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16286; // 43 -static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 16287; // 43 -static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 16288; // 43 -static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 16289; // 43 -static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 16290; // 43 -static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 16291; // 43 -static const uint64_t SH_FLD_SBASE = 16292; // 12 -static const uint64_t SH_FLD_SBASE_LEN = 16293; // 12 -static const uint64_t SH_FLD_SBC_DMA = 16294; // 1 -static const uint64_t SH_FLD_SBC_DMA_LEN = 16295; // 1 -static const uint64_t SH_FLD_SBC_EOI = 16296; // 1 -static const uint64_t SH_FLD_SBC_EOI_LEN = 16297; // 1 -static const uint64_t SH_FLD_SBC_LOOKUP = 16298; // 1 -static const uint64_t SH_FLD_SBC_LOOKUP_LEN = 16299; // 1 -static const uint64_t SH_FLD_SBEFIFO_DATA = 16300; // 5 -static const uint64_t SH_FLD_SBEFIFO_RESET = 16301; // 5 -static const uint64_t SH_FLD_SBE_ERROR_RATE = 16302; // 5 -static const uint64_t SH_FLD_SBE_ERROR_RATE_LEN = 16303; // 5 -static const uint64_t SH_FLD_SBE_EXTERNAL_FIRS = 16304; // 1 -static const uint64_t SH_FLD_SBE_EXTERNAL_FIRS_LEN = 16305; // 1 -static const uint64_t SH_FLD_SB_SCOM_ERRHOLD = 16306; // 2 -static const uint64_t SH_FLD_SB_STRENGTH = 16307; // 43 -static const uint64_t SH_FLD_SB_STRENGTH_LEN = 16308; // 43 -static const uint64_t SH_FLD_SCAN0_MODE = 16309; // 43 -static const uint64_t SH_FLD_SCAN_CLK_USE_EVEN = 16310; // 43 -static const uint64_t SH_FLD_SCAN_COUNT = 16311; // 43 -static const uint64_t SH_FLD_SCAN_COUNT_LEN = 16312; // 43 -static const uint64_t SH_FLD_SCAN_INIT_VERSION_PARITY_MASK = 16313; // 43 -static const uint64_t SH_FLD_SCAN_RATIO = 16314; // 43 -static const uint64_t SH_FLD_SCAN_RATIO_LEN = 16315; // 43 -static const uint64_t SH_FLD_SCOM1_SAT_ERR = 16316; // 2 -static const uint64_t SH_FLD_SCOM20A_SEL = 16317; // 8 -static const uint64_t SH_FLD_SCOMFIR_INT_ERR_0 = 16318; // 2 -static const uint64_t SH_FLD_SCOMFIR_INT_ERR_1 = 16319; // 2 -static const uint64_t SH_FLD_SCOMSAT00_ERR = 16320; // 1 -static const uint64_t SH_FLD_SCOMSAT01_ERR = 16321; // 1 -static const uint64_t SH_FLD_SCOM_CMD_REG_INJ = 16322; // 2 -static const uint64_t SH_FLD_SCOM_CMD_REG_INJ_MODE = 16323; // 2 -static const uint64_t SH_FLD_SCOM_ERR = 16324; // 26 -static const uint64_t SH_FLD_SCOM_ERR1 = 16325; // 36 -static const uint64_t SH_FLD_SCOM_ERR2 = 16326; // 40 -static const uint64_t SH_FLD_SCOM_ERROR = 16327; // 10 -static const uint64_t SH_FLD_SCOM_ERR_DUP = 16328; // 22 -static const uint64_t SH_FLD_SCOM_FATAL_ERROR = 16329; // 6 -static const uint64_t SH_FLD_SCOM_FATAL_REG_PE = 16330; // 2 -static const uint64_t SH_FLD_SCOM_FIR_HMI = 16331; // 96 -static const uint64_t SH_FLD_SCOM_HANG_LIMIT = 16332; // 43 -static const uint64_t SH_FLD_SCOM_HANG_LIMIT_LEN = 16333; // 43 -static const uint64_t SH_FLD_SCOM_INF_ERROR = 16334; // 6 -static const uint64_t SH_FLD_SCOM_LINK01_RESET_KEEPER = 16335; // 2 -static const uint64_t SH_FLD_SCOM_LINK23_RESET_KEEPER = 16336; // 2 -static const uint64_t SH_FLD_SCOM_LINK45_RESET_KEEPER = 16337; // 2 -static const uint64_t SH_FLD_SCOM_LINK67_RESET_KEEPER = 16338; // 1 -static const uint64_t SH_FLD_SCOM_MMIO_ADDR_ERR = 16339; // 2 -static const uint64_t SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE = 16340; // 8 -static const uint64_t SH_FLD_SCOM_PARITY_CLASS_STATUS = 16341; // 8 -static const uint64_t SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE = 16342; // 8 -static const uint64_t SH_FLD_SCOM_PARITY_ERR = 16343; // 3 -static const uint64_t SH_FLD_SCOM_PARITY_ERR2 = 16344; // 3 -static const uint64_t SH_FLD_SCOM_PE = 16345; // 3 -static const uint64_t SH_FLD_SCOM_PERFMON_START_COMMAND = 16346; // 4 -static const uint64_t SH_FLD_SCOM_PERFMON_STOP_COMMAND = 16347; // 4 -static const uint64_t SH_FLD_SCOM_PERR0 = 16348; // 6 -static const uint64_t SH_FLD_SCOM_PERR1 = 16349; // 6 -static const uint64_t SH_FLD_SCOM_PE_DUP = 16350; // 3 -static const uint64_t SH_FLD_SCOM_PE_DUP_FIR = 16351; // 1 -static const uint64_t SH_FLD_SCOM_PE_FIR = 16352; // 1 -static const uint64_t SH_FLD_SCOM_RECOVERABLE_REG_PE = 16353; // 2 -static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_ARM = 16354; // 2 -static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_RESET = 16355; // 2 -static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_TRIGGER = 16356; // 2 -static const uint64_t SH_FLD_SCOM_S_ERR = 16357; // 1 -static const uint64_t SH_FLD_SCOM_WRITE = 16358; // 24 -static const uint64_t SH_FLD_SCOPE = 16359; // 24 -static const uint64_t SH_FLD_SCOPE_ATTN_BAR = 16360; // 1 -static const uint64_t SH_FLD_SCOPE_ATTN_BAR_LEN = 16361; // 1 -static const uint64_t SH_FLD_SCOPE_CONTROL = 16362; // 6 -static const uint64_t SH_FLD_SCOPE_CONTROL_LEN = 16363; // 6 -static const uint64_t SH_FLD_SCOPE_LEN = 16364; // 24 -static const uint64_t SH_FLD_SCOPE_MODE = 16365; // 48 -static const uint64_t SH_FLD_SCOPE_MODE_LEN = 16366; // 48 -static const uint64_t SH_FLD_SCPTGT_LFSR_MODE = 16367; // 2 -static const uint64_t SH_FLD_SCPTGT_LFSR_MODE_LEN = 16368; // 2 -static const uint64_t SH_FLD_SCRATCH_ATOMIC_DATA = 16369; // 24 -static const uint64_t SH_FLD_SCRATCH_ATOMIC_DATA_LEN = 16370; // 24 -static const uint64_t SH_FLD_SCRATCH_N = 16371; // 4 -static const uint64_t SH_FLD_SCRATCH_N_LEN = 16372; // 4 -static const uint64_t SH_FLD_SC_RDATA_PARITY_ERRHOLD = 16373; // 2 -static const uint64_t SH_FLD_SEC = 16374; // 8 -static const uint64_t SH_FLD_SECOND = 16375; // 1 -static const uint64_t SH_FLD_SECURE = 16376; // 1 -static const uint64_t SH_FLD_SECURE_ACCESS = 16377; // 1 -static const uint64_t SH_FLD_SECURE_ACCESS_BIT = 16378; // 1 -static const uint64_t SH_FLD_SECURE_DEBUG = 16379; // 1 -static const uint64_t SH_FLD_SECURE_DEBUG_MODE = 16380; // 1 -static const uint64_t SH_FLD_SECURE_ERR = 16381; // 2 -static const uint64_t SH_FLD_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD = 16382; // 2 -static const uint64_t SH_FLD_SECURE_LNK_SCOM_CONFLICT_ERRHOLD = 16383; // 2 -static const uint64_t SH_FLD_SECURE_SCOM_ERROR = 16384; // 4 -static const uint64_t SH_FLD_SECURITY_DEBUG_MODE = 16385; // 43 -static const uint64_t SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE = 16386; // 1 -static const uint64_t SH_FLD_SEC_LEN = 16387; // 8 -static const uint64_t SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE = 16388; // 1 -static const uint64_t SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE = 16389; // 1 -static const uint64_t SH_FLD_SEC_M_PATH_SELECT = 16390; // 2 -static const uint64_t SH_FLD_SEC_M_S_DRAWER_SELECT = 16391; // 2 -static const uint64_t SH_FLD_SEC_M_S_SELECT = 16392; // 2 -static const uint64_t SH_FLD_SEC_SELECT = 16393; // 1 -static const uint64_t SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE = 16394; // 1 -static const uint64_t SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE = 16395; // 1 -static const uint64_t SH_FLD_SEC_S_PATH_SELECT = 16396; // 1 -static const uint64_t SH_FLD_SEC_V = 16397; // 8 -static const uint64_t SH_FLD_SEC_WBRD_DEBUG_0_SELECT = 16398; // 8 -static const uint64_t SH_FLD_SEC_WBRD_DEBUG_1_SELECT = 16399; // 8 -static const uint64_t SH_FLD_SEEPROM_UPDATE_LOCK = 16400; // 1 -static const uint64_t SH_FLD_SEG_TEST_CLK_STATUS = 16401; // 4 -static const uint64_t SH_FLD_SEG_TEST_CLK_STATUS_LEN = 16402; // 4 -static const uint64_t SH_FLD_SEG_TEST_LEAKAGE_CTRL = 16403; // 6 -static const uint64_t SH_FLD_SEG_TEST_MODE = 16404; // 6 -static const uint64_t SH_FLD_SEG_TEST_MODE_LEN = 16405; // 6 -static const uint64_t SH_FLD_SEG_TEST_STATUS = 16406; // 116 -static const uint64_t SH_FLD_SEG_TEST_STATUS_LEN = 16407; // 116 -static const uint64_t SH_FLD_SEIDBAR = 16408; // 1 -static const uint64_t SH_FLD_SEIDBAR_LEN = 16409; // 1 -static const uint64_t SH_FLD_SEIDR = 16410; // 256 -static const uint64_t SH_FLD_SEIDR_LEN = 16411; // 256 -static const uint64_t SH_FLD_SEL = 16412; // 10 -static const uint64_t SH_FLD_SEL0 = 16413; // 1 -static const uint64_t SH_FLD_SEL0_LEN = 16414; // 1 -static const uint64_t SH_FLD_SEL1 = 16415; // 1 -static const uint64_t SH_FLD_SEL1_LEN = 16416; // 1 -static const uint64_t SH_FLD_SELD2SPR = 16417; // 10 -static const uint64_t SH_FLD_SELECT = 16418; // 2 -static const uint64_t SH_FLD_SELECT_0 = 16419; // 5 -static const uint64_t SH_FLD_SELECT_0_LEN = 16420; // 5 -static const uint64_t SH_FLD_SELECT_1 = 16421; // 5 -static const uint64_t SH_FLD_SELECT_1_LEN = 16422; // 5 -static const uint64_t SH_FLD_SELECT_2 = 16423; // 5 -static const uint64_t SH_FLD_SELECT_2_LEN = 16424; // 5 -static const uint64_t SH_FLD_SELECT_3 = 16425; // 5 -static const uint64_t SH_FLD_SELECT_3_LEN = 16426; // 5 -static const uint64_t SH_FLD_SELECT_4 = 16427; // 5 -static const uint64_t SH_FLD_SELECT_4_LEN = 16428; // 5 -static const uint64_t SH_FLD_SELECT_5 = 16429; // 5 -static const uint64_t SH_FLD_SELECT_5_LEN = 16430; // 5 -static const uint64_t SH_FLD_SELECT_6 = 16431; // 5 -static const uint64_t SH_FLD_SELECT_6_LEN = 16432; // 5 -static const uint64_t SH_FLD_SELECT_7 = 16433; // 5 -static const uint64_t SH_FLD_SELECT_7_LEN = 16434; // 5 -static const uint64_t SH_FLD_SELECT_LEN = 16435; // 2 -static const uint64_t SH_FLD_SELECT_LOCAL_HANG_PULSE = 16436; // 4 -static const uint64_t SH_FLD_SELECT_PB_HANG_PULSE = 16437; // 4 -static const uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB = 16438; // 1 -static const uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB_LEN = 16439; // 1 -static const uint64_t SH_FLD_SELECT_SECONDARY_SEEPROM = 16440; // 1 -static const uint64_t SH_FLD_SELFBOOT_DONE = 16441; // 1 -static const uint64_t SH_FLD_SELFBOOT_ENGINE_ATTENTION = 16442; // 1 -static const uint64_t SH_FLD_SELF_BUSY_0 = 16443; // 4 -static const uint64_t SH_FLD_SELF_BUSY_1 = 16444; // 2 -static const uint64_t SH_FLD_SELF_BUSY_2 = 16445; // 2 -static const uint64_t SH_FLD_SELF_BUSY_3 = 16446; // 2 -static const uint64_t SH_FLD_SELPFDPW = 16447; // 10 -static const uint64_t SH_FLD_SELPREFB = 16448; // 10 -static const uint64_t SH_FLD_SELPRESPE = 16449; // 10 -static const uint64_t SH_FLD_SEL_03_NPU_NOT = 16450; // 1 -static const uint64_t SH_FLD_SEL_04_NPU_NOT = 16451; // 1 -static const uint64_t SH_FLD_SEL_05_NPU_NOT = 16452; // 1 -static const uint64_t SH_FLD_SEL_0_2 = 16453; // 16 -static const uint64_t SH_FLD_SEL_0_2_LEN = 16454; // 16 -static const uint64_t SH_FLD_SEL_1_3 = 16455; // 16 -static const uint64_t SH_FLD_SEL_1_3_LEN = 16456; // 16 -static const uint64_t SH_FLD_SEL_LEN = 16457; // 10 -static const uint64_t SH_FLD_SEL_RG_PMU_DATA = 16458; // 1 -static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI = 16459; // 1 -static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI_LEN = 16460; // 1 -static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO = 16461; // 1 -static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO_LEN = 16462; // 1 -static const uint64_t SH_FLD_SEL_RG_TRIGGERS_01 = 16463; // 1 -static const uint64_t SH_FLD_SEL_RG_TRIGGERS_01_LEN = 16464; // 1 -static const uint64_t SH_FLD_SEL_RG_TRIGGERS_23 = 16465; // 1 -static const uint64_t SH_FLD_SEL_RG_TRIGGERS_23_LEN = 16466; // 1 -static const uint64_t SH_FLD_SEL_THOLD_ARY = 16467; // 43 -static const uint64_t SH_FLD_SEL_THOLD_NSL = 16468; // 43 -static const uint64_t SH_FLD_SEL_THOLD_SL = 16469; // 43 -static const uint64_t SH_FLD_SEL_TYPE_0_2 = 16470; // 16 -static const uint64_t SH_FLD_SEL_TYPE_1_3 = 16471; // 16 -static const uint64_t SH_FLD_SEND_DELAY_CYCLES = 16472; // 2 -static const uint64_t SH_FLD_SEND_DELAY_CYCLES_LEN = 16473; // 2 -static const uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE = 16474; // 2 -static const uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE_LEN = 16475; // 2 -static const uint64_t SH_FLD_SENSEADJ_RESET0 = 16476; // 43 -static const uint64_t SH_FLD_SENSEADJ_RESET1 = 16477; // 43 -static const uint64_t SH_FLD_SEQ = 16478; // 8 -static const uint64_t SH_FLD_SEQ_01 = 16479; // 43 -static const uint64_t SH_FLD_SEQ_01_LEN = 16480; // 43 -static const uint64_t SH_FLD_SEQ_02 = 16481; // 43 -static const uint64_t SH_FLD_SEQ_02_LEN = 16482; // 43 -static const uint64_t SH_FLD_SEQ_03 = 16483; // 43 -static const uint64_t SH_FLD_SEQ_03_LEN = 16484; // 43 -static const uint64_t SH_FLD_SEQ_04 = 16485; // 43 -static const uint64_t SH_FLD_SEQ_04_LEN = 16486; // 43 -static const uint64_t SH_FLD_SEQ_05 = 16487; // 43 -static const uint64_t SH_FLD_SEQ_05_LEN = 16488; // 43 -static const uint64_t SH_FLD_SEQ_06 = 16489; // 43 -static const uint64_t SH_FLD_SEQ_06_LEN = 16490; // 43 -static const uint64_t SH_FLD_SEQ_07 = 16491; // 43 -static const uint64_t SH_FLD_SEQ_07EVEN = 16492; // 43 -static const uint64_t SH_FLD_SEQ_07EVEN_LEN = 16493; // 43 -static const uint64_t SH_FLD_SEQ_07ODD = 16494; // 43 -static const uint64_t SH_FLD_SEQ_07ODD_LEN = 16495; // 43 -static const uint64_t SH_FLD_SEQ_07_LEN = 16496; // 43 -static const uint64_t SH_FLD_SEQ_08 = 16497; // 43 -static const uint64_t SH_FLD_SEQ_08EVEN = 16498; // 43 -static const uint64_t SH_FLD_SEQ_08EVEN_LEN = 16499; // 43 -static const uint64_t SH_FLD_SEQ_08ODD = 16500; // 43 -static const uint64_t SH_FLD_SEQ_08ODD_LEN = 16501; // 43 -static const uint64_t SH_FLD_SEQ_08_LEN = 16502; // 43 -static const uint64_t SH_FLD_SEQ_09 = 16503; // 43 -static const uint64_t SH_FLD_SEQ_09EVEN = 16504; // 43 -static const uint64_t SH_FLD_SEQ_09EVEN_LEN = 16505; // 43 -static const uint64_t SH_FLD_SEQ_09ODD = 16506; // 43 -static const uint64_t SH_FLD_SEQ_09ODD_LEN = 16507; // 43 -static const uint64_t SH_FLD_SEQ_09_LEN = 16508; // 43 -static const uint64_t SH_FLD_SEQ_10 = 16509; // 43 -static const uint64_t SH_FLD_SEQ_10EVEN = 16510; // 43 -static const uint64_t SH_FLD_SEQ_10EVEN_LEN = 16511; // 43 -static const uint64_t SH_FLD_SEQ_10ODD = 16512; // 43 -static const uint64_t SH_FLD_SEQ_10ODD_LEN = 16513; // 43 -static const uint64_t SH_FLD_SEQ_10_LEN = 16514; // 43 -static const uint64_t SH_FLD_SEQ_11 = 16515; // 43 -static const uint64_t SH_FLD_SEQ_11EVEN = 16516; // 43 -static const uint64_t SH_FLD_SEQ_11EVEN_LEN = 16517; // 43 -static const uint64_t SH_FLD_SEQ_11ODD = 16518; // 43 -static const uint64_t SH_FLD_SEQ_11ODD_LEN = 16519; // 43 -static const uint64_t SH_FLD_SEQ_11_LEN = 16520; // 43 -static const uint64_t SH_FLD_SEQ_12 = 16521; // 43 -static const uint64_t SH_FLD_SEQ_12EVEN = 16522; // 43 -static const uint64_t SH_FLD_SEQ_12EVEN_LEN = 16523; // 43 -static const uint64_t SH_FLD_SEQ_12ODD = 16524; // 43 -static const uint64_t SH_FLD_SEQ_12ODD_LEN = 16525; // 43 -static const uint64_t SH_FLD_SEQ_12_LEN = 16526; // 43 -static const uint64_t SH_FLD_SEQ_13_01EVEN = 16527; // 43 -static const uint64_t SH_FLD_SEQ_13_01EVEN_LEN = 16528; // 43 -static const uint64_t SH_FLD_SEQ_14_01ODD = 16529; // 43 -static const uint64_t SH_FLD_SEQ_14_01ODD_LEN = 16530; // 43 -static const uint64_t SH_FLD_SEQ_15_02EVEN = 16531; // 43 -static const uint64_t SH_FLD_SEQ_15_02EVEN_LEN = 16532; // 43 -static const uint64_t SH_FLD_SEQ_16_02ODD = 16533; // 43 -static const uint64_t SH_FLD_SEQ_16_02ODD_LEN = 16534; // 43 -static const uint64_t SH_FLD_SEQ_17_03EVEN = 16535; // 43 -static const uint64_t SH_FLD_SEQ_17_03EVEN_LEN = 16536; // 43 -static const uint64_t SH_FLD_SEQ_18_03ODD = 16537; // 43 -static const uint64_t SH_FLD_SEQ_18_03ODD_LEN = 16538; // 43 -static const uint64_t SH_FLD_SEQ_19_04EVEN = 16539; // 43 -static const uint64_t SH_FLD_SEQ_19_04EVEN_LEN = 16540; // 43 -static const uint64_t SH_FLD_SEQ_20_04ODD = 16541; // 43 -static const uint64_t SH_FLD_SEQ_20_04ODD_LEN = 16542; // 43 -static const uint64_t SH_FLD_SEQ_21_05EVEN = 16543; // 43 -static const uint64_t SH_FLD_SEQ_21_05EVEN_LEN = 16544; // 43 -static const uint64_t SH_FLD_SEQ_22_05ODD = 16545; // 43 -static const uint64_t SH_FLD_SEQ_22_05ODD_LEN = 16546; // 43 -static const uint64_t SH_FLD_SEQ_23_06EVEN = 16547; // 43 -static const uint64_t SH_FLD_SEQ_23_06EVEN_LEN = 16548; // 43 -static const uint64_t SH_FLD_SEQ_24_06ODD = 16549; // 43 -static const uint64_t SH_FLD_SEQ_24_06ODD_LEN = 16550; // 43 -static const uint64_t SH_FLD_SEQ_MASK = 16551; // 8 -static const uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 16552; // 43 -static const uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 16553; // 43 -static const uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16554; // 43 -static const uint64_t SH_FLD_SERVO_CHG_CFG = 16555; // 6 -static const uint64_t SH_FLD_SERVO_CHG_CFG_LEN = 16556; // 6 -static const uint64_t SH_FLD_SERVO_CONFIG = 16557; // 6 -static const uint64_t SH_FLD_SERVO_CONFIG_LEN = 16558; // 6 -static const uint64_t SH_FLD_SERVO_DONE = 16559; // 6 -static const uint64_t SH_FLD_SERVO_OP = 16560; // 6 -static const uint64_t SH_FLD_SERVO_OP_LEN = 16561; // 6 -static const uint64_t SH_FLD_SERVO_RECAL_IP = 16562; // 4 -static const uint64_t SH_FLD_SERVO_RESULT = 16563; // 6 -static const uint64_t SH_FLD_SERVO_RESULT_LEN = 16564; // 6 -static const uint64_t SH_FLD_SERVO_THRESH1 = 16565; // 6 -static const uint64_t SH_FLD_SERVO_THRESH1_LEN = 16566; // 6 -static const uint64_t SH_FLD_SERVO_THRESH2 = 16567; // 6 -static const uint64_t SH_FLD_SERVO_THRESH2_LEN = 16568; // 6 -static const uint64_t SH_FLD_SERVO_THRESH3 = 16569; // 4 -static const uint64_t SH_FLD_SERVO_THRESH3_LEN = 16570; // 4 -static const uint64_t SH_FLD_SET = 16571; // 6 -static const uint64_t SH_FLD_SET_CMDS = 16572; // 2 -static const uint64_t SH_FLD_SET_CMDS_EN = 16573; // 2 -static const uint64_t SH_FLD_SET_CMDS_LEN = 16574; // 2 -static const uint64_t SH_FLD_SET_ECC_INJECT_ERR = 16575; // 12 -static const uint64_t SH_FLD_SET_EXT_ARM = 16576; // 4 -static const uint64_t SH_FLD_SET_EXT_RESET = 16577; // 4 -static const uint64_t SH_FLD_SET_EXT_TRIGGER = 16578; // 4 -static const uint64_t SH_FLD_SET_INDEX = 16579; // 2 -static const uint64_t SH_FLD_SET_INDEX_LEN = 16580; // 2 -static const uint64_t SH_FLD_SET_LEN = 16581; // 6 -static const uint64_t SH_FLD_SGB_BYTE_VALID = 16582; // 21 -static const uint64_t SH_FLD_SGB_BYTE_VALID_LEN = 16583; // 21 -static const uint64_t SH_FLD_SGB_FLUSH_PENDING = 16584; // 21 -static const uint64_t SH_FLD_SG_HIGH_DURING_FILL = 16585; // 43 -static const uint64_t SH_FLD_SHADOW_ANALOGTUNE = 16586; // 14 -static const uint64_t SH_FLD_SHADOW_ANALOGTUNE_LEN = 16587; // 14 -static const uint64_t SH_FLD_SHADOW_ATSTSEL = 16588; // 14 -static const uint64_t SH_FLD_SHADOW_ATSTSEL_LEN = 16589; // 14 -static const uint64_t SH_FLD_SHADOW_BANDSEL = 16590; // 14 -static const uint64_t SH_FLD_SHADOW_BANDSEL_LEN = 16591; // 14 -static const uint64_t SH_FLD_SHADOW_BGOFFSET = 16592; // 14 -static const uint64_t SH_FLD_SHADOW_BGOFFSET_LEN = 16593; // 14 -static const uint64_t SH_FLD_SHADOW_BYPASSN = 16594; // 10 -static const uint64_t SH_FLD_SHADOW_CALRECAL = 16595; // 10 -static const uint64_t SH_FLD_SHADOW_CALREQ = 16596; // 10 -static const uint64_t SH_FLD_SHADOW_CAPSEL = 16597; // 4 -static const uint64_t SH_FLD_SHADOW_CCALBANDSEL = 16598; // 10 -static const uint64_t SH_FLD_SHADOW_CCALBANDSEL_LEN = 16599; // 10 -static const uint64_t SH_FLD_SHADOW_CCALCOMP = 16600; // 10 -static const uint64_t SH_FLD_SHADOW_CCALCVHOLD = 16601; // 10 -static const uint64_t SH_FLD_SHADOW_CCALERR = 16602; // 10 -static const uint64_t SH_FLD_SHADOW_CCALFMAX = 16603; // 10 -static const uint64_t SH_FLD_SHADOW_CCALFMIN = 16604; // 10 -static const uint64_t SH_FLD_SHADOW_CCALLOAD = 16605; // 10 -static const uint64_t SH_FLD_SHADOW_CCALMETH = 16606; // 10 -static const uint64_t SH_FLD_SHADOW_CMLEN = 16607; // 7 -static const uint64_t SH_FLD_SHADOW_CMLEN100 = 16608; // 3 -static const uint64_t SH_FLD_SHADOW_CMLEN133 = 16609; // 3 -static const uint64_t SH_FLD_SHADOW_CMLEN156 = 16610; // 3 -static const uint64_t SH_FLD_SHADOW_CPISEL = 16611; // 14 -static const uint64_t SH_FLD_SHADOW_CPISEL_LEN = 16612; // 14 -static const uint64_t SH_FLD_SHADOW_CSEL = 16613; // 10 -static const uint64_t SH_FLD_SHADOW_CSEL_LEN = 16614; // 10 -static const uint64_t SH_FLD_SHADOW_DIVSELB = 16615; // 10 -static const uint64_t SH_FLD_SHADOW_DIVSELB_LEN = 16616; // 10 -static const uint64_t SH_FLD_SHADOW_DIVSELFB = 16617; // 4 -static const uint64_t SH_FLD_SHADOW_DIVSELFB_LEN = 16618; // 4 -static const uint64_t SH_FLD_SHADOW_EN = 16619; // 10 -static const uint64_t SH_FLD_SHADOW_ENABLE = 16620; // 10 -static const uint64_t SH_FLD_SHADOW_FILTDIVSEL = 16621; // 3 -static const uint64_t SH_FLD_SHADOW_FILTDIVSEL_LEN = 16622; // 3 -static const uint64_t SH_FLD_SHADOW_FRAC1 = 16623; // 3 -static const uint64_t SH_FLD_SHADOW_FRAC1_LEN = 16624; // 3 -static const uint64_t SH_FLD_SHADOW_FRAC2 = 16625; // 3 -static const uint64_t SH_FLD_SHADOW_FRAC2_LEN = 16626; // 3 -static const uint64_t SH_FLD_SHADOW_ITUNE = 16627; // 4 -static const uint64_t SH_FLD_SHADOW_ITUNE_LEN = 16628; // 4 -static const uint64_t SH_FLD_SHADOW_LOCK = 16629; // 10 -static const uint64_t SH_FLD_SHADOW_MUXEN = 16630; // 4 -static const uint64_t SH_FLD_SHADOW_MUXSEL = 16631; // 4 -static const uint64_t SH_FLD_SHADOW_MUXSEL_LEN = 16632; // 4 -static const uint64_t SH_FLD_SHADOW_PCLKDIFSEL = 16633; // 10 -static const uint64_t SH_FLD_SHADOW_PCLKSEL = 16634; // 14 -static const uint64_t SH_FLD_SHADOW_PCLKSEL_LEN = 16635; // 14 -static const uint64_t SH_FLD_SHADOW_PFD360SEL = 16636; // 4 -static const uint64_t SH_FLD_SHADOW_PHASEFB = 16637; // 4 -static const uint64_t SH_FLD_SHADOW_PHASEFB_LEN = 16638; // 4 -static const uint64_t SH_FLD_SHADOW_PLLLOCK = 16639; // 4 -static const uint64_t SH_FLD_SHADOW_RDIV = 16640; // 14 -static const uint64_t SH_FLD_SHADOW_RDIV_LEN = 16641; // 10 -static const uint64_t SH_FLD_SHADOW_REFCLKSEL = 16642; // 4 -static const uint64_t SH_FLD_SHADOW_RESET = 16643; // 10 -static const uint64_t SH_FLD_SHADOW_RESSEL = 16644; // 4 -static const uint64_t SH_FLD_SHADOW_RSEL = 16645; // 10 -static const uint64_t SH_FLD_SHADOW_RSEL_LEN = 16646; // 10 -static const uint64_t SH_FLD_SHADOW_SEL = 16647; // 10 -static const uint64_t SH_FLD_SHADOW_SELD2SPR = 16648; // 10 -static const uint64_t SH_FLD_SHADOW_SELPFDPW = 16649; // 10 -static const uint64_t SH_FLD_SHADOW_SELPREFB = 16650; // 10 -static const uint64_t SH_FLD_SHADOW_SELPRESPE = 16651; // 10 -static const uint64_t SH_FLD_SHADOW_SEL_LEN = 16652; // 10 -static const uint64_t SH_FLD_SHADOW_SPARE = 16653; // 7 -static const uint64_t SH_FLD_SHADOW_SPARE_LEN = 16654; // 3 -static const uint64_t SH_FLD_SHADOW_SPEDIV = 16655; // 10 -static const uint64_t SH_FLD_SHADOW_SPEDIV_LEN = 16656; // 10 -static const uint64_t SH_FLD_SHADOW_SSCGEN = 16657; // 3 -static const uint64_t SH_FLD_SHADOW_SYNCEN = 16658; // 7 -static const uint64_t SH_FLD_SHADOW_UNUSED23_31 = 16659; // 7 -static const uint64_t SH_FLD_SHADOW_UNUSED23_31_LEN = 16660; // 7 -static const uint64_t SH_FLD_SHADOW_UNUSED4 = 16661; // 7 -static const uint64_t SH_FLD_SHADOW_UNUSED5 = 16662; // 7 -static const uint64_t SH_FLD_SHADOW_UNUSED63 = 16663; // 3 -static const uint64_t SH_FLD_SHADOW_UNUSED88 = 16664; // 3 -static const uint64_t SH_FLD_SHADOW_UNUSED88_LEN = 16665; // 3 -static const uint64_t SH_FLD_SHADOW_VCORANGE = 16666; // 10 -static const uint64_t SH_FLD_SHADOW_VCORANGE_LEN = 16667; // 10 -static const uint64_t SH_FLD_SHADOW_VCOSEL = 16668; // 10 -static const uint64_t SH_FLD_SHADOW_VREGBYPASS = 16669; // 4 -static const uint64_t SH_FLD_SHADOW_VREGENABLE_N = 16670; // 4 -static const uint64_t SH_FLD_SHADOW_VSEL = 16671; // 10 -static const uint64_t SH_FLD_SHADOW_VSEL_LEN = 16672; // 10 -static const uint64_t SH_FLD_SHA_LATENCY_CFG = 16673; // 1 -static const uint64_t SH_FLD_SHIFTER_PARITY_MASK = 16674; // 43 -static const uint64_t SH_FLD_SHIFTER_VALID_MASK = 16675; // 43 -static const uint64_t SH_FLD_SIBLING_CORE_DROPOUT_ENABLE = 16676; // 12 -static const uint64_t SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN = 16677; // 12 -static const uint64_t SH_FLD_SIGNATURE = 16678; // 1 -static const uint64_t SH_FLD_SIGNATURE_LEN = 16679; // 1 -static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP0 = 16680; // 8 -static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP1 = 16681; // 8 -static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP2 = 16682; // 8 -static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP3 = 16683; // 8 -static const uint64_t SH_FLD_SINGLE_OUTSTANDING_CMD = 16684; // 1 -static const uint64_t SH_FLD_SIZE = 16685; // 45 -static const uint64_t SH_FLD_SIZE_0 = 16686; // 5 -static const uint64_t SH_FLD_SIZE_0_LEN = 16687; // 5 -static const uint64_t SH_FLD_SIZE_1 = 16688; // 5 -static const uint64_t SH_FLD_SIZE_1_LEN = 16689; // 5 -static const uint64_t SH_FLD_SIZE_2 = 16690; // 5 -static const uint64_t SH_FLD_SIZE_2_LEN = 16691; // 5 -static const uint64_t SH_FLD_SIZE_3 = 16692; // 5 -static const uint64_t SH_FLD_SIZE_3_LEN = 16693; // 5 -static const uint64_t SH_FLD_SIZE_4 = 16694; // 5 -static const uint64_t SH_FLD_SIZE_4_LEN = 16695; // 5 -static const uint64_t SH_FLD_SIZE_5 = 16696; // 5 -static const uint64_t SH_FLD_SIZE_5_LEN = 16697; // 5 -static const uint64_t SH_FLD_SIZE_6 = 16698; // 5 -static const uint64_t SH_FLD_SIZE_6_LEN = 16699; // 5 -static const uint64_t SH_FLD_SIZE_7 = 16700; // 5 -static const uint64_t SH_FLD_SIZE_7_LEN = 16701; // 5 -static const uint64_t SH_FLD_SIZE_LEN = 16702; // 45 -static const uint64_t SH_FLD_SKIP_G = 16703; // 4 -static const uint64_t SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS = 16704; // 2 -static const uint64_t SH_FLD_SKIP_RDCENTERING = 16705; // 8 -static const uint64_t SH_FLD_SKITTER0 = 16706; // 43 -static const uint64_t SH_FLD_SKITTER0_DELAY_SELECT = 16707; // 43 -static const uint64_t SH_FLD_SKITTER0_DELAY_SELECT_LEN = 16708; // 43 -static const uint64_t SH_FLD_SKITTER0_LEN = 16709; // 43 -static const uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_MASK = 16710; // 43 -static const uint64_t SH_FLD_SKITTER_MODEREG_PARITY_MASK = 16711; // 43 -static const uint64_t SH_FLD_SLAVE10_ERROR_CODE = 16712; // 1 -static const uint64_t SH_FLD_SLAVE10_ERROR_CODE_LEN = 16713; // 1 -static const uint64_t SH_FLD_SLAVE10_RESPONSE_BIT = 16714; // 1 -static const uint64_t SH_FLD_SLAVE11_ERROR_CODE = 16715; // 1 -static const uint64_t SH_FLD_SLAVE11_ERROR_CODE_LEN = 16716; // 1 -static const uint64_t SH_FLD_SLAVE11_RESPONSE_BIT = 16717; // 1 -static const uint64_t SH_FLD_SLAVE12_ERROR_CODE = 16718; // 1 -static const uint64_t SH_FLD_SLAVE12_ERROR_CODE_LEN = 16719; // 1 -static const uint64_t SH_FLD_SLAVE12_RESPONSE_BIT = 16720; // 1 -static const uint64_t SH_FLD_SLAVE13_ERROR_CODE = 16721; // 1 -static const uint64_t SH_FLD_SLAVE13_ERROR_CODE_LEN = 16722; // 1 -static const uint64_t SH_FLD_SLAVE13_RESPONSE_BIT = 16723; // 1 -static const uint64_t SH_FLD_SLAVE14_ERROR_CODE = 16724; // 1 -static const uint64_t SH_FLD_SLAVE14_ERROR_CODE_LEN = 16725; // 1 -static const uint64_t SH_FLD_SLAVE14_RESPONSE_BIT = 16726; // 1 -static const uint64_t SH_FLD_SLAVE15_ERROR_CODE = 16727; // 1 -static const uint64_t SH_FLD_SLAVE15_ERROR_CODE_LEN = 16728; // 1 -static const uint64_t SH_FLD_SLAVE15_RESPONSE_BIT = 16729; // 1 -static const uint64_t SH_FLD_SLAVE16_ERROR_CODE = 16730; // 1 -static const uint64_t SH_FLD_SLAVE16_ERROR_CODE_LEN = 16731; // 1 -static const uint64_t SH_FLD_SLAVE16_RESPONSE_BIT = 16732; // 1 -static const uint64_t SH_FLD_SLAVE17_ERROR_CODE = 16733; // 1 -static const uint64_t SH_FLD_SLAVE17_ERROR_CODE_LEN = 16734; // 1 -static const uint64_t SH_FLD_SLAVE17_RESPONSE_BIT = 16735; // 1 -static const uint64_t SH_FLD_SLAVE18_ERROR_CODE = 16736; // 1 -static const uint64_t SH_FLD_SLAVE18_ERROR_CODE_LEN = 16737; // 1 -static const uint64_t SH_FLD_SLAVE18_RESPONSE_BIT = 16738; // 1 -static const uint64_t SH_FLD_SLAVE19_ERROR_CODE = 16739; // 1 -static const uint64_t SH_FLD_SLAVE19_ERROR_CODE_LEN = 16740; // 1 -static const uint64_t SH_FLD_SLAVE19_RESPONSE_BIT = 16741; // 1 -static const uint64_t SH_FLD_SLAVE1_ERROR_CODE = 16742; // 1 -static const uint64_t SH_FLD_SLAVE1_ERROR_CODE_LEN = 16743; // 1 -static const uint64_t SH_FLD_SLAVE1_RESPONSE_BIT = 16744; // 1 -static const uint64_t SH_FLD_SLAVE20_ERROR_CODE = 16745; // 1 -static const uint64_t SH_FLD_SLAVE20_ERROR_CODE_LEN = 16746; // 1 -static const uint64_t SH_FLD_SLAVE20_RESPONSE_BIT = 16747; // 1 -static const uint64_t SH_FLD_SLAVE21_ERROR_CODE = 16748; // 1 -static const uint64_t SH_FLD_SLAVE21_ERROR_CODE_LEN = 16749; // 1 -static const uint64_t SH_FLD_SLAVE21_RESPONSE_BIT = 16750; // 1 -static const uint64_t SH_FLD_SLAVE22_ERROR_CODE = 16751; // 1 -static const uint64_t SH_FLD_SLAVE22_ERROR_CODE_LEN = 16752; // 1 -static const uint64_t SH_FLD_SLAVE22_RESPONSE_BIT = 16753; // 1 -static const uint64_t SH_FLD_SLAVE23_ERROR_CODE = 16754; // 1 -static const uint64_t SH_FLD_SLAVE23_ERROR_CODE_LEN = 16755; // 1 -static const uint64_t SH_FLD_SLAVE23_RESPONSE_BIT = 16756; // 1 -static const uint64_t SH_FLD_SLAVE24_ERROR_CODE = 16757; // 1 -static const uint64_t SH_FLD_SLAVE24_ERROR_CODE_LEN = 16758; // 1 -static const uint64_t SH_FLD_SLAVE24_RESPONSE_BIT = 16759; // 1 -static const uint64_t SH_FLD_SLAVE25_ERROR_CODE = 16760; // 1 -static const uint64_t SH_FLD_SLAVE25_ERROR_CODE_LEN = 16761; // 1 -static const uint64_t SH_FLD_SLAVE25_RESPONSE_BIT = 16762; // 1 -static const uint64_t SH_FLD_SLAVE26_ERROR_CODE = 16763; // 1 -static const uint64_t SH_FLD_SLAVE26_ERROR_CODE_LEN = 16764; // 1 -static const uint64_t SH_FLD_SLAVE26_RESPONSE_BIT = 16765; // 1 -static const uint64_t SH_FLD_SLAVE27_ERROR_CODE = 16766; // 1 -static const uint64_t SH_FLD_SLAVE27_ERROR_CODE_LEN = 16767; // 1 -static const uint64_t SH_FLD_SLAVE27_RESPONSE_BIT = 16768; // 1 -static const uint64_t SH_FLD_SLAVE28_ERROR_CODE = 16769; // 1 -static const uint64_t SH_FLD_SLAVE28_ERROR_CODE_LEN = 16770; // 1 -static const uint64_t SH_FLD_SLAVE28_RESPONSE_BIT = 16771; // 1 -static const uint64_t SH_FLD_SLAVE29_ERROR_CODE = 16772; // 1 -static const uint64_t SH_FLD_SLAVE29_ERROR_CODE_LEN = 16773; // 1 -static const uint64_t SH_FLD_SLAVE29_RESPONSE_BIT = 16774; // 1 -static const uint64_t SH_FLD_SLAVE2_ERROR_CODE = 16775; // 1 -static const uint64_t SH_FLD_SLAVE2_ERROR_CODE_LEN = 16776; // 1 -static const uint64_t SH_FLD_SLAVE2_RESPONSE_BIT = 16777; // 1 -static const uint64_t SH_FLD_SLAVE30_ERROR_CODE = 16778; // 1 -static const uint64_t SH_FLD_SLAVE30_ERROR_CODE_LEN = 16779; // 1 -static const uint64_t SH_FLD_SLAVE30_RESPONSE_BIT = 16780; // 1 -static const uint64_t SH_FLD_SLAVE31_ERROR_CODE = 16781; // 1 -static const uint64_t SH_FLD_SLAVE31_ERROR_CODE_LEN = 16782; // 1 -static const uint64_t SH_FLD_SLAVE31_RESPONSE_BIT = 16783; // 1 -static const uint64_t SH_FLD_SLAVE32_ERROR_CODE = 16784; // 1 -static const uint64_t SH_FLD_SLAVE32_ERROR_CODE_LEN = 16785; // 1 -static const uint64_t SH_FLD_SLAVE32_RESPONSE_BIT = 16786; // 1 -static const uint64_t SH_FLD_SLAVE33_ERROR_CODE = 16787; // 1 -static const uint64_t SH_FLD_SLAVE33_ERROR_CODE_LEN = 16788; // 1 -static const uint64_t SH_FLD_SLAVE33_RESPONSE_BIT = 16789; // 1 -static const uint64_t SH_FLD_SLAVE34_ERROR_CODE = 16790; // 1 -static const uint64_t SH_FLD_SLAVE34_ERROR_CODE_LEN = 16791; // 1 -static const uint64_t SH_FLD_SLAVE34_RESPONSE_BIT = 16792; // 1 -static const uint64_t SH_FLD_SLAVE35_ERROR_CODE = 16793; // 1 -static const uint64_t SH_FLD_SLAVE35_ERROR_CODE_LEN = 16794; // 1 -static const uint64_t SH_FLD_SLAVE35_RESPONSE_BIT = 16795; // 1 -static const uint64_t SH_FLD_SLAVE36_ERROR_CODE = 16796; // 1 -static const uint64_t SH_FLD_SLAVE36_ERROR_CODE_LEN = 16797; // 1 -static const uint64_t SH_FLD_SLAVE36_RESPONSE_BIT = 16798; // 1 -static const uint64_t SH_FLD_SLAVE37_ERROR_CODE = 16799; // 1 -static const uint64_t SH_FLD_SLAVE37_ERROR_CODE_LEN = 16800; // 1 -static const uint64_t SH_FLD_SLAVE37_RESPONSE_BIT = 16801; // 1 -static const uint64_t SH_FLD_SLAVE38_ERROR_CODE = 16802; // 1 -static const uint64_t SH_FLD_SLAVE38_ERROR_CODE_LEN = 16803; // 1 -static const uint64_t SH_FLD_SLAVE38_RESPONSE_BIT = 16804; // 1 -static const uint64_t SH_FLD_SLAVE39_ERROR_CODE = 16805; // 1 -static const uint64_t SH_FLD_SLAVE39_ERROR_CODE_LEN = 16806; // 1 -static const uint64_t SH_FLD_SLAVE39_RESPONSE_BIT = 16807; // 1 -static const uint64_t SH_FLD_SLAVE3_ERROR_CODE = 16808; // 1 -static const uint64_t SH_FLD_SLAVE3_ERROR_CODE_LEN = 16809; // 1 -static const uint64_t SH_FLD_SLAVE3_RESPONSE_BIT = 16810; // 1 -static const uint64_t SH_FLD_SLAVE40_ERROR_CODE = 16811; // 1 -static const uint64_t SH_FLD_SLAVE40_ERROR_CODE_LEN = 16812; // 1 -static const uint64_t SH_FLD_SLAVE40_RESPONSE_BIT = 16813; // 1 -static const uint64_t SH_FLD_SLAVE41_ERROR_CODE = 16814; // 1 -static const uint64_t SH_FLD_SLAVE41_ERROR_CODE_LEN = 16815; // 1 -static const uint64_t SH_FLD_SLAVE41_RESPONSE_BIT = 16816; // 1 -static const uint64_t SH_FLD_SLAVE42_ERROR_CODE = 16817; // 1 -static const uint64_t SH_FLD_SLAVE42_ERROR_CODE_LEN = 16818; // 1 -static const uint64_t SH_FLD_SLAVE42_RESPONSE_BIT = 16819; // 1 -static const uint64_t SH_FLD_SLAVE43_ERROR_CODE = 16820; // 1 -static const uint64_t SH_FLD_SLAVE43_ERROR_CODE_LEN = 16821; // 1 -static const uint64_t SH_FLD_SLAVE43_RESPONSE_BIT = 16822; // 1 -static const uint64_t SH_FLD_SLAVE44_ERROR_CODE = 16823; // 1 -static const uint64_t SH_FLD_SLAVE44_ERROR_CODE_LEN = 16824; // 1 -static const uint64_t SH_FLD_SLAVE44_RESPONSE_BIT = 16825; // 1 -static const uint64_t SH_FLD_SLAVE45_ERROR_CODE = 16826; // 1 -static const uint64_t SH_FLD_SLAVE45_ERROR_CODE_LEN = 16827; // 1 -static const uint64_t SH_FLD_SLAVE45_RESPONSE_BIT = 16828; // 1 -static const uint64_t SH_FLD_SLAVE46_ERROR_CODE = 16829; // 1 -static const uint64_t SH_FLD_SLAVE46_ERROR_CODE_LEN = 16830; // 1 -static const uint64_t SH_FLD_SLAVE46_RESPONSE_BIT = 16831; // 1 -static const uint64_t SH_FLD_SLAVE47_ERROR_CODE = 16832; // 1 -static const uint64_t SH_FLD_SLAVE47_ERROR_CODE_LEN = 16833; // 1 -static const uint64_t SH_FLD_SLAVE47_RESPONSE_BIT = 16834; // 1 -static const uint64_t SH_FLD_SLAVE48_ERROR_CODE = 16835; // 1 -static const uint64_t SH_FLD_SLAVE48_ERROR_CODE_LEN = 16836; // 1 -static const uint64_t SH_FLD_SLAVE48_RESPONSE_BIT = 16837; // 1 -static const uint64_t SH_FLD_SLAVE49_ERROR_CODE = 16838; // 1 -static const uint64_t SH_FLD_SLAVE49_ERROR_CODE_LEN = 16839; // 1 -static const uint64_t SH_FLD_SLAVE49_RESPONSE_BIT = 16840; // 1 -static const uint64_t SH_FLD_SLAVE4_ERROR_CODE = 16841; // 1 -static const uint64_t SH_FLD_SLAVE4_ERROR_CODE_LEN = 16842; // 1 -static const uint64_t SH_FLD_SLAVE4_RESPONSE_BIT = 16843; // 1 -static const uint64_t SH_FLD_SLAVE50_ERROR_CODE = 16844; // 1 -static const uint64_t SH_FLD_SLAVE50_ERROR_CODE_LEN = 16845; // 1 -static const uint64_t SH_FLD_SLAVE50_RESPONSE_BIT = 16846; // 1 -static const uint64_t SH_FLD_SLAVE51_ERROR_CODE = 16847; // 1 -static const uint64_t SH_FLD_SLAVE51_ERROR_CODE_LEN = 16848; // 1 -static const uint64_t SH_FLD_SLAVE51_RESPONSE_BIT = 16849; // 1 -static const uint64_t SH_FLD_SLAVE52_ERROR_CODE = 16850; // 1 -static const uint64_t SH_FLD_SLAVE52_ERROR_CODE_LEN = 16851; // 1 -static const uint64_t SH_FLD_SLAVE52_RESPONSE_BIT = 16852; // 1 -static const uint64_t SH_FLD_SLAVE53_ERROR_CODE = 16853; // 1 -static const uint64_t SH_FLD_SLAVE53_ERROR_CODE_LEN = 16854; // 1 -static const uint64_t SH_FLD_SLAVE53_RESPONSE_BIT = 16855; // 1 -static const uint64_t SH_FLD_SLAVE54_ERROR_CODE = 16856; // 1 -static const uint64_t SH_FLD_SLAVE54_ERROR_CODE_LEN = 16857; // 1 -static const uint64_t SH_FLD_SLAVE54_RESPONSE_BIT = 16858; // 1 -static const uint64_t SH_FLD_SLAVE55_ERROR_CODE = 16859; // 1 -static const uint64_t SH_FLD_SLAVE55_ERROR_CODE_LEN = 16860; // 1 -static const uint64_t SH_FLD_SLAVE55_RESPONSE_BIT = 16861; // 1 -static const uint64_t SH_FLD_SLAVE56_ERROR_CODE = 16862; // 1 -static const uint64_t SH_FLD_SLAVE56_ERROR_CODE_LEN = 16863; // 1 -static const uint64_t SH_FLD_SLAVE56_RESPONSE_BIT = 16864; // 1 -static const uint64_t SH_FLD_SLAVE57_ERROR_CODE = 16865; // 1 -static const uint64_t SH_FLD_SLAVE57_ERROR_CODE_LEN = 16866; // 1 -static const uint64_t SH_FLD_SLAVE57_RESPONSE_BIT = 16867; // 1 -static const uint64_t SH_FLD_SLAVE58_ERROR_CODE = 16868; // 1 -static const uint64_t SH_FLD_SLAVE58_ERROR_CODE_LEN = 16869; // 1 -static const uint64_t SH_FLD_SLAVE58_RESPONSE_BIT = 16870; // 1 -static const uint64_t SH_FLD_SLAVE59_ERROR_CODE = 16871; // 1 -static const uint64_t SH_FLD_SLAVE59_ERROR_CODE_LEN = 16872; // 1 -static const uint64_t SH_FLD_SLAVE59_RESPONSE_BIT = 16873; // 1 -static const uint64_t SH_FLD_SLAVE5_ERROR_CODE = 16874; // 1 -static const uint64_t SH_FLD_SLAVE5_ERROR_CODE_LEN = 16875; // 1 -static const uint64_t SH_FLD_SLAVE5_RESPONSE_BIT = 16876; // 1 -static const uint64_t SH_FLD_SLAVE60_ERROR_CODE = 16877; // 1 -static const uint64_t SH_FLD_SLAVE60_ERROR_CODE_LEN = 16878; // 1 -static const uint64_t SH_FLD_SLAVE60_RESPONSE_BIT = 16879; // 1 -static const uint64_t SH_FLD_SLAVE61_ERROR_CODE = 16880; // 1 -static const uint64_t SH_FLD_SLAVE61_ERROR_CODE_LEN = 16881; // 1 -static const uint64_t SH_FLD_SLAVE61_RESPONSE_BIT = 16882; // 1 -static const uint64_t SH_FLD_SLAVE62_ERROR_CODE = 16883; // 1 -static const uint64_t SH_FLD_SLAVE62_ERROR_CODE_LEN = 16884; // 1 -static const uint64_t SH_FLD_SLAVE62_RESPONSE_BIT = 16885; // 1 -static const uint64_t SH_FLD_SLAVE63_ERROR_CODE = 16886; // 1 -static const uint64_t SH_FLD_SLAVE63_ERROR_CODE_LEN = 16887; // 1 -static const uint64_t SH_FLD_SLAVE63_RESPONSE_BIT = 16888; // 1 -static const uint64_t SH_FLD_SLAVE6_ERROR_CODE = 16889; // 1 -static const uint64_t SH_FLD_SLAVE6_ERROR_CODE_LEN = 16890; // 1 -static const uint64_t SH_FLD_SLAVE6_RESPONSE_BIT = 16891; // 1 -static const uint64_t SH_FLD_SLAVE7_ERROR_CODE = 16892; // 1 -static const uint64_t SH_FLD_SLAVE7_ERROR_CODE_LEN = 16893; // 1 -static const uint64_t SH_FLD_SLAVE7_RESPONSE_BIT = 16894; // 1 -static const uint64_t SH_FLD_SLAVE8_ERROR_CODE = 16895; // 1 -static const uint64_t SH_FLD_SLAVE8_ERROR_CODE_LEN = 16896; // 1 -static const uint64_t SH_FLD_SLAVE8_RESPONSE_BIT = 16897; // 1 -static const uint64_t SH_FLD_SLAVE9_ERROR_CODE = 16898; // 1 -static const uint64_t SH_FLD_SLAVE9_ERROR_CODE_LEN = 16899; // 1 -static const uint64_t SH_FLD_SLAVE9_RESPONSE_BIT = 16900; // 1 -static const uint64_t SH_FLD_SLAVE_IDLE = 16901; // 1 -static const uint64_t SH_FLD_SLAVE_MODE = 16902; // 43 -static const uint64_t SH_FLD_SLAVE_RESET_TO_405_ENABLE = 16903; // 1 -static const uint64_t SH_FLD_SLBI_GROUP_PUMP_EN = 16904; // 12 -static const uint64_t SH_FLD_SLB_BUS0_STG1_SEL = 16905; // 1 -static const uint64_t SH_FLD_SLB_BUS0_STG2_SEL = 16906; // 1 -static const uint64_t SH_FLD_SLB_BUS1_STG1_SEL = 16907; // 1 -static const uint64_t SH_FLD_SLB_BUS1_STG2_SEL = 16908; // 1 -static const uint64_t SH_FLD_SLB_CAC_PERR_DET = 16909; // 1 -static const uint64_t SH_FLD_SLB_DIR_PERR_DET = 16910; // 1 -static const uint64_t SH_FLD_SLB_LRU_PERR_DET = 16911; // 1 -static const uint64_t SH_FLD_SLB_MULTIHIT_DET = 16912; // 1 -static const uint64_t SH_FLD_SLEWCTL = 16913; // 1 -static const uint64_t SH_FLD_SLEWCTL_LEN = 16914; // 1 -static const uint64_t SH_FLD_SLEW_DN_SEL = 16915; // 6 -static const uint64_t SH_FLD_SLICE = 16916; // 3 -static const uint64_t SH_FLD_SLICE0_CFG_ECC_CE_ERR = 16917; // 2 -static const uint64_t SH_FLD_SLICE0_CFG_ECC_UE_ERR = 16918; // 2 -static const uint64_t SH_FLD_SLICE1_CFG_ECC_CE_ERR = 16919; // 2 -static const uint64_t SH_FLD_SLICE1_CFG_ECC_UE_ERR = 16920; // 2 -static const uint64_t SH_FLD_SLICE2_CFG_ECC_CE_ERR = 16921; // 2 -static const uint64_t SH_FLD_SLICE2_CFG_ECC_UE_ERR = 16922; // 2 -static const uint64_t SH_FLD_SLICE3_CFG_ECC_CE_ERR = 16923; // 2 -static const uint64_t SH_FLD_SLICE3_CFG_ECC_UE_ERR = 16924; // 2 -static const uint64_t SH_FLD_SLICE_LEN = 16925; // 3 -static const uint64_t SH_FLD_SLOT0_B2_VALID = 16926; // 8 -static const uint64_t SH_FLD_SLOT0_D_VALUE = 16927; // 8 -static const uint64_t SH_FLD_SLOT0_M0_VALID = 16928; // 8 -static const uint64_t SH_FLD_SLOT0_M1_VALID = 16929; // 8 -static const uint64_t SH_FLD_SLOT0_ROW15_VALID = 16930; // 8 -static const uint64_t SH_FLD_SLOT0_ROW16_VALID = 16931; // 8 -static const uint64_t SH_FLD_SLOT0_ROW17_VALID = 16932; // 8 -static const uint64_t SH_FLD_SLOT0_S0_VALID = 16933; // 8 -static const uint64_t SH_FLD_SLOT0_S1_VALID = 16934; // 8 -static const uint64_t SH_FLD_SLOT0_S2_VALID = 16935; // 8 -static const uint64_t SH_FLD_SLOT0_VALID = 16936; // 8 -static const uint64_t SH_FLD_SLOT1_B2_VALID = 16937; // 8 -static const uint64_t SH_FLD_SLOT1_D_VALUE = 16938; // 8 -static const uint64_t SH_FLD_SLOT1_M0_VALID = 16939; // 8 -static const uint64_t SH_FLD_SLOT1_M1_VALID = 16940; // 8 -static const uint64_t SH_FLD_SLOT1_ROW15_VALID = 16941; // 8 -static const uint64_t SH_FLD_SLOT1_ROW16_VALID = 16942; // 8 -static const uint64_t SH_FLD_SLOT1_ROW17_VALID = 16943; // 8 -static const uint64_t SH_FLD_SLOT1_S0_VALID = 16944; // 8 -static const uint64_t SH_FLD_SLOT1_S1_VALID = 16945; // 8 -static const uint64_t SH_FLD_SLOT1_S2_VALID = 16946; // 8 -static const uint64_t SH_FLD_SLOT1_VALID = 16947; // 8 -static const uint64_t SH_FLD_SLOW_CMD_RATE = 16948; // 1 -static const uint64_t SH_FLD_SLOW_TO_MODE = 16949; // 86 -static const uint64_t SH_FLD_SLS_CMD_GCRMSG = 16950; // 4 -static const uint64_t SH_FLD_SLS_CMD_GCRMSG_LEN = 16951; // 4 -static const uint64_t SH_FLD_SLS_CNTR_TAP_PTS = 16952; // 4 -static const uint64_t SH_FLD_SLS_CNTR_TAP_PTS_LEN = 16953; // 4 -static const uint64_t SH_FLD_SLS_DISABLE = 16954; // 4 -static const uint64_t SH_FLD_SLS_EXCEPTION2_CS = 16955; // 4 -static const uint64_t SH_FLD_SLS_EXTEND_SEL = 16956; // 4 -static const uint64_t SH_FLD_SLS_EXTEND_SEL_LEN = 16957; // 4 -static const uint64_t SH_FLD_SLS_LANE_GCRMSG = 16958; // 4 -static const uint64_t SH_FLD_SLS_LANE_GCRMSG_LEN = 16959; // 4 -static const uint64_t SH_FLD_SLS_LANE_SEL_LG_GCRMSG = 16960; // 4 -static const uint64_t SH_FLD_SLS_LANE_SHDW_GCRMSG = 16961; // 4 -static const uint64_t SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG = 16962; // 4 -static const uint64_t SH_FLD_SLS_LANE_VAL_GCRMSG = 16963; // 4 -static const uint64_t SH_FLD_SLS_RCVY_DISABLE = 16964; // 4 -static const uint64_t SH_FLD_SLS_SCRAMBLE_MODE = 16965; // 4 -static const uint64_t SH_FLD_SLS_SCRAMBLE_MODE_LEN = 16966; // 4 -static const uint64_t SH_FLD_SLS_TIMEOUT_SEL = 16967; // 4 -static const uint64_t SH_FLD_SLS_TIMEOUT_SEL_LEN = 16968; // 4 -static const uint64_t SH_FLD_SLV_DIS_ABUSPAR = 16969; // 1 -static const uint64_t SH_FLD_SLV_DIS_BE = 16970; // 1 -static const uint64_t SH_FLD_SLV_DIS_BEPAR = 16971; // 1 -static const uint64_t SH_FLD_SLV_DIS_RDDBUSPAREN = 16972; // 1 -static const uint64_t SH_FLD_SLV_DIS_SACK = 16973; // 1 -static const uint64_t SH_FLD_SLV_DIS_WRDBUSPAR = 16974; // 1 -static const uint64_t SH_FLD_SLV_EVENT_MUX = 16975; // 1 -static const uint64_t SH_FLD_SLV_EVENT_MUX_LEN = 16976; // 1 -static const uint64_t SH_FLD_SLV_LGL_RPR_REQ_GCRMSG = 16977; // 4 -static const uint64_t SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG = 16978; // 4 -static const uint64_t SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG = 16979; // 4 -static const uint64_t SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 16980; // 4 -static const uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 16981; // 4 -static const uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 16982; // 4 -static const uint64_t SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG = 16983; // 4 -static const uint64_t SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG = 16984; // 4 -static const uint64_t SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG = 16985; // 4 -static const uint64_t SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG = 16986; // 4 -static const uint64_t SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG = 16987; // 4 -static const uint64_t SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG = 16988; // 4 -static const uint64_t SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG = 16989; // 4 -static const uint64_t SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG = 16990; // 4 -static const uint64_t SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG = 16991; // 4 -static const uint64_t SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG = 16992; // 4 -static const uint64_t SH_FLD_SLV_SPARE = 16993; // 1 -static const uint64_t SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG = 16994; // 4 -static const uint64_t SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG = 16995; // 4 -static const uint64_t SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG = 16996; // 4 -static const uint64_t SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG = 16997; // 4 -static const uint64_t SH_FLD_SL_UE_CRC_ERR = 16998; // 5 -static const uint64_t SH_FLD_SMALL_EVENT_PROFILE_CTR = 16999; // 12 -static const uint64_t SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN = 17000; // 12 -static const uint64_t SH_FLD_SMALL_EVENT_THRESHOLD = 17001; // 12 -static const uint64_t SH_FLD_SMALL_EVENT_THRESHOLD_LEN = 17002; // 12 -static const uint64_t SH_FLD_SMALL_STEP = 17003; // 8 -static const uint64_t SH_FLD_SMALL_STEP_LEN = 17004; // 8 -static const uint64_t SH_FLD_SMASK_IN0 = 17005; // 43 -static const uint64_t SH_FLD_SMASK_IN1 = 17006; // 43 -static const uint64_t SH_FLD_SMASK_IN2 = 17007; // 43 -static const uint64_t SH_FLD_SMASK_IN3 = 17008; // 43 -static const uint64_t SH_FLD_SMASK_IN4 = 17009; // 43 -static const uint64_t SH_FLD_SM_1HOT_ERR = 17010; // 16 -static const uint64_t SH_FLD_SM_MMIO0 = 17011; // 3 -static const uint64_t SH_FLD_SM_MMIO1 = 17012; // 3 -static const uint64_t SH_FLD_SM_MMIO2 = 17013; // 3 -static const uint64_t SH_FLD_SM_MMIO3 = 17014; // 3 -static const uint64_t SH_FLD_SM_OR_CASE = 17015; // 2 -static const uint64_t SH_FLD_SM_RESET = 17016; // 1 -static const uint64_t SH_FLD_SN0_CRESP_ATAG_P = 17017; // 12 -static const uint64_t SH_FLD_SN0_CRESP_TTAG_P = 17018; // 12 -static const uint64_t SH_FLD_SN0_RCMD_ADDR_P = 17019; // 12 -static const uint64_t SH_FLD_SN0_RCMD_TTAG_P = 17020; // 12 -static const uint64_t SH_FLD_SN1_CRESP_ATAG_P = 17021; // 12 -static const uint64_t SH_FLD_SN1_CRESP_TTAG_P = 17022; // 12 -static const uint64_t SH_FLD_SN1_RCMD_ADDR_P = 17023; // 12 -static const uint64_t SH_FLD_SN1_RCMD_TTAG_P = 17024; // 12 -static const uint64_t SH_FLD_SN2_CRESP_ATAG_P = 17025; // 12 -static const uint64_t SH_FLD_SN2_CRESP_TTAG_P = 17026; // 12 -static const uint64_t SH_FLD_SN2_RCMD_ADDR_P = 17027; // 12 -static const uint64_t SH_FLD_SN2_RCMD_TTAG_P = 17028; // 12 -static const uint64_t SH_FLD_SN3_CRESP_ATAG_P = 17029; // 12 -static const uint64_t SH_FLD_SN3_CRESP_TTAG_P = 17030; // 12 -static const uint64_t SH_FLD_SN3_RCMD_ADDR_P = 17031; // 12 -static const uint64_t SH_FLD_SN3_RCMD_TTAG_P = 17032; // 12 -static const uint64_t SH_FLD_SND_CHIPID = 17033; // 1 -static const uint64_t SH_FLD_SND_CHIPID_LEN = 17034; // 1 -static const uint64_t SH_FLD_SND_CNT = 17035; // 1 -static const uint64_t SH_FLD_SND_CNT_LEN = 17036; // 1 -static const uint64_t SH_FLD_SND_CNT_STATUS = 17037; // 1 -static const uint64_t SH_FLD_SND_CNT_STATUS_LEN = 17038; // 1 -static const uint64_t SH_FLD_SND_ERROR = 17039; // 1 -static const uint64_t SH_FLD_SND_GROUPID = 17040; // 1 -static const uint64_t SH_FLD_SND_GROUPID_LEN = 17041; // 1 -static const uint64_t SH_FLD_SND_IN_PROGRESS = 17042; // 1 -static const uint64_t SH_FLD_SND_PHASE_STATUS = 17043; // 1 -static const uint64_t SH_FLD_SND_PHASE_STATUS_LEN = 17044; // 1 -static const uint64_t SH_FLD_SND_QID = 17045; // 1 -static const uint64_t SH_FLD_SND_RESERVATION = 17046; // 1 -static const uint64_t SH_FLD_SND_RESET = 17047; // 1 -static const uint64_t SH_FLD_SND_RETRY_COUNT = 17048; // 1 -static const uint64_t SH_FLD_SND_RETRY_COUNT_LEN = 17049; // 1 -static const uint64_t SH_FLD_SND_RETRY_COUNT_OVERCOM = 17050; // 1 -static const uint64_t SH_FLD_SND_RETRY_THRESH = 17051; // 1 -static const uint64_t SH_FLD_SND_RETRY_THRESH_LEN = 17052; // 1 -static const uint64_t SH_FLD_SND_RSVTO_DIV = 17053; // 1 -static const uint64_t SH_FLD_SND_RSVTO_DIV_LEN = 17054; // 1 -static const uint64_t SH_FLD_SND_SCOPE = 17055; // 1 -static const uint64_t SH_FLD_SND_SCOPE_LEN = 17056; // 1 -static const uint64_t SH_FLD_SND_SLS_CMD_GCRMSG = 17057; // 4 -static const uint64_t SH_FLD_SND_SLS_CMD_PREV_GCRMSG = 17058; // 4 -static const uint64_t SH_FLD_SND_SLS_USING_REG_SCRAMBLE = 17059; // 4 -static const uint64_t SH_FLD_SND_STOP = 17060; // 1 -static const uint64_t SH_FLD_SND_TYPE = 17061; // 1 -static const uint64_t SH_FLD_SNFSM_ADDR = 17062; // 12 -static const uint64_t SH_FLD_SNGL_THD_EN = 17063; // 2 -static const uint64_t SH_FLD_SNOOPER_RECOVERABLE_ERROR = 17064; // 4 -static const uint64_t SH_FLD_SNOOPER_SYS_XSTOP_ERROR = 17065; // 4 -static const uint64_t SH_FLD_SNOOP_ARRAY_CE = 17066; // 4 -static const uint64_t SH_FLD_SNOOP_ARRAY_UE = 17067; // 4 -static const uint64_t SH_FLD_SNOOP_DIS = 17068; // 8 -static const uint64_t SH_FLD_SNOP = 17069; // 43 -static const uint64_t SH_FLD_SNOP_FORCE_SG = 17070; // 43 -static const uint64_t SH_FLD_SNOP_LEN = 17071; // 43 -static const uint64_t SH_FLD_SNOP_WAIT = 17072; // 43 -static const uint64_t SH_FLD_SNOP_WAIT_LEN = 17073; // 43 -static const uint64_t SH_FLD_SNPBE_TRIGGER_ENABLE = 17074; // 2 -static const uint64_t SH_FLD_SNPBE_UOP_TRIGGER_ENABLE = 17075; // 2 -static const uint64_t SH_FLD_SNPFE_DIR_TRIGGER_ENABLE = 17076; // 2 -static const uint64_t SH_FLD_SNPFE_TRIGGER_ENABLE = 17077; // 2 -static const uint64_t SH_FLD_SNP_ERROR_INJECT_ENABLE = 17078; // 2 -static const uint64_t SH_FLD_SNP_ERROR_INJECT_TARGET = 17079; // 2 -static const uint64_t SH_FLD_SNP_ERROR_INJECT_TARGET_LEN = 17080; // 2 -static const uint64_t SH_FLD_SNP_INJECT_CONTINOUS_ERROR = 17081; // 2 -static const uint64_t SH_FLD_SNP_INJECT_DBL_ECC_ERROR = 17082; // 2 -static const uint64_t SH_FLD_SNP_MUX_PORT_SEL = 17083; // 2 -static const uint64_t SH_FLD_SNP_MUX_PORT_SEL_LEN = 17084; // 2 -static const uint64_t SH_FLD_SNP_REG_ERR0 = 17085; // 1 -static const uint64_t SH_FLD_SNP_REG_ERR1 = 17086; // 1 -static const uint64_t SH_FLD_SNP_REG_ERR2 = 17087; // 1 -static const uint64_t SH_FLD_SNP_REG_ERR3 = 17088; // 1 -static const uint64_t SH_FLD_SNP_REG_ERR4 = 17089; // 1 -static const uint64_t SH_FLD_SNP_REG_ERR5 = 17090; // 1 -static const uint64_t SH_FLD_SNP_REG_ERR6 = 17091; // 1 -static const uint64_t SH_FLD_SNS1_UNUSED_0_31 = 17092; // 1 -static const uint64_t SH_FLD_SNS1_UNUSED_0_31_LEN = 17093; // 1 -static const uint64_t SH_FLD_SNS2_UNUSED_0_31 = 17094; // 1 -static const uint64_t SH_FLD_SNS2_UNUSED_0_31_LEN = 17095; // 1 -static const uint64_t SH_FLD_SN_CRESP_ACK_DEAD = 17096; // 12 -static const uint64_t SH_FLD_SN_MACHINE_HANG = 17097; // 12 -static const uint64_t SH_FLD_SN_MSG_MAX_CREDIT = 17098; // 2 -static const uint64_t SH_FLD_SN_MSG_MAX_CREDIT_LEN = 17099; // 2 -static const uint64_t SH_FLD_SN_SC_RDATA_PARITY_ERRHOLD = 17100; // 2 -static const uint64_t SH_FLD_SN_UNSOLICITED_CRESP = 17101; // 12 -static const uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT = 17102; // 2 -static const uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN = 17103; // 2 -static const uint64_t SH_FLD_SOCKET = 17104; // 1 -static const uint64_t SH_FLD_SOCKET_LEN = 17105; // 1 -static const uint64_t SH_FLD_SOFT_CE_COUNT = 17106; // 2 -static const uint64_t SH_FLD_SOFT_CE_COUNT_LEN = 17107; // 2 -static const uint64_t SH_FLD_SOFT_MCE_COUNT = 17108; // 2 -static const uint64_t SH_FLD_SOFT_MCE_COUNT_LEN = 17109; // 2 -static const uint64_t SH_FLD_SOFT_NCE_ETE_ATTN = 17110; // 2 -static const uint64_t SH_FLD_SOURCE_SELECT = 17111; // 43 -static const uint64_t SH_FLD_SOURCE_SELECT_LEN = 17112; // 43 -static const uint64_t SH_FLD_SOURCE_SUBUNIT_0_1 = 17113; // 1 -static const uint64_t SH_FLD_SOURCE_SUBUNIT_0_1_LEN = 17114; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_CQ_IDLE_BIT = 17115; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_ECC = 17116; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB = 17117; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR = 17118; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_EG_IDLE_BIT = 17119; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD = 17120; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG = 17121; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 17122; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER = 17123; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_EN_FAST_SCRUB = 17124; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_UNUSED = 17125; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_UNUSED_LEN = 17126; // 1 -static const uint64_t SH_FLD_SOUTH_CTL_WC_IDLE_BIT = 17127; // 1 -static const uint64_t SH_FLD_SPARE = 17128; // 87 -static const uint64_t SH_FLD_SPARE0 = 17129; // 105 -static const uint64_t SH_FLD_SPARE0_LEN = 17130; // 8 -static const uint64_t SH_FLD_SPARE1 = 17131; // 5 -static const uint64_t SH_FLD_SPARE10 = 17132; // 1 -static const uint64_t SH_FLD_SPARE11 = 17133; // 14 -static const uint64_t SH_FLD_SPARE13 = 17134; // 1 -static const uint64_t SH_FLD_SPARE14 = 17135; // 1 -static const uint64_t SH_FLD_SPARE15 = 17136; // 1 -static const uint64_t SH_FLD_SPARE2 = 17137; // 4 -static const uint64_t SH_FLD_SPARE3 = 17138; // 1 -static const uint64_t SH_FLD_SPARE41_43 = 17139; // 24 -static const uint64_t SH_FLD_SPARE41_43_LEN = 17140; // 24 -static const uint64_t SH_FLD_SPARE4_TIMEOUT = 17141; // 6 -static const uint64_t SH_FLD_SPARE4_TIMEOUT_LEN = 17142; // 6 -static const uint64_t SH_FLD_SPARE7 = 17143; // 1 -static const uint64_t SH_FLD_SPARE8 = 17144; // 1 -static const uint64_t SH_FLD_SPARE9 = 17145; // 1 -static const uint64_t SH_FLD_SPARED = 17146; // 4 -static const uint64_t SH_FLD_SPARED_LEN = 17147; // 4 -static const uint64_t SH_FLD_SPARES = 17148; // 3 -static const uint64_t SH_FLD_SPARES1 = 17149; // 4 -static const uint64_t SH_FLD_SPARES1_LEN = 17150; // 4 -static const uint64_t SH_FLD_SPARES2 = 17151; // 4 -static const uint64_t SH_FLD_SPARES2_LEN = 17152; // 4 -static const uint64_t SH_FLD_SPARES_LEN = 17153; // 3 -static const uint64_t SH_FLD_SPARE_0 = 17154; // 4 -static const uint64_t SH_FLD_SPARE_0_LEN = 17155; // 4 -static const uint64_t SH_FLD_SPARE_10 = 17156; // 2 -static const uint64_t SH_FLD_SPARE_11 = 17157; // 5 -static const uint64_t SH_FLD_SPARE_12 = 17158; // 4 -static const uint64_t SH_FLD_SPARE_13 = 17159; // 4 -static const uint64_t SH_FLD_SPARE_14 = 17160; // 4 -static const uint64_t SH_FLD_SPARE_15 = 17161; // 16 -static const uint64_t SH_FLD_SPARE_16 = 17162; // 14 -static const uint64_t SH_FLD_SPARE_17 = 17163; // 14 -static const uint64_t SH_FLD_SPARE_18 = 17164; // 2 -static const uint64_t SH_FLD_SPARE_18_19 = 17165; // 6 -static const uint64_t SH_FLD_SPARE_18_19_LEN = 17166; // 6 -static const uint64_t SH_FLD_SPARE_19 = 17167; // 4 -static const uint64_t SH_FLD_SPARE_1_3 = 17168; // 1 -static const uint64_t SH_FLD_SPARE_1_3_LEN = 17169; // 1 -static const uint64_t SH_FLD_SPARE_2 = 17170; // 4 -static const uint64_t SH_FLD_SPARE_20 = 17171; // 4 -static const uint64_t SH_FLD_SPARE_21 = 17172; // 4 -static const uint64_t SH_FLD_SPARE_22 = 17173; // 4 -static const uint64_t SH_FLD_SPARE_22_23 = 17174; // 12 -static const uint64_t SH_FLD_SPARE_22_23_LEN = 17175; // 12 -static const uint64_t SH_FLD_SPARE_23 = 17176; // 4 -static const uint64_t SH_FLD_SPARE_24 = 17177; // 4 -static const uint64_t SH_FLD_SPARE_24_31 = 17178; // 1 -static const uint64_t SH_FLD_SPARE_24_31_LEN = 17179; // 1 -static const uint64_t SH_FLD_SPARE_25 = 17180; // 4 -static const uint64_t SH_FLD_SPARE_26 = 17181; // 4 -static const uint64_t SH_FLD_SPARE_27 = 17182; // 4 -static const uint64_t SH_FLD_SPARE_28 = 17183; // 4 -static const uint64_t SH_FLD_SPARE_29 = 17184; // 4 -static const uint64_t SH_FLD_SPARE_2_MASK = 17185; // 1 -static const uint64_t SH_FLD_SPARE_3 = 17186; // 6 -static const uint64_t SH_FLD_SPARE_30 = 17187; // 4 -static const uint64_t SH_FLD_SPARE_31 = 17188; // 5 -static const uint64_t SH_FLD_SPARE_32_33 = 17189; // 12 -static const uint64_t SH_FLD_SPARE_32_33_LEN = 17190; // 12 -static const uint64_t SH_FLD_SPARE_3_MASK = 17191; // 1 -static const uint64_t SH_FLD_SPARE_58 = 17192; // 4 -static const uint64_t SH_FLD_SPARE_59 = 17193; // 4 -static const uint64_t SH_FLD_SPARE_59_61 = 17194; // 2 -static const uint64_t SH_FLD_SPARE_59_61_LEN = 17195; // 2 -static const uint64_t SH_FLD_SPARE_60 = 17196; // 4 -static const uint64_t SH_FLD_SPARE_61 = 17197; // 4 -static const uint64_t SH_FLD_SPARE_63 = 17198; // 3 -static const uint64_t SH_FLD_SPARE_6_7 = 17199; // 16 -static const uint64_t SH_FLD_SPARE_6_7_LEN = 17200; // 16 -static const uint64_t SH_FLD_SPARE_8 = 17201; // 2 -static const uint64_t SH_FLD_SPARE_8_11 = 17202; // 6 -static const uint64_t SH_FLD_SPARE_8_11_LEN = 17203; // 6 -static const uint64_t SH_FLD_SPARE_9 = 17204; // 2 -static const uint64_t SH_FLD_SPARE_DI_CONTROL = 17205; // 3 -static const uint64_t SH_FLD_SPARE_ERR_38 = 17206; // 1 -static const uint64_t SH_FLD_SPARE_ERR_38_MASK = 17207; // 1 -static const uint64_t SH_FLD_SPARE_FENCE_CONTROL = 17208; // 3 -static const uint64_t SH_FLD_SPARE_FILT0_PLL = 17209; // 3 -static const uint64_t SH_FLD_SPARE_FILT1_PLL = 17210; // 3 -static const uint64_t SH_FLD_SPARE_LEN = 17211; // 57 -static const uint64_t SH_FLD_SPARE_MODE_0 = 17212; // 116 -static const uint64_t SH_FLD_SPARE_MODE_1 = 17213; // 116 -static const uint64_t SH_FLD_SPARE_MODE_2 = 17214; // 116 -static const uint64_t SH_FLD_SPARE_MODE_3 = 17215; // 116 -static const uint64_t SH_FLD_SPARE_N = 17216; // 2 -static const uint64_t SH_FLD_SPARE_N_LEN = 17217; // 2 -static const uint64_t SH_FLD_SPARE_PIB_CONTROL = 17218; // 3 -static const uint64_t SH_FLD_SPARE_RI_CONTROL = 17219; // 3 -static const uint64_t SH_FLD_SPECIAL_ATTENTION = 17220; // 1 -static const uint64_t SH_FLD_SPECIAL_WAKEUP_C0 = 17221; // 24 -static const uint64_t SH_FLD_SPECIAL_WAKEUP_C1 = 17222; // 24 -static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 17223; // 12 -static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17224; // 12 -static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE = 17225; // 12 -static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_C0 = 17226; // 12 -static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_C1 = 17227; // 12 -static const uint64_t SH_FLD_SPECIAL_WKUP_PROTOCOL = 17228; // 30 -static const uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT = 17229; // 1 -static const uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN = 17230; // 1 -static const uint64_t SH_FLD_SPEC_CILD_G = 17231; // 1 -static const uint64_t SH_FLD_SPEC_HPC_DIR_STATE = 17232; // 2 -static const uint64_t SH_FLD_SPEC_HPC_DIR_STATE_LEN = 17233; // 2 -static const uint64_t SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE = 17234; // 4 -static const uint64_t SH_FLD_SPEDIV = 17235; // 20 -static const uint64_t SH_FLD_SPEDIV_LEN = 17236; // 20 -static const uint64_t SH_FLD_SPEED_SELECT = 17237; // 2 -static const uint64_t SH_FLD_SPEED_SELECT_LEN = 17238; // 2 -static const uint64_t SH_FLD_SPLURGE = 17239; // 1 -static const uint64_t SH_FLD_SPRG0 = 17240; // 21 -static const uint64_t SH_FLD_SPRG0_LEN = 17241; // 21 -static const uint64_t SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG = 17242; // 4 -static const uint64_t SH_FLD_SP_COUNT_LT = 17243; // 86 -static const uint64_t SH_FLD_SP_COUNT_LT_LEN = 17244; // 86 -static const uint64_t SH_FLD_SQ_LFSR_CNTL = 17245; // 8 -static const uint64_t SH_FLD_SQ_LFSR_CNTL_LEN = 17246; // 8 -static const uint64_t SH_FLD_SR = 17247; // 8 -static const uint64_t SH_FLD_SRAM_ABIST_DONE_DC = 17248; // 43 -static const uint64_t SH_FLD_SRAM_ACCESS_MODE = 17249; // 16 -static const uint64_t SH_FLD_SRAM_ADDRESS = 17250; // 16 -static const uint64_t SH_FLD_SRAM_ADDRESS_LEN = 17251; // 16 -static const uint64_t SH_FLD_SRAM_CE = 17252; // 13 -static const uint64_t SH_FLD_SRAM_CERRRPT = 17253; // 1 -static const uint64_t SH_FLD_SRAM_CERRRPT_LEN = 17254; // 1 -static const uint64_t SH_FLD_SRAM_DATA = 17255; // 16 -static const uint64_t SH_FLD_SRAM_DATA_LEN = 17256; // 16 -static const uint64_t SH_FLD_SRAM_HIGH_PRIORITY = 17257; // 4 -static const uint64_t SH_FLD_SRAM_HIGH_PRIORITY_LEN = 17258; // 4 -static const uint64_t SH_FLD_SRAM_LOW_PRIORITY = 17259; // 4 -static const uint64_t SH_FLD_SRAM_LOW_PRIORITY_LEN = 17260; // 4 -static const uint64_t SH_FLD_SRAM_SCRUB_ENABLE = 17261; // 16 -static const uint64_t SH_FLD_SRAM_SCRUB_ERR = 17262; // 13 -static const uint64_t SH_FLD_SRAM_SCRUB_INDEX = 17263; // 16 -static const uint64_t SH_FLD_SRAM_SCRUB_INDEX_LEN = 17264; // 16 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0 = 17265; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0_MASK = 17266; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1 = 17267; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1_MASK = 17268; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2 = 17269; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2_MASK = 17270; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3 = 17271; // 1 -static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3_MASK = 17272; // 1 -static const uint64_t SH_FLD_SRAM_UE = 17273; // 13 -static const uint64_t SH_FLD_SRC_BUS = 17274; // 24 -static const uint64_t SH_FLD_SRC_BUS_LEN = 17275; // 24 -static const uint64_t SH_FLD_SRC_DDE = 17276; // 3 -static const uint64_t SH_FLD_SRC_DDE_LEN = 17277; // 3 -static const uint64_t SH_FLD_SRC_SEL_EQ1_ERR = 17278; // 1 -static const uint64_t SH_FLD_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT = 17279; // 2 -static const uint64_t SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 17280; // 2 -static const uint64_t SH_FLD_SRT_CE = 17281; // 1 -static const uint64_t SH_FLD_SRT_CE_MASK = 17282; // 1 -static const uint64_t SH_FLD_SRT_DATAOUT_PERR = 17283; // 1 -static const uint64_t SH_FLD_SRT_DATAOUT_PERR_MASK = 17284; // 1 -static const uint64_t SH_FLD_SRT_ERROR = 17285; // 1 -static const uint64_t SH_FLD_SRT_FSM_ERR = 17286; // 1 -static const uint64_t SH_FLD_SRT_FSM_ERR_MASK = 17287; // 1 -static const uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR = 17288; // 1 -static const uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR_MASK = 17289; // 1 -static const uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR = 17290; // 1 -static const uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR_MASK = 17291; // 1 -static const uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY = 17292; // 1 -static const uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY_MASK = 17293; // 1 -static const uint64_t SH_FLD_SRT_READ_ERROR = 17294; // 1 -static const uint64_t SH_FLD_SRT_READ_ERROR_MASK = 17295; // 1 -static const uint64_t SH_FLD_SRT_UE = 17296; // 1 -static const uint64_t SH_FLD_SRT_UE_MASK = 17297; // 1 -static const uint64_t SH_FLD_SRT_WRITE_ERROR = 17298; // 1 -static const uint64_t SH_FLD_SRT_WRITE_ERROR_MASK = 17299; // 1 -static const uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL = 17300; // 4 -static const uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN = 17301; // 4 -static const uint64_t SH_FLD_SR_LEN = 17302; // 8 -static const uint64_t SH_FLD_SSA_ECC_HI_CE_ERRHOLD = 17303; // 2 -static const uint64_t SH_FLD_SSA_ECC_HI_SUE_ERRHOLD = 17304; // 2 -static const uint64_t SH_FLD_SSA_ECC_HI_UE_ERRHOLD = 17305; // 2 -static const uint64_t SH_FLD_SSA_ECC_LO_CE_ERRHOLD = 17306; // 2 -static const uint64_t SH_FLD_SSA_ECC_LO_SUE_ERRHOLD = 17307; // 2 -static const uint64_t SH_FLD_SSA_ECC_LO_UE_ERRHOLD = 17308; // 2 -static const uint64_t SH_FLD_SSCGEN = 17309; // 3 -static const uint64_t SH_FLD_SS_ENABLE = 17310; // 6 -static const uint64_t SH_FLD_ST2_RESET_PERIOD = 17311; // 1 -static const uint64_t SH_FLD_ST2_RESET_PERIOD_LEN = 17312; // 1 -static const uint64_t SH_FLD_STACK = 17313; // 16 -static const uint64_t SH_FLD_STACK_LEN = 17314; // 16 -static const uint64_t SH_FLD_STAGGERED_PATTERN = 17315; // 8 -static const uint64_t SH_FLD_START = 17316; // 59 -static const uint64_t SH_FLD_START0 = 17317; // 5 -static const uint64_t SH_FLD_START1 = 17318; // 5 -static const uint64_t SH_FLD_STARTING_ADDRESS = 17319; // 4 -static const uint64_t SH_FLD_STARTING_ADDRESS_LEN = 17320; // 4 -static const uint64_t SH_FLD_STARTS_BIST = 17321; // 43 -static const uint64_t SH_FLD_START_BOOT_SEQUENCER = 17322; // 1 -static const uint64_t SH_FLD_START_DC_CALIBRATE = 17323; // 4 -static const uint64_t SH_FLD_START_DESKEW = 17324; // 4 -static const uint64_t SH_FLD_START_EYE_OPT = 17325; // 4 -static const uint64_t SH_FLD_START_FUNC_MODE = 17326; // 4 -static const uint64_t SH_FLD_START_INIT = 17327; // 8 -static const uint64_t SH_FLD_START_JTAG_CMD = 17328; // 1 -static const uint64_t SH_FLD_START_LANE_ID = 17329; // 8 -static const uint64_t SH_FLD_START_LANE_ID_LEN = 17330; // 8 -static const uint64_t SH_FLD_START_LEN = 17331; // 36 -static const uint64_t SH_FLD_START_PPE_ADDR = 17332; // 4 -static const uint64_t SH_FLD_START_PPE_ADDR_LEN = 17333; // 4 -static const uint64_t SH_FLD_START_READ = 17334; // 1 -static const uint64_t SH_FLD_START_REPAIR = 17335; // 4 -static const uint64_t SH_FLD_START_RESTART_VECTOR0 = 17336; // 1 -static const uint64_t SH_FLD_START_RESTART_VECTOR1 = 17337; // 1 -static const uint64_t SH_FLD_START_SEEPROM_ADDRESS = 17338; // 4 -static const uint64_t SH_FLD_START_SEEPROM_ADDRESS_LEN = 17339; // 4 -static const uint64_t SH_FLD_START_WIRETEST = 17340; // 4 -static const uint64_t SH_FLD_START_WRITE = 17341; // 1 -static const uint64_t SH_FLD_START_WR_ADDR = 17342; // 2 -static const uint64_t SH_FLD_START_WR_ADDR_LEN = 17343; // 2 -static const uint64_t SH_FLD_STAT = 17344; // 2 -static const uint64_t SH_FLD_STATE = 17345; // 44 -static const uint64_t SH_FLD_STATE_LEN = 17346; // 43 -static const uint64_t SH_FLD_STATE_LOSS_ENABLE_A_N = 17347; // 96 -static const uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY = 17348; // 1 -static const uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN = 17349; // 1 -static const uint64_t SH_FLD_STATIC_MAX_SPARES_EXCEEDED = 17350; // 8 -static const uint64_t SH_FLD_STATIC_SPARE_DEPLOYED = 17351; // 8 -static const uint64_t SH_FLD_STATUS = 17352; // 5 -static const uint64_t SH_FLD_STATUS_INVALID_CRESP = 17353; // 2 -static const uint64_t SH_FLD_STATUS_LEN = 17354; // 2 -static const uint64_t SH_FLD_STATUS_PARITY_ERROR = 17355; // 2 -static const uint64_t SH_FLD_STATUS_PERV = 17356; // 129 -static const uint64_t SH_FLD_STATUS_REC_DROPPED_Q = 17357; // 26 -static const uint64_t SH_FLD_STATUS_REG = 17358; // 1 -static const uint64_t SH_FLD_STATUS_REG_LEN = 17359; // 1 -static const uint64_t SH_FLD_STATUS_SCOM_ERROR = 17360; // 26 -static const uint64_t SH_FLD_STATUS_TRIG_DROPPED_Q = 17361; // 26 -static const uint64_t SH_FLD_STATUS_UNIT1 = 17362; // 129 -static const uint64_t SH_FLD_STATUS_UNIT10 = 17363; // 129 -static const uint64_t SH_FLD_STATUS_UNIT2 = 17364; // 129 -static const uint64_t SH_FLD_STATUS_UNIT3 = 17365; // 129 -static const uint64_t SH_FLD_STATUS_UNIT4 = 17366; // 129 -static const uint64_t SH_FLD_STATUS_UNIT5 = 17367; // 129 -static const uint64_t SH_FLD_STATUS_UNIT6 = 17368; // 129 -static const uint64_t SH_FLD_STATUS_UNIT7 = 17369; // 129 -static const uint64_t SH_FLD_STATUS_UNIT8 = 17370; // 129 -static const uint64_t SH_FLD_STATUS_UNIT9 = 17371; // 129 -static const uint64_t SH_FLD_STATUS_UNUSED = 17372; // 24 -static const uint64_t SH_FLD_STATUS_UNUSED_LEN = 17373; // 24 -static const uint64_t SH_FLD_STAT_LEN = 17374; // 2 -static const uint64_t SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE = 17375; // 1 -static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION = 17376; // 1 -static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR = 17377; // 3 -static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 17378; // 3 -static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN = 17379; // 1 -static const uint64_t SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 17380; // 1 -static const uint64_t SH_FLD_STEP_CHECK_STEP_SELECT = 17381; // 1 -static const uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT = 17382; // 1 -static const uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN = 17383; // 1 -static const uint64_t SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE = 17384; // 1 -static const uint64_t SH_FLD_STICKY_CACHE_VDM_DATA = 17385; // 12 -static const uint64_t SH_FLD_STICKY_CACHE_VDM_DATA_LEN = 17386; // 12 -static const uint64_t SH_FLD_STICKY_CORE0_VDM_DATA = 17387; // 12 -static const uint64_t SH_FLD_STICKY_CORE0_VDM_DATA_LEN = 17388; // 12 -static const uint64_t SH_FLD_STICKY_CORE1_VDM_DATA = 17389; // 12 -static const uint64_t SH_FLD_STICKY_CORE1_VDM_DATA_LEN = 17390; // 12 -static const uint64_t SH_FLD_STICKY_CORE2_VDM_DATA = 17391; // 12 -static const uint64_t SH_FLD_STICKY_CORE2_VDM_DATA_LEN = 17392; // 12 -static const uint64_t SH_FLD_STICKY_CORE3_VDM_DATA = 17393; // 12 -static const uint64_t SH_FLD_STICKY_CORE3_VDM_DATA_LEN = 17394; // 12 -static const uint64_t SH_FLD_STICKY_ERROR_INJECT_ENABLE = 17395; // 1 -static const uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY = 17396; // 12 -static const uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN = 17397; // 12 -static const uint64_t SH_FLD_STOP = 17398; // 6 -static const uint64_t SH_FLD_STOP1_ACTIVE_ENABLE = 17399; // 12 -static const uint64_t SH_FLD_STOPPED = 17400; // 2 -static const uint64_t SH_FLD_STOP_ACTIVE_MASK = 17401; // 12 -static const uint64_t SH_FLD_STOP_ERROR_0 = 17402; // 4 -static const uint64_t SH_FLD_STOP_ERROR_1 = 17403; // 2 -static const uint64_t SH_FLD_STOP_ERROR_2 = 17404; // 2 -static const uint64_t SH_FLD_STOP_ERROR_3 = 17405; // 2 -static const uint64_t SH_FLD_STOP_EXIT_TYPE_SEL = 17406; // 24 -static const uint64_t SH_FLD_STOP_ON_ERR = 17407; // 45 -static const uint64_t SH_FLD_STOP_ON_RECOV_ERR_SELECTION = 17408; // 43 -static const uint64_t SH_FLD_STOP_ON_SPATTN_SELECTION = 17409; // 43 -static const uint64_t SH_FLD_STOP_ON_XSTOP_SELECTION = 17410; // 43 -static const uint64_t SH_FLD_STOP_OVERRIDE_MODE = 17411; // 12 -static const uint64_t SH_FLD_STOP_RECOVERY_NOTIFY_PRD = 17412; // 1 -static const uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N = 17413; // 96 -static const uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN = 17414; // 96 -static const uint64_t SH_FLD_STOP_RUNN_ON_XSTOP = 17415; // 43 -static const uint64_t SH_FLD_STORE_ADDRESS = 17416; // 21 -static const uint64_t SH_FLD_STORE_ADDRESS_LEN = 17417; // 21 -static const uint64_t SH_FLD_STORE_ON_TRIG_MODE = 17418; // 90 -static const uint64_t SH_FLD_STORE_ON_TRIG_MODE_LEN = 17419; // 90 -static const uint64_t SH_FLD_STORE_TIMEOUT = 17420; // 12 -static const uint64_t SH_FLD_STQ_DATA_HANG = 17421; // 1 -static const uint64_t SH_FLD_STQ_DATA_PARITY_ERR = 17422; // 12 -static const uint64_t SH_FLD_STQ_ERR = 17423; // 12 -static const uint64_t SH_FLD_STQ_ERR_LEN = 17424; // 12 -static const uint64_t SH_FLD_STQ_FSM_PERR = 17425; // 1 -static const uint64_t SH_FLD_STQ_HW_MAX_0_4 = 17426; // 1 -static const uint64_t SH_FLD_STQ_HW_MAX_0_4_LEN = 17427; // 1 -static const uint64_t SH_FLD_STQ_HW_MIN_0_4 = 17428; // 1 -static const uint64_t SH_FLD_STQ_HW_MIN_0_4_LEN = 17429; // 1 -static const uint64_t SH_FLD_STQ_HYP_MAX_0_4 = 17430; // 1 -static const uint64_t SH_FLD_STQ_HYP_MAX_0_4_LEN = 17431; // 1 -static const uint64_t SH_FLD_STQ_HYP_MIN_0_4 = 17432; // 1 -static const uint64_t SH_FLD_STQ_HYP_MIN_0_4_LEN = 17433; // 1 -static const uint64_t SH_FLD_STQ_IPI_MAX_0_4 = 17434; // 1 -static const uint64_t SH_FLD_STQ_IPI_MAX_0_4_LEN = 17435; // 1 -static const uint64_t SH_FLD_STQ_IPI_MIN_0_4 = 17436; // 1 -static const uint64_t SH_FLD_STQ_IPI_MIN_0_4_LEN = 17437; // 1 -static const uint64_t SH_FLD_STQ_OS_MAX_0_4 = 17438; // 1 -static const uint64_t SH_FLD_STQ_OS_MAX_0_4_LEN = 17439; // 1 -static const uint64_t SH_FLD_STQ_OS_MIN_0_4 = 17440; // 1 -static const uint64_t SH_FLD_STQ_OS_MIN_0_4_LEN = 17441; // 1 -static const uint64_t SH_FLD_STQ_RDI_MAX_0_4 = 17442; // 1 -static const uint64_t SH_FLD_STQ_RDI_MAX_0_4_LEN = 17443; // 1 -static const uint64_t SH_FLD_STQ_RDI_MIN_0_4 = 17444; // 1 -static const uint64_t SH_FLD_STQ_RDI_MIN_0_4_LEN = 17445; // 1 -static const uint64_t SH_FLD_STQ_REG_MAX_0_4 = 17446; // 1 -static const uint64_t SH_FLD_STQ_REG_MAX_0_4_LEN = 17447; // 1 -static const uint64_t SH_FLD_STQ_REG_MIN_0_4 = 17448; // 1 -static const uint64_t SH_FLD_STQ_REG_MIN_0_4_LEN = 17449; // 1 -static const uint64_t SH_FLD_STQ_THR_MAX_0_4 = 17450; // 1 -static const uint64_t SH_FLD_STQ_THR_MAX_0_4_LEN = 17451; // 1 -static const uint64_t SH_FLD_STQ_THR_MIN_0_4 = 17452; // 1 -static const uint64_t SH_FLD_STQ_THR_MIN_0_4_LEN = 17453; // 1 -static const uint64_t SH_FLD_STQ_TYPE = 17454; // 12 -static const uint64_t SH_FLD_STQ_TYPE_LEN = 17455; // 12 -static const uint64_t SH_FLD_STQ_VPC_MAX_0_4 = 17456; // 1 -static const uint64_t SH_FLD_STQ_VPC_MAX_0_4_LEN = 17457; // 1 -static const uint64_t SH_FLD_STQ_VPC_MIN_0_4 = 17458; // 1 -static const uint64_t SH_FLD_STQ_VPC_MIN_0_4_LEN = 17459; // 1 -static const uint64_t SH_FLD_STREAM_MODE = 17460; // 4 -static const uint64_t SH_FLD_STREAM_TYPE = 17461; // 4 -static const uint64_t SH_FLD_STRICT_IPI_RULES = 17462; // 1 -static const uint64_t SH_FLD_STRICT_ORDER = 17463; // 1 -static const uint64_t SH_FLD_STROBE_WINDOW_EN = 17464; // 43 -static const uint64_t SH_FLD_ST_ACK_DEAD = 17465; // 12 -static const uint64_t SH_FLD_ST_ADDR_ERR = 17466; // 12 -static const uint64_t SH_FLD_ST_CLASS_CMD_ADDR_ERR = 17467; // 4 -static const uint64_t SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 17468; // 4 -static const uint64_t SH_FLD_ST_ECC_CE = 17469; // 1 -static const uint64_t SH_FLD_ST_ECC_UE = 17470; // 1 -static const uint64_t SH_FLD_SUE_0 = 17471; // 8 -static const uint64_t SH_FLD_SUE_1 = 17472; // 8 -static const uint64_t SH_FLD_SUE_DIS_BR = 17473; // 3 -static const uint64_t SH_FLD_SUE_DIS_BR_PERR = 17474; // 3 -static const uint64_t SH_FLD_SUE_DIS_IR = 17475; // 3 -static const uint64_t SH_FLD_SUE_DIS_IR_PERR = 17476; // 3 -static const uint64_t SH_FLD_SUE_DIS_OR = 17477; // 3 -static const uint64_t SH_FLD_SUE_DIS_OR_PERR = 17478; // 3 -static const uint64_t SH_FLD_SUE_DIS_PR = 17479; // 3 -static const uint64_t SH_FLD_SUE_DIS_PT = 17480; // 3 -static const uint64_t SH_FLD_SUMMARY = 17481; // 1 -static const uint64_t SH_FLD_SUOP_ERROR_1 = 17482; // 4 -static const uint64_t SH_FLD_SUOP_ERROR_2 = 17483; // 4 -static const uint64_t SH_FLD_SUOP_ERROR_3 = 17484; // 4 -static const uint64_t SH_FLD_SUPPRESS = 17485; // 301 -static const uint64_t SH_FLD_SUPPRESS_EVEN_CLK = 17486; // 43 -static const uint64_t SH_FLD_SWC_VALUE = 17487; // 1 -static const uint64_t SH_FLD_SWC_VALUE_LEN = 17488; // 1 -static const uint64_t SH_FLD_SWITCH_SYNC_ERROR_DISABLE = 17489; // 1 -static const uint64_t SH_FLD_SYM_CPB_CHECK_DISABLE = 17490; // 1 -static const uint64_t SH_FLD_SYM_MAX_INRD = 17491; // 1 -static const uint64_t SH_FLD_SYM_MAX_INRD_LEN = 17492; // 1 -static const uint64_t SH_FLD_SYNCEN = 17493; // 7 -static const uint64_t SH_FLD_SYNC_BRK = 17494; // 1 -static const uint64_t SH_FLD_SYNC_BRK_LEN = 17495; // 1 -static const uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT = 17496; // 1 -static const uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT_LEN = 17497; // 1 -static const uint64_t SH_FLD_SYNC_DONE = 17498; // 2 -static const uint64_t SH_FLD_SYNC_DONE_LEN = 17499; // 2 -static const uint64_t SH_FLD_SYNC_FENCE = 17500; // 4 -static const uint64_t SH_FLD_SYNC_GO_CH0 = 17501; // 4 -static const uint64_t SH_FLD_SYNC_GO_CH1 = 17502; // 4 -static const uint64_t SH_FLD_SYNC_HEADER_ERROR_RATE = 17503; // 2 -static const uint64_t SH_FLD_SYNC_HEADER_ERROR_RATE_LEN = 17504; // 2 -static const uint64_t SH_FLD_SYNC_MODE = 17505; // 4 -static const uint64_t SH_FLD_SYNC_REPLAY_COUNT = 17506; // 4 -static const uint64_t SH_FLD_SYNC_REPLAY_COUNT_LEN = 17507; // 4 -static const uint64_t SH_FLD_SYNC_RESERVED = 17508; // 4 -static const uint64_t SH_FLD_SYNC_RESERVED_LEN = 17509; // 4 -static const uint64_t SH_FLD_SYNC_RESET = 17510; // 1 -static const uint64_t SH_FLD_SYNC_TIMER_SEL = 17511; // 1 -static const uint64_t SH_FLD_SYNC_TIMER_SEL_LEN = 17512; // 1 -static const uint64_t SH_FLD_SYNC_TYPE = 17513; // 4 -static const uint64_t SH_FLD_SYNC_TYPE_LEN = 17514; // 4 -static const uint64_t SH_FLD_SYNC_WAIT = 17515; // 1 -static const uint64_t SH_FLD_SYNC_WAIT_LEN = 17516; // 1 -static const uint64_t SH_FLD_SYNDROME = 17517; // 8 -static const uint64_t SH_FLD_SYNDROME_LEN = 17518; // 8 -static const uint64_t SH_FLD_SYN_HI_0_7 = 17519; // 1 -static const uint64_t SH_FLD_SYN_HI_0_7_LEN = 17520; // 1 -static const uint64_t SH_FLD_SYN_LO_0_7 = 17521; // 1 -static const uint64_t SH_FLD_SYN_LO_0_7_LEN = 17522; // 1 -static const uint64_t SH_FLD_SYSCLK_2X_MEMINTCLKO = 17523; // 8 -static const uint64_t SH_FLD_SYSCLK_RESET = 17524; // 8 -static const uint64_t SH_FLD_SYSMAP_SM_NOT_LG_SEL = 17525; // 12 -static const uint64_t SH_FLD_SYSTEM = 17526; // 2 -static const uint64_t SH_FLD_SYSTEM_CHECKSTOP = 17527; // 1 -static const uint64_t SH_FLD_SYSTEM_FAST_INIT = 17528; // 43 -static const uint64_t SH_FLD_SYSTEM_LEN = 17529; // 2 -static const uint64_t SH_FLD_SYSTEM_RESET = 17530; // 1 -static const uint64_t SH_FLD_S_PATH_0_PARITY = 17531; // 4 -static const uint64_t SH_FLD_S_PATH_0_STEP_CHECK = 17532; // 4 -static const uint64_t SH_FLD_S_PATH_0_STEP_CHECK_VALID = 17533; // 1 -static const uint64_t SH_FLD_S_PATH_1_PARITY = 17534; // 4 -static const uint64_t SH_FLD_S_PATH_1_STEP_CHECK = 17535; // 4 -static const uint64_t SH_FLD_S_PATH_1_STEP_CHECK_VALID = 17536; // 1 -static const uint64_t SH_FLD_S_PATH_SELECT = 17537; // 1 -static const uint64_t SH_FLD_T0_RUN_Q = 17538; // 24 -static const uint64_t SH_FLD_T1_RUN_Q = 17539; // 24 -static const uint64_t SH_FLD_T2_RUN_Q = 17540; // 24 -static const uint64_t SH_FLD_T3_RUN_Q = 17541; // 24 -static const uint64_t SH_FLD_T4_RUN_Q = 17542; // 24 -static const uint64_t SH_FLD_T5_RUN_Q = 17543; // 24 -static const uint64_t SH_FLD_T6_RUN_Q = 17544; // 24 -static const uint64_t SH_FLD_T7_RUN_Q = 17545; // 24 -static const uint64_t SH_FLD_TABLE_ADDRESS = 17546; // 1 -static const uint64_t SH_FLD_TABLE_ADDRESS_LEN = 17547; // 1 -static const uint64_t SH_FLD_TABLE_DATA = 17548; // 1 -static const uint64_t SH_FLD_TABLE_DATA_LEN = 17549; // 1 -static const uint64_t SH_FLD_TABLE_SELECT = 17550; // 1 -static const uint64_t SH_FLD_TABLE_SELECT_LEN = 17551; // 1 -static const uint64_t SH_FLD_TABLE_SEL_0_3 = 17552; // 1 -static const uint64_t SH_FLD_TABLE_SEL_0_3_LEN = 17553; // 1 -static const uint64_t SH_FLD_TAG_ECC = 17554; // 12 -static const uint64_t SH_FLD_TAG_ECC_LEN = 17555; // 12 -static const uint64_t SH_FLD_TAP_SEL = 17556; // 24 -static const uint64_t SH_FLD_TAP_SEL_LEN = 17557; // 24 -static const uint64_t SH_FLD_TARGET = 17558; // 2 -static const uint64_t SH_FLD_TARGET_DDE = 17559; // 3 -static const uint64_t SH_FLD_TARGET_DDE_LEN = 17560; // 3 -static const uint64_t SH_FLD_TARGET_ID0 = 17561; // 2 -static const uint64_t SH_FLD_TARGET_LEN = 17562; // 2 -static const uint64_t SH_FLD_TARGET_MIN = 17563; // 2 -static const uint64_t SH_FLD_TARGET_MIN_LEN = 17564; // 2 -static const uint64_t SH_FLD_TARGET_VALID = 17565; // 2 -static const uint64_t SH_FLD_TARGET_VALID_LEN = 17566; // 2 -static const uint64_t SH_FLD_TBST0_BADIN_ERRHOLD = 17567; // 2 -static const uint64_t SH_FLD_TBST6_BADIN_ERRHOLD = 17568; // 2 -static const uint64_t SH_FLD_TBST7_BADIN_ERRHOLD = 17569; // 2 -static const uint64_t SH_FLD_TBST9_BADIN_ERRHOLD = 17570; // 2 -static const uint64_t SH_FLD_TBST_CORRUPT_ERRHOLD = 17571; // 2 -static const uint64_t SH_FLD_TB_CMD_DISCARDED_ERRHOLD = 17572; // 2 -static const uint64_t SH_FLD_TB_FIR_ERR_ERRHOLD = 17573; // 2 -static const uint64_t SH_FLD_TB_MISSING_STEP_ERRHOLD = 17574; // 2 -static const uint64_t SH_FLD_TB_MISSING_SYNC_ERRHOLD = 17575; // 2 -static const uint64_t SH_FLD_TB_REG_RDATA_PERR_ERRHOLD = 17576; // 2 -static const uint64_t SH_FLD_TB_RESIDUE_ERR_ERRHOLD = 17577; // 2 -static const uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_0 = 17578; // 4 -static const uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_1 = 17579; // 4 -static const uint64_t SH_FLD_TCD_PERR_ESR = 17580; // 1 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ = 17581; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN = 17582; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN = 17583; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN = 17584; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP = 17585; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN = 17586; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN = 17587; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN = 17588; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP = 17589; // 24 -static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN = 17590; // 24 -static const uint64_t SH_FLD_TCE_CACHE_1W = 17591; // 1 -static const uint64_t SH_FLD_TCE_CACHE_DISABLE = 17592; // 1 -static const uint64_t SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR = 17593; // 1 -static const uint64_t SH_FLD_TCE_COMMON_FATAL_ERROR = 17594; // 6 -static const uint64_t SH_FLD_TCE_ECC_CORRECTABLE_ERROR = 17595; // 6 -static const uint64_t SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR = 17596; // 6 -static const uint64_t SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR = 17597; // 6 -static const uint64_t SH_FLD_TCE_PAGE_ACCESS_ERR_ESR = 17598; // 1 -static const uint64_t SH_FLD_TCE_REQUEST_TIMEOUT_ERROR = 17599; // 6 -static const uint64_t SH_FLD_TCE_REQ_TO_ERR_ESR = 17600; // 1 -static const uint64_t SH_FLD_TCE_RESPONSE = 17601; // 1 -static const uint64_t SH_FLD_TCE_TIMEOUT = 17602; // 1 -static const uint64_t SH_FLD_TCE_TIMEOUT_LEN = 17603; // 1 -static const uint64_t SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR = 17604; // 6 -static const uint64_t SH_FLD_TCK_WIDTH = 17605; // 1 -static const uint64_t SH_FLD_TCK_WIDTH_LEN = 17606; // 1 -static const uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP = 17607; // 1 -static const uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN = 17608; // 1 -static const uint64_t SH_FLD_TCTXT_PRESP_ERROR = 17609; // 1 -static const uint64_t SH_FLD_TC_BSC_EXTMODE_DC = 17610; // 43 -static const uint64_t SH_FLD_TC_BSC_INTMODE_DC = 17611; // 43 -static const uint64_t SH_FLD_TC_BSC_INV_DC = 17612; // 43 -static const uint64_t SH_FLD_TC_BSC_WRAPSEL_DC = 17613; // 43 -static const uint64_t SH_FLD_TC_DIAG_PORT0_OUT = 17614; // 43 -static const uint64_t SH_FLD_TC_DIAG_PORT1_OUT = 17615; // 43 -static const uint64_t SH_FLD_TC_EDRAM_ABIST_MODE_DC = 17616; // 43 -static const uint64_t SH_FLD_TC_IOBIST_MODE_DC = 17617; // 43 -static const uint64_t SH_FLD_TC_IOM01_DDR0_DFI_RESET_ALL = 17618; // 2 -static const uint64_t SH_FLD_TC_IOM01_DDR1_DFI_RESET_ALL = 17619; // 2 -static const uint64_t SH_FLD_TC_IOM01_DDR2_DFI_RESET_ALL = 17620; // 2 -static const uint64_t SH_FLD_TC_IOM01_DDR3_DFI_RESET_ALL = 17621; // 2 -static const uint64_t SH_FLD_TC_IOM01_FORCETOKNOWN_DC = 17622; // 2 -static const uint64_t SH_FLD_TC_IOP_HSSPORWREN = 17623; // 4 -static const uint64_t SH_FLD_TC_IOP_SYS_RESET_PCS = 17624; // 4 -static const uint64_t SH_FLD_TC_IOP_SYS_RESET_PMA = 17625; // 4 -static const uint64_t SH_FLD_TC_IOX_MUX_VSEL = 17626; // 1 -static const uint64_t SH_FLD_TC_IOX_MUX_VSEL_LEN = 17627; // 1 -static const uint64_t SH_FLD_TC_LP_RESET = 17628; // 1 -static const uint64_t SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC = 17629; // 43 -static const uint64_t SH_FLD_TC_NBTI_PROBE_GATE_DC = 17630; // 43 -static const uint64_t SH_FLD_TC_OB_RATIO_DC = 17631; // 6 -static const uint64_t SH_FLD_TC_OB_RATIO_DC_LEN = 17632; // 6 -static const uint64_t SH_FLD_TC_OELCC_ALIGN_FLUSH_DC = 17633; // 43 -static const uint64_t SH_FLD_TC_OELCC_EDGE_DELAYED_DC = 17634; // 43 -static const uint64_t SH_FLD_TC_PBE0_IOVALID_DC = 17635; // 1 -static const uint64_t SH_FLD_TC_PBE1_IOVALID_DC = 17636; // 1 -static const uint64_t SH_FLD_TC_PBE2_IOVALID_DC = 17637; // 1 -static const uint64_t SH_FLD_TC_PBE3_IOVALID_DC = 17638; // 1 -static const uint64_t SH_FLD_TC_PBE4_IOVALID_DC = 17639; // 1 -static const uint64_t SH_FLD_TC_PBE5_IOVALID_DC = 17640; // 1 -static const uint64_t SH_FLD_TC_PBIOO0_IOVALID = 17641; // 6 -static const uint64_t SH_FLD_TC_PBIOO1_IOVALID = 17642; // 6 -static const uint64_t SH_FLD_TC_PCI0_IOVALID = 17643; // 1 -static const uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC = 17644; // 1 -static const uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC_LEN = 17645; // 1 -static const uint64_t SH_FLD_TC_PCI0_RATIO_DC = 17646; // 1 -static const uint64_t SH_FLD_TC_PCI0_RATIO_DC_LEN = 17647; // 1 -static const uint64_t SH_FLD_TC_PCI0_RATIO_OVERRIDE = 17648; // 1 -static const uint64_t SH_FLD_TC_PCI0_SWAP_DC = 17649; // 1 -static const uint64_t SH_FLD_TC_PCI1X_IOVALID = 17650; // 1 -static const uint64_t SH_FLD_TC_PCI1X_IOVALID_LEN = 17651; // 1 -static const uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC = 17652; // 1 -static const uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC_LEN = 17653; // 1 -static const uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC = 17654; // 1 -static const uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC_LEN = 17655; // 1 -static const uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC = 17656; // 1 -static const uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC_LEN = 17657; // 1 -static const uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE = 17658; // 1 -static const uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE_LEN = 17659; // 1 -static const uint64_t SH_FLD_TC_PCI1_SWAP_DC = 17660; // 1 -static const uint64_t SH_FLD_TC_PCI1_SWAP_DC_LEN = 17661; // 1 -static const uint64_t SH_FLD_TC_PCI2_IOVALID = 17662; // 2 -static const uint64_t SH_FLD_TC_PCI2_IOVALID_LEN = 17663; // 2 -static const uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC = 17664; // 2 -static const uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC_LEN = 17665; // 2 -static const uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC = 17666; // 2 -static const uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC_LEN = 17667; // 2 -static const uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC = 17668; // 2 -static const uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC_LEN = 17669; // 2 -static const uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC = 17670; // 2 -static const uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC_LEN = 17671; // 2 -static const uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE = 17672; // 2 -static const uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE_LEN = 17673; // 2 -static const uint64_t SH_FLD_TC_PCI2_SWAP_DC = 17674; // 2 -static const uint64_t SH_FLD_TC_PCI2_SWAP_DC_LEN = 17675; // 2 -static const uint64_t SH_FLD_TC_PERV_EXPORT_FREEZE = 17676; // 1 -static const uint64_t SH_FLD_TC_PERV_REGION_FENCE = 17677; // 43 -static const uint64_t SH_FLD_TC_PSI_IOVALID_DC = 17678; // 1 -static const uint64_t SH_FLD_TC_PSRO_SEL_DC = 17679; // 43 -static const uint64_t SH_FLD_TC_PSRO_SEL_DC_LEN = 17680; // 43 -static const uint64_t SH_FLD_TC_REFCLK_DRVR_EN_DC = 17681; // 43 -static const uint64_t SH_FLD_TC_REGION1_FENCE = 17682; // 36 -static const uint64_t SH_FLD_TC_REGION2_FENCE = 17683; // 36 -static const uint64_t SH_FLD_TC_REGION3_FENCE = 17684; // 36 -static const uint64_t SH_FLD_TC_REGION4_FENCE = 17685; // 31 -static const uint64_t SH_FLD_TC_REGION5_FENCE = 17686; // 28 -static const uint64_t SH_FLD_TC_REGION6_FENCE = 17687; // 26 -static const uint64_t SH_FLD_TC_REGION7_FENCE = 17688; // 25 -static const uint64_t SH_FLD_TC_REGION8_FENCE = 17689; // 24 -static const uint64_t SH_FLD_TC_REGION9_FENCE = 17690; // 24 -static const uint64_t SH_FLD_TC_SKIT_MODE_BIST_DC = 17691; // 43 -static const uint64_t SH_FLD_TC_SRAM_ABIST_MODE_DC = 17692; // 43 -static const uint64_t SH_FLD_TC_START_TEST_DC = 17693; // 43 -static const uint64_t SH_FLD_TC_UNIT_ARY_WRT_THRU_DC = 17694; // 43 -static const uint64_t SH_FLD_TC_UNIT_AVP_MODE = 17695; // 43 -static const uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC = 17696; // 43 -static const uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC_LEN = 17697; // 43 -static const uint64_t SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 17698; // 43 -static const uint64_t SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 17699; // 43 -static const uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC = 17700; // 43 -static const uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC_LEN = 17701; // 43 -static const uint64_t SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC = 17702; // 43 -static const uint64_t SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE = 17703; // 43 -static const uint64_t SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC = 17704; // 43 -static const uint64_t SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC = 17705; // 43 -static const uint64_t SH_FLD_TC_UNIT_SYS_ID_DC = 17706; // 43 -static const uint64_t SH_FLD_TC_UNIT_SYS_ID_DC_LEN = 17707; // 43 -static const uint64_t SH_FLD_TC_VITL_REGION_FENCE = 17708; // 43 -static const uint64_t SH_FLD_TDM_DELAY = 17709; // 5 -static const uint64_t SH_FLD_TDM_DELAY_LEN = 17710; // 5 -static const uint64_t SH_FLD_TDR_DAC_CNTL = 17711; // 6 -static const uint64_t SH_FLD_TDR_DAC_CNTL_LEN = 17712; // 6 -static const uint64_t SH_FLD_TDR_ENABLE = 17713; // 116 -static const uint64_t SH_FLD_TDR_PERR_ESR = 17714; // 1 -static const uint64_t SH_FLD_TDR_PHASE_SEL = 17715; // 6 -static const uint64_t SH_FLD_TDR_PULSE_OFFSET = 17716; // 6 -static const uint64_t SH_FLD_TDR_PULSE_OFFSET_LEN = 17717; // 6 -static const uint64_t SH_FLD_TDR_PULSE_WIDTH = 17718; // 6 -static const uint64_t SH_FLD_TDR_PULSE_WIDTH_LEN = 17719; // 6 -static const uint64_t SH_FLD_TER = 17720; // 8 -static const uint64_t SH_FLD_TERM_ENC = 17721; // 1 -static const uint64_t SH_FLD_TERM_ENC_LEN = 17722; // 1 -static const uint64_t SH_FLD_TERM_TEST = 17723; // 1 -static const uint64_t SH_FLD_TER_LEN = 17724; // 8 -static const uint64_t SH_FLD_TER_V = 17725; // 8 -static const uint64_t SH_FLD_TEST_ENABLE = 17726; // 43 -static const uint64_t SH_FLD_TFAC_ERR = 17727; // 96 -static const uint64_t SH_FLD_TFMR_PARITY_ERR = 17728; // 96 -static const uint64_t SH_FLD_TFREQ0 = 17729; // 9 -static const uint64_t SH_FLD_TFREQ0_LEN = 17730; // 9 -static const uint64_t SH_FLD_TFREQ1 = 17731; // 9 -static const uint64_t SH_FLD_TFREQ1_LEN = 17732; // 9 -static const uint64_t SH_FLD_TGT_NODAL_DINC_ERR = 17733; // 12 -static const uint64_t SH_FLD_TGT_NODAL_REQ_DINC_ERR = 17734; // 12 -static const uint64_t SH_FLD_THERM_MODE = 17735; // 43 -static const uint64_t SH_FLD_THERM_MODEREG_PARITY_MASK = 17736; // 43 -static const uint64_t SH_FLD_THERM_MODE_LEN = 17737; // 43 -static const uint64_t SH_FLD_THERM_TRIP = 17738; // 43 -static const uint64_t SH_FLD_THERM_TRIP_LEN = 17739; // 43 -static const uint64_t SH_FLD_THRESHOLD = 17740; // 1 -static const uint64_t SH_FLD_THRESH_0 = 17741; // 3 -static const uint64_t SH_FLD_THRESH_0_LEN = 17742; // 3 -static const uint64_t SH_FLD_THRESH_1 = 17743; // 3 -static const uint64_t SH_FLD_THRESH_1_LEN = 17744; // 3 -static const uint64_t SH_FLD_THRESH_2 = 17745; // 3 -static const uint64_t SH_FLD_THRESH_2_LEN = 17746; // 3 -static const uint64_t SH_FLD_THRESH_DIS_TAP_CLEAR = 17747; // 12 -static const uint64_t SH_FLD_THRESH_DIS_TAP_STOP = 17748; // 12 -static const uint64_t SH_FLD_THRESH_DIS_TB_CLEAR = 17749; // 12 -static const uint64_t SH_FLD_THRESH_ENABLE = 17750; // 12 -static const uint64_t SH_FLD_THRESH_ENABLE_LEN = 17751; // 12 -static const uint64_t SH_FLD_THRESH_LINK0_CLEAR = 17752; // 12 -static const uint64_t SH_FLD_THRESH_LINK0_COUNT = 17753; // 12 -static const uint64_t SH_FLD_THRESH_LINK0_COUNT_LEN = 17754; // 12 -static const uint64_t SH_FLD_THRESH_LINK1_CLEAR = 17755; // 12 -static const uint64_t SH_FLD_THRESH_LINK1_COUNT = 17756; // 12 -static const uint64_t SH_FLD_THRESH_LINK1_COUNT_LEN = 17757; // 12 -static const uint64_t SH_FLD_THRESH_TAP_SEL = 17758; // 12 -static const uint64_t SH_FLD_THRESH_TAP_SEL_LEN = 17759; // 12 -static const uint64_t SH_FLD_THRESH_TB_SEL = 17760; // 12 -static const uint64_t SH_FLD_THRESH_TB_SEL_LEN = 17761; // 12 -static const uint64_t SH_FLD_THRESH_UNUSED1 = 17762; // 12 -static const uint64_t SH_FLD_THRESH_UNUSED1_LEN = 17763; // 12 -static const uint64_t SH_FLD_THRESH_UNUSED2 = 17764; // 12 -static const uint64_t SH_FLD_THRES_ENA = 17765; // 43 -static const uint64_t SH_FLD_THRES_ENA_LEN = 17766; // 43 -static const uint64_t SH_FLD_THRES_OVERFLOW_MASK = 17767; // 43 -static const uint64_t SH_FLD_THRES_STATE_MASK = 17768; // 43 -static const uint64_t SH_FLD_THRES_TRIP_ENA = 17769; // 43 -static const uint64_t SH_FLD_THRES_TRIP_ENA_LEN = 17770; // 43 -static const uint64_t SH_FLD_THRID = 17771; // 1 -static const uint64_t SH_FLD_THRID_LEN = 17772; // 1 -static const uint64_t SH_FLD_THR_ID = 17773; // 1 -static const uint64_t SH_FLD_THR_ID_LEN = 17774; // 1 -static const uint64_t SH_FLD_TID = 17775; // 8 -static const uint64_t SH_FLD_TID_LEN = 17776; // 8 -static const uint64_t SH_FLD_TIER0_VALUE = 17777; // 12 -static const uint64_t SH_FLD_TIER0_VALUE_LEN = 17778; // 12 -static const uint64_t SH_FLD_TIER1_VALUE = 17779; // 24 -static const uint64_t SH_FLD_TIER1_VALUE_LEN = 17780; // 24 -static const uint64_t SH_FLD_TIER2_VALUE = 17781; // 24 -static const uint64_t SH_FLD_TIER2_VALUE_LEN = 17782; // 24 -static const uint64_t SH_FLD_TIME = 17783; // 43 -static const uint64_t SH_FLD_TIMEBASE = 17784; // 330 -static const uint64_t SH_FLD_TIMEBASE_ENABLE = 17785; // 1 -static const uint64_t SH_FLD_TIMEBASE_LEN = 17786; // 330 -static const uint64_t SH_FLD_TIMEOUT = 17787; // 5 -static const uint64_t SH_FLD_TIMEOUT_ACTIVE = 17788; // 2 -static const uint64_t SH_FLD_TIMEOUT_EN = 17789; // 1 -static const uint64_t SH_FLD_TIMEOUT_LEN = 17790; // 5 -static const uint64_t SH_FLD_TIMEOUT_MASK = 17791; // 43 -static const uint64_t SH_FLD_TIMEOUT_N = 17792; // 2 -static const uint64_t SH_FLD_TIMEOUT_ON_I2C_STATUS_RD = 17793; // 1 -static const uint64_t SH_FLD_TIMEOUT_PARITY = 17794; // 43 -static const uint64_t SH_FLD_TIMEOUT_SEL = 17795; // 3 -static const uint64_t SH_FLD_TIMEOUT_SEL_LEN = 17796; // 3 -static const uint64_t SH_FLD_TIMEOUT_VALUE = 17797; // 5 -static const uint64_t SH_FLD_TIMEOUT_VALUE_LEN = 17798; // 5 -static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 17799; // 43 -static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 17800; // 43 -static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 17801; // 43 -static const uint64_t SH_FLD_TIMER = 17802; // 3 -static const uint64_t SH_FLD_TIMER_1US = 17803; // 5 -static const uint64_t SH_FLD_TIMER_1US_LEN = 17804; // 5 -static const uint64_t SH_FLD_TIMER_ENABLE = 17805; // 4 -static const uint64_t SH_FLD_TIMER_EXPIRED_RECOV_ERROR = 17806; // 4 -static const uint64_t SH_FLD_TIMER_EXPIRED_XSTOP_ERROR = 17807; // 4 -static const uint64_t SH_FLD_TIMER_LEN = 17808; // 3 -static const uint64_t SH_FLD_TIMER_N = 17809; // 2 -static const uint64_t SH_FLD_TIMER_N_LEN = 17810; // 2 -static const uint64_t SH_FLD_TIMER_PERIOD_MASK = 17811; // 4 -static const uint64_t SH_FLD_TIMER_PERIOD_MASK_LEN = 17812; // 4 -static const uint64_t SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR = 17813; // 43 -static const uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE = 17814; // 43 -static const uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN = 17815; // 43 -static const uint64_t SH_FLD_TIME_BASE_ERR = 17816; // 4 -static const uint64_t SH_FLD_TLBIE_CNT_THRESH = 17817; // 13 -static const uint64_t SH_FLD_TLBIE_CNT_THRESH_LEN = 17818; // 13 -static const uint64_t SH_FLD_TLBIE_CNT_WT4TX_CORE_EN = 17819; // 12 -static const uint64_t SH_FLD_TLBIE_CONTROL_ERR = 17820; // 12 -static const uint64_t SH_FLD_TLBIE_DEC_RATE = 17821; // 13 -static const uint64_t SH_FLD_TLBIE_DEC_RATE_LEN = 17822; // 13 -static const uint64_t SH_FLD_TLBIE_INC_RATE = 17823; // 13 -static const uint64_t SH_FLD_TLBIE_INC_RATE_LEN = 17824; // 13 -static const uint64_t SH_FLD_TLBIE_MASTER_TIMEOUT = 17825; // 12 -static const uint64_t SH_FLD_TLBIE_PACING_CNT_EN = 17826; // 12 -static const uint64_t SH_FLD_TLBIE_SLBIEG_SW_ERR = 17827; // 12 -static const uint64_t SH_FLD_TLBIE_SNOOP_TIMEOUT = 17828; // 12 -static const uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT = 17829; // 14 -static const uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN = 17830; // 14 -static const uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT = 17831; // 14 -static const uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT_LEN = 17832; // 14 -static const uint64_t SH_FLD_TLBIE_STALL_EN = 17833; // 14 -static const uint64_t SH_FLD_TLBIE_STALL_THRESHOLD = 17834; // 14 -static const uint64_t SH_FLD_TLBIE_STALL_THRESHOLD_LEN = 17835; // 14 -static const uint64_t SH_FLD_TLBI_BAD_OP_ERR = 17836; // 4 -static const uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV = 17837; // 2 -static const uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN = 17838; // 2 -static const uint64_t SH_FLD_TLBI_FENCE = 17839; // 2 -static const uint64_t SH_FLD_TLBI_GROUP_PUMP_EN = 17840; // 12 -static const uint64_t SH_FLD_TLBI_PSL_DEAD = 17841; // 2 -static const uint64_t SH_FLD_TLBI_REGS_PARITY_ERRHOLD = 17842; // 2 -static const uint64_t SH_FLD_TLBI_SC_RDATA_PARITY_ERRHOLD = 17843; // 2 -static const uint64_t SH_FLD_TLBI_SEQ_NUM_PARITY_ERR = 17844; // 4 -static const uint64_t SH_FLD_TLBI_SOT_ERR = 17845; // 4 -static const uint64_t SH_FLD_TLBI_TIMEOUT = 17846; // 4 -static const uint64_t SH_FLD_TLB_BUS0_STG1_SEL = 17847; // 1 -static const uint64_t SH_FLD_TLB_BUS0_STG2_SEL = 17848; // 1 -static const uint64_t SH_FLD_TLB_BUS1_STG1_SEL = 17849; // 1 -static const uint64_t SH_FLD_TLB_BUS1_STG2_SEL = 17850; // 1 -static const uint64_t SH_FLD_TLB_CAC_PERR_DET = 17851; // 1 -static const uint64_t SH_FLD_TLB_CHK_WAIT_DEC = 17852; // 12 -static const uint64_t SH_FLD_TLB_CHK_WAIT_DEC_LEN = 17853; // 12 -static const uint64_t SH_FLD_TLB_DIR_PERR_DET = 17854; // 1 -static const uint64_t SH_FLD_TLB_LRU_PERR_DET = 17855; // 1 -static const uint64_t SH_FLD_TLB_MULTIHIT_DET = 17856; // 1 -static const uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV = 17857; // 12 -static const uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 17858; // 12 -static const uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV = 17859; // 12 -static const uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 17860; // 12 -static const uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV = 17861; // 12 -static const uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 17862; // 12 -static const uint64_t SH_FLD_TMOD_CYCLES = 17863; // 8 -static const uint64_t SH_FLD_TMOD_CYCLES_LEN = 17864; // 8 -static const uint64_t SH_FLD_TMRSC_CYCLES = 17865; // 8 -static const uint64_t SH_FLD_TMRSC_CYCLES_LEN = 17866; // 8 -static const uint64_t SH_FLD_TMR_PE = 17867; // 8 -static const uint64_t SH_FLD_TM_CAM = 17868; // 12 -static const uint64_t SH_FLD_TM_CAM_LEN = 17869; // 12 -static const uint64_t SH_FLD_TODTLON_OFF_CYCLES = 17870; // 8 -static const uint64_t SH_FLD_TODTLON_OFF_CYCLES_LEN = 17871; // 8 -static const uint64_t SH_FLD_TOD_CMD_OVERRUN = 17872; // 1 -static const uint64_t SH_FLD_TOD_CNTR_REF = 17873; // 1 -static const uint64_t SH_FLD_TOD_CNTR_REF_LEN = 17874; // 1 -static const uint64_t SH_FLD_TOD_HANG_ERR = 17875; // 1 -static const uint64_t SH_FLD_TOD_TAP = 17876; // 24 -static const uint64_t SH_FLD_TOO_MANY_BUS_ERRORS = 17877; // 8 -static const uint64_t SH_FLD_TOR_PERR_ESR = 17878; // 1 -static const uint64_t SH_FLD_TOTAL_DROOP_EVENT_CTR = 17879; // 12 -static const uint64_t SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN = 17880; // 12 -static const uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT = 17881; // 1 -static const uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT_LEN = 17882; // 1 -static const uint64_t SH_FLD_TO_CMP_LT = 17883; // 86 -static const uint64_t SH_FLD_TO_CMP_LT_LEN = 17884; // 86 -static const uint64_t SH_FLD_TO_IFU = 17885; // 24 -static const uint64_t SH_FLD_TO_ISU = 17886; // 24 -static const uint64_t SH_FLD_TO_LSU = 17887; // 24 -static const uint64_t SH_FLD_TO_PC = 17888; // 24 -static const uint64_t SH_FLD_TO_VSU = 17889; // 24 -static const uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC = 17890; // 3 -static const uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN = 17891; // 3 -static const uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC = 17892; // 3 -static const uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN = 17893; // 3 -static const uint64_t SH_FLD_TPCFSI_OPB_SW_RESET_DC = 17894; // 3 -static const uint64_t SH_FLD_TPFSI_ALTREFCLK_SE1 = 17895; // 3 -static const uint64_t SH_FLD_TPFSI_ALTREFCLK_SEL = 17896; // 3 -static const uint64_t SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 17897; // 2 -static const uint64_t SH_FLD_TPFSI_ARRAY_VBL_TO_VDD_DC = 17898; // 1 -static const uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC = 17899; // 3 -static const uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 17900; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW0_PGOOD_N = 17901; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW1_PGOOD = 17902; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC = 17903; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN = 17904; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC = 17905; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN = 17906; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC = 17907; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 17908; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 17909; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 17910; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC = 17911; // 3 -static const uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN = 17912; // 3 -static const uint64_t SH_FLD_TPFSI_TC_HSSPORWREN_ALLOW = 17913; // 3 -static const uint64_t SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC = 17914; // 3 -static const uint64_t SH_FLD_TPFSI_TP_EDRAM_CTRL_GATE = 17915; // 3 -static const uint64_t SH_FLD_TPFSI_TP_FENCE_VTLIO_DC = 17916; // 3 -static const uint64_t SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 17917; // 3 -static const uint64_t SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC = 17918; // 3 -static const uint64_t SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 17919; // 3 -static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 17920; // 3 -static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 17921; // 3 -static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 17922; // 3 -static const uint64_t SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 17923; // 3 -static const uint64_t SH_FLD_TPSBE_TPBR_SBE_INTR = 17924; // 1 -static const uint64_t SH_FLD_TPSBE_TPIO_TPM_RESET = 17925; // 1 -static const uint64_t SH_FLD_TPSBE_TPOCC_HALT_COMPLEX = 17926; // 1 -static const uint64_t SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC = 17927; // 3 -static const uint64_t SH_FLD_TP_CHIPLET_EN_DC = 17928; // 3 -static const uint64_t SH_FLD_TP_CLK_ASYNC_RESET_DC = 17929; // 3 -static const uint64_t SH_FLD_TP_CLK_DIV_BYPASS_EN_DC = 17930; // 3 -static const uint64_t SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC = 17931; // 3 -static const uint64_t SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC = 17932; // 3 -static const uint64_t SH_FLD_TP_CLK_PULSE_ENABLE_DC = 17933; // 3 -static const uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC = 17934; // 3 -static const uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC_LEN = 17935; // 3 -static const uint64_t SH_FLD_TP_CPM_CAL = 17936; // 1 -static const uint64_t SH_FLD_TP_CPM_CAL_SET = 17937; // 2 -static const uint64_t SH_FLD_TP_DI1_DC_B = 17938; // 3 -static const uint64_t SH_FLD_TP_DI1_DC_N = 17939; // 3 -static const uint64_t SH_FLD_TP_DI2_DC_B = 17940; // 3 -static const uint64_t SH_FLD_TP_DI2_DC_N = 17941; // 3 -static const uint64_t SH_FLD_TP_EDRAM_ENABLE_DC = 17942; // 3 -static const uint64_t SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC = 17943; // 1 -static const uint64_t SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 17944; // 1 -static const uint64_t SH_FLD_TP_FENCE_EN_DC = 17945; // 3 -static const uint64_t SH_FLD_TP_FENCE_PCB = 17946; // 43 -static const uint64_t SH_FLD_TP_FENCE_PCB_DC = 17947; // 3 -static const uint64_t SH_FLD_TP_FILT0_PLL_BYPASS = 17948; // 3 -static const uint64_t SH_FLD_TP_FILT0_PLL_RESET = 17949; // 3 -static const uint64_t SH_FLD_TP_FILT0_PLL_TEST_EN = 17950; // 3 -static const uint64_t SH_FLD_TP_FILT1_PLL_BYPASS = 17951; // 3 -static const uint64_t SH_FLD_TP_FILT1_PLL_RESET = 17952; // 3 -static const uint64_t SH_FLD_TP_FILT1_PLL_TEST_EN = 17953; // 3 -static const uint64_t SH_FLD_TP_FLUSH_ALIGN_OVERWRITE = 17954; // 3 -static const uint64_t SH_FLD_TP_FLUSH_SCAN_DC_N = 17955; // 3 -static const uint64_t SH_FLD_TP_FSI_CLKIN_SEL_DC = 17956; // 3 -static const uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC = 17957; // 3 -static const uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC_LEN = 17958; // 3 -static const uint64_t SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC = 17959; // 3 -static const uint64_t SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 17960; // 3 -static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 17961; // 3 -static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 17962; // 3 -static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 17963; // 3 -static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 17964; // 3 -static const uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT = 17965; // 3 -static const uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN = 17966; // 3 -static const uint64_t SH_FLD_TP_IDDQ_DC = 17967; // 3 -static const uint64_t SH_FLD_TP_IO_SPARE2_MCPRECOMP = 17968; // 1 -static const uint64_t SH_FLD_TP_IO_SPARE2_MCPRECOMP_LEN = 17969; // 1 -static const uint64_t SH_FLD_TP_IO_SPARE3_MCPRECOMP = 17970; // 1 -static const uint64_t SH_FLD_TP_IO_SPARE3_MCPRECOMP_LEN = 17971; // 1 -static const uint64_t SH_FLD_TP_IO_SPI_APSS_MCPRECOMP = 17972; // 1 -static const uint64_t SH_FLD_TP_IO_SPI_APSS_MCPRECOMP_LEN = 17973; // 1 -static const uint64_t SH_FLD_TP_IO_VSB_OP0A_V1P8_EN = 17974; // 3 -static const uint64_t SH_FLD_TP_IO_VSB_OP0B_V1P8_EN = 17975; // 3 -static const uint64_t SH_FLD_TP_IO_VSB_OP3A_V1P8_EN = 17976; // 3 -static const uint64_t SH_FLD_TP_IO_VSB_OP3B_V1P8_EN = 17977; // 3 -static const uint64_t SH_FLD_TP_LVLTRANS_FENCE_DC = 17978; // 3 -static const uint64_t SH_FLD_TP_NX_ALLOW_CRYPTO_DC = 17979; // 1 -static const uint64_t SH_FLD_TP_OSCSWITCH_VSB = 17980; // 3 -static const uint64_t SH_FLD_TP_OSCSWITCH_VSB_LEN = 17981; // 3 -static const uint64_t SH_FLD_TP_PB_FUSE_SPARE = 17982; // 1 -static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_2CHIP = 17983; // 1 -static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP = 17984; // 1 -static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN = 17985; // 1 -static const uint64_t SH_FLD_TP_PCB_EP_RESET_DC = 17986; // 3 -static const uint64_t SH_FLD_TP_PCB_PM_MUX_SEL_DC = 17987; // 3 -static const uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC = 17988; // 3 -static const uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 17989; // 3 -static const uint64_t SH_FLD_TP_PIB_TRACE_MODE_DATA_DC = 17990; // 3 -static const uint64_t SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC = 17991; // 3 -static const uint64_t SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE = 17992; // 3 -static const uint64_t SH_FLD_TP_PLLBYP_DC = 17993; // 3 -static const uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC = 17994; // 3 -static const uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 17995; // 3 -static const uint64_t SH_FLD_TP_PLLRST_DC = 17996; // 3 -static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL1_DC = 17997; // 3 -static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL2_DC = 17998; // 3 -static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL3_DC = 17999; // 3 -static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL4_DC = 18000; // 3 -static const uint64_t SH_FLD_TP_PLL_FORCE_OUT_EN_DC = 18001; // 3 -static const uint64_t SH_FLD_TP_PLL_TEST_EN = 18002; // 3 -static const uint64_t SH_FLD_TP_PLL_TEST_EN_DC = 18003; // 3 -static const uint64_t SH_FLD_TP_PROBE0_SEL_DC = 18004; // 3 -static const uint64_t SH_FLD_TP_PROBE0_SEL_DC_LEN = 18005; // 3 -static const uint64_t SH_FLD_TP_PROBE1_SEL_DC = 18006; // 3 -static const uint64_t SH_FLD_TP_PROBE1_SEL_DC_LEN = 18007; // 3 -static const uint64_t SH_FLD_TP_PROBE_DRV_EN_DC = 18008; // 3 -static const uint64_t SH_FLD_TP_PROBE_HIGHDRIVE_DC = 18009; // 3 -static const uint64_t SH_FLD_TP_PROBE_MESH_SEL_DC = 18010; // 3 -static const uint64_t SH_FLD_TP_RESCLK_DIS_DC = 18011; // 3 -static const uint64_t SH_FLD_TP_RI_DC_B = 18012; // 3 -static const uint64_t SH_FLD_TP_RI_DC_N = 18013; // 3 -static const uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC = 18014; // 3 -static const uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 18015; // 3 -static const uint64_t SH_FLD_TP_SS0_PLL_BYPASS = 18016; // 3 -static const uint64_t SH_FLD_TP_SS0_PLL_RESET = 18017; // 3 -static const uint64_t SH_FLD_TP_SS0_PLL_TEST_EN = 18018; // 3 -static const uint64_t SH_FLD_TP_TEST_BURNIN_MODE_DC = 18019; // 3 -static const uint64_t SH_FLD_TP_TPCPERV_VSB_TRACE_STOP = 18020; // 3 -static const uint64_t SH_FLD_TP_TPFSI_ACK = 18021; // 43 -static const uint64_t SH_FLD_TP_VITL_ACT_DIS_DC = 18022; // 3 -static const uint64_t SH_FLD_TP_VITL_CLKOFF_DC = 18023; // 3 -static const uint64_t SH_FLD_TP_VITL_DELAY_LCLKR_DC = 18024; // 3 -static const uint64_t SH_FLD_TP_VITL_MPW1_DC_N = 18025; // 3 -static const uint64_t SH_FLD_TP_VITL_MPW2_DC_N = 18026; // 3 -static const uint64_t SH_FLD_TP_VITL_MPW3_DC_N = 18027; // 3 -static const uint64_t SH_FLD_TP_VITL_SCAN_CLK_DC = 18028; // 3 -static const uint64_t SH_FLD_TP_VITL_SCIN_DC = 18029; // 3 -static const uint64_t SH_FLD_TRACE_BUS_BITS_0_63 = 18030; // 1 -static const uint64_t SH_FLD_TRACE_BUS_BITS_0_63_LEN = 18031; // 1 -static const uint64_t SH_FLD_TRACE_BUS_BITS_64_87 = 18032; // 1 -static const uint64_t SH_FLD_TRACE_BUS_BITS_64_87_LEN = 18033; // 1 -static const uint64_t SH_FLD_TRACE_BUS_EN = 18034; // 1 -static const uint64_t SH_FLD_TRACE_BUS_SEL_0_1 = 18035; // 1 -static const uint64_t SH_FLD_TRACE_BUS_SEL_0_1_LEN = 18036; // 1 -static const uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS = 18037; // 1 -static const uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN = 18038; // 1 -static const uint64_t SH_FLD_TRACE_DATA_SEL = 18039; // 16 -static const uint64_t SH_FLD_TRACE_DATA_SELECT = 18040; // 1 -static const uint64_t SH_FLD_TRACE_DATA_SELECT_LEN = 18041; // 1 -static const uint64_t SH_FLD_TRACE_DATA_SEL_LEN = 18042; // 16 -static const uint64_t SH_FLD_TRACE_DISABLE = 18043; // 1 -static const uint64_t SH_FLD_TRACE_ENABLE = 18044; // 7 -static const uint64_t SH_FLD_TRACE_EVENT = 18045; // 1 -static const uint64_t SH_FLD_TRACE_MODE_SEL = 18046; // 16 -static const uint64_t SH_FLD_TRACE_MODE_SEL_LEN = 18047; // 16 -static const uint64_t SH_FLD_TRACE_MUX_SEL = 18048; // 1 -static const uint64_t SH_FLD_TRACE_SEL = 18049; // 87 -static const uint64_t SH_FLD_TRACE_SELECT = 18050; // 2 -static const uint64_t SH_FLD_TRACE_SELECT_LEN = 18051; // 2 -static const uint64_t SH_FLD_TRACE_SEL_0_1 = 18052; // 1 -static const uint64_t SH_FLD_TRACE_SEL_0_1_LEN = 18053; // 1 -static const uint64_t SH_FLD_TRACE_SEL_LEN = 18054; // 44 -static const uint64_t SH_FLD_TRACE_TRIGGER = 18055; // 1 -static const uint64_t SH_FLD_TRACKING_TIMEOUT_SEL = 18056; // 6 -static const uint64_t SH_FLD_TRACKING_TIMEOUT_SEL_LEN = 18057; // 6 -static const uint64_t SH_FLD_TRAIN = 18058; // 10 -static const uint64_t SH_FLD_TRAIN_A_ADJ = 18059; // 2 -static const uint64_t SH_FLD_TRAIN_A_ADJ_LEN = 18060; // 2 -static const uint64_t SH_FLD_TRAIN_A_HYST = 18061; // 2 -static const uint64_t SH_FLD_TRAIN_A_HYST_LEN = 18062; // 2 -static const uint64_t SH_FLD_TRAIN_B_ADJ = 18063; // 2 -static const uint64_t SH_FLD_TRAIN_B_ADJ_LEN = 18064; // 2 -static const uint64_t SH_FLD_TRAIN_B_HYST = 18065; // 2 -static const uint64_t SH_FLD_TRAIN_B_HYST_LEN = 18066; // 2 -static const uint64_t SH_FLD_TRAIN_LEN = 18067; // 10 -static const uint64_t SH_FLD_TRAIN_TIME = 18068; // 2 -static const uint64_t SH_FLD_TRAIN_TIME_LEN = 18069; // 2 -static const uint64_t SH_FLD_TRANSPORT_INFORMATIONAL_ERR = 18070; // 4 -static const uint64_t SH_FLD_TRANS_DELAY = 18071; // 1 -static const uint64_t SH_FLD_TRANS_DELAY_LEN = 18072; // 1 -static const uint64_t SH_FLD_TRAPPED_DL_RETURN_P0 = 18073; // 43 -static const uint64_t SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY = 18074; // 43 -static const uint64_t SH_FLD_TRAPPED_GENERAL_TIMEOUT = 18075; // 43 -static const uint64_t SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID = 18076; // 43 -static const uint64_t SH_FLD_TRAPPED_PARALLEL_READ_NVLD = 18077; // 43 -static const uint64_t SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD = 18078; // 43 -static const uint64_t SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 18079; // 43 -static const uint64_t SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE = 18080; // 43 -static const uint64_t SH_FLD_TRAPPED_PCB_ADDRESS_PARITY = 18081; // 43 -static const uint64_t SH_FLD_TRAPPED_PCB_COMMAND_PARITY = 18082; // 43 -static const uint64_t SH_FLD_TRAPPED_PCB_WDATA_PARITY = 18083; // 43 -static const uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 18084; // 43 -static const uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 18085; // 43 -static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 18086; // 43 -static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 18087; // 43 -static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 18088; // 43 -static const uint64_t SH_FLD_TRAPPED_UL_P0 = 18089; // 43 -static const uint64_t SH_FLD_TRAPPED_UL_RDATA_PARITY = 18090; // 43 -static const uint64_t SH_FLD_TRASH_EN = 18091; // 12 -static const uint64_t SH_FLD_TRCD_CYCLES = 18092; // 8 -static const uint64_t SH_FLD_TRCD_CYCLES_LEN = 18093; // 8 -static const uint64_t SH_FLD_TRC_CMD_OVERRUN = 18094; // 1 -static const uint64_t SH_FLD_TRC_CYCLES = 18095; // 8 -static const uint64_t SH_FLD_TRC_CYCLES_LEN = 18096; // 8 -static const uint64_t SH_FLD_TRC_MODE = 18097; // 6 -static const uint64_t SH_FLD_TRC_MODE_LEN = 18098; // 6 -static const uint64_t SH_FLD_TRFC_CYCLES = 18099; // 8 -static const uint64_t SH_FLD_TRFC_CYCLES_LEN = 18100; // 8 -static const uint64_t SH_FLD_TRIG = 18101; // 17 -static const uint64_t SH_FLD_TRIG0_AND_MASK = 18102; // 90 -static const uint64_t SH_FLD_TRIG0_AND_MASK_LEN = 18103; // 90 -static const uint64_t SH_FLD_TRIG0_LEVEL_SEL = 18104; // 43 -static const uint64_t SH_FLD_TRIG0_LEVEL_SEL_LEN = 18105; // 43 -static const uint64_t SH_FLD_TRIG0_NOT_MODE = 18106; // 90 -static const uint64_t SH_FLD_TRIG0_OR_MASK = 18107; // 90 -static const uint64_t SH_FLD_TRIG0_OR_MASK_LEN = 18108; // 90 -static const uint64_t SH_FLD_TRIG1_AND_MASK = 18109; // 90 -static const uint64_t SH_FLD_TRIG1_AND_MASK_LEN = 18110; // 90 -static const uint64_t SH_FLD_TRIG1_LEVEL_SEL = 18111; // 43 -static const uint64_t SH_FLD_TRIG1_LEVEL_SEL_LEN = 18112; // 43 -static const uint64_t SH_FLD_TRIG1_NOT_MODE = 18113; // 90 -static const uint64_t SH_FLD_TRIG1_OR_MASK = 18114; // 90 -static const uint64_t SH_FLD_TRIG1_OR_MASK_LEN = 18115; // 90 -static const uint64_t SH_FLD_TRIGGER = 18116; // 55 -static const uint64_t SH_FLD_TRIGGER1 = 18117; // 24 -static const uint64_t SH_FLD_TRIGGERED = 18118; // 1 -static const uint64_t SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL = 18119; // 43 -static const uint64_t SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL = 18120; // 43 -static const uint64_t SH_FLD_TRIGGER_OPCG_ON = 18121; // 129 -static const uint64_t SH_FLD_TRIG_FIR_HMI = 18122; // 96 -static const uint64_t SH_FLD_TRIG_SEL = 18123; // 86 -static const uint64_t SH_FLD_TRP_CYCLES = 18124; // 8 -static const uint64_t SH_FLD_TRP_CYCLES_LEN = 18125; // 8 -static const uint64_t SH_FLD_TRRD = 18126; // 8 -static const uint64_t SH_FLD_TRRD_LEN = 18127; // 8 -static const uint64_t SH_FLD_TRRD_SBG = 18128; // 8 -static const uint64_t SH_FLD_TRRD_SBG_LEN = 18129; // 8 -static const uint64_t SH_FLD_TRST_B_EQ0_ERR = 18130; // 1 -static const uint64_t SH_FLD_TRY_ATR_RO = 18131; // 1 -static const uint64_t SH_FLD_TSIZE = 18132; // 25 -static const uint64_t SH_FLD_TSIZE_4_6 = 18133; // 1 -static const uint64_t SH_FLD_TSIZE_4_6_LEN = 18134; // 1 -static const uint64_t SH_FLD_TSIZE_LEN = 18135; // 24 -static const uint64_t SH_FLD_TSIZE_MASK = 18136; // 8 -static const uint64_t SH_FLD_TSIZE_MASK_LEN = 18137; // 8 -static const uint64_t SH_FLD_TSIZE_MATCH = 18138; // 8 -static const uint64_t SH_FLD_TSIZE_MATCH_LEN = 18139; // 8 -static const uint64_t SH_FLD_TTAG_PARITY = 18140; // 2 -static const uint64_t SH_FLD_TTAG_PARITY_ERROR = 18141; // 2 -static const uint64_t SH_FLD_TTYPE = 18142; // 24 -static const uint64_t SH_FLD_TTYPE_LEN = 18143; // 24 -static const uint64_t SH_FLD_TTYPE_MATCH = 18144; // 8 -static const uint64_t SH_FLD_TTYPE_MATCH_LEN = 18145; // 8 -static const uint64_t SH_FLD_TTYPE_REPLACE = 18146; // 8 -static const uint64_t SH_FLD_TTYPE_REPLACE_LEN = 18147; // 8 -static const uint64_t SH_FLD_TVT0_PAGE_SIZE = 18148; // 1 -static const uint64_t SH_FLD_TVT0_PAGE_SIZE_LEN = 18149; // 1 -static const uint64_t SH_FLD_TVT0_SPARE = 18150; // 1 -static const uint64_t SH_FLD_TVT0_SPARE_LEN = 18151; // 1 -static const uint64_t SH_FLD_TVT0_TABLE_LEVEL = 18152; // 1 -static const uint64_t SH_FLD_TVT0_TABLE_LEVEL_LEN = 18153; // 1 -static const uint64_t SH_FLD_TVT0_TABLE_SIZE = 18154; // 1 -static const uint64_t SH_FLD_TVT0_TABLE_SIZE_LEN = 18155; // 1 -static const uint64_t SH_FLD_TVT0_XLAT_ADDR = 18156; // 1 -static const uint64_t SH_FLD_TVT0_XLAT_ADDR_LEN = 18157; // 1 -static const uint64_t SH_FLD_TVT_ADDR_RANGE_ERR_ESR = 18158; // 1 -static const uint64_t SH_FLD_TVT_ENTRY_INVALID_ESR = 18159; // 1 -static const uint64_t SH_FLD_TVT_PERR_ESR = 18160; // 1 -static const uint64_t SH_FLD_TWLDQSEN_CYCLES = 18161; // 8 -static const uint64_t SH_FLD_TWLDQSEN_CYCLES_LEN = 18162; // 8 -static const uint64_t SH_FLD_TWLO_TWLOE = 18163; // 8 -static const uint64_t SH_FLD_TWLO_TWLOE_LEN = 18164; // 8 -static const uint64_t SH_FLD_TWO_CYCLE_ADDR_EN = 18165; // 8 -static const uint64_t SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD = 18166; // 2 -static const uint64_t SH_FLD_TWRMRD_CYCLES = 18167; // 8 -static const uint64_t SH_FLD_TWRMRD_CYCLES_LEN = 18168; // 8 -static const uint64_t SH_FLD_TWSM_DIS = 18169; // 1 -static const uint64_t SH_FLD_TWSM_DIS_LEN = 18170; // 1 -static const uint64_t SH_FLD_TW_ADD_ERR_CR_RD_DET = 18171; // 1 -static const uint64_t SH_FLD_TW_ADD_ERR_CR_WR_DET = 18172; // 1 -static const uint64_t SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS = 18173; // 1 -static const uint64_t SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS = 18174; // 1 -static const uint64_t SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS = 18175; // 1 -static const uint64_t SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS = 18176; // 1 -static const uint64_t SH_FLD_TW_BUS0_STG0_SEL = 18177; // 1 -static const uint64_t SH_FLD_TW_BUS0_STG0_SEL_LEN = 18178; // 1 -static const uint64_t SH_FLD_TW_BUS0_STG1_SEL = 18179; // 1 -static const uint64_t SH_FLD_TW_BUS0_STG2_SEL = 18180; // 1 -static const uint64_t SH_FLD_TW_BUS1_STG0_SEL = 18181; // 1 -static const uint64_t SH_FLD_TW_BUS1_STG0_SEL_LEN = 18182; // 1 -static const uint64_t SH_FLD_TW_BUS1_STG1_SEL = 18183; // 1 -static const uint64_t SH_FLD_TW_BUS1_STG2_SEL = 18184; // 1 -static const uint64_t SH_FLD_TW_CXT_CAC_DIS = 18185; // 1 -static const uint64_t SH_FLD_TW_CXT_CAC_PERR_DET = 18186; // 1 -static const uint64_t SH_FLD_TW_FOREIGN_ADDR_DET = 18187; // 1 -static const uint64_t SH_FLD_TW_INVALID_WIMG_DET = 18188; // 1 -static const uint64_t SH_FLD_TW_INV_RDX_QUAD_DET = 18189; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_C_DIS = 18190; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_EN = 18191; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_PDE_EN = 18192; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L2_DIS = 18193; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L3_DIS = 18194; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L4_DIS = 18195; // 1 -static const uint64_t SH_FLD_TW_LCO_RDX_P_DIS = 18196; // 1 -static const uint64_t SH_FLD_TW_MPSS_DIS = 18197; // 1 -static const uint64_t SH_FLD_TW_PG_FAULT_BPCHK_DET = 18198; // 1 -static const uint64_t SH_FLD_TW_PG_FAULT_NOPTE_DET = 18199; // 1 -static const uint64_t SH_FLD_TW_PG_FAULT_SEID_DET = 18200; // 1 -static const uint64_t SH_FLD_TW_PG_FAULT_VPCHK_DET = 18201; // 1 -static const uint64_t SH_FLD_TW_PREFETCH_ABT_DET = 18202; // 1 -static const uint64_t SH_FLD_TW_PROT_ERR_CHK_DIS = 18203; // 1 -static const uint64_t SH_FLD_TW_PTE_UPD_FAIL_DET = 18204; // 1 -static const uint64_t SH_FLD_TW_PTE_UPD_INTR_EN = 18205; // 1 -static const uint64_t SH_FLD_TW_RDX_CFG_GUEST_DET = 18206; // 1 -static const uint64_t SH_FLD_TW_RDX_CFG_HOST_DET = 18207; // 1 -static const uint64_t SH_FLD_TW_RDX_INT_PWC_DIS = 18208; // 1 -static const uint64_t SH_FLD_TW_RDX_INT_TLB_DIS = 18209; // 1 -static const uint64_t SH_FLD_TW_RDX_PWC_DIS = 18210; // 1 -static const uint64_t SH_FLD_TW_RDX_PWC_PERR_DET = 18211; // 1 -static const uint64_t SH_FLD_TW_RDX_PWC_SPLIT_EN = 18212; // 1 -static const uint64_t SH_FLD_TW_RDX_PWC_VA_HASH = 18213; // 1 -static const uint64_t SH_FLD_TW_SEG_FAULT_DET = 18214; // 1 -static const uint64_t SH_FLD_TW_SM_CTL_ERR_DET = 18215; // 1 -static const uint64_t SH_FLD_TW_TIMEOUT_CHK_DIS = 18216; // 1 -static const uint64_t SH_FLD_TW_TIMEOUT_ERR_DET = 18217; // 1 -static const uint64_t SH_FLD_TXAERR = 18218; // 6 -static const uint64_t SH_FLD_TXBERR = 18219; // 6 -static const uint64_t SH_FLD_TXCERR = 18220; // 6 -static const uint64_t SH_FLD_TXDERR = 18221; // 6 -static const uint64_t SH_FLD_TXEERR = 18222; // 6 -static const uint64_t SH_FLD_TXFERR = 18223; // 6 -static const uint64_t SH_FLD_TXGERR = 18224; // 6 -static const uint64_t SH_FLD_TXHERR = 18225; // 6 -static const uint64_t SH_FLD_TXIERR = 18226; // 6 -static const uint64_t SH_FLD_TXJERR = 18227; // 6 -static const uint64_t SH_FLD_TXKERR = 18228; // 6 -static const uint64_t SH_FLD_TXLERR = 18229; // 6 -static const uint64_t SH_FLD_TXMERR = 18230; // 6 -static const uint64_t SH_FLD_TXNERR = 18231; // 6 -static const uint64_t SH_FLD_TXOERR = 18232; // 6 -static const uint64_t SH_FLD_TXPERR = 18233; // 6 -static const uint64_t SH_FLD_TX_BUS_WIDTH = 18234; // 4 -static const uint64_t SH_FLD_TX_BUS_WIDTH_LEN = 18235; // 4 -static const uint64_t SH_FLD_TX_BW = 18236; // 10 -static const uint64_t SH_FLD_TX_BW_LEN = 18237; // 10 -static const uint64_t SH_FLD_TX_DATA_ECC_CORR_ENA = 18238; // 6 -static const uint64_t SH_FLD_TX_ECC_DATA_POISON_ENA = 18239; // 6 -static const uint64_t SH_FLD_TX_SLS_DISABLE = 18240; // 4 -static const uint64_t SH_FLD_TX_TFMR_CORRUPT_ERRHOLD = 18241; // 2 -static const uint64_t SH_FLD_TX_TRISTATE = 18242; // 8 -static const uint64_t SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 18243; // 1 -static const uint64_t SH_FLD_TX_TTYPE_PIB_MST_IF_RESET = 18244; // 1 -static const uint64_t SH_FLD_TYPE = 18245; // 108 -static const uint64_t SH_FLD_TYPE_LEN = 18246; // 44 -static const uint64_t SH_FLD_TZQCS_CYCLES = 18247; // 8 -static const uint64_t SH_FLD_TZQCS_CYCLES_LEN = 18248; // 8 -static const uint64_t SH_FLD_TZQINIT_CYCLES = 18249; // 8 -static const uint64_t SH_FLD_TZQINIT_CYCLES_LEN = 18250; // 8 -static const uint64_t SH_FLD_UE = 18251; // 10 -static const uint64_t SH_FLD_UE1_0_OUT = 18252; // 4 -static const uint64_t SH_FLD_UE1_1_OUT = 18253; // 4 -static const uint64_t SH_FLD_UE1_2_OUT = 18254; // 4 -static const uint64_t SH_FLD_UE1_3_OUT = 18255; // 4 -static const uint64_t SH_FLD_UE1_4_OUT = 18256; // 4 -static const uint64_t SH_FLD_UE1_5_OUT = 18257; // 4 -static const uint64_t SH_FLD_UE1_6_OUT = 18258; // 4 -static const uint64_t SH_FLD_UE1_7_OUT = 18259; // 4 -static const uint64_t SH_FLD_UE2_0_OUT = 18260; // 4 -static const uint64_t SH_FLD_UE2_1_OUT = 18261; // 4 -static const uint64_t SH_FLD_UE2_2_OUT = 18262; // 4 -static const uint64_t SH_FLD_UE2_3_OUT = 18263; // 4 -static const uint64_t SH_FLD_UE2_4_OUT = 18264; // 4 -static const uint64_t SH_FLD_UE2_5_OUT = 18265; // 4 -static const uint64_t SH_FLD_UE2_6_OUT = 18266; // 4 -static const uint64_t SH_FLD_UE2_7_OUT = 18267; // 4 -static const uint64_t SH_FLD_UE_COUNT = 18268; // 2 -static const uint64_t SH_FLD_UE_COUNT_LEN = 18269; // 2 -static const uint64_t SH_FLD_UE_DISABLE = 18270; // 2 -static const uint64_t SH_FLD_UE_LEN = 18271; // 10 -static const uint64_t SH_FLD_UL_P0 = 18272; // 43 -static const uint64_t SH_FLD_UL_RDATA_PARITY = 18273; // 43 -static const uint64_t SH_FLD_UMAC_CRB_SUE = 18274; // 1 -static const uint64_t SH_FLD_UMAC_CRB_UE = 18275; // 1 -static const uint64_t SH_FLD_UMAC_LD_LINK_ERR = 18276; // 1 -static const uint64_t SH_FLD_UMAC_LINK_ABORT = 18277; // 1 -static const uint64_t SH_FLD_UMAC_MUX_SELECT = 18278; // 1 -static const uint64_t SH_FLD_UMAC_MUX_SELECT_LEN = 18279; // 1 -static const uint64_t SH_FLD_UMAC_RD_DISABLE_GROUP = 18280; // 1 -static const uint64_t SH_FLD_UMAC_RD_DISABLE_LN = 18281; // 1 -static const uint64_t SH_FLD_UMAC_RD_DISABLE_NN_RN = 18282; // 1 -static const uint64_t SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS = 18283; // 1 -static const uint64_t SH_FLD_UMAC_WC_INT_ADDR_UE = 18284; // 1 -static const uint64_t SH_FLD_UMAC_WR_DISABLE_GROUP = 18285; // 1 -static const uint64_t SH_FLD_UMAC_WR_DISABLE_LN = 18286; // 1 -static const uint64_t SH_FLD_UMAC_WR_DISABLE_NN_RN = 18287; // 1 -static const uint64_t SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS = 18288; // 1 -static const uint64_t SH_FLD_UNCORR_ERROR = 18289; // 1 -static const uint64_t SH_FLD_UNEXPECTED_PB = 18290; // 4 -static const uint64_t SH_FLD_UNEXPECT_DATA = 18291; // 1 -static const uint64_t SH_FLD_UNIT1 = 18292; // 215 -static const uint64_t SH_FLD_UNIT10 = 18293; // 215 -static const uint64_t SH_FLD_UNIT2 = 18294; // 215 -static const uint64_t SH_FLD_UNIT3 = 18295; // 215 -static const uint64_t SH_FLD_UNIT4 = 18296; // 215 -static const uint64_t SH_FLD_UNIT5 = 18297; // 215 -static const uint64_t SH_FLD_UNIT6 = 18298; // 215 -static const uint64_t SH_FLD_UNIT7 = 18299; // 215 -static const uint64_t SH_FLD_UNIT8 = 18300; // 215 -static const uint64_t SH_FLD_UNIT9 = 18301; // 215 -static const uint64_t SH_FLD_UNIT_REGION_CLKCMD_DISABLE = 18302; // 43 -static const uint64_t SH_FLD_UNLOAD_CLK_DISABLE = 18303; // 116 -static const uint64_t SH_FLD_UNLOAD_SEL = 18304; // 116 -static const uint64_t SH_FLD_UNLOAD_SEL_LEN = 18305; // 116 -static const uint64_t SH_FLD_UNRECOV = 18306; // 10 -static const uint64_t SH_FLD_UNRECOV_LEN = 18307; // 10 -static const uint64_t SH_FLD_UNSOLICITED_CRESP = 18308; // 3 -static const uint64_t SH_FLD_UNSOLICITED_DATA_RCV_ERRHOLD = 18309; // 2 -static const uint64_t SH_FLD_UNSOLICITED_PBDATA = 18310; // 1 -static const uint64_t SH_FLD_UNTRUSTED = 18311; // 4 -static const uint64_t SH_FLD_UNTRUSTED_LEN = 18312; // 4 -static const uint64_t SH_FLD_UNUSED = 18313; // 351 -static const uint64_t SH_FLD_UNUSED0 = 18314; // 3 -static const uint64_t SH_FLD_UNUSED0A = 18315; // 3 -static const uint64_t SH_FLD_UNUSED0B = 18316; // 3 -static const uint64_t SH_FLD_UNUSED0B_LEN = 18317; // 3 -static const uint64_t SH_FLD_UNUSED0_LEN = 18318; // 2 -static const uint64_t SH_FLD_UNUSED1 = 18319; // 55 -static const uint64_t SH_FLD_UNUSED1119 = 18320; // 43 -static const uint64_t SH_FLD_UNUSED1119_LEN = 18321; // 43 -static const uint64_t SH_FLD_UNUSED1520 = 18322; // 43 -static const uint64_t SH_FLD_UNUSED1520_LEN = 18323; // 43 -static const uint64_t SH_FLD_UNUSED1A = 18324; // 3 -static const uint64_t SH_FLD_UNUSED1B = 18325; // 3 -static const uint64_t SH_FLD_UNUSED1B_LEN = 18326; // 3 -static const uint64_t SH_FLD_UNUSED1_LEN = 18327; // 52 -static const uint64_t SH_FLD_UNUSED2 = 18328; // 55 -static const uint64_t SH_FLD_UNUSED23_31 = 18329; // 7 -static const uint64_t SH_FLD_UNUSED23_31_LEN = 18330; // 7 -static const uint64_t SH_FLD_UNUSED2_LEN = 18331; // 44 -static const uint64_t SH_FLD_UNUSED3 = 18332; // 11 -static const uint64_t SH_FLD_UNUSED3_LEN = 18333; // 6 -static const uint64_t SH_FLD_UNUSED4 = 18334; // 14 -static const uint64_t SH_FLD_UNUSED41_63 = 18335; // 43 -static const uint64_t SH_FLD_UNUSED41_63_LEN = 18336; // 43 -static const uint64_t SH_FLD_UNUSED46 = 18337; // 43 -static const uint64_t SH_FLD_UNUSED4_LEN = 18338; // 6 -static const uint64_t SH_FLD_UNUSED5 = 18339; // 12 -static const uint64_t SH_FLD_UNUSED50 = 18340; // 2 -static const uint64_t SH_FLD_UNUSED51 = 18341; // 2 -static const uint64_t SH_FLD_UNUSED5_LEN = 18342; // 5 -static const uint64_t SH_FLD_UNUSED63 = 18343; // 3 -static const uint64_t SH_FLD_UNUSED88 = 18344; // 3 -static const uint64_t SH_FLD_UNUSED88_LEN = 18345; // 3 -static const uint64_t SH_FLD_UNUSED_0 = 18346; // 44 -static const uint64_t SH_FLD_UNUSED_0B = 18347; // 43 -static const uint64_t SH_FLD_UNUSED_0D = 18348; // 17 -static const uint64_t SH_FLD_UNUSED_1 = 18349; // 44 -static const uint64_t SH_FLD_UNUSED_10B = 18350; // 17 -static const uint64_t SH_FLD_UNUSED_11B = 18351; // 18 -static const uint64_t SH_FLD_UNUSED_12B = 18352; // 19 -static const uint64_t SH_FLD_UNUSED_13B = 18353; // 19 -static const uint64_t SH_FLD_UNUSED_14B = 18354; // 43 -static const uint64_t SH_FLD_UNUSED_16_22 = 18355; // 1 -static const uint64_t SH_FLD_UNUSED_16_22_LEN = 18356; // 1 -static const uint64_t SH_FLD_UNUSED_17B = 18357; // 43 -static const uint64_t SH_FLD_UNUSED_18B = 18358; // 43 -static const uint64_t SH_FLD_UNUSED_19B = 18359; // 43 -static const uint64_t SH_FLD_UNUSED_1B = 18360; // 43 -static const uint64_t SH_FLD_UNUSED_1D = 18361; // 17 -static const uint64_t SH_FLD_UNUSED_2 = 18362; // 87 -static const uint64_t SH_FLD_UNUSED_20B = 18363; // 42 -static const uint64_t SH_FLD_UNUSED_21B = 18364; // 43 -static const uint64_t SH_FLD_UNUSED_22B = 18365; // 43 -static const uint64_t SH_FLD_UNUSED_23B = 18366; // 43 -static const uint64_t SH_FLD_UNUSED_24B = 18367; // 43 -static const uint64_t SH_FLD_UNUSED_25B = 18368; // 43 -static const uint64_t SH_FLD_UNUSED_26B = 18369; // 43 -static const uint64_t SH_FLD_UNUSED_26_31 = 18370; // 1 -static const uint64_t SH_FLD_UNUSED_26_31_LEN = 18371; // 1 -static const uint64_t SH_FLD_UNUSED_27B = 18372; // 43 -static const uint64_t SH_FLD_UNUSED_28B = 18373; // 43 -static const uint64_t SH_FLD_UNUSED_29B = 18374; // 43 -static const uint64_t SH_FLD_UNUSED_2B = 18375; // 43 -static const uint64_t SH_FLD_UNUSED_2D = 18376; // 17 -static const uint64_t SH_FLD_UNUSED_2_LEN = 18377; // 86 -static const uint64_t SH_FLD_UNUSED_3 = 18378; // 1 -static const uint64_t SH_FLD_UNUSED_30B = 18379; // 43 -static const uint64_t SH_FLD_UNUSED_31B = 18380; // 43 -static const uint64_t SH_FLD_UNUSED_39_43 = 18381; // 1 -static const uint64_t SH_FLD_UNUSED_39_43_LEN = 18382; // 1 -static const uint64_t SH_FLD_UNUSED_3D = 18383; // 17 -static const uint64_t SH_FLD_UNUSED_47_51 = 18384; // 1 -static const uint64_t SH_FLD_UNUSED_47_51_LEN = 18385; // 1 -static const uint64_t SH_FLD_UNUSED_4_15 = 18386; // 1 -static const uint64_t SH_FLD_UNUSED_4_15_LEN = 18387; // 1 -static const uint64_t SH_FLD_UNUSED_53 = 18388; // 1 -static const uint64_t SH_FLD_UNUSED_5B = 18389; // 7 -static const uint64_t SH_FLD_UNUSED_6B = 18390; // 7 -static const uint64_t SH_FLD_UNUSED_7B = 18391; // 7 -static const uint64_t SH_FLD_UNUSED_8B = 18392; // 12 -static const uint64_t SH_FLD_UNUSED_8_14 = 18393; // 1 -static const uint64_t SH_FLD_UNUSED_8_14_LEN = 18394; // 1 -static const uint64_t SH_FLD_UNUSED_9B = 18395; // 15 -static const uint64_t SH_FLD_UNUSED_LEN = 18396; // 178 -static const uint64_t SH_FLD_UPDATE_COMPLETE = 18397; // 6 -static const uint64_t SH_FLD_UPDATE_ERR = 18398; // 2 -static const uint64_t SH_FLD_UPSTREAM = 18399; // 4 -static const uint64_t SH_FLD_USERDEF_CFG = 18400; // 6 -static const uint64_t SH_FLD_USERDEF_CFG_LEN = 18401; // 6 -static const uint64_t SH_FLD_USERDEF_TIMEOUT = 18402; // 6 -static const uint64_t SH_FLD_USERDEF_TIMEOUT_LEN = 18403; // 6 -static const uint64_t SH_FLD_USER_FILTER_MASK = 18404; // 6 -static const uint64_t SH_FLD_USER_FILTER_MASK_LEN = 18405; // 6 -static const uint64_t SH_FLD_USE_FOR_SCAN = 18406; // 43 -static const uint64_t SH_FLD_USE_OSC_OBSERVATION = 18407; // 1 -static const uint64_t SH_FLD_USE_OSC_OBSERVATION_LEN = 18408; // 1 -static const uint64_t SH_FLD_USE_PECE = 18409; // 24 -static const uint64_t SH_FLD_USE_PECE_LEN = 18410; // 24 -static const uint64_t SH_FLD_USE_PREV_COARSE_VAL = 18411; // 4 -static const uint64_t SH_FLD_USE_REC_LIMIT = 18412; // 24 -static const uint64_t SH_FLD_USE_SLS_AS_SPR = 18413; // 4 -static const uint64_t SH_FLD_USE_TB_STEP_SYNC = 18414; // 1 -static const uint64_t SH_FLD_USE_TB_SYNC_MECHANISM = 18415; // 1 -static const uint64_t SH_FLD_USE_WATCH_TO_READ_CTRL_ARY = 18416; // 2 -static const uint64_t SH_FLD_UT = 18417; // 24 -static const uint64_t SH_FLD_VALID = 18418; // 68 -static const uint64_t SH_FLD_VALID_ATRGPA0 = 18419; // 256 -static const uint64_t SH_FLD_VALID_ATRGPA1 = 18420; // 256 -static const uint64_t SH_FLD_VALID_ATSD = 18421; // 256 -static const uint64_t SH_FLD_VALID_ENTRY = 18422; // 1 -static const uint64_t SH_FLD_VALUE = 18423; // 48 -static const uint64_t SH_FLD_VALUES0 = 18424; // 16 -static const uint64_t SH_FLD_VALUES0_LEN = 18425; // 16 -static const uint64_t SH_FLD_VALUES1 = 18426; // 16 -static const uint64_t SH_FLD_VALUES1_LEN = 18427; // 16 -static const uint64_t SH_FLD_VALUES2 = 18428; // 16 -static const uint64_t SH_FLD_VALUES2_LEN = 18429; // 16 -static const uint64_t SH_FLD_VALUES3 = 18430; // 16 -static const uint64_t SH_FLD_VALUES3_LEN = 18431; // 16 -static const uint64_t SH_FLD_VALUES4 = 18432; // 16 -static const uint64_t SH_FLD_VALUES4_LEN = 18433; // 16 -static const uint64_t SH_FLD_VALUES5 = 18434; // 16 -static const uint64_t SH_FLD_VALUES5_LEN = 18435; // 16 -static const uint64_t SH_FLD_VALUES6 = 18436; // 16 -static const uint64_t SH_FLD_VALUES6_LEN = 18437; // 16 -static const uint64_t SH_FLD_VALUES7 = 18438; // 16 -static const uint64_t SH_FLD_VALUES7_LEN = 18439; // 16 -static const uint64_t SH_FLD_VALUE_LEN = 18440; // 48 -static const uint64_t SH_FLD_VAS_LOCAL_XSTOP = 18441; // 1 -static const uint64_t SH_FLD_VBGENDOC = 18442; // 3 -static const uint64_t SH_FLD_VBGENDOC_LEN = 18443; // 3 -static const uint64_t SH_FLD_VCORANGE = 18444; // 10 -static const uint64_t SH_FLD_VCORANGE_LEN = 18445; // 10 -static const uint64_t SH_FLD_VCOSEL = 18446; // 10 -static const uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE = 18447; // 30 -static const uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE_LEN = 18448; // 30 -static const uint64_t SH_FLD_VCS_PFET_FORCE_STATE = 18449; // 30 -static const uint64_t SH_FLD_VCS_PFET_FORCE_STATE_LEN = 18450; // 30 -static const uint64_t SH_FLD_VCS_PFET_SEL_OVERRIDE = 18451; // 30 -static const uint64_t SH_FLD_VCS_PFET_SEL_VALUE = 18452; // 30 -static const uint64_t SH_FLD_VCS_PFET_SEL_VALUE_LEN = 18453; // 30 -static const uint64_t SH_FLD_VCS_PFET_VAL_OVERRIDE = 18454; // 30 -static const uint64_t SH_FLD_VCS_PG_SEL = 18455; // 30 -static const uint64_t SH_FLD_VCS_PG_SEL_LEN = 18456; // 30 -static const uint64_t SH_FLD_VCS_PG_STATE = 18457; // 30 -static const uint64_t SH_FLD_VCS_PG_STATE_LEN = 18458; // 30 -static const uint64_t SH_FLD_VCS_VOFF_SEL = 18459; // 30 -static const uint64_t SH_FLD_VCS_VOFF_SEL_LEN = 18460; // 30 -static const uint64_t SH_FLD_VC_CRD_AVAIL_PERR = 18461; // 1 -static const uint64_t SH_FLD_VC_CRD_PERR = 18462; // 1 -static const uint64_t SH_FLD_VC_FATAL_ERROR_0_1 = 18463; // 1 -static const uint64_t SH_FLD_VC_FATAL_ERROR_0_1_LEN = 18464; // 1 -static const uint64_t SH_FLD_VC_INFO_ERROR_0_1 = 18465; // 1 -static const uint64_t SH_FLD_VC_INFO_ERROR_0_1_LEN = 18466; // 1 -static const uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3 = 18467; // 1 -static const uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN = 18468; // 1 -static const uint64_t SH_FLD_VC_RECOV_ERROR_0_1 = 18469; // 1 -static const uint64_t SH_FLD_VC_RECOV_ERROR_0_1_LEN = 18470; // 1 -static const uint64_t SH_FLD_VDD2VIO_LVL_FENCE_DC = 18471; // 3 -static const uint64_t SH_FLD_VDD_NEST_OBSERVE = 18472; // 1 -static const uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE = 18473; // 30 -static const uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE_LEN = 18474; // 30 -static const uint64_t SH_FLD_VDD_PFET_FORCE_STATE = 18475; // 30 -static const uint64_t SH_FLD_VDD_PFET_FORCE_STATE_LEN = 18476; // 30 -static const uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_EN = 18477; // 30 -static const uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE = 18478; // 30 -static const uint64_t SH_FLD_VDD_PFET_SEL_OVERRIDE = 18479; // 30 -static const uint64_t SH_FLD_VDD_PFET_SEL_VALUE = 18480; // 30 -static const uint64_t SH_FLD_VDD_PFET_SEL_VALUE_LEN = 18481; // 30 -static const uint64_t SH_FLD_VDD_PFET_VAL_OVERRIDE = 18482; // 30 -static const uint64_t SH_FLD_VDD_PG_SEL = 18483; // 30 -static const uint64_t SH_FLD_VDD_PG_SEL_LEN = 18484; // 30 -static const uint64_t SH_FLD_VDD_PG_STATE = 18485; // 30 -static const uint64_t SH_FLD_VDD_PG_STATE_LEN = 18486; // 30 -static const uint64_t SH_FLD_VDD_VOFF_SEL = 18487; // 30 -static const uint64_t SH_FLD_VDD_VOFF_SEL_LEN = 18488; // 30 -static const uint64_t SH_FLD_VDM_DISABLE = 18489; // 30 -static const uint64_t SH_FLD_VDM_DROOP_LARGE = 18490; // 6 -static const uint64_t SH_FLD_VDM_DROOP_LARGE_LEN = 18491; // 6 -static const uint64_t SH_FLD_VDM_DROOP_SMALL = 18492; // 6 -static const uint64_t SH_FLD_VDM_DROOP_SMALL_LEN = 18493; // 6 -static const uint64_t SH_FLD_VDM_DROOP_XTREME = 18494; // 6 -static const uint64_t SH_FLD_VDM_DROOP_XTREME_LEN = 18495; // 6 -static const uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR = 18496; // 12 -static const uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR_LEN = 18497; // 12 -static const uint64_t SH_FLD_VDM_EXTREME_DROOP_THRESHOLD = 18498; // 12 -static const uint64_t SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN = 18499; // 12 -static const uint64_t SH_FLD_VDM_LARGE_DROOP_CTR = 18500; // 12 -static const uint64_t SH_FLD_VDM_LARGE_DROOP_CTR_LEN = 18501; // 12 -static const uint64_t SH_FLD_VDM_LARGE_DROOP_THRESHOLD = 18502; // 12 -static const uint64_t SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN = 18503; // 12 -static const uint64_t SH_FLD_VDM_LCL_SAMPLE_EN = 18504; // 12 -static const uint64_t SH_FLD_VDM_NO_DROOP_CTR = 18505; // 12 -static const uint64_t SH_FLD_VDM_NO_DROOP_CTR_LEN = 18506; // 12 -static const uint64_t SH_FLD_VDM_OVERVOLT = 18507; // 6 -static const uint64_t SH_FLD_VDM_OVERVOLT_CTR = 18508; // 12 -static const uint64_t SH_FLD_VDM_OVERVOLT_CTR_LEN = 18509; // 12 -static const uint64_t SH_FLD_VDM_OVERVOLT_LEN = 18510; // 6 -static const uint64_t SH_FLD_VDM_POWERON = 18511; // 30 -static const uint64_t SH_FLD_VDM_SMALL_DROOP_CTR = 18512; // 12 -static const uint64_t SH_FLD_VDM_SMALL_DROOP_CTR_LEN = 18513; // 12 -static const uint64_t SH_FLD_VDM_SMALL_DROOP_THRESHOLD = 18514; // 12 -static const uint64_t SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN = 18515; // 12 -static const uint64_t SH_FLD_VDM_VID_COMPARE = 18516; // 6 -static const uint64_t SH_FLD_VDM_VID_COMPARE_LEN = 18517; // 6 -static const uint64_t SH_FLD_VECTOR_GROUP_EPSILON = 18518; // 8 -static const uint64_t SH_FLD_VECTOR_GROUP_EPSILON_LEN = 18519; // 8 -static const uint64_t SH_FLD_VG = 18520; // 1 -static const uint64_t SH_FLD_VG_COUNT = 18521; // 2 -static const uint64_t SH_FLD_VG_COUNT_LEN = 18522; // 2 -static const uint64_t SH_FLD_VG_TARGE = 18523; // 1 -static const uint64_t SH_FLD_VG_TARGET_SEL = 18524; // 24 -static const uint64_t SH_FLD_VG_TARGE_LEN = 18525; // 1 -static const uint64_t SH_FLD_VID_COMPARE_MAX = 18526; // 6 -static const uint64_t SH_FLD_VID_COMPARE_MAX_LEN = 18527; // 6 -static const uint64_t SH_FLD_VID_COMPARE_MIN = 18528; // 6 -static const uint64_t SH_FLD_VID_COMPARE_MIN_LEN = 18529; // 6 -static const uint64_t SH_FLD_VITAL_AL = 18530; // 43 -static const uint64_t SH_FLD_VITAL_PHASE = 18531; // 43 -static const uint64_t SH_FLD_VITAL_SCAN = 18532; // 43 -static const uint64_t SH_FLD_VITAL_SCAN_IN = 18533; // 43 -static const uint64_t SH_FLD_VITAL_THOLD = 18534; // 43 -static const uint64_t SH_FLD_VITL = 18535; // 43 -static const uint64_t SH_FLD_VITL_CLKOFF = 18536; // 43 -static const uint64_t SH_FLD_VOFF_CFG = 18537; // 6 -static const uint64_t SH_FLD_VOFF_CFG_LEN = 18538; // 6 -static const uint64_t SH_FLD_VOLT_MODEREG_PARITY_MASK = 18539; // 43 -static const uint64_t SH_FLD_VP = 18540; // 1 -static const uint64_t SH_FLD_VPC_DMA_ORDERING_TAG = 18541; // 1 -static const uint64_t SH_FLD_VPC_DMA_ORDERING_TAG_LEN = 18542; // 1 -static const uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG = 18543; // 1 -static const uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN = 18544; // 1 -static const uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG = 18545; // 1 -static const uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN = 18546; // 1 -static const uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG = 18547; // 1 -static const uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN = 18548; // 1 -static const uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG = 18549; // 1 -static const uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN = 18550; // 1 -static const uint64_t SH_FLD_VPD_DMA_READ = 18551; // 1 -static const uint64_t SH_FLD_VPD_DMA_READ_LEN = 18552; // 1 -static const uint64_t SH_FLD_VPD_DMA_WRITE = 18553; // 1 -static const uint64_t SH_FLD_VPD_DMA_WRITE_LEN = 18554; // 1 -static const uint64_t SH_FLD_VPROTH = 18555; // 8 -static const uint64_t SH_FLD_VPROTH_CTL = 18556; // 8 -static const uint64_t SH_FLD_VPROTH_CTL_LEN = 18557; // 8 -static const uint64_t SH_FLD_VPROTH_PSEL_MODE = 18558; // 8 -static const uint64_t SH_FLD_VREF = 18559; // 9 -static const uint64_t SH_FLD_VREFDQ0D = 18560; // 8 -static const uint64_t SH_FLD_VREFDQ0DSGN = 18561; // 8 -static const uint64_t SH_FLD_VREFDQ0D_LEN = 18562; // 8 -static const uint64_t SH_FLD_VREFDQ1D = 18563; // 8 -static const uint64_t SH_FLD_VREFDQ1DSGN = 18564; // 8 -static const uint64_t SH_FLD_VREFDQ1D_LEN = 18565; // 8 -static const uint64_t SH_FLD_VREFTUNE = 18566; // 3 -static const uint64_t SH_FLD_VREFTUNE_LEN = 18567; // 3 -static const uint64_t SH_FLD_VREF_LEN = 18568; // 1 -static const uint64_t SH_FLD_VREGBYP = 18569; // 6 -static const uint64_t SH_FLD_VREGBYPASS = 18570; // 4 -static const uint64_t SH_FLD_VREGENABLE_N = 18571; // 4 -static const uint64_t SH_FLD_VREG_S = 18572; // 8 -static const uint64_t SH_FLD_VSEL = 18573; // 10 -static const uint64_t SH_FLD_VSEL_LEN = 18574; // 10 -static const uint64_t SH_FLD_VST_TYPE = 18575; // 1 -static const uint64_t SH_FLD_VST_TYPE_LEN = 18576; // 1 -static const uint64_t SH_FLD_VTARGET = 18577; // 4 -static const uint64_t SH_FLD_VTARGET_LEN = 18578; // 4 -static const uint64_t SH_FLD_V_TARG = 18579; // 1 -static const uint64_t SH_FLD_V_TARG_LEN = 18580; // 1 -static const uint64_t SH_FLD_W0_COUNT = 18581; // 12 -static const uint64_t SH_FLD_W0_COUNT_LEN = 18582; // 12 -static const uint64_t SH_FLD_W1_COUNT = 18583; // 12 -static const uint64_t SH_FLD_W1_COUNT_LEN = 18584; // 12 -static const uint64_t SH_FLD_WAITING = 18585; // 2 -static const uint64_t SH_FLD_WAIT_ALLWAYS = 18586; // 129 -static const uint64_t SH_FLD_WAIT_CYCLES = 18587; // 172 -static const uint64_t SH_FLD_WAIT_CYCLES_LEN = 18588; // 172 -static const uint64_t SH_FLD_WANT_CACHE_DISABLE = 18589; // 4 -static const uint64_t SH_FLD_WANT_INVALIDATE = 18590; // 3 -static const uint64_t SH_FLD_WARB_INVALID_CASE_ERROR = 18591; // 2 -static const uint64_t SH_FLD_WARM_START_COMPLETED = 18592; // 2 -static const uint64_t SH_FLD_WAT0_EVENT_SELECT = 18593; // 8 -static const uint64_t SH_FLD_WAT0_EVENT_SELECT_LEN = 18594; // 8 -static const uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA = 18595; // 8 -static const uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA_LEN = 18596; // 8 -static const uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST = 18597; // 8 -static const uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST_LEN = 18598; // 8 -static const uint64_t SH_FLD_WAT1_EVENT_SELECT = 18599; // 8 -static const uint64_t SH_FLD_WAT1_EVENT_SELECT_LEN = 18600; // 8 -static const uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA = 18601; // 8 -static const uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA_LEN = 18602; // 8 -static const uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST = 18603; // 8 -static const uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST_LEN = 18604; // 8 -static const uint64_t SH_FLD_WATCHDOG = 18605; // 1 -static const uint64_t SH_FLD_WATCHDOG_ENABLE = 18606; // 43 -static const uint64_t SH_FLD_WATCHDOG_SEL = 18607; // 17 -static const uint64_t SH_FLD_WATCHDOG_SEL_LEN = 18608; // 17 -static const uint64_t SH_FLD_WATERMARK_REG_0 = 18609; // 2 -static const uint64_t SH_FLD_WATERMARK_REG_0_LEN = 18610; // 2 -static const uint64_t SH_FLD_WATERMARK_REG_1 = 18611; // 1 -static const uint64_t SH_FLD_WATERMARK_REG_1_LEN = 18612; // 1 -static const uint64_t SH_FLD_WATERMARK_REG_2 = 18613; // 1 -static const uint64_t SH_FLD_WATERMARK_REG_2_LEN = 18614; // 1 -static const uint64_t SH_FLD_WATERMARK_REG_3 = 18615; // 1 -static const uint64_t SH_FLD_WATERMARK_REG_3_LEN = 18616; // 1 -static const uint64_t SH_FLD_WAT_ACTION_DIS_ALL_SPEC = 18617; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_ALL_SPEC_LEN = 18618; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_FASTPATH = 18619; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_FASTPATH_LEN = 18620; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_PREFETCH = 18621; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_PREFETCH_LEN = 18622; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_READ_BYP = 18623; // 4 -static const uint64_t SH_FLD_WAT_ACTION_DIS_READ_BYP_LEN = 18624; // 4 -static const uint64_t SH_FLD_WAT_ACTION_FORCE_MDI = 18625; // 4 -static const uint64_t SH_FLD_WAT_ACTION_FORCE_MDI_LEN = 18626; // 4 -static const uint64_t SH_FLD_WAT_ACTION_FORCE_SFSTAT = 18627; // 4 -static const uint64_t SH_FLD_WAT_ACTION_FORCE_SFSTAT_LEN = 18628; // 4 -static const uint64_t SH_FLD_WAT_ACTION_SEL = 18629; // 8 -static const uint64_t SH_FLD_WAT_ACTION_SEL_LEN = 18630; // 8 -static const uint64_t SH_FLD_WAT_CNTL_REG_SEL = 18631; // 4 -static const uint64_t SH_FLD_WAT_CNTL_REG_SEL_LEN = 18632; // 4 -static const uint64_t SH_FLD_WAT_DEBUG_ATTN = 18633; // 2 -static const uint64_t SH_FLD_WAT_DEBUG_REG_PE = 18634; // 2 -static const uint64_t SH_FLD_WAT_ERROR = 18635; // 16 -static const uint64_t SH_FLD_WAT_EVENT_ENABLE = 18636; // 8 -static const uint64_t SH_FLD_WAT_EVENT_ENABLE_MCA = 18637; // 8 -static const uint64_t SH_FLD_WAT_EVENT_ENABLE_NEST = 18638; // 8 -static const uint64_t SH_FLD_WAT_EVENT_SEL = 18639; // 4 -static const uint64_t SH_FLD_WAT_EVENT_SEL_LEN = 18640; // 4 -static const uint64_t SH_FLD_WAT_EXT_EVENT_TO_INT_SEL = 18641; // 4 -static const uint64_t SH_FLD_WAT_EXT_EVENT_TO_INT_SEL_LEN = 18642; // 4 -static const uint64_t SH_FLD_WAT_EXT_SEL = 18643; // 4 -static const uint64_t SH_FLD_WAT_EXT_SEL_LEN = 18644; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT0_SEL = 18645; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT0_SEL_LEN = 18646; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT1_SEL = 18647; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT1_SEL_LEN = 18648; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT2_SEL = 18649; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT2_SEL_LEN = 18650; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT3_SEL = 18651; // 4 -static const uint64_t SH_FLD_WAT_GLOB_EVENT3_SEL_LEN = 18652; // 4 -static const uint64_t SH_FLD_WAT_LOCAL_EVENT_SEL = 18653; // 4 -static const uint64_t SH_FLD_WAT_LOCAL_EVENT_SEL_LEN = 18654; // 4 -static const uint64_t SH_FLD_WAT_SPARE1 = 18655; // 8 -static const uint64_t SH_FLD_WAT_SPARE1_LEN = 18656; // 8 -static const uint64_t SH_FLD_WAT_SPARE1_MCA = 18657; // 8 -static const uint64_t SH_FLD_WAT_SPARE1_MCA_LEN = 18658; // 8 -static const uint64_t SH_FLD_WAT_SPARE1_NEST = 18659; // 8 -static const uint64_t SH_FLD_WAT_SPARE1_NEST_LEN = 18660; // 8 -static const uint64_t SH_FLD_WAT_STALL_ACTION = 18661; // 8 -static const uint64_t SH_FLD_WAT_STALL_ACTION_LEN = 18662; // 8 -static const uint64_t SH_FLD_WBMGR_DBG_0_SELECT = 18663; // 8 -static const uint64_t SH_FLD_WBMGR_DBG_1_SELECT = 18664; // 8 -static const uint64_t SH_FLD_WBRD_DEBUG_0_SELECT = 18665; // 8 -static const uint64_t SH_FLD_WBRD_DEBUG_1_SELECT = 18666; // 8 -static const uint64_t SH_FLD_WC = 18667; // 8 -static const uint64_t SH_FLD_WC_BS_BAR = 18668; // 1 -static const uint64_t SH_FLD_WC_BS_BAR_LEN = 18669; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT10 = 18670; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT11 = 18671; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT12 = 18672; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT13 = 18673; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT14 = 18674; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT15 = 18675; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT16 = 18676; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT17 = 18677; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT18 = 18678; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT19 = 18679; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT20 = 18680; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT21 = 18681; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT22 = 18682; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT23 = 18683; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT4 = 18684; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT5 = 18685; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT6 = 18686; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT7 = 18687; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT8 = 18688; // 1 -static const uint64_t SH_FLD_WC_CERR_BIT9 = 18689; // 1 -static const uint64_t SH_FLD_WC_CERR_RESET = 18690; // 1 -static const uint64_t SH_FLD_WC_ECC_CE_ERROR = 18691; // 2 -static const uint64_t SH_FLD_WC_ECC_SUE_ERROR = 18692; // 2 -static const uint64_t SH_FLD_WC_ECC_UE_ERROR = 18693; // 2 -static const uint64_t SH_FLD_WC_LOGIC_HW_ERROR = 18694; // 2 -static const uint64_t SH_FLD_WC_MASK = 18695; // 8 -static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI = 18696; // 1 -static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN = 18697; // 1 -static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO = 18698; // 1 -static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN = 18699; // 1 -static const uint64_t SH_FLD_WC_TRACE_INT_DATA_HI = 18700; // 1 -static const uint64_t SH_FLD_WC_TRACE_INT_DATA_LO = 18701; // 1 -static const uint64_t SH_FLD_WC_TRACE_INT_TRIG_01 = 18702; // 1 -static const uint64_t SH_FLD_WC_TRACE_INT_TRIG_23 = 18703; // 1 -static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01 = 18704; // 1 -static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN = 18705; // 1 -static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23 = 18706; // 1 -static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN = 18707; // 1 -static const uint64_t SH_FLD_WDATA = 18708; // 1 -static const uint64_t SH_FLD_WDATA_LEN = 18709; // 1 -static const uint64_t SH_FLD_WDFCFG_PE = 18710; // 8 -static const uint64_t SH_FLD_WDF_ASYNC_ERROR = 18711; // 8 -static const uint64_t SH_FLD_WDF_ASYNC_INTERFACE_ERROR = 18712; // 8 -static const uint64_t SH_FLD_WDF_BUFFER_CE = 18713; // 8 -static const uint64_t SH_FLD_WDF_BUFFER_SUE = 18714; // 8 -static const uint64_t SH_FLD_WDF_BUFFER_UE = 18715; // 8 -static const uint64_t SH_FLD_WDF_ERR_INJECT0 = 18716; // 8 -static const uint64_t SH_FLD_WDF_ERR_INJECT0_LEN = 18717; // 8 -static const uint64_t SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR = 18718; // 8 -static const uint64_t SH_FLD_WDF_OVERRUN_ERROR_0 = 18719; // 8 -static const uint64_t SH_FLD_WDF_OVERRUN_ERROR_1 = 18720; // 8 -static const uint64_t SH_FLD_WDF_SCOM_SEQUENCE_ERROR = 18721; // 8 -static const uint64_t SH_FLD_WDF_STATE_MACHINE_ERROR = 18722; // 8 -static const uint64_t SH_FLD_WECR_PE = 18723; // 8 -static const uint64_t SH_FLD_WHICH_8BECK = 18724; // 8 -static const uint64_t SH_FLD_WHICH_8BECK_LEN = 18725; // 8 -static const uint64_t SH_FLD_WILDCARD = 18726; // 6 -static const uint64_t SH_FLD_WINDOW_SELECT = 18727; // 3 -static const uint64_t SH_FLD_WINDOW_SELECT_LEN = 18728; // 3 -static const uint64_t SH_FLD_WIRETEST_DONE = 18729; // 4 -static const uint64_t SH_FLD_WIRETEST_FAILED = 18730; // 4 -static const uint64_t SH_FLD_WITH_ADDRESS_0 = 18731; // 2 -static const uint64_t SH_FLD_WITH_ADDRESS_1 = 18732; // 1 -static const uint64_t SH_FLD_WITH_ADDRESS_2 = 18733; // 1 -static const uint64_t SH_FLD_WITH_ADDRESS_3 = 18734; // 1 -static const uint64_t SH_FLD_WITH_START_0 = 18735; // 2 -static const uint64_t SH_FLD_WITH_START_1 = 18736; // 1 -static const uint64_t SH_FLD_WITH_START_2 = 18737; // 1 -static const uint64_t SH_FLD_WITH_START_3 = 18738; // 1 -static const uint64_t SH_FLD_WITH_STOP_0 = 18739; // 2 -static const uint64_t SH_FLD_WITH_STOP_1 = 18740; // 1 -static const uint64_t SH_FLD_WITH_STOP_2 = 18741; // 1 -static const uint64_t SH_FLD_WITH_STOP_3 = 18742; // 1 -static const uint64_t SH_FLD_WI_MACHINE_HANG = 18743; // 12 -static const uint64_t SH_FLD_WI_MACHINE_W4DT_HANG = 18744; // 12 -static const uint64_t SH_FLD_WI_UNSOLICITED_DATA = 18745; // 12 -static const uint64_t SH_FLD_WKUP_NOTIFY_SELECT = 18746; // 24 -static const uint64_t SH_FLD_WL = 18747; // 8 -static const uint64_t SH_FLD_WL_ONE_DQS_PULSE = 18748; // 8 -static const uint64_t SH_FLD_WM_MULTIHIT_ERR = 18749; // 2 -static const uint64_t SH_FLD_WM_WIN_NOT_OPEN_ERR = 18750; // 2 -static const uint64_t SH_FLD_WOF = 18751; // 5 -static const uint64_t SH_FLD_WOF_COUNTER = 18752; // 1 -static const uint64_t SH_FLD_WOF_COUNTER_LEN = 18753; // 1 -static const uint64_t SH_FLD_WOF_LEN = 18754; // 5 -static const uint64_t SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 18755; // 4 -static const uint64_t SH_FLD_WORD = 18756; // 8 -static const uint64_t SH_FLD_WORD_LEN = 18757; // 8 -static const uint64_t SH_FLD_WORK1 = 18758; // 3 -static const uint64_t SH_FLD_WORK1_LEN = 18759; // 3 -static const uint64_t SH_FLD_WORK2 = 18760; // 3 -static const uint64_t SH_FLD_WORK2_LEN = 18761; // 3 -static const uint64_t SH_FLD_WRAP_0 = 18762; // 2 -static const uint64_t SH_FLD_WRAP_1 = 18763; // 1 -static const uint64_t SH_FLD_WRAP_2 = 18764; // 1 -static const uint64_t SH_FLD_WRAP_3 = 18765; // 1 -static const uint64_t SH_FLD_WRCMP = 18766; // 2 -static const uint64_t SH_FLD_WRCMP_LEN = 18767; // 2 -static const uint64_t SH_FLD_WRCNTL_DBG_SELECT = 18768; // 8 -static const uint64_t SH_FLD_WRDM_DLY = 18769; // 8 -static const uint64_t SH_FLD_WRDM_DLY_LEN = 18770; // 8 -static const uint64_t SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 18771; // 2 -static const uint64_t SH_FLD_WRITE = 18772; // 9 -static const uint64_t SH_FLD_WRITE_CMD = 18773; // 1 -static const uint64_t SH_FLD_WRITE_COMPLETE = 18774; // 1 -static const uint64_t SH_FLD_WRITE_COUNT = 18775; // 8 -static const uint64_t SH_FLD_WRITE_COUNTER = 18776; // 1 -static const uint64_t SH_FLD_WRITE_COUNTER_LEN = 18777; // 1 -static const uint64_t SH_FLD_WRITE_COUNT_LEN = 18778; // 8 -static const uint64_t SH_FLD_WRITE_CRD_POOL = 18779; // 1 -static const uint64_t SH_FLD_WRITE_CRD_POOL_LEN = 18780; // 1 -static const uint64_t SH_FLD_WRITE_CTR = 18781; // 8 -static const uint64_t SH_FLD_WRITE_ECC_DATAPATH_ERROR = 18782; // 8 -static const uint64_t SH_FLD_WRITE_ENABLE = 18783; // 129 -static const uint64_t SH_FLD_WRITE_ERR_INJECT0 = 18784; // 8 -static const uint64_t SH_FLD_WRITE_ERR_INJECT0_LEN = 18785; // 8 -static const uint64_t SH_FLD_WRITE_INVALID_FACES = 18786; // 1 -static const uint64_t SH_FLD_WRITE_INVALID_PIB = 18787; // 1 -static const uint64_t SH_FLD_WRITE_LATENCY_OFFSET = 18788; // 8 -static const uint64_t SH_FLD_WRITE_LATENCY_OFFSET_LEN = 18789; // 8 -static const uint64_t SH_FLD_WRITE_NOT_READ = 18790; // 3 -static const uint64_t SH_FLD_WRITE_NVLD = 18791; // 1 -static const uint64_t SH_FLD_WRITE_ON_RUN = 18792; // 90 -static const uint64_t SH_FLD_WRITE_POOL = 18793; // 1 -static const uint64_t SH_FLD_WRITE_POOL_LEN = 18794; // 1 -static const uint64_t SH_FLD_WRITE_RMW_CE = 18795; // 8 -static const uint64_t SH_FLD_WRITE_RMW_SUE = 18796; // 8 -static const uint64_t SH_FLD_WRITE_RMW_UE = 18797; // 8 -static const uint64_t SH_FLD_WRITE_RST_INTERRUPT_FACES = 18798; // 1 -static const uint64_t SH_FLD_WRITE_RST_INTERRUPT_PIB = 18799; // 1 -static const uint64_t SH_FLD_WRITE_TSIZE = 18800; // 4 -static const uint64_t SH_FLD_WRITE_TSIZE_LEN = 18801; // 4 -static const uint64_t SH_FLD_WRITE_TTYPE = 18802; // 4 -static const uint64_t SH_FLD_WRITE_TTYPE_LEN = 18803; // 4 -static const uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR = 18804; // 1 -static const uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 18805; // 1 -static const uint64_t SH_FLD_WRMON_BAR0_BA = 18806; // 1 -static const uint64_t SH_FLD_WRMON_BAR0_BA_LEN = 18807; // 1 -static const uint64_t SH_FLD_WRMON_BAR0_SIZE = 18808; // 1 -static const uint64_t SH_FLD_WRMON_BAR0_SIZE_LEN = 18809; // 1 -static const uint64_t SH_FLD_WRMON_BAR1_BA = 18810; // 1 -static const uint64_t SH_FLD_WRMON_BAR1_BA_LEN = 18811; // 1 -static const uint64_t SH_FLD_WRMON_BAR1_SIZE = 18812; // 1 -static const uint64_t SH_FLD_WRMON_BAR1_SIZE_LEN = 18813; // 1 -static const uint64_t SH_FLD_WRMON_BAR2_BA = 18814; // 1 -static const uint64_t SH_FLD_WRMON_BAR2_BA_LEN = 18815; // 1 -static const uint64_t SH_FLD_WRMON_BAR2_SIZE = 18816; // 1 -static const uint64_t SH_FLD_WRMON_BAR2_SIZE_LEN = 18817; // 1 -static const uint64_t SH_FLD_WRMON_BAR3_BA = 18818; // 1 -static const uint64_t SH_FLD_WRMON_BAR3_BA_LEN = 18819; // 1 -static const uint64_t SH_FLD_WRMON_BAR3_SIZE = 18820; // 1 -static const uint64_t SH_FLD_WRMON_BAR3_SIZE_LEN = 18821; // 1 -static const uint64_t SH_FLD_WRMON_BAR4_BA = 18822; // 1 -static const uint64_t SH_FLD_WRMON_BAR4_BA_LEN = 18823; // 1 -static const uint64_t SH_FLD_WRMON_BAR4_SIZE = 18824; // 1 -static const uint64_t SH_FLD_WRMON_BAR4_SIZE_LEN = 18825; // 1 -static const uint64_t SH_FLD_WRMON_BAR5_BA = 18826; // 1 -static const uint64_t SH_FLD_WRMON_BAR5_BA_LEN = 18827; // 1 -static const uint64_t SH_FLD_WRMON_BAR5_SIZE = 18828; // 1 -static const uint64_t SH_FLD_WRMON_BAR5_SIZE_LEN = 18829; // 1 -static const uint64_t SH_FLD_WRMON_BAR6_BA = 18830; // 1 -static const uint64_t SH_FLD_WRMON_BAR6_BA_LEN = 18831; // 1 -static const uint64_t SH_FLD_WRMON_BAR6_SIZE = 18832; // 1 -static const uint64_t SH_FLD_WRMON_BAR6_SIZE_LEN = 18833; // 1 -static const uint64_t SH_FLD_WRMON_BAR7_BA = 18834; // 1 -static const uint64_t SH_FLD_WRMON_BAR7_BA_LEN = 18835; // 1 -static const uint64_t SH_FLD_WRMON_BAR7_SIZE = 18836; // 1 -static const uint64_t SH_FLD_WRMON_BAR7_SIZE_LEN = 18837; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_ENADTTYPE = 18838; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TSIZE = 18839; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK = 18840; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK_LEN = 18841; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TSIZE_LEN = 18842; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TTYPE = 18843; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS = 18844; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS_LEN = 18845; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK = 18846; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK_LEN = 18847; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_TTYPE_LEN = 18848; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_UNUSED = 18849; // 1 -static const uint64_t SH_FLD_WRMON_CMP0_VAL = 18850; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_ENADTTYPE = 18851; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TSIZE = 18852; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK = 18853; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK_LEN = 18854; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TSIZE_LEN = 18855; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TTYPE = 18856; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS = 18857; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS_LEN = 18858; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK = 18859; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK_LEN = 18860; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_TTYPE_LEN = 18861; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_UNUSED = 18862; // 1 -static const uint64_t SH_FLD_WRMON_CMP1_VAL = 18863; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_ENADTTYPE = 18864; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TSIZE = 18865; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK = 18866; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK_LEN = 18867; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TSIZE_LEN = 18868; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TTYPE = 18869; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS = 18870; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS_LEN = 18871; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK = 18872; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK_LEN = 18873; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_TTYPE_LEN = 18874; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_UNUSED = 18875; // 1 -static const uint64_t SH_FLD_WRMON_CMP2_VAL = 18876; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_ENADTTYPE = 18877; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TSIZE = 18878; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK = 18879; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK_LEN = 18880; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TSIZE_LEN = 18881; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TTYPE = 18882; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS = 18883; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS_LEN = 18884; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK = 18885; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK_LEN = 18886; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_TTYPE_LEN = 18887; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_UNUSED = 18888; // 1 -static const uint64_t SH_FLD_WRMON_CMP3_VAL = 18889; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_ENADTTYPE = 18890; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TSIZE = 18891; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK = 18892; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK_LEN = 18893; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TSIZE_LEN = 18894; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TTYPE = 18895; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS = 18896; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS_LEN = 18897; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK = 18898; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK_LEN = 18899; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_TTYPE_LEN = 18900; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_UNUSED = 18901; // 1 -static const uint64_t SH_FLD_WRMON_CMP4_VAL = 18902; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_ENADTTYPE = 18903; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TSIZE = 18904; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK = 18905; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK_LEN = 18906; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TSIZE_LEN = 18907; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TTYPE = 18908; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS = 18909; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS_LEN = 18910; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK = 18911; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK_LEN = 18912; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_TTYPE_LEN = 18913; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_UNUSED = 18914; // 1 -static const uint64_t SH_FLD_WRMON_CMP5_VAL = 18915; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_ENADTTYPE = 18916; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TSIZE = 18917; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK = 18918; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK_LEN = 18919; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TSIZE_LEN = 18920; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TTYPE = 18921; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS = 18922; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS_LEN = 18923; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK = 18924; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK_LEN = 18925; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_TTYPE_LEN = 18926; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_UNUSED = 18927; // 1 -static const uint64_t SH_FLD_WRMON_CMP6_VAL = 18928; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_ENADTTYPE = 18929; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TSIZE = 18930; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK = 18931; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK_LEN = 18932; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TSIZE_LEN = 18933; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TTYPE = 18934; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS = 18935; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS_LEN = 18936; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK = 18937; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK_LEN = 18938; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_TTYPE_LEN = 18939; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_UNUSED = 18940; // 1 -static const uint64_t SH_FLD_WRMON_CMP7_VAL = 18941; // 1 -static const uint64_t SH_FLD_WRMON_WID0 = 18942; // 1 -static const uint64_t SH_FLD_WRMON_WID0_LEN = 18943; // 1 -static const uint64_t SH_FLD_WRMON_WID1 = 18944; // 1 -static const uint64_t SH_FLD_WRMON_WID1_LEN = 18945; // 1 -static const uint64_t SH_FLD_WRMON_WID2 = 18946; // 1 -static const uint64_t SH_FLD_WRMON_WID2_LEN = 18947; // 1 -static const uint64_t SH_FLD_WRMON_WID3 = 18948; // 1 -static const uint64_t SH_FLD_WRMON_WID3_LEN = 18949; // 1 -static const uint64_t SH_FLD_WRMON_WID4 = 18950; // 1 -static const uint64_t SH_FLD_WRMON_WID4_LEN = 18951; // 1 -static const uint64_t SH_FLD_WRMON_WID5 = 18952; // 1 -static const uint64_t SH_FLD_WRMON_WID5_LEN = 18953; // 1 -static const uint64_t SH_FLD_WRMON_WID6 = 18954; // 1 -static const uint64_t SH_FLD_WRMON_WID6_LEN = 18955; // 1 -static const uint64_t SH_FLD_WRMON_WID7 = 18956; // 1 -static const uint64_t SH_FLD_WRMON_WID7_LEN = 18957; // 1 -static const uint64_t SH_FLD_WRQ0_EMPTY = 18958; // 4 -static const uint64_t SH_FLD_WRQ1_EMPTY = 18959; // 4 -static const uint64_t SH_FLD_WRQ_BAD_CRESP = 18960; // 1 -static const uint64_t SH_FLD_WRQ_CAPACITY_LIMIT = 18961; // 4 -static const uint64_t SH_FLD_WRQ_CAPACITY_LIMIT_LEN = 18962; // 4 -static const uint64_t SH_FLD_WRQ_FSM_PERR = 18963; // 1 -static const uint64_t SH_FLD_WRQ_HANG = 18964; // 8 -static const uint64_t SH_FLD_WRQ_OP_HANG = 18965; // 1 -static const uint64_t SH_FLD_WRQ_OVERFLOW = 18966; // 1 -static const uint64_t SH_FLD_WRQ_PE = 18967; // 8 -static const uint64_t SH_FLD_WRQ_RRQ_HANG_ERR = 18968; // 16 -static const uint64_t SH_FLD_WRSBG_DLY = 18969; // 8 -static const uint64_t SH_FLD_WRSBG_DLY_LEN = 18970; // 8 -static const uint64_t SH_FLD_WRSMDR_DLY = 18971; // 8 -static const uint64_t SH_FLD_WRSMDR_DLY_LEN = 18972; // 8 -static const uint64_t SH_FLD_WRSMSR_DLY = 18973; // 8 -static const uint64_t SH_FLD_WRSMSR_DLY_LEN = 18974; // 8 -static const uint64_t SH_FLD_WRTCFG_PE = 18975; // 8 -static const uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES = 18976; // 8 -static const uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES_LEN = 18977; // 8 -static const uint64_t SH_FLD_WRT_BUFFER_CE = 18978; // 8 -static const uint64_t SH_FLD_WRT_BUFFER_SUE = 18979; // 8 -static const uint64_t SH_FLD_WRT_BUFFER_UE = 18980; // 8 -static const uint64_t SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR = 18981; // 8 -static const uint64_t SH_FLD_WRT_RST_INTRPT_FACES = 18982; // 1 -static const uint64_t SH_FLD_WRT_RST_INTRPT_PIB = 18983; // 1 -static const uint64_t SH_FLD_WRT_SCOM_SEQUENCE_ERROR = 18984; // 8 -static const uint64_t SH_FLD_WR_BUFFER_STATUS = 18985; // 2 -static const uint64_t SH_FLD_WR_BUFFER_STATUS_LEN = 18986; // 2 -static const uint64_t SH_FLD_WR_BYTE_COUNT = 18987; // 2 -static const uint64_t SH_FLD_WR_BYTE_COUNT_LEN = 18988; // 2 -static const uint64_t SH_FLD_WR_CNTL = 18989; // 8 -static const uint64_t SH_FLD_WR_CNTL_MASK = 18990; // 8 -static const uint64_t SH_FLD_WR_DATA_PARITY_ERROR = 18991; // 3 -static const uint64_t SH_FLD_WR_ECC_CE = 18992; // 1 -static const uint64_t SH_FLD_WR_ECC_UE = 18993; // 1 -static const uint64_t SH_FLD_WR_EPSILON_VALUE = 18994; // 2 -static const uint64_t SH_FLD_WR_EPSILON_VALUE_LEN = 18995; // 2 -static const uint64_t SH_FLD_WR_FIFO_STAB = 18996; // 8 -static const uint64_t SH_FLD_WR_GATHER_TIMEOUT = 18997; // 4 -static const uint64_t SH_FLD_WR_GATHER_TIMEOUT_LEN = 18998; // 4 -static const uint64_t SH_FLD_WR_LEVEL = 18999; // 8 -static const uint64_t SH_FLD_WR_MON_NOT_DISABLED_ERR = 19000; // 2 -static const uint64_t SH_FLD_WR_PAR_ERR = 19001; // 8 -static const uint64_t SH_FLD_WR_PAR_ERR_MASK = 19002; // 8 -static const uint64_t SH_FLD_WR_PRE_DLY = 19003; // 8 -static const uint64_t SH_FLD_WR_PRE_DLY_LEN = 19004; // 8 -static const uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT = 19005; // 8 -static const uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 19006; // 8 -static const uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT = 19007; // 8 -static const uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT_LEN = 19008; // 8 -static const uint64_t SH_FLD_WR_SCOPE = 19009; // 24 -static const uint64_t SH_FLD_WR_SLVNUM = 19010; // 2 -static const uint64_t SH_FLD_WR_SLVNUM_LEN = 19011; // 2 -static const uint64_t SH_FLD_WR_SPLIT_UT0_ENA = 19012; // 6 -static const uint64_t SH_FLD_WR_SPLIT_UT1_ENA = 19013; // 6 -static const uint64_t SH_FLD_WR_TIER_1_CNT_VAL = 19014; // 1 -static const uint64_t SH_FLD_WR_TIER_1_CNT_VAL_LEN = 19015; // 1 -static const uint64_t SH_FLD_WR_TIER_1_DIV_VAL = 19016; // 1 -static const uint64_t SH_FLD_WR_TIER_1_DIV_VAL_LEN = 19017; // 1 -static const uint64_t SH_FLD_WR_TIER_2_CNT_VAL = 19018; // 1 -static const uint64_t SH_FLD_WR_TIER_2_CNT_VAL_LEN = 19019; // 1 -static const uint64_t SH_FLD_WR_TIER_2_DIV_VAL = 19020; // 1 -static const uint64_t SH_FLD_WR_TIER_2_DIV_VAL_LEN = 19021; // 1 -static const uint64_t SH_FLD_WR_VALID = 19022; // 1 -static const uint64_t SH_FLD_WSIZE = 19023; // 1 -static const uint64_t SH_FLD_WSIZE_LEN = 19024; // 1 -static const uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL = 19025; // 12 -static const uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL_LEN = 19026; // 12 -static const uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL = 19027; // 24 -static const uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL_LEN = 19028; // 24 -static const uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL = 19029; // 24 -static const uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL_LEN = 19030; // 24 -static const uint64_t SH_FLD_WTL_SM_STATUS = 19031; // 4 -static const uint64_t SH_FLD_WTL_SM_STATUS_LEN = 19032; // 4 -static const uint64_t SH_FLD_WTL_TEST_CLOCK = 19033; // 4 -static const uint64_t SH_FLD_WTL_TEST_DATA = 19034; // 4 -static const uint64_t SH_FLD_WTR_MAX_BAD_LANES = 19035; // 4 -static const uint64_t SH_FLD_WTR_MAX_BAD_LANES_LEN = 19036; // 4 -static const uint64_t SH_FLD_WT_ALL_DONE_GCRMSG = 19037; // 4 -static const uint64_t SH_FLD_WT_BS_CLOCK_EN_BYP = 19038; // 4 -static const uint64_t SH_FLD_WT_BS_DATA_EN_BYP = 19039; // 4 -static const uint64_t SH_FLD_WT_CHECK_COUNT = 19040; // 4 -static const uint64_t SH_FLD_WT_CHECK_COUNT_LEN = 19041; // 4 -static const uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE = 19042; // 4 -static const uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE_LEN = 19043; // 4 -static const uint64_t SH_FLD_WT_CLK_LANE_INVERTED = 19044; // 4 -static const uint64_t SH_FLD_WT_CU_BYP_PLL_LOCK = 19045; // 4 -static const uint64_t SH_FLD_WT_CU_PLL_PGOOD = 19046; // 4 -static const uint64_t SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG = 19047; // 4 -static const uint64_t SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG = 19048; // 4 -static const uint64_t SH_FLD_WT_LANE_BAD_CODE = 19049; // 96 -static const uint64_t SH_FLD_WT_LANE_BAD_CODE_LEN = 19050; // 96 -static const uint64_t SH_FLD_WT_LANE_DISABLED = 19051; // 96 -static const uint64_t SH_FLD_WT_PATTERN_LENGTH = 19052; // 8 -static const uint64_t SH_FLD_WT_PATTERN_LENGTH_LEN = 19053; // 8 -static const uint64_t SH_FLD_WT_PLL_REFCLKSEL = 19054; // 4 -static const uint64_t SH_FLD_WT_PREV_DONE_GCRMSG = 19055; // 4 -static const uint64_t SH_FLD_WT_TIMEOUT_SEL = 19056; // 4 -static const uint64_t SH_FLD_WT_TIMEOUT_SEL_LEN = 19057; // 4 -static const uint64_t SH_FLD_WWDM_DLY = 19058; // 8 -static const uint64_t SH_FLD_WWDM_DLY_LEN = 19059; // 8 -static const uint64_t SH_FLD_WWOP_DLY = 19060; // 8 -static const uint64_t SH_FLD_WWOP_DLY_LEN = 19061; // 8 -static const uint64_t SH_FLD_WWSMDR_DLY = 19062; // 8 -static const uint64_t SH_FLD_WWSMDR_DLY_LEN = 19063; // 8 -static const uint64_t SH_FLD_WWSMSR_DLY = 19064; // 8 -static const uint64_t SH_FLD_WWSMSR_DLY_LEN = 19065; // 8 -static const uint64_t SH_FLD_X0_ACT = 19066; // 1 -static const uint64_t SH_FLD_X0_HI = 19067; // 1 -static const uint64_t SH_FLD_X0_HI_LEN = 19068; // 1 -static const uint64_t SH_FLD_X0_LO = 19069; // 1 -static const uint64_t SH_FLD_X0_LO_LEN = 19070; // 1 -static const uint64_t SH_FLD_X0_TX_ENABLE = 19071; // 4 -static const uint64_t SH_FLD_X0_TX_SELECT = 19072; // 4 -static const uint64_t SH_FLD_X0_TX_SELECT_LEN = 19073; // 4 -static const uint64_t SH_FLD_X1_ACT = 19074; // 1 -static const uint64_t SH_FLD_X1_HI = 19075; // 1 -static const uint64_t SH_FLD_X1_HI_LEN = 19076; // 1 -static const uint64_t SH_FLD_X1_LO = 19077; // 1 -static const uint64_t SH_FLD_X1_LO_LEN = 19078; // 1 -static const uint64_t SH_FLD_X1_TX_ENABLE = 19079; // 4 -static const uint64_t SH_FLD_X1_TX_SELECT = 19080; // 4 -static const uint64_t SH_FLD_X1_TX_SELECT_LEN = 19081; // 4 -static const uint64_t SH_FLD_X2_ACT = 19082; // 1 -static const uint64_t SH_FLD_X2_HI = 19083; // 1 -static const uint64_t SH_FLD_X2_HI_LEN = 19084; // 1 -static const uint64_t SH_FLD_X2_LO = 19085; // 1 -static const uint64_t SH_FLD_X2_LO_LEN = 19086; // 1 -static const uint64_t SH_FLD_X2_TX_ENABLE = 19087; // 4 -static const uint64_t SH_FLD_X2_TX_SELECT = 19088; // 4 -static const uint64_t SH_FLD_X2_TX_SELECT_LEN = 19089; // 4 -static const uint64_t SH_FLD_X3_TX_ENABLE = 19090; // 4 -static const uint64_t SH_FLD_X3_TX_SELECT = 19091; // 4 -static const uint64_t SH_FLD_X3_TX_SELECT_LEN = 19092; // 4 -static const uint64_t SH_FLD_X4_TX_ENABLE = 19093; // 4 -static const uint64_t SH_FLD_X4_TX_SELECT = 19094; // 4 -static const uint64_t SH_FLD_X4_TX_SELECT_LEN = 19095; // 4 -static const uint64_t SH_FLD_X5_TX_ENABLE = 19096; // 4 -static const uint64_t SH_FLD_X5_TX_SELECT = 19097; // 4 -static const uint64_t SH_FLD_X5_TX_SELECT_LEN = 19098; // 4 -static const uint64_t SH_FLD_X6_TX_ENABLE = 19099; // 4 -static const uint64_t SH_FLD_X6_TX_SELECT = 19100; // 4 -static const uint64_t SH_FLD_X6_TX_SELECT_LEN = 19101; // 4 -static const uint64_t SH_FLD_X7_TX_ENABLE = 19102; // 4 -static const uint64_t SH_FLD_X7_TX_SELECT = 19103; // 4 -static const uint64_t SH_FLD_X7_TX_SELECT_LEN = 19104; // 4 -static const uint64_t SH_FLD_XARS = 19105; // 3 -static const uint64_t SH_FLD_XARSP = 19106; // 12 -static const uint64_t SH_FLD_XATS = 19107; // 12 -static const uint64_t SH_FLD_XCR = 19108; // 21 -static const uint64_t SH_FLD_XCR_LEN = 19109; // 21 -static const uint64_t SH_FLD_XIMEM_MEM_IFETCH_PENDING = 19110; // 21 -static const uint64_t SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 19111; // 21 -static const uint64_t SH_FLD_XIRAMGA_IR = 19112; // 21 -static const uint64_t SH_FLD_XIRAMGA_IR_LEN = 19113; // 21 -static const uint64_t SH_FLD_XIRAMRA_SPRG0 = 19114; // 42 -static const uint64_t SH_FLD_XIRAMRA_SPRG0_LEN = 19115; // 42 -static const uint64_t SH_FLD_XISIB_PIB_IFETCH_PENDING = 19116; // 1 -static const uint64_t SH_FLD_XIXCR_XCR = 19117; // 21 -static const uint64_t SH_FLD_XIXCR_XCR_LEN = 19118; // 21 -static const uint64_t SH_FLD_XLAT = 19119; // 16 -static const uint64_t SH_FLD_XLATE_TO_ADDR_ID_ENABLE = 19120; // 2 -static const uint64_t SH_FLD_XLAT_LEN = 19121; // 16 -static const uint64_t SH_FLD_XPT_ERROR_INJECT_ENABLE = 19122; // 2 -static const uint64_t SH_FLD_XPT_ERROR_INJECT_TARGET = 19123; // 2 -static const uint64_t SH_FLD_XPT_ERROR_INJECT_TARGET_LEN = 19124; // 2 -static const uint64_t SH_FLD_XPT_ERROR_TYPE = 19125; // 2 -static const uint64_t SH_FLD_XPT_ERROR_TYPE_LEN = 19126; // 2 -static const uint64_t SH_FLD_XPT_INJECT_CONTINUOUS_ERROR = 19127; // 2 -static const uint64_t SH_FLD_XPT_POWERBUS_CE = 19128; // 4 -static const uint64_t SH_FLD_XPT_POWERBUS_SUE = 19129; // 4 -static const uint64_t SH_FLD_XPT_POWERBUS_UE = 19130; // 4 -static const uint64_t SH_FLD_XPT_RECOVERABLE_ERROR = 19131; // 4 -static const uint64_t SH_FLD_XPT_SYS_XSTOP_ERROR = 19132; // 4 -static const uint64_t SH_FLD_XSCOM_DONE = 19133; // 96 -static const uint64_t SH_FLD_XSCOM_FAIL = 19134; // 96 -static const uint64_t SH_FLD_XSCOM_STATUS = 19135; // 96 -static const uint64_t SH_FLD_XSCOM_STATUS_LEN = 19136; // 96 -static const uint64_t SH_FLD_XSC_CMD_OVERRUN = 19137; // 1 -static const uint64_t SH_FLD_XSTOP = 19138; // 5 -static const uint64_t SH_FLD_XSTOP_GATE = 19139; // 1 -static const uint64_t SH_FLD_XTS_CONFIG_P = 19140; // 1 -static const uint64_t SH_FLD_XTS_INT = 19141; // 1 -static const uint64_t SH_FLD_XTS_PBUS_PROTOCOL = 19142; // 1 -static const uint64_t SH_FLD_XTS_PROTOCOL_CE = 19143; // 1 -static const uint64_t SH_FLD_XTS_PROTOCOL_UE = 19144; // 1 -static const uint64_t SH_FLD_XTS_RSVD_10 = 19145; // 1 -static const uint64_t SH_FLD_XTS_RSVD_11 = 19146; // 1 -static const uint64_t SH_FLD_XTS_RSVD_12 = 19147; // 1 -static const uint64_t SH_FLD_XTS_RSVD_13 = 19148; // 1 -static const uint64_t SH_FLD_XTS_RSVD_14 = 19149; // 1 -static const uint64_t SH_FLD_XTS_RSVD_15 = 19150; // 1 -static const uint64_t SH_FLD_XTS_RSVD_16 = 19151; // 1 -static const uint64_t SH_FLD_XTS_RSVD_17 = 19152; // 1 -static const uint64_t SH_FLD_XTS_RSVD_18 = 19153; // 1 -static const uint64_t SH_FLD_XTS_RSVD_19 = 19154; // 1 -static const uint64_t SH_FLD_XTS_RSVD_6 = 19155; // 1 -static const uint64_t SH_FLD_XTS_RSVD_7 = 19156; // 1 -static const uint64_t SH_FLD_XTS_RSVD_8 = 19157; // 1 -static const uint64_t SH_FLD_XTS_RSVD_9 = 19158; // 1 -static const uint64_t SH_FLD_XTS_SRAM_CE = 19159; // 1 -static const uint64_t SH_FLD_XTS_SRAM_UE = 19160; // 1 -static const uint64_t SH_FLD_Z = 19161; // 1 -static const uint64_t SH_FLD_ZCAL = 19162; // 12 -static const uint64_t SH_FLD_ZCAL_CYA_DATA_INV = 19163; // 4 -static const uint64_t SH_FLD_ZCAL_LEN = 19164; // 4 -static const uint64_t SH_FLD_ZCAL_N = 19165; // 4 -static const uint64_t SH_FLD_ZCAL_N_LEN = 19166; // 4 -static const uint64_t SH_FLD_ZCAL_P = 19167; // 4 -static const uint64_t SH_FLD_ZCAL_P_LEN = 19168; // 4 -static const uint64_t SH_FLD_ZCAL_RANGE_CHECK = 19169; // 4 -static const uint64_t SH_FLD_ZCAL_SM_MAX_VAL = 19170; // 4 -static const uint64_t SH_FLD_ZCAL_SM_MAX_VAL_LEN = 19171; // 4 -static const uint64_t SH_FLD_ZCAL_SM_MIN_VAL = 19172; // 4 -static const uint64_t SH_FLD_ZCAL_SM_MIN_VAL_LEN = 19173; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_CAL_SEGS = 19174; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_CMP_INV = 19175; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_CMP_OFFSET = 19176; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_CMP_RESET = 19177; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_EN = 19178; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_POWERDOWN = 19179; // 4 -static const uint64_t SH_FLD_ZCAL_SWO_TCOIL = 19180; // 4 -static const uint64_t SH_FLD_ZCAL_TEST_CLK_DIV = 19181; // 4 -static const uint64_t SH_FLD_ZCAL_TEST_OVR_1R = 19182; // 4 -static const uint64_t SH_FLD_ZCAL_TEST_OVR_2R = 19183; // 4 -static const uint64_t SH_FLD_ZCAL_TEST_OVR_4X_SEG = 19184; // 4 +static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY0 = 506; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 = 507; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN = 508; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN = 509; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE = 510; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN = 511; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER = 512; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN = 513; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER = 514; // 32 +static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN = 515; // 32 +static const uint64_t SH_FLD_01_RESERVED_63 = 516; // 64 +static const uint64_t SH_FLD_01_ROT0 = 517; // 16 +static const uint64_t SH_FLD_01_ROT0_LEN = 518; // 16 +static const uint64_t SH_FLD_01_ROT1 = 519; // 16 +static const uint64_t SH_FLD_01_ROT1_LEN = 520; // 16 +static const uint64_t SH_FLD_01_ROT_CLK_N0 = 521; // 128 +static const uint64_t SH_FLD_01_ROT_CLK_N0_LEN = 522; // 128 +static const uint64_t SH_FLD_01_ROT_CLK_N1 = 523; // 128 +static const uint64_t SH_FLD_01_ROT_CLK_N1_LEN = 524; // 128 +static const uint64_t SH_FLD_01_ROT_N0 = 525; // 128 +static const uint64_t SH_FLD_01_ROT_N0_LEN = 526; // 128 +static const uint64_t SH_FLD_01_ROT_N1 = 527; // 128 +static const uint64_t SH_FLD_01_ROT_N1_LEN = 528; // 128 +static const uint64_t SH_FLD_01_ROT_OVERRIDE = 529; // 32 +static const uint64_t SH_FLD_01_ROT_OVERRIDE_EN = 530; // 32 +static const uint64_t SH_FLD_01_ROT_OVERRIDE_LEN = 531; // 32 +static const uint64_t SH_FLD_01_RXCAL_DETECT_DONE_META = 532; // 32 +static const uint64_t SH_FLD_01_RXCAL_PD_CAL_LAG_META = 533; // 32 +static const uint64_t SH_FLD_01_RXCAL_PD_MAIN_LAG_META = 534; // 32 +static const uint64_t SH_FLD_01_RXCAL_PD_MAIN_LEAD_META = 535; // 32 +static const uint64_t SH_FLD_01_RXREG_COMPCON_DC = 536; // 32 +static const uint64_t SH_FLD_01_RXREG_COMPCON_DC_LEN = 537; // 32 +static const uint64_t SH_FLD_01_RXREG_CON_DC = 538; // 32 +static const uint64_t SH_FLD_01_RXREG_DAC_PULLUP_DC = 539; // 32 +static const uint64_t SH_FLD_01_RXREG_DRVCON_DC = 540; // 32 +static const uint64_t SH_FLD_01_RXREG_DRVCON_DC_LEN = 541; // 32 +static const uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC = 542; // 32 +static const uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN = 543; // 32 +static const uint64_t SH_FLD_01_RXREG_FINECAL_2XILSB_DC = 544; // 32 +static const uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC = 545; // 32 +static const uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 546; // 32 +static const uint64_t SH_FLD_01_RXREG_REF_SEL_DC = 547; // 32 +static const uint64_t SH_FLD_01_RXREG_REF_SEL_DC_LEN = 548; // 32 +static const uint64_t SH_FLD_01_S0ACENSLICENDRV_DC = 549; // 16 +static const uint64_t SH_FLD_01_S0ACENSLICENDRV_DC_LEN = 550; // 16 +static const uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC = 551; // 16 +static const uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC_LEN = 552; // 16 +static const uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC = 553; // 16 +static const uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC_LEN = 554; // 16 +static const uint64_t SH_FLD_01_S0INSDLYTAP = 555; // 16 +static const uint64_t SH_FLD_01_S1ACENSLICENDRV_DC = 556; // 16 +static const uint64_t SH_FLD_01_S1ACENSLICENDRV_DC_LEN = 557; // 16 +static const uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC = 558; // 16 +static const uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC_LEN = 559; // 16 +static const uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC = 560; // 16 +static const uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC_LEN = 561; // 16 +static const uint64_t SH_FLD_01_S1INSDLYTAP = 562; // 16 +static const uint64_t SH_FLD_01_SEL0 = 563; // 32 +static const uint64_t SH_FLD_01_SEL0_LEN = 564; // 16 +static const uint64_t SH_FLD_01_SEL1 = 565; // 32 +static const uint64_t SH_FLD_01_SEL10 = 566; // 32 +static const uint64_t SH_FLD_01_SEL10_LEN = 567; // 32 +static const uint64_t SH_FLD_01_SEL11 = 568; // 32 +static const uint64_t SH_FLD_01_SEL11_LEN = 569; // 32 +static const uint64_t SH_FLD_01_SEL12 = 570; // 32 +static const uint64_t SH_FLD_01_SEL12_LEN = 571; // 32 +static const uint64_t SH_FLD_01_SEL13 = 572; // 32 +static const uint64_t SH_FLD_01_SEL13_LEN = 573; // 32 +static const uint64_t SH_FLD_01_SEL14 = 574; // 32 +static const uint64_t SH_FLD_01_SEL14_LEN = 575; // 32 +static const uint64_t SH_FLD_01_SEL15 = 576; // 32 +static const uint64_t SH_FLD_01_SEL15_LEN = 577; // 32 +static const uint64_t SH_FLD_01_SEL1_LEN = 578; // 32 +static const uint64_t SH_FLD_01_SEL2 = 579; // 32 +static const uint64_t SH_FLD_01_SEL2_LEN = 580; // 32 +static const uint64_t SH_FLD_01_SEL3 = 581; // 32 +static const uint64_t SH_FLD_01_SEL3_LEN = 582; // 32 +static const uint64_t SH_FLD_01_SEL4 = 583; // 32 +static const uint64_t SH_FLD_01_SEL4_LEN = 584; // 32 +static const uint64_t SH_FLD_01_SEL5 = 585; // 32 +static const uint64_t SH_FLD_01_SEL5_LEN = 586; // 32 +static const uint64_t SH_FLD_01_SEL6 = 587; // 32 +static const uint64_t SH_FLD_01_SEL6_LEN = 588; // 32 +static const uint64_t SH_FLD_01_SEL7 = 589; // 32 +static const uint64_t SH_FLD_01_SEL7_LEN = 590; // 32 +static const uint64_t SH_FLD_01_SEL8 = 591; // 32 +static const uint64_t SH_FLD_01_SEL8_LEN = 592; // 16 +static const uint64_t SH_FLD_01_SEL9 = 593; // 32 +static const uint64_t SH_FLD_01_SEL9_LEN = 594; // 32 +static const uint64_t SH_FLD_01_SEL_A = 595; // 16 +static const uint64_t SH_FLD_01_SEL_A_LEN = 596; // 16 +static const uint64_t SH_FLD_01_SEL_B = 597; // 16 +static const uint64_t SH_FLD_01_SEL_B_LEN = 598; // 16 +static const uint64_t SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN = 599; // 32 +static const uint64_t SH_FLD_01_SLAVE_VREG_DAC_COARSE = 600; // 32 +static const uint64_t SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN = 601; // 32 +static const uint64_t SH_FLD_01_SLAVE_VREG_OVERRIDE = 602; // 32 +static const uint64_t SH_FLD_01_SLAVE_VREG_REF_SEL_DC = 603; // 32 +static const uint64_t SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN = 604; // 32 +static const uint64_t SH_FLD_01_SMALL_STEP_LEFT = 605; // 16 +static const uint64_t SH_FLD_01_SMALL_STEP_RIGHT = 606; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE = 607; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR0 = 608; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR1 = 609; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR2 = 610; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR3 = 611; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK1 = 612; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK2 = 613; // 16 +static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK3 = 614; // 16 +static const uint64_t SH_FLD_01_SYNC = 615; // 16 +static const uint64_t SH_FLD_01_SYNC_LEN = 616; // 16 +static const uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET = 617; // 16 +static const uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN = 618; // 16 +static const uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET = 619; // 16 +static const uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN = 620; // 16 +static const uint64_t SH_FLD_01_TEST_4TO1_MODE = 621; // 16 +static const uint64_t SH_FLD_01_TEST_CHECK_EN = 622; // 16 +static const uint64_t SH_FLD_01_TEST_CLEAR_ERROR = 623; // 16 +static const uint64_t SH_FLD_01_TEST_DATA_EN = 624; // 16 +static const uint64_t SH_FLD_01_TEST_GEN_EN = 625; // 16 +static const uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL = 626; // 16 +static const uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN = 627; // 16 +static const uint64_t SH_FLD_01_TEST_MODE = 628; // 16 +static const uint64_t SH_FLD_01_TEST_MODE_LEN = 629; // 16 +static const uint64_t SH_FLD_01_TEST_RESET = 630; // 16 +static const uint64_t SH_FLD_01_TRAILING_EDGE_FOUND_MASK = 631; // 16 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND = 632; // 16 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 = 633; // 8 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 634; // 8 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 = 635; // 8 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 636; // 8 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 = 637; // 16 +static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 638; // 16 +static const uint64_t SH_FLD_01_TRIG_PERIOD = 639; // 16 +static const uint64_t SH_FLD_01_TSYS = 640; // 16 +static const uint64_t SH_FLD_01_TSYS_LEN = 641; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE = 642; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 = 643; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 = 644; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 = 645; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 = 646; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 = 647; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 = 648; // 16 +static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 = 649; // 16 +static const uint64_t SH_FLD_01_UPPER = 650; // 32 +static const uint64_t SH_FLD_01_UPPER_LEN = 651; // 32 +static const uint64_t SH_FLD_01_VALID_NS_BIG_L = 652; // 16 +static const uint64_t SH_FLD_01_VALID_NS_BIG_L_MASK = 653; // 16 +static const uint64_t SH_FLD_01_VALID_NS_BIG_R = 654; // 16 +static const uint64_t SH_FLD_01_VALID_NS_BIG_R_MASK = 655; // 16 +static const uint64_t SH_FLD_01_VALID_NS_JUMP_BACK = 656; // 16 +static const uint64_t SH_FLD_01_VALID_NS_JUMP_BACK_MASK = 657; // 16 +static const uint64_t SH_FLD_01_VALUE_DRAM0 = 658; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM0_LEN = 659; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM1 = 660; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM1_LEN = 661; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM2 = 662; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM2_LEN = 663; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM3 = 664; // 64 +static const uint64_t SH_FLD_01_VALUE_DRAM3_LEN = 665; // 64 +static const uint64_t SH_FLD_01_VREG_RXCAL_COMP_OUT_META = 666; // 32 +static const uint64_t SH_FLD_01_VREG_SLAVE_COMP_OUT = 667; // 32 +static const uint64_t SH_FLD_01_WL_ADVANCE_DISABLE = 668; // 16 +static const uint64_t SH_FLD_01_WL_ERR_CLK16 = 669; // 32 +static const uint64_t SH_FLD_01_WL_ERR_CLK16_MASK = 670; // 16 +static const uint64_t SH_FLD_01_WL_ERR_CLK18 = 671; // 32 +static const uint64_t SH_FLD_01_WL_ERR_CLK18_MASK = 672; // 16 +static const uint64_t SH_FLD_01_WL_ERR_CLK20 = 673; // 32 +static const uint64_t SH_FLD_01_WL_ERR_CLK20_MASK = 674; // 16 +static const uint64_t SH_FLD_01_WL_ERR_CLK22 = 675; // 32 +static const uint64_t SH_FLD_01_WRAPSEL = 676; // 16 +static const uint64_t SH_FLD_01_WTRFL_AVE_DIS = 677; // 16 +static const uint64_t SH_FLD_01_ZERO_DETECTED = 678; // 16 +static const uint64_t SH_FLD_0X00_DATA_PARITY = 679; // 4 +static const uint64_t SH_FLD_0X00_SPARE_30_31 = 680; // 1 +static const uint64_t SH_FLD_0X00_SPARE_30_31_LEN = 681; // 1 +static const uint64_t SH_FLD_0X01_DATA_PARITY = 682; // 4 +static const uint64_t SH_FLD_0X01_SPARE_03 = 683; // 1 +static const uint64_t SH_FLD_0X01_SPARE_28_31 = 684; // 1 +static const uint64_t SH_FLD_0X01_SPARE_28_31_LEN = 685; // 1 +static const uint64_t SH_FLD_0X02_DATA_PARITY = 686; // 4 +static const uint64_t SH_FLD_0X02_SPARE_03 = 687; // 1 +static const uint64_t SH_FLD_0X02_SPARE_28_31 = 688; // 1 +static const uint64_t SH_FLD_0X02_SPARE_28_31_LEN = 689; // 1 +static const uint64_t SH_FLD_0X03_DATA_PARITY = 690; // 4 +static const uint64_t SH_FLD_0X03_SPARE_03 = 691; // 1 +static const uint64_t SH_FLD_0X03_SPARE_28_31 = 692; // 1 +static const uint64_t SH_FLD_0X03_SPARE_28_31_LEN = 693; // 1 +static const uint64_t SH_FLD_0X04_DATA_PARITY = 694; // 4 +static const uint64_t SH_FLD_0X04_SPARE_03 = 695; // 1 +static const uint64_t SH_FLD_0X04_SPARE_28_31 = 696; // 1 +static const uint64_t SH_FLD_0X04_SPARE_28_31_LEN = 697; // 1 +static const uint64_t SH_FLD_0X05_DATA_PARITY = 698; // 4 +static const uint64_t SH_FLD_0X05_SPARE_01 = 699; // 1 +static const uint64_t SH_FLD_0X05_SPARE_05 = 700; // 1 +static const uint64_t SH_FLD_0X06_DATA_PARITY = 701; // 4 +static const uint64_t SH_FLD_0X06_SPARE_02_04 = 702; // 1 +static const uint64_t SH_FLD_0X06_SPARE_02_04_LEN = 703; // 1 +static const uint64_t SH_FLD_0X06_SPARE_16_21 = 704; // 1 +static const uint64_t SH_FLD_0X06_SPARE_16_21_LEN = 705; // 1 +static const uint64_t SH_FLD_0X07_DATA_PARITY = 706; // 4 +static const uint64_t SH_FLD_0X07_SPARE_19 = 707; // 1 +static const uint64_t SH_FLD_0X07_SPARE_20 = 708; // 1 +static const uint64_t SH_FLD_0X07_SPARE_22_31 = 709; // 1 +static const uint64_t SH_FLD_0X07_SPARE_22_31_LEN = 710; // 1 +static const uint64_t SH_FLD_0X08_DATA_PARITY = 711; // 4 +static const uint64_t SH_FLD_0X08_SPARE_03 = 712; // 1 +static const uint64_t SH_FLD_0X08_SPARE_30 = 713; // 1 +static const uint64_t SH_FLD_0X09_DATA_PARITY = 714; // 4 +static const uint64_t SH_FLD_0X0A_DATA_PARITY = 715; // 4 +static const uint64_t SH_FLD_0X0A_SPARE_13_15 = 716; // 1 +static const uint64_t SH_FLD_0X0A_SPARE_13_15_LEN = 717; // 1 +static const uint64_t SH_FLD_0X0B_DATA_PARITY = 718; // 4 +static const uint64_t SH_FLD_0X0B_SPARE_04_05 = 719; // 1 +static const uint64_t SH_FLD_0X0B_SPARE_04_05_LEN = 720; // 1 +static const uint64_t SH_FLD_0X0B_SPARE_17 = 721; // 1 +static const uint64_t SH_FLD_0X0B_SPARE_33_39 = 722; // 1 +static const uint64_t SH_FLD_0X0B_SPARE_33_39_LEN = 723; // 1 +static const uint64_t SH_FLD_0X0C_DATA_PARITY = 724; // 4 +static const uint64_t SH_FLD_0X0D_SPARE_60_62 = 725; // 1 +static const uint64_t SH_FLD_0X0D_SPARE_60_62_LEN = 726; // 1 +static const uint64_t SH_FLD_0X10_DATA_PARITY = 727; // 4 +static const uint64_t SH_FLD_0X10_SPARE_17_18 = 728; // 1 +static const uint64_t SH_FLD_0X10_SPARE_17_18_LEN = 729; // 1 +static const uint64_t SH_FLD_0X10_SPARE_19_23 = 730; // 1 +static const uint64_t SH_FLD_0X10_SPARE_19_23_LEN = 731; // 1 +static const uint64_t SH_FLD_0X10_SPARE_24_25 = 732; // 1 +static const uint64_t SH_FLD_0X10_SPARE_24_25_LEN = 733; // 1 +static const uint64_t SH_FLD_0X10_SPARE_27 = 734; // 1 +static const uint64_t SH_FLD_0X10_SPARE_29 = 735; // 1 +static const uint64_t SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 736; // 4 +static const uint64_t SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY = 737; // 4 +static const uint64_t SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY = 738; // 4 +static const uint64_t SH_FLD_0X20_DATA_PARITY = 739; // 4 +static const uint64_t SH_FLD_0X22_SPARE_01 = 740; // 1 +static const uint64_t SH_FLD_0X22_SPARE_03_07 = 741; // 1 +static const uint64_t SH_FLD_0X22_SPARE_03_07_LEN = 742; // 1 +static const uint64_t SH_FLD_0X23_DATA_PARITY = 743; // 4 +static const uint64_t SH_FLD_0X23_SPARE_06_07 = 744; // 1 +static const uint64_t SH_FLD_0X23_SPARE_06_07_LEN = 745; // 1 +static const uint64_t SH_FLD_0X24_DATA_PARITY = 746; // 4 +static const uint64_t SH_FLD_0X24_SPARE_05_07 = 747; // 1 +static const uint64_t SH_FLD_0X24_SPARE_05_07_LEN = 748; // 1 +static const uint64_t SH_FLD_0X27_DATA_PARITY = 749; // 4 +static const uint64_t SH_FLD_0X27_SPARE_34 = 750; // 1 +static const uint64_t SH_FLD_0X27_SPARE_36 = 751; // 1 +static const uint64_t SH_FLD_0X29_DATA_PARITY = 752; // 4 +static const uint64_t SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY = 753; // 4 +static const uint64_t SH_FLD_0_2 = 754; // 16 +static const uint64_t SH_FLD_0_CANNED_0 = 755; // 2 +static const uint64_t SH_FLD_0_CANNED_0_LEN = 756; // 2 +static const uint64_t SH_FLD_0_CANNED_1 = 757; // 2 +static const uint64_t SH_FLD_0_CANNED_1_LEN = 758; // 2 +static const uint64_t SH_FLD_0_CPS = 759; // 2 +static const uint64_t SH_FLD_0_CPS_LEN = 760; // 2 +static const uint64_t SH_FLD_0_DATA = 761; // 1 +static const uint64_t SH_FLD_0_DATA_LEN = 762; // 1 +static const uint64_t SH_FLD_0_LEN = 763; // 62 +static const uint64_t SH_FLD_0_LOCAL_STEP_MODE_ENABLE = 764; // 1 +static const uint64_t SH_FLD_0_OSC_NOT_VALID = 765; // 1 +static const uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT = 766; // 1 +static const uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 767; // 1 +static const uint64_t SH_FLD_0_RESULT = 768; // 43 +static const uint64_t SH_FLD_0_RESULT_LEN = 769; // 43 +static const uint64_t SH_FLD_0_SELECT = 770; // 1 +static const uint64_t SH_FLD_0_SELECT_LEN = 771; // 1 +static const uint64_t SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL = 772; // 3 +static const uint64_t SH_FLD_0_STEP_ALIGN_DISABLE = 773; // 1 +static const uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD = 774; // 1 +static const uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN = 775; // 1 +static const uint64_t SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 776; // 2 +static const uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION = 777; // 2 +static const uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN = 778; // 2 +static const uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT = 779; // 2 +static const uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN = 780; // 2 +static const uint64_t SH_FLD_0_STEP_STEER_ENABLE = 781; // 1 +static const uint64_t SH_FLD_1 = 782; // 525 +static const uint64_t SH_FLD_10 = 783; // 8 +static const uint64_t SH_FLD_10_RESERVED = 784; // 3 +static const uint64_t SH_FLD_10_SPARE_REFCLOCK = 785; // 3 +static const uint64_t SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL = 786; // 3 +static const uint64_t SH_FLD_11 = 787; // 8 +static const uint64_t SH_FLD_11_RESERVED = 788; // 3 +static const uint64_t SH_FLD_11_SPARE_REFCLOCK = 789; // 3 +static const uint64_t SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL = 790; // 3 +static const uint64_t SH_FLD_12 = 791; // 8 +static const uint64_t SH_FLD_12GB_ENABLE = 792; // 8 +static const uint64_t SH_FLD_12_RESERVED = 793; // 3 +static const uint64_t SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL = 794; // 3 +static const uint64_t SH_FLD_13 = 795; // 8 +static const uint64_t SH_FLD_13_RESERVED = 796; // 3 +static const uint64_t SH_FLD_13_SPARE_OPB_CONTROL = 797; // 3 +static const uint64_t SH_FLD_13_SPARE_PROBE = 798; // 3 +static const uint64_t SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL = 799; // 3 +static const uint64_t SH_FLD_14 = 800; // 8 +static const uint64_t SH_FLD_14_RESERVED = 801; // 3 +static const uint64_t SH_FLD_14_SPARE_OPB_CONTROL = 802; // 3 +static const uint64_t SH_FLD_14_SPARE_PLL = 803; // 3 +static const uint64_t SH_FLD_14_SPARE_PROBE = 804; // 3 +static const uint64_t SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL = 805; // 3 +static const uint64_t SH_FLD_15 = 806; // 8 +static const uint64_t SH_FLD_15_RESERVED = 807; // 3 +static const uint64_t SH_FLD_15_SPARE_OPB_CONTROL = 808; // 3 +static const uint64_t SH_FLD_15_SPARE_OSC = 809; // 3 +static const uint64_t SH_FLD_15_SPARE_PLL = 810; // 3 +static const uint64_t SH_FLD_15_SPARE_PROBE = 811; // 3 +static const uint64_t SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL = 812; // 3 +static const uint64_t SH_FLD_16 = 813; // 6 +static const uint64_t SH_FLD_16_SPARE_OSC = 814; // 3 +static const uint64_t SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL = 815; // 3 +static const uint64_t SH_FLD_17 = 816; // 6 +static const uint64_t SH_FLD_17_SPARE_OSC = 817; // 3 +static const uint64_t SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL = 818; // 3 +static const uint64_t SH_FLD_18 = 819; // 6 +static const uint64_t SH_FLD_18_31_SPARE = 820; // 8 +static const uint64_t SH_FLD_18_31_SPARE_LEN = 821; // 8 +static const uint64_t SH_FLD_18_SPARE_MUX_CONTROL = 822; // 3 +static const uint64_t SH_FLD_18_SPARE_OSC = 823; // 3 +static const uint64_t SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL = 824; // 3 +static const uint64_t SH_FLD_19 = 825; // 6 +static const uint64_t SH_FLD_19_SPARE_MUX_CONTROL = 826; // 3 +static const uint64_t SH_FLD_19_SPARE_OSC = 827; // 3 +static const uint64_t SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL = 828; // 3 +static const uint64_t SH_FLD_1_3 = 829; // 16 +static const uint64_t SH_FLD_1_CANNED_0 = 830; // 2 +static const uint64_t SH_FLD_1_CANNED_0_LEN = 831; // 2 +static const uint64_t SH_FLD_1_CANNED_1 = 832; // 2 +static const uint64_t SH_FLD_1_CANNED_1_LEN = 833; // 2 +static const uint64_t SH_FLD_1_CPS = 834; // 2 +static const uint64_t SH_FLD_1_CPS_LEN = 835; // 2 +static const uint64_t SH_FLD_1_DATA = 836; // 1 +static const uint64_t SH_FLD_1_DATA_LEN = 837; // 1 +static const uint64_t SH_FLD_1_LEN = 838; // 105 +static const uint64_t SH_FLD_1_LOCAL_STEP_MODE_ENABLE = 839; // 1 +static const uint64_t SH_FLD_1_OSC_NOT_VALID = 840; // 1 +static const uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT = 841; // 1 +static const uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 842; // 1 +static const uint64_t SH_FLD_1_RESULT = 843; // 43 +static const uint64_t SH_FLD_1_RESULT_LEN = 844; // 43 +static const uint64_t SH_FLD_1_SELECT = 845; // 1 +static const uint64_t SH_FLD_1_SELECT_LEN = 846; // 1 +static const uint64_t SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL = 847; // 3 +static const uint64_t SH_FLD_1_STEP_ALIGN_DISABLE = 848; // 1 +static const uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD = 849; // 1 +static const uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN = 850; // 1 +static const uint64_t SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 851; // 2 +static const uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION = 852; // 2 +static const uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN = 853; // 2 +static const uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT = 854; // 2 +static const uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN = 855; // 2 +static const uint64_t SH_FLD_1_STEP_STEER_ENABLE = 856; // 1 +static const uint64_t SH_FLD_1_UNUSED = 857; // 1 +static const uint64_t SH_FLD_2 = 858; // 466 +static const uint64_t SH_FLD_20 = 859; // 6 +static const uint64_t SH_FLD_20_RESERVED = 860; // 3 +static const uint64_t SH_FLD_20_SPARE_OSC = 861; // 3 +static const uint64_t SH_FLD_20_SPARE_PLL_CONTROL = 862; // 3 +static const uint64_t SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL = 863; // 3 +static const uint64_t SH_FLD_21 = 864; // 6 +static const uint64_t SH_FLD_21_FREE_USAGE = 865; // 3 +static const uint64_t SH_FLD_21_RESERVED = 866; // 3 +static const uint64_t SH_FLD_21_SPARE_OSC = 867; // 3 +static const uint64_t SH_FLD_21_SPARE_PLL_CONTROL = 868; // 3 +static const uint64_t SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL = 869; // 3 +static const uint64_t SH_FLD_22 = 870; // 6 +static const uint64_t SH_FLD_22_FREE_USAGE = 871; // 3 +static const uint64_t SH_FLD_22_RESERVED = 872; // 6 +static const uint64_t SH_FLD_22_SPARE_OSC = 873; // 3 +static const uint64_t SH_FLD_22_SPARE_PLL_CONTROL = 874; // 3 +static const uint64_t SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL = 875; // 3 +static const uint64_t SH_FLD_22_SPARE_TEST = 876; // 3 +static const uint64_t SH_FLD_23 = 877; // 134 +static const uint64_t SH_FLD_23_0_11 = 878; // 16 +static const uint64_t SH_FLD_23_0_11_LEN = 879; // 16 +static const uint64_t SH_FLD_23_12_15 = 880; // 16 +static const uint64_t SH_FLD_23_12_15_LEN = 881; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE = 882; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR0 = 883; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR1 = 884; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR2 = 885; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR3 = 886; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK1 = 887; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK2 = 888; // 16 +static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK3 = 889; // 16 +static const uint64_t SH_FLD_23_ADVANCE_PING_PONG = 890; // 16 +static const uint64_t SH_FLD_23_ADVANCE_PR_VALUE = 891; // 16 +static const uint64_t SH_FLD_23_ATESTSEL_0_4 = 892; // 16 +static const uint64_t SH_FLD_23_ATESTSEL_0_4_LEN = 893; // 16 +static const uint64_t SH_FLD_23_ATEST_SEL_0_1 = 894; // 16 +static const uint64_t SH_FLD_23_ATEST_SEL_0_1_LEN = 895; // 16 +static const uint64_t SH_FLD_23_BAD_BIT = 896; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_ERR0 = 897; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_ERR1 = 898; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_ERR2 = 899; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_ERR3 = 900; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_MASK1 = 901; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_MASK2 = 902; // 16 +static const uint64_t SH_FLD_23_BAD_BIT_MASK3 = 903; // 16 +static const uint64_t SH_FLD_23_BB_LOCK0 = 904; // 16 +static const uint64_t SH_FLD_23_BB_LOCK1 = 905; // 16 +static const uint64_t SH_FLD_23_BIG_STEP_RIGHT = 906; // 16 +static const uint64_t SH_FLD_23_BIT_CENTERED = 907; // 16 +static const uint64_t SH_FLD_23_BIT_CENTERED_LEN = 908; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA = 909; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR0 = 910; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR1 = 911; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR2 = 912; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR3 = 913; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK1 = 914; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK2 = 915; // 16 +static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK3 = 916; // 16 +static const uint64_t SH_FLD_23_BLFIFO_DIS = 917; // 16 +static const uint64_t SH_FLD_23_BUMP = 918; // 16 +static const uint64_t SH_FLD_23_CALGATE_ON = 919; // 16 +static const uint64_t SH_FLD_23_CALIBRATE_BIT = 920; // 16 +static const uint64_t SH_FLD_23_CALIBRATE_BIT_LEN = 921; // 16 +static const uint64_t SH_FLD_23_CAL_CKTS_ACTIVE = 922; // 32 +static const uint64_t SH_FLD_23_CAL_ERROR = 923; // 32 +static const uint64_t SH_FLD_23_CAL_ERROR_FINE = 924; // 32 +static const uint64_t SH_FLD_23_CAL_GOOD = 925; // 32 +static const uint64_t SH_FLD_23_CAL_PD_ENABLE = 926; // 32 +static const uint64_t SH_FLD_23_CHECKER_ENABLE = 927; // 16 +static const uint64_t SH_FLD_23_CHECKER_RESET = 928; // 16 +static const uint64_t SH_FLD_23_CHICKSW_HW278227 = 929; // 16 +static const uint64_t SH_FLD_23_CLK16_SINGLE_ENDED = 930; // 64 +static const uint64_t SH_FLD_23_CLK18_SINGLE_ENDED = 931; // 64 +static const uint64_t SH_FLD_23_CLK20_SINGLE_ENDED = 932; // 64 +static const uint64_t SH_FLD_23_CLK22_SINGLE_ENDED = 933; // 64 +static const uint64_t SH_FLD_23_CLK_LEVEL = 934; // 16 +static const uint64_t SH_FLD_23_CLK_LEVEL_LEN = 935; // 16 +static const uint64_t SH_FLD_23_CNTL_POL = 936; // 16 +static const uint64_t SH_FLD_23_CNTL_SRC = 937; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0 = 938; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK = 939; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1 = 940; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK = 941; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2 = 942; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK = 943; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3 = 944; // 16 +static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK = 945; // 16 +static const uint64_t SH_FLD_23_CONTINUOUS_UPDATE = 946; // 32 +static const uint64_t SH_FLD_23_CTR_1D_CHICKEN_SWITCH = 947; // 16 +static const uint64_t SH_FLD_23_CTR_2D_BIG_STEP_VAL = 948; // 16 +static const uint64_t SH_FLD_23_CTR_2D_BIG_STEP_VAL_LEN = 949; // 16 +static const uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL = 950; // 16 +static const uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN = 951; // 16 +static const uint64_t SH_FLD_23_CTR_CUR = 952; // 16 +static const uint64_t SH_FLD_23_CTR_CUR_LEN = 953; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP = 954; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN = 955; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP = 956; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN = 957; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT = 958; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN = 959; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT = 960; // 16 +static const uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN = 961; // 16 +static const uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER = 962; // 16 +static const uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER_LEN = 963; // 16 +static const uint64_t SH_FLD_23_CTR_RANGE_SELECT = 964; // 16 +static const uint64_t SH_FLD_23_CTR_RUN_FULL_1D = 965; // 16 +static const uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX = 966; // 16 +static const uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN = 967; // 16 +static const uint64_t SH_FLD_23_DD2_DQS_FIX_DIS = 968; // 16 +static const uint64_t SH_FLD_23_DD2_FIX_DIS = 969; // 16 +static const uint64_t SH_FLD_23_DD2_WTRFL_SYNC_DIS = 970; // 16 +static const uint64_t SH_FLD_23_DELAY1 = 971; // 16 +static const uint64_t SH_FLD_23_DELAY10 = 972; // 16 +static const uint64_t SH_FLD_23_DELAY10_LEN = 973; // 16 +static const uint64_t SH_FLD_23_DELAY11 = 974; // 16 +static const uint64_t SH_FLD_23_DELAY11_LEN = 975; // 16 +static const uint64_t SH_FLD_23_DELAY12 = 976; // 16 +static const uint64_t SH_FLD_23_DELAY12_LEN = 977; // 16 +static const uint64_t SH_FLD_23_DELAY13 = 978; // 16 +static const uint64_t SH_FLD_23_DELAY13_LEN = 979; // 16 +static const uint64_t SH_FLD_23_DELAY14 = 980; // 16 +static const uint64_t SH_FLD_23_DELAY14_LEN = 981; // 16 +static const uint64_t SH_FLD_23_DELAY15 = 982; // 16 +static const uint64_t SH_FLD_23_DELAY15_LEN = 983; // 16 +static const uint64_t SH_FLD_23_DELAY1_LEN = 984; // 16 +static const uint64_t SH_FLD_23_DELAY2 = 985; // 16 +static const uint64_t SH_FLD_23_DELAY2_LEN = 986; // 16 +static const uint64_t SH_FLD_23_DELAY3 = 987; // 16 +static const uint64_t SH_FLD_23_DELAY3_LEN = 988; // 16 +static const uint64_t SH_FLD_23_DELAY4 = 989; // 16 +static const uint64_t SH_FLD_23_DELAY4_LEN = 990; // 16 +static const uint64_t SH_FLD_23_DELAY5 = 991; // 16 +static const uint64_t SH_FLD_23_DELAY5_LEN = 992; // 16 +static const uint64_t SH_FLD_23_DELAY6 = 993; // 16 +static const uint64_t SH_FLD_23_DELAY6_LEN = 994; // 16 +static const uint64_t SH_FLD_23_DELAY7 = 995; // 16 +static const uint64_t SH_FLD_23_DELAY7_LEN = 996; // 16 +static const uint64_t SH_FLD_23_DELAY8 = 997; // 16 +static const uint64_t SH_FLD_23_DELAY8_LEN = 998; // 16 +static const uint64_t SH_FLD_23_DELAY9 = 999; // 16 +static const uint64_t SH_FLD_23_DELAY9_LEN = 1000; // 16 +static const uint64_t SH_FLD_23_DELAYG = 1001; // 1280 +static const uint64_t SH_FLD_23_DELAYG_LEN = 1002; // 1280 +static const uint64_t SH_FLD_23_DELAY_PING_PONG_HALF = 1003; // 16 +static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 1004; // 16 +static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1005; // 16 +static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW = 1006; // 16 +static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1007; // 16 +static const uint64_t SH_FLD_23_DETECT_REQ = 1008; // 32 +static const uint64_t SH_FLD_23_DFT_FORCE_OUTPUTS = 1009; // 16 +static const uint64_t SH_FLD_23_DFT_PRBS7_GEN_EN = 1010; // 16 +static const uint64_t SH_FLD_23_DIGITAL_EN = 1011; // 16 +static const uint64_t SH_FLD_23_DIR_0_15 = 1012; // 16 +static const uint64_t SH_FLD_23_DIR_0_15_LEN = 1013; // 16 +static const uint64_t SH_FLD_23_DISABLE_0_15 = 1014; // 64 +static const uint64_t SH_FLD_23_DISABLE_0_15_LEN = 1015; // 64 +static const uint64_t SH_FLD_23_DISABLE_16_23 = 1016; // 64 +static const uint64_t SH_FLD_23_DISABLE_16_23_LEN = 1017; // 64 +static const uint64_t SH_FLD_23_DISABLE_PING_PONG = 1018; // 16 +static const uint64_t SH_FLD_23_DISABLE_TERMINATION = 1019; // 16 +static const uint64_t SH_FLD_23_DIS_CLK_GATE = 1020; // 16 +static const uint64_t SH_FLD_23_DI_ADR0_ADR1 = 1021; // 16 +static const uint64_t SH_FLD_23_DI_ADR10_ADR11 = 1022; // 16 +static const uint64_t SH_FLD_23_DI_ADR12_ADR13 = 1023; // 16 +static const uint64_t SH_FLD_23_DI_ADR14_ADR15 = 1024; // 16 +static const uint64_t SH_FLD_23_DI_ADR2 = 1025; // 8 +static const uint64_t SH_FLD_23_DI_ADR3 = 1026; // 8 +static const uint64_t SH_FLD_23_DI_ADR4_ADR5 = 1027; // 16 +static const uint64_t SH_FLD_23_DI_ADR6_ADR7 = 1028; // 16 +static const uint64_t SH_FLD_23_DI_ADR8_ADR9 = 1029; // 16 +static const uint64_t SH_FLD_23_DLL_ADJUST = 1030; // 32 +static const uint64_t SH_FLD_23_DLL_ADJUST_LEN = 1031; // 32 +static const uint64_t SH_FLD_23_DLL_COMPARE_OUT = 1032; // 32 +static const uint64_t SH_FLD_23_DLL_CORRECT_EN = 1033; // 32 +static const uint64_t SH_FLD_23_DLL_ITER_A = 1034; // 32 +static const uint64_t SH_FLD_23_DL_FORCE_ON = 1035; // 16 +static const uint64_t SH_FLD_23_DONE = 1036; // 32 +static const uint64_t SH_FLD_23_DQS = 1037; // 16 +static const uint64_t SH_FLD_23_DQSCLK_SELECT0 = 1038; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT0_LEN = 1039; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT1 = 1040; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT1_LEN = 1041; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT2 = 1042; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT2_LEN = 1043; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT3 = 1044; // 64 +static const uint64_t SH_FLD_23_DQSCLK_SELECT3_LEN = 1045; // 64 +static const uint64_t SH_FLD_23_DQS_ALIGN_CNTR = 1046; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_CNTR_LEN = 1047; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_FIX_DIS = 1048; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_JITTER = 1049; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_QUAD = 1050; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_QUAD_LEN = 1051; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_SM = 1052; // 16 +static const uint64_t SH_FLD_23_DQS_ALIGN_SM_LEN = 1053; // 16 +static const uint64_t SH_FLD_23_DQS_LEN = 1054; // 16 +static const uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS = 1055; // 16 +static const uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS_LEN = 1056; // 16 +static const uint64_t SH_FLD_23_DQS_QUAD_CONFIG = 1057; // 16 +static const uint64_t SH_FLD_23_DQS_QUAD_CONFIG_LEN = 1058; // 16 +static const uint64_t SH_FLD_23_DRIFT_ERROR = 1059; // 16 +static const uint64_t SH_FLD_23_DRIFT_MASK = 1060; // 16 +static const uint64_t SH_FLD_23_DRVREN_MODE = 1061; // 32 +static const uint64_t SH_FLD_23_DYN_MCTERM_CNTL_EN = 1062; // 16 +static const uint64_t SH_FLD_23_DYN_POWER_CNTL_EN = 1063; // 16 +static const uint64_t SH_FLD_23_DYN_RX_GATE_CNTL_EN = 1064; // 16 +static const uint64_t SH_FLD_23_ENABLE_0_15 = 1065; // 16 +static const uint64_t SH_FLD_23_ENABLE_0_15_LEN = 1066; // 16 +static const uint64_t SH_FLD_23_ENABLE_16_23 = 1067; // 16 +static const uint64_t SH_FLD_23_ENABLE_16_23_LEN = 1068; // 16 +static const uint64_t SH_FLD_23_EN_DQS_OFFSET = 1069; // 16 +static const uint64_t SH_FLD_23_EN_DRIVER_INVFB_DC = 1070; // 32 +static const uint64_t SH_FLD_23_EN_N_WR = 1071; // 16 +static const uint64_t SH_FLD_23_EN_N_WR_LEN = 1072; // 16 +static const uint64_t SH_FLD_23_EN_P_WR = 1073; // 32 +static const uint64_t SH_FLD_23_EN_P_WR_LEN = 1074; // 32 +static const uint64_t SH_FLD_23_ERROR = 1075; // 16 +static const uint64_t SH_FLD_23_ERROR_LEN = 1076; // 16 +static const uint64_t SH_FLD_23_ERR_CLK22_MASK = 1077; // 16 +static const uint64_t SH_FLD_23_EYE_CLIPPING = 1078; // 16 +static const uint64_t SH_FLD_23_EYE_CLIPPING_MASK = 1079; // 16 +static const uint64_t SH_FLD_23_FINE_STEPPING = 1080; // 16 +static const uint64_t SH_FLD_23_FLUSH = 1081; // 16 +static const uint64_t SH_FLD_23_FORCE_DQS_LANES_ON = 1082; // 16 +static const uint64_t SH_FLD_23_FORCE_FIFO_CAPTURE = 1083; // 16 +static const uint64_t SH_FLD_23_FREE_USAGE = 1084; // 3 +static const uint64_t SH_FLD_23_FW_LEFT_SIDE = 1085; // 16 +static const uint64_t SH_FLD_23_FW_LEFT_SIDE_LEN = 1086; // 16 +static const uint64_t SH_FLD_23_FW_RIGHT_SIDE = 1087; // 16 +static const uint64_t SH_FLD_23_FW_RIGHT_SIDE_LEN = 1088; // 16 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0 = 1089; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3 = 1090; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3_LEN = 1091; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_LEN = 1092; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0 = 1093; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3 = 1094; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3_LEN = 1095; // 8 +static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_LEN = 1096; // 8 +static const uint64_t SH_FLD_23_HS_PROBE_A = 1097; // 16 +static const uint64_t SH_FLD_23_HS_PROBE_A_LEN = 1098; // 16 +static const uint64_t SH_FLD_23_HS_PROBE_B = 1099; // 16 +static const uint64_t SH_FLD_23_HS_PROBE_B_LEN = 1100; // 16 +static const uint64_t SH_FLD_23_HW_VALUE = 1101; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N0 = 1102; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N0_MASK = 1103; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N1 = 1104; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N1_MASK = 1105; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N2 = 1106; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N2_MASK = 1107; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N3 = 1108; // 16 +static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N3_MASK = 1109; // 16 +static const uint64_t SH_FLD_23_INIT_IO = 1110; // 16 +static const uint64_t SH_FLD_23_INIT_RXDLL_CAL_RESET = 1111; // 32 +static const uint64_t SH_FLD_23_INIT_RXDLL_CAL_UPDATE = 1112; // 32 +static const uint64_t SH_FLD_23_INTERP_SIG_SLEW = 1113; // 16 +static const uint64_t SH_FLD_23_INTERP_SIG_SLEW_LEN = 1114; // 16 +static const uint64_t SH_FLD_23_INVALID_NS_BIG_R = 1115; // 16 +static const uint64_t SH_FLD_23_INVALID_NS_BIG_R_MASK = 1116; // 16 +static const uint64_t SH_FLD_23_INVALID_NS_SMALL_L = 1117; // 16 +static const uint64_t SH_FLD_23_INVALID_NS_SMALL_L_MASK = 1118; // 16 +static const uint64_t SH_FLD_23_INVALID_NS_SMALL_R = 1119; // 16 +static const uint64_t SH_FLD_23_INVALID_NS_SMALL_R_MASK = 1120; // 16 +static const uint64_t SH_FLD_23_ITERATION_CNTR = 1121; // 16 +static const uint64_t SH_FLD_23_ITERATION_CNTR_LEN = 1122; // 16 +static const uint64_t SH_FLD_23_JUMP_BACK_RIGHT = 1123; // 16 +static const uint64_t SH_FLD_23_LANE__0_11_PD = 1124; // 16 +static const uint64_t SH_FLD_23_LANE__0_11_PD_LEN = 1125; // 16 +static const uint64_t SH_FLD_23_LANE__12_15_PD = 1126; // 16 +static const uint64_t SH_FLD_23_LANE__12_15_PD_LEN = 1127; // 16 +static const uint64_t SH_FLD_23_LEADING_EDGE_FOUND_MASK = 1128; // 16 +static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND = 1129; // 16 +static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 = 1130; // 16 +static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1131; // 16 +static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 = 1132; // 16 +static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1133; // 16 +static const uint64_t SH_FLD_23_LEN = 1134; // 128 +static const uint64_t SH_FLD_23_LOOPBACK_DLY12 = 1135; // 16 +static const uint64_t SH_FLD_23_LOOPBACK_FIX_EN = 1136; // 16 +static const uint64_t SH_FLD_23_LOWER = 1137; // 32 +static const uint64_t SH_FLD_23_LOWER_LEN = 1138; // 32 +static const uint64_t SH_FLD_23_MAIN_PD_ENABLE = 1139; // 32 +static const uint64_t SH_FLD_23_MATCH_STEP_RIGHT = 1140; // 16 +static const uint64_t SH_FLD_23_MAX_DQS = 1141; // 16 +static const uint64_t SH_FLD_23_MAX_DQS_ITER = 1142; // 16 +static const uint64_t SH_FLD_23_MAX_DQS_LEN = 1143; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE = 1144; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_ERR0 = 1145; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_ERR1 = 1146; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_ERR2 = 1147; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_ERR3 = 1148; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_MASK1 = 1149; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_MASK2 = 1150; // 16 +static const uint64_t SH_FLD_23_MAX_RANGE_MASK3 = 1151; // 16 +static const uint64_t SH_FLD_23_MEMINTD00 = 1152; // 16 +static const uint64_t SH_FLD_23_MEMINTD00_LEN = 1153; // 16 +static const uint64_t SH_FLD_23_MEMINTD01 = 1154; // 16 +static const uint64_t SH_FLD_23_MEMINTD01_LEN = 1155; // 16 +static const uint64_t SH_FLD_23_MEMINTD02 = 1156; // 16 +static const uint64_t SH_FLD_23_MEMINTD02_LEN = 1157; // 16 +static const uint64_t SH_FLD_23_MEMINTD03 = 1158; // 16 +static const uint64_t SH_FLD_23_MEMINTD03_LEN = 1159; // 16 +static const uint64_t SH_FLD_23_MEMINTD04 = 1160; // 16 +static const uint64_t SH_FLD_23_MEMINTD04_LEN = 1161; // 16 +static const uint64_t SH_FLD_23_MEMINTD05 = 1162; // 16 +static const uint64_t SH_FLD_23_MEMINTD05_LEN = 1163; // 16 +static const uint64_t SH_FLD_23_MEMINTD06 = 1164; // 16 +static const uint64_t SH_FLD_23_MEMINTD06_LEN = 1165; // 16 +static const uint64_t SH_FLD_23_MEMINTD07 = 1166; // 16 +static const uint64_t SH_FLD_23_MEMINTD07_LEN = 1167; // 16 +static const uint64_t SH_FLD_23_MEMINTD08 = 1168; // 16 +static const uint64_t SH_FLD_23_MEMINTD08_LEN = 1169; // 16 +static const uint64_t SH_FLD_23_MEMINTD09 = 1170; // 16 +static const uint64_t SH_FLD_23_MEMINTD09_LEN = 1171; // 16 +static const uint64_t SH_FLD_23_MEMINTD10 = 1172; // 16 +static const uint64_t SH_FLD_23_MEMINTD10_LEN = 1173; // 16 +static const uint64_t SH_FLD_23_MEMINTD11 = 1174; // 16 +static const uint64_t SH_FLD_23_MEMINTD11_LEN = 1175; // 16 +static const uint64_t SH_FLD_23_MEMINTD12 = 1176; // 16 +static const uint64_t SH_FLD_23_MEMINTD12_LEN = 1177; // 16 +static const uint64_t SH_FLD_23_MEMINTD13 = 1178; // 16 +static const uint64_t SH_FLD_23_MEMINTD13_LEN = 1179; // 16 +static const uint64_t SH_FLD_23_MEMINTD14 = 1180; // 16 +static const uint64_t SH_FLD_23_MEMINTD14_LEN = 1181; // 16 +static const uint64_t SH_FLD_23_MEMINTD15 = 1182; // 16 +static const uint64_t SH_FLD_23_MEMINTD15_LEN = 1183; // 16 +static const uint64_t SH_FLD_23_MEMINTD16 = 1184; // 16 +static const uint64_t SH_FLD_23_MEMINTD16_LEN = 1185; // 16 +static const uint64_t SH_FLD_23_MEMINTD17 = 1186; // 16 +static const uint64_t SH_FLD_23_MEMINTD17_LEN = 1187; // 16 +static const uint64_t SH_FLD_23_MEMINTD18 = 1188; // 16 +static const uint64_t SH_FLD_23_MEMINTD18_LEN = 1189; // 16 +static const uint64_t SH_FLD_23_MEMINTD19 = 1190; // 16 +static const uint64_t SH_FLD_23_MEMINTD19_LEN = 1191; // 16 +static const uint64_t SH_FLD_23_MEMINTD20 = 1192; // 16 +static const uint64_t SH_FLD_23_MEMINTD20_LEN = 1193; // 16 +static const uint64_t SH_FLD_23_MEMINTD21 = 1194; // 16 +static const uint64_t SH_FLD_23_MEMINTD21_LEN = 1195; // 16 +static const uint64_t SH_FLD_23_MEMINTD22 = 1196; // 16 +static const uint64_t SH_FLD_23_MEMINTD22_LEN = 1197; // 16 +static const uint64_t SH_FLD_23_MEMINTD23 = 1198; // 16 +static const uint64_t SH_FLD_23_MEMINTD23_LEN = 1199; // 16 +static const uint64_t SH_FLD_23_MIN_EYE = 1200; // 16 +static const uint64_t SH_FLD_23_MIN_EYE_MASK = 1201; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE = 1202; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_ERR0 = 1203; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_ERR1 = 1204; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_ERR2 = 1205; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_ERR3 = 1206; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_MASK1 = 1207; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_MASK2 = 1208; // 16 +static const uint64_t SH_FLD_23_MIN_RANGE_MASK3 = 1209; // 16 +static const uint64_t SH_FLD_23_MIN_RD_EYE_SIZE = 1210; // 16 +static const uint64_t SH_FLD_23_MIN_RD_EYE_SIZE_LEN = 1211; // 16 +static const uint64_t SH_FLD_23_MRS_CMD_N0 = 1212; // 16 +static const uint64_t SH_FLD_23_MRS_CMD_N1 = 1213; // 16 +static const uint64_t SH_FLD_23_MRS_CMD_N2 = 1214; // 16 +static const uint64_t SH_FLD_23_MRS_CMD_N3 = 1215; // 16 +static const uint64_t SH_FLD_23_N0 = 1216; // 128 +static const uint64_t SH_FLD_23_N0_LEN = 1217; // 128 +static const uint64_t SH_FLD_23_N1 = 1218; // 128 +static const uint64_t SH_FLD_23_N1_LEN = 1219; // 128 +static const uint64_t SH_FLD_23_N2 = 1220; // 128 +static const uint64_t SH_FLD_23_N2_LEN = 1221; // 128 +static const uint64_t SH_FLD_23_N3 = 1222; // 128 +static const uint64_t SH_FLD_23_N3_LEN = 1223; // 128 +static const uint64_t SH_FLD_23_NIB0 = 1224; // 16 +static const uint64_t SH_FLD_23_NIB0TCFLIP_DC = 1225; // 16 +static const uint64_t SH_FLD_23_NIB0_EN_FORCE = 1226; // 16 +static const uint64_t SH_FLD_23_NIB0_LEN = 1227; // 16 +static const uint64_t SH_FLD_23_NIB1 = 1228; // 16 +static const uint64_t SH_FLD_23_NIB1TCFLIP_DC = 1229; // 16 +static const uint64_t SH_FLD_23_NIB1_EN_FORCE = 1230; // 16 +static const uint64_t SH_FLD_23_NIB1_LEN = 1231; // 16 +static const uint64_t SH_FLD_23_NIB2 = 1232; // 16 +static const uint64_t SH_FLD_23_NIB2TCFLIP_DC = 1233; // 16 +static const uint64_t SH_FLD_23_NIB2_EN_FORCE = 1234; // 16 +static const uint64_t SH_FLD_23_NIB2_LEN = 1235; // 16 +static const uint64_t SH_FLD_23_NIB3 = 1236; // 16 +static const uint64_t SH_FLD_23_NIB3TCFLIP_DC = 1237; // 16 +static const uint64_t SH_FLD_23_NIB3_EN_FORCE = 1238; // 16 +static const uint64_t SH_FLD_23_NIB3_LEN = 1239; // 16 +static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP = 1240; // 16 +static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN = 1241; // 16 +static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES = 1242; // 16 +static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES_LEN = 1243; // 16 +static const uint64_t SH_FLD_23_NIB_0_DQSEL_CAP = 1244; // 16 +static const uint64_t SH_FLD_23_NIB_0_DQSEL_CAP_LEN = 1245; // 16 +static const uint64_t SH_FLD_23_NIB_0_DQSEL_RES = 1246; // 16 +static const uint64_t SH_FLD_23_NIB_0_DQSEL_RES_LEN = 1247; // 16 +static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP = 1248; // 16 +static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN = 1249; // 16 +static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES = 1250; // 16 +static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES_LEN = 1251; // 16 +static const uint64_t SH_FLD_23_NIB_1_DQSEL_CAP = 1252; // 16 +static const uint64_t SH_FLD_23_NIB_1_DQSEL_CAP_LEN = 1253; // 16 +static const uint64_t SH_FLD_23_NIB_1_DQSEL_RES = 1254; // 16 +static const uint64_t SH_FLD_23_NIB_1_DQSEL_RES_LEN = 1255; // 16 +static const uint64_t SH_FLD_23_NO_DQS = 1256; // 16 +static const uint64_t SH_FLD_23_NO_DQS_MASK = 1257; // 16 +static const uint64_t SH_FLD_23_NO_EYE_DETECTED = 1258; // 16 +static const uint64_t SH_FLD_23_NO_EYE_DETECTED_MASK = 1259; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE = 1260; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_ERR0 = 1261; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_ERR1 = 1262; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_ERR2 = 1263; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_ERR3 = 1264; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_MASK1 = 1265; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_MASK2 = 1266; // 16 +static const uint64_t SH_FLD_23_NO_INCREASE_MASK3 = 1267; // 16 +static const uint64_t SH_FLD_23_NO_LOCK = 1268; // 16 +static const uint64_t SH_FLD_23_NO_LOCK_MASK = 1269; // 16 +static const uint64_t SH_FLD_23_OFFSET0 = 1270; // 16 +static const uint64_t SH_FLD_23_OFFSET0_LEN = 1271; // 16 +static const uint64_t SH_FLD_23_OFFSET1 = 1272; // 16 +static const uint64_t SH_FLD_23_OFFSET1_LEN = 1273; // 16 +static const uint64_t SH_FLD_23_OFFSET2 = 1274; // 32 +static const uint64_t SH_FLD_23_OFFSET2_LEN = 1275; // 32 +static const uint64_t SH_FLD_23_OFFSET3 = 1276; // 32 +static const uint64_t SH_FLD_23_OFFSET3_LEN = 1277; // 32 +static const uint64_t SH_FLD_23_OFFSET4 = 1278; // 32 +static const uint64_t SH_FLD_23_OFFSET4_LEN = 1279; // 32 +static const uint64_t SH_FLD_23_OFFSET5 = 1280; // 32 +static const uint64_t SH_FLD_23_OFFSET5_LEN = 1281; // 32 +static const uint64_t SH_FLD_23_OFFSET6 = 1282; // 32 +static const uint64_t SH_FLD_23_OFFSET6_LEN = 1283; // 32 +static const uint64_t SH_FLD_23_OFFSET7 = 1284; // 32 +static const uint64_t SH_FLD_23_OFFSET7_LEN = 1285; // 32 +static const uint64_t SH_FLD_23_OFFSET_ERR = 1286; // 16 +static const uint64_t SH_FLD_23_OFFSET_ERR_MASK = 1287; // 16 +static const uint64_t SH_FLD_23_OPERATE_MODE = 1288; // 16 +static const uint64_t SH_FLD_23_OPERATE_MODE_LEN = 1289; // 16 +static const uint64_t SH_FLD_23_OVERRIDE = 1290; // 32 +static const uint64_t SH_FLD_23_PERCAL_PWR_DIS = 1291; // 16 +static const uint64_t SH_FLD_23_PER_CAL_UPDATE_DISABLE = 1292; // 16 +static const uint64_t SH_FLD_23_PHASE_ALIGN_RESET = 1293; // 32 +static const uint64_t SH_FLD_23_PHASE_CNTL_EN = 1294; // 32 +static const uint64_t SH_FLD_23_PHASE_DEFAULT_EN = 1295; // 32 +static const uint64_t SH_FLD_23_POS_EDGE_ALIGN = 1296; // 32 +static const uint64_t SH_FLD_23_QUAD0 = 1297; // 16 +static const uint64_t SH_FLD_23_QUAD0_CLK16 = 1298; // 128 +static const uint64_t SH_FLD_23_QUAD0_CLK18 = 1299; // 128 +static const uint64_t SH_FLD_23_QUAD0_LEN = 1300; // 16 +static const uint64_t SH_FLD_23_QUAD1 = 1301; // 16 +static const uint64_t SH_FLD_23_QUAD1_CLK16 = 1302; // 128 +static const uint64_t SH_FLD_23_QUAD1_CLK18 = 1303; // 128 +static const uint64_t SH_FLD_23_QUAD1_LEN = 1304; // 16 +static const uint64_t SH_FLD_23_QUAD2 = 1305; // 16 +static const uint64_t SH_FLD_23_QUAD2_CLK16 = 1306; // 64 +static const uint64_t SH_FLD_23_QUAD2_CLK18 = 1307; // 64 +static const uint64_t SH_FLD_23_QUAD2_CLK20 = 1308; // 128 +static const uint64_t SH_FLD_23_QUAD2_CLK22 = 1309; // 128 +static const uint64_t SH_FLD_23_QUAD2_LEN = 1310; // 16 +static const uint64_t SH_FLD_23_QUAD3 = 1311; // 16 +static const uint64_t SH_FLD_23_QUAD3_CLK16 = 1312; // 64 +static const uint64_t SH_FLD_23_QUAD3_CLK18 = 1313; // 64 +static const uint64_t SH_FLD_23_QUAD3_CLK20 = 1314; // 128 +static const uint64_t SH_FLD_23_QUAD3_CLK22 = 1315; // 128 +static const uint64_t SH_FLD_23_QUAD3_LEN = 1316; // 16 +static const uint64_t SH_FLD_23_RANGE_DRAM0 = 1317; // 64 +static const uint64_t SH_FLD_23_RANGE_DRAM1 = 1318; // 64 +static const uint64_t SH_FLD_23_RANGE_DRAM2 = 1319; // 64 +static const uint64_t SH_FLD_23_RANGE_DRAM3 = 1320; // 64 +static const uint64_t SH_FLD_23_RD = 1321; // 272 +static const uint64_t SH_FLD_23_RDCLK_SELECT0 = 1322; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT0_LEN = 1323; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT1 = 1324; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT1_LEN = 1325; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT2 = 1326; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT2_LEN = 1327; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT3 = 1328; // 64 +static const uint64_t SH_FLD_23_RDCLK_SELECT3_LEN = 1329; // 64 +static const uint64_t SH_FLD_23_RD_DELAY0 = 1330; // 112 +static const uint64_t SH_FLD_23_RD_DELAY0_LEN = 1331; // 112 +static const uint64_t SH_FLD_23_RD_DELAY1 = 1332; // 112 +static const uint64_t SH_FLD_23_RD_DELAY1_LEN = 1333; // 112 +static const uint64_t SH_FLD_23_RD_DELAY2 = 1334; // 112 +static const uint64_t SH_FLD_23_RD_DELAY2_LEN = 1335; // 112 +static const uint64_t SH_FLD_23_RD_DELAY3 = 1336; // 112 +static const uint64_t SH_FLD_23_RD_DELAY3_LEN = 1337; // 112 +static const uint64_t SH_FLD_23_RD_DELAY4 = 1338; // 112 +static const uint64_t SH_FLD_23_RD_DELAY4_LEN = 1339; // 112 +static const uint64_t SH_FLD_23_RD_DELAY5 = 1340; // 112 +static const uint64_t SH_FLD_23_RD_DELAY5_LEN = 1341; // 112 +static const uint64_t SH_FLD_23_RD_DELAY6 = 1342; // 112 +static const uint64_t SH_FLD_23_RD_DELAY6_LEN = 1343; // 112 +static const uint64_t SH_FLD_23_RD_DELAY7 = 1344; // 112 +static const uint64_t SH_FLD_23_RD_DELAY7_LEN = 1345; // 112 +static const uint64_t SH_FLD_23_RD_LEN = 1346; // 272 +static const uint64_t SH_FLD_23_RD_SIZE0 = 1347; // 176 +static const uint64_t SH_FLD_23_RD_SIZE0_LEN = 1348; // 176 +static const uint64_t SH_FLD_23_RD_SIZE1 = 1349; // 176 +static const uint64_t SH_FLD_23_RD_SIZE1_LEN = 1350; // 176 +static const uint64_t SH_FLD_23_RD_SIZE2 = 1351; // 176 +static const uint64_t SH_FLD_23_RD_SIZE2_LEN = 1352; // 176 +static const uint64_t SH_FLD_23_RD_SIZE3 = 1353; // 176 +static const uint64_t SH_FLD_23_RD_SIZE3_LEN = 1354; // 176 +static const uint64_t SH_FLD_23_RD_SIZE4 = 1355; // 176 +static const uint64_t SH_FLD_23_RD_SIZE4_LEN = 1356; // 176 +static const uint64_t SH_FLD_23_RD_SIZE5 = 1357; // 176 +static const uint64_t SH_FLD_23_RD_SIZE5_LEN = 1358; // 176 +static const uint64_t SH_FLD_23_RD_SIZE6 = 1359; // 176 +static const uint64_t SH_FLD_23_RD_SIZE6_LEN = 1360; // 176 +static const uint64_t SH_FLD_23_RD_SIZE7 = 1361; // 176 +static const uint64_t SH_FLD_23_RD_SIZE7_LEN = 1362; // 176 +static const uint64_t SH_FLD_23_READ_CENTERING_MODE = 1363; // 16 +static const uint64_t SH_FLD_23_READ_CENTERING_MODE_LEN = 1364; // 16 +static const uint64_t SH_FLD_23_REFERENCE1 = 1365; // 16 +static const uint64_t SH_FLD_23_REFERENCE1_LEN = 1366; // 16 +static const uint64_t SH_FLD_23_REFERENCE2 = 1367; // 16 +static const uint64_t SH_FLD_23_REFERENCE2_LEN = 1368; // 16 +static const uint64_t SH_FLD_23_REFERENCE3 = 1369; // 16 +static const uint64_t SH_FLD_23_REFERENCE3_LEN = 1370; // 16 +static const uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP = 1371; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN = 1372; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY0 = 1373; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 = 1374; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN = 1375; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN = 1376; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE = 1377; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN = 1378; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER = 1379; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN = 1380; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER = 1381; // 32 +static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN = 1382; // 32 +static const uint64_t SH_FLD_23_RESERVED = 1383; // 6 +static const uint64_t SH_FLD_23_RESERVED_63 = 1384; // 64 +static const uint64_t SH_FLD_23_ROT0 = 1385; // 16 +static const uint64_t SH_FLD_23_ROT0_LEN = 1386; // 16 +static const uint64_t SH_FLD_23_ROT1 = 1387; // 16 +static const uint64_t SH_FLD_23_ROT1_LEN = 1388; // 16 +static const uint64_t SH_FLD_23_ROT_CLK_N0 = 1389; // 128 +static const uint64_t SH_FLD_23_ROT_CLK_N0_LEN = 1390; // 128 +static const uint64_t SH_FLD_23_ROT_CLK_N1 = 1391; // 128 +static const uint64_t SH_FLD_23_ROT_CLK_N1_LEN = 1392; // 128 +static const uint64_t SH_FLD_23_ROT_N0 = 1393; // 128 +static const uint64_t SH_FLD_23_ROT_N0_LEN = 1394; // 128 +static const uint64_t SH_FLD_23_ROT_N1 = 1395; // 128 +static const uint64_t SH_FLD_23_ROT_N1_LEN = 1396; // 128 +static const uint64_t SH_FLD_23_ROT_OVERRIDE = 1397; // 32 +static const uint64_t SH_FLD_23_ROT_OVERRIDE_EN = 1398; // 32 +static const uint64_t SH_FLD_23_ROT_OVERRIDE_LEN = 1399; // 32 +static const uint64_t SH_FLD_23_RXCAL_DETECT_DONE_META = 1400; // 32 +static const uint64_t SH_FLD_23_RXCAL_PD_CAL_LAG_META = 1401; // 32 +static const uint64_t SH_FLD_23_RXCAL_PD_MAIN_LAG_META = 1402; // 32 +static const uint64_t SH_FLD_23_RXCAL_PD_MAIN_LEAD_META = 1403; // 32 +static const uint64_t SH_FLD_23_RXREG_COMPCON_DC = 1404; // 32 +static const uint64_t SH_FLD_23_RXREG_COMPCON_DC_LEN = 1405; // 32 +static const uint64_t SH_FLD_23_RXREG_CON_DC = 1406; // 32 +static const uint64_t SH_FLD_23_RXREG_DAC_PULLUP_DC = 1407; // 32 +static const uint64_t SH_FLD_23_RXREG_DRVCON_DC = 1408; // 32 +static const uint64_t SH_FLD_23_RXREG_DRVCON_DC_LEN = 1409; // 32 +static const uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC = 1410; // 32 +static const uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN = 1411; // 32 +static const uint64_t SH_FLD_23_RXREG_FINECAL_2XILSB_DC = 1412; // 32 +static const uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC = 1413; // 32 +static const uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1414; // 32 +static const uint64_t SH_FLD_23_RXREG_REF_SEL_DC = 1415; // 32 +static const uint64_t SH_FLD_23_RXREG_REF_SEL_DC_LEN = 1416; // 32 +static const uint64_t SH_FLD_23_S0ACENSLICENDRV_DC = 1417; // 16 +static const uint64_t SH_FLD_23_S0ACENSLICENDRV_DC_LEN = 1418; // 16 +static const uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC = 1419; // 16 +static const uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC_LEN = 1420; // 16 +static const uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC = 1421; // 16 +static const uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC_LEN = 1422; // 16 +static const uint64_t SH_FLD_23_S0INSDLYTAP = 1423; // 16 +static const uint64_t SH_FLD_23_S1ACENSLICENDRV_DC = 1424; // 16 +static const uint64_t SH_FLD_23_S1ACENSLICENDRV_DC_LEN = 1425; // 16 +static const uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC = 1426; // 16 +static const uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC_LEN = 1427; // 16 +static const uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC = 1428; // 16 +static const uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC_LEN = 1429; // 16 +static const uint64_t SH_FLD_23_S1INSDLYTAP = 1430; // 16 +static const uint64_t SH_FLD_23_SEL0 = 1431; // 32 +static const uint64_t SH_FLD_23_SEL0_LEN = 1432; // 16 +static const uint64_t SH_FLD_23_SEL1 = 1433; // 32 +static const uint64_t SH_FLD_23_SEL10 = 1434; // 32 +static const uint64_t SH_FLD_23_SEL10_LEN = 1435; // 32 +static const uint64_t SH_FLD_23_SEL11 = 1436; // 32 +static const uint64_t SH_FLD_23_SEL11_LEN = 1437; // 32 +static const uint64_t SH_FLD_23_SEL12 = 1438; // 32 +static const uint64_t SH_FLD_23_SEL12_LEN = 1439; // 32 +static const uint64_t SH_FLD_23_SEL13 = 1440; // 32 +static const uint64_t SH_FLD_23_SEL13_LEN = 1441; // 32 +static const uint64_t SH_FLD_23_SEL14 = 1442; // 32 +static const uint64_t SH_FLD_23_SEL14_LEN = 1443; // 32 +static const uint64_t SH_FLD_23_SEL15 = 1444; // 32 +static const uint64_t SH_FLD_23_SEL15_LEN = 1445; // 32 +static const uint64_t SH_FLD_23_SEL1_LEN = 1446; // 32 +static const uint64_t SH_FLD_23_SEL2 = 1447; // 32 +static const uint64_t SH_FLD_23_SEL2_LEN = 1448; // 32 +static const uint64_t SH_FLD_23_SEL3 = 1449; // 32 +static const uint64_t SH_FLD_23_SEL3_LEN = 1450; // 32 +static const uint64_t SH_FLD_23_SEL4 = 1451; // 32 +static const uint64_t SH_FLD_23_SEL4_LEN = 1452; // 32 +static const uint64_t SH_FLD_23_SEL5 = 1453; // 32 +static const uint64_t SH_FLD_23_SEL5_LEN = 1454; // 32 +static const uint64_t SH_FLD_23_SEL6 = 1455; // 32 +static const uint64_t SH_FLD_23_SEL6_LEN = 1456; // 32 +static const uint64_t SH_FLD_23_SEL7 = 1457; // 32 +static const uint64_t SH_FLD_23_SEL7_LEN = 1458; // 32 +static const uint64_t SH_FLD_23_SEL8 = 1459; // 32 +static const uint64_t SH_FLD_23_SEL8_LEN = 1460; // 16 +static const uint64_t SH_FLD_23_SEL9 = 1461; // 32 +static const uint64_t SH_FLD_23_SEL9_LEN = 1462; // 32 +static const uint64_t SH_FLD_23_SEL_A = 1463; // 16 +static const uint64_t SH_FLD_23_SEL_A_LEN = 1464; // 16 +static const uint64_t SH_FLD_23_SEL_B = 1465; // 16 +static const uint64_t SH_FLD_23_SEL_B_LEN = 1466; // 16 +static const uint64_t SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN = 1467; // 32 +static const uint64_t SH_FLD_23_SLAVE_VREG_DAC_COARSE = 1468; // 32 +static const uint64_t SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN = 1469; // 32 +static const uint64_t SH_FLD_23_SLAVE_VREG_OVERRIDE = 1470; // 32 +static const uint64_t SH_FLD_23_SLAVE_VREG_REF_SEL_DC = 1471; // 32 +static const uint64_t SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN = 1472; // 32 +static const uint64_t SH_FLD_23_SMALL_STEP_LEFT = 1473; // 16 +static const uint64_t SH_FLD_23_SMALL_STEP_RIGHT = 1474; // 16 +static const uint64_t SH_FLD_23_SPARE_OSC = 1475; // 3 +static const uint64_t SH_FLD_23_SPARE_PLL_CONTROL = 1476; // 3 +static const uint64_t SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL = 1477; // 3 +static const uint64_t SH_FLD_23_SPARE_TEST = 1478; // 3 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE = 1479; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR0 = 1480; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR1 = 1481; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR2 = 1482; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR3 = 1483; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK1 = 1484; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK2 = 1485; // 16 +static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK3 = 1486; // 16 +static const uint64_t SH_FLD_23_SYNC = 1487; // 16 +static const uint64_t SH_FLD_23_SYNC_LEN = 1488; // 16 +static const uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET = 1489; // 16 +static const uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN = 1490; // 16 +static const uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET = 1491; // 16 +static const uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN = 1492; // 16 +static const uint64_t SH_FLD_23_TEST_4TO1_MODE = 1493; // 16 +static const uint64_t SH_FLD_23_TEST_CHECK_EN = 1494; // 16 +static const uint64_t SH_FLD_23_TEST_CLEAR_ERROR = 1495; // 16 +static const uint64_t SH_FLD_23_TEST_DATA_EN = 1496; // 16 +static const uint64_t SH_FLD_23_TEST_GEN_EN = 1497; // 16 +static const uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL = 1498; // 16 +static const uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN = 1499; // 16 +static const uint64_t SH_FLD_23_TEST_MODE = 1500; // 16 +static const uint64_t SH_FLD_23_TEST_MODE_LEN = 1501; // 16 +static const uint64_t SH_FLD_23_TEST_RESET = 1502; // 16 +static const uint64_t SH_FLD_23_TRAILING_EDGE_FOUND_MASK = 1503; // 16 +static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND = 1504; // 16 +static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 = 1505; // 16 +static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1506; // 16 +static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 = 1507; // 16 +static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1508; // 16 +static const uint64_t SH_FLD_23_TRIG_PERIOD = 1509; // 16 +static const uint64_t SH_FLD_23_TSYS = 1510; // 16 +static const uint64_t SH_FLD_23_TSYS_LEN = 1511; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE = 1512; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 = 1513; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 = 1514; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 = 1515; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 = 1516; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 = 1517; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 = 1518; // 16 +static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 = 1519; // 16 +static const uint64_t SH_FLD_23_UPPER = 1520; // 32 +static const uint64_t SH_FLD_23_UPPER_LEN = 1521; // 32 +static const uint64_t SH_FLD_23_VALID_NS_BIG_L = 1522; // 16 +static const uint64_t SH_FLD_23_VALID_NS_BIG_L_MASK = 1523; // 16 +static const uint64_t SH_FLD_23_VALID_NS_BIG_R = 1524; // 16 +static const uint64_t SH_FLD_23_VALID_NS_BIG_R_MASK = 1525; // 16 +static const uint64_t SH_FLD_23_VALID_NS_JUMP_BACK = 1526; // 16 +static const uint64_t SH_FLD_23_VALID_NS_JUMP_BACK_MASK = 1527; // 16 +static const uint64_t SH_FLD_23_VALUE_DRAM0 = 1528; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM0_LEN = 1529; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM1 = 1530; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM1_LEN = 1531; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM2 = 1532; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM2_LEN = 1533; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM3 = 1534; // 64 +static const uint64_t SH_FLD_23_VALUE_DRAM3_LEN = 1535; // 64 +static const uint64_t SH_FLD_23_VREG_RXCAL_COMP_OUT_META = 1536; // 32 +static const uint64_t SH_FLD_23_VREG_SLAVE_COMP_OUT = 1537; // 32 +static const uint64_t SH_FLD_23_WL_ADVANCE_DISABLE = 1538; // 16 +static const uint64_t SH_FLD_23_WL_ERR_CLK16 = 1539; // 32 +static const uint64_t SH_FLD_23_WL_ERR_CLK16_MASK = 1540; // 16 +static const uint64_t SH_FLD_23_WL_ERR_CLK18 = 1541; // 32 +static const uint64_t SH_FLD_23_WL_ERR_CLK18_MASK = 1542; // 16 +static const uint64_t SH_FLD_23_WL_ERR_CLK20 = 1543; // 32 +static const uint64_t SH_FLD_23_WL_ERR_CLK20_MASK = 1544; // 16 +static const uint64_t SH_FLD_23_WL_ERR_CLK22 = 1545; // 32 +static const uint64_t SH_FLD_23_WRAPSEL = 1546; // 16 +static const uint64_t SH_FLD_23_WTRFL_AVE_DIS = 1547; // 16 +static const uint64_t SH_FLD_23_ZERO_DETECTED = 1548; // 16 +static const uint64_t SH_FLD_24 = 1549; // 6 +static const uint64_t SH_FLD_24_RESERVED = 1550; // 6 +static const uint64_t SH_FLD_24_SPARE_CBS_CONTROL = 1551; // 3 +static const uint64_t SH_FLD_24_SPARE_OSC = 1552; // 3 +static const uint64_t SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL = 1553; // 3 +static const uint64_t SH_FLD_25 = 1554; // 6 +static const uint64_t SH_FLD_256K = 1555; // 12 +static const uint64_t SH_FLD_25_SPARE_CBS_CONTROL = 1556; // 3 +static const uint64_t SH_FLD_25_SPARE_CLKIN_CONTROL = 1557; // 3 +static const uint64_t SH_FLD_25_SPARE_OSC = 1558; // 3 +static const uint64_t SH_FLD_25_SPARE_REFCLOCK_CONTROL = 1559; // 3 +static const uint64_t SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL = 1560; // 3 +static const uint64_t SH_FLD_26 = 1561; // 6 +static const uint64_t SH_FLD_26_FREE_USAGE = 1562; // 3 +static const uint64_t SH_FLD_26_SPARE_CBS_CONTROL = 1563; // 3 +static const uint64_t SH_FLD_26_SPARE_CLKIN_CONTROL = 1564; // 3 +static const uint64_t SH_FLD_26_SPARE_OSC = 1565; // 3 +static const uint64_t SH_FLD_26_SPARE_REFCLOCK_CONTROL = 1566; // 3 +static const uint64_t SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL = 1567; // 3 +static const uint64_t SH_FLD_27 = 1568; // 6 +static const uint64_t SH_FLD_27_FREE_USAGE = 1569; // 3 +static const uint64_t SH_FLD_27_SPARE_CBS_CONTROL = 1570; // 3 +static const uint64_t SH_FLD_27_SPARE_CLKIN_CONTROL = 1571; // 3 +static const uint64_t SH_FLD_27_SPARE_OSC = 1572; // 3 +static const uint64_t SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL = 1573; // 3 +static const uint64_t SH_FLD_28 = 1574; // 6 +static const uint64_t SH_FLD_28_FREE_USAGE = 1575; // 3 +static const uint64_t SH_FLD_28_RESERVED_FOR_HTB = 1576; // 3 +static const uint64_t SH_FLD_28_SPARE_OSC = 1577; // 3 +static const uint64_t SH_FLD_28_SPARE_RESET = 1578; // 3 +static const uint64_t SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL = 1579; // 3 +static const uint64_t SH_FLD_28_SPARE_TEST_CONTROL = 1580; // 3 +static const uint64_t SH_FLD_29 = 1581; // 6 +static const uint64_t SH_FLD_29_FREE_USAGE = 1582; // 3 +static const uint64_t SH_FLD_29_RESERVED_FOR_HTB = 1583; // 3 +static const uint64_t SH_FLD_29_SPARE_OSC = 1584; // 3 +static const uint64_t SH_FLD_29_SPARE_REFCLOCK_CONTROL = 1585; // 3 +static const uint64_t SH_FLD_29_SPARE_RESET = 1586; // 3 +static const uint64_t SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL = 1587; // 3 +static const uint64_t SH_FLD_29_SPARE_TEST_CONTROL = 1588; // 3 +static const uint64_t SH_FLD_2_CANNED_0 = 1589; // 2 +static const uint64_t SH_FLD_2_CANNED_0_LEN = 1590; // 2 +static const uint64_t SH_FLD_2_CANNED_1 = 1591; // 2 +static const uint64_t SH_FLD_2_CANNED_1_LEN = 1592; // 2 +static const uint64_t SH_FLD_2_DATA = 1593; // 1 +static const uint64_t SH_FLD_2_DATA_LEN = 1594; // 1 +static const uint64_t SH_FLD_2_LEN = 1595; // 46 +static const uint64_t SH_FLD_2_RESERVED = 1596; // 3 +static const uint64_t SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL = 1597; // 3 +static const uint64_t SH_FLD_3 = 1598; // 466 +static const uint64_t SH_FLD_30 = 1599; // 6 +static const uint64_t SH_FLD_30_RESERVED = 1600; // 3 +static const uint64_t SH_FLD_30_RESERVED_FOR_HTB = 1601; // 3 +static const uint64_t SH_FLD_30_SPARE_OSC = 1602; // 3 +static const uint64_t SH_FLD_30_SPARE_REFCLOCK_CONTROL = 1603; // 3 +static const uint64_t SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL = 1604; // 3 +static const uint64_t SH_FLD_30_SPARE_TEST_CONTROL = 1605; // 3 +static const uint64_t SH_FLD_31 = 1606; // 6 +static const uint64_t SH_FLD_31_SPARE_OSC = 1607; // 3 +static const uint64_t SH_FLD_31_SPARE_REFCLOCK_CONTROL = 1608; // 3 +static const uint64_t SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL = 1609; // 3 +static const uint64_t SH_FLD_31_SPARE_TEST_CONTROL = 1610; // 3 +static const uint64_t SH_FLD_3_DATA = 1611; // 1 +static const uint64_t SH_FLD_3_DATA_LEN = 1612; // 1 +static const uint64_t SH_FLD_3_LEN = 1613; // 46 +static const uint64_t SH_FLD_3_RESERVED = 1614; // 3 +static const uint64_t SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL = 1615; // 3 +static const uint64_t SH_FLD_3_SPARE_SS_PLL_CONTROL = 1616; // 3 +static const uint64_t SH_FLD_4 = 1617; // 520 +static const uint64_t SH_FLD_4X4_MODE = 1618; // 2 +static const uint64_t SH_FLD_4_1D_EYE_NOISE = 1619; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR0 = 1620; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR1 = 1621; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR2 = 1622; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR3 = 1623; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK1 = 1624; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK2 = 1625; // 8 +static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK3 = 1626; // 8 +static const uint64_t SH_FLD_4_ADVANCE_PING_PONG = 1627; // 8 +static const uint64_t SH_FLD_4_ADVANCE_PR_VALUE = 1628; // 8 +static const uint64_t SH_FLD_4_ATESTSEL_0 = 1629; // 8 +static const uint64_t SH_FLD_4_ATESTSEL_0_LEN = 1630; // 8 +static const uint64_t SH_FLD_4_ATEST_SEL_0_1 = 1631; // 8 +static const uint64_t SH_FLD_4_ATEST_SEL_0_1_LEN = 1632; // 8 +static const uint64_t SH_FLD_4_BAD_BIT = 1633; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_ERR0 = 1634; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_ERR1 = 1635; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_ERR2 = 1636; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_ERR3 = 1637; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_MASK1 = 1638; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_MASK2 = 1639; // 8 +static const uint64_t SH_FLD_4_BAD_BIT_MASK3 = 1640; // 8 +static const uint64_t SH_FLD_4_BB_LOCK0 = 1641; // 8 +static const uint64_t SH_FLD_4_BB_LOCK1 = 1642; // 8 +static const uint64_t SH_FLD_4_BIG_STEP_RIGHT = 1643; // 8 +static const uint64_t SH_FLD_4_BIT_CENTERED = 1644; // 8 +static const uint64_t SH_FLD_4_BIT_CENTERED_LEN = 1645; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA = 1646; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR0 = 1647; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR1 = 1648; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR2 = 1649; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR3 = 1650; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK1 = 1651; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK2 = 1652; // 8 +static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK3 = 1653; // 8 +static const uint64_t SH_FLD_4_BLFIFO_DIS = 1654; // 8 +static const uint64_t SH_FLD_4_BUMP = 1655; // 8 +static const uint64_t SH_FLD_4_CALGATE_ON = 1656; // 8 +static const uint64_t SH_FLD_4_CALIBRATE_BIT = 1657; // 8 +static const uint64_t SH_FLD_4_CALIBRATE_BIT_LEN = 1658; // 8 +static const uint64_t SH_FLD_4_CAL_CKTS_ACTIVE = 1659; // 16 +static const uint64_t SH_FLD_4_CAL_ERROR = 1660; // 16 +static const uint64_t SH_FLD_4_CAL_ERROR_FINE = 1661; // 16 +static const uint64_t SH_FLD_4_CAL_GOOD = 1662; // 16 +static const uint64_t SH_FLD_4_CAL_PD_ENABLE = 1663; // 16 +static const uint64_t SH_FLD_4_CHECKER_ENABLE = 1664; // 8 +static const uint64_t SH_FLD_4_CHECKER_RESET = 1665; // 8 +static const uint64_t SH_FLD_4_CHICKSW_HW278227 = 1666; // 8 +static const uint64_t SH_FLD_4_CLK16_SINGLE_ENDED = 1667; // 32 +static const uint64_t SH_FLD_4_CLK18_SINGLE_ENDED = 1668; // 32 +static const uint64_t SH_FLD_4_CLK20_SINGLE_ENDED = 1669; // 32 +static const uint64_t SH_FLD_4_CLK22_SINGLE_ENDED = 1670; // 32 +static const uint64_t SH_FLD_4_CLK_LEVEL = 1671; // 8 +static const uint64_t SH_FLD_4_CLK_LEVEL_LEN = 1672; // 8 +static const uint64_t SH_FLD_4_CNTL_POL = 1673; // 8 +static const uint64_t SH_FLD_4_CNTL_SRC = 1674; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0 = 1675; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK = 1676; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1 = 1677; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK = 1678; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2 = 1679; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK = 1680; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3 = 1681; // 8 +static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK = 1682; // 8 +static const uint64_t SH_FLD_4_CONTINUOUS_UPDATE = 1683; // 16 +static const uint64_t SH_FLD_4_CTR_1D_CHICKEN_SWITCH = 1684; // 8 +static const uint64_t SH_FLD_4_CTR_2D_BIG_STEP_VAL = 1685; // 8 +static const uint64_t SH_FLD_4_CTR_2D_BIG_STEP_VAL_LEN = 1686; // 8 +static const uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL = 1687; // 8 +static const uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL_LEN = 1688; // 8 +static const uint64_t SH_FLD_4_CTR_CUR = 1689; // 8 +static const uint64_t SH_FLD_4_CTR_CUR_LEN = 1690; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP = 1691; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP_LEN = 1692; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP = 1693; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP_LEN = 1694; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT = 1695; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT_LEN = 1696; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT = 1697; // 8 +static const uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT_LEN = 1698; // 8 +static const uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER = 1699; // 8 +static const uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER_LEN = 1700; // 8 +static const uint64_t SH_FLD_4_CTR_RANGE_SELECT = 1701; // 8 +static const uint64_t SH_FLD_4_CTR_RUN_FULL_1D = 1702; // 8 +static const uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX = 1703; // 8 +static const uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN = 1704; // 8 +static const uint64_t SH_FLD_4_DD2_DQS_FIX_DIS = 1705; // 8 +static const uint64_t SH_FLD_4_DD2_FIX_DIS = 1706; // 8 +static const uint64_t SH_FLD_4_DD2_WTRFL_SYNC_DIS = 1707; // 8 +static const uint64_t SH_FLD_4_DELAYG = 1708; // 608 +static const uint64_t SH_FLD_4_DELAYG_LEN = 1709; // 608 +static const uint64_t SH_FLD_4_DELAY_PING_PONG_HALF = 1710; // 8 +static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 1711; // 8 +static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1712; // 8 +static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW = 1713; // 8 +static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1714; // 8 +static const uint64_t SH_FLD_4_DETECT_REQ = 1715; // 16 +static const uint64_t SH_FLD_4_DFT_FORCE_OUTPUTS = 1716; // 8 +static const uint64_t SH_FLD_4_DFT_PRBS7_GEN_EN = 1717; // 8 +static const uint64_t SH_FLD_4_DIGITAL_EN = 1718; // 8 +static const uint64_t SH_FLD_4_DIR_0_15 = 1719; // 8 +static const uint64_t SH_FLD_4_DIR_0_15_LEN = 1720; // 8 +static const uint64_t SH_FLD_4_DISABLE_0_15 = 1721; // 32 +static const uint64_t SH_FLD_4_DISABLE_0_15_LEN = 1722; // 32 +static const uint64_t SH_FLD_4_DISABLE_16_23 = 1723; // 32 +static const uint64_t SH_FLD_4_DISABLE_16_23_LEN = 1724; // 32 +static const uint64_t SH_FLD_4_DISABLE_PING_PONG = 1725; // 8 +static const uint64_t SH_FLD_4_DISABLE_TERMINATION = 1726; // 8 +static const uint64_t SH_FLD_4_DIS_CLK_GATE = 1727; // 8 +static const uint64_t SH_FLD_4_DLL_ADJUST = 1728; // 16 +static const uint64_t SH_FLD_4_DLL_ADJUST_LEN = 1729; // 16 +static const uint64_t SH_FLD_4_DLL_COMPARE_OUT = 1730; // 16 +static const uint64_t SH_FLD_4_DLL_CORRECT_EN = 1731; // 16 +static const uint64_t SH_FLD_4_DLL_ITER_A = 1732; // 16 +static const uint64_t SH_FLD_4_DL_FORCE_ON = 1733; // 8 +static const uint64_t SH_FLD_4_DONE = 1734; // 16 +static const uint64_t SH_FLD_4_DQS = 1735; // 8 +static const uint64_t SH_FLD_4_DQSCLK_SELECT0 = 1736; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT0_LEN = 1737; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT1 = 1738; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT1_LEN = 1739; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT2 = 1740; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT2_LEN = 1741; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT3 = 1742; // 32 +static const uint64_t SH_FLD_4_DQSCLK_SELECT3_LEN = 1743; // 32 +static const uint64_t SH_FLD_4_DQS_ALIGN_CNTR = 1744; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_CNTR_LEN = 1745; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_FIX_DIS = 1746; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_JITTER = 1747; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_QUAD = 1748; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_QUAD_LEN = 1749; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_SM = 1750; // 8 +static const uint64_t SH_FLD_4_DQS_ALIGN_SM_LEN = 1751; // 8 +static const uint64_t SH_FLD_4_DQS_LEN = 1752; // 8 +static const uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS = 1753; // 8 +static const uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS_LEN = 1754; // 8 +static const uint64_t SH_FLD_4_DQS_QUAD_CONFIG = 1755; // 8 +static const uint64_t SH_FLD_4_DQS_QUAD_CONFIG_LEN = 1756; // 8 +static const uint64_t SH_FLD_4_DRIFT_ERROR = 1757; // 8 +static const uint64_t SH_FLD_4_DRIFT_MASK = 1758; // 8 +static const uint64_t SH_FLD_4_DRVREN_MODE = 1759; // 16 +static const uint64_t SH_FLD_4_DYN_MCTERM_CNTL_EN = 1760; // 8 +static const uint64_t SH_FLD_4_DYN_POWER_CNTL_EN = 1761; // 8 +static const uint64_t SH_FLD_4_DYN_RX_GATE_CNTL_EN = 1762; // 8 +static const uint64_t SH_FLD_4_ENABLE_0_15 = 1763; // 8 +static const uint64_t SH_FLD_4_ENABLE_0_15_LEN = 1764; // 8 +static const uint64_t SH_FLD_4_ENABLE_16_23 = 1765; // 8 +static const uint64_t SH_FLD_4_ENABLE_16_23_LEN = 1766; // 8 +static const uint64_t SH_FLD_4_EN_DQS_OFFSET = 1767; // 8 +static const uint64_t SH_FLD_4_EN_DRIVER_INVFB_DC = 1768; // 16 +static const uint64_t SH_FLD_4_EN_N_WR = 1769; // 8 +static const uint64_t SH_FLD_4_EN_N_WR_LEN = 1770; // 8 +static const uint64_t SH_FLD_4_EN_P_WR = 1771; // 16 +static const uint64_t SH_FLD_4_EN_P_WR_LEN = 1772; // 16 +static const uint64_t SH_FLD_4_ERROR = 1773; // 8 +static const uint64_t SH_FLD_4_ERROR_LEN = 1774; // 8 +static const uint64_t SH_FLD_4_ERR_CLK22_MASK = 1775; // 8 +static const uint64_t SH_FLD_4_EYE_CLIPPING = 1776; // 8 +static const uint64_t SH_FLD_4_EYE_CLIPPING_MASK = 1777; // 8 +static const uint64_t SH_FLD_4_FINE_STEPPING = 1778; // 8 +static const uint64_t SH_FLD_4_FLUSH = 1779; // 8 +static const uint64_t SH_FLD_4_FORCE_DQS_LANES_ON = 1780; // 8 +static const uint64_t SH_FLD_4_FORCE_FIFO_CAPTURE = 1781; // 8 +static const uint64_t SH_FLD_4_FW_LEFT_SIDE = 1782; // 8 +static const uint64_t SH_FLD_4_FW_LEFT_SIDE_LEN = 1783; // 8 +static const uint64_t SH_FLD_4_FW_RIGHT_SIDE = 1784; // 8 +static const uint64_t SH_FLD_4_FW_RIGHT_SIDE_LEN = 1785; // 8 +static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3 = 1786; // 8 +static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3_LEN = 1787; // 8 +static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3 = 1788; // 8 +static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3_LEN = 1789; // 8 +static const uint64_t SH_FLD_4_HS_PROBE_A = 1790; // 8 +static const uint64_t SH_FLD_4_HS_PROBE_A_LEN = 1791; // 8 +static const uint64_t SH_FLD_4_HS_PROBE_B = 1792; // 8 +static const uint64_t SH_FLD_4_HS_PROBE_B_LEN = 1793; // 8 +static const uint64_t SH_FLD_4_HW_VALUE = 1794; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N0 = 1795; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N0_MASK = 1796; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N1 = 1797; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N1_MASK = 1798; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N2 = 1799; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N2_MASK = 1800; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N3 = 1801; // 8 +static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N3_MASK = 1802; // 8 +static const uint64_t SH_FLD_4_INIT_IO = 1803; // 8 +static const uint64_t SH_FLD_4_INIT_RXDLL_CAL_RESET = 1804; // 16 +static const uint64_t SH_FLD_4_INIT_RXDLL_CAL_UPDATE = 1805; // 16 +static const uint64_t SH_FLD_4_INTERP_SIG_SLEW = 1806; // 8 +static const uint64_t SH_FLD_4_INTERP_SIG_SLEW_LEN = 1807; // 8 +static const uint64_t SH_FLD_4_INVALID_NS_BIG_R = 1808; // 8 +static const uint64_t SH_FLD_4_INVALID_NS_BIG_R_MASK = 1809; // 8 +static const uint64_t SH_FLD_4_INVALID_NS_SMALL_L = 1810; // 8 +static const uint64_t SH_FLD_4_INVALID_NS_SMALL_L_MASK = 1811; // 8 +static const uint64_t SH_FLD_4_INVALID_NS_SMALL_R = 1812; // 8 +static const uint64_t SH_FLD_4_INVALID_NS_SMALL_R_MASK = 1813; // 8 +static const uint64_t SH_FLD_4_ITERATION_CNTR = 1814; // 8 +static const uint64_t SH_FLD_4_ITERATION_CNTR_LEN = 1815; // 8 +static const uint64_t SH_FLD_4_JUMP_BACK_RIGHT = 1816; // 8 +static const uint64_t SH_FLD_4_LEADING_EDGE_FOUND_MASK = 1817; // 8 +static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND = 1818; // 8 +static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 = 1819; // 8 +static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1820; // 8 +static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 = 1821; // 8 +static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1822; // 8 +static const uint64_t SH_FLD_4_LEN = 1823; // 100 +static const uint64_t SH_FLD_4_LOOPBACK_DLY12 = 1824; // 8 +static const uint64_t SH_FLD_4_LOOPBACK_FIX_EN = 1825; // 8 +static const uint64_t SH_FLD_4_LOWER = 1826; // 16 +static const uint64_t SH_FLD_4_LOWER_LEN = 1827; // 16 +static const uint64_t SH_FLD_4_MAIN_PD_ENABLE = 1828; // 16 +static const uint64_t SH_FLD_4_MATCH_STEP_RIGHT = 1829; // 8 +static const uint64_t SH_FLD_4_MAX_DQS = 1830; // 8 +static const uint64_t SH_FLD_4_MAX_DQS_ITER = 1831; // 8 +static const uint64_t SH_FLD_4_MAX_DQS_LEN = 1832; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE = 1833; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_ERR0 = 1834; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_ERR1 = 1835; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_ERR2 = 1836; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_ERR3 = 1837; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_MASK1 = 1838; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_MASK2 = 1839; // 8 +static const uint64_t SH_FLD_4_MAX_RANGE_MASK3 = 1840; // 8 +static const uint64_t SH_FLD_4_MEMINTD00 = 1841; // 8 +static const uint64_t SH_FLD_4_MEMINTD00_LEN = 1842; // 8 +static const uint64_t SH_FLD_4_MEMINTD01 = 1843; // 8 +static const uint64_t SH_FLD_4_MEMINTD01_LEN = 1844; // 8 +static const uint64_t SH_FLD_4_MEMINTD02 = 1845; // 8 +static const uint64_t SH_FLD_4_MEMINTD02_LEN = 1846; // 8 +static const uint64_t SH_FLD_4_MEMINTD03 = 1847; // 8 +static const uint64_t SH_FLD_4_MEMINTD03_LEN = 1848; // 8 +static const uint64_t SH_FLD_4_MEMINTD04 = 1849; // 8 +static const uint64_t SH_FLD_4_MEMINTD04_LEN = 1850; // 8 +static const uint64_t SH_FLD_4_MEMINTD05 = 1851; // 8 +static const uint64_t SH_FLD_4_MEMINTD05_LEN = 1852; // 8 +static const uint64_t SH_FLD_4_MEMINTD06 = 1853; // 8 +static const uint64_t SH_FLD_4_MEMINTD06_LEN = 1854; // 8 +static const uint64_t SH_FLD_4_MEMINTD07 = 1855; // 8 +static const uint64_t SH_FLD_4_MEMINTD07_LEN = 1856; // 8 +static const uint64_t SH_FLD_4_MEMINTD08 = 1857; // 8 +static const uint64_t SH_FLD_4_MEMINTD08_LEN = 1858; // 8 +static const uint64_t SH_FLD_4_MEMINTD09 = 1859; // 8 +static const uint64_t SH_FLD_4_MEMINTD09_LEN = 1860; // 8 +static const uint64_t SH_FLD_4_MEMINTD10 = 1861; // 8 +static const uint64_t SH_FLD_4_MEMINTD10_LEN = 1862; // 8 +static const uint64_t SH_FLD_4_MEMINTD11 = 1863; // 8 +static const uint64_t SH_FLD_4_MEMINTD11_LEN = 1864; // 8 +static const uint64_t SH_FLD_4_MEMINTD12 = 1865; // 8 +static const uint64_t SH_FLD_4_MEMINTD12_LEN = 1866; // 8 +static const uint64_t SH_FLD_4_MEMINTD13 = 1867; // 8 +static const uint64_t SH_FLD_4_MEMINTD13_LEN = 1868; // 8 +static const uint64_t SH_FLD_4_MEMINTD14 = 1869; // 8 +static const uint64_t SH_FLD_4_MEMINTD14_LEN = 1870; // 8 +static const uint64_t SH_FLD_4_MEMINTD15 = 1871; // 8 +static const uint64_t SH_FLD_4_MEMINTD15_LEN = 1872; // 8 +static const uint64_t SH_FLD_4_MEMINTD16 = 1873; // 8 +static const uint64_t SH_FLD_4_MEMINTD16_LEN = 1874; // 8 +static const uint64_t SH_FLD_4_MEMINTD17 = 1875; // 8 +static const uint64_t SH_FLD_4_MEMINTD17_LEN = 1876; // 8 +static const uint64_t SH_FLD_4_MEMINTD18 = 1877; // 8 +static const uint64_t SH_FLD_4_MEMINTD18_LEN = 1878; // 8 +static const uint64_t SH_FLD_4_MEMINTD19 = 1879; // 8 +static const uint64_t SH_FLD_4_MEMINTD19_LEN = 1880; // 8 +static const uint64_t SH_FLD_4_MEMINTD20 = 1881; // 8 +static const uint64_t SH_FLD_4_MEMINTD20_LEN = 1882; // 8 +static const uint64_t SH_FLD_4_MEMINTD21 = 1883; // 8 +static const uint64_t SH_FLD_4_MEMINTD21_LEN = 1884; // 8 +static const uint64_t SH_FLD_4_MEMINTD22 = 1885; // 8 +static const uint64_t SH_FLD_4_MEMINTD22_LEN = 1886; // 8 +static const uint64_t SH_FLD_4_MEMINTD23 = 1887; // 8 +static const uint64_t SH_FLD_4_MEMINTD23_LEN = 1888; // 8 +static const uint64_t SH_FLD_4_MIN_EYE = 1889; // 8 +static const uint64_t SH_FLD_4_MIN_EYE_MASK = 1890; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE = 1891; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_ERR0 = 1892; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_ERR1 = 1893; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_ERR2 = 1894; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_ERR3 = 1895; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_MASK1 = 1896; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_MASK2 = 1897; // 8 +static const uint64_t SH_FLD_4_MIN_RANGE_MASK3 = 1898; // 8 +static const uint64_t SH_FLD_4_MIN_RD_EYE_SIZE = 1899; // 8 +static const uint64_t SH_FLD_4_MIN_RD_EYE_SIZE_LEN = 1900; // 8 +static const uint64_t SH_FLD_4_MRS_CMD_N0 = 1901; // 8 +static const uint64_t SH_FLD_4_MRS_CMD_N1 = 1902; // 8 +static const uint64_t SH_FLD_4_MRS_CMD_N2 = 1903; // 8 +static const uint64_t SH_FLD_4_MRS_CMD_N3 = 1904; // 8 +static const uint64_t SH_FLD_4_N0 = 1905; // 64 +static const uint64_t SH_FLD_4_N0_LEN = 1906; // 64 +static const uint64_t SH_FLD_4_N1 = 1907; // 64 +static const uint64_t SH_FLD_4_N1_LEN = 1908; // 64 +static const uint64_t SH_FLD_4_N2 = 1909; // 64 +static const uint64_t SH_FLD_4_N2_LEN = 1910; // 64 +static const uint64_t SH_FLD_4_N3 = 1911; // 64 +static const uint64_t SH_FLD_4_N3_LEN = 1912; // 64 +static const uint64_t SH_FLD_4_NIB0 = 1913; // 8 +static const uint64_t SH_FLD_4_NIB0TCFLIP_DC = 1914; // 8 +static const uint64_t SH_FLD_4_NIB0_EN_FORCE = 1915; // 8 +static const uint64_t SH_FLD_4_NIB0_LEN = 1916; // 8 +static const uint64_t SH_FLD_4_NIB1 = 1917; // 8 +static const uint64_t SH_FLD_4_NIB1TCFLIP_DC = 1918; // 8 +static const uint64_t SH_FLD_4_NIB1_EN_FORCE = 1919; // 8 +static const uint64_t SH_FLD_4_NIB1_LEN = 1920; // 8 +static const uint64_t SH_FLD_4_NIB2 = 1921; // 8 +static const uint64_t SH_FLD_4_NIB2TCFLIP_DC = 1922; // 8 +static const uint64_t SH_FLD_4_NIB2_EN_FORCE = 1923; // 8 +static const uint64_t SH_FLD_4_NIB2_LEN = 1924; // 8 +static const uint64_t SH_FLD_4_NIB3 = 1925; // 8 +static const uint64_t SH_FLD_4_NIB3TCFLIP_DC = 1926; // 8 +static const uint64_t SH_FLD_4_NIB3_EN_FORCE = 1927; // 8 +static const uint64_t SH_FLD_4_NIB3_LEN = 1928; // 8 +static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP = 1929; // 16 +static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN = 1930; // 16 +static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES = 1931; // 16 +static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES_LEN = 1932; // 16 +static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP = 1933; // 16 +static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN = 1934; // 16 +static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES = 1935; // 16 +static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES_LEN = 1936; // 16 +static const uint64_t SH_FLD_4_NO_DQS = 1937; // 8 +static const uint64_t SH_FLD_4_NO_DQS_MASK = 1938; // 8 +static const uint64_t SH_FLD_4_NO_EYE_DETECTED = 1939; // 8 +static const uint64_t SH_FLD_4_NO_EYE_DETECTED_MASK = 1940; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE = 1941; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_ERR0 = 1942; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_ERR1 = 1943; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_ERR2 = 1944; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_ERR3 = 1945; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_MASK1 = 1946; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_MASK2 = 1947; // 8 +static const uint64_t SH_FLD_4_NO_INCREASE_MASK3 = 1948; // 8 +static const uint64_t SH_FLD_4_NO_LOCK = 1949; // 8 +static const uint64_t SH_FLD_4_NO_LOCK_MASK = 1950; // 8 +static const uint64_t SH_FLD_4_OFFSET0 = 1951; // 8 +static const uint64_t SH_FLD_4_OFFSET0_LEN = 1952; // 8 +static const uint64_t SH_FLD_4_OFFSET1 = 1953; // 8 +static const uint64_t SH_FLD_4_OFFSET1_LEN = 1954; // 8 +static const uint64_t SH_FLD_4_OFFSET2 = 1955; // 16 +static const uint64_t SH_FLD_4_OFFSET2_LEN = 1956; // 16 +static const uint64_t SH_FLD_4_OFFSET3 = 1957; // 16 +static const uint64_t SH_FLD_4_OFFSET3_LEN = 1958; // 16 +static const uint64_t SH_FLD_4_OFFSET4 = 1959; // 16 +static const uint64_t SH_FLD_4_OFFSET4_LEN = 1960; // 16 +static const uint64_t SH_FLD_4_OFFSET5 = 1961; // 16 +static const uint64_t SH_FLD_4_OFFSET5_LEN = 1962; // 16 +static const uint64_t SH_FLD_4_OFFSET6 = 1963; // 16 +static const uint64_t SH_FLD_4_OFFSET6_LEN = 1964; // 16 +static const uint64_t SH_FLD_4_OFFSET7 = 1965; // 16 +static const uint64_t SH_FLD_4_OFFSET7_LEN = 1966; // 16 +static const uint64_t SH_FLD_4_OFFSET_ERR = 1967; // 8 +static const uint64_t SH_FLD_4_OFFSET_ERR_MASK = 1968; // 8 +static const uint64_t SH_FLD_4_OPERATE_MODE = 1969; // 8 +static const uint64_t SH_FLD_4_OPERATE_MODE_LEN = 1970; // 8 +static const uint64_t SH_FLD_4_OVERRIDE = 1971; // 16 +static const uint64_t SH_FLD_4_PERCAL_PWR_DIS = 1972; // 8 +static const uint64_t SH_FLD_4_PER_CAL_UPDATE_DISABLE = 1973; // 8 +static const uint64_t SH_FLD_4_PHASE_ALIGN_RESET = 1974; // 16 +static const uint64_t SH_FLD_4_PHASE_CNTL_EN = 1975; // 16 +static const uint64_t SH_FLD_4_PHASE_DEFAULT_EN = 1976; // 16 +static const uint64_t SH_FLD_4_POS_EDGE_ALIGN = 1977; // 16 +static const uint64_t SH_FLD_4_QUAD0 = 1978; // 8 +static const uint64_t SH_FLD_4_QUAD0_CLK16 = 1979; // 64 +static const uint64_t SH_FLD_4_QUAD0_CLK18 = 1980; // 64 +static const uint64_t SH_FLD_4_QUAD0_LEN = 1981; // 8 +static const uint64_t SH_FLD_4_QUAD1 = 1982; // 8 +static const uint64_t SH_FLD_4_QUAD1_CLK16 = 1983; // 64 +static const uint64_t SH_FLD_4_QUAD1_CLK18 = 1984; // 64 +static const uint64_t SH_FLD_4_QUAD1_LEN = 1985; // 8 +static const uint64_t SH_FLD_4_QUAD2 = 1986; // 8 +static const uint64_t SH_FLD_4_QUAD2_CLK16 = 1987; // 32 +static const uint64_t SH_FLD_4_QUAD2_CLK18 = 1988; // 32 +static const uint64_t SH_FLD_4_QUAD2_CLK20 = 1989; // 64 +static const uint64_t SH_FLD_4_QUAD2_CLK22 = 1990; // 64 +static const uint64_t SH_FLD_4_QUAD2_LEN = 1991; // 8 +static const uint64_t SH_FLD_4_QUAD3 = 1992; // 8 +static const uint64_t SH_FLD_4_QUAD3_CLK16 = 1993; // 32 +static const uint64_t SH_FLD_4_QUAD3_CLK18 = 1994; // 32 +static const uint64_t SH_FLD_4_QUAD3_CLK20 = 1995; // 64 +static const uint64_t SH_FLD_4_QUAD3_CLK22 = 1996; // 64 +static const uint64_t SH_FLD_4_QUAD3_LEN = 1997; // 8 +static const uint64_t SH_FLD_4_RANGE_DRAM0 = 1998; // 32 +static const uint64_t SH_FLD_4_RANGE_DRAM1 = 1999; // 32 +static const uint64_t SH_FLD_4_RANGE_DRAM2 = 2000; // 32 +static const uint64_t SH_FLD_4_RANGE_DRAM3 = 2001; // 32 +static const uint64_t SH_FLD_4_RD = 2002; // 136 +static const uint64_t SH_FLD_4_RDCLK_SELECT0 = 2003; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT0_LEN = 2004; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT1 = 2005; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT1_LEN = 2006; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT2 = 2007; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT2_LEN = 2008; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT3 = 2009; // 32 +static const uint64_t SH_FLD_4_RDCLK_SELECT3_LEN = 2010; // 32 +static const uint64_t SH_FLD_4_RD_DELAY0 = 2011; // 56 +static const uint64_t SH_FLD_4_RD_DELAY0_LEN = 2012; // 56 +static const uint64_t SH_FLD_4_RD_DELAY1 = 2013; // 56 +static const uint64_t SH_FLD_4_RD_DELAY1_LEN = 2014; // 56 +static const uint64_t SH_FLD_4_RD_DELAY2 = 2015; // 56 +static const uint64_t SH_FLD_4_RD_DELAY2_LEN = 2016; // 56 +static const uint64_t SH_FLD_4_RD_DELAY3 = 2017; // 56 +static const uint64_t SH_FLD_4_RD_DELAY3_LEN = 2018; // 56 +static const uint64_t SH_FLD_4_RD_DELAY4 = 2019; // 56 +static const uint64_t SH_FLD_4_RD_DELAY4_LEN = 2020; // 56 +static const uint64_t SH_FLD_4_RD_DELAY5 = 2021; // 56 +static const uint64_t SH_FLD_4_RD_DELAY5_LEN = 2022; // 56 +static const uint64_t SH_FLD_4_RD_DELAY6 = 2023; // 56 +static const uint64_t SH_FLD_4_RD_DELAY6_LEN = 2024; // 56 +static const uint64_t SH_FLD_4_RD_DELAY7 = 2025; // 56 +static const uint64_t SH_FLD_4_RD_DELAY7_LEN = 2026; // 56 +static const uint64_t SH_FLD_4_RD_LEN = 2027; // 136 +static const uint64_t SH_FLD_4_RD_SIZE0 = 2028; // 88 +static const uint64_t SH_FLD_4_RD_SIZE0_LEN = 2029; // 88 +static const uint64_t SH_FLD_4_RD_SIZE1 = 2030; // 88 +static const uint64_t SH_FLD_4_RD_SIZE1_LEN = 2031; // 88 +static const uint64_t SH_FLD_4_RD_SIZE2 = 2032; // 88 +static const uint64_t SH_FLD_4_RD_SIZE2_LEN = 2033; // 88 +static const uint64_t SH_FLD_4_RD_SIZE3 = 2034; // 88 +static const uint64_t SH_FLD_4_RD_SIZE3_LEN = 2035; // 88 +static const uint64_t SH_FLD_4_RD_SIZE4 = 2036; // 88 +static const uint64_t SH_FLD_4_RD_SIZE4_LEN = 2037; // 88 +static const uint64_t SH_FLD_4_RD_SIZE5 = 2038; // 88 +static const uint64_t SH_FLD_4_RD_SIZE5_LEN = 2039; // 88 +static const uint64_t SH_FLD_4_RD_SIZE6 = 2040; // 88 +static const uint64_t SH_FLD_4_RD_SIZE6_LEN = 2041; // 88 +static const uint64_t SH_FLD_4_RD_SIZE7 = 2042; // 88 +static const uint64_t SH_FLD_4_RD_SIZE7_LEN = 2043; // 88 +static const uint64_t SH_FLD_4_READ_CENTERING_MODE = 2044; // 8 +static const uint64_t SH_FLD_4_READ_CENTERING_MODE_LEN = 2045; // 8 +static const uint64_t SH_FLD_4_REFERENCE1 = 2046; // 8 +static const uint64_t SH_FLD_4_REFERENCE1_LEN = 2047; // 8 +static const uint64_t SH_FLD_4_REFERENCE2 = 2048; // 8 +static const uint64_t SH_FLD_4_REFERENCE2_LEN = 2049; // 8 +static const uint64_t SH_FLD_4_REFERENCE3 = 2050; // 8 +static const uint64_t SH_FLD_4_REFERENCE3_LEN = 2051; // 8 +static const uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP = 2052; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN = 2053; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY0 = 2054; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 = 2055; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN = 2056; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN = 2057; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE = 2058; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN = 2059; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER = 2060; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN = 2061; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER = 2062; // 16 +static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN = 2063; // 16 +static const uint64_t SH_FLD_4_RESERVED = 2064; // 3 +static const uint64_t SH_FLD_4_RESERVED_63 = 2065; // 32 +static const uint64_t SH_FLD_4_ROT0 = 2066; // 8 +static const uint64_t SH_FLD_4_ROT0_LEN = 2067; // 8 +static const uint64_t SH_FLD_4_ROT1 = 2068; // 8 +static const uint64_t SH_FLD_4_ROT1_LEN = 2069; // 8 +static const uint64_t SH_FLD_4_ROT_CLK_N0 = 2070; // 64 +static const uint64_t SH_FLD_4_ROT_CLK_N0_LEN = 2071; // 64 +static const uint64_t SH_FLD_4_ROT_CLK_N1 = 2072; // 64 +static const uint64_t SH_FLD_4_ROT_CLK_N1_LEN = 2073; // 64 +static const uint64_t SH_FLD_4_ROT_N0 = 2074; // 64 +static const uint64_t SH_FLD_4_ROT_N0_LEN = 2075; // 64 +static const uint64_t SH_FLD_4_ROT_N1 = 2076; // 64 +static const uint64_t SH_FLD_4_ROT_N1_LEN = 2077; // 64 +static const uint64_t SH_FLD_4_ROT_OVERRIDE = 2078; // 16 +static const uint64_t SH_FLD_4_ROT_OVERRIDE_EN = 2079; // 16 +static const uint64_t SH_FLD_4_ROT_OVERRIDE_LEN = 2080; // 16 +static const uint64_t SH_FLD_4_RXCAL_DETECT_DONE_META = 2081; // 16 +static const uint64_t SH_FLD_4_RXCAL_PD_CAL_LAG_META = 2082; // 16 +static const uint64_t SH_FLD_4_RXCAL_PD_MAIN_LAG_META = 2083; // 16 +static const uint64_t SH_FLD_4_RXCAL_PD_MAIN_LEAD_META = 2084; // 16 +static const uint64_t SH_FLD_4_RXREG_COMPCON_DC = 2085; // 16 +static const uint64_t SH_FLD_4_RXREG_COMPCON_DC_LEN = 2086; // 16 +static const uint64_t SH_FLD_4_RXREG_CON_DC = 2087; // 16 +static const uint64_t SH_FLD_4_RXREG_DAC_PULLUP_DC = 2088; // 16 +static const uint64_t SH_FLD_4_RXREG_DRVCON_DC = 2089; // 16 +static const uint64_t SH_FLD_4_RXREG_DRVCON_DC_LEN = 2090; // 16 +static const uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC = 2091; // 16 +static const uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN = 2092; // 16 +static const uint64_t SH_FLD_4_RXREG_FINECAL_2XILSB_DC = 2093; // 16 +static const uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC = 2094; // 16 +static const uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2095; // 16 +static const uint64_t SH_FLD_4_RXREG_REF_SEL_DC = 2096; // 16 +static const uint64_t SH_FLD_4_RXREG_REF_SEL_DC_LEN = 2097; // 16 +static const uint64_t SH_FLD_4_S0ACENSLICENDRV_DC = 2098; // 8 +static const uint64_t SH_FLD_4_S0ACENSLICENDRV_DC_LEN = 2099; // 8 +static const uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC = 2100; // 8 +static const uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC_LEN = 2101; // 8 +static const uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC = 2102; // 8 +static const uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC_LEN = 2103; // 8 +static const uint64_t SH_FLD_4_S0INSDLYTAP = 2104; // 8 +static const uint64_t SH_FLD_4_S1ACENSLICENDRV_DC = 2105; // 8 +static const uint64_t SH_FLD_4_S1ACENSLICENDRV_DC_LEN = 2106; // 8 +static const uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC = 2107; // 8 +static const uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC_LEN = 2108; // 8 +static const uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC = 2109; // 8 +static const uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC_LEN = 2110; // 8 +static const uint64_t SH_FLD_4_S1INSDLYTAP = 2111; // 8 +static const uint64_t SH_FLD_4_SEL_A = 2112; // 8 +static const uint64_t SH_FLD_4_SEL_A_LEN = 2113; // 8 +static const uint64_t SH_FLD_4_SEL_B = 2114; // 8 +static const uint64_t SH_FLD_4_SEL_B_LEN = 2115; // 8 +static const uint64_t SH_FLD_4_SEND_ENABLE = 2116; // 1 +static const uint64_t SH_FLD_4_SEND_MODE = 2117; // 1 +static const uint64_t SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN = 2118; // 16 +static const uint64_t SH_FLD_4_SLAVE_VREG_DAC_COARSE = 2119; // 16 +static const uint64_t SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN = 2120; // 16 +static const uint64_t SH_FLD_4_SLAVE_VREG_OVERRIDE = 2121; // 16 +static const uint64_t SH_FLD_4_SLAVE_VREG_REF_SEL_DC = 2122; // 16 +static const uint64_t SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN = 2123; // 16 +static const uint64_t SH_FLD_4_SMALL_STEP_LEFT = 2124; // 8 +static const uint64_t SH_FLD_4_SMALL_STEP_RIGHT = 2125; // 8 +static const uint64_t SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL = 2126; // 3 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE = 2127; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR0 = 2128; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR1 = 2129; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR2 = 2130; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR3 = 2131; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK1 = 2132; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK2 = 2133; // 8 +static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK3 = 2134; // 8 +static const uint64_t SH_FLD_4_SYNC = 2135; // 8 +static const uint64_t SH_FLD_4_SYNC_LEN = 2136; // 8 +static const uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET = 2137; // 8 +static const uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN = 2138; // 8 +static const uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET = 2139; // 8 +static const uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN = 2140; // 8 +static const uint64_t SH_FLD_4_TRAILING_EDGE_FOUND_MASK = 2141; // 8 +static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND = 2142; // 8 +static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 = 2143; // 8 +static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 2144; // 8 +static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 = 2145; // 8 +static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 2146; // 8 +static const uint64_t SH_FLD_4_TRIG_PERIOD = 2147; // 8 +static const uint64_t SH_FLD_4_TSYS = 2148; // 8 +static const uint64_t SH_FLD_4_TSYS_LEN = 2149; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE = 2150; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR0 = 2151; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR1 = 2152; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR2 = 2153; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR3 = 2154; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK1 = 2155; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK2 = 2156; // 8 +static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK3 = 2157; // 8 +static const uint64_t SH_FLD_4_UPPER = 2158; // 16 +static const uint64_t SH_FLD_4_UPPER_LEN = 2159; // 16 +static const uint64_t SH_FLD_4_VALID_NS_BIG_L = 2160; // 8 +static const uint64_t SH_FLD_4_VALID_NS_BIG_L_MASK = 2161; // 8 +static const uint64_t SH_FLD_4_VALID_NS_BIG_R = 2162; // 8 +static const uint64_t SH_FLD_4_VALID_NS_BIG_R_MASK = 2163; // 8 +static const uint64_t SH_FLD_4_VALID_NS_JUMP_BACK = 2164; // 8 +static const uint64_t SH_FLD_4_VALID_NS_JUMP_BACK_MASK = 2165; // 8 +static const uint64_t SH_FLD_4_VALUE_DRAM0 = 2166; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM0_LEN = 2167; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM1 = 2168; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM1_LEN = 2169; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM2 = 2170; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM2_LEN = 2171; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM3 = 2172; // 32 +static const uint64_t SH_FLD_4_VALUE_DRAM3_LEN = 2173; // 32 +static const uint64_t SH_FLD_4_VREG_RXCAL_COMP_OUT_META = 2174; // 16 +static const uint64_t SH_FLD_4_VREG_SLAVE_COMP_OUT = 2175; // 16 +static const uint64_t SH_FLD_4_WL_ADVANCE_DISABLE = 2176; // 8 +static const uint64_t SH_FLD_4_WL_ERR_CLK16 = 2177; // 16 +static const uint64_t SH_FLD_4_WL_ERR_CLK16_MASK = 2178; // 8 +static const uint64_t SH_FLD_4_WL_ERR_CLK18 = 2179; // 16 +static const uint64_t SH_FLD_4_WL_ERR_CLK18_MASK = 2180; // 8 +static const uint64_t SH_FLD_4_WL_ERR_CLK20 = 2181; // 16 +static const uint64_t SH_FLD_4_WL_ERR_CLK20_MASK = 2182; // 8 +static const uint64_t SH_FLD_4_WL_ERR_CLK22 = 2183; // 16 +static const uint64_t SH_FLD_4_WRAPSEL = 2184; // 8 +static const uint64_t SH_FLD_4_WTRFL_AVE_DIS = 2185; // 8 +static const uint64_t SH_FLD_4_ZERO_DETECTED = 2186; // 8 +static const uint64_t SH_FLD_5 = 2187; // 457 +static const uint64_t SH_FLD_5_LEN = 2188; // 43 +static const uint64_t SH_FLD_5_RESERVED = 2189; // 3 +static const uint64_t SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL = 2190; // 3 +static const uint64_t SH_FLD_6 = 2191; // 457 +static const uint64_t SH_FLD_6_LEN = 2192; // 43 +static const uint64_t SH_FLD_6_RESERVED = 2193; // 3 +static const uint64_t SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL = 2194; // 3 +static const uint64_t SH_FLD_6_SPARE_TERM_DIS = 2195; // 3 +static const uint64_t SH_FLD_7 = 2196; // 414 +static const uint64_t SH_FLD_7_RESERVED = 2197; // 3 +static const uint64_t SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL = 2198; // 3 +static const uint64_t SH_FLD_7_SPARE_TERM_DIS = 2199; // 3 +static const uint64_t SH_FLD_8 = 2200; // 8 +static const uint64_t SH_FLD_842_FC_SELECT = 2201; // 1 +static const uint64_t SH_FLD_842_FC_SELECT_LEN = 2202; // 1 +static const uint64_t SH_FLD_842_LATENCY_CFG = 2203; // 1 +static const uint64_t SH_FLD_8_11_SPARE = 2204; // 8 +static const uint64_t SH_FLD_8_11_SPARE_LEN = 2205; // 8 +static const uint64_t SH_FLD_8_9 = 2206; // 6 +static const uint64_t SH_FLD_8_9_LEN = 2207; // 6 +static const uint64_t SH_FLD_8_RESERVED = 2208; // 6 +static const uint64_t SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL = 2209; // 3 +static const uint64_t SH_FLD_9 = 2210; // 8 +static const uint64_t SH_FLD_9_RESERVED = 2211; // 3 +static const uint64_t SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL = 2212; // 3 +static const uint64_t SH_FLD_AACR_PE = 2213; // 8 +static const uint64_t SH_FLD_AADR_PE = 2214; // 8 +static const uint64_t SH_FLD_AAER_PE = 2215; // 8 +static const uint64_t SH_FLD_ABIST = 2216; // 43 +static const uint64_t SH_FLD_ABORT = 2217; // 6 +static const uint64_t SH_FLD_ABORTED_CMD = 2218; // 1 +static const uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL = 2219; // 6 +static const uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN = 2220; // 6 +static const uint64_t SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR = 2221; // 43 +static const uint64_t SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 2222; // 43 +static const uint64_t SH_FLD_ABORT_ON_ERROR = 2223; // 8 +static const uint64_t SH_FLD_ABORT_ON_ERR_EN = 2224; // 8 +static const uint64_t SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR = 2225; // 43 +static const uint64_t SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR = 2226; // 43 +static const uint64_t SH_FLD_ABUS_LOCK = 2227; // 1 +static const uint64_t SH_FLD_ACCUM = 2228; // 6 +static const uint64_t SH_FLD_ACCUMULATED_DL_RETURN_P0 = 2229; // 43 +static const uint64_t SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2230; // 43 +static const uint64_t SH_FLD_ACCUMULATED_GENERAL_TIMEOUT = 2231; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID = 2232; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD = 2233; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD = 2234; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 2235; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE = 2236; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY = 2237; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY = 2238; // 43 +static const uint64_t SH_FLD_ACCUMULATED_PCB_WDATA_PARITY = 2239; // 43 +static const uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 2240; // 43 +static const uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 2241; // 43 +static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 2242; // 43 +static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 2243; // 43 +static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 2244; // 43 +static const uint64_t SH_FLD_ACCUMULATED_UL_P0 = 2245; // 43 +static const uint64_t SH_FLD_ACCUMULATED_UL_RDATA_PARITY = 2246; // 43 +static const uint64_t SH_FLD_ACCUM_HIST = 2247; // 43 +static const uint64_t SH_FLD_ACCUM_LEN = 2248; // 6 +static const uint64_t SH_FLD_ACK = 2249; // 1 +static const uint64_t SH_FLD_ACK_DEAD_CRESP = 2250; // 2 +static const uint64_t SH_FLD_ACK_FIFO_CAP_ADDR = 2251; // 10 +static const uint64_t SH_FLD_ACK_FIFO_CAP_ADDR_LEN = 2252; // 10 +static const uint64_t SH_FLD_ACK_FIFO_CAP_VALID = 2253; // 10 +static const uint64_t SH_FLD_ACK_QUEUE_HIGH = 2254; // 2 +static const uint64_t SH_FLD_ACK_QUEUE_HIGH_LEN = 2255; // 2 +static const uint64_t SH_FLD_ACK_QUEUE_LOW = 2256; // 2 +static const uint64_t SH_FLD_ACK_QUEUE_LOW_LEN = 2257; // 2 +static const uint64_t SH_FLD_ACK_QUEUE_START = 2258; // 2 +static const uint64_t SH_FLD_ACK_QUEUE_START_LEN = 2259; // 2 +static const uint64_t SH_FLD_ACT = 2260; // 63 +static const uint64_t SH_FLD_ACTCYCLECNT = 2261; // 3 +static const uint64_t SH_FLD_ACTCYCLECNT_LEN = 2262; // 3 +static const uint64_t SH_FLD_ACTION0 = 2263; // 67 +static const uint64_t SH_FLD_ACTION0_LEN = 2264; // 67 +static const uint64_t SH_FLD_ACTION1 = 2265; // 67 +static const uint64_t SH_FLD_ACTION1_LEN = 2266; // 67 +static const uint64_t SH_FLD_ACTION_0 = 2267; // 4 +static const uint64_t SH_FLD_ACTION_0_LEN = 2268; // 4 +static const uint64_t SH_FLD_ACTION_1 = 2269; // 4 +static const uint64_t SH_FLD_ACTION_1_LEN = 2270; // 4 +static const uint64_t SH_FLD_ACTION_IF_LOG_REC_ERROR = 2271; // 48 +static const uint64_t SH_FLD_ACTION_IF_LOG_XSTOP_ERROR = 2272; // 48 +static const uint64_t SH_FLD_ACTION_IF_RFILE_REC_ERROR = 2273; // 48 +static const uint64_t SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR = 2274; // 48 +static const uint64_t SH_FLD_ACTION_IF_SRAM_REC_ERROR = 2275; // 48 +static const uint64_t SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR = 2276; // 48 +static const uint64_t SH_FLD_ACTION_LS_LOG_REC_ERROR = 2277; // 48 +static const uint64_t SH_FLD_ACTION_LS_LOG_XSTOP_ERROR = 2278; // 48 +static const uint64_t SH_FLD_ACTION_LS_NOT_MT_REC_ERROR = 2279; // 48 +static const uint64_t SH_FLD_ACTION_LS_RFILE_REC_ERROR = 2280; // 48 +static const uint64_t SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR = 2281; // 48 +static const uint64_t SH_FLD_ACTION_LS_SETDELETE_ERROR = 2282; // 48 +static const uint64_t SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR = 2283; // 48 +static const uint64_t SH_FLD_ACTION_LS_SRAM_PARITY_ERROR = 2284; // 48 +static const uint64_t SH_FLD_ACTION_LS_SYS_XSTOP_ERROR = 2285; // 48 +static const uint64_t SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR = 2286; // 48 +static const uint64_t SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR = 2287; // 48 +static const uint64_t SH_FLD_ACTION_PC_FW_INJ_REC_ERROR = 2288; // 48 +static const uint64_t SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR = 2289; // 48 +static const uint64_t SH_FLD_ACTION_PC_HANG_DETECT_ERROR = 2290; // 48 +static const uint64_t SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED = 2291; // 48 +static const uint64_t SH_FLD_ACTION_PC_HYP_RES_ERROR = 2292; // 48 +static const uint64_t SH_FLD_ACTION_PC_LOG_XSTOP_ERROR = 2293; // 48 +static const uint64_t SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR = 2294; // 48 +static const uint64_t SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR = 2295; // 48 +static const uint64_t SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 2296; // 48 +static const uint64_t SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR = 2297; // 48 +static const uint64_t SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR = 2298; // 48 +static const uint64_t SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR = 2299; // 48 +static const uint64_t SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR = 2300; // 48 +static const uint64_t SH_FLD_ACTION_PC_SCOM_ERROR = 2301; // 48 +static const uint64_t SH_FLD_ACTION_PC_SYS_XSTOP_ERROR = 2302; // 48 +static const uint64_t SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR = 2303; // 48 +static const uint64_t SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR = 2304; // 48 +static const uint64_t SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 2305; // 48 +static const uint64_t SH_FLD_ACTION_SD_CI_UE_ERROR = 2306; // 48 +static const uint64_t SH_FLD_ACTION_SD_L2_UE_ERROR = 2307; // 48 +static const uint64_t SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR = 2308; // 48 +static const uint64_t SH_FLD_ACTION_SD_LOG_REC_ERROR = 2309; // 48 +static const uint64_t SH_FLD_ACTION_SD_LOG_XSTOP_ERROR = 2310; // 48 +static const uint64_t SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR = 2311; // 48 +static const uint64_t SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR = 2312; // 48 +static const uint64_t SH_FLD_ACTION_SD_RFILE_REC_ERROR = 2313; // 48 +static const uint64_t SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR = 2314; // 48 +static const uint64_t SH_FLD_ACTION_SD_SYS_XSTOP_ERROR = 2315; // 48 +static const uint64_t SH_FLD_ACTION_TC_FIR_XSTOP_ERROR = 2316; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_18 = 2317; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_19 = 2318; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_21 = 2319; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_22 = 2320; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_23 = 2321; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_40 = 2322; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_42 = 2323; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_44 = 2324; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_46 = 2325; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_49 = 2326; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_50 = 2327; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_51 = 2328; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_54 = 2329; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_6 = 2330; // 48 +static const uint64_t SH_FLD_ACTION_UNUSED_7 = 2331; // 48 +static const uint64_t SH_FLD_ACTION_VS_DU_LOG_REC_ERROR = 2332; // 48 +static const uint64_t SH_FLD_ACTION_VS_LOG_REC_ERROR = 2333; // 48 +static const uint64_t SH_FLD_ACTION_VS_LOG_XSTOP_ERROR = 2334; // 48 +static const uint64_t SH_FLD_ACTIVATE_COUNT = 2335; // 8 +static const uint64_t SH_FLD_ACTIVATE_COUNT_LEN = 2336; // 8 +static const uint64_t SH_FLD_ACTIVATE_FSMERR = 2337; // 2 +static const uint64_t SH_FLD_ACTIVE_CHANNEL_CNT = 2338; // 1 +static const uint64_t SH_FLD_ACTIVE_CHANNEL_CNT_LEN = 2339; // 1 +static const uint64_t SH_FLD_ACTIVE_MASK = 2340; // 24 +static const uint64_t SH_FLD_ACTIVE_MASK_LEN = 2341; // 24 +static const uint64_t SH_FLD_ACTIVITY = 2342; // 129 +static const uint64_t SH_FLD_ACTIVITY_LEN = 2343; // 129 +static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE = 2344; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN = 2345; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN = 2346; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SB_SPARE = 2347; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH = 2348; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN = 2349; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK = 2350; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN = 2351; // 24 +static const uint64_t SH_FLD_ACTUAL_CLK_SW_SPARE = 2352; // 24 +static const uint64_t SH_FLD_ACTUAL_ERROR = 2353; // 3 +static const uint64_t SH_FLD_ACTUAL_ERROR_LEN = 2354; // 3 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE = 2355; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN = 2356; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN = 2357; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_SPARE0 = 2358; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH = 2359; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN = 2360; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK = 2361; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN = 2362; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_SPARE1 = 2363; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE = 2364; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN = 2365; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN = 2366; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_SPARE0 = 2367; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH = 2368; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN = 2369; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK = 2370; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN = 2371; // 6 +static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_SPARE1 = 2372; // 6 +static const uint64_t SH_FLD_ACT_DIS = 2373; // 43 +static const uint64_t SH_FLD_ACT_STOP_LEVEL = 2374; // 150 +static const uint64_t SH_FLD_ACT_STOP_LEVEL_LEN = 2375; // 150 +static const uint64_t SH_FLD_ACT_WRITE_ENABLE = 2376; // 30 +static const uint64_t SH_FLD_AC_COUPLED = 2377; // 2 +static const uint64_t SH_FLD_ADAPTEST_1BIT_ENABLE = 2378; // 1 +static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX = 2379; // 1 +static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 2380; // 1 +static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN = 2381; // 1 +static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 2382; // 1 +static const uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH = 2383; // 1 +static const uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 2384; // 1 +static const uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH = 2385; // 1 +static const uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 2386; // 1 +static const uint64_t SH_FLD_ADAPTEST_ENABLE = 2387; // 1 +static const uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH = 2388; // 1 +static const uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 2389; // 1 +static const uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH = 2390; // 1 +static const uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 2391; // 1 +static const uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE = 2392; // 1 +static const uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN = 2393; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 2394; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 2395; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 2396; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 2397; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 2398; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 2399; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 2400; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 2401; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH = 2402; // 1 +static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN = 2403; // 1 +static const uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE = 2404; // 1 +static const uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE_LEN = 2405; // 1 +static const uint64_t SH_FLD_ADCFSM_ONGOING = 2406; // 1 +static const uint64_t SH_FLD_ADDR = 2407; // 43 +static const uint64_t SH_FLD_ADDR0 = 2408; // 8 +static const uint64_t SH_FLD_ADDR0_LEN = 2409; // 8 +static const uint64_t SH_FLD_ADDR1 = 2410; // 8 +static const uint64_t SH_FLD_ADDR1_LEN = 2411; // 8 +static const uint64_t SH_FLD_ADDR2 = 2412; // 16 +static const uint64_t SH_FLD_ADDR2_LEN = 2413; // 16 +static const uint64_t SH_FLD_ADDR3 = 2414; // 16 +static const uint64_t SH_FLD_ADDR3_LEN = 2415; // 16 +static const uint64_t SH_FLD_ADDR4 = 2416; // 16 +static const uint64_t SH_FLD_ADDR4_LEN = 2417; // 16 +static const uint64_t SH_FLD_ADDRESS = 2418; // 389 +static const uint64_t SH_FLD_ADDRESS_28_63 = 2419; // 1 +static const uint64_t SH_FLD_ADDRESS_28_63_LEN = 2420; // 1 +static const uint64_t SH_FLD_ADDRESS_LEN = 2421; // 388 +static const uint64_t SH_FLD_ADDRESS_PARITY = 2422; // 43 +static const uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 2423; // 2 +static const uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 2424; // 2 +static const uint64_t SH_FLD_ADDR_21_37 = 2425; // 1 +static const uint64_t SH_FLD_ADDR_21_37_LEN = 2426; // 1 +static const uint64_t SH_FLD_ADDR_26_38 = 2427; // 1 +static const uint64_t SH_FLD_ADDR_26_38_LEN = 2428; // 1 +static const uint64_t SH_FLD_ADDR_8_37 = 2429; // 1 +static const uint64_t SH_FLD_ADDR_8_37_LEN = 2430; // 1 +static const uint64_t SH_FLD_ADDR_8_38 = 2431; // 1 +static const uint64_t SH_FLD_ADDR_8_38_LEN = 2432; // 1 +static const uint64_t SH_FLD_ADDR_8_48 = 2433; // 1 +static const uint64_t SH_FLD_ADDR_8_48_LEN = 2434; // 1 +static const uint64_t SH_FLD_ADDR_8_49 = 2435; // 2 +static const uint64_t SH_FLD_ADDR_8_49_LEN = 2436; // 2 +static const uint64_t SH_FLD_ADDR_BAR = 2437; // 2 +static const uint64_t SH_FLD_ADDR_BAR_MODE = 2438; // 2 +static const uint64_t SH_FLD_ADDR_BUFFER = 2439; // 43 +static const uint64_t SH_FLD_ADDR_ERROR = 2440; // 2 +static const uint64_t SH_FLD_ADDR_ERROR_PULSE = 2441; // 2 +static const uint64_t SH_FLD_ADDR_INVALID_FACES = 2442; // 1 +static const uint64_t SH_FLD_ADDR_INVALID_PIB = 2443; // 1 +static const uint64_t SH_FLD_ADDR_LEN = 2444; // 43 +static const uint64_t SH_FLD_ADDR_MIRROR_A11_A13 = 2445; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_A3_A4 = 2446; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_A5_A6 = 2447; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_A7_A8 = 2448; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_BA0_BA1 = 2449; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_BG0_BG1 = 2450; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP0_PRI = 2451; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP0_QUA = 2452; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP0_SEC = 2453; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP0_TER = 2454; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP1_PRI = 2455; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP1_QUA = 2456; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP1_SEC = 2457; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP1_TER = 2458; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP2_PRI = 2459; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP2_QUA = 2460; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP2_SEC = 2461; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP2_TER = 2462; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP3_PRI = 2463; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP3_QUA = 2464; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP3_SEC = 2465; // 8 +static const uint64_t SH_FLD_ADDR_MIRROR_RP3_TER = 2466; // 8 +static const uint64_t SH_FLD_ADDR_NVLD = 2467; // 1 +static const uint64_t SH_FLD_ADDR_PARITY_ERR = 2468; // 4 +static const uint64_t SH_FLD_ADDR_RESET_INTR_FACES = 2469; // 1 +static const uint64_t SH_FLD_ADDR_RESET_INTR_FACES_LEN = 2470; // 1 +static const uint64_t SH_FLD_ADDR_RESET_INTR_PIB = 2471; // 1 +static const uint64_t SH_FLD_ADDR_RESET_INTR_PIB_LEN = 2472; // 1 +static const uint64_t SH_FLD_ADDR_TAG = 2473; // 1 +static const uint64_t SH_FLD_ADDR_TAG_LEN = 2474; // 1 +static const uint64_t SH_FLD_ADJUSTMENT_DIR = 2475; // 36 +static const uint64_t SH_FLD_ADJUST_ERROR_SIGNAL = 2476; // 36 +static const uint64_t SH_FLD_ADJUST_MODE_REG = 2477; // 6 +static const uint64_t SH_FLD_ADJ_FUNC_CLKSEL = 2478; // 43 +static const uint64_t SH_FLD_ADR = 2479; // 4 +static const uint64_t SH_FLD_ADR0 = 2480; // 16 +static const uint64_t SH_FLD_ADR0_ANALOG_WRAPON = 2481; // 8 +static const uint64_t SH_FLD_ADR0_ATESTSEL_0_2 = 2482; // 8 +static const uint64_t SH_FLD_ADR0_ATESTSEL_0_2_LEN = 2483; // 8 +static const uint64_t SH_FLD_ADR0_ATEST_SEL_0 = 2484; // 8 +static const uint64_t SH_FLD_ADR0_ATEST_SEL_0_LEN = 2485; // 8 +static const uint64_t SH_FLD_ADR0_BB_LOCK = 2486; // 8 +static const uint64_t SH_FLD_ADR0_CAL_CKTS_ACTIVE = 2487; // 8 +static const uint64_t SH_FLD_ADR0_CAL_ERROR = 2488; // 8 +static const uint64_t SH_FLD_ADR0_CAL_ERROR_FINE = 2489; // 8 +static const uint64_t SH_FLD_ADR0_CAL_GOOD = 2490; // 8 +static const uint64_t SH_FLD_ADR0_CAL_PD_ENABLE = 2491; // 8 +static const uint64_t SH_FLD_ADR0_CONTINUOUS_UPDATE = 2492; // 8 +static const uint64_t SH_FLD_ADR0_DETECT_REQ = 2493; // 8 +static const uint64_t SH_FLD_ADR0_DLL_ADJUST = 2494; // 8 +static const uint64_t SH_FLD_ADR0_DLL_ADJUST_LEN = 2495; // 8 +static const uint64_t SH_FLD_ADR0_DLL_COMPARE_OUT = 2496; // 8 +static const uint64_t SH_FLD_ADR0_DLL_CORRECT_EN = 2497; // 8 +static const uint64_t SH_FLD_ADR0_DLL_ITER_A = 2498; // 8 +static const uint64_t SH_FLD_ADR0_EN = 2499; // 8 +static const uint64_t SH_FLD_ADR0_EN_DRIVER_INVFB_DC = 2500; // 8 +static const uint64_t SH_FLD_ADR0_FLUSH = 2501; // 8 +static const uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 = 2502; // 8 +static const uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN = 2503; // 8 +static const uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 = 2504; // 8 +static const uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN = 2505; // 8 +static const uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 = 2506; // 8 +static const uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN = 2507; // 8 +static const uint64_t SH_FLD_ADR0_INIT_IO = 2508; // 8 +static const uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_RESET = 2509; // 8 +static const uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE = 2510; // 8 +static const uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW = 2511; // 8 +static const uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_LEN = 2512; // 8 +static const uint64_t SH_FLD_ADR0_LEN = 2513; // 16 +static const uint64_t SH_FLD_ADR0_MAIN_PD_ENABLE = 2514; // 8 +static const uint64_t SH_FLD_ADR0_OVERRIDE = 2515; // 16 +static const uint64_t SH_FLD_ADR0_OVERRIDE_EN = 2516; // 8 +static const uint64_t SH_FLD_ADR0_OVERRIDE_LEN = 2517; // 8 +static const uint64_t SH_FLD_ADR0_PHASE_ALIGN_RESET = 2518; // 8 +static const uint64_t SH_FLD_ADR0_PHASE_DEFAULT_EN = 2519; // 8 +static const uint64_t SH_FLD_ADR0_PHASE_EN = 2520; // 8 +static const uint64_t SH_FLD_ADR0_POS_EDGE_ALIGN = 2521; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP = 2522; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2523; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY0 = 2524; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 2525; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC = 2526; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC_LEN = 2527; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_EN = 2528; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_EN_LEN = 2529; // 8 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG = 2530; // 16 +static const uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG_LEN = 2531; // 16 +static const uint64_t SH_FLD_ADR0_ROT = 2532; // 8 +static const uint64_t SH_FLD_ADR0_ROT_LEN = 2533; // 8 +static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE = 2534; // 8 +static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE_EN = 2535; // 8 +static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE_LEN = 2536; // 8 +static const uint64_t SH_FLD_ADR0_RXCAL_DETECT_DONE_META = 2537; // 8 +static const uint64_t SH_FLD_ADR0_RXCAL_PD_CAL_LAG_META = 2538; // 8 +static const uint64_t SH_FLD_ADR0_RXCAL_PD_MAIN_LAG_META = 2539; // 8 +static const uint64_t SH_FLD_ADR0_RXCAL_PD_MAIN_LEAD_META = 2540; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC = 2541; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC_LEN = 2542; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_CON_DC = 2543; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_DAC_PULLUP_DC = 2544; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC = 2545; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC_LEN = 2546; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC = 2547; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 2548; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_FINECAL_2XILSB_DC = 2549; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 2550; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2551; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC = 2552; // 8 +static const uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN = 2553; // 8 +static const uint64_t SH_FLD_ADR0_SLAVE_CAL_CKT_POWERDOWN = 2554; // 8 +static const uint64_t SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE = 2555; // 8 +static const uint64_t SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE_LEN = 2556; // 8 +static const uint64_t SH_FLD_ADR0_SLAVE_VREG_OVERRIDE = 2557; // 8 +static const uint64_t SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC = 2558; // 8 +static const uint64_t SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC_LEN = 2559; // 8 +static const uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS = 2560; // 8 +static const uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS_LEN = 2561; // 8 +static const uint64_t SH_FLD_ADR0_START = 2562; // 8 +static const uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET = 2563; // 8 +static const uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET_LEN = 2564; // 8 +static const uint64_t SH_FLD_ADR0_TSYS = 2565; // 8 +static const uint64_t SH_FLD_ADR0_TSYS_LEN = 2566; // 8 +static const uint64_t SH_FLD_ADR0_VALUE = 2567; // 16 +static const uint64_t SH_FLD_ADR0_VALUE_LEN = 2568; // 16 +static const uint64_t SH_FLD_ADR0_VREG_RXCAL_COMP_OUT_META = 2569; // 8 +static const uint64_t SH_FLD_ADR0_VREG_SLAVE1_COMP_OUT = 2570; // 8 +static const uint64_t SH_FLD_ADR0_VREG_SLAVE2_COMP_OUT = 2571; // 8 +static const uint64_t SH_FLD_ADR1 = 2572; // 16 +static const uint64_t SH_FLD_ADR1_ANALOG_WRAPON = 2573; // 8 +static const uint64_t SH_FLD_ADR1_ATESTSEL_0_2 = 2574; // 8 +static const uint64_t SH_FLD_ADR1_ATESTSEL_0_2_LEN = 2575; // 8 +static const uint64_t SH_FLD_ADR1_ATEST_SEL_0 = 2576; // 8 +static const uint64_t SH_FLD_ADR1_ATEST_SEL_0_LEN = 2577; // 8 +static const uint64_t SH_FLD_ADR1_BB_LOCK = 2578; // 8 +static const uint64_t SH_FLD_ADR1_CAL_CKTS_ACTIVE = 2579; // 8 +static const uint64_t SH_FLD_ADR1_CAL_ERROR = 2580; // 8 +static const uint64_t SH_FLD_ADR1_CAL_ERROR_FINE = 2581; // 8 +static const uint64_t SH_FLD_ADR1_CAL_GOOD = 2582; // 8 +static const uint64_t SH_FLD_ADR1_CAL_PD_ENABLE = 2583; // 8 +static const uint64_t SH_FLD_ADR1_CONTINUOUS_UPDATE = 2584; // 8 +static const uint64_t SH_FLD_ADR1_DETECT_REQ = 2585; // 8 +static const uint64_t SH_FLD_ADR1_DLL_ADJUST = 2586; // 8 +static const uint64_t SH_FLD_ADR1_DLL_ADJUST_LEN = 2587; // 8 +static const uint64_t SH_FLD_ADR1_DLL_COMPARE_OUT = 2588; // 8 +static const uint64_t SH_FLD_ADR1_DLL_CORRECT_EN = 2589; // 8 +static const uint64_t SH_FLD_ADR1_DLL_ITER_A = 2590; // 8 +static const uint64_t SH_FLD_ADR1_EN = 2591; // 8 +static const uint64_t SH_FLD_ADR1_EN_DRIVER_INVFB_DC = 2592; // 8 +static const uint64_t SH_FLD_ADR1_FLUSH = 2593; // 8 +static const uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 = 2594; // 8 +static const uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN = 2595; // 8 +static const uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 = 2596; // 8 +static const uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN = 2597; // 8 +static const uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 = 2598; // 8 +static const uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN = 2599; // 8 +static const uint64_t SH_FLD_ADR1_INIT_IO = 2600; // 8 +static const uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_RESET = 2601; // 8 +static const uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE = 2602; // 8 +static const uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW = 2603; // 8 +static const uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_LEN = 2604; // 8 +static const uint64_t SH_FLD_ADR1_LEN = 2605; // 16 +static const uint64_t SH_FLD_ADR1_MAIN_PD_ENABLE = 2606; // 8 +static const uint64_t SH_FLD_ADR1_OVERRIDE = 2607; // 16 +static const uint64_t SH_FLD_ADR1_OVERRIDE_EN = 2608; // 8 +static const uint64_t SH_FLD_ADR1_OVERRIDE_LEN = 2609; // 8 +static const uint64_t SH_FLD_ADR1_PHASE_ALIGN_RESET = 2610; // 8 +static const uint64_t SH_FLD_ADR1_PHASE_DEFAULT_EN = 2611; // 8 +static const uint64_t SH_FLD_ADR1_PHASE_EN = 2612; // 8 +static const uint64_t SH_FLD_ADR1_POS_EDGE_ALIGN = 2613; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP = 2614; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2615; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY0 = 2616; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 2617; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC = 2618; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC_LEN = 2619; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_EN = 2620; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_EN_LEN = 2621; // 8 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG = 2622; // 16 +static const uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG_LEN = 2623; // 16 +static const uint64_t SH_FLD_ADR1_ROT = 2624; // 8 +static const uint64_t SH_FLD_ADR1_ROT_LEN = 2625; // 8 +static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE = 2626; // 8 +static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE_EN = 2627; // 8 +static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE_LEN = 2628; // 8 +static const uint64_t SH_FLD_ADR1_RXCAL_DETECT_DONE_META = 2629; // 8 +static const uint64_t SH_FLD_ADR1_RXCAL_PD_CAL_LAG_META = 2630; // 8 +static const uint64_t SH_FLD_ADR1_RXCAL_PD_MAIN_LAG_META = 2631; // 8 +static const uint64_t SH_FLD_ADR1_RXCAL_PD_MAIN_LEAD_META = 2632; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC = 2633; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC_LEN = 2634; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_CON_DC = 2635; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_DAC_PULLUP_DC = 2636; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC = 2637; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC_LEN = 2638; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC = 2639; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 2640; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_FINECAL_2XILSB_DC = 2641; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 2642; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2643; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC = 2644; // 8 +static const uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN = 2645; // 8 +static const uint64_t SH_FLD_ADR1_SLAVE_CAL_CKT_POWERDOWN = 2646; // 8 +static const uint64_t SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE = 2647; // 8 +static const uint64_t SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE_LEN = 2648; // 8 +static const uint64_t SH_FLD_ADR1_SLAVE_VREG_OVERRIDE = 2649; // 8 +static const uint64_t SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC = 2650; // 8 +static const uint64_t SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC_LEN = 2651; // 8 +static const uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS = 2652; // 8 +static const uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS_LEN = 2653; // 8 +static const uint64_t SH_FLD_ADR1_START = 2654; // 8 +static const uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET = 2655; // 8 +static const uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET_LEN = 2656; // 8 +static const uint64_t SH_FLD_ADR1_TSYS = 2657; // 8 +static const uint64_t SH_FLD_ADR1_TSYS_LEN = 2658; // 8 +static const uint64_t SH_FLD_ADR1_VALUE = 2659; // 16 +static const uint64_t SH_FLD_ADR1_VALUE_LEN = 2660; // 16 +static const uint64_t SH_FLD_ADR1_VREG_RXCAL_COMP_OUT_META = 2661; // 8 +static const uint64_t SH_FLD_ADR1_VREG_SLAVE1_COMP_OUT = 2662; // 8 +static const uint64_t SH_FLD_ADR1_VREG_SLAVE2_COMP_OUT = 2663; // 8 +static const uint64_t SH_FLD_ADR_DLL_CAL_ERROR = 2664; // 8 +static const uint64_t SH_FLD_ADR_DLL_CAL_ERROR_FINE = 2665; // 8 +static const uint64_t SH_FLD_ADR_ERROR = 2666; // 8 +static const uint64_t SH_FLD_ADR_ERROR_FINE = 2667; // 8 +static const uint64_t SH_FLD_ADR_GOOD = 2668; // 8 +static const uint64_t SH_FLD_ADR_LEN = 2669; // 4 +static const uint64_t SH_FLD_ADR_SLAVE_SEL = 2670; // 8 +static const uint64_t SH_FLD_ADR_TX_TRISTATE = 2671; // 8 +static const uint64_t SH_FLD_ADS_HANG = 2672; // 1 +static const uint64_t SH_FLD_ADU_ALTDSM_RECOV_ERROR = 2673; // 4 +static const uint64_t SH_FLD_ADU_ALTDSM_XSTOP_ERROR = 2674; // 4 +static const uint64_t SH_FLD_ADU_MALF_ALERT = 2675; // 1 +static const uint64_t SH_FLD_ADU_PBADR_RECOV_ERROR = 2676; // 4 +static const uint64_t SH_FLD_ADU_PBADR_XSTOP_ERROR = 2677; // 4 +static const uint64_t SH_FLD_ADU_PBDAT_RECOV_ERROR = 2678; // 4 +static const uint64_t SH_FLD_ADU_PBDAT_XSTOP_ERROR = 2679; // 4 +static const uint64_t SH_FLD_ADU_RCV_RRC = 2680; // 4 +static const uint64_t SH_FLD_ADU_RCV_XSTOP_ERROR = 2681; // 4 +static const uint64_t SH_FLD_ADU_SND_RECOV_ERROR = 2682; // 4 +static const uint64_t SH_FLD_ADU_SND_XSTOP_ERROR = 2683; // 4 +static const uint64_t SH_FLD_ADU_XCSMP_RECOV_ERROR = 2684; // 4 +static const uint64_t SH_FLD_ADU_XCSMP_XSTOP_ERROR = 2685; // 4 +static const uint64_t SH_FLD_ADVANCE_RD_VALID = 2686; // 8 +static const uint64_t SH_FLD_AECS = 2687; // 6 +static const uint64_t SH_FLD_AECS_LEN = 2688; // 6 +static const uint64_t SH_FLD_AESSHA_LATENCY_CFG = 2689; // 1 +static const uint64_t SH_FLD_AES_LATENCY_CFG = 2690; // 1 +static const uint64_t SH_FLD_AIB_ACCESS_ERROR = 2691; // 30 +static const uint64_t SH_FLD_AIB_ADDRESSING_ERROR = 2692; // 24 +static const uint64_t SH_FLD_AIB_ADDRESS_INVALID = 2693; // 6 +static const uint64_t SH_FLD_AIB_COMMAND_INVALID = 2694; // 30 +static const uint64_t SH_FLD_AIB_DAT_ERR_SIGNALED = 2695; // 24 +static const uint64_t SH_FLD_AIB_FATAL_CLASS_ERROR = 2696; // 30 +static const uint64_t SH_FLD_AIB_INF_CLASS_ERROR = 2697; // 36 +static const uint64_t SH_FLD_AIB_IN_CMD_CTL_PERR = 2698; // 1 +static const uint64_t SH_FLD_AIB_IN_CMD_PERR = 2699; // 1 +static const uint64_t SH_FLD_AIB_IN_DAT_CTL_PERR = 2700; // 1 +static const uint64_t SH_FLD_AIB_PEC_SCOM_ERR = 2701; // 9 +static const uint64_t SH_FLD_AIB_STACK_SCOM_ERR = 2702; // 9 +static const uint64_t SH_FLD_AIL = 2703; // 96 +static const uint64_t SH_FLD_AIL_LEN = 2704; // 96 +static const uint64_t SH_FLD_AI_ECC_CE = 2705; // 1 +static const uint64_t SH_FLD_AI_ECC_UE = 2706; // 1 +static const uint64_t SH_FLD_ALIGN_ON_EVEN_CYCLES = 2707; // 8 +static const uint64_t SH_FLD_ALLOC = 2708; // 24 +static const uint64_t SH_FLD_ALLOC_LEN = 2709; // 24 +static const uint64_t SH_FLD_ALLOW_CRYPTO = 2710; // 1 +static const uint64_t SH_FLD_ALLOW_RD_FIFO_AUTO_RESET = 2711; // 8 +static const uint64_t SH_FLD_ALLOW_REG_WAKEUP_C0 = 2712; // 12 +static const uint64_t SH_FLD_ALLOW_REG_WAKEUP_C1 = 2713; // 12 +static const uint64_t SH_FLD_ALL_BRIDGE_GENERAL_RESET = 2714; // 3 +static const uint64_t SH_FLD_ALL_PORT_GENERAL_RESET = 2715; // 3 +static const uint64_t SH_FLD_ALTD_DATA_ITAG = 2716; // 1 +static const uint64_t SH_FLD_ALTD_DATA_TX = 2717; // 1 +static const uint64_t SH_FLD_ALTD_DATA_TX_LEN = 2718; // 1 +static const uint64_t SH_FLD_ALTD_DATA_TX_OVERWRITE = 2719; // 1 +static const uint64_t SH_FLD_ALT_M = 2720; // 8 +static const uint64_t SH_FLD_ALT_M_LEN = 2721; // 8 +static const uint64_t SH_FLD_ALT_SEGSZ_DIS = 2722; // 1 +static const uint64_t SH_FLD_ALU_ADR = 2723; // 3 +static const uint64_t SH_FLD_ALU_ADR_LEN = 2724; // 3 +static const uint64_t SH_FLD_ALU_FLIP_ENDIAN_BIG = 2725; // 3 +static const uint64_t SH_FLD_ALU_FLIP_ENDIAN_LITTLE = 2726; // 3 +static const uint64_t SH_FLD_ALU_SAFE_LATENCY = 2727; // 3 +static const uint64_t SH_FLD_ALU_SZ = 2728; // 3 +static const uint64_t SH_FLD_ALU_TYPE = 2729; // 3 +static const uint64_t SH_FLD_ALU_TYPE_LEN = 2730; // 3 +static const uint64_t SH_FLD_ALWAYS_RTY = 2731; // 8 +static const uint64_t SH_FLD_AMAX_HIGH = 2732; // 6 +static const uint64_t SH_FLD_AMAX_HIGH_LEN = 2733; // 6 +static const uint64_t SH_FLD_AMAX_LOW = 2734; // 6 +static const uint64_t SH_FLD_AMAX_LOW_LEN = 2735; // 6 +static const uint64_t SH_FLD_AMIN_CFG = 2736; // 6 +static const uint64_t SH_FLD_AMIN_CFG_LEN = 2737; // 6 +static const uint64_t SH_FLD_AMIN_ENABLE_HDAC = 2738; // 4 +static const uint64_t SH_FLD_AMIN_TIMEOUT = 2739; // 6 +static const uint64_t SH_FLD_AMIN_TIMEOUT_LEN = 2740; // 6 +static const uint64_t SH_FLD_AMO_DRAM_SIZE_128B = 2741; // 8 +static const uint64_t SH_FLD_AMO_LIMIT = 2742; // 8 +static const uint64_t SH_FLD_AMO_LIMIT_LEN = 2743; // 8 +static const uint64_t SH_FLD_AMP0_FILTER_MASK = 2744; // 6 +static const uint64_t SH_FLD_AMP0_FILTER_MASK_LEN = 2745; // 6 +static const uint64_t SH_FLD_AMP1_FILTER_MASK = 2746; // 6 +static const uint64_t SH_FLD_AMP1_FILTER_MASK_LEN = 2747; // 6 +static const uint64_t SH_FLD_AMP_CFG = 2748; // 6 +static const uint64_t SH_FLD_AMP_CFG_LEN = 2749; // 6 +static const uint64_t SH_FLD_AMP_GAIN_CNT_MAX = 2750; // 6 +static const uint64_t SH_FLD_AMP_GAIN_CNT_MAX_LEN = 2751; // 6 +static const uint64_t SH_FLD_AMP_INIT_CFG = 2752; // 6 +static const uint64_t SH_FLD_AMP_INIT_CFG_LEN = 2753; // 6 +static const uint64_t SH_FLD_AMP_INIT_TIMEOUT = 2754; // 6 +static const uint64_t SH_FLD_AMP_INIT_TIMEOUT_LEN = 2755; // 6 +static const uint64_t SH_FLD_AMP_RECAL_CFG = 2756; // 6 +static const uint64_t SH_FLD_AMP_RECAL_CFG_LEN = 2757; // 6 +static const uint64_t SH_FLD_AMP_RECAL_TIMEOUT = 2758; // 6 +static const uint64_t SH_FLD_AMP_RECAL_TIMEOUT_LEN = 2759; // 6 +static const uint64_t SH_FLD_AMP_START_VAL = 2760; // 6 +static const uint64_t SH_FLD_AMP_START_VAL_LEN = 2761; // 6 +static const uint64_t SH_FLD_AMP_TIMEOUT = 2762; // 6 +static const uint64_t SH_FLD_AMP_TIMEOUT_LEN = 2763; // 6 +static const uint64_t SH_FLD_AMP_VAL = 2764; // 120 +static const uint64_t SH_FLD_AMP_VAL_LEN = 2765; // 120 +static const uint64_t SH_FLD_AMR = 2766; // 256 +static const uint64_t SH_FLD_AMR_LEN = 2767; // 256 +static const uint64_t SH_FLD_ANALOGTUNE = 2768; // 20 +static const uint64_t SH_FLD_ANALOGTUNE_LEN = 2769; // 20 +static const uint64_t SH_FLD_ANALOG_INPUT_STAB = 2770; // 8 +static const uint64_t SH_FLD_AND_TRIGGER_MODE1 = 2771; // 86 +static const uint64_t SH_FLD_AND_TRIGGER_MODE2 = 2772; // 86 +static const uint64_t SH_FLD_AND_WAT_OUTPUTS = 2773; // 4 +static const uint64_t SH_FLD_ANY_ERROR = 2774; // 4 +static const uint64_t SH_FLD_ANY_REQ_ACTIVE = 2775; // 12 +static const uint64_t SH_FLD_ANY_SLV_ERROR = 2776; // 2 +static const uint64_t SH_FLD_AP = 2777; // 8 +static const uint64_t SH_FLD_AP110_AP010_DELTA_MAX = 2778; // 6 +static const uint64_t SH_FLD_AP110_AP010_DELTA_MAX_LEN = 2779; // 6 +static const uint64_t SH_FLD_APB = 2780; // 8 +static const uint64_t SH_FLD_APB_MASK = 2781; // 8 +static const uint64_t SH_FLD_APC0_ENABLE = 2782; // 2 +static const uint64_t SH_FLD_APC0_SC_RDATA_PARITY_ERRHOLD = 2783; // 2 +static const uint64_t SH_FLD_APC1_ENABLE = 2784; // 2 +static const uint64_t SH_FLD_APCARY = 2785; // 4 +static const uint64_t SH_FLD_APCARY_ADDRESS = 2786; // 2 +static const uint64_t SH_FLD_APCARY_ADDRESS_LEN = 2787; // 2 +static const uint64_t SH_FLD_APCARY_LEN = 2788; // 4 +static const uint64_t SH_FLD_APCCTL_ADR_BAR_MODE = 2789; // 2 +static const uint64_t SH_FLD_APCCTL_CFG_BKILL_INC = 2790; // 2 +static const uint64_t SH_FLD_APCCTL_DISABLE_G = 2791; // 2 +static const uint64_t SH_FLD_APCCTL_DISABLE_LN = 2792; // 2 +static const uint64_t SH_FLD_APCCTL_DISABLE_NN_RN = 2793; // 2 +static const uint64_t SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE = 2794; // 2 +static const uint64_t SH_FLD_APCCTL_DISABLE_VG_NOT_SYS = 2795; // 2 +static const uint64_t SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 2796; // 2 +static const uint64_t SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT = 2797; // 2 +static const uint64_t SH_FLD_APCCTL_ENB_CRESP_EXAM = 2798; // 2 +static const uint64_t SH_FLD_APCCTL_ENB_FRC_ADDR13 = 2799; // 2 +static const uint64_t SH_FLD_APCCTL_HANG_ARE = 2800; // 2 +static const uint64_t SH_FLD_APCCTL_HANG_DEAD = 2801; // 2 +static const uint64_t SH_FLD_APCCTL_MAX_RETRY = 2802; // 2 +static const uint64_t SH_FLD_APCCTL_MAX_RETRY_LEN = 2803; // 2 +static const uint64_t SH_FLD_APCCTL_MEM_SEL_MODE = 2804; // 2 +static const uint64_t SH_FLD_APCCTL_P9_MODE = 2805; // 2 +static const uint64_t SH_FLD_APCCTL_PHB_SEL = 2806; // 2 +static const uint64_t SH_FLD_APCCTL_PHB_SEL_LEN = 2807; // 2 +static const uint64_t SH_FLD_APCCTL_SKIP_G = 2808; // 2 +static const uint64_t SH_FLD_APCCTL_SYSADDR = 2809; // 2 +static const uint64_t SH_FLD_APCCTL_SYSADDR_LEN = 2810; // 2 +static const uint64_t SH_FLD_APC_ARRAY_CMD_CE_ERPT = 2811; // 4 +static const uint64_t SH_FLD_APC_ARRAY_CMD_UE_ERPT = 2812; // 4 +static const uint64_t SH_FLD_APC_COLLISION = 2813; // 2 +static const uint64_t SH_FLD_APC_RDFSM_MASK = 2814; // 2 +static const uint64_t SH_FLD_APC_RDFSM_MASK_LEN = 2815; // 2 +static const uint64_t SH_FLD_APC_SC_RDATA_PARITY_ERRHOLD = 2816; // 2 +static const uint64_t SH_FLD_APX111_HIGH = 2817; // 6 +static const uint64_t SH_FLD_APX111_HIGH_LEN = 2818; // 6 +static const uint64_t SH_FLD_APX111_LOW = 2819; // 6 +static const uint64_t SH_FLD_APX111_LOW_LEN = 2820; // 6 +static const uint64_t SH_FLD_AP_LEN = 2821; // 8 +static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_0 = 2822; // 4 +static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_1 = 2823; // 2 +static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_2 = 2824; // 2 +static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_3 = 2825; // 2 +static const uint64_t SH_FLD_ARB_ARY_CE = 2826; // 6 +static const uint64_t SH_FLD_ARB_ARY_UE = 2827; // 6 +static const uint64_t SH_FLD_ARB_BLIF_COMPLETION_ERROR = 2828; // 30 +static const uint64_t SH_FLD_ARB_COMMON_FATAL_ERROR = 2829; // 30 +static const uint64_t SH_FLD_ARB_ECC_CORRECTABLE_ERROR = 2830; // 30 +static const uint64_t SH_FLD_ARB_ECC_INJECT_ERR = 2831; // 3 +static const uint64_t SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR = 2832; // 30 +static const uint64_t SH_FLD_ARB_EN_SEND_ALL_WRITES = 2833; // 1 +static const uint64_t SH_FLD_ARB_IODA_FATAL_ERROR = 2834; // 30 +static const uint64_t SH_FLD_ARB_MISSED_SCRUB_TICK = 2835; // 6 +static const uint64_t SH_FLD_ARB_MSI_ADDRESS_ERROR = 2836; // 30 +static const uint64_t SH_FLD_ARB_MSI_PE_MATCH_ERROR = 2837; // 30 +static const uint64_t SH_FLD_ARB_PCT_TIMEOUT_ERROR = 2838; // 30 +static const uint64_t SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 2839; // 30 +static const uint64_t SH_FLD_ARB_RCVD_FATAL_ERROR_MSG = 2840; // 30 +static const uint64_t SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG = 2841; // 30 +static const uint64_t SH_FLD_ARB_RTT_PENUM_INVALID_ERROR = 2842; // 30 +static const uint64_t SH_FLD_ARB_STALL = 2843; // 1 +static const uint64_t SH_FLD_ARB_STOP = 2844; // 1 +static const uint64_t SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR = 2845; // 30 +static const uint64_t SH_FLD_ARB_TLP_POISON_SIGNALED = 2846; // 30 +static const uint64_t SH_FLD_ARB_TVT_ERROR = 2847; // 30 +static const uint64_t SH_FLD_ARM_SEL = 2848; // 43 +static const uint64_t SH_FLD_ARM_SEL_LEN = 2849; // 43 +static const uint64_t SH_FLD_ARRAY_ADDR = 2850; // 6 +static const uint64_t SH_FLD_ARRAY_ADDR_LEN = 2851; // 6 +static const uint64_t SH_FLD_ARRAY_ECC_CE = 2852; // 2 +static const uint64_t SH_FLD_ARRAY_ECC_UE = 2853; // 2 +static const uint64_t SH_FLD_ARRAY_POINTER_SELECT = 2854; // 6 +static const uint64_t SH_FLD_ARRAY_POINTER_SELECT_LEN = 2855; // 6 +static const uint64_t SH_FLD_ARRAY_SELECT = 2856; // 1 +static const uint64_t SH_FLD_ARRAY_SELECT_LEN = 2857; // 1 +static const uint64_t SH_FLD_ARRAY_WRITE_ASSIST_EN = 2858; // 43 +static const uint64_t SH_FLD_ARX_AIB_CMD_ERROR = 2859; // 1 +static const uint64_t SH_FLD_ARX_AIB_DATA_ECC_CE = 2860; // 1 +static const uint64_t SH_FLD_ARX_AIB_DATA_ECC_UE = 2861; // 1 +static const uint64_t SH_FLD_ARX_AIB_RESP_TIMEOUT = 2862; // 1 +static const uint64_t SH_FLD_ARX_CMD_PTY_ERROR = 2863; // 1 +static const uint64_t SH_FLD_ARX_CTRL_PTY_ERROR = 2864; // 1 +static const uint64_t SH_FLD_ARX_TAG_SRAM_ECC_CE = 2865; // 1 +static const uint64_t SH_FLD_ARX_TAG_SRAM_ECC_UE = 2866; // 1 +static const uint64_t SH_FLD_ARX_TIMEOUT = 2867; // 1 +static const uint64_t SH_FLD_ARX_TIMEOUT_LEN = 2868; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_AIB = 2869; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_AIB_LEN = 2870; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_AT_SSA = 2871; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_BAR_SRAM = 2872; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_CMD_SSA = 2873; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_CMD_SSA_LEN = 2874; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_VPC_SSA = 2875; // 1 +static const uint64_t SH_FLD_ARY_SELECT_ATX_VPC_SSA_LEN = 2876; // 1 +static const uint64_t SH_FLD_ARY_SELECT_CMD_RSP_SRAM = 2877; // 1 +static const uint64_t SH_FLD_ARY_SELECT_CMD_VRQ_SRAM = 2878; // 1 +static const uint64_t SH_FLD_ARY_SELECT_CRESP_SRAM = 2879; // 1 +static const uint64_t SH_FLD_ASSIGN_DONE = 2880; // 1 +static const uint64_t SH_FLD_ASYNC_ERROR = 2881; // 9 +static const uint64_t SH_FLD_ASYNC_IF_ERROR = 2882; // 16 +static const uint64_t SH_FLD_ASYNC_INJ = 2883; // 16 +static const uint64_t SH_FLD_ASYNC_INJ_LEN = 2884; // 16 +static const uint64_t SH_FLD_ASYNC_MODE = 2885; // 8 +static const uint64_t SH_FLD_ASYNC_OBS = 2886; // 43 +static const uint64_t SH_FLD_ASYNC_TYPE = 2887; // 43 +static const uint64_t SH_FLD_AS_RCMD0_PARITY_ERR_ERRHOLD = 2888; // 2 +static const uint64_t SH_FLD_AS_REGS_PARITY_ERR_ERRHOLD = 2889; // 2 +static const uint64_t SH_FLD_AS_REG_RDATA_PERR_ERRHOLD = 2890; // 2 +static const uint64_t SH_FLD_AS_SM_ERRHOLD = 2891; // 2 +static const uint64_t SH_FLD_ATAG_0_15 = 2892; // 1 +static const uint64_t SH_FLD_ATAG_0_15_LEN = 2893; // 1 +static const uint64_t SH_FLD_ATOMIC_ALT_CE_INJ = 2894; // 2 +static const uint64_t SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ = 2895; // 2 +static const uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL = 2896; // 2 +static const uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN = 2897; // 2 +static const uint64_t SH_FLD_ATOMIC_ALT_SUE_INJ = 2898; // 2 +static const uint64_t SH_FLD_ATOMIC_ALT_UE_INJ = 2899; // 2 +static const uint64_t SH_FLD_ATRMISS_ADDR = 2900; // 1 +static const uint64_t SH_FLD_ATRMISS_ADDR_LEN = 2901; // 1 +static const uint64_t SH_FLD_ATRMISS_BDF = 2902; // 1 +static const uint64_t SH_FLD_ATRMISS_BDF_LEN = 2903; // 1 +static const uint64_t SH_FLD_ATRMISS_ENA = 2904; // 1 +static const uint64_t SH_FLD_ATRMISS_FLAG_DMD = 2905; // 1 +static const uint64_t SH_FLD_ATRMISS_FLAG_FENCE = 2906; // 1 +static const uint64_t SH_FLD_ATRMISS_FLAG_MAP = 2907; // 1 +static const uint64_t SH_FLD_ATRMISS_FLAG_OTHER = 2908; // 1 +static const uint64_t SH_FLD_ATRMISS_FLAG_PREF = 2909; // 1 +static const uint64_t SH_FLD_ATRMISS_GPA = 2910; // 1 +static const uint64_t SH_FLD_ATRMISS_IRQENA = 2911; // 1 +static const uint64_t SH_FLD_ATRMISS_PASID = 2912; // 1 +static const uint64_t SH_FLD_ATRMISS_PASID_LEN = 2913; // 1 +static const uint64_t SH_FLD_ATRMISS_RETIRE = 2914; // 1 +static const uint64_t SH_FLD_ATRMISS_SECOND = 2915; // 1 +static const uint64_t SH_FLD_ATRMISS_TRIGGERED = 2916; // 1 +static const uint64_t SH_FLD_ATRR = 2917; // 3 +static const uint64_t SH_FLD_ATR_ARBSTATE = 2918; // 1 +static const uint64_t SH_FLD_ATR_ERR_INJ_PEND = 2919; // 1 +static const uint64_t SH_FLD_ATR_MISS_IRQ = 2920; // 1 +static const uint64_t SH_FLD_ATR_SM_STATE = 2921; // 1 +static const uint64_t SH_FLD_ATR_TIMEOUT = 2922; // 2 +static const uint64_t SH_FLD_ATR_TIMEOUT_LEN = 2923; // 1 +static const uint64_t SH_FLD_ATSD_BAD_TAG = 2924; // 1 +static const uint64_t SH_FLD_ATSD_SM_STATE = 2925; // 1 +static const uint64_t SH_FLD_ATSD_TIMEOUT = 2926; // 2 +static const uint64_t SH_FLD_ATSD_TIMEOUT_LEN = 2927; // 1 +static const uint64_t SH_FLD_ATSREQ = 2928; // 3 +static const uint64_t SH_FLD_ATSTSEL = 2929; // 17 +static const uint64_t SH_FLD_ATSTSEL_LEN = 2930; // 17 +static const uint64_t SH_FLD_ATSXLATE = 2931; // 12 +static const uint64_t SH_FLD_ATS_AT_EA_CE = 2932; // 1 +static const uint64_t SH_FLD_ATS_AT_EA_UE = 2933; // 1 +static const uint64_t SH_FLD_ATS_AT_RSPOUT_CE = 2934; // 1 +static const uint64_t SH_FLD_ATS_AT_RSPOUT_UE = 2935; // 1 +static const uint64_t SH_FLD_ATS_AT_TDRMEM_CE = 2936; // 1 +static const uint64_t SH_FLD_ATS_AT_TDRMEM_UE = 2937; // 1 +static const uint64_t SH_FLD_ATS_INVAL_IODA_TBL_SEL = 2938; // 1 +static const uint64_t SH_FLD_ATS_IODA_ADDR_PERR = 2939; // 1 +static const uint64_t SH_FLD_ATS_NPU_CTRL_PERR = 2940; // 1 +static const uint64_t SH_FLD_ATS_NPU_TOR_PERR = 2941; // 1 +static const uint64_t SH_FLD_ATS_RSVD_19 = 2942; // 1 +static const uint64_t SH_FLD_ATS_SYNC = 2943; // 3 +static const uint64_t SH_FLD_ATS_TCD_PERR = 2944; // 1 +static const uint64_t SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR = 2945; // 1 +static const uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR = 2946; // 1 +static const uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR = 2947; // 1 +static const uint64_t SH_FLD_ATS_TCE_REQ_TO_ERR = 2948; // 1 +static const uint64_t SH_FLD_ATS_TDR_PERR = 2949; // 1 +static const uint64_t SH_FLD_ATS_TVT_ADDR_RANGE_ERR = 2950; // 1 +static const uint64_t SH_FLD_ATS_TVT_ENTRY_INVALID = 2951; // 1 +static const uint64_t SH_FLD_ATS_TVT_PERR = 2952; // 1 +static const uint64_t SH_FLD_ATTENTION = 2953; // 1 +static const uint64_t SH_FLD_ATTN = 2954; // 86 +static const uint64_t SH_FLD_ATX_AT_SRAM_ECC_UE = 2955; // 1 +static const uint64_t SH_FLD_ATX_BAR_SRAM_ECC_UE = 2956; // 1 +static const uint64_t SH_FLD_ATX_CRD_OVERFLOW = 2957; // 1 +static const uint64_t SH_FLD_ATX_CRD_PARITY_ERROR = 2958; // 1 +static const uint64_t SH_FLD_ATX_CRD_UNDERFLOW = 2959; // 1 +static const uint64_t SH_FLD_ATX_FOR_BLCK_UPD = 2960; // 1 +static const uint64_t SH_FLD_ATX_FOR_BLCK_UPD_LEN = 2961; // 1 +static const uint64_t SH_FLD_ATX_FOR_REGS = 2962; // 1 +static const uint64_t SH_FLD_ATX_FOR_REGS_LEN = 2963; // 1 +static const uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR = 2964; // 1 +static const uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN = 2965; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_CI_LD = 2966; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_CI_LD_LEN = 2967; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_DMA = 2968; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_DMA_LEN = 2969; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT = 2970; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT_LEN = 2971; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC = 2972; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN = 2973; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT = 2974; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_LEN = 2975; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC = 2976; // 1 +static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN = 2977; // 1 +static const uint64_t SH_FLD_ATX_INVALID_BAR = 2978; // 1 +static const uint64_t SH_FLD_ATX_LACK_OF_TAG = 2979; // 1 +static const uint64_t SH_FLD_ATX_LIMIT_AT_DEM_IN_PIPE = 2980; // 1 +static const uint64_t SH_FLD_ATX_PAGE_OVERFLOW = 2981; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP = 2982; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2983; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA = 2984; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN = 2985; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_IRQ = 2986; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_IRQ_LEN = 2987; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_IVC = 2988; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_IVC_LEN = 2989; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD = 2990; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2991; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_REGS = 2992; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_REGS_LEN = 2993; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA = 2994; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN = 2995; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP = 2996; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2997; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD = 2998; // 1 +static const uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN = 2999; // 1 +static const uint64_t SH_FLD_ATX_SLOT_OVERFLOW = 3000; // 1 +static const uint64_t SH_FLD_ATX_SRAM_ECC_CE = 3001; // 1 +static const uint64_t SH_FLD_ATX_TAG_RELEASE_ERROR = 3002; // 1 +static const uint64_t SH_FLD_ATX_WB_SRAM_ECC_UE = 3003; // 1 +static const uint64_t SH_FLD_ATYPE = 3004; // 24 +static const uint64_t SH_FLD_ATYPE_LEN = 3005; // 24 +static const uint64_t SH_FLD_AT_BAD_CAM_STATE = 3006; // 1 +static const uint64_t SH_FLD_AT_EA_CE_ESR = 3007; // 1 +static const uint64_t SH_FLD_AT_EA_UE_ESR = 3008; // 1 +static const uint64_t SH_FLD_AT_INVALID_CMD = 3009; // 1 +static const uint64_t SH_FLD_AT_INVALID_I = 3010; // 1 +static const uint64_t SH_FLD_AT_INVALID_IND_BAR = 3011; // 1 +static const uint64_t SH_FLD_AT_INVALID_IND_PZ = 3012; // 1 +static const uint64_t SH_FLD_AT_MULTIPLE_HIT = 3013; // 1 +static const uint64_t SH_FLD_AT_MULTIPLE_PRF_RQ = 3014; // 1 +static const uint64_t SH_FLD_AT_PARITY_ERROR = 3015; // 1 +static const uint64_t SH_FLD_AT_PRF_OVERFLOW = 3016; // 1 +static const uint64_t SH_FLD_AT_PRF_UNDERFLOW = 3017; // 1 +static const uint64_t SH_FLD_AT_TDRMEM_CE_ESR = 3018; // 1 +static const uint64_t SH_FLD_AT_TDRMEM_UE_ESR = 3019; // 1 +static const uint64_t SH_FLD_AT_TOO_LARGE_SLOTID = 3020; // 1 +static const uint64_t SH_FLD_AUE = 3021; // 2 +static const uint64_t SH_FLD_AUE_LEN = 3022; // 2 +static const uint64_t SH_FLD_AUTOINC = 3023; // 12 +static const uint64_t SH_FLD_AUTO_INC = 3024; // 7 +static const uint64_t SH_FLD_AUTO_INCREMENT = 3025; // 3 +static const uint64_t SH_FLD_AUTO_INC_TRIG = 3026; // 6 +static const uint64_t SH_FLD_AUTO_INC_TRIG_LEN = 3027; // 6 +static const uint64_t SH_FLD_AUTO_POST_DECREMENT_FACES = 3028; // 1 +static const uint64_t SH_FLD_AUTO_POST_DECREMENT_PIB = 3029; // 1 +static const uint64_t SH_FLD_AUTO_PRE_INCREMENT_FACES = 3030; // 1 +static const uint64_t SH_FLD_AUTO_PRE_INCREMENT_PIB = 3031; // 1 +static const uint64_t SH_FLD_AUTO_RELOAD_N = 3032; // 2 +static const uint64_t SH_FLD_AUTO_STOP1_DISABLE = 3033; // 12 +static const uint64_t SH_FLD_AUTO_TDM_AND_NOT_OR = 3034; // 5 +static const uint64_t SH_FLD_AUTO_TDM_BW_DIFF = 3035; // 5 +static const uint64_t SH_FLD_AUTO_TDM_BW_DIFF_LEN = 3036; // 5 +static const uint64_t SH_FLD_AUTO_TDM_ERROR_RATE = 3037; // 5 +static const uint64_t SH_FLD_AUTO_TDM_ERROR_RATE_LEN = 3038; // 5 +static const uint64_t SH_FLD_AUTO_TDM_RX = 3039; // 5 +static const uint64_t SH_FLD_AUTO_TDM_TX = 3040; // 5 +static const uint64_t SH_FLD_AUX_DI_LEVEL = 3041; // 2 +static const uint64_t SH_FLD_AUX_DI_REFERENCE = 3042; // 2 +static const uint64_t SH_FLD_AVA = 3043; // 8 +static const uint64_t SH_FLD_AVAIL_GROUPS = 3044; // 2 +static const uint64_t SH_FLD_AVAIL_GROUPS_LEN = 3045; // 2 +static const uint64_t SH_FLD_AVA_LEN = 3046; // 8 +static const uint64_t SH_FLD_AVG_CYCLE_SAMPLE = 3047; // 12 +static const uint64_t SH_FLD_AVG_CYCLE_SAMPLE_LEN = 3048; // 12 +static const uint64_t SH_FLD_AVG_FREQ_TSEL = 3049; // 12 +static const uint64_t SH_FLD_AVG_FREQ_TSEL_LEN = 3050; // 12 +static const uint64_t SH_FLD_AVS_SLAVE0 = 3051; // 1 +static const uint64_t SH_FLD_AVS_SLAVE1 = 3052; // 1 +static const uint64_t SH_FLD_AXFLOW_ERR = 3053; // 1 +static const uint64_t SH_FLD_AXFLOW_ERR_MASK = 3054; // 1 +static const uint64_t SH_FLD_AXPUSH_WRERR = 3055; // 1 +static const uint64_t SH_FLD_AXPUSH_WRERR_MASK = 3056; // 1 +static const uint64_t SH_FLD_AXRCV_DLO_ERR = 3057; // 1 +static const uint64_t SH_FLD_AXRCV_DLO_ERR_MASK = 3058; // 1 +static const uint64_t SH_FLD_AXRCV_DLO_TO = 3059; // 1 +static const uint64_t SH_FLD_AXRCV_DLO_TO_MASK = 3060; // 1 +static const uint64_t SH_FLD_AXRCV_RSVDATA_TO = 3061; // 1 +static const uint64_t SH_FLD_AXRCV_RSVDATA_TO_MASK = 3062; // 1 +static const uint64_t SH_FLD_AXSND_DHI_RTYTO = 3063; // 1 +static const uint64_t SH_FLD_AXSND_DHI_RTYTO_MASK = 3064; // 1 +static const uint64_t SH_FLD_AXSND_DLO_RTYTO = 3065; // 1 +static const uint64_t SH_FLD_AXSND_DLO_RTYTO_MASK = 3066; // 1 +static const uint64_t SH_FLD_AXSND_RSVERR = 3067; // 1 +static const uint64_t SH_FLD_AXSND_RSVERR_MASK = 3068; // 1 +static const uint64_t SH_FLD_AXSND_RSVTO = 3069; // 1 +static const uint64_t SH_FLD_AXSND_RSVTO_MASK = 3070; // 1 +static const uint64_t SH_FLD_A_AP = 3071; // 144 +static const uint64_t SH_FLD_A_AP_LEN = 3072; // 144 +static const uint64_t SH_FLD_A_BAD_DFE_CONV = 3073; // 144 +static const uint64_t SH_FLD_A_BANK_CONTROLS = 3074; // 48 +static const uint64_t SH_FLD_A_BANK_CONTROLS_LEN = 3075; // 48 +static const uint64_t SH_FLD_A_BIST_EN = 3076; // 6 +static const uint64_t SH_FLD_A_CONTROLS = 3077; // 120 +static const uint64_t SH_FLD_A_CONTROLS_LEN = 3078; // 120 +static const uint64_t SH_FLD_A_CTLE_COARSE = 3079; // 48 +static const uint64_t SH_FLD_A_CTLE_COARSE_LEN = 3080; // 48 +static const uint64_t SH_FLD_A_CTLE_GAIN = 3081; // 120 +static const uint64_t SH_FLD_A_CTLE_GAIN_LEN = 3082; // 120 +static const uint64_t SH_FLD_A_CTLE_PEAK = 3083; // 72 +static const uint64_t SH_FLD_A_CTLE_PEAK_LEN = 3084; // 72 +static const uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN = 3085; // 120 +static const uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN = 3086; // 120 +static const uint64_t SH_FLD_A_H10_VAL = 3087; // 72 +static const uint64_t SH_FLD_A_H10_VAL_LEN = 3088; // 72 +static const uint64_t SH_FLD_A_H11_VAL = 3089; // 72 +static const uint64_t SH_FLD_A_H11_VAL_LEN = 3090; // 72 +static const uint64_t SH_FLD_A_H12_VAL = 3091; // 72 +static const uint64_t SH_FLD_A_H12_VAL_LEN = 3092; // 72 +static const uint64_t SH_FLD_A_H1AP_AT_LIMIT = 3093; // 144 +static const uint64_t SH_FLD_A_H1ARATIO_VAL = 3094; // 72 +static const uint64_t SH_FLD_A_H1ARATIO_VAL_LEN = 3095; // 72 +static const uint64_t SH_FLD_A_H1CAL_EN = 3096; // 72 +static const uint64_t SH_FLD_A_H1CAL_VAL = 3097; // 72 +static const uint64_t SH_FLD_A_H1CAL_VAL_LEN = 3098; // 72 +static const uint64_t SH_FLD_A_H1E_VAL = 3099; // 120 +static const uint64_t SH_FLD_A_H1E_VAL_LEN = 3100; // 120 +static const uint64_t SH_FLD_A_H1O_VAL = 3101; // 120 +static const uint64_t SH_FLD_A_H1O_VAL_LEN = 3102; // 120 +static const uint64_t SH_FLD_A_H2E_VAL = 3103; // 72 +static const uint64_t SH_FLD_A_H2E_VAL_LEN = 3104; // 72 +static const uint64_t SH_FLD_A_H2O_VAL = 3105; // 72 +static const uint64_t SH_FLD_A_H2O_VAL_LEN = 3106; // 72 +static const uint64_t SH_FLD_A_H3E_VAL = 3107; // 72 +static const uint64_t SH_FLD_A_H3E_VAL_LEN = 3108; // 72 +static const uint64_t SH_FLD_A_H3O_VAL = 3109; // 72 +static const uint64_t SH_FLD_A_H3O_VAL_LEN = 3110; // 72 +static const uint64_t SH_FLD_A_H4E_VAL = 3111; // 72 +static const uint64_t SH_FLD_A_H4E_VAL_LEN = 3112; // 72 +static const uint64_t SH_FLD_A_H4O_VAL = 3113; // 72 +static const uint64_t SH_FLD_A_H4O_VAL_LEN = 3114; // 72 +static const uint64_t SH_FLD_A_H5E_VAL = 3115; // 72 +static const uint64_t SH_FLD_A_H5E_VAL_LEN = 3116; // 72 +static const uint64_t SH_FLD_A_H5O_VAL = 3117; // 72 +static const uint64_t SH_FLD_A_H5O_VAL_LEN = 3118; // 72 +static const uint64_t SH_FLD_A_H6_VAL = 3119; // 72 +static const uint64_t SH_FLD_A_H6_VAL_LEN = 3120; // 72 +static const uint64_t SH_FLD_A_H7_VAL = 3121; // 72 +static const uint64_t SH_FLD_A_H7_VAL_LEN = 3122; // 72 +static const uint64_t SH_FLD_A_H8_VAL = 3123; // 72 +static const uint64_t SH_FLD_A_H8_VAL_LEN = 3124; // 72 +static const uint64_t SH_FLD_A_H9_VAL = 3125; // 72 +static const uint64_t SH_FLD_A_H9_VAL_LEN = 3126; // 72 +static const uint64_t SH_FLD_A_INTEG_COARSE_GAIN = 3127; // 120 +static const uint64_t SH_FLD_A_INTEG_COARSE_GAIN_LEN = 3128; // 120 +static const uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN = 3129; // 120 +static const uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN = 3130; // 120 +static const uint64_t SH_FLD_A_OFFSET_E0 = 3131; // 120 +static const uint64_t SH_FLD_A_OFFSET_E0_LEN = 3132; // 120 +static const uint64_t SH_FLD_A_OFFSET_E1 = 3133; // 120 +static const uint64_t SH_FLD_A_OFFSET_E1_LEN = 3134; // 120 +static const uint64_t SH_FLD_A_OFFSET_O0 = 3135; // 120 +static const uint64_t SH_FLD_A_OFFSET_O0_LEN = 3136; // 120 +static const uint64_t SH_FLD_A_OFFSET_O1 = 3137; // 120 +static const uint64_t SH_FLD_A_OFFSET_O1_LEN = 3138; // 120 +static const uint64_t SH_FLD_A_PATH_OFF_EVEN = 3139; // 144 +static const uint64_t SH_FLD_A_PATH_OFF_EVEN_LEN = 3140; // 144 +static const uint64_t SH_FLD_A_PATH_OFF_ODD = 3141; // 144 +static const uint64_t SH_FLD_A_PATH_OFF_ODD_LEN = 3142; // 144 +static const uint64_t SH_FLD_A_PR_DFE_CLKADJ = 3143; // 120 +static const uint64_t SH_FLD_A_PR_DFE_CLKADJ_LEN = 3144; // 120 +static const uint64_t SH_FLD_B = 3145; // 8 +static const uint64_t SH_FLD_B0_63 = 3146; // 2 +static const uint64_t SH_FLD_B0_63_LEN = 3147; // 2 +static const uint64_t SH_FLD_B64_87 = 3148; // 2 +static const uint64_t SH_FLD_B64_87_LEN = 3149; // 2 +static const uint64_t SH_FLD_BACKUP_SEEPROM_SELECT = 3150; // 1 +static const uint64_t SH_FLD_BAD_128K_VP_OP = 3151; // 1 +static const uint64_t SH_FLD_BAD_ARRAY_ADDRESS_FACES = 3152; // 1 +static const uint64_t SH_FLD_BAD_ARRAY_ADDRESS_PIB = 3153; // 1 +static const uint64_t SH_FLD_BAD_ARRAY_ADDR_FACES = 3154; // 1 +static const uint64_t SH_FLD_BAD_ARRAY_ADDR_PIB = 3155; // 1 +static const uint64_t SH_FLD_BAD_BLOCK_LOCK = 3156; // 96 +static const uint64_t SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 3157; // 4 +static const uint64_t SH_FLD_BAD_DESKEW = 3158; // 96 +static const uint64_t SH_FLD_BAD_EYE_OPT_BER = 3159; // 96 +static const uint64_t SH_FLD_BAD_EYE_OPT_HEIGHT = 3160; // 96 +static const uint64_t SH_FLD_BAD_EYE_OPT_WIDTH = 3161; // 96 +static const uint64_t SH_FLD_BAD_HANDSHAKE_AT_START = 3162; // 2 +static const uint64_t SH_FLD_BAD_LANE1 = 3163; // 4 +static const uint64_t SH_FLD_BAD_LANE1_GCRMSG = 3164; // 4 +static const uint64_t SH_FLD_BAD_LANE1_GCRMSG_LEN = 3165; // 4 +static const uint64_t SH_FLD_BAD_LANE1_LEN = 3166; // 4 +static const uint64_t SH_FLD_BAD_LANE2 = 3167; // 4 +static const uint64_t SH_FLD_BAD_LANE2_GCRMSG = 3168; // 4 +static const uint64_t SH_FLD_BAD_LANE2_GCRMSG_LEN = 3169; // 4 +static const uint64_t SH_FLD_BAD_LANE2_LEN = 3170; // 4 +static const uint64_t SH_FLD_BAD_LANE_CODE = 3171; // 4 +static const uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG = 3172; // 4 +static const uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG_LEN = 3173; // 4 +static const uint64_t SH_FLD_BAD_LANE_CODE_LEN = 3174; // 4 +static const uint64_t SH_FLD_BAD_LANE_DURATION = 3175; // 2 +static const uint64_t SH_FLD_BAD_LANE_DURATION_LEN = 3176; // 2 +static const uint64_t SH_FLD_BAD_LANE_MAX = 3177; // 2 +static const uint64_t SH_FLD_BAD_LANE_MAX_LEN = 3178; // 2 +static const uint64_t SH_FLD_BAD_SKEW = 3179; // 96 +static const uint64_t SH_FLD_BANDSEL = 3180; // 20 +static const uint64_t SH_FLD_BANDSEL_LEN = 3181; // 20 +static const uint64_t SH_FLD_BANK = 3182; // 24 +static const uint64_t SH_FLD_BANK0_BIT_MAP = 3183; // 8 +static const uint64_t SH_FLD_BANK0_BIT_MAP_LEN = 3184; // 8 +static const uint64_t SH_FLD_BANK1_BIT_MAP = 3185; // 8 +static const uint64_t SH_FLD_BANK1_BIT_MAP_LEN = 3186; // 8 +static const uint64_t SH_FLD_BANK2_BIT_MAP = 3187; // 8 +static const uint64_t SH_FLD_BANK2_BIT_MAP_LEN = 3188; // 8 +static const uint64_t SH_FLD_BANK_GROUP0_BIT_MAP = 3189; // 8 +static const uint64_t SH_FLD_BANK_GROUP0_BIT_MAP_LEN = 3190; // 8 +static const uint64_t SH_FLD_BANK_GROUP1_BIT_MAP = 3191; // 8 +static const uint64_t SH_FLD_BANK_GROUP1_BIT_MAP_LEN = 3192; // 8 +static const uint64_t SH_FLD_BANK_MODE = 3193; // 162 +static const uint64_t SH_FLD_BANK_ON_RUNN_MATCH = 3194; // 43 +static const uint64_t SH_FLD_BANK_SEL_A = 3195; // 48 +static const uint64_t SH_FLD_BAR = 3196; // 6 +static const uint64_t SH_FLD_BAR1_EN = 3197; // 4 +static const uint64_t SH_FLD_BAR1_MS_GROUP_CHIP = 3198; // 2 +static const uint64_t SH_FLD_BAR1_MS_GROUP_CHIP_LEN = 3199; // 2 +static const uint64_t SH_FLD_BAR1_SIZE = 3200; // 2 +static const uint64_t SH_FLD_BAR1_SIZE_LEN = 3201; // 2 +static const uint64_t SH_FLD_BAR1_STARTING_ADDRESS = 3202; // 4 +static const uint64_t SH_FLD_BAR1_STARTING_ADDRESS_LEN = 3203; // 4 +static const uint64_t SH_FLD_BAR1_SYSTEM = 3204; // 2 +static const uint64_t SH_FLD_BAR1_SYSTEM_LEN = 3205; // 2 +static const uint64_t SH_FLD_BARSEL = 3206; // 12 +static const uint64_t SH_FLD_BAR_LEN = 3207; // 6 +static const uint64_t SH_FLD_BAR_PE = 3208; // 4 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR1 = 3209; // 1 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR2 = 3210; // 1 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR3 = 3211; // 1 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR4 = 3212; // 1 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR5 = 3213; // 1 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR6 = 3214; // 1 +static const uint64_t SH_FLD_BAR_PIB_ON_ERROR7 = 3215; // 1 +static const uint64_t SH_FLD_BAR_VEC_0_3 = 3216; // 1 +static const uint64_t SH_FLD_BAR_VEC_0_3_LEN = 3217; // 1 +static const uint64_t SH_FLD_BASE = 3218; // 26 +static const uint64_t SH_FLD_BASE_ADDR = 3219; // 2 +static const uint64_t SH_FLD_BASE_ADDR_LEN = 3220; // 2 +static const uint64_t SH_FLD_BASE_IDLE_COUNT = 3221; // 8 +static const uint64_t SH_FLD_BASE_IDLE_COUNT_LEN = 3222; // 8 +static const uint64_t SH_FLD_BASE_LEN = 3223; // 26 +static const uint64_t SH_FLD_BASE_UPPER_BITS = 3224; // 1 +static const uint64_t SH_FLD_BASE_UPPER_BITS_LEN = 3225; // 1 +static const uint64_t SH_FLD_BBUF_AIDX = 3226; // 3 +static const uint64_t SH_FLD_BBUF_AIDX_LEN = 3227; // 3 +static const uint64_t SH_FLD_BBUF_RSRC = 3228; // 3 +static const uint64_t SH_FLD_BBUF_RSRC_LEN = 3229; // 3 +static const uint64_t SH_FLD_BBUF_WSRC = 3230; // 3 +static const uint64_t SH_FLD_BBUF_WSRC_LEN = 3231; // 3 +static const uint64_t SH_FLD_BBWR_MASK = 3232; // 3 +static const uint64_t SH_FLD_BBWR_MASK_LEN = 3233; // 3 +static const uint64_t SH_FLD_BCAST_DONE = 3234; // 1 +static const uint64_t SH_FLD_BCDE_CE = 3235; // 1 +static const uint64_t SH_FLD_BCDE_CE_MASK = 3236; // 1 +static const uint64_t SH_FLD_BCDE_OCITRANS = 3237; // 1 +static const uint64_t SH_FLD_BCDE_OCITRANS_LEN = 3238; // 1 +static const uint64_t SH_FLD_BCDE_OCI_DATERR = 3239; // 1 +static const uint64_t SH_FLD_BCDE_OCI_DATERR_MASK = 3240; // 1 +static const uint64_t SH_FLD_BCDE_PB_ACK_DEAD = 3241; // 1 +static const uint64_t SH_FLD_BCDE_PB_ACK_DEAD_MASK = 3242; // 1 +static const uint64_t SH_FLD_BCDE_PB_ADRERR = 3243; // 1 +static const uint64_t SH_FLD_BCDE_PB_ADRERR_MASK = 3244; // 1 +static const uint64_t SH_FLD_BCDE_RDDATATO_ERR = 3245; // 1 +static const uint64_t SH_FLD_BCDE_RDDATATO_ERR_MASK = 3246; // 1 +static const uint64_t SH_FLD_BCDE_SETUP_ERR = 3247; // 1 +static const uint64_t SH_FLD_BCDE_SETUP_ERR_MASK = 3248; // 1 +static const uint64_t SH_FLD_BCDE_SUE_ERR = 3249; // 1 +static const uint64_t SH_FLD_BCDE_SUE_ERR_MASK = 3250; // 1 +static const uint64_t SH_FLD_BCDE_UE_ERR = 3251; // 1 +static const uint64_t SH_FLD_BCDE_UE_ERR_MASK = 3252; // 1 +static const uint64_t SH_FLD_BCECSR_OVERRIDE_EN = 3253; // 12 +static const uint64_t SH_FLD_BCE_BUSY_HIGH = 3254; // 12 +static const uint64_t SH_FLD_BCE_BUSY_LOW = 3255; // 12 +static const uint64_t SH_FLD_BCE_ERROR = 3256; // 13 +static const uint64_t SH_FLD_BCE_TIMEOUT = 3257; // 24 +static const uint64_t SH_FLD_BCUE_OCITRANS = 3258; // 1 +static const uint64_t SH_FLD_BCUE_OCITRANS_LEN = 3259; // 1 +static const uint64_t SH_FLD_BCUE_OCI_DATERR = 3260; // 1 +static const uint64_t SH_FLD_BCUE_OCI_DATERR_MASK = 3261; // 1 +static const uint64_t SH_FLD_BCUE_PB_ACK_DEAD = 3262; // 1 +static const uint64_t SH_FLD_BCUE_PB_ACK_DEAD_MASK = 3263; // 1 +static const uint64_t SH_FLD_BCUE_PB_ADRERR = 3264; // 1 +static const uint64_t SH_FLD_BCUE_PB_ADRERR_MASK = 3265; // 1 +static const uint64_t SH_FLD_BCUE_SETUP_ERR = 3266; // 1 +static const uint64_t SH_FLD_BCUE_SETUP_ERR_MASK = 3267; // 1 +static const uint64_t SH_FLD_BDF = 3268; // 52 +static const uint64_t SH_FLD_BDF2PE_00 = 3269; // 1 +static const uint64_t SH_FLD_BDF2PE_01 = 3270; // 1 +static const uint64_t SH_FLD_BDF2PE_02 = 3271; // 1 +static const uint64_t SH_FLD_BDF2PE_10 = 3272; // 1 +static const uint64_t SH_FLD_BDF2PE_11 = 3273; // 1 +static const uint64_t SH_FLD_BDF2PE_12 = 3274; // 1 +static const uint64_t SH_FLD_BDF2PE_20 = 3275; // 1 +static const uint64_t SH_FLD_BDF2PE_21 = 3276; // 1 +static const uint64_t SH_FLD_BDF2PE_22 = 3277; // 1 +static const uint64_t SH_FLD_BDF2PE_30 = 3278; // 1 +static const uint64_t SH_FLD_BDF2PE_31 = 3279; // 1 +static const uint64_t SH_FLD_BDF2PE_32 = 3280; // 1 +static const uint64_t SH_FLD_BDF2PE_40 = 3281; // 1 +static const uint64_t SH_FLD_BDF2PE_41 = 3282; // 1 +static const uint64_t SH_FLD_BDF2PE_42 = 3283; // 1 +static const uint64_t SH_FLD_BDF2PE_50 = 3284; // 1 +static const uint64_t SH_FLD_BDF2PE_51 = 3285; // 1 +static const uint64_t SH_FLD_BDF2PE_52 = 3286; // 1 +static const uint64_t SH_FLD_BDF_LEN = 3287; // 52 +static const uint64_t SH_FLD_BE = 3288; // 102 +static const uint64_t SH_FLD_BEAT_NUM = 3289; // 1 +static const uint64_t SH_FLD_BEAT_NUM_ERR = 3290; // 1 +static const uint64_t SH_FLD_BEAT_REC = 3291; // 1 +static const uint64_t SH_FLD_BEAT_REC_ERR = 3292; // 1 +static const uint64_t SH_FLD_BENIGN_PTR_DATA = 3293; // 2 +static const uint64_t SH_FLD_BER_CFG = 3294; // 120 +static const uint64_t SH_FLD_BER_CFG_LEN = 3295; // 120 +static const uint64_t SH_FLD_BER_CLR_COUNT_ON_READ_EN = 3296; // 6 +static const uint64_t SH_FLD_BER_CLR_TIMER_ON_READ_EN = 3297; // 6 +static const uint64_t SH_FLD_BER_COUNT_FREEZE_EN = 3298; // 6 +static const uint64_t SH_FLD_BER_COUNT_SEL = 3299; // 6 +static const uint64_t SH_FLD_BER_COUNT_SEL_LEN = 3300; // 6 +static const uint64_t SH_FLD_BER_DPIPE_MUX_SEL = 3301; // 120 +static const uint64_t SH_FLD_BER_EN = 3302; // 6 +static const uint64_t SH_FLD_BER_TIMEOUT = 3303; // 6 +static const uint64_t SH_FLD_BER_TIMEOUT_LEN = 3304; // 6 +static const uint64_t SH_FLD_BER_TIMER_FREEZE_EN = 3305; // 6 +static const uint64_t SH_FLD_BER_TIMER_SEL = 3306; // 6 +static const uint64_t SH_FLD_BER_TIMER_SEL_LEN = 3307; // 6 +static const uint64_t SH_FLD_BE_ACC_ERROR_0 = 3308; // 4 +static const uint64_t SH_FLD_BE_ACC_ERROR_1 = 3309; // 2 +static const uint64_t SH_FLD_BE_ACC_ERROR_2 = 3310; // 2 +static const uint64_t SH_FLD_BE_ACC_ERROR_3 = 3311; // 2 +static const uint64_t SH_FLD_BE_OV_ERROR_0 = 3312; // 4 +static const uint64_t SH_FLD_BE_OV_ERROR_1 = 3313; // 2 +static const uint64_t SH_FLD_BE_OV_ERROR_2 = 3314; // 2 +static const uint64_t SH_FLD_BE_OV_ERROR_3 = 3315; // 2 +static const uint64_t SH_FLD_BGOFFSET = 3316; // 14 +static const uint64_t SH_FLD_BGOFFSET_LEN = 3317; // 14 +static const uint64_t SH_FLD_BG_SCAN_RATE = 3318; // 3 +static const uint64_t SH_FLD_BG_SCAN_RATE_LEN = 3319; // 3 +static const uint64_t SH_FLD_BHRBA = 3320; // 96 +static const uint64_t SH_FLD_BHRB_FILTER = 3321; // 96 +static const uint64_t SH_FLD_BHRB_FILTER_LEN = 3322; // 96 +static const uint64_t SH_FLD_BHR_DIR_STATE = 3323; // 2 +static const uint64_t SH_FLD_BHR_DIR_STATE_LEN = 3324; // 2 +static const uint64_t SH_FLD_BIG_RSP = 3325; // 1 +static const uint64_t SH_FLD_BIG_STEP = 3326; // 8 +static const uint64_t SH_FLD_BIG_STEP_LEN = 3327; // 8 +static const uint64_t SH_FLD_BISTCLK_EN = 3328; // 2 +static const uint64_t SH_FLD_BISTCLK_EN_LEN = 3329; // 2 +static const uint64_t SH_FLD_BIST_BIT_FAIL_TH = 3330; // 1 +static const uint64_t SH_FLD_BIST_BIT_FAIL_TH_LEN = 3331; // 1 +static const uint64_t SH_FLD_BIST_BUS_DATA_MODE = 3332; // 6 +static const uint64_t SH_FLD_BIST_COMPLETE = 3333; // 1 +static const uint64_t SH_FLD_BIST_CUPLL_LOCK_CHECK_EN = 3334; // 6 +static const uint64_t SH_FLD_BIST_CU_PLL_ERR = 3335; // 4 +static const uint64_t SH_FLD_BIST_DONE = 3336; // 6 +static const uint64_t SH_FLD_BIST_EN = 3337; // 13 +static const uint64_t SH_FLD_BIST_ENABLE = 3338; // 1 +static const uint64_t SH_FLD_BIST_ERR = 3339; // 96 +static const uint64_t SH_FLD_BIST_ERROR = 3340; // 1 +static const uint64_t SH_FLD_BIST_ERROR_LEN = 3341; // 1 +static const uint64_t SH_FLD_BIST_ERR_A = 3342; // 48 +static const uint64_t SH_FLD_BIST_ERR_B = 3343; // 48 +static const uint64_t SH_FLD_BIST_ERR_E = 3344; // 48 +static const uint64_t SH_FLD_BIST_EXT_START_MODE = 3345; // 6 +static const uint64_t SH_FLD_BIST_EYE_A_WIDTH = 3346; // 6 +static const uint64_t SH_FLD_BIST_EYE_A_WIDTH_LEN = 3347; // 6 +static const uint64_t SH_FLD_BIST_EYE_B_WIDTH = 3348; // 6 +static const uint64_t SH_FLD_BIST_EYE_B_WIDTH_LEN = 3349; // 6 +static const uint64_t SH_FLD_BIST_INIT_DISABLE = 3350; // 6 +static const uint64_t SH_FLD_BIST_INIT_DISABLE_LEN = 3351; // 6 +static const uint64_t SH_FLD_BIST_INIT_DONE = 3352; // 6 +static const uint64_t SH_FLD_BIST_LL_ERR = 3353; // 2 +static const uint64_t SH_FLD_BIST_LL_TEST_EN = 3354; // 2 +static const uint64_t SH_FLD_BIST_MIN_EYE_WIDTH = 3355; // 6 +static const uint64_t SH_FLD_BIST_MIN_EYE_WIDTH_LEN = 3356; // 6 +static const uint64_t SH_FLD_BIST_NO_EDGE_DET = 3357; // 6 +static const uint64_t SH_FLD_BIST_PIPE_DATA_SHIFT = 3358; // 48 +static const uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT = 3359; // 4 +static const uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN = 3360; // 4 +static const uint64_t SH_FLD_BIST_PRBS_PROP_TIME = 3361; // 6 +static const uint64_t SH_FLD_BIST_PRBS_PROP_TIME_LEN = 3362; // 6 +static const uint64_t SH_FLD_BIST_PRBS_TEST_TIME = 3363; // 6 +static const uint64_t SH_FLD_BIST_PRBS_TEST_TIME_LEN = 3364; // 6 +static const uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL = 3365; // 6 +static const uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN = 3366; // 6 +static const uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL = 3367; // 6 +static const uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN = 3368; // 6 +static const uint64_t SH_FLD_BITS = 3369; // 27 +static const uint64_t SH_FLD_BITSEL = 3370; // 4 +static const uint64_t SH_FLD_BITSEL_LEN = 3371; // 4 +static const uint64_t SH_FLD_BITS_LEN = 3372; // 27 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_0 = 3373; // 6 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_0_LEN = 3374; // 6 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_1 = 3375; // 3 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_1_LEN = 3376; // 3 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_2 = 3377; // 3 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_2_LEN = 3378; // 3 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_3 = 3379; // 3 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_3_LEN = 3380; // 3 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE = 3381; // 1 +static const uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN = 3382; // 1 +static const uint64_t SH_FLD_BKINV_INTERLOCK_DIS = 3383; // 1 +static const uint64_t SH_FLD_BKLG0 = 3384; // 1 +static const uint64_t SH_FLD_BKLG0_LEN = 3385; // 1 +static const uint64_t SH_FLD_BKLG1 = 3386; // 1 +static const uint64_t SH_FLD_BKLG1_LEN = 3387; // 1 +static const uint64_t SH_FLD_BKLG2 = 3388; // 1 +static const uint64_t SH_FLD_BKLG2_LEN = 3389; // 1 +static const uint64_t SH_FLD_BKLG3 = 3390; // 1 +static const uint64_t SH_FLD_BKLG3_LEN = 3391; // 1 +static const uint64_t SH_FLD_BKLG4 = 3392; // 1 +static const uint64_t SH_FLD_BKLG4_LEN = 3393; // 1 +static const uint64_t SH_FLD_BKLG5 = 3394; // 1 +static const uint64_t SH_FLD_BKLG5_LEN = 3395; // 1 +static const uint64_t SH_FLD_BKLG6 = 3396; // 1 +static const uint64_t SH_FLD_BKLG6_LEN = 3397; // 1 +static const uint64_t SH_FLD_BKLG7 = 3398; // 1 +static const uint64_t SH_FLD_BKLG7_LEN = 3399; // 1 +static const uint64_t SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR = 3400; // 30 +static const uint64_t SH_FLD_BLK_UPDT_DONE = 3401; // 1 +static const uint64_t SH_FLD_BLOCK = 3402; // 24 +static const uint64_t SH_FLD_BLOCKID = 3403; // 15 +static const uint64_t SH_FLD_BLOCKID_LEN = 3404; // 15 +static const uint64_t SH_FLD_BLOCKY0 = 3405; // 24 +static const uint64_t SH_FLD_BLOCKY1 = 3406; // 24 +static const uint64_t SH_FLD_BLOCK_ACTIVE = 3407; // 6 +static const uint64_t SH_FLD_BLOCK_ALL_WKUP_EVENTS = 3408; // 30 +static const uint64_t SH_FLD_BLOCK_CMD_OVERLAP = 3409; // 1 +static const uint64_t SH_FLD_BLOCK_INTR_INPUTS = 3410; // 24 +static const uint64_t SH_FLD_BLOCK_LEN = 3411; // 24 +static const uint64_t SH_FLD_BLOCK_MUX_PORT_SEL = 3412; // 2 +static const uint64_t SH_FLD_BLOCK_MUX_PORT_SEL_LEN = 3413; // 2 +static const uint64_t SH_FLD_BLOCK_REG_WKUP_EVENTS = 3414; // 30 +static const uint64_t SH_FLD_BLOCK_SEL = 3415; // 2 +static const uint64_t SH_FLD_BLOCK_SEL_LEN = 3416; // 2 +static const uint64_t SH_FLD_BNDY = 3417; // 43 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD0 = 3418; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD0_LEN = 3419; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD1 = 3420; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD1_LEN = 3421; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD2 = 3422; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD2_LEN = 3423; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD3 = 3424; // 1 +static const uint64_t SH_FLD_BOOT_VECTOR_WORD3_LEN = 3425; // 1 +static const uint64_t SH_FLD_BRAZOS = 3426; // 1 +static const uint64_t SH_FLD_BREAKPOINT_ERROR = 3427; // 1 +static const uint64_t SH_FLD_BREAK_PENDING = 3428; // 2 +static const uint64_t SH_FLD_BRICK = 3429; // 16 +static const uint64_t SH_FLD_BRICK_DEBUG_MODE = 3430; // 6 +static const uint64_t SH_FLD_BRICK_ENABLE = 3431; // 6 +static const uint64_t SH_FLD_BRIDGE_ENABLE = 3432; // 1 +static const uint64_t SH_FLD_BRIDGE_ERROR = 3433; // 3 +static const uint64_t SH_FLD_BRIDGE_ERROR_RESET = 3434; // 3 +static const uint64_t SH_FLD_BRIDGE_GENERAL_RESET = 3435; // 3 +static const uint64_t SH_FLD_BRIEFING_DATA_SYNC_FR_LEFT = 3436; // 2 +static const uint64_t SH_FLD_BRIEFING_DATA_SYNC_FR_LEFT_LEN = 3437; // 2 +static const uint64_t SH_FLD_BRIEFING_DATA_SYNC_FR_RIGHT = 3438; // 2 +static const uint64_t SH_FLD_BRIEFING_DATA_SYNC_FR_RIGHT_LEN = 3439; // 2 +static const uint64_t SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_0 = 3440; // 1 +static const uint64_t SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_0_LEN = 3441; // 1 +static const uint64_t SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_1 = 3442; // 1 +static const uint64_t SH_FLD_BRIEFING_DATA_TO_SLAVE_SIDE_1_LEN = 3443; // 1 +static const uint64_t SH_FLD_BRINGUP = 3444; // 4 +static const uint64_t SH_FLD_BRINGUP_LEN = 3445; // 4 +static const uint64_t SH_FLD_BRK0 = 3446; // 1 +static const uint64_t SH_FLD_BRK0_CLUSTER = 3447; // 1 +static const uint64_t SH_FLD_BRK0_CLUSTER_LEN = 3448; // 1 +static const uint64_t SH_FLD_BRK0_NVL = 3449; // 3 +static const uint64_t SH_FLD_BRK0_RLX = 3450; // 3 +static const uint64_t SH_FLD_BRK1 = 3451; // 1 +static const uint64_t SH_FLD_BRK1_CLUSTER = 3452; // 1 +static const uint64_t SH_FLD_BRK1_CLUSTER_LEN = 3453; // 1 +static const uint64_t SH_FLD_BRK1_NVL = 3454; // 3 +static const uint64_t SH_FLD_BRK1_RLX = 3455; // 3 +static const uint64_t SH_FLD_BRK2 = 3456; // 1 +static const uint64_t SH_FLD_BRK2_CLUSTER = 3457; // 1 +static const uint64_t SH_FLD_BRK2_CLUSTER_LEN = 3458; // 1 +static const uint64_t SH_FLD_BRK3 = 3459; // 1 +static const uint64_t SH_FLD_BRK3_CLUSTER = 3460; // 1 +static const uint64_t SH_FLD_BRK3_CLUSTER_LEN = 3461; // 1 +static const uint64_t SH_FLD_BRK4 = 3462; // 1 +static const uint64_t SH_FLD_BRK4_CLUSTER = 3463; // 1 +static const uint64_t SH_FLD_BRK4_CLUSTER_LEN = 3464; // 1 +static const uint64_t SH_FLD_BRK5 = 3465; // 1 +static const uint64_t SH_FLD_BRK5_CLUSTER = 3466; // 1 +static const uint64_t SH_FLD_BRK5_CLUSTER_LEN = 3467; // 1 +static const uint64_t SH_FLD_BROADCAST_SYNC_EN = 3468; // 2 +static const uint64_t SH_FLD_BROADCAST_SYNC_WAIT = 3469; // 2 +static const uint64_t SH_FLD_BROADCAST_SYNC_WAIT_LEN = 3470; // 2 +static const uint64_t SH_FLD_BUF0_REG_DATA0 = 3471; // 2 +static const uint64_t SH_FLD_BUF0_REG_DATA0_LEN = 3472; // 2 +static const uint64_t SH_FLD_BUF1_REG_DATA0 = 3473; // 1 +static const uint64_t SH_FLD_BUF1_REG_DATA0_LEN = 3474; // 1 +static const uint64_t SH_FLD_BUF1_REG_DATA1 = 3475; // 1 +static const uint64_t SH_FLD_BUF1_REG_DATA1_LEN = 3476; // 1 +static const uint64_t SH_FLD_BUFFER = 3477; // 12 +static const uint64_t SH_FLD_BUFFER_OVERRUN = 3478; // 8 +static const uint64_t SH_FLD_BUFFER_STATUS = 3479; // 6 +static const uint64_t SH_FLD_BUFFER_STATUS_LEN = 3480; // 6 +static const uint64_t SH_FLD_BUF_ALLOC_A = 3481; // 4 +static const uint64_t SH_FLD_BUF_ALLOC_B = 3482; // 4 +static const uint64_t SH_FLD_BUF_ALLOC_C = 3483; // 4 +static const uint64_t SH_FLD_BUF_ALLOC_W = 3484; // 4 +static const uint64_t SH_FLD_BUF_INVALIDATE_CTL = 3485; // 4 +static const uint64_t SH_FLD_BURST_WINDOW = 3486; // 8 +static const uint64_t SH_FLD_BURST_WINDOW_LEN = 3487; // 8 +static const uint64_t SH_FLD_BUSY = 3488; // 44 +static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0 = 3489; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN = 3490; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1 = 3491; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN = 3492; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2 = 3493; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN = 3494; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT = 3495; // 8 +static const uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN = 3496; // 8 +static const uint64_t SH_FLD_BUSY_ENABLE = 3497; // 3 +static const uint64_t SH_FLD_BUSY_RESPONSE_CODE = 3498; // 1 +static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_LEN = 3499; // 1 +static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1 = 3500; // 1 +static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN = 3501; // 1 +static const uint64_t SH_FLD_BUSY_STATUS = 3502; // 1 +static const uint64_t SH_FLD_BUSY_STATUS_LEN = 3503; // 1 +static const uint64_t SH_FLD_BUS_ADDR_NVLD_0 = 3504; // 1 +static const uint64_t SH_FLD_BUS_ADDR_NVLD_1 = 3505; // 1 +static const uint64_t SH_FLD_BUS_ADDR_NVLD_2 = 3506; // 1 +static const uint64_t SH_FLD_BUS_ADDR_NVLD_3 = 3507; // 1 +static const uint64_t SH_FLD_BUS_ADDR_P_ERR_0 = 3508; // 1 +static const uint64_t SH_FLD_BUS_ADDR_P_ERR_1 = 3509; // 1 +static const uint64_t SH_FLD_BUS_ADDR_P_ERR_2 = 3510; // 1 +static const uint64_t SH_FLD_BUS_ADDR_P_ERR_3 = 3511; // 1 +static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 = 3512; // 1 +static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 = 3513; // 1 +static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 = 3514; // 1 +static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 = 3515; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 = 3516; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 = 3517; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 = 3518; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 = 3519; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 = 3520; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 = 3521; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 = 3522; // 1 +static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 = 3523; // 1 +static const uint64_t SH_FLD_BUS_BUSY_0 = 3524; // 1 +static const uint64_t SH_FLD_BUS_BUSY_1 = 3525; // 1 +static const uint64_t SH_FLD_BUS_BUSY_2 = 3526; // 1 +static const uint64_t SH_FLD_BUS_BUSY_3 = 3527; // 1 +static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_0 = 3528; // 1 +static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_1 = 3529; // 1 +static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_2 = 3530; // 1 +static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_3 = 3531; // 1 +static const uint64_t SH_FLD_BUS_DATA_REQUEST_0 = 3532; // 1 +static const uint64_t SH_FLD_BUS_DATA_REQUEST_1 = 3533; // 1 +static const uint64_t SH_FLD_BUS_DATA_REQUEST_2 = 3534; // 1 +static const uint64_t SH_FLD_BUS_DATA_REQUEST_3 = 3535; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0 = 3536; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN = 3537; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1 = 3538; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN = 3539; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2 = 3540; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN = 3541; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3 = 3542; // 1 +static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN = 3543; // 1 +static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_0 = 3544; // 1 +static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_1 = 3545; // 1 +static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_2 = 3546; // 1 +static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_3 = 3547; // 1 +static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_0 = 3548; // 1 +static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_1 = 3549; // 1 +static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_2 = 3550; // 1 +static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_3 = 3551; // 1 +static const uint64_t SH_FLD_BUS_ID = 3552; // 12 +static const uint64_t SH_FLD_BUS_ID_LEN = 3553; // 12 +static const uint64_t SH_FLD_BUS_INVALID_COMMAND_0 = 3554; // 1 +static const uint64_t SH_FLD_BUS_INVALID_COMMAND_1 = 3555; // 1 +static const uint64_t SH_FLD_BUS_INVALID_COMMAND_2 = 3556; // 1 +static const uint64_t SH_FLD_BUS_INVALID_COMMAND_3 = 3557; // 1 +static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_0 = 3558; // 1 +static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_1 = 3559; // 1 +static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_2 = 3560; // 1 +static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_3 = 3561; // 1 +static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_0 = 3562; // 1 +static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_1 = 3563; // 1 +static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_2 = 3564; // 1 +static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_3 = 3565; // 1 +static const uint64_t SH_FLD_BUS_PARITY_ERROR_0 = 3566; // 1 +static const uint64_t SH_FLD_BUS_PARITY_ERROR_1 = 3567; // 1 +static const uint64_t SH_FLD_BUS_PARITY_ERROR_2 = 3568; // 1 +static const uint64_t SH_FLD_BUS_PARITY_ERROR_3 = 3569; // 1 +static const uint64_t SH_FLD_BUS_PAR_ERR_0 = 3570; // 1 +static const uint64_t SH_FLD_BUS_PAR_ERR_1 = 3571; // 1 +static const uint64_t SH_FLD_BUS_PAR_ERR_2 = 3572; // 1 +static const uint64_t SH_FLD_BUS_PAR_ERR_3 = 3573; // 1 +static const uint64_t SH_FLD_BUS_READ_NVLD_0 = 3574; // 1 +static const uint64_t SH_FLD_BUS_READ_NVLD_1 = 3575; // 1 +static const uint64_t SH_FLD_BUS_READ_NVLD_2 = 3576; // 1 +static const uint64_t SH_FLD_BUS_READ_NVLD_3 = 3577; // 1 +static const uint64_t SH_FLD_BUS_STOP_ERROR_0 = 3578; // 1 +static const uint64_t SH_FLD_BUS_STOP_ERROR_1 = 3579; // 1 +static const uint64_t SH_FLD_BUS_STOP_ERROR_2 = 3580; // 1 +static const uint64_t SH_FLD_BUS_STOP_ERROR_3 = 3581; // 1 +static const uint64_t SH_FLD_BUS_WIDTH = 3582; // 4 +static const uint64_t SH_FLD_BUS_WIDTH_LEN = 3583; // 4 +static const uint64_t SH_FLD_BUS_WRITE_NVLD_0 = 3584; // 1 +static const uint64_t SH_FLD_BUS_WRITE_NVLD_1 = 3585; // 1 +static const uint64_t SH_FLD_BUS_WRITE_NVLD_2 = 3586; // 1 +static const uint64_t SH_FLD_BUS_WRITE_NVLD_3 = 3587; // 1 +static const uint64_t SH_FLD_BW_SAMPLE_SIZE = 3588; // 5 +static const uint64_t SH_FLD_BW_WINDOW_SIZE = 3589; // 5 +static const uint64_t SH_FLD_BYPASS = 3590; // 1 +static const uint64_t SH_FLD_BYPASSCLKOUT = 3591; // 3 +static const uint64_t SH_FLD_BYPASSING_RESET_SEQUENCE_PIB_I2CM = 3592; // 1 +static const uint64_t SH_FLD_BYPASSN = 3593; // 10 +static const uint64_t SH_FLD_BYTE0_SEL = 3594; // 8 +static const uint64_t SH_FLD_BYTE0_SEL_LEN = 3595; // 8 +static const uint64_t SH_FLD_BYTE1_SEL = 3596; // 8 +static const uint64_t SH_FLD_BYTE1_SEL_LEN = 3597; // 8 +static const uint64_t SH_FLD_BYTE2_SEL = 3598; // 8 +static const uint64_t SH_FLD_BYTE2_SEL_LEN = 3599; // 8 +static const uint64_t SH_FLD_BYTE3_SEL = 3600; // 8 +static const uint64_t SH_FLD_BYTE3_SEL_LEN = 3601; // 8 +static const uint64_t SH_FLD_B_BAD_DFE_CONV = 3602; // 48 +static const uint64_t SH_FLD_B_BANK_CONTROLS = 3603; // 48 +static const uint64_t SH_FLD_B_BANK_CONTROLS_LEN = 3604; // 48 +static const uint64_t SH_FLD_B_BIST_EN = 3605; // 2 +static const uint64_t SH_FLD_B_CONTROLS = 3606; // 48 +static const uint64_t SH_FLD_B_CONTROLS_LEN = 3607; // 48 +static const uint64_t SH_FLD_B_CTLE_COARSE = 3608; // 48 +static const uint64_t SH_FLD_B_CTLE_COARSE_LEN = 3609; // 48 +static const uint64_t SH_FLD_B_CTLE_GAIN = 3610; // 48 +static const uint64_t SH_FLD_B_CTLE_GAIN_LEN = 3611; // 48 +static const uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN = 3612; // 48 +static const uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN = 3613; // 48 +static const uint64_t SH_FLD_B_H1AP_AT_LIMIT = 3614; // 48 +static const uint64_t SH_FLD_B_H1E_VAL = 3615; // 48 +static const uint64_t SH_FLD_B_H1E_VAL_LEN = 3616; // 48 +static const uint64_t SH_FLD_B_H1O_VAL = 3617; // 48 +static const uint64_t SH_FLD_B_H1O_VAL_LEN = 3618; // 48 +static const uint64_t SH_FLD_B_INTEG_COARSE_GAIN = 3619; // 48 +static const uint64_t SH_FLD_B_INTEG_COARSE_GAIN_LEN = 3620; // 48 +static const uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN = 3621; // 48 +static const uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN = 3622; // 48 +static const uint64_t SH_FLD_B_OFFSET_E0 = 3623; // 48 +static const uint64_t SH_FLD_B_OFFSET_E0_LEN = 3624; // 48 +static const uint64_t SH_FLD_B_OFFSET_E1 = 3625; // 48 +static const uint64_t SH_FLD_B_OFFSET_E1_LEN = 3626; // 48 +static const uint64_t SH_FLD_B_OFFSET_O0 = 3627; // 48 +static const uint64_t SH_FLD_B_OFFSET_O0_LEN = 3628; // 48 +static const uint64_t SH_FLD_B_OFFSET_O1 = 3629; // 48 +static const uint64_t SH_FLD_B_OFFSET_O1_LEN = 3630; // 48 +static const uint64_t SH_FLD_B_PATH_OFF_EVEN = 3631; // 48 +static const uint64_t SH_FLD_B_PATH_OFF_EVEN_LEN = 3632; // 48 +static const uint64_t SH_FLD_B_PATH_OFF_ODD = 3633; // 48 +static const uint64_t SH_FLD_B_PATH_OFF_ODD_LEN = 3634; // 48 +static const uint64_t SH_FLD_B_PR_DFE_CLKADJ = 3635; // 48 +static const uint64_t SH_FLD_B_PR_DFE_CLKADJ_LEN = 3636; // 48 +static const uint64_t SH_FLD_C0N_INCDECFSM_STATE_HISTORY_Q = 3637; // 6 +static const uint64_t SH_FLD_C0N_INCDECFSM_STATE_HISTORY_Q_LEN = 3638; // 6 +static const uint64_t SH_FLD_C0N_PDLYFSM_STATE_HISTORY_Q = 3639; // 6 +static const uint64_t SH_FLD_C0N_PDLYFSM_STATE_HISTORY_Q_LEN = 3640; // 6 +static const uint64_t SH_FLD_C0S_INCDECFSM_STATE_HISTORY_Q = 3641; // 6 +static const uint64_t SH_FLD_C0S_INCDECFSM_STATE_HISTORY_Q_LEN = 3642; // 6 +static const uint64_t SH_FLD_C0S_PDLYFSM_STATE_HISTORY_Q = 3643; // 6 +static const uint64_t SH_FLD_C0S_PDLYFSM_STATE_HISTORY_Q_LEN = 3644; // 6 +static const uint64_t SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 3645; // 12 +static const uint64_t SH_FLD_C0_DROPOUT_EVENT_COUNT = 3646; // 12 +static const uint64_t SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN = 3647; // 12 +static const uint64_t SH_FLD_C0_DROPOUT_INAROW_COUNT = 3648; // 12 +static const uint64_t SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN = 3649; // 12 +static const uint64_t SH_FLD_C0_ERRACK_RISE = 3650; // 2 +static const uint64_t SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE = 3651; // 12 +static const uint64_t SH_FLD_C0_IVRM_DROPOUT = 3652; // 12 +static const uint64_t SH_FLD_C0_PSIRFACC_C_RXDATA_RDY_ERR = 3653; // 1 +static const uint64_t SH_FLD_C0_PSIRFACC_RLINK_STATE_LT_02 = 3654; // 1 +static const uint64_t SH_FLD_C0_PSIRXLC_CE_RF = 3655; // 1 +static const uint64_t SH_FLD_C0_PSITXLC_CE_GX_2N = 3656; // 1 +static const uint64_t SH_FLD_C0_PSITXLC_CE_RF = 3657; // 1 +static const uint64_t SH_FLD_C1N_INCDECFSM_STATE_HISTORY_Q = 3658; // 6 +static const uint64_t SH_FLD_C1N_INCDECFSM_STATE_HISTORY_Q_LEN = 3659; // 6 +static const uint64_t SH_FLD_C1N_PDLYFSM_STATE_HISTORY_Q = 3660; // 6 +static const uint64_t SH_FLD_C1N_PDLYFSM_STATE_HISTORY_Q_LEN = 3661; // 6 +static const uint64_t SH_FLD_C1S_INCDECFSM_STATE_HISTORY_Q = 3662; // 6 +static const uint64_t SH_FLD_C1S_INCDECFSM_STATE_HISTORY_Q_LEN = 3663; // 6 +static const uint64_t SH_FLD_C1S_PDLYFSM_STATE_HISTORY_Q = 3664; // 6 +static const uint64_t SH_FLD_C1S_PDLYFSM_STATE_HISTORY_Q_LEN = 3665; // 6 +static const uint64_t SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 3666; // 12 +static const uint64_t SH_FLD_C1_COUNT_LT = 3667; // 86 +static const uint64_t SH_FLD_C1_COUNT_LT_LEN = 3668; // 86 +static const uint64_t SH_FLD_C1_DROPOUT_EVENT_COUNT = 3669; // 12 +static const uint64_t SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN = 3670; // 12 +static const uint64_t SH_FLD_C1_DROPOUT_INAROW_COUNT = 3671; // 12 +static const uint64_t SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN = 3672; // 12 +static const uint64_t SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE = 3673; // 12 +static const uint64_t SH_FLD_C1_INAROW_MODE = 3674; // 86 +static const uint64_t SH_FLD_C1_IVRM_DROPOUT = 3675; // 12 +static const uint64_t SH_FLD_C1_PSIRXBFF_DATA_PCK = 3676; // 1 +static const uint64_t SH_FLD_C1_PSIRXEI_SHIFT_PCK = 3677; // 1 +static const uint64_t SH_FLD_C1_PSIRXEI_TRANSMIT_PCK = 3678; // 1 +static const uint64_t SH_FLD_C1_PSIRXINS_DATA_PCK = 3679; // 1 +static const uint64_t SH_FLD_C1_PSIRXINS_OVERRUN = 3680; // 1 +static const uint64_t SH_FLD_C1_PSIRXINS_RFGSHIFT_PCK = 3681; // 1 +static const uint64_t SH_FLD_C1_PSIRXINS_RZRTMP_PCK = 3682; // 1 +static const uint64_t SH_FLD_C1_PSITXBFF_TDO_PCK = 3683; // 1 +static const uint64_t SH_FLD_C1_PSITXEI_SHIFT_PCK = 3684; // 1 +static const uint64_t SH_FLD_C1_PSITXEI_TRANSMIT_PCK = 3685; // 1 +static const uint64_t SH_FLD_C1_PSITXINS_DATA_PCK = 3686; // 1 +static const uint64_t SH_FLD_C1_PSITXINS_PARITY = 3687; // 1 +static const uint64_t SH_FLD_C1_PSITXINS_TZRTMP_PCK = 3688; // 1 +static const uint64_t SH_FLD_C1_PSITXINS_UNDERRUN = 3689; // 1 +static const uint64_t SH_FLD_C2_COUNT_LT = 3690; // 86 +static const uint64_t SH_FLD_C2_COUNT_LT_LEN = 3691; // 86 +static const uint64_t SH_FLD_C2_INAROW_MODE = 3692; // 86 +static const uint64_t SH_FLD_C2_PSIRFACC_RADDR_PCK = 3693; // 1 +static const uint64_t SH_FLD_C2_PSIRFACC_RCTRL_PCK = 3694; // 1 +static const uint64_t SH_FLD_C2_PSIRXBFF_DATAO_PCK = 3695; // 1 +static const uint64_t SH_FLD_C2_PSIRXBFF_RFC_PCK = 3696; // 1 +static const uint64_t SH_FLD_C2_PSIRXLC_DATA_GXST1_PCK_2N = 3697; // 1 +static const uint64_t SH_FLD_C2_PSIRXLC_DATA_PCK = 3698; // 1 +static const uint64_t SH_FLD_C2_PSIRXLC_FSM_PCK = 3699; // 1 +static const uint64_t SH_FLD_C2_PSIRXLC_RADDR_PCK = 3700; // 1 +static const uint64_t SH_FLD_C2_PSIRXLC_RCTRL_PCK = 3701; // 1 +static const uint64_t SH_FLD_C2_PSITXBFF_DATA_PCK = 3702; // 1 +static const uint64_t SH_FLD_C2_PSITXBFF_TFC_PCK = 3703; // 1 +static const uint64_t SH_FLD_C2_PSITXLC_FSM_PCK = 3704; // 1 +static const uint64_t SH_FLD_C2_PSITXLC_TADDR_PCK = 3705; // 1 +static const uint64_t SH_FLD_C2_PSITXLC_TCTRL_PCK = 3706; // 1 +static const uint64_t SH_FLD_C2_PSITXLC_TDO_PCK = 3707; // 1 +static const uint64_t SH_FLD_C2_PSITXLC_UE_RF = 3708; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_RDL_FSM_PCK = 3709; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_RFSM_PCK = 3710; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TADDR_PCK = 3711; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TCTRL_PCK = 3712; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TDL_CMD_CTRL_PCK = 3713; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TDL_FSM_PCK = 3714; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TDL_RETRY_ERR = 3715; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TDL_RSP_CTRL_PCK = 3716; // 1 +static const uint64_t SH_FLD_C3_PSIRFACC_TFSM_PCK = 3717; // 1 +static const uint64_t SH_FLD_C3_PSIRXLC_DATA_BUFF_PCK = 3718; // 1 +static const uint64_t SH_FLD_C3_PSIRXLC_UE_RF = 3719; // 1 +static const uint64_t SH_FLD_C3_PSITXLC_DATA_BUFF_PCK = 3720; // 1 +static const uint64_t SH_FLD_C3_PSITXLC_DATA_GXST2_PCK_2N = 3721; // 1 +static const uint64_t SH_FLD_C3_PSITXLC_DATA_GXST3_PCK_2N = 3722; // 1 +static const uint64_t SH_FLD_C3_PSITXLC_UE_GX_2N = 3723; // 1 +static const uint64_t SH_FLD_C405DCU_M_TIMEOUT = 3724; // 1 +static const uint64_t SH_FLD_C405DCU_M_TIMEOUT_MASK = 3725; // 1 +static const uint64_t SH_FLD_C405ICU_M_TIMEOUT = 3726; // 1 +static const uint64_t SH_FLD_C405ICU_M_TIMEOUT_MASK = 3727; // 1 +static const uint64_t SH_FLD_C405_DCU_ECC_CE = 3728; // 1 +static const uint64_t SH_FLD_C405_DCU_ECC_UE = 3729; // 1 +static const uint64_t SH_FLD_C405_ECC_CE = 3730; // 1 +static const uint64_t SH_FLD_C405_ECC_CE_MASK = 3731; // 1 +static const uint64_t SH_FLD_C405_ECC_UE = 3732; // 1 +static const uint64_t SH_FLD_C405_ECC_UE_MASK = 3733; // 1 +static const uint64_t SH_FLD_C405_ICU_ECC_CE = 3734; // 1 +static const uint64_t SH_FLD_C405_ICU_ECC_UE = 3735; // 1 +static const uint64_t SH_FLD_C405_OCI_MACHINECHECK = 3736; // 1 +static const uint64_t SH_FLD_C405_OCI_MACHINECHECK_MASK = 3737; // 1 +static const uint64_t SH_FLD_C4_CARD_TEST_BSC = 3738; // 1 +static const uint64_t SH_FLD_C4_CHIP_MASTER = 3739; // 1 +static const uint64_t SH_FLD_C4_FSI_IN_ENA = 3740; // 1 +static const uint64_t SH_FLD_C4_PSIRFACC_RXSC_PCK = 3741; // 1 +static const uint64_t SH_FLD_C4_PSIRFACC_TXSC_PCK = 3742; // 1 +static const uint64_t SH_FLD_C4_SMD = 3743; // 1 +static const uint64_t SH_FLD_C4_TEST_ENABLE = 3744; // 1 +static const uint64_t SH_FLD_C4_VDN_GPOOD = 3745; // 1 +static const uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT = 3746; // 4 +static const uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT_LEN = 3747; // 4 +static const uint64_t SH_FLD_CACHE_DROPOUT_ENABLE = 3748; // 12 +static const uint64_t SH_FLD_CACHE_DROPOUT_EVENT_COUNT = 3749; // 12 +static const uint64_t SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN = 3750; // 12 +static const uint64_t SH_FLD_CACHE_DROPOUT_INAROW_COUNT = 3751; // 12 +static const uint64_t SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN = 3752; // 12 +static const uint64_t SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 3753; // 12 +static const uint64_t SH_FLD_CACHE_IVRM_DROPOUT = 3754; // 12 +static const uint64_t SH_FLD_CACHE_RD_CE = 3755; // 12 +static const uint64_t SH_FLD_CACHE_RD_CE_AND_UE = 3756; // 12 +static const uint64_t SH_FLD_CACHE_RD_SUE = 3757; // 12 +static const uint64_t SH_FLD_CACHE_RD_UE = 3758; // 12 +static const uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO = 3759; // 12 +static const uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO = 3760; // 12 +static const uint64_t SH_FLD_CAC_ALLOC_DIS = 3761; // 2 +static const uint64_t SH_FLD_CAC_PERR_CHK_DIS = 3762; // 2 +static const uint64_t SH_FLD_CAL0_PE = 3763; // 8 +static const uint64_t SH_FLD_CAL1_PE = 3764; // 8 +static const uint64_t SH_FLD_CAL2_PE = 3765; // 8 +static const uint64_t SH_FLD_CAL3_PE = 3766; // 8 +static const uint64_t SH_FLD_CALIBRATION_ENABLE = 3767; // 8 +static const uint64_t SH_FLD_CALRECAL = 3768; // 10 +static const uint64_t SH_FLD_CALREQ = 3769; // 10 +static const uint64_t SH_FLD_CAL_DONE = 3770; // 1 +static const uint64_t SH_FLD_CAL_LANE_GCRMSG = 3771; // 4 +static const uint64_t SH_FLD_CAL_LANE_GCRMSG_LEN = 3772; // 4 +static const uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG = 3773; // 6 +static const uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG_LEN = 3774; // 6 +static const uint64_t SH_FLD_CAL_LANE_SEL = 3775; // 188 +static const uint64_t SH_FLD_CAL_LANE_VAL_GCRMSG = 3776; // 4 +static const uint64_t SH_FLD_CAL_SM_1HOT = 3777; // 8 +static const uint64_t SH_FLD_CAM256_MAX_CNT = 3778; // 6 +static const uint64_t SH_FLD_CAM256_MAX_CNT_LEN = 3779; // 6 +static const uint64_t SH_FLD_CAM_DISPLAY_REG_0 = 3780; // 1 +static const uint64_t SH_FLD_CAM_DISPLAY_REG_0_LEN = 3781; // 1 +static const uint64_t SH_FLD_CAM_DISPLAY_REG_1 = 3782; // 1 +static const uint64_t SH_FLD_CAM_DISPLAY_REG_1_LEN = 3783; // 1 +static const uint64_t SH_FLD_CANCEL_ACK_ASYNC_IF = 3784; // 8 +static const uint64_t SH_FLD_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD = 3785; // 2 +static const uint64_t SH_FLD_CAPSEL = 3786; // 4 +static const uint64_t SH_FLD_CASCADE = 3787; // 19 +static const uint64_t SH_FLD_CASCADE_LEN = 3788; // 19 +static const uint64_t SH_FLD_CASTOUT_COUNTER = 3789; // 1 +static const uint64_t SH_FLD_CASTOUT_COUNTER_LEN = 3790; // 1 +static const uint64_t SH_FLD_CBS_PROTOCOL_ERR = 3791; // 43 +static const uint64_t SH_FLD_CC = 3792; // 10 +static const uint64_t SH_FLD_CCALBANDSEL = 3793; // 10 +static const uint64_t SH_FLD_CCALBANDSEL_LEN = 3794; // 10 +static const uint64_t SH_FLD_CCALCOMP = 3795; // 10 +static const uint64_t SH_FLD_CCALCVHOLD = 3796; // 10 +static const uint64_t SH_FLD_CCALERR = 3797; // 10 +static const uint64_t SH_FLD_CCALFMAX = 3798; // 10 +static const uint64_t SH_FLD_CCALFMIN = 3799; // 10 +static const uint64_t SH_FLD_CCALLOAD = 3800; // 10 +static const uint64_t SH_FLD_CCALMETH = 3801; // 10 +static const uint64_t SH_FLD_CCFG_GPTR = 3802; // 43 +static const uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ = 3803; // 2 +static const uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE = 3804; // 2 +static const uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ = 3805; // 2 +static const uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE = 3806; // 2 +static const uint64_t SH_FLD_CCS_CNTLQ_PE_HOLD_OUT = 3807; // 2 +static const uint64_t SH_FLD_CCS_FSM_INJ_MODE = 3808; // 2 +static const uint64_t SH_FLD_CCS_FSM_INJ_REG = 3809; // 2 +static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0 = 3810; // 2 +static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN = 3811; // 2 +static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1 = 3812; // 2 +static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN = 3813; // 2 +static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2 = 3814; // 2 +static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN = 3815; // 2 +static const uint64_t SH_FLD_CC_ACTIVITY_0 = 3816; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_0_LEN = 3817; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_1 = 3818; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_1_LEN = 3819; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_2 = 3820; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_2_LEN = 3821; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_3 = 3822; // 1 +static const uint64_t SH_FLD_CC_ACTIVITY_3_LEN = 3823; // 1 +static const uint64_t SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 3824; // 43 +static const uint64_t SH_FLD_CC_CTRL_OPCG_DONE_DC = 3825; // 43 +static const uint64_t SH_FLD_CC_ENABLE_0 = 3826; // 1 +static const uint64_t SH_FLD_CC_ENABLE_1 = 3827; // 1 +static const uint64_t SH_FLD_CC_ENABLE_2 = 3828; // 1 +static const uint64_t SH_FLD_CC_ENABLE_3 = 3829; // 1 +static const uint64_t SH_FLD_CC_ID_0 = 3830; // 1 +static const uint64_t SH_FLD_CC_ID_0_LEN = 3831; // 1 +static const uint64_t SH_FLD_CC_ID_1 = 3832; // 1 +static const uint64_t SH_FLD_CC_ID_1_LEN = 3833; // 1 +static const uint64_t SH_FLD_CC_ID_2 = 3834; // 1 +static const uint64_t SH_FLD_CC_ID_2_LEN = 3835; // 1 +static const uint64_t SH_FLD_CC_ID_3 = 3836; // 1 +static const uint64_t SH_FLD_CC_ID_3_LEN = 3837; // 1 +static const uint64_t SH_FLD_CC_MASK = 3838; // 8 +static const uint64_t SH_FLD_CC_READ_ENABLE_0 = 3839; // 1 +static const uint64_t SH_FLD_CC_READ_ENABLE_1 = 3840; // 1 +static const uint64_t SH_FLD_CC_READ_ENABLE_2 = 3841; // 1 +static const uint64_t SH_FLD_CC_READ_ENABLE_3 = 3842; // 1 +static const uint64_t SH_FLD_CC_WRITE_ENABLE_0 = 3843; // 1 +static const uint64_t SH_FLD_CC_WRITE_ENABLE_1 = 3844; // 1 +static const uint64_t SH_FLD_CC_WRITE_ENABLE_2 = 3845; // 1 +static const uint64_t SH_FLD_CC_WRITE_ENABLE_3 = 3846; // 1 +static const uint64_t SH_FLD_CE = 3847; // 53 +static const uint64_t SH_FLD_CE1_0_OUT = 3848; // 4 +static const uint64_t SH_FLD_CE1_1_OUT = 3849; // 4 +static const uint64_t SH_FLD_CE1_2_OUT = 3850; // 4 +static const uint64_t SH_FLD_CE1_3_OUT = 3851; // 4 +static const uint64_t SH_FLD_CE1_4_OUT = 3852; // 4 +static const uint64_t SH_FLD_CE1_5_OUT = 3853; // 4 +static const uint64_t SH_FLD_CE1_6_OUT = 3854; // 4 +static const uint64_t SH_FLD_CE1_7_OUT = 3855; // 4 +static const uint64_t SH_FLD_CE2_0_OUT = 3856; // 4 +static const uint64_t SH_FLD_CE2_1_OUT = 3857; // 4 +static const uint64_t SH_FLD_CE2_2_OUT = 3858; // 4 +static const uint64_t SH_FLD_CE2_3_OUT = 3859; // 4 +static const uint64_t SH_FLD_CE2_4_OUT = 3860; // 4 +static const uint64_t SH_FLD_CE2_5_OUT = 3861; // 4 +static const uint64_t SH_FLD_CE2_6_OUT = 3862; // 4 +static const uint64_t SH_FLD_CE2_7_OUT = 3863; // 4 +static const uint64_t SH_FLD_CEC_PSI_INTERRUPT = 3864; // 1 +static const uint64_t SH_FLD_CENTAURP_ENABLE_BYPASS_CMD = 3865; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD = 3866; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_CP_ME = 3867; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND = 3868; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_DTAG_CR = 3869; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC = 3870; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_ECRESP = 3871; // 4 +static const uint64_t SH_FLD_CENTAURP_ENABLE_NEW_AMO = 3872; // 4 +static const uint64_t SH_FLD_CENTAURP_INBAND_IS_63 = 3873; // 4 +static const uint64_t SH_FLD_CENTAUR_MODE = 3874; // 4 +static const uint64_t SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED = 3875; // 4 +static const uint64_t SH_FLD_CERR_AXFLOW_ERR = 3876; // 1 +static const uint64_t SH_FLD_CERR_AXFLOW_ERR_LEN = 3877; // 1 +static const uint64_t SH_FLD_CERR_AXPUSH_WRERR = 3878; // 1 +static const uint64_t SH_FLD_CERR_AXPUSH_WRERR_LEN = 3879; // 1 +static const uint64_t SH_FLD_CERR_BAR_PARITY_ERR = 3880; // 1 +static const uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR = 3881; // 1 +static const uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN = 3882; // 1 +static const uint64_t SH_FLD_CERR_BCDE_SETUP_ERR = 3883; // 1 +static const uint64_t SH_FLD_CERR_BCDE_SETUP_ERR_LEN = 3884; // 1 +static const uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR = 3885; // 1 +static const uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN = 3886; // 1 +static const uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR = 3887; // 1 +static const uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR_LEN = 3888; // 1 +static const uint64_t SH_FLD_CERR_BCUE_SETUP_ERR = 3889; // 1 +static const uint64_t SH_FLD_CERR_BCUE_SETUP_ERR_LEN = 3890; // 1 +static const uint64_t SH_FLD_CERR_PBDOUT_PARITY_ERR = 3891; // 1 +static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD = 3892; // 1 +static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN = 3893; // 1 +static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR = 3894; // 1 +static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN = 3895; // 1 +static const uint64_t SH_FLD_CERR_PB_BADCRESP = 3896; // 1 +static const uint64_t SH_FLD_CERR_PB_BADCRESP_LEN = 3897; // 1 +static const uint64_t SH_FLD_CERR_PB_OPERTO = 3898; // 1 +static const uint64_t SH_FLD_CERR_PB_OPERTO_LEN = 3899; // 1 +static const uint64_t SH_FLD_CERR_PB_PARITY_ERR = 3900; // 1 +static const uint64_t SH_FLD_CERR_PB_PARITY_ERR_LEN = 3901; // 1 +static const uint64_t SH_FLD_CERR_PB_RDADRERR_FW = 3902; // 1 +static const uint64_t SH_FLD_CERR_PB_RDADRERR_FW_LEN = 3903; // 1 +static const uint64_t SH_FLD_CERR_PB_RDDATATO_FW = 3904; // 1 +static const uint64_t SH_FLD_CERR_PB_RDDATATO_FW_LEN = 3905; // 1 +static const uint64_t SH_FLD_CERR_PB_UNEXPCRESP = 3906; // 1 +static const uint64_t SH_FLD_CERR_PB_UNEXPCRESP_LEN = 3907; // 1 +static const uint64_t SH_FLD_CERR_PB_UNEXPDATA = 3908; // 1 +static const uint64_t SH_FLD_CERR_PB_UNEXPDATA_LEN = 3909; // 1 +static const uint64_t SH_FLD_CERR_PB_WRADRERR_FW = 3910; // 1 +static const uint64_t SH_FLD_CERR_PB_WRADRERR_FW_LEN = 3911; // 1 +static const uint64_t SH_FLD_CERR_SCOMTB_ERR = 3912; // 1 +static const uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR = 3913; // 1 +static const uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR_LEN = 3914; // 1 +static const uint64_t SH_FLD_CERR_SPARE = 3915; // 1 +static const uint64_t SH_FLD_CERR_SPARE_LEN = 3916; // 1 +static const uint64_t SH_FLD_CE_LEN = 3917; // 10 +static const uint64_t SH_FLD_CFAM_CYCLE_TIME = 3918; // 2 +static const uint64_t SH_FLD_CFAM_CYCLE_TIME_LEN = 3919; // 2 +static const uint64_t SH_FLD_CFAR = 3920; // 96 +static const uint64_t SH_FLD_CFAR_LEN = 3921; // 96 +static const uint64_t SH_FLD_CFG = 3922; // 46 +static const uint64_t SH_FLD_CFG0_SYNC_MODE = 3923; // 2 +static const uint64_t SH_FLD_CFG1_SYNC_MODE = 3924; // 2 +static const uint64_t SH_FLD_CFG_0_1_OP = 3925; // 2 +static const uint64_t SH_FLD_CFG_0_1_OP_LEN = 3926; // 2 +static const uint64_t SH_FLD_CFG_10_11_OP = 3927; // 2 +static const uint64_t SH_FLD_CFG_10_11_OP_LEN = 3928; // 2 +static const uint64_t SH_FLD_CFG_12_13_OP = 3929; // 2 +static const uint64_t SH_FLD_CFG_12_13_OP_LEN = 3930; // 2 +static const uint64_t SH_FLD_CFG_14_15_OP = 3931; // 2 +static const uint64_t SH_FLD_CFG_14_15_OP_LEN = 3932; // 2 +static const uint64_t SH_FLD_CFG_16_17_OP = 3933; // 2 +static const uint64_t SH_FLD_CFG_16_17_OP_LEN = 3934; // 2 +static const uint64_t SH_FLD_CFG_18_19_OP = 3935; // 2 +static const uint64_t SH_FLD_CFG_18_19_OP_LEN = 3936; // 2 +static const uint64_t SH_FLD_CFG_20_21_OP = 3937; // 2 +static const uint64_t SH_FLD_CFG_20_21_OP_LEN = 3938; // 2 +static const uint64_t SH_FLD_CFG_22_23_OP = 3939; // 2 +static const uint64_t SH_FLD_CFG_22_23_OP_LEN = 3940; // 2 +static const uint64_t SH_FLD_CFG_24_25_OP = 3941; // 2 +static const uint64_t SH_FLD_CFG_24_25_OP_LEN = 3942; // 2 +static const uint64_t SH_FLD_CFG_26_27_OP = 3943; // 2 +static const uint64_t SH_FLD_CFG_26_27_OP_LEN = 3944; // 2 +static const uint64_t SH_FLD_CFG_28_29_OP = 3945; // 2 +static const uint64_t SH_FLD_CFG_28_29_OP_LEN = 3946; // 2 +static const uint64_t SH_FLD_CFG_2N_ADDR = 3947; // 8 +static const uint64_t SH_FLD_CFG_2_3_OP = 3948; // 2 +static const uint64_t SH_FLD_CFG_2_3_OP_LEN = 3949; // 2 +static const uint64_t SH_FLD_CFG_30_31_OP = 3950; // 2 +static const uint64_t SH_FLD_CFG_30_31_OP_LEN = 3951; // 2 +static const uint64_t SH_FLD_CFG_4_5_OP = 3952; // 2 +static const uint64_t SH_FLD_CFG_4_5_OP_LEN = 3953; // 2 +static const uint64_t SH_FLD_CFG_6_7_OP = 3954; // 2 +static const uint64_t SH_FLD_CFG_6_7_OP_LEN = 3955; // 2 +static const uint64_t SH_FLD_CFG_8_9_OP = 3956; // 2 +static const uint64_t SH_FLD_CFG_8_9_OP_LEN = 3957; // 2 +static const uint64_t SH_FLD_CFG_ACM_EN = 3958; // 1 +static const uint64_t SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME = 3959; // 8 +static const uint64_t SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 3960; // 8 +static const uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY = 3961; // 8 +static const uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 3962; // 8 +static const uint64_t SH_FLD_CFG_ADDRESS_COUNTER = 3963; // 2 +static const uint64_t SH_FLD_CFG_ADDRESS_COUNTER_LEN = 3964; // 2 +static const uint64_t SH_FLD_CFG_ADDR_BAR = 3965; // 6 +static const uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE = 3966; // 2 +static const uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE_LEN = 3967; // 2 +static const uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH = 3968; // 8 +static const uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN = 3969; // 8 +static const uint64_t SH_FLD_CFG_ALL_PERIODIC_TB = 3970; // 8 +static const uint64_t SH_FLD_CFG_ALL_PERIODIC_TB_LEN = 3971; // 8 +static const uint64_t SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME = 3972; // 8 +static const uint64_t SH_FLD_CFG_AMAP_BANK0 = 3973; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK0_LEN = 3974; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK1 = 3975; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK1_LEN = 3976; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK2 = 3977; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK2_LEN = 3978; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0 = 3979; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0_LEN = 3980; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1 = 3981; // 2 +static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1_LEN = 3982; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL2 = 3983; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL2_LEN = 3984; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL3 = 3985; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL3_LEN = 3986; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL4 = 3987; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL4_LEN = 3988; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL5 = 3989; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL5_LEN = 3990; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL6 = 3991; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL6_LEN = 3992; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL7 = 3993; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL7_LEN = 3994; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL8 = 3995; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL8_LEN = 3996; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL9 = 3997; // 2 +static const uint64_t SH_FLD_CFG_AMAP_COL9_LEN = 3998; // 2 +static const uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT = 3999; // 2 +static const uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT_LEN = 4000; // 2 +static const uint64_t SH_FLD_CFG_AMAP_MRANK0 = 4001; // 2 +static const uint64_t SH_FLD_CFG_AMAP_MRANK0_LEN = 4002; // 2 +static const uint64_t SH_FLD_CFG_AMAP_MRANK1 = 4003; // 2 +static const uint64_t SH_FLD_CFG_AMAP_MRANK1_LEN = 4004; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW0 = 4005; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW0_LEN = 4006; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW1 = 4007; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW10 = 4008; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW10_LEN = 4009; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW11 = 4010; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW11_LEN = 4011; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW12 = 4012; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW12_LEN = 4013; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW13 = 4014; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW13_LEN = 4015; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW14 = 4016; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW14_LEN = 4017; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW15 = 4018; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW15_LEN = 4019; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW16 = 4020; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW16_LEN = 4021; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW17 = 4022; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW17_LEN = 4023; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW1_LEN = 4024; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW2 = 4025; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW2_LEN = 4026; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW3 = 4027; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW3_LEN = 4028; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW4 = 4029; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW4_LEN = 4030; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW5 = 4031; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW5_LEN = 4032; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW6 = 4033; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW6_LEN = 4034; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW7 = 4035; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW7_LEN = 4036; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW8 = 4037; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW8_LEN = 4038; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW9 = 4039; // 2 +static const uint64_t SH_FLD_CFG_AMAP_ROW9_LEN = 4040; // 2 +static const uint64_t SH_FLD_CFG_AMAP_SRANK0 = 4041; // 2 +static const uint64_t SH_FLD_CFG_AMAP_SRANK0_LEN = 4042; // 2 +static const uint64_t SH_FLD_CFG_AMAP_SRANK1 = 4043; // 2 +static const uint64_t SH_FLD_CFG_AMAP_SRANK1_LEN = 4044; // 2 +static const uint64_t SH_FLD_CFG_AMAP_SRANK2 = 4045; // 2 +static const uint64_t SH_FLD_CFG_AMAP_SRANK2_LEN = 4046; // 2 +static const uint64_t SH_FLD_CFG_APM_DD1_MODE = 4047; // 1 +static const uint64_t SH_FLD_CFG_APM_ENABLE = 4048; // 1 +static const uint64_t SH_FLD_CFG_APM_LM_HI_COMP = 4049; // 2 +static const uint64_t SH_FLD_CFG_APM_LM_HI_COMP_LEN = 4050; // 1 +static const uint64_t SH_FLD_CFG_APM_LM_LO_COMP = 4051; // 2 +static const uint64_t SH_FLD_CFG_APM_LM_LO_COMP_LEN = 4052; // 1 +static const uint64_t SH_FLD_CFG_APM_NM_HI_COMP = 4053; // 2 +static const uint64_t SH_FLD_CFG_APM_NM_HI_COMP_LEN = 4054; // 1 +static const uint64_t SH_FLD_CFG_APM_NM_LO_COMP = 4055; // 2 +static const uint64_t SH_FLD_CFG_APM_NM_LO_COMP_LEN = 4056; // 1 +static const uint64_t SH_FLD_CFG_APM_SAMPLE_SEL = 4057; // 1 +static const uint64_t SH_FLD_CFG_APM_SAMPLE_SEL_LEN = 4058; // 1 +static const uint64_t SH_FLD_CFG_APM_SEL = 4059; // 1 +static const uint64_t SH_FLD_CFG_APM_SEL_LEN = 4060; // 1 +static const uint64_t SH_FLD_CFG_A_AGGREGATE = 4061; // 6 +static const uint64_t SH_FLD_CFG_A_CMD_RATE = 4062; // 6 +static const uint64_t SH_FLD_CFG_A_CMD_RATE_LEN = 4063; // 6 +static const uint64_t SH_FLD_CFG_A_GATHER_ENABLE = 4064; // 6 +static const uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS = 4065; // 8 +static const uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN = 4066; // 8 +static const uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS = 4067; // 8 +static const uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 4068; // 8 +static const uint64_t SH_FLD_CFG_BC4_EN = 4069; // 2 +static const uint64_t SH_FLD_CFG_BLOCK_EN = 4070; // 1 +static const uint64_t SH_FLD_CFG_BLOCK_FILTER_EN = 4071; // 1 +static const uint64_t SH_FLD_CFG_BLOCK_FILTER_VPC_EN = 4072; // 1 +static const uint64_t SH_FLD_CFG_BLOCK_GROUP_EN = 4073; // 1 +static const uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY = 4074; // 1 +static const uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY_LEN = 4075; // 1 +static const uint64_t SH_FLD_CFG_BW_SNAPSHOT = 4076; // 8 +static const uint64_t SH_FLD_CFG_BW_SNAPSHOT_LEN = 4077; // 8 +static const uint64_t SH_FLD_CFG_BW_WINDOW_SIZE = 4078; // 8 +static const uint64_t SH_FLD_CFG_BW_WINDOW_SIZE_LEN = 4079; // 8 +static const uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL = 4080; // 12 +static const uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 4081; // 12 +static const uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL = 4082; // 12 +static const uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 4083; // 12 +static const uint64_t SH_FLD_CFG_CAC_ERR_REPAIR_EN = 4084; // 12 +static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE = 4085; // 8 +static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE = 4086; // 8 +static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE = 4087; // 8 +static const uint64_t SH_FLD_CFG_CAL_RANK_ENABLE = 4088; // 8 +static const uint64_t SH_FLD_CFG_CAL_RANK_ENABLE_LEN = 4089; // 8 +static const uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE = 4090; // 8 +static const uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN = 4091; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE = 4092; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE = 4093; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE = 4094; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN = 4095; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE = 4096; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE = 4097; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE = 4098; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN = 4099; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE = 4100; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE = 4101; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE = 4102; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN = 4103; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE = 4104; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR = 4105; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 4106; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 4107; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 4108; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_SINGLE_RANK = 4109; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC = 4110; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN = 4111; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE = 4112; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE = 4113; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE = 4114; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN = 4115; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE = 4116; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE = 4117; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE = 4118; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN = 4119; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE = 4120; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE = 4121; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE = 4122; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN = 4123; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_SINGLE_RANK = 4124; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC = 4125; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN = 4126; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE = 4127; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE = 4128; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE = 4129; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN = 4130; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE = 4131; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE = 4132; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE = 4133; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN = 4134; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE = 4135; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE = 4136; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE = 4137; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN = 4138; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_SINGLE_RANK = 4139; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 4140; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC = 4141; // 8 +static const uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN = 4142; // 8 +static const uint64_t SH_FLD_CFG_CAPI = 4143; // 6 +static const uint64_t SH_FLD_CFG_CASCADE_PMU0 = 4144; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU0_LEN = 4145; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU1 = 4146; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU1_LEN = 4147; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU2 = 4148; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU2_LEN = 4149; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU3 = 4150; // 2 +static const uint64_t SH_FLD_CFG_CASCADE_PMU3_LEN = 4151; // 2 +static const uint64_t SH_FLD_CFG_CCS_ADDR_MUX_SEL = 4152; // 8 +static const uint64_t SH_FLD_CFG_CCS_INST_RESET_ENABLE = 4153; // 8 +static const uint64_t SH_FLD_CFG_CCS_RETRY_DIS = 4154; // 2 +static const uint64_t SH_FLD_CFG_CHG_RATE_GP_MASTER = 4155; // 6 +static const uint64_t SH_FLD_CFG_CHG_RATE_SP_MASTER = 4156; // 6 +static const uint64_t SH_FLD_CFG_CHIPID = 4157; // 1 +static const uint64_t SH_FLD_CFG_CHIPID_LEN = 4158; // 1 +static const uint64_t SH_FLD_CFG_CHIPID_OVERRIDE = 4159; // 1 +static const uint64_t SH_FLD_CFG_CHIP_IS_SYSTEM = 4160; // 3 +static const uint64_t SH_FLD_CFG_CKE_PUP_STATE = 4161; // 8 +static const uint64_t SH_FLD_CFG_CKE_PUP_STATE_LEN = 4162; // 8 +static const uint64_t SH_FLD_CFG_CLOCK_MONITOR_EN = 4163; // 2 +static const uint64_t SH_FLD_CFG_CMD0_BANK = 4164; // 8 +static const uint64_t SH_FLD_CFG_CMD0_BANK_LEN = 4165; // 8 +static const uint64_t SH_FLD_CFG_CMD0_BANK_MATCH_EN = 4166; // 8 +static const uint64_t SH_FLD_CFG_CMD0_BG = 4167; // 8 +static const uint64_t SH_FLD_CFG_CMD0_BG_LEN = 4168; // 8 +static const uint64_t SH_FLD_CFG_CMD0_BG_MATCH_EN = 4169; // 8 +static const uint64_t SH_FLD_CFG_CMD0_MRANK = 4170; // 8 +static const uint64_t SH_FLD_CFG_CMD0_MRANK_LEN = 4171; // 8 +static const uint64_t SH_FLD_CFG_CMD0_MRANK_MATCH_EN = 4172; // 8 +static const uint64_t SH_FLD_CFG_CMD0_SRANK = 4173; // 8 +static const uint64_t SH_FLD_CFG_CMD0_SRANK_LEN = 4174; // 8 +static const uint64_t SH_FLD_CFG_CMD0_SRANK_MATCH_EN = 4175; // 8 +static const uint64_t SH_FLD_CFG_CMD0_TYPE = 4176; // 8 +static const uint64_t SH_FLD_CFG_CMD0_TYPE_LEN = 4177; // 8 +static const uint64_t SH_FLD_CFG_CMD1_BANK = 4178; // 8 +static const uint64_t SH_FLD_CFG_CMD1_BANK_LEN = 4179; // 8 +static const uint64_t SH_FLD_CFG_CMD1_BANK_MATCH_EN = 4180; // 8 +static const uint64_t SH_FLD_CFG_CMD1_BG = 4181; // 8 +static const uint64_t SH_FLD_CFG_CMD1_BG_LEN = 4182; // 8 +static const uint64_t SH_FLD_CFG_CMD1_BG_MATCH_EN = 4183; // 8 +static const uint64_t SH_FLD_CFG_CMD1_MRANK = 4184; // 8 +static const uint64_t SH_FLD_CFG_CMD1_MRANK_LEN = 4185; // 8 +static const uint64_t SH_FLD_CFG_CMD1_MRANK_MATCH_EN = 4186; // 8 +static const uint64_t SH_FLD_CFG_CMD1_SRANK = 4187; // 8 +static const uint64_t SH_FLD_CFG_CMD1_SRANK_LEN = 4188; // 8 +static const uint64_t SH_FLD_CFG_CMD1_SRANK_MATCH_EN = 4189; // 8 +static const uint64_t SH_FLD_CFG_CMD1_TYPE = 4190; // 8 +static const uint64_t SH_FLD_CFG_CMD1_TYPE_LEN = 4191; // 8 +static const uint64_t SH_FLD_CFG_CMD2_BANK = 4192; // 8 +static const uint64_t SH_FLD_CFG_CMD2_BANK_LEN = 4193; // 8 +static const uint64_t SH_FLD_CFG_CMD2_BANK_MATCH_EN = 4194; // 8 +static const uint64_t SH_FLD_CFG_CMD2_BG = 4195; // 8 +static const uint64_t SH_FLD_CFG_CMD2_BG_LEN = 4196; // 8 +static const uint64_t SH_FLD_CFG_CMD2_BG_MATCH_EN = 4197; // 8 +static const uint64_t SH_FLD_CFG_CMD2_MRANK = 4198; // 8 +static const uint64_t SH_FLD_CFG_CMD2_MRANK_LEN = 4199; // 8 +static const uint64_t SH_FLD_CFG_CMD2_MRANK_MATCH_EN = 4200; // 8 +static const uint64_t SH_FLD_CFG_CMD2_SRANK = 4201; // 8 +static const uint64_t SH_FLD_CFG_CMD2_SRANK_LEN = 4202; // 8 +static const uint64_t SH_FLD_CFG_CMD2_SRANK_MATCH_EN = 4203; // 8 +static const uint64_t SH_FLD_CFG_CMD2_TYPE = 4204; // 8 +static const uint64_t SH_FLD_CFG_CMD2_TYPE_LEN = 4205; // 8 +static const uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE = 4206; // 2 +static const uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN = 4207; // 2 +static const uint64_t SH_FLD_CFG_CNPME_BITWISE_ENABLE = 4208; // 1 +static const uint64_t SH_FLD_CFG_CNPME_BITWISE_ENABLE_LEN = 4209; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C0 = 4210; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C0_LEN = 4211; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C1 = 4212; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C1_LEN = 4213; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C2 = 4214; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C2_LEN = 4215; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C3 = 4216; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP0_C3_LEN = 4217; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C0 = 4218; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C0_LEN = 4219; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C1 = 4220; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C1_LEN = 4221; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C2 = 4222; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C2_LEN = 4223; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C3 = 4224; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP1_C3_LEN = 4225; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C0 = 4226; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C0_LEN = 4227; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C1 = 4228; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C1_LEN = 4229; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C2 = 4230; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C2_LEN = 4231; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C3 = 4232; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP2_C3_LEN = 4233; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C0 = 4234; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C0_LEN = 4235; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C1 = 4236; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C1_LEN = 4237; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C2 = 4238; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C2_LEN = 4239; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C3 = 4240; // 1 +static const uint64_t SH_FLD_CFG_CNPME_GRP3_C3_LEN = 4241; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_BITWISE_ENABLE = 4242; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_BITWISE_ENABLE_LEN = 4243; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C0 = 4244; // 2 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C1 = 4245; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C1_LEN = 4246; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C2 = 4247; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C2_LEN = 4248; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C3 = 4249; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C3_LEN = 4250; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C0 = 4251; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C0_LEN = 4252; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C1 = 4253; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C1_LEN = 4254; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C2 = 4255; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C2_LEN = 4256; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C3 = 4257; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C3_LEN = 4258; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C0 = 4259; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C0_LEN = 4260; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C1 = 4261; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C1_LEN = 4262; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C2 = 4263; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C2_LEN = 4264; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C3 = 4265; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C3_LEN = 4266; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C0 = 4267; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C0_LEN = 4268; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C1 = 4269; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C1_LEN = 4270; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C2 = 4271; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C2_LEN = 4272; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C3 = 4273; // 1 +static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C3_LEN = 4274; // 1 +static const uint64_t SH_FLD_CFG_COMPA_PRESP = 4275; // 1 +static const uint64_t SH_FLD_CFG_COMPA_PRESP_LEN = 4276; // 1 +static const uint64_t SH_FLD_CFG_COMPA_PRESP_MASK = 4277; // 1 +static const uint64_t SH_FLD_CFG_COMPA_PRESP_MASK_LEN = 4278; // 1 +static const uint64_t SH_FLD_CFG_COMPA_SCOPE_MASK = 4279; // 1 +static const uint64_t SH_FLD_CFG_COMPA_SCOPE_MASK_LEN = 4280; // 1 +static const uint64_t SH_FLD_CFG_COMPB_PRESP = 4281; // 1 +static const uint64_t SH_FLD_CFG_COMPB_PRESP_LEN = 4282; // 1 +static const uint64_t SH_FLD_CFG_COMPB_PRESP_MASK = 4283; // 1 +static const uint64_t SH_FLD_CFG_COMPB_PRESP_MASK_LEN = 4284; // 1 +static const uint64_t SH_FLD_CFG_COMPB_SCOPE_MASK = 4285; // 1 +static const uint64_t SH_FLD_CFG_COMPB_SCOPE_MASK_LEN = 4286; // 1 +static const uint64_t SH_FLD_CFG_CORE_PUSH_EN = 4287; // 1 +static const uint64_t SH_FLD_CFG_COUNTER_MODE = 4288; // 2 +static const uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 4289; // 12 +static const uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN = 4290; // 12 +static const uint64_t SH_FLD_CFG_CPU_RATIO_OVERRIDE = 4291; // 1 +static const uint64_t SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN = 4292; // 1 +static const uint64_t SH_FLD_CFG_CRESP = 4293; // 2 +static const uint64_t SH_FLD_CFG_CRESP_LEN = 4294; // 2 +static const uint64_t SH_FLD_CFG_CRESP_MASK = 4295; // 2 +static const uint64_t SH_FLD_CFG_CRESP_MASK_LEN = 4296; // 2 +static const uint64_t SH_FLD_CFG_CRESP_POLARITY = 4297; // 2 +static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP = 4298; // 2 +static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN = 4299; // 2 +static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 4300; // 2 +static const uint64_t SH_FLD_CFG_CURRENT_DIMM_TRAP = 4301; // 2 +static const uint64_t SH_FLD_CFG_CURRENT_PORT_TRAP = 4302; // 2 +static const uint64_t SH_FLD_CFG_CURRENT_PORT_TRAP_LEN = 4303; // 2 +static const uint64_t SH_FLD_CFG_DATA_ROT = 4304; // 2 +static const uint64_t SH_FLD_CFG_DATA_ROT_LEN = 4305; // 2 +static const uint64_t SH_FLD_CFG_DATA_ROT_SEED = 4306; // 4 +static const uint64_t SH_FLD_CFG_DATA_ROT_SEED_LEN = 4307; // 4 +static const uint64_t SH_FLD_CFG_DATA_SEED_MODE = 4308; // 2 +static const uint64_t SH_FLD_CFG_DATA_SEED_MODE_LEN = 4309; // 2 +static const uint64_t SH_FLD_CFG_DBG_ENABLE = 4310; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01 = 4311; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01_LEN = 4312; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23 = 4313; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23_LEN = 4314; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01 = 4315; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01_LEN = 4316; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23 = 4317; // 2 +static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23_LEN = 4318; // 2 +static const uint64_t SH_FLD_CFG_DBG_SRQ_ENABLE = 4319; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL0 = 4320; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL0_LEN = 4321; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL1 = 4322; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL1_LEN = 4323; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL2 = 4324; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL2_LEN = 4325; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL3 = 4326; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL3_LEN = 4327; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL4 = 4328; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL4_LEN = 4329; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL5 = 4330; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL5_LEN = 4331; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL6 = 4332; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL6_LEN = 4333; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL7 = 4334; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL7_LEN = 4335; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ = 4336; // 8 +static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN = 4337; // 8 +static const uint64_t SH_FLD_CFG_DCACHE_CAPP = 4338; // 6 +static const uint64_t SH_FLD_CFG_DCACHE_CAPP_LPC_EN = 4339; // 12 +static const uint64_t SH_FLD_CFG_DCBZ_TRASHMODE_EN = 4340; // 12 +static const uint64_t SH_FLD_CFG_DDR4E_BLIND_STEER_MODE = 4341; // 2 +static const uint64_t SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS = 4342; // 8 +static const uint64_t SH_FLD_CFG_DDR_DPHY_NCLK = 4343; // 8 +static const uint64_t SH_FLD_CFG_DDR_DPHY_NCLK_LEN = 4344; // 8 +static const uint64_t SH_FLD_CFG_DDR_DPHY_PCLK = 4345; // 8 +static const uint64_t SH_FLD_CFG_DDR_DPHY_PCLK_LEN = 4346; // 8 +static const uint64_t SH_FLD_CFG_DDR_RESETN = 4347; // 8 +static const uint64_t SH_FLD_CFG_DGEN_FIXED_MODE = 4348; // 2 +static const uint64_t SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK = 4349; // 43 +static const uint64_t SH_FLD_CFG_DISABLE_FAST_PATH = 4350; // 8 +static const uint64_t SH_FLD_CFG_DISABLE_FORCE_TO_ZERO = 4351; // 43 +static const uint64_t SH_FLD_CFG_DISABLE_HEARTBEAT = 4352; // 43 +static const uint64_t SH_FLD_CFG_DISABLE_MALF_PULSE_GEN = 4353; // 43 +static const uint64_t SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK = 4354; // 43 +static const uint64_t SH_FLD_CFG_DISABLE_RCD_RECOVERY = 4355; // 8 +static const uint64_t SH_FLD_CFG_DISABLE_RD_PG_MODE = 4356; // 8 +static const uint64_t SH_FLD_CFG_DISABLE_WR_PG_MODE = 4357; // 8 +static const uint64_t SH_FLD_CFG_DIS_CLK_IN_STR = 4358; // 8 +static const uint64_t SH_FLD_CFG_DIS_SMDR = 4359; // 8 +static const uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP = 4360; // 1 +static const uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN = 4361; // 1 +static const uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL = 4362; // 1 +static const uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 4363; // 1 +static const uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL = 4364; // 1 +static const uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 4365; // 1 +static const uint64_t SH_FLD_CFG_DONE_PRIO_IACK = 4366; // 1 +static const uint64_t SH_FLD_CFG_DONE_PRIO_IACK_LEN = 4367; // 1 +static const uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP = 4368; // 1 +static const uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN = 4369; // 1 +static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH = 4370; // 8 +static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN = 4371; // 8 +static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB = 4372; // 8 +static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN = 4373; // 8 +static const uint64_t SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 4374; // 12 +static const uint64_t SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS = 4375; // 12 +static const uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN = 4376; // 8 +static const uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN = 4377; // 8 +static const uint64_t SH_FLD_CFG_EN = 4378; // 3 +static const uint64_t SH_FLD_CFG_ENABLE_HOST_ATTN = 4379; // 10 +static const uint64_t SH_FLD_CFG_ENABLE_PERFTRACE_FIXED_WIN = 4380; // 1 +static const uint64_t SH_FLD_CFG_ENABLE_PERFTRACE_PRESCALE = 4381; // 1 +static const uint64_t SH_FLD_CFG_ENABLE_SPEC_ATTN = 4382; // 10 +static const uint64_t SH_FLD_CFG_END_ADDR_0 = 4383; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_0_LEN = 4384; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_1 = 4385; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_1_LEN = 4386; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_2 = 4387; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_2_LEN = 4388; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_3 = 4389; // 2 +static const uint64_t SH_FLD_CFG_END_ADDR_3_LEN = 4390; // 2 +static const uint64_t SH_FLD_CFG_ENTER_STR_TIME = 4391; // 8 +static const uint64_t SH_FLD_CFG_ENTER_STR_TIME_LEN = 4392; // 8 +static const uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 4393; // 8 +static const uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 4394; // 8 +static const uint64_t SH_FLD_CFG_EN_RANDCMD_GAP = 4395; // 2 +static const uint64_t SH_FLD_CFG_EVENT0_SELECT = 4396; // 8 +static const uint64_t SH_FLD_CFG_EVENT0_SELECT_LEN = 4397; // 8 +static const uint64_t SH_FLD_CFG_EVENT1_SELECT = 4398; // 8 +static const uint64_t SH_FLD_CFG_EVENT1_SELECT_LEN = 4399; // 8 +static const uint64_t SH_FLD_CFG_EVENT2_SELECT = 4400; // 8 +static const uint64_t SH_FLD_CFG_EVENT2_SELECT_LEN = 4401; // 8 +static const uint64_t SH_FLD_CFG_EVENT3_SELECT = 4402; // 8 +static const uint64_t SH_FLD_CFG_EVENT3_SELECT_LEN = 4403; // 8 +static const uint64_t SH_FLD_CFG_EVENTN = 4404; // 8 +static const uint64_t SH_FLD_CFG_EXTERNAL_FREEZE = 4405; // 2 +static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH = 4406; // 8 +static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN = 4407; // 8 +static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB = 4408; // 8 +static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN = 4409; // 8 +static const uint64_t SH_FLD_CFG_FARB_CLOSE_ALL_PAGES = 4410; // 8 +static const uint64_t SH_FLD_CFG_FINISH_WR_BEFORE_RD = 4411; // 8 +static const uint64_t SH_FLD_CFG_FIXED_SEED = 4412; // 16 +static const uint64_t SH_FLD_CFG_FIXED_SEED1 = 4413; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED1_LEN = 4414; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED2 = 4415; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED2_LEN = 4416; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED3 = 4417; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED3_LEN = 4418; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED4 = 4419; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED4_LEN = 4420; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED5 = 4421; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED5_LEN = 4422; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED6 = 4423; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED6_LEN = 4424; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED7 = 4425; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED7_LEN = 4426; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED8 = 4427; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED8_LEN = 4428; // 2 +static const uint64_t SH_FLD_CFG_FIXED_SEED_LEN = 4429; // 16 +static const uint64_t SH_FLD_CFG_FIXED_WIDTH = 4430; // 2 +static const uint64_t SH_FLD_CFG_FIXED_WIDTH_LEN = 4431; // 2 +static const uint64_t SH_FLD_CFG_FORCE_MCLK_LOW_N = 4432; // 8 +static const uint64_t SH_FLD_CFG_FORCE_SPARE_PUP = 4433; // 8 +static const uint64_t SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS = 4434; // 8 +static const uint64_t SH_FLD_CFG_FUSE_CORE_EN = 4435; // 1 +static const uint64_t SH_FLD_CFG_GLOBAL_PMISC_DIS = 4436; // 2 +static const uint64_t SH_FLD_CFG_GLOBAL_PMISC_MODE = 4437; // 2 +static const uint64_t SH_FLD_CFG_GP_BIT_3_ENABLE = 4438; // 8 +static const uint64_t SH_FLD_CFG_GP_HW_MARK = 4439; // 3 +static const uint64_t SH_FLD_CFG_GP_HW_MARK_LEN = 4440; // 3 +static const uint64_t SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN = 4441; // 1 +static const uint64_t SH_FLD_CFG_HASH_L3_ADDR_EN = 4442; // 12 +static const uint64_t SH_FLD_CFG_HNG_CHK_DISABLE = 4443; // 3 +static const uint64_t SH_FLD_CFG_HOP = 4444; // 6 +static const uint64_t SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 4445; // 12 +static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 = 4446; // 8 +static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT = 4447; // 8 +static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_WEN = 4448; // 8 +static const uint64_t SH_FLD_CFG_INJ_CANCEL_ACK_ERR = 4449; // 8 +static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH = 4450; // 8 +static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN = 4451; // 8 +static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB = 4452; // 8 +static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB_LEN = 4453; // 8 +static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0 = 4454; // 8 +static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN = 4455; // 8 +static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1 = 4456; // 8 +static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN = 4457; // 8 +static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2 = 4458; // 8 +static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN = 4459; // 8 +static const uint64_t SH_FLD_CFG_INT_MASK = 4460; // 1 +static const uint64_t SH_FLD_CFG_L3_DIS = 4461; // 12 +static const uint64_t SH_FLD_CFG_LCL_HW_MARK = 4462; // 3 +static const uint64_t SH_FLD_CFG_LCL_HW_MARK_LEN = 4463; // 3 +static const uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD = 4464; // 1 +static const uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN = 4465; // 1 +static const uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD = 4466; // 1 +static const uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD_LEN = 4467; // 1 +static const uint64_t SH_FLD_CFG_LFSR_MASK_A0 = 4468; // 2 +static const uint64_t SH_FLD_CFG_LFSR_MASK_A0_LEN = 4469; // 2 +static const uint64_t SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN = 4470; // 12 +static const uint64_t SH_FLD_CFG_LINK_A0_EN = 4471; // 6 +static const uint64_t SH_FLD_CFG_LINK_A0_GROUPID = 4472; // 6 +static const uint64_t SH_FLD_CFG_LINK_A0_GROUPID_LEN = 4473; // 6 +static const uint64_t SH_FLD_CFG_LINK_A1_EN = 4474; // 6 +static const uint64_t SH_FLD_CFG_LINK_A1_GROUPID = 4475; // 6 +static const uint64_t SH_FLD_CFG_LINK_A1_GROUPID_LEN = 4476; // 6 +static const uint64_t SH_FLD_CFG_LINK_A2_EN = 4477; // 6 +static const uint64_t SH_FLD_CFG_LINK_A2_GROUPID = 4478; // 6 +static const uint64_t SH_FLD_CFG_LINK_A2_GROUPID_LEN = 4479; // 6 +static const uint64_t SH_FLD_CFG_LINK_A3_EN = 4480; // 6 +static const uint64_t SH_FLD_CFG_LINK_A3_GROUPID = 4481; // 6 +static const uint64_t SH_FLD_CFG_LINK_A3_GROUPID_LEN = 4482; // 6 +static const uint64_t SH_FLD_CFG_LINK_NA0_ADDR_DIS = 4483; // 6 +static const uint64_t SH_FLD_CFG_LINK_NA1_ADDR_DIS = 4484; // 6 +static const uint64_t SH_FLD_CFG_LINK_NA2_ADDR_DIS = 4485; // 6 +static const uint64_t SH_FLD_CFG_LINK_NA3_ADDR_DIS = 4486; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX0_ADDR_DIS = 4487; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX1_ADDR_DIS = 4488; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX2_ADDR_DIS = 4489; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX3_ADDR_DIS = 4490; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX4_ADDR_DIS = 4491; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX5_ADDR_DIS = 4492; // 6 +static const uint64_t SH_FLD_CFG_LINK_NX6_ADDR_DIS = 4493; // 6 +static const uint64_t SH_FLD_CFG_LINK_X0_CHIPID = 4494; // 6 +static const uint64_t SH_FLD_CFG_LINK_X0_CHIPID_LEN = 4495; // 6 +static const uint64_t SH_FLD_CFG_LINK_X0_EN = 4496; // 6 +static const uint64_t SH_FLD_CFG_LINK_X1_CHIPID = 4497; // 6 +static const uint64_t SH_FLD_CFG_LINK_X1_CHIPID_LEN = 4498; // 6 +static const uint64_t SH_FLD_CFG_LINK_X1_EN = 4499; // 6 +static const uint64_t SH_FLD_CFG_LINK_X2_CHIPID = 4500; // 6 +static const uint64_t SH_FLD_CFG_LINK_X2_CHIPID_LEN = 4501; // 6 +static const uint64_t SH_FLD_CFG_LINK_X2_EN = 4502; // 6 +static const uint64_t SH_FLD_CFG_LINK_X3_CHIPID = 4503; // 6 +static const uint64_t SH_FLD_CFG_LINK_X3_CHIPID_LEN = 4504; // 6 +static const uint64_t SH_FLD_CFG_LINK_X3_EN = 4505; // 6 +static const uint64_t SH_FLD_CFG_LINK_X4_CHIPID = 4506; // 6 +static const uint64_t SH_FLD_CFG_LINK_X4_CHIPID_LEN = 4507; // 6 +static const uint64_t SH_FLD_CFG_LINK_X4_EN = 4508; // 6 +static const uint64_t SH_FLD_CFG_LINK_X5_CHIPID = 4509; // 6 +static const uint64_t SH_FLD_CFG_LINK_X5_CHIPID_LEN = 4510; // 6 +static const uint64_t SH_FLD_CFG_LINK_X5_EN = 4511; // 6 +static const uint64_t SH_FLD_CFG_LINK_X6_CHIPID = 4512; // 6 +static const uint64_t SH_FLD_CFG_LINK_X6_CHIPID_LEN = 4513; // 6 +static const uint64_t SH_FLD_CFG_LINK_X6_EN = 4514; // 6 +static const uint64_t SH_FLD_CFG_LOGIC_SIGNALED_ERROR = 4515; // 30 +static const uint64_t SH_FLD_CFG_LOG_COUNTS_IN_TRACE = 4516; // 2 +static const uint64_t SH_FLD_CFG_LP_SUB_CNT = 4517; // 8 +static const uint64_t SH_FLD_CFG_LP_SUB_CNT_LEN = 4518; // 8 +static const uint64_t SH_FLD_CFG_LRU_DIRECT_MAP = 4519; // 12 +static const uint64_t SH_FLD_CFG_LTE_MC = 4520; // 2 +static const uint64_t SH_FLD_CFG_LTE_MC_LEN = 4521; // 2 +static const uint64_t SH_FLD_CFG_LVL0 = 4522; // 2 +static const uint64_t SH_FLD_CFG_LVL0_LEN = 4523; // 2 +static const uint64_t SH_FLD_CFG_LVL1 = 4524; // 2 +static const uint64_t SH_FLD_CFG_LVL1_LEN = 4525; // 2 +static const uint64_t SH_FLD_CFG_LVL2 = 4526; // 2 +static const uint64_t SH_FLD_CFG_LVL2_LEN = 4527; // 2 +static const uint64_t SH_FLD_CFG_LVL3 = 4528; // 2 +static const uint64_t SH_FLD_CFG_LVL3_LEN = 4529; // 2 +static const uint64_t SH_FLD_CFG_LVL4 = 4530; // 2 +static const uint64_t SH_FLD_CFG_LVL4_LEN = 4531; // 2 +static const uint64_t SH_FLD_CFG_LVL5 = 4532; // 2 +static const uint64_t SH_FLD_CFG_LVL5_LEN = 4533; // 2 +static const uint64_t SH_FLD_CFG_LVL6 = 4534; // 2 +static const uint64_t SH_FLD_CFG_LVL6_LEN = 4535; // 2 +static const uint64_t SH_FLD_CFG_LVL7 = 4536; // 2 +static const uint64_t SH_FLD_CFG_LVL7_LEN = 4537; // 2 +static const uint64_t SH_FLD_CFG_MAINT_ADDR_MODE_EN = 4538; // 2 +static const uint64_t SH_FLD_CFG_MAINT_BROADCAST_MODE_EN = 4539; // 2 +static const uint64_t SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 4540; // 2 +static const uint64_t SH_FLD_CFG_MAINT_RCE_WITH_CE = 4541; // 2 +static const uint64_t SH_FLD_CFG_MASK = 4542; // 2 +static const uint64_t SH_FLD_CFG_MASTER_CHIP = 4543; // 6 +static const uint64_t SH_FLD_CFG_MAX = 4544; // 1 +static const uint64_t SH_FLD_CFG_MAX_LEN = 4545; // 1 +static const uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW = 4546; // 8 +static const uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN = 4547; // 8 +static const uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW = 4548; // 8 +static const uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN = 4549; // 8 +static const uint64_t SH_FLD_CFG_MC0_MCS0_MASK = 4550; // 1 +static const uint64_t SH_FLD_CFG_MC0_MCS1_MASK = 4551; // 1 +static const uint64_t SH_FLD_CFG_MC1_MCS0_MASK = 4552; // 1 +static const uint64_t SH_FLD_CFG_MC1_MCS1_MASK = 4553; // 1 +static const uint64_t SH_FLD_CFG_MC2_MCS0_MASK = 4554; // 1 +static const uint64_t SH_FLD_CFG_MC2_MCS1_MASK = 4555; // 1 +static const uint64_t SH_FLD_CFG_MC3_MCS0_MASK = 4556; // 1 +static const uint64_t SH_FLD_CFG_MC3_MCS1_MASK = 4557; // 1 +static const uint64_t SH_FLD_CFG_MCB_LEN64 = 4558; // 2 +static const uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 4559; // 2 +static const uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 4560; // 2 +static const uint64_t SH_FLD_CFG_MCD_MASK = 4561; // 1 +static const uint64_t SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 4562; // 2 +static const uint64_t SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 4563; // 2 +static const uint64_t SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 4564; // 2 +static const uint64_t SH_FLD_CFG_MIN_CMD_GAP = 4565; // 2 +static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER = 4566; // 2 +static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 4567; // 2 +static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_LEN = 4568; // 2 +static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 4569; // 8 +static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 4570; // 8 +static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME = 4571; // 8 +static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 4572; // 8 +static const uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE = 4573; // 2 +static const uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 4574; // 2 +static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS = 4575; // 8 +static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE = 4576; // 8 +static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_LEN = 4577; // 8 +static const uint64_t SH_FLD_CFG_MISR_BLOCK = 4578; // 8 +static const uint64_t SH_FLD_CFG_MISR_BLOCK_LEN = 4579; // 8 +static const uint64_t SH_FLD_CFG_MISR_FEEDBACK_ENABLE = 4580; // 8 +static const uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH = 4581; // 8 +static const uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH_LEN = 4582; // 8 +static const uint64_t SH_FLD_CFG_MPR_READEYE_TB = 4583; // 8 +static const uint64_t SH_FLD_CFG_MPR_READEYE_TB_LEN = 4584; // 8 +static const uint64_t SH_FLD_CFG_MSGSND = 4585; // 1 +static const uint64_t SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 4586; // 2 +static const uint64_t SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 4587; // 2 +static const uint64_t SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 4588; // 2 +static const uint64_t SH_FLD_CFG_NM_CAS_WEIGHT = 4589; // 8 +static const uint64_t SH_FLD_CFG_NM_CAS_WEIGHT_LEN = 4590; // 8 +static const uint64_t SH_FLD_CFG_NM_CHANGE_AFTER_SYNC = 4591; // 8 +static const uint64_t SH_FLD_CFG_NM_M = 4592; // 8 +static const uint64_t SH_FLD_CFG_NM_M_LEN = 4593; // 8 +static const uint64_t SH_FLD_CFG_NM_N_PER_PORT = 4594; // 8 +static const uint64_t SH_FLD_CFG_NM_N_PER_PORT_LEN = 4595; // 8 +static const uint64_t SH_FLD_CFG_NM_N_PER_SLOT = 4596; // 8 +static const uint64_t SH_FLD_CFG_NM_N_PER_SLOT_LEN = 4597; // 8 +static const uint64_t SH_FLD_CFG_NM_RAS_WEIGHT = 4598; // 8 +static const uint64_t SH_FLD_CFG_NM_RAS_WEIGHT_LEN = 4599; // 8 +static const uint64_t SH_FLD_CFG_NOISE_WAIT_TIME = 4600; // 8 +static const uint64_t SH_FLD_CFG_NOISE_WAIT_TIME_LEN = 4601; // 8 +static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TB_SEL = 4602; // 8 +static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL = 4603; // 8 +static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4604; // 8 +static const uint64_t SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN = 4605; // 8 +static const uint64_t SH_FLD_CFG_OE_ALWAYS_ON = 4606; // 8 +static const uint64_t SH_FLD_CFG_OPT0 = 4607; // 6 +static const uint64_t SH_FLD_CFG_OPT0_LEN = 4608; // 6 +static const uint64_t SH_FLD_CFG_OPT1 = 4609; // 6 +static const uint64_t SH_FLD_CFG_OPT1_LEN = 4610; // 6 +static const uint64_t SH_FLD_CFG_OPT2 = 4611; // 6 +static const uint64_t SH_FLD_CFG_OPT2_LEN = 4612; // 6 +static const uint64_t SH_FLD_CFG_OPT3 = 4613; // 6 +static const uint64_t SH_FLD_CFG_OPT3_LEN = 4614; // 6 +static const uint64_t SH_FLD_CFG_OPT_RD_SIZE = 4615; // 8 +static const uint64_t SH_FLD_CFG_OPT_RD_SIZE_LEN = 4616; // 8 +static const uint64_t SH_FLD_CFG_PARITY_AFTER_CMD = 4617; // 10 +static const uint64_t SH_FLD_CFG_PARITY_DETECT_TIME = 4618; // 8 +static const uint64_t SH_FLD_CFG_PARITY_DETECT_TIME_LEN = 4619; // 8 +static const uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL = 4620; // 1 +static const uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN = 4621; // 1 +static const uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL = 4622; // 1 +static const uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN = 4623; // 1 +static const uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL = 4624; // 1 +static const uint64_t SH_FLD_CFG_PAUSE_MCB_ERROR = 4625; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_MCB_LOG_FULL = 4626; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_AUE = 4627; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE = 4628; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN = 4629; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_MPE = 4630; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_RCD = 4631; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_SCE = 4632; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_SUE = 4633; // 2 +static const uint64_t SH_FLD_CFG_PAUSE_ON_UE = 4634; // 2 +static const uint64_t SH_FLD_CFG_PBIEN_DBG_0_SEL = 4635; // 1 +static const uint64_t SH_FLD_CFG_PBIEN_DBG_0_SEL_LEN = 4636; // 1 +static const uint64_t SH_FLD_CFG_PBIEN_DBG_1_SEL = 4637; // 1 +static const uint64_t SH_FLD_CFG_PBIEN_DBG_1_SEL_LEN = 4638; // 1 +static const uint64_t SH_FLD_CFG_PBIES_DBG_0_SEL = 4639; // 1 +static const uint64_t SH_FLD_CFG_PBIES_DBG_0_SEL_LEN = 4640; // 1 +static const uint64_t SH_FLD_CFG_PBIES_DBG_1_SEL = 4641; // 1 +static const uint64_t SH_FLD_CFG_PBIES_DBG_1_SEL_LEN = 4642; // 1 +static const uint64_t SH_FLD_CFG_PBIOT_DBG_0_SEL = 4643; // 1 +static const uint64_t SH_FLD_CFG_PBIOT_DBG_0_SEL_LEN = 4644; // 1 +static const uint64_t SH_FLD_CFG_PBIOT_DBG_1_SEL = 4645; // 1 +static const uint64_t SH_FLD_CFG_PBIOT_DBG_1_SEL_LEN = 4646; // 1 +static const uint64_t SH_FLD_CFG_PBIOT_SEL = 4647; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_DONE = 4648; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_DONE_LEN = 4649; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP = 4650; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN = 4651; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET = 4652; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN = 4653; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_RR = 4654; // 1 +static const uint64_t SH_FLD_CFG_PCMD_PRIO_RR_LEN = 4655; // 1 +static const uint64_t SH_FLD_CFG_PDN_PUP = 4656; // 8 +static const uint64_t SH_FLD_CFG_PDN_PUP_LEN = 4657; // 8 +static const uint64_t SH_FLD_CFG_PE0_MASK = 4658; // 2 +static const uint64_t SH_FLD_CFG_PE1_MASK = 4659; // 2 +static const uint64_t SH_FLD_CFG_PE2_MASK = 4660; // 2 +static const uint64_t SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL = 4661; // 12 +static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_MATCH = 4662; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_MATCH_LEN = 4663; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_SEL = 4664; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_SEL_LEN = 4665; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_EN = 4666; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_GRP1_SEL = 4667; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_GRP2_SEL = 4668; // 1 +static const uint64_t SH_FLD_CFG_PERFTRACE_TRIG = 4669; // 1 +static const uint64_t SH_FLD_CFG_PER_BANK_REFRESH = 4670; // 8 +static const uint64_t SH_FLD_CFG_PE_MATCH0 = 4671; // 1 +static const uint64_t SH_FLD_CFG_PE_MATCH0_LEN = 4672; // 1 +static const uint64_t SH_FLD_CFG_PE_MATCH1 = 4673; // 1 +static const uint64_t SH_FLD_CFG_PE_MATCH1_LEN = 4674; // 1 +static const uint64_t SH_FLD_CFG_PHYP_IS_GROUP = 4675; // 6 +static const uint64_t SH_FLD_CFG_PMUCNT_EN = 4676; // 1 +static const uint64_t SH_FLD_CFG_PMUCNT_SEL = 4677; // 1 +static const uint64_t SH_FLD_CFG_PMUCNT_SEL_LEN = 4678; // 1 +static const uint64_t SH_FLD_CFG_PMU_FREEZE_MODE = 4679; // 1 +static const uint64_t SH_FLD_CFG_PMU_PORT = 4680; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL0 = 4681; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL0_LEN = 4682; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL1 = 4683; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL1_LEN = 4684; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL2 = 4685; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL2_LEN = 4686; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL3 = 4687; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL3_LEN = 4688; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL4 = 4689; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL4_LEN = 4690; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL5 = 4691; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL5_LEN = 4692; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL6 = 4693; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL6_LEN = 4694; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL7 = 4695; // 1 +static const uint64_t SH_FLD_CFG_PMU_SEL7_LEN = 4696; // 1 +static const uint64_t SH_FLD_CFG_PM_DISABLE = 4697; // 43 +static const uint64_t SH_FLD_CFG_PM_MUX_DISABLE = 4698; // 43 +static const uint64_t SH_FLD_CFG_PORT_FAIL_DISABLE = 4699; // 8 +static const uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME = 4700; // 8 +static const uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN = 4701; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C0 = 4702; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C0_LEN = 4703; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C1 = 4704; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C1_LEN = 4705; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C2 = 4706; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C2_LEN = 4707; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C3 = 4708; // 8 +static const uint64_t SH_FLD_CFG_PRESCALER_C3_LEN = 4709; // 8 +static const uint64_t SH_FLD_CFG_PRIO_LSI = 4710; // 1 +static const uint64_t SH_FLD_CFG_PRIO_LSI_LEN = 4711; // 1 +static const uint64_t SH_FLD_CFG_PRIO_MMIO = 4712; // 1 +static const uint64_t SH_FLD_CFG_PRIO_MMIO_LEN = 4713; // 1 +static const uint64_t SH_FLD_CFG_PRIO_PULL = 4714; // 2 +static const uint64_t SH_FLD_CFG_PRIO_PULL_LEN = 4715; // 2 +static const uint64_t SH_FLD_CFG_PRIO_PUSH = 4716; // 1 +static const uint64_t SH_FLD_CFG_PRIO_PUSH_ARX = 4717; // 1 +static const uint64_t SH_FLD_CFG_PRIO_PUSH_ARX_LEN = 4718; // 1 +static const uint64_t SH_FLD_CFG_PRIO_PUSH_LCL = 4719; // 1 +static const uint64_t SH_FLD_CFG_PRIO_PUSH_LCL_LEN = 4720; // 1 +static const uint64_t SH_FLD_CFG_PRIO_PUSH_LEN = 4721; // 1 +static const uint64_t SH_FLD_CFG_PRIO_QUERY = 4722; // 1 +static const uint64_t SH_FLD_CFG_PRIO_QUERY_LEN = 4723; // 1 +static const uint64_t SH_FLD_CFG_PRIO_RR = 4724; // 3 +static const uint64_t SH_FLD_CFG_PRIO_RR_LEN = 4725; // 3 +static const uint64_t SH_FLD_CFG_PRIO_RSVD = 4726; // 1 +static const uint64_t SH_FLD_CFG_PRIO_RSVD_LEN = 4727; // 1 +static const uint64_t SH_FLD_CFG_PRIO_VRQ_REQ = 4728; // 1 +static const uint64_t SH_FLD_CFG_PRIO_VRQ_REQ_LEN = 4729; // 1 +static const uint64_t SH_FLD_CFG_PRIO_VRQ_RSP = 4730; // 1 +static const uint64_t SH_FLD_CFG_PRIO_VRQ_RSP_LEN = 4731; // 1 +static const uint64_t SH_FLD_CFG_PULL_LMIT = 4732; // 1 +static const uint64_t SH_FLD_CFG_PULL_LMIT_LEN = 4733; // 1 +static const uint64_t SH_FLD_CFG_PULL_PRIO_HYP = 4734; // 1 +static const uint64_t SH_FLD_CFG_PULL_PRIO_HYP_LEN = 4735; // 1 +static const uint64_t SH_FLD_CFG_PULL_RSVD = 4736; // 1 +static const uint64_t SH_FLD_CFG_PULL_RSVD_LEN = 4737; // 1 +static const uint64_t SH_FLD_CFG_PULSE_WIDTH = 4738; // 1 +static const uint64_t SH_FLD_CFG_PULSE_WIDTH_LEN = 4739; // 1 +static const uint64_t SH_FLD_CFG_PUMP = 4740; // 8 +static const uint64_t SH_FLD_CFG_PUMP_MODE = 4741; // 1 +static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 4742; // 8 +static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 4743; // 8 +static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 4744; // 8 +static const uint64_t SH_FLD_CFG_PUP_ALL_WRITES_PENDING = 4745; // 8 +static const uint64_t SH_FLD_CFG_PUP_AVAIL = 4746; // 8 +static const uint64_t SH_FLD_CFG_PUP_AVAIL_LEN = 4747; // 8 +static const uint64_t SH_FLD_CFG_PUP_PDN = 4748; // 8 +static const uint64_t SH_FLD_CFG_PUP_PDN_LEN = 4749; // 8 +static const uint64_t SH_FLD_CFG_PUSH_ARX_LMIT = 4750; // 1 +static const uint64_t SH_FLD_CFG_PUSH_ARX_LMIT_LEN = 4751; // 1 +static const uint64_t SH_FLD_CFG_PUSH_ARX_RSVD = 4752; // 1 +static const uint64_t SH_FLD_CFG_PUSH_ARX_RSVD_LEN = 4753; // 1 +static const uint64_t SH_FLD_CFG_PUSH_LCL_LMIT = 4754; // 1 +static const uint64_t SH_FLD_CFG_PUSH_LCL_LMIT_LEN = 4755; // 1 +static const uint64_t SH_FLD_CFG_PUSH_LCL_RSVD = 4756; // 1 +static const uint64_t SH_FLD_CFG_PUSH_LCL_RSVD_LEN = 4757; // 1 +static const uint64_t SH_FLD_CFG_PUSH_PRIO_HYP = 4758; // 1 +static const uint64_t SH_FLD_CFG_PUSH_PRIO_HYP_LEN = 4759; // 1 +static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL = 4760; // 1 +static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL_LEN = 4761; // 1 +static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL = 4762; // 1 +static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 4763; // 1 +static const uint64_t SH_FLD_CFG_Q_BIT_TID_MASK = 4764; // 12 +static const uint64_t SH_FLD_CFG_Q_BIT_TID_MASK_LEN = 4765; // 12 +static const uint64_t SH_FLD_CFG_RANDCMD_WGT = 4766; // 2 +static const uint64_t SH_FLD_CFG_RANDCMD_WGT_LEN = 4767; // 2 +static const uint64_t SH_FLD_CFG_RANDGAP_WGT = 4768; // 2 +static const uint64_t SH_FLD_CFG_RANDGAP_WGT_LEN = 4769; // 2 +static const uint64_t SH_FLD_CFG_RANDOM_EN = 4770; // 12 +static const uint64_t SH_FLD_CFG_RANK0_RD_ODT = 4771; // 8 +static const uint64_t SH_FLD_CFG_RANK0_RD_ODT_LEN = 4772; // 8 +static const uint64_t SH_FLD_CFG_RANK0_WR_ODT = 4773; // 8 +static const uint64_t SH_FLD_CFG_RANK0_WR_ODT_LEN = 4774; // 8 +static const uint64_t SH_FLD_CFG_RANK1_RD_ODT = 4775; // 8 +static const uint64_t SH_FLD_CFG_RANK1_RD_ODT_LEN = 4776; // 8 +static const uint64_t SH_FLD_CFG_RANK1_WR_ODT = 4777; // 8 +static const uint64_t SH_FLD_CFG_RANK1_WR_ODT_LEN = 4778; // 8 +static const uint64_t SH_FLD_CFG_RANK2_RD_ODT = 4779; // 8 +static const uint64_t SH_FLD_CFG_RANK2_RD_ODT_LEN = 4780; // 8 +static const uint64_t SH_FLD_CFG_RANK2_WR_ODT = 4781; // 8 +static const uint64_t SH_FLD_CFG_RANK2_WR_ODT_LEN = 4782; // 8 +static const uint64_t SH_FLD_CFG_RANK3_RD_ODT = 4783; // 8 +static const uint64_t SH_FLD_CFG_RANK3_RD_ODT_LEN = 4784; // 8 +static const uint64_t SH_FLD_CFG_RANK3_WR_ODT = 4785; // 8 +static const uint64_t SH_FLD_CFG_RANK3_WR_ODT_LEN = 4786; // 8 +static const uint64_t SH_FLD_CFG_RANK4_RD_ODT = 4787; // 8 +static const uint64_t SH_FLD_CFG_RANK4_RD_ODT_LEN = 4788; // 8 +static const uint64_t SH_FLD_CFG_RANK4_WR_ODT = 4789; // 8 +static const uint64_t SH_FLD_CFG_RANK4_WR_ODT_LEN = 4790; // 8 +static const uint64_t SH_FLD_CFG_RANK5_RD_ODT = 4791; // 8 +static const uint64_t SH_FLD_CFG_RANK5_RD_ODT_LEN = 4792; // 8 +static const uint64_t SH_FLD_CFG_RANK5_WR_ODT = 4793; // 8 +static const uint64_t SH_FLD_CFG_RANK5_WR_ODT_LEN = 4794; // 8 +static const uint64_t SH_FLD_CFG_RANK6_RD_ODT = 4795; // 8 +static const uint64_t SH_FLD_CFG_RANK6_RD_ODT_LEN = 4796; // 8 +static const uint64_t SH_FLD_CFG_RANK6_WR_ODT = 4797; // 8 +static const uint64_t SH_FLD_CFG_RANK6_WR_ODT_LEN = 4798; // 8 +static const uint64_t SH_FLD_CFG_RANK7_RD_ODT = 4799; // 8 +static const uint64_t SH_FLD_CFG_RANK7_RD_ODT_LEN = 4800; // 8 +static const uint64_t SH_FLD_CFG_RANK7_WR_ODT = 4801; // 8 +static const uint64_t SH_FLD_CFG_RANK7_WR_ODT_LEN = 4802; // 8 +static const uint64_t SH_FLD_CFG_RANK_SM_STALL_DISABLE = 4803; // 8 +static const uint64_t SH_FLD_CFG_RCD_PARITY_DLY = 4804; // 8 +static const uint64_t SH_FLD_CFG_RCD_PARITY_DLY_LEN = 4805; // 8 +static const uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME = 4806; // 8 +static const uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME_LEN = 4807; // 8 +static const uint64_t SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN = 4808; // 12 +static const uint64_t SH_FLD_CFG_RD2PRE = 4809; // 8 +static const uint64_t SH_FLD_CFG_RD2PRE_LEN = 4810; // 8 +static const uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT = 4811; // 8 +static const uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 4812; // 8 +static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH = 4813; // 8 +static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN = 4814; // 8 +static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB = 4815; // 8 +static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN = 4816; // 8 +static const uint64_t SH_FLD_CFG_RDTAG_DLY = 4817; // 8 +static const uint64_t SH_FLD_CFG_RDTAG_DLY_LEN = 4818; // 8 +static const uint64_t SH_FLD_CFG_RDTAG_MBX_CYCLE = 4819; // 8 +static const uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR = 4820; // 8 +static const uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN = 4821; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_DEBUG_SELECT = 4822; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_ENABLE = 4823; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 4824; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL = 4825; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_LEN = 4826; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 4827; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 4828; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD = 4829; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 4830; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL = 4831; // 8 +static const uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN = 4832; // 8 +static const uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL = 4833; // 8 +static const uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN = 4834; // 8 +static const uint64_t SH_FLD_CFG_REFR_TSV_STACK = 4835; // 8 +static const uint64_t SH_FLD_CFG_REFR_TSV_STACK_LEN = 4836; // 8 +static const uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY = 4837; // 8 +static const uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN = 4838; // 8 +static const uint64_t SH_FLD_CFG_REG_PARITY_ERRHOLD = 4839; // 2 +static const uint64_t SH_FLD_CFG_REQ_GATHER_ENABLE = 4840; // 3 +static const uint64_t SH_FLD_CFG_RESET_CNTS_START_OF_RANK = 4841; // 2 +static const uint64_t SH_FLD_CFG_RESET_ERROR_CAPTURE = 4842; // 1 +static const uint64_t SH_FLD_CFG_RESET_MODE = 4843; // 2 +static const uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT = 4844; // 8 +static const uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 4845; // 8 +static const uint64_t SH_FLD_CFG_RNS_LVL0 = 4846; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL0_LEN = 4847; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL1 = 4848; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL1_LEN = 4849; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL2 = 4850; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL2_LEN = 4851; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL3 = 4852; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL3_LEN = 4853; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL4 = 4854; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL4_LEN = 4855; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL5 = 4856; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL5_LEN = 4857; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL6 = 4858; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL6_LEN = 4859; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL7 = 4860; // 2 +static const uint64_t SH_FLD_CFG_RNS_LVL7_LEN = 4861; // 2 +static const uint64_t SH_FLD_CFG_RODT_BC4_END_DLY = 4862; // 8 +static const uint64_t SH_FLD_CFG_RODT_BC4_END_DLY_LEN = 4863; // 8 +static const uint64_t SH_FLD_CFG_RODT_END_DLY = 4864; // 8 +static const uint64_t SH_FLD_CFG_RODT_END_DLY_LEN = 4865; // 8 +static const uint64_t SH_FLD_CFG_RODT_START_DLY = 4866; // 8 +static const uint64_t SH_FLD_CFG_RODT_START_DLY_LEN = 4867; // 8 +static const uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD = 4868; // 8 +static const uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN = 4869; // 8 +static const uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING = 4870; // 8 +static const uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4871; // 8 +static const uint64_t SH_FLD_CFG_RRQ_DEPTH = 4872; // 8 +static const uint64_t SH_FLD_CFG_RRQ_DEPTH_LEN = 4873; // 8 +static const uint64_t SH_FLD_CFG_RRQ_ENTRY0_ENABLE = 4874; // 8 +static const uint64_t SH_FLD_CFG_RRQ_FIFO_MODE = 4875; // 8 +static const uint64_t SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE = 4876; // 8 +static const uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT = 4877; // 8 +static const uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN = 4878; // 8 +static const uint64_t SH_FLD_CFG_RSV0 = 4879; // 8 +static const uint64_t SH_FLD_CFG_RSV0_LEN = 4880; // 8 +static const uint64_t SH_FLD_CFG_RUNTIME_CTR = 4881; // 2 +static const uint64_t SH_FLD_CFG_RUNTIME_CTR_LEN = 4882; // 2 +static const uint64_t SH_FLD_CFG_RUNTIME_MCBALL = 4883; // 2 +static const uint64_t SH_FLD_CFG_RUNTIME_OVERHEAD = 4884; // 2 +static const uint64_t SH_FLD_CFG_RUNTIME_SUBTEST = 4885; // 2 +static const uint64_t SH_FLD_CFG_RUNTIME_SUBTEST_LEN = 4886; // 2 +static const uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL = 4887; // 8 +static const uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN = 4888; // 8 +static const uint64_t SH_FLD_CFG_SCOPE = 4889; // 2 +static const uint64_t SH_FLD_CFG_SCOPE_LEN = 4890; // 2 +static const uint64_t SH_FLD_CFG_SELCR0 = 4891; // 1 +static const uint64_t SH_FLD_CFG_SELCR0_LEN = 4892; // 1 +static const uint64_t SH_FLD_CFG_SELCR1 = 4893; // 1 +static const uint64_t SH_FLD_CFG_SELCR1_LEN = 4894; // 1 +static const uint64_t SH_FLD_CFG_SELCR2 = 4895; // 1 +static const uint64_t SH_FLD_CFG_SELCR2_LEN = 4896; // 1 +static const uint64_t SH_FLD_CFG_SELCR3 = 4897; // 1 +static const uint64_t SH_FLD_CFG_SELCR3_LEN = 4898; // 1 +static const uint64_t SH_FLD_CFG_SELECT = 4899; // 3 +static const uint64_t SH_FLD_CFG_SELECT_LEN = 4900; // 3 +static const uint64_t SH_FLD_CFG_SELRT = 4901; // 1 +static const uint64_t SH_FLD_CFG_SELRT_LEN = 4902; // 1 +static const uint64_t SH_FLD_CFG_SELSN0 = 4903; // 1 +static const uint64_t SH_FLD_CFG_SELSN0_LEN = 4904; // 1 +static const uint64_t SH_FLD_CFG_SELSN1 = 4905; // 1 +static const uint64_t SH_FLD_CFG_SELSN1_LEN = 4906; // 1 +static const uint64_t SH_FLD_CFG_SELSN2 = 4907; // 1 +static const uint64_t SH_FLD_CFG_SELSN2_LEN = 4908; // 1 +static const uint64_t SH_FLD_CFG_SELSN3 = 4909; // 1 +static const uint64_t SH_FLD_CFG_SELSN3_LEN = 4910; // 1 +static const uint64_t SH_FLD_CFG_SHIFT_COUNT = 4911; // 3 +static const uint64_t SH_FLD_CFG_SHIFT_COUNT_LEN = 4912; // 3 +static const uint64_t SH_FLD_CFG_SHIFT_DATA = 4913; // 3 +static const uint64_t SH_FLD_CFG_SHIFT_DATA_LEN = 4914; // 3 +static const uint64_t SH_FLD_CFG_SIM_FAST_NOISE_WINDOW = 4915; // 8 +static const uint64_t SH_FLD_CFG_SINGLE_MEM = 4916; // 12 +static const uint64_t SH_FLD_CFG_SINGLE_MEM_EN = 4917; // 12 +static const uint64_t SH_FLD_CFG_SINGLE_MEM_LEN = 4918; // 12 +static const uint64_t SH_FLD_CFG_SKIP_GRP_SCOPE_EN = 4919; // 12 +static const uint64_t SH_FLD_CFG_SLOT0_S0_CID = 4920; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S0_CID_LEN = 4921; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S1_CID = 4922; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S1_CID_LEN = 4923; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S2_CID = 4924; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S2_CID_LEN = 4925; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S3_CID = 4926; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S3_CID_LEN = 4927; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S4_CID = 4928; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S4_CID_LEN = 4929; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S5_CID = 4930; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S5_CID_LEN = 4931; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S6_CID = 4932; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S6_CID_LEN = 4933; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S7_CID = 4934; // 8 +static const uint64_t SH_FLD_CFG_SLOT0_S7_CID_LEN = 4935; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S0_CID = 4936; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S0_CID_LEN = 4937; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S1_CID = 4938; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S1_CID_LEN = 4939; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S2_CID = 4940; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S2_CID_LEN = 4941; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S3_CID = 4942; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S3_CID_LEN = 4943; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S4_CID = 4944; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S4_CID_LEN = 4945; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S5_CID = 4946; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S5_CID_LEN = 4947; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S6_CID = 4948; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S6_CID_LEN = 4949; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S7_CID = 4950; // 8 +static const uint64_t SH_FLD_CFG_SLOT1_S7_CID_LEN = 4951; // 8 +static const uint64_t SH_FLD_CFG_SLOW = 4952; // 3 +static const uint64_t SH_FLD_CFG_SMP_OPTICS = 4953; // 6 +static const uint64_t SH_FLD_CFG_SMT_MODE = 4954; // 1 +static const uint64_t SH_FLD_CFG_SMT_MODE_LEN = 4955; // 1 +static const uint64_t SH_FLD_CFG_SP_HW_MARK = 4956; // 3 +static const uint64_t SH_FLD_CFG_SP_HW_MARK_LEN = 4957; // 3 +static const uint64_t SH_FLD_CFG_STALL_PULL = 4958; // 1 +static const uint64_t SH_FLD_CFG_STALL_PUSH_ARX = 4959; // 1 +static const uint64_t SH_FLD_CFG_STALL_PUSH_LCL = 4960; // 1 +static const uint64_t SH_FLD_CFG_START_ADDR_0 = 4961; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_0_LEN = 4962; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_1 = 4963; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_1_LEN = 4964; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_2 = 4965; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_2_LEN = 4966; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_3 = 4967; // 2 +static const uint64_t SH_FLD_CFG_START_ADDR_3_LEN = 4968; // 2 +static const uint64_t SH_FLD_CFG_STATIC_IDLE_DLY = 4969; // 8 +static const uint64_t SH_FLD_CFG_STATIC_IDLE_DLY_LEN = 4970; // 8 +static const uint64_t SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP = 4971; // 43 +static const uint64_t SH_FLD_CFG_STQ_PF_EN = 4972; // 12 +static const uint64_t SH_FLD_CFG_STR_ENABLE = 4973; // 8 +static const uint64_t SH_FLD_CFG_STR_STATE = 4974; // 8 +static const uint64_t SH_FLD_CFG_SWITCH_CD_PULSE = 4975; // 3 +static const uint64_t SH_FLD_CFG_SWITCH_OPTION_AB = 4976; // 3 +static const uint64_t SH_FLD_CFG_SW_AB_WAIT = 4977; // 3 +static const uint64_t SH_FLD_CFG_SW_AB_WAIT_LEN = 4978; // 3 +static const uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE = 4979; // 2 +static const uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN = 4980; // 2 +static const uint64_t SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL = 4981; // 12 +static const uint64_t SH_FLD_CFG_TARGET_EN = 4982; // 1 +static const uint64_t SH_FLD_CFG_TCKESR = 4983; // 8 +static const uint64_t SH_FLD_CFG_TCKESR_LEN = 4984; // 8 +static const uint64_t SH_FLD_CFG_TCKSRE = 4985; // 8 +static const uint64_t SH_FLD_CFG_TCKSRE_LEN = 4986; // 8 +static const uint64_t SH_FLD_CFG_TCKSRX = 4987; // 8 +static const uint64_t SH_FLD_CFG_TCKSRX_LEN = 4988; // 8 +static const uint64_t SH_FLD_CFG_TFAW = 4989; // 8 +static const uint64_t SH_FLD_CFG_TFAW_LEN = 4990; // 8 +static const uint64_t SH_FLD_CFG_THRD_C0_EN = 4991; // 1 +static const uint64_t SH_FLD_CFG_THRD_C0_EN_LEN = 4992; // 1 +static const uint64_t SH_FLD_CFG_THRD_C10_EN = 4993; // 1 +static const uint64_t SH_FLD_CFG_THRD_C10_EN_LEN = 4994; // 1 +static const uint64_t SH_FLD_CFG_THRD_C11_EN = 4995; // 1 +static const uint64_t SH_FLD_CFG_THRD_C11_EN_LEN = 4996; // 1 +static const uint64_t SH_FLD_CFG_THRD_C1_EN = 4997; // 1 +static const uint64_t SH_FLD_CFG_THRD_C1_EN_LEN = 4998; // 1 +static const uint64_t SH_FLD_CFG_THRD_C2_EN = 4999; // 1 +static const uint64_t SH_FLD_CFG_THRD_C2_EN_LEN = 5000; // 1 +static const uint64_t SH_FLD_CFG_THRD_C3_EN = 5001; // 1 +static const uint64_t SH_FLD_CFG_THRD_C3_EN_LEN = 5002; // 1 +static const uint64_t SH_FLD_CFG_THRD_C4_EN = 5003; // 1 +static const uint64_t SH_FLD_CFG_THRD_C4_EN_LEN = 5004; // 1 +static const uint64_t SH_FLD_CFG_THRD_C5_EN = 5005; // 1 +static const uint64_t SH_FLD_CFG_THRD_C5_EN_LEN = 5006; // 1 +static const uint64_t SH_FLD_CFG_THRD_C6_EN = 5007; // 1 +static const uint64_t SH_FLD_CFG_THRD_C6_EN_LEN = 5008; // 1 +static const uint64_t SH_FLD_CFG_THRD_C7_EN = 5009; // 1 +static const uint64_t SH_FLD_CFG_THRD_C7_EN_LEN = 5010; // 1 +static const uint64_t SH_FLD_CFG_THRD_C8_EN = 5011; // 1 +static const uint64_t SH_FLD_CFG_THRD_C8_EN_LEN = 5012; // 1 +static const uint64_t SH_FLD_CFG_THRD_C9_EN = 5013; // 1 +static const uint64_t SH_FLD_CFG_THRD_C9_EN_LEN = 5014; // 1 +static const uint64_t SH_FLD_CFG_THRESH_MAG_ICE = 5015; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_ICE_LEN = 5016; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD = 5017; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN = 5018; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT = 5019; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN = 5020; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT = 5021; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN = 5022; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD = 5023; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN = 5024; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT = 5025; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN = 5026; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT = 5027; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN = 5028; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_RCE = 5029; // 2 +static const uint64_t SH_FLD_CFG_THRESH_MAG_RCE_LEN = 5030; // 2 +static const uint64_t SH_FLD_CFG_TIME_BASE_TMR0 = 5031; // 8 +static const uint64_t SH_FLD_CFG_TIME_BASE_TMR0_LEN = 5032; // 8 +static const uint64_t SH_FLD_CFG_TIME_BASE_TMR1 = 5033; // 8 +static const uint64_t SH_FLD_CFG_TIME_BASE_TMR1_LEN = 5034; // 8 +static const uint64_t SH_FLD_CFG_TIME_BASE_TMR2 = 5035; // 8 +static const uint64_t SH_FLD_CFG_TIME_BASE_TMR2_LEN = 5036; // 8 +static const uint64_t SH_FLD_CFG_TM_MASTER = 5037; // 6 +static const uint64_t SH_FLD_CFG_TRAS = 5038; // 8 +static const uint64_t SH_FLD_CFG_TRAS_LEN = 5039; // 8 +static const uint64_t SH_FLD_CFG_TRCD = 5040; // 8 +static const uint64_t SH_FLD_CFG_TRCD_LEN = 5041; // 8 +static const uint64_t SH_FLD_CFG_TRFC = 5042; // 8 +static const uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS = 5043; // 8 +static const uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS_LEN = 5044; // 8 +static const uint64_t SH_FLD_CFG_TRFC_LEN = 5045; // 8 +static const uint64_t SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF = 5046; // 8 +static const uint64_t SH_FLD_CFG_TRP = 5047; // 8 +static const uint64_t SH_FLD_CFG_TRP_LEN = 5048; // 8 +static const uint64_t SH_FLD_CFG_TSIZE = 5049; // 2 +static const uint64_t SH_FLD_CFG_TSIZE_LEN = 5050; // 2 +static const uint64_t SH_FLD_CFG_TSIZE_MASK = 5051; // 2 +static const uint64_t SH_FLD_CFG_TSIZE_MASK_LEN = 5052; // 2 +static const uint64_t SH_FLD_CFG_TTAG = 5053; // 2 +static const uint64_t SH_FLD_CFG_TTAG_LEN = 5054; // 2 +static const uint64_t SH_FLD_CFG_TTAG_MASK = 5055; // 2 +static const uint64_t SH_FLD_CFG_TTAG_MASK_LEN = 5056; // 2 +static const uint64_t SH_FLD_CFG_TTYPE = 5057; // 2 +static const uint64_t SH_FLD_CFG_TTYPE_LEN = 5058; // 2 +static const uint64_t SH_FLD_CFG_TTYPE_MASK = 5059; // 2 +static const uint64_t SH_FLD_CFG_TTYPE_MASK_LEN = 5060; // 2 +static const uint64_t SH_FLD_CFG_TXSDLL = 5061; // 8 +static const uint64_t SH_FLD_CFG_TXSDLL_LEN = 5062; // 8 +static const uint64_t SH_FLD_CFG_VAS_MASK = 5063; // 1 +static const uint64_t SH_FLD_CFG_VG_LVL0 = 5064; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL0_LEN = 5065; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL1 = 5066; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL1_LEN = 5067; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL2 = 5068; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL2_LEN = 5069; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL3 = 5070; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL3_LEN = 5071; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL4 = 5072; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL4_LEN = 5073; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL5 = 5074; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL5_LEN = 5075; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL6 = 5076; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL6_LEN = 5077; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL7 = 5078; // 2 +static const uint64_t SH_FLD_CFG_VG_LVL7_LEN = 5079; // 2 +static const uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 5080; // 2 +static const uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 5081; // 2 +static const uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 5082; // 2 +static const uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 5083; // 2 +static const uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE = 5084; // 2 +static const uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 5085; // 2 +static const uint64_t SH_FLD_CFG_WAT_CAL_SYNC = 5086; // 8 +static const uint64_t SH_FLD_CFG_WAT_CAL_SYNC_LEN = 5087; // 8 +static const uint64_t SH_FLD_CFG_WAT_CNTL = 5088; // 8 +static const uint64_t SH_FLD_CFG_WAT_CNTL_LEN = 5089; // 8 +static const uint64_t SH_FLD_CFG_WAT_CNT_VALUE = 5090; // 2 +static const uint64_t SH_FLD_CFG_WAT_CNT_VALUE_LEN = 5091; // 2 +static const uint64_t SH_FLD_CFG_WAT_DIS_RD_PG = 5092; // 8 +static const uint64_t SH_FLD_CFG_WAT_DIS_RD_PG_LEN = 5093; // 8 +static const uint64_t SH_FLD_CFG_WAT_DIS_WR_PG = 5094; // 8 +static const uint64_t SH_FLD_CFG_WAT_DIS_WR_PG_LEN = 5095; // 8 +static const uint64_t SH_FLD_CFG_WAT_EMER_TH = 5096; // 8 +static const uint64_t SH_FLD_CFG_WAT_EMER_TH_LEN = 5097; // 8 +static const uint64_t SH_FLD_CFG_WAT_ENABLE = 5098; // 2 +static const uint64_t SH_FLD_CFG_WAT_EVENT_SEL = 5099; // 8 +static const uint64_t SH_FLD_CFG_WAT_EVENT_SEL_LEN = 5100; // 8 +static const uint64_t SH_FLD_CFG_WAT_EXIT_STR = 5101; // 8 +static const uint64_t SH_FLD_CFG_WAT_EXIT_STR_LEN = 5102; // 8 +static const uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL = 5103; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL_LEN = 5104; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT = 5105; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT_LEN = 5106; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL = 5107; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL_LEN = 5108; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL = 5109; // 2 +static const uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL_LEN = 5110; // 2 +static const uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT = 5111; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT_LEN = 5112; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_REF_GT = 5113; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_REF_GT_LEN = 5114; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT = 5115; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT_LEN = 5116; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT = 5117; // 8 +static const uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT_LEN = 5118; // 8 +static const uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP = 5119; // 8 +static const uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 5120; // 8 +static const uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP = 5121; // 8 +static const uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 5122; // 8 +static const uint64_t SH_FLD_CFG_WAT_FP_DIS = 5123; // 8 +static const uint64_t SH_FLD_CFG_WAT_FP_DIS_LEN = 5124; // 8 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL = 5125; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL_LEN = 5126; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL = 5127; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL_LEN = 5128; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL = 5129; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL_LEN = 5130; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL = 5131; // 2 +static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL_LEN = 5132; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL = 5133; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL_LEN = 5134; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL = 5135; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL_LEN = 5136; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL = 5137; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL_LEN = 5138; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL = 5139; // 2 +static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL_LEN = 5140; // 2 +static const uint64_t SH_FLD_CFG_WAT_MSKA = 5141; // 8 +static const uint64_t SH_FLD_CFG_WAT_MSKA_LEN = 5142; // 8 +static const uint64_t SH_FLD_CFG_WAT_MSKB = 5143; // 8 +static const uint64_t SH_FLD_CFG_WAT_MSKB_LEN = 5144; // 8 +static const uint64_t SH_FLD_CFG_WAT_OUTPUT_PULSE = 5145; // 2 +static const uint64_t SH_FLD_CFG_WAT_PATA = 5146; // 8 +static const uint64_t SH_FLD_CFG_WAT_PATA_LEN = 5147; // 8 +static const uint64_t SH_FLD_CFG_WAT_PATB = 5148; // 8 +static const uint64_t SH_FLD_CFG_WAT_PATB_LEN = 5149; // 8 +static const uint64_t SH_FLD_CFG_WAT_PUP_ALL = 5150; // 8 +static const uint64_t SH_FLD_CFG_WAT_PUP_ALL_LEN = 5151; // 8 +static const uint64_t SH_FLD_CFG_WAT_REF_HP = 5152; // 8 +static const uint64_t SH_FLD_CFG_WAT_REF_HP_LEN = 5153; // 8 +static const uint64_t SH_FLD_CFG_WAT_REF_SAFE = 5154; // 8 +static const uint64_t SH_FLD_CFG_WAT_REF_SAFE_LEN = 5155; // 8 +static const uint64_t SH_FLD_CFG_WAT_REF_SYNC = 5156; // 8 +static const uint64_t SH_FLD_CFG_WAT_REF_SYNC_LEN = 5157; // 8 +static const uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT = 5158; // 8 +static const uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT_LEN = 5159; // 8 +static const uint64_t SH_FLD_CFG_WAT_SET_FIR = 5160; // 8 +static const uint64_t SH_FLD_CFG_WAT_SET_FIR_LEN = 5161; // 8 +static const uint64_t SH_FLD_CFG_WAT_START_RECOVERY = 5162; // 8 +static const uint64_t SH_FLD_CFG_WAT_START_RECOVERY_LEN = 5163; // 8 +static const uint64_t SH_FLD_CFG_WAT_TMR_VALUE = 5164; // 2 +static const uint64_t SH_FLD_CFG_WAT_TMR_VALUE_LEN = 5165; // 2 +static const uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT = 5166; // 8 +static const uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT_LEN = 5167; // 8 +static const uint64_t SH_FLD_CFG_WDF_SERIAL_SEQ_MODE = 5168; // 8 +static const uint64_t SH_FLD_CFG_WODT_BC4_END_DLY = 5169; // 8 +static const uint64_t SH_FLD_CFG_WODT_BC4_END_DLY_LEN = 5170; // 8 +static const uint64_t SH_FLD_CFG_WODT_END_DLY = 5171; // 8 +static const uint64_t SH_FLD_CFG_WODT_END_DLY_LEN = 5172; // 8 +static const uint64_t SH_FLD_CFG_WODT_START_DLY = 5173; // 8 +static const uint64_t SH_FLD_CFG_WODT_START_DLY_LEN = 5174; // 8 +static const uint64_t SH_FLD_CFG_WR2PRE = 5175; // 8 +static const uint64_t SH_FLD_CFG_WR2PRE_LEN = 5176; // 8 +static const uint64_t SH_FLD_CFG_WRDATA_DLY = 5177; // 8 +static const uint64_t SH_FLD_CFG_WRDATA_DLY_LEN = 5178; // 8 +static const uint64_t SH_FLD_CFG_WRDONE_DLY = 5179; // 8 +static const uint64_t SH_FLD_CFG_WRDONE_DLY_LEN = 5180; // 8 +static const uint64_t SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE = 5181; // 6 +static const uint64_t SH_FLD_CFG_WRITE_HW_MARK = 5182; // 8 +static const uint64_t SH_FLD_CFG_WRITE_HW_MARK_LEN = 5183; // 8 +static const uint64_t SH_FLD_CFG_WRITE_LW_MARK = 5184; // 8 +static const uint64_t SH_FLD_CFG_WRITE_LW_MARK_LEN = 5185; // 8 +static const uint64_t SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS = 5186; // 16 +static const uint64_t SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS = 5187; // 16 +static const uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING = 5188; // 8 +static const uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 5189; // 8 +static const uint64_t SH_FLD_CFG_WRQ_DEPTH = 5190; // 8 +static const uint64_t SH_FLD_CFG_WRQ_DEPTH_LEN = 5191; // 8 +static const uint64_t SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR = 5192; // 8 +static const uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY = 5193; // 8 +static const uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN = 5194; // 8 +static const uint64_t SH_FLD_CFG_WRQ_FIFO_MODE = 5195; // 8 +static const uint64_t SH_FLD_CFG_WRQ_FLUSH_WR_RANK = 5196; // 8 +static const uint64_t SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE = 5197; // 8 +static const uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT = 5198; // 8 +static const uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN = 5199; // 8 +static const uint64_t SH_FLD_CFG_XLATE_ADDR_TO_ID = 5200; // 6 +static const uint64_t SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN = 5201; // 6 +static const uint64_t SH_FLD_CFG_X_AGGREGATE = 5202; // 6 +static const uint64_t SH_FLD_CFG_X_CMD_RATE = 5203; // 6 +static const uint64_t SH_FLD_CFG_X_CMD_RATE_LEN = 5204; // 6 +static const uint64_t SH_FLD_CFG_X_FP_DISABLED = 5205; // 6 +static const uint64_t SH_FLD_CFG_X_GATHER_ENABLE = 5206; // 6 +static const uint64_t SH_FLD_CFG_X_INDIRECT_EN = 5207; // 6 +static const uint64_t SH_FLD_CGC = 5208; // 24 +static const uint64_t SH_FLD_CGC_LEN = 5209; // 24 +static const uint64_t SH_FLD_CH0EFT_ACTION = 5210; // 1 +static const uint64_t SH_FLD_CH0EFT_ENA = 5211; // 1 +static const uint64_t SH_FLD_CH0EFT_SELECT = 5212; // 1 +static const uint64_t SH_FLD_CH0EFT_SELECT_LEN = 5213; // 1 +static const uint64_t SH_FLD_CH0EFT_TYPE = 5214; // 1 +static const uint64_t SH_FLD_CH0_842_ECC_CE = 5215; // 1 +static const uint64_t SH_FLD_CH0_842_ECC_UE = 5216; // 1 +static const uint64_t SH_FLD_CH0_CMD_CREDITS_0_5 = 5217; // 1 +static const uint64_t SH_FLD_CH0_CMD_CREDITS_0_5_LEN = 5218; // 1 +static const uint64_t SH_FLD_CH0_EFT = 5219; // 1 +static const uint64_t SH_FLD_CH0_INVALID_STATE = 5220; // 1 +static const uint64_t SH_FLD_CH0_MAX = 5221; // 2 +static const uint64_t SH_FLD_CH0_MAX_LEN = 5222; // 2 +static const uint64_t SH_FLD_CH0_REF_DIV = 5223; // 1 +static const uint64_t SH_FLD_CH0_REF_DIV_LEN = 5224; // 1 +static const uint64_t SH_FLD_CH0_TIMER_ENBL = 5225; // 1 +static const uint64_t SH_FLD_CH1EFT_ACTION = 5226; // 1 +static const uint64_t SH_FLD_CH1EFT_ENA = 5227; // 1 +static const uint64_t SH_FLD_CH1EFT_SELECT = 5228; // 1 +static const uint64_t SH_FLD_CH1EFT_SELECT_LEN = 5229; // 1 +static const uint64_t SH_FLD_CH1EFT_TYPE = 5230; // 1 +static const uint64_t SH_FLD_CH1_842_ECC_CE = 5231; // 1 +static const uint64_t SH_FLD_CH1_842_ECC_UE = 5232; // 1 +static const uint64_t SH_FLD_CH1_CMD_CREDITS_0_5 = 5233; // 1 +static const uint64_t SH_FLD_CH1_CMD_CREDITS_0_5_LEN = 5234; // 1 +static const uint64_t SH_FLD_CH1_DAT_CREDITS_0_5 = 5235; // 1 +static const uint64_t SH_FLD_CH1_DAT_CREDITS_0_5_LEN = 5236; // 1 +static const uint64_t SH_FLD_CH1_EFT = 5237; // 1 +static const uint64_t SH_FLD_CH1_INVALID_STATE = 5238; // 1 +static const uint64_t SH_FLD_CH1_MAX = 5239; // 2 +static const uint64_t SH_FLD_CH1_MAX_LEN = 5240; // 2 +static const uint64_t SH_FLD_CH1_REF_DIV = 5241; // 1 +static const uint64_t SH_FLD_CH1_REF_DIV_LEN = 5242; // 1 +static const uint64_t SH_FLD_CH1_TIMER_ENBL = 5243; // 1 +static const uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5 = 5244; // 1 +static const uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN = 5245; // 1 +static const uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5 = 5246; // 1 +static const uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN = 5247; // 1 +static const uint64_t SH_FLD_CH2_INVALID_STATE = 5248; // 1 +static const uint64_t SH_FLD_CH2_MAX = 5249; // 2 +static const uint64_t SH_FLD_CH2_MAX_LEN = 5250; // 2 +static const uint64_t SH_FLD_CH2_REF_DIV = 5251; // 1 +static const uint64_t SH_FLD_CH2_REF_DIV_LEN = 5252; // 1 +static const uint64_t SH_FLD_CH2_SYM = 5253; // 1 +static const uint64_t SH_FLD_CH2_TIMER_ENBL = 5254; // 1 +static const uint64_t SH_FLD_CH3_INVALID_STATE = 5255; // 1 +static const uint64_t SH_FLD_CH3_MAX = 5256; // 2 +static const uint64_t SH_FLD_CH3_MAX_LEN = 5257; // 2 +static const uint64_t SH_FLD_CH3_REF_DIV = 5258; // 1 +static const uint64_t SH_FLD_CH3_REF_DIV_LEN = 5259; // 1 +static const uint64_t SH_FLD_CH3_SYM = 5260; // 1 +static const uint64_t SH_FLD_CH3_TIMER_ENBL = 5261; // 1 +static const uint64_t SH_FLD_CH4GZIP_ACTION = 5262; // 1 +static const uint64_t SH_FLD_CH4GZIP_ENA = 5263; // 1 +static const uint64_t SH_FLD_CH4GZIP_SELECT = 5264; // 1 +static const uint64_t SH_FLD_CH4GZIP_SELECT_LEN = 5265; // 1 +static const uint64_t SH_FLD_CH4GZIP_TYPE = 5266; // 1 +static const uint64_t SH_FLD_CH4_AMF_ECC_CE = 5267; // 1 +static const uint64_t SH_FLD_CH4_AMF_ECC_UE = 5268; // 1 +static const uint64_t SH_FLD_CH4_GZIP = 5269; // 1 +static const uint64_t SH_FLD_CH4_INVALID_STATE = 5270; // 1 +static const uint64_t SH_FLD_CH4_REF_DIV = 5271; // 1 +static const uint64_t SH_FLD_CH4_REF_DIV_LEN = 5272; // 1 +static const uint64_t SH_FLD_CH4_TIMER_ENBL = 5273; // 1 +static const uint64_t SH_FLD_CH5_AMF_ECC_CE = 5274; // 1 +static const uint64_t SH_FLD_CH5_AMF_ECC_UE = 5275; // 1 +static const uint64_t SH_FLD_CH5_INVALID_STATE = 5276; // 1 +static const uint64_t SH_FLD_CH6_AMF_ECC_CE = 5277; // 1 +static const uint64_t SH_FLD_CH6_AMF_ECC_UE = 5278; // 1 +static const uint64_t SH_FLD_CH6_INVALID_STATE = 5279; // 1 +static const uint64_t SH_FLD_CH7_AMF_ECC_CE = 5280; // 1 +static const uint64_t SH_FLD_CH7_AMF_ECC_UE = 5281; // 1 +static const uint64_t SH_FLD_CH7_INVALID_STATE = 5282; // 1 +static const uint64_t SH_FLD_CHANGE_IN_PROGRESS = 5283; // 2 +static const uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 5284; // 4 +static const uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 5285; // 4 +static const uint64_t SH_FLD_CHANNEL_0_TIMEOUT_ERROR = 5286; // 4 +static const uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 5287; // 4 +static const uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 5288; // 4 +static const uint64_t SH_FLD_CHANNEL_1_TIMEOUT_ERROR = 5289; // 4 +static const uint64_t SH_FLD_CHANNEL_SELECT = 5290; // 4 +static const uint64_t SH_FLD_CHANNEL_SELECT_LEN = 5291; // 4 +static const uint64_t SH_FLD_CHAN_FAIL_MASK = 5292; // 4 +static const uint64_t SH_FLD_CHAN_FAIL_MASK_LEN = 5293; // 4 +static const uint64_t SH_FLD_CHECKSTOP = 5294; // 1 +static const uint64_t SH_FLD_CHECK_CMDS = 5295; // 2 +static const uint64_t SH_FLD_CHECK_CMDS_EN = 5296; // 2 +static const uint64_t SH_FLD_CHECK_CMDS_LEN = 5297; // 2 +static const uint64_t SH_FLD_CHECK_STOP_GPE0 = 5298; // 1 +static const uint64_t SH_FLD_CHECK_STOP_GPE1 = 5299; // 1 +static const uint64_t SH_FLD_CHECK_STOP_GPE2 = 5300; // 1 +static const uint64_t SH_FLD_CHECK_STOP_GPE3 = 5301; // 1 +static const uint64_t SH_FLD_CHECK_STOP_PPC405 = 5302; // 1 +static const uint64_t SH_FLD_CHGRATE = 5303; // 12 +static const uint64_t SH_FLD_CHICKEN_SWITCH = 5304; // 1 +static const uint64_t SH_FLD_CHIPLET_ATOMIC_LOCK = 5305; // 43 +static const uint64_t SH_FLD_CHIPLET_ENABLE = 5306; // 73 +static const uint64_t SH_FLD_CHIPLET_ERRORS = 5307; // 43 +static const uint64_t SH_FLD_CHIPLET_ERRORS_LEN = 5308; // 43 +static const uint64_t SH_FLD_CHIPLET_ID = 5309; // 24 +static const uint64_t SH_FLD_CHIPLET_INTERRUPT_FROM_HOST = 5310; // 1 +static const uint64_t SH_FLD_CHIPLET_IS_ALIGNED = 5311; // 43 +static const uint64_t SH_FLD_CHIPLET_OFFLINE = 5312; // 43 +static const uint64_t SH_FLD_CHIPMARK = 5313; // 72 +static const uint64_t SH_FLD_CHIPMARK_LEN = 5314; // 72 +static const uint64_t SH_FLD_CHIPPOS = 5315; // 1 +static const uint64_t SH_FLD_CHIP_ID = 5316; // 24 +static const uint64_t SH_FLD_CHIP_ID_LEN = 5317; // 24 +static const uint64_t SH_FLD_CHIP_INTERFACEMODE = 5318; // 2 +static const uint64_t SH_FLD_CHIP_PERSONALISATION = 5319; // 2 +static const uint64_t SH_FLD_CHIP_RESET = 5320; // 1 +static const uint64_t SH_FLD_CHIP_STATUS = 5321; // 194 +static const uint64_t SH_FLD_CHIP_STATUS_LEN = 5322; // 194 +static const uint64_t SH_FLD_CHIP_TOD_INTERRUPT = 5323; // 98 +static const uint64_t SH_FLD_CHIP_TOD_PARITY_ERROR = 5324; // 96 +static const uint64_t SH_FLD_CHIP_TOD_STATUS = 5325; // 98 +static const uint64_t SH_FLD_CHIP_TOD_STATUS_LEN = 5326; // 98 +static const uint64_t SH_FLD_CHKSW_ALLOW1_RD = 5327; // 1 +static const uint64_t SH_FLD_CHKSW_ALLOW1_RDWR = 5328; // 1 +static const uint64_t SH_FLD_CHKSW_ALLOW1_WR = 5329; // 1 +static const uint64_t SH_FLD_CHKSW_AR012 = 5330; // 3 +static const uint64_t SH_FLD_CHKSW_AR012_0 = 5331; // 1 +static const uint64_t SH_FLD_CHKSW_AR012_1 = 5332; // 1 +static const uint64_t SH_FLD_CHKSW_AR012_2 = 5333; // 1 +static const uint64_t SH_FLD_CHKSW_AR012_3 = 5334; // 1 +static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_0 = 5335; // 1 +static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_1 = 5336; // 1 +static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_2 = 5337; // 1 +static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_3 = 5338; // 1 +static const uint64_t SH_FLD_CHKSW_I2C_BUSY_0 = 5339; // 2 +static const uint64_t SH_FLD_CHKSW_I2C_BUSY_1 = 5340; // 1 +static const uint64_t SH_FLD_CHKSW_I2C_BUSY_2 = 5341; // 1 +static const uint64_t SH_FLD_CHKSW_I2C_BUSY_3 = 5342; // 1 +static const uint64_t SH_FLD_CHKSW_OCI_PARCHK_DIS = 5343; // 1 +static const uint64_t SH_FLD_CHKSW_SO_SPARE = 5344; // 1 +static const uint64_t SH_FLD_CHKSW_SO_SPARE_LEN = 5345; // 1 +static const uint64_t SH_FLD_CHKSW_SPARE_6 = 5346; // 1 +static const uint64_t SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS = 5347; // 1 +static const uint64_t SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS = 5348; // 1 +static const uint64_t SH_FLD_CHKSW_WRFSM_DLY_DIS = 5349; // 1 +static const uint64_t SH_FLD_CHOP1G = 5350; // 1 +static const uint64_t SH_FLD_CHSW_DIS_DATA_HANG = 5351; // 1 +static const uint64_t SH_FLD_CHSW_DIS_ECC_CHECK = 5352; // 1 +static const uint64_t SH_FLD_CHSW_DIS_GROUP_SCOPE = 5353; // 1 +static const uint64_t SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK = 5354; // 1 +static const uint64_t SH_FLD_CHSW_DIS_OCIBEPAR_CHECK = 5355; // 1 +static const uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK = 5356; // 1 +static const uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_GEN = 5357; // 1 +static const uint64_t SH_FLD_CHSW_DIS_OPER_HANG = 5358; // 1 +static const uint64_t SH_FLD_CHSW_DIS_PB_PARITY_CHK = 5359; // 1 +static const uint64_t SH_FLD_CHSW_DIS_RETRY_BACKOFF = 5360; // 1 +static const uint64_t SH_FLD_CHSW_DIS_RTAG_PARITY_CHK = 5361; // 1 +static const uint64_t SH_FLD_CHSW_DIS_WRITE_MATCH_REARB = 5362; // 1 +static const uint64_t SH_FLD_CHSW_EXIT_ON_INVALID_CRESP = 5363; // 1 +static const uint64_t SH_FLD_CHSW_HANG_ON_ADRERROR = 5364; // 1 +static const uint64_t SH_FLD_CHSW_HANG_ON_DERROR = 5365; // 1 +static const uint64_t SH_FLD_CHSW_SKIP_GROUP_SCOPE = 5366; // 1 +static const uint64_t SH_FLD_CHSW_USE_CL_DMA_INJ = 5367; // 1 +static const uint64_t SH_FLD_CHSW_USE_PR_DMA_INJ = 5368; // 1 +static const uint64_t SH_FLD_CHTM_PURGE_C0 = 5369; // 12 +static const uint64_t SH_FLD_CHTM_PURGE_C1 = 5370; // 12 +static const uint64_t SH_FLD_CHTM_PURGE_DONE_C0 = 5371; // 24 +static const uint64_t SH_FLD_CHTM_PURGE_DONE_C1 = 5372; // 24 +static const uint64_t SH_FLD_CIEA = 5373; // 96 +static const uint64_t SH_FLD_CIEA_LEN = 5374; // 96 +static const uint64_t SH_FLD_CI_BUFF_AVAIL = 5375; // 2 +static const uint64_t SH_FLD_CI_BUFF_MIN = 5376; // 2 +static const uint64_t SH_FLD_CI_BUFF_MIN_LEN = 5377; // 2 +static const uint64_t SH_FLD_CI_LOAD = 5378; // 2 +static const uint64_t SH_FLD_CI_LOAD_LEN = 5379; // 2 +static const uint64_t SH_FLD_CI_MACHINE_HANG = 5380; // 12 +static const uint64_t SH_FLD_CI_READ = 5381; // 1 +static const uint64_t SH_FLD_CI_SM_CTL_ERR_DET = 5382; // 1 +static const uint64_t SH_FLD_CI_STORE = 5383; // 1 +static const uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD = 5384; // 2 +static const uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN = 5385; // 2 +static const uint64_t SH_FLD_CI_STORE_LEN = 5386; // 1 +static const uint64_t SH_FLD_CI_STORE_RMT = 5387; // 1 +static const uint64_t SH_FLD_CI_STORE_RMT_LEN = 5388; // 1 +static const uint64_t SH_FLD_CI_STORE_RMT_VC = 5389; // 1 +static const uint64_t SH_FLD_CI_STORE_RMT_VC_LEN = 5390; // 1 +static const uint64_t SH_FLD_CI_TIMEOUT_ERR_DET = 5391; // 1 +static const uint64_t SH_FLD_CI_WRITE = 5392; // 1 +static const uint64_t SH_FLD_CKINSM_DIS = 5393; // 1 +static const uint64_t SH_FLD_CKINSM_DIS_LEN = 5394; // 1 +static const uint64_t SH_FLD_CKIN_PROT_ERR_CHK_DIS = 5395; // 1 +static const uint64_t SH_FLD_CKIN_TIMEOUT_CHK_DIS = 5396; // 1 +static const uint64_t SH_FLD_CL = 5397; // 1 +static const uint64_t SH_FLD_CLEAR = 5398; // 1 +static const uint64_t SH_FLD_CLEAR_BAD_LANE_COUNTER = 5399; // 2 +static const uint64_t SH_FLD_CLEAR_CHIPLET_IS_ALIGNED = 5400; // 43 +static const uint64_t SH_FLD_CLEAR_DMA_IRQ_SUSPEND_MODE = 5401; // 3 +static const uint64_t SH_FLD_CLEAR_LINK_FAIL_COUNTER = 5402; // 2 +static const uint64_t SH_FLD_CLEAR_STICKY_LEVEL = 5403; // 24 +static const uint64_t SH_FLD_CLEAR_TB_ERRORS = 5404; // 98 +static const uint64_t SH_FLD_CLKCMD_REQUEST_ERR = 5405; // 43 +static const uint64_t SH_FLD_CLKDIST_PDWN = 5406; // 12 +static const uint64_t SH_FLD_CLKDIST_PDWN_LEN = 5407; // 4 +static const uint64_t SH_FLD_CLKGLM_ASYNC_RESET = 5408; // 30 +static const uint64_t SH_FLD_CLKGLM_SEL = 5409; // 30 +static const uint64_t SH_FLD_CLK_ASYNC_RESET = 5410; // 43 +static const uint64_t SH_FLD_CLK_BIST_ACTIVITY_DET = 5411; // 4 +static const uint64_t SH_FLD_CLK_BIST_ERR = 5412; // 4 +static const uint64_t SH_FLD_CLK_DCC_BYPASS_EN = 5413; // 43 +static const uint64_t SH_FLD_CLK_DIV_BYPASS_EN = 5414; // 43 +static const uint64_t SH_FLD_CLK_DLY = 5415; // 1 +static const uint64_t SH_FLD_CLK_DLY_LEN = 5416; // 1 +static const uint64_t SH_FLD_CLK_HALF_WIDTH_MODE = 5417; // 4 +static const uint64_t SH_FLD_CLK_INVERT = 5418; // 6 +static const uint64_t SH_FLD_CLK_PDLY_BYPASS_EN = 5419; // 43 +static const uint64_t SH_FLD_CLK_PULSE_EN = 5420; // 43 +static const uint64_t SH_FLD_CLK_PULSE_MODE = 5421; // 43 +static const uint64_t SH_FLD_CLK_PULSE_MODE_LEN = 5422; // 43 +static const uint64_t SH_FLD_CLK_QUIESCE = 5423; // 4 +static const uint64_t SH_FLD_CLK_QUIESCE_LEN = 5424; // 4 +static const uint64_t SH_FLD_CLK_QUIESCE_N = 5425; // 1 +static const uint64_t SH_FLD_CLK_QUIESCE_N_LEN = 5426; // 1 +static const uint64_t SH_FLD_CLK_QUIESCE_P = 5427; // 1 +static const uint64_t SH_FLD_CLK_QUIESCE_P_LEN = 5428; // 1 +static const uint64_t SH_FLD_CLK_RATE = 5429; // 4 +static const uint64_t SH_FLD_CLK_RATE_LEN = 5430; // 4 +static const uint64_t SH_FLD_CLK_RATE_SEL = 5431; // 1 +static const uint64_t SH_FLD_CLK_RATE_SEL_LEN = 5432; // 1 +static const uint64_t SH_FLD_CLK_RUN_COUNT = 5433; // 4 +static const uint64_t SH_FLD_CLK_SB_PULSE_MODE = 5434; // 24 +static const uint64_t SH_FLD_CLK_SB_PULSE_MODE_EN = 5435; // 24 +static const uint64_t SH_FLD_CLK_SB_PULSE_MODE_LEN = 5436; // 24 +static const uint64_t SH_FLD_CLK_SB_SPARE = 5437; // 24 +static const uint64_t SH_FLD_CLK_SB_STRENGTH = 5438; // 24 +static const uint64_t SH_FLD_CLK_SB_STRENGTH_LEN = 5439; // 24 +static const uint64_t SH_FLD_CLK_SW_RESCLK = 5440; // 24 +static const uint64_t SH_FLD_CLK_SW_RESCLK_LEN = 5441; // 24 +static const uint64_t SH_FLD_CLK_SW_SPARE = 5442; // 24 +static const uint64_t SH_FLD_CLK_SYNC = 5443; // 24 +static const uint64_t SH_FLD_CLK_SYNC_DONE = 5444; // 24 +static const uint64_t SH_FLD_CLK_SYNC_ENABLE = 5445; // 24 +static const uint64_t SH_FLD_CLK_UNLOAD_CLK_DISABLE = 5446; // 4 +static const uint64_t SH_FLD_CLK_UNLOAD_SEL = 5447; // 4 +static const uint64_t SH_FLD_CLK_UNLOAD_SEL_LEN = 5448; // 4 +static const uint64_t SH_FLD_CLOCK_CMD = 5449; // 43 +static const uint64_t SH_FLD_CLOCK_CMD_CONFLICT_ERR = 5450; // 43 +static const uint64_t SH_FLD_CLOCK_CMD_LEN = 5451; // 43 +static const uint64_t SH_FLD_CLOCK_CMD_PREVENTED_ERR = 5452; // 43 +static const uint64_t SH_FLD_CLOCK_DIVIDER = 5453; // 1 +static const uint64_t SH_FLD_CLOCK_DIVIDER_LEN = 5454; // 1 +static const uint64_t SH_FLD_CLOCK_DIV_4 = 5455; // 3 +static const uint64_t SH_FLD_CLOCK_PERV = 5456; // 43 +static const uint64_t SH_FLD_CLOCK_PULSE_USE_EVEN = 5457; // 43 +static const uint64_t SH_FLD_CLOCK_RATE_SELECTION = 5458; // 3 +static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_0 = 5459; // 1 +static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_0_LEN = 5460; // 1 +static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_1 = 5461; // 2 +static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_1_LEN = 5462; // 2 +static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_LEN = 5463; // 3 +static const uint64_t SH_FLD_CLOCK_UNIT1 = 5464; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT10 = 5465; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT2 = 5466; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT3 = 5467; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT4 = 5468; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT5 = 5469; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT6 = 5470; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT7 = 5471; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT8 = 5472; // 43 +static const uint64_t SH_FLD_CLOCK_UNIT9 = 5473; // 43 +static const uint64_t SH_FLD_CLONE_CS_MODE = 5474; // 8 +static const uint64_t SH_FLD_CLR_PAR_ERRS = 5475; // 16 +static const uint64_t SH_FLD_CLR_PORT_ENABLE = 5476; // 3 +static const uint64_t SH_FLD_CLR_PORT_ENABLE_LEN = 5477; // 3 +static const uint64_t SH_FLD_CLSTATE_DEBUG_SEL = 5478; // 8 +static const uint64_t SH_FLD_CLSTATE_DEBUG_SEL_LEN = 5479; // 8 +static const uint64_t SH_FLD_CL_DATA = 5480; // 43 +static const uint64_t SH_FLD_CL_ECC_CE = 5481; // 1 +static const uint64_t SH_FLD_CL_ECC_UE = 5482; // 1 +static const uint64_t SH_FLD_CL_FINE_DISABLE = 5483; // 4 +static const uint64_t SH_FLD_CL_FINE_DISABLE_LEN = 5484; // 4 +static const uint64_t SH_FLD_CL_FSM = 5485; // 43 +static const uint64_t SH_FLD_CL_GLOBAL_DISABLE = 5486; // 4 +static const uint64_t SH_FLD_CL_GLOBAL_DISABLE_LEN = 5487; // 4 +static const uint64_t SH_FLD_CL_LEN = 5488; // 1 +static const uint64_t SH_FLD_CL_PROBE_PB_HANG = 5489; // 2 +static const uint64_t SH_FLD_CL_TIMEOUT_SEL = 5490; // 4 +static const uint64_t SH_FLD_CL_TIMEOUT_SEL_LEN = 5491; // 4 +static const uint64_t SH_FLD_CL_WRAP_DEBUG_SEL = 5492; // 8 +static const uint64_t SH_FLD_CL_WRAP_DEBUG_SEL_LEN = 5493; // 8 +static const uint64_t SH_FLD_CMD = 5494; // 130 +static const uint64_t SH_FLD_CMDQ_CE_ERR = 5495; // 2 +static const uint64_t SH_FLD_CMDQ_UE_ERR = 5496; // 2 +static const uint64_t SH_FLD_CMDREG_BROADCAST_FLAG = 5497; // 1 +static const uint64_t SH_FLD_CMDREG_SCAN_ADDRESS = 5498; // 1 +static const uint64_t SH_FLD_CMDREG_SCAN_ADDRESS_LEN = 5499; // 1 +static const uint64_t SH_FLD_CMDREG_SCAN_REGION = 5500; // 1 +static const uint64_t SH_FLD_CMDREG_SCAN_REGION_LEN = 5501; // 1 +static const uint64_t SH_FLD_CMDREG_SCAN_TYPE = 5502; // 1 +static const uint64_t SH_FLD_CMDREG_SCAN_TYPE_LEN = 5503; // 1 +static const uint64_t SH_FLD_CMDREG_WRITE_FLAG = 5504; // 1 +static const uint64_t SH_FLD_CMD_BUFFER_PAR_ERR = 5505; // 4 +static const uint64_t SH_FLD_CMD_COUNT_ERR = 5506; // 1 +static const uint64_t SH_FLD_CMD_EXP_TIME = 5507; // 7 +static const uint64_t SH_FLD_CMD_EXP_TIME_LEN = 5508; // 7 +static const uint64_t SH_FLD_CMD_IN_PROG = 5509; // 1 +static const uint64_t SH_FLD_CMD_LEN = 5510; // 130 +static const uint64_t SH_FLD_CMD_PARITY_ERROR = 5511; // 19 +static const uint64_t SH_FLD_CMD_PRECEDE_TIME = 5512; // 8 +static const uint64_t SH_FLD_CMD_PRECEDE_TIME_LEN = 5513; // 8 +static const uint64_t SH_FLD_CMD_QX_SEVERE_ERR = 5514; // 1 +static const uint64_t SH_FLD_CMD_REG = 5515; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_1 = 5516; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_1_LEN = 5517; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_2 = 5518; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_2_LEN = 5519; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_3 = 5520; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_3_LEN = 5521; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_4 = 5522; // 1 +static const uint64_t SH_FLD_CMD_REG_ADDR_4_LEN = 5523; // 1 +static const uint64_t SH_FLD_CMD_REG_BIT_READCONT = 5524; // 1 +static const uint64_t SH_FLD_CMD_REG_BIT_RNW = 5525; // 1 +static const uint64_t SH_FLD_CMD_REG_BIT_WITHADDR = 5526; // 1 +static const uint64_t SH_FLD_CMD_REG_BIT_WITHSTART = 5527; // 1 +static const uint64_t SH_FLD_CMD_REG_BIT_WITHSTOP = 5528; // 1 +static const uint64_t SH_FLD_CMD_REG_LEN = 5529; // 1 +static const uint64_t SH_FLD_CMD_REG_LENGTH = 5530; // 1 +static const uint64_t SH_FLD_CMD_REG_LENGTH_LEN = 5531; // 1 +static const uint64_t SH_FLD_CMD_SCOPE = 5532; // 4 +static const uint64_t SH_FLD_CMD_SCOPE_LEN = 5533; // 4 +static const uint64_t SH_FLD_CMD_STATUS = 5534; // 1 +static const uint64_t SH_FLD_CMD_STATUS_LEN = 5535; // 1 +static const uint64_t SH_FLD_CME0_IVRM_DROPOUT = 5536; // 6 +static const uint64_t SH_FLD_CME1_IVRM_DROPOUT = 5537; // 6 +static const uint64_t SH_FLD_CMETH = 5538; // 6 +static const uint64_t SH_FLD_CMETH_LEN = 5539; // 6 +static const uint64_t SH_FLD_CME_ERROR_NOTIFY = 5540; // 1 +static const uint64_t SH_FLD_CME_ERR_NOTIFY_DIS = 5541; // 24 +static const uint64_t SH_FLD_CME_INTERPPM_ACLK_ENABLE = 5542; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_ACLK_SEL = 5543; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_DPLL_ENABLE = 5544; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_DPLL_SEL = 5545; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_IVRM_ENABLE = 5546; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_IVRM_SEL = 5547; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_VDATA_ENABLE = 5548; // 6 +static const uint64_t SH_FLD_CME_INTERPPM_VDATA_SEL = 5549; // 6 +static const uint64_t SH_FLD_CME_MESSAGE = 5550; // 24 +static const uint64_t SH_FLD_CME_MESSAGE_HI = 5551; // 48 +static const uint64_t SH_FLD_CME_MESSAGE_HI_LEN = 5552; // 48 +static const uint64_t SH_FLD_CME_MESSAGE_LEN = 5553; // 24 +static const uint64_t SH_FLD_CME_MESSAGE_NUMBER0 = 5554; // 24 +static const uint64_t SH_FLD_CME_MESSAGE_NUMBER0_LEN = 5555; // 24 +static const uint64_t SH_FLD_CME_MESSAGE_NUMBER_N = 5556; // 72 +static const uint64_t SH_FLD_CME_MESSAGE_NUMBER_N_LEN = 5557; // 72 +static const uint64_t SH_FLD_CME_POWSAV = 5558; // 24 +static const uint64_t SH_FLD_CME_REQUEST = 5559; // 96 +static const uint64_t SH_FLD_CME_SCOM_XISIB_PIB_IFETCH_PENDING = 5560; // 12 +static const uint64_t SH_FLD_CME_SPECIAL_WKUP_DONE = 5561; // 24 +static const uint64_t SH_FLD_CME_SPECIAL_WKUP_DONE_DIS = 5562; // 24 +static const uint64_t SH_FLD_CMFSI_ACCESS_PROTCT = 5563; // 1 +static const uint64_t SH_FLD_CMFSI_PORT_ID_SELECT = 5564; // 2 +static const uint64_t SH_FLD_CMFSI_PORT_ID_SELECT_LEN = 5565; // 2 +static const uint64_t SH_FLD_CMFSI_SLAVE_ID_SELECT = 5566; // 2 +static const uint64_t SH_FLD_CMFSI_SLAVE_ID_SELECT_LEN = 5567; // 2 +static const uint64_t SH_FLD_CMLEN = 5568; // 7 +static const uint64_t SH_FLD_CMLEN100 = 5569; // 3 +static const uint64_t SH_FLD_CMLEN133 = 5570; // 3 +static const uint64_t SH_FLD_CMLEN156 = 5571; // 3 +static const uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87 = 5572; // 162 +static const uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN = 5573; // 162 +static const uint64_t SH_FLD_CMP_MSK_LT_B_TO_63 = 5574; // 162 +static const uint64_t SH_FLD_CMP_MSK_LT_B_TO_63_LEN = 5575; // 162 +static const uint64_t SH_FLD_CMSK = 5576; // 43 +static const uint64_t SH_FLD_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 5577; // 3 +static const uint64_t SH_FLD_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 5578; // 3 +static const uint64_t SH_FLD_CM_ANY_MASTER_ERROR = 5579; // 3 +static const uint64_t SH_FLD_CM_ANY_PORT_INTERRUPT = 5580; // 3 +static const uint64_t SH_FLD_CM_CFG = 5581; // 6 +static const uint64_t SH_FLD_CM_CFG_LEN = 5582; // 6 +static const uint64_t SH_FLD_CM_CNTL = 5583; // 120 +static const uint64_t SH_FLD_CM_CNTL_LEN = 5584; // 120 +static const uint64_t SH_FLD_CM_CONTROL_REGISTER_PARITY_INTERRUPT = 5585; // 3 +static const uint64_t SH_FLD_CM_HOT_PLUG_EVENT = 5586; // 3 +static const uint64_t SH_FLD_CM_OFFSET_VAL = 5587; // 6 +static const uint64_t SH_FLD_CM_OFFSET_VAL_LEN = 5588; // 6 +static const uint64_t SH_FLD_CM_TIMEOUT = 5589; // 6 +static const uint64_t SH_FLD_CM_TIMEOUT_LEN = 5590; // 6 +static const uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE = 5591; // 1 +static const uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE_LEN = 5592; // 1 +static const uint64_t SH_FLD_CNT0 = 5593; // 2 +static const uint64_t SH_FLD_CNT0_BIT_PAIR_SEL = 5594; // 1 +static const uint64_t SH_FLD_CNT0_BIT_PAIR_SEL_LEN = 5595; // 1 +static const uint64_t SH_FLD_CNT0_ENABLE = 5596; // 1 +static const uint64_t SH_FLD_CNT0_EVENT_SEL = 5597; // 1 +static const uint64_t SH_FLD_CNT0_EVENT_SEL_LEN = 5598; // 1 +static const uint64_t SH_FLD_CNT0_LEN = 5599; // 2 +static const uint64_t SH_FLD_CNT0_LE_EN = 5600; // 6 +static const uint64_t SH_FLD_CNT0_MUX_SEL = 5601; // 2 +static const uint64_t SH_FLD_CNT0_MUX_SEL_LEN = 5602; // 2 +static const uint64_t SH_FLD_CNT0_PAIR_OP = 5603; // 2 +static const uint64_t SH_FLD_CNT0_PAIR_OP_LEN = 5604; // 2 +static const uint64_t SH_FLD_CNT0_POSEDGE_SEL = 5605; // 1 +static const uint64_t SH_FLD_CNT0_TE_EN = 5606; // 6 +static const uint64_t SH_FLD_CNT1 = 5607; // 2 +static const uint64_t SH_FLD_CNT1_BIT_PAIR_SEL = 5608; // 1 +static const uint64_t SH_FLD_CNT1_BIT_PAIR_SEL_LEN = 5609; // 1 +static const uint64_t SH_FLD_CNT1_ENABLE = 5610; // 1 +static const uint64_t SH_FLD_CNT1_EVENT_SEL = 5611; // 1 +static const uint64_t SH_FLD_CNT1_EVENT_SEL_LEN = 5612; // 1 +static const uint64_t SH_FLD_CNT1_LEN = 5613; // 2 +static const uint64_t SH_FLD_CNT1_LE_EN = 5614; // 6 +static const uint64_t SH_FLD_CNT1_MUX_SEL = 5615; // 2 +static const uint64_t SH_FLD_CNT1_MUX_SEL_LEN = 5616; // 2 +static const uint64_t SH_FLD_CNT1_PAIR_OP = 5617; // 2 +static const uint64_t SH_FLD_CNT1_PAIR_OP_LEN = 5618; // 2 +static const uint64_t SH_FLD_CNT1_POSEDGE_SEL = 5619; // 1 +static const uint64_t SH_FLD_CNT1_TE_EN = 5620; // 6 +static const uint64_t SH_FLD_CNT2 = 5621; // 2 +static const uint64_t SH_FLD_CNT2_BIT_PAIR_SEL = 5622; // 1 +static const uint64_t SH_FLD_CNT2_BIT_PAIR_SEL_LEN = 5623; // 1 +static const uint64_t SH_FLD_CNT2_ENABLE = 5624; // 1 +static const uint64_t SH_FLD_CNT2_EVENT_SEL = 5625; // 1 +static const uint64_t SH_FLD_CNT2_EVENT_SEL_LEN = 5626; // 1 +static const uint64_t SH_FLD_CNT2_LEN = 5627; // 2 +static const uint64_t SH_FLD_CNT2_LE_EN = 5628; // 6 +static const uint64_t SH_FLD_CNT2_MUX_SEL = 5629; // 2 +static const uint64_t SH_FLD_CNT2_MUX_SEL_LEN = 5630; // 2 +static const uint64_t SH_FLD_CNT2_PAIR_OP = 5631; // 2 +static const uint64_t SH_FLD_CNT2_PAIR_OP_LEN = 5632; // 2 +static const uint64_t SH_FLD_CNT2_POSEDGE_SEL = 5633; // 1 +static const uint64_t SH_FLD_CNT2_TE_EN = 5634; // 6 +static const uint64_t SH_FLD_CNT3 = 5635; // 2 +static const uint64_t SH_FLD_CNT3_BIT_PAIR_SEL = 5636; // 1 +static const uint64_t SH_FLD_CNT3_BIT_PAIR_SEL_LEN = 5637; // 1 +static const uint64_t SH_FLD_CNT3_ENABLE = 5638; // 1 +static const uint64_t SH_FLD_CNT3_EVENT_SEL = 5639; // 1 +static const uint64_t SH_FLD_CNT3_EVENT_SEL_LEN = 5640; // 1 +static const uint64_t SH_FLD_CNT3_LEN = 5641; // 2 +static const uint64_t SH_FLD_CNT3_LE_EN = 5642; // 6 +static const uint64_t SH_FLD_CNT3_MUX_SEL = 5643; // 2 +static const uint64_t SH_FLD_CNT3_MUX_SEL_LEN = 5644; // 2 +static const uint64_t SH_FLD_CNT3_PAIR_OP = 5645; // 2 +static const uint64_t SH_FLD_CNT3_PAIR_OP_LEN = 5646; // 2 +static const uint64_t SH_FLD_CNT3_POSEDGE_SEL = 5647; // 1 +static const uint64_t SH_FLD_CNT3_TE_EN = 5648; // 6 +static const uint64_t SH_FLD_CNTL = 5649; // 8 +static const uint64_t SH_FLD_CNTLS_PREV_LDED_GCRMSG = 5650; // 4 +static const uint64_t SH_FLD_CNTL_LEN = 5651; // 8 +static const uint64_t SH_FLD_CNT_BROADCAST_BL = 5652; // 1 +static const uint64_t SH_FLD_CNT_BROADCAST_BL_LEN = 5653; // 1 +static const uint64_t SH_FLD_CNT_CI_STORE_REPLAY = 5654; // 1 +static const uint64_t SH_FLD_CNT_CI_STORE_REPLAY_LEN = 5655; // 1 +static const uint64_t SH_FLD_CNT_DEM_CACHE_HIT = 5656; // 1 +static const uint64_t SH_FLD_CNT_DEM_CACHE_HIT_LEN = 5657; // 1 +static const uint64_t SH_FLD_CNT_DMA_RD = 5658; // 6 +static const uint64_t SH_FLD_CNT_DMA_RD_LEN = 5659; // 6 +static const uint64_t SH_FLD_CNT_DMA_WR = 5660; // 6 +static const uint64_t SH_FLD_CNT_DMA_WR_LEN = 5661; // 6 +static const uint64_t SH_FLD_CNT_EBB = 5662; // 1 +static const uint64_t SH_FLD_CNT_EBB_LEN = 5663; // 1 +static const uint64_t SH_FLD_CNT_EN = 5664; // 6 +static const uint64_t SH_FLD_CNT_EOI_CACHE_HIT = 5665; // 1 +static const uint64_t SH_FLD_CNT_EOI_CACHE_HIT_LEN = 5666; // 1 +static const uint64_t SH_FLD_CNT_EOI_RESP_REPLAY = 5667; // 2 +static const uint64_t SH_FLD_CNT_EOI_RESP_REPLAY_LEN = 5668; // 2 +static const uint64_t SH_FLD_CNT_EQC_COMMAND = 5669; // 1 +static const uint64_t SH_FLD_CNT_EQC_COMMAND_LEN = 5670; // 1 +static const uint64_t SH_FLD_CNT_EQD_FETCH = 5671; // 1 +static const uint64_t SH_FLD_CNT_EQD_FETCH_LEN = 5672; // 1 +static const uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY = 5673; // 1 +static const uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY_LEN = 5674; // 1 +static const uint64_t SH_FLD_CNT_EQP = 5675; // 1 +static const uint64_t SH_FLD_CNT_EQP_LEN = 5676; // 1 +static const uint64_t SH_FLD_CNT_EQP_REPLAY = 5677; // 1 +static const uint64_t SH_FLD_CNT_EQP_REPLAY_LEN = 5678; // 1 +static const uint64_t SH_FLD_CNT_EQ_FWD = 5679; // 1 +static const uint64_t SH_FLD_CNT_EQ_FWD_LEN = 5680; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC = 5681; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 5682; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC = 5683; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 5684; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD = 5685; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN = 5686; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI = 5687; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN = 5688; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS = 5689; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 5690; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT = 5691; // 1 +static const uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN = 5692; // 1 +static const uint64_t SH_FLD_CNT_ESCALATE = 5693; // 1 +static const uint64_t SH_FLD_CNT_ESCALATE_LEN = 5694; // 1 +static const uint64_t SH_FLD_CNT_FIFO_FULL = 5695; // 6 +static const uint64_t SH_FLD_CNT_FIFO_FULL_LEN = 5696; // 6 +static const uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT = 5697; // 1 +static const uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN = 5698; // 1 +static const uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE = 5699; // 1 +static const uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN = 5700; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE = 5701; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN = 5702; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC = 5703; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 5704; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE = 5705; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN = 5706; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC = 5707; // 1 +static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 5708; // 1 +static const uint64_t SH_FLD_CNT_ISB_FETCH = 5709; // 1 +static const uint64_t SH_FLD_CNT_ISB_FETCH_LEN = 5710; // 1 +static const uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY = 5711; // 1 +static const uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY_LEN = 5712; // 1 +static const uint64_t SH_FLD_CNT_ISB_WRITE = 5713; // 1 +static const uint64_t SH_FLD_CNT_ISB_WRITE_LEN = 5714; // 1 +static const uint64_t SH_FLD_CNT_IVC_DEMAND = 5715; // 1 +static const uint64_t SH_FLD_CNT_IVC_DEMAND_LEN = 5716; // 1 +static const uint64_t SH_FLD_CNT_IVC_PRF = 5717; // 1 +static const uint64_t SH_FLD_CNT_IVC_PRF_LEN = 5718; // 1 +static const uint64_t SH_FLD_CNT_IVC_RESP_REPLAY = 5719; // 1 +static const uint64_t SH_FLD_CNT_IVC_RESP_REPLAY_LEN = 5720; // 1 +static const uint64_t SH_FLD_CNT_IVE_FETCH = 5721; // 1 +static const uint64_t SH_FLD_CNT_IVE_FETCH_LEN = 5722; // 1 +static const uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY = 5723; // 1 +static const uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY_LEN = 5724; // 1 +static const uint64_t SH_FLD_CNT_IVVC_RESP = 5725; // 1 +static const uint64_t SH_FLD_CNT_IVVC_RESP_LEN = 5726; // 1 +static const uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY = 5727; // 1 +static const uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN = 5728; // 1 +static const uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF = 5729; // 1 +static const uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF_LEN = 5730; // 1 +static const uint64_t SH_FLD_CNT_LCL_REDIST = 5731; // 1 +static const uint64_t SH_FLD_CNT_LCL_REDIST_LEN = 5732; // 1 +static const uint64_t SH_FLD_CNT_LD_CACHE_HIT = 5733; // 1 +static const uint64_t SH_FLD_CNT_LD_CACHE_HIT_LEN = 5734; // 1 +static const uint64_t SH_FLD_CNT_LD_REQ_REPLAY = 5735; // 1 +static const uint64_t SH_FLD_CNT_LD_REQ_REPLAY_LEN = 5736; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_ESCALATE = 5737; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_ESCALATE_LEN = 5738; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT = 5739; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN = 5740; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY = 5741; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN = 5742; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN = 5743; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN = 5744; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY = 5745; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN = 5746; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_SBC_UPD = 5747; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_SBC_UPD_LEN = 5748; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY = 5749; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN = 5750; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_VPC_UPD = 5751; // 1 +static const uint64_t SH_FLD_CNT_LOCAL_VPC_UPD_LEN = 5752; // 1 +static const uint64_t SH_FLD_CNT_LS = 5753; // 1 +static const uint64_t SH_FLD_CNT_LS_LEN = 5754; // 1 +static const uint64_t SH_FLD_CNT_NEW_CMD_STALLED = 5755; // 1 +static const uint64_t SH_FLD_CNT_NEW_CMD_STALLED_LEN = 5756; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_EOI = 5757; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_LEN = 5758; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED = 5759; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 5760; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED = 5761; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN = 5762; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_LOAD = 5763; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_LOAD_LEN = 5764; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD = 5765; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN = 5766; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD = 5767; // 1 +static const uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN = 5768; // 1 +static const uint64_t SH_FLD_CNT_OTHER_CACHE_HIT = 5769; // 1 +static const uint64_t SH_FLD_CNT_OTHER_CACHE_HIT_LEN = 5770; // 1 +static const uint64_t SH_FLD_CNT_PRF_CACHE_HIT = 5771; // 2 +static const uint64_t SH_FLD_CNT_PRF_CACHE_HIT_LEN = 5772; // 2 +static const uint64_t SH_FLD_CNT_R0 = 5773; // 6 +static const uint64_t SH_FLD_CNT_R0_LEN = 5774; // 6 +static const uint64_t SH_FLD_CNT_R10R = 5775; // 3 +static const uint64_t SH_FLD_CNT_R10R_LEN = 5776; // 3 +static const uint64_t SH_FLD_CNT_R10W = 5777; // 3 +static const uint64_t SH_FLD_CNT_R10W_LEN = 5778; // 3 +static const uint64_t SH_FLD_CNT_R1R = 5779; // 6 +static const uint64_t SH_FLD_CNT_R1R_LEN = 5780; // 6 +static const uint64_t SH_FLD_CNT_R1W = 5781; // 6 +static const uint64_t SH_FLD_CNT_R1W_LEN = 5782; // 6 +static const uint64_t SH_FLD_CNT_R2 = 5783; // 6 +static const uint64_t SH_FLD_CNT_R2_LEN = 5784; // 6 +static const uint64_t SH_FLD_CNT_R3 = 5785; // 6 +static const uint64_t SH_FLD_CNT_R3_LEN = 5786; // 6 +static const uint64_t SH_FLD_CNT_R4 = 5787; // 3 +static const uint64_t SH_FLD_CNT_R4R = 5788; // 3 +static const uint64_t SH_FLD_CNT_R4R_LEN = 5789; // 3 +static const uint64_t SH_FLD_CNT_R4W = 5790; // 3 +static const uint64_t SH_FLD_CNT_R4W_LEN = 5791; // 3 +static const uint64_t SH_FLD_CNT_R4_LEN = 5792; // 3 +static const uint64_t SH_FLD_CNT_R5 = 5793; // 3 +static const uint64_t SH_FLD_CNT_R5R = 5794; // 3 +static const uint64_t SH_FLD_CNT_R5R_LEN = 5795; // 3 +static const uint64_t SH_FLD_CNT_R5W = 5796; // 3 +static const uint64_t SH_FLD_CNT_R5W_LEN = 5797; // 3 +static const uint64_t SH_FLD_CNT_R5_LEN = 5798; // 3 +static const uint64_t SH_FLD_CNT_R6 = 5799; // 6 +static const uint64_t SH_FLD_CNT_R6_LEN = 5800; // 6 +static const uint64_t SH_FLD_CNT_R7 = 5801; // 3 +static const uint64_t SH_FLD_CNT_R7EQP = 5802; // 3 +static const uint64_t SH_FLD_CNT_R7EQP_LEN = 5803; // 3 +static const uint64_t SH_FLD_CNT_R7INT = 5804; // 3 +static const uint64_t SH_FLD_CNT_R7INT_LEN = 5805; // 3 +static const uint64_t SH_FLD_CNT_R7RSP = 5806; // 3 +static const uint64_t SH_FLD_CNT_R7RSP_LEN = 5807; // 3 +static const uint64_t SH_FLD_CNT_R7_LEN = 5808; // 3 +static const uint64_t SH_FLD_CNT_R8 = 5809; // 6 +static const uint64_t SH_FLD_CNT_R8_LEN = 5810; // 6 +static const uint64_t SH_FLD_CNT_R9 = 5811; // 6 +static const uint64_t SH_FLD_CNT_R9_LEN = 5812; // 6 +static const uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY = 5813; // 1 +static const uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 5814; // 1 +static const uint64_t SH_FLD_CNT_REMOTE_SBC_UPD = 5815; // 1 +static const uint64_t SH_FLD_CNT_REMOTE_SBC_UPD_LEN = 5816; // 1 +static const uint64_t SH_FLD_CNT_REMOTE_VPC_UPD = 5817; // 1 +static const uint64_t SH_FLD_CNT_REMOTE_VPC_UPD_LEN = 5818; // 1 +static const uint64_t SH_FLD_CNT_REPLAY = 5819; // 1 +static const uint64_t SH_FLD_CNT_REPLAY_LEN = 5820; // 1 +static const uint64_t SH_FLD_CNT_RESUME = 5821; // 1 +static const uint64_t SH_FLD_CNT_RESUME_LEN = 5822; // 1 +static const uint64_t SH_FLD_CNT_RETRY = 5823; // 3 +static const uint64_t SH_FLD_CNT_RETRY_LEN = 5824; // 3 +static const uint64_t SH_FLD_CNT_RMT_PULL_1STGRP = 5825; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_1STGRP_LEN = 5826; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_1STVP = 5827; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_1STVP_LEN = 5828; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_GRP = 5829; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_GRP_LEN = 5830; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_VP = 5831; // 1 +static const uint64_t SH_FLD_CNT_RMT_PULL_VP_LEN = 5832; // 1 +static const uint64_t SH_FLD_CNT_RMT_PUSH = 5833; // 1 +static const uint64_t SH_FLD_CNT_RMT_PUSH_LEN = 5834; // 1 +static const uint64_t SH_FLD_CNT_RMT_PUSH_VC = 5835; // 1 +static const uint64_t SH_FLD_CNT_RMT_PUSH_VC_LEN = 5836; // 1 +static const uint64_t SH_FLD_CNT_RSP_ATX_REPLAY = 5837; // 1 +static const uint64_t SH_FLD_CNT_RSP_ATX_REPLAY_LEN = 5838; // 1 +static const uint64_t SH_FLD_CNT_RSP_LCL_TCTXT = 5839; // 1 +static const uint64_t SH_FLD_CNT_RSP_LCL_TCTXT_LEN = 5840; // 1 +static const uint64_t SH_FLD_CNT_RSP_LCL_VC = 5841; // 1 +static const uint64_t SH_FLD_CNT_RSP_LCL_VC_LEN = 5842; // 1 +static const uint64_t SH_FLD_CNT_RSP_RMT = 5843; // 1 +static const uint64_t SH_FLD_CNT_RSP_RMT_LEN = 5844; // 1 +static const uint64_t SH_FLD_CNT_RSP_RMT_VC = 5845; // 1 +static const uint64_t SH_FLD_CNT_RSP_RMT_VC_LEN = 5846; // 1 +static const uint64_t SH_FLD_CNT_RSP_SW_LD = 5847; // 1 +static const uint64_t SH_FLD_CNT_RSP_SW_LD_LEN = 5848; // 1 +static const uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY = 5849; // 1 +static const uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN = 5850; // 1 +static const uint64_t SH_FLD_CNT_SAME_VPD_REPLAY = 5851; // 1 +static const uint64_t SH_FLD_CNT_SAME_VPD_REPLAY_LEN = 5852; // 1 +static const uint64_t SH_FLD_CNT_SBC_LOOKUP = 5853; // 1 +static const uint64_t SH_FLD_CNT_SBC_LOOKUP_LEN = 5854; // 1 +static const uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY = 5855; // 1 +static const uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN = 5856; // 1 +static const uint64_t SH_FLD_CNT_SINGLE_LANE_RECAL = 5857; // 6 +static const uint64_t SH_FLD_CNT_SPEC_EOI = 5858; // 1 +static const uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT = 5859; // 1 +static const uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN = 5860; // 1 +static const uint64_t SH_FLD_CNT_SPEC_EOI_LEN = 5861; // 1 +static const uint64_t SH_FLD_CNT_ST_LCL_REPLAY = 5862; // 1 +static const uint64_t SH_FLD_CNT_ST_LCL_REPLAY_LEN = 5863; // 1 +static const uint64_t SH_FLD_CNT_ST_RMT_REPLAY = 5864; // 1 +static const uint64_t SH_FLD_CNT_ST_RMT_REPLAY_LEN = 5865; // 1 +static const uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY = 5866; // 1 +static const uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN = 5867; // 1 +static const uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES = 5868; // 3 +static const uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES_LEN = 5869; // 3 +static const uint64_t SH_FLD_CNT_TRIG_DROPPED = 5870; // 6 +static const uint64_t SH_FLD_CNT_TRIG_DROPPED_LEN = 5871; // 6 +static const uint64_t SH_FLD_CNT_TRIG_FROM_AIB = 5872; // 6 +static const uint64_t SH_FLD_CNT_TRIG_FROM_AIB_LEN = 5873; // 6 +static const uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC = 5874; // 6 +static const uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN = 5875; // 6 +static const uint64_t SH_FLD_CNT_USE_L2_DIVIDER_EN = 5876; // 12 +static const uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE = 5877; // 2 +static const uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN = 5878; // 2 +static const uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE = 5879; // 2 +static const uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN = 5880; // 2 +static const uint64_t SH_FLD_CNT_VICTIM_IS_LRU = 5881; // 4 +static const uint64_t SH_FLD_CNT_VICTIM_IS_LRU_LEN = 5882; // 4 +static const uint64_t SH_FLD_CNT_VP = 5883; // 1 +static const uint64_t SH_FLD_CNT_VPD_FETCH = 5884; // 1 +static const uint64_t SH_FLD_CNT_VPD_FETCH_LEN = 5885; // 1 +static const uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY = 5886; // 1 +static const uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY_LEN = 5887; // 1 +static const uint64_t SH_FLD_CNT_VPD_WB = 5888; // 1 +static const uint64_t SH_FLD_CNT_VPD_WB_LEN = 5889; // 1 +static const uint64_t SH_FLD_CNT_VP_LEN = 5890; // 1 +static const uint64_t SH_FLD_CNT_VRQ_CACHE_HIT = 5891; // 1 +static const uint64_t SH_FLD_CNT_VRQ_CACHE_HIT_LEN = 5892; // 1 +static const uint64_t SH_FLD_CNT_VRQ_PULL = 5893; // 1 +static const uint64_t SH_FLD_CNT_VRQ_PULL_LEN = 5894; // 1 +static const uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL = 5895; // 1 +static const uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN = 5896; // 1 +static const uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE = 5897; // 1 +static const uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN = 5898; // 1 +static const uint64_t SH_FLD_COARSE_CAL_STEP_SIZE = 5899; // 8 +static const uint64_t SH_FLD_COARSE_CAL_STEP_SIZE_LEN = 5900; // 8 +static const uint64_t SH_FLD_COARSE_DIR_ENABLE = 5901; // 2 +static const uint64_t SH_FLD_COARSE_DIR_SECTORS = 5902; // 2 +static const uint64_t SH_FLD_COARSE_RD = 5903; // 8 +static const uint64_t SH_FLD_COFSM_ADDR = 5904; // 12 +static const uint64_t SH_FLD_COHERENCY_ERROR = 5905; // 2 +static const uint64_t SH_FLD_COL4_BIT_MAP = 5906; // 8 +static const uint64_t SH_FLD_COL4_BIT_MAP_LEN = 5907; // 8 +static const uint64_t SH_FLD_COL5_BIT_MAP = 5908; // 8 +static const uint64_t SH_FLD_COL5_BIT_MAP_LEN = 5909; // 8 +static const uint64_t SH_FLD_COL6_BIT_MAP = 5910; // 8 +static const uint64_t SH_FLD_COL6_BIT_MAP_LEN = 5911; // 8 +static const uint64_t SH_FLD_COL7_BIT_MAP = 5912; // 8 +static const uint64_t SH_FLD_COL7_BIT_MAP_LEN = 5913; // 8 +static const uint64_t SH_FLD_COL8_BIT_MAP = 5914; // 8 +static const uint64_t SH_FLD_COL8_BIT_MAP_LEN = 5915; // 8 +static const uint64_t SH_FLD_COL9_BIT_MAP = 5916; // 8 +static const uint64_t SH_FLD_COL9_BIT_MAP_LEN = 5917; // 8 +static const uint64_t SH_FLD_COLLISION_MODES = 5918; // 4 +static const uint64_t SH_FLD_COLLISION_MODES_LEN = 5919; // 4 +static const uint64_t SH_FLD_COLLISON = 5920; // 1 +static const uint64_t SH_FLD_COMMAND_ADDRESS_TIMEOUT = 5921; // 2 +static const uint64_t SH_FLD_COMMAND_COMPLETE = 5922; // 1 +static const uint64_t SH_FLD_COMMAND_LIST_TIMEOUT = 5923; // 4 +static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE = 5924; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_EN = 5925; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_LEN = 5926; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SB_SPARE = 5927; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH = 5928; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH_LEN = 5929; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SW_RESCLK = 5930; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SW_RESCLK_LEN = 5931; // 6 +static const uint64_t SH_FLD_COMMON_CLK_SW_SPARE = 5932; // 6 +static const uint64_t SH_FLD_COMMON_FREEZE_MODE = 5933; // 7 +static const uint64_t SH_FLD_COMM_ACK = 5934; // 12 +static const uint64_t SH_FLD_COMM_NACK = 5935; // 12 +static const uint64_t SH_FLD_COMM_RECV = 5936; // 12 +static const uint64_t SH_FLD_COMM_RECVD = 5937; // 12 +static const uint64_t SH_FLD_COMM_RECV_LEN = 5938; // 12 +static const uint64_t SH_FLD_COMM_SEND = 5939; // 12 +static const uint64_t SH_FLD_COMM_SEND_ACK = 5940; // 12 +static const uint64_t SH_FLD_COMM_SEND_LEN = 5941; // 12 +static const uint64_t SH_FLD_COMM_SEND_NACK = 5942; // 12 +static const uint64_t SH_FLD_COMPARE = 5943; // 2 +static const uint64_t SH_FLD_COMPARE_LEN = 5944; // 2 +static const uint64_t SH_FLD_COMPLETE = 5945; // 8 +static const uint64_t SH_FLD_COMPLETE_LEN = 5946; // 8 +static const uint64_t SH_FLD_COMPLETION_DELAY = 5947; // 96 +static const uint64_t SH_FLD_COMPLETION_DELAY_LEN = 5948; // 96 +static const uint64_t SH_FLD_COMPLEX_FAULT = 5949; // 1 +static const uint64_t SH_FLD_COMPLEX_FAULT_MASK = 5950; // 1 +static const uint64_t SH_FLD_COMPLEX_NOTIFY = 5951; // 1 +static const uint64_t SH_FLD_COMPLEX_NOTIFY_MASK = 5952; // 1 +static const uint64_t SH_FLD_COMPRESSED_RSP_ENA = 5953; // 6 +static const uint64_t SH_FLD_COMP_CNT_LIMIT = 5954; // 24 +static const uint64_t SH_FLD_COMP_CNT_LIMIT_LEN = 5955; // 24 +static const uint64_t SH_FLD_COMP_CYCLE = 5956; // 36 +static const uint64_t SH_FLD_COMP_CYCLE_LEN = 5957; // 36 +static const uint64_t SH_FLD_COMP_MASK = 5958; // 4 +static const uint64_t SH_FLD_COMP_MASK_LEN = 5959; // 4 +static const uint64_t SH_FLD_COND1_SEL_A = 5960; // 86 +static const uint64_t SH_FLD_COND1_SEL_A_LEN = 5961; // 86 +static const uint64_t SH_FLD_COND1_SEL_B = 5962; // 86 +static const uint64_t SH_FLD_COND1_SEL_B_LEN = 5963; // 86 +static const uint64_t SH_FLD_COND2_SEL_A = 5964; // 86 +static const uint64_t SH_FLD_COND2_SEL_A_LEN = 5965; // 86 +static const uint64_t SH_FLD_COND2_SEL_B = 5966; // 86 +static const uint64_t SH_FLD_COND2_SEL_B_LEN = 5967; // 86 +static const uint64_t SH_FLD_COND3_ENABLE_RESET = 5968; // 86 +static const uint64_t SH_FLD_COND_STARTUP_TEST_FAIL = 5969; // 1 +static const uint64_t SH_FLD_CONFIG = 5970; // 1 +static const uint64_t SH_FLD_CONFIG1_RESERVED0 = 5971; // 3 +static const uint64_t SH_FLD_CONFIG1_RESERVED1 = 5972; // 15 +static const uint64_t SH_FLD_CONFIG1_RESERVED1_LEN = 5973; // 3 +static const uint64_t SH_FLD_CONFIG1_RESERVED2 = 5974; // 15 +static const uint64_t SH_FLD_CONFIG1_RESERVED2_LEN = 5975; // 3 +static const uint64_t SH_FLD_CONFIG_0 = 5976; // 5 +static const uint64_t SH_FLD_CONFIG_0_LEN = 5977; // 5 +static const uint64_t SH_FLD_CONFIG_1 = 5978; // 5 +static const uint64_t SH_FLD_CONFIG_1_LEN = 5979; // 5 +static const uint64_t SH_FLD_CONFIG_ADDR = 5980; // 48 +static const uint64_t SH_FLD_CONFIG_ADDR_LEN = 5981; // 48 +static const uint64_t SH_FLD_CONFIG_ADR_BAR_MODE = 5982; // 15 +static const uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY = 5983; // 12 +static const uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN = 5984; // 12 +static const uint64_t SH_FLD_CONFIG_BRAZOS = 5985; // 1 +static const uint64_t SH_FLD_CONFIG_BRAZOS_MODE = 5986; // 15 +static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 5987; // 12 +static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 5988; // 12 +static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 5989; // 12 +static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 5990; // 12 +static const uint64_t SH_FLD_CONFIG_CHIP = 5991; // 48 +static const uint64_t SH_FLD_CONFIG_CHIP_LEN = 5992; // 48 +static const uint64_t SH_FLD_CONFIG_DCACHE_MODE = 5993; // 12 +static const uint64_t SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL = 5994; // 12 +static const uint64_t SH_FLD_CONFIG_DISABLE_G = 5995; // 12 +static const uint64_t SH_FLD_CONFIG_DISABLE_INJECT = 5996; // 12 +static const uint64_t SH_FLD_CONFIG_DISABLE_LN = 5997; // 12 +static const uint64_t SH_FLD_CONFIG_DISABLE_NN_RN = 5998; // 12 +static const uint64_t SH_FLD_CONFIG_DISABLE_PBM_ECC_COR = 5999; // 3 +static const uint64_t SH_FLD_CONFIG_DISABLE_VG_NOT_SYS = 6000; // 12 +static const uint64_t SH_FLD_CONFIG_ENABLE = 6001; // 48 +static const uint64_t SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC = 6002; // 12 +static const uint64_t SH_FLD_CONFIG_ENABLE_PBUS = 6003; // 12 +static const uint64_t SH_FLD_CONFIG_ENABLE_SNARF_CPM = 6004; // 12 +static const uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT = 6005; // 12 +static const uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN = 6006; // 12 +static const uint64_t SH_FLD_CONFIG_EVAPORATE_BY_LCO = 6007; // 12 +static const uint64_t SH_FLD_CONFIG_FORBID_MMIO_ATOMIC = 6008; // 12 +static const uint64_t SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 = 6009; // 12 +static const uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY = 6010; // 3 +static const uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN = 6011; // 3 +static const uint64_t SH_FLD_CONFIG_GPU0_ADDR = 6012; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_ADDR_LEN = 6013; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_CHIP = 6014; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_CHIP_LEN = 6015; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_ENABLE = 6016; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_GRANULE = 6017; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_GROUP = 6018; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_GROUP_LEN = 6019; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE = 6020; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE_LEN = 6021; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_MODE = 6022; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_MODE_LEN = 6023; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_RESERVED = 6024; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_SIZE = 6025; // 12 +static const uint64_t SH_FLD_CONFIG_GPU0_SIZE_LEN = 6026; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_ADDR = 6027; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_ADDR_LEN = 6028; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_CHIP = 6029; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_CHIP_LEN = 6030; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_ENABLE = 6031; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_GRANULE = 6032; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_GROUP = 6033; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_GROUP_LEN = 6034; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE = 6035; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE_LEN = 6036; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_MODE = 6037; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_MODE_LEN = 6038; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_RESERVED = 6039; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_SIZE = 6040; // 12 +static const uint64_t SH_FLD_CONFIG_GPU1_SIZE_LEN = 6041; // 12 +static const uint64_t SH_FLD_CONFIG_GROUP = 6042; // 48 +static const uint64_t SH_FLD_CONFIG_GROUP_LEN = 6043; // 48 +static const uint64_t SH_FLD_CONFIG_INC_PRI_MASK = 6044; // 12 +static const uint64_t SH_FLD_CONFIG_INC_PRI_MASK_LEN = 6045; // 12 +static const uint64_t SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 = 6046; // 3 +static const uint64_t SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 = 6047; // 3 +static const uint64_t SH_FLD_CONFIG_LEN = 6048; // 1 +static const uint64_t SH_FLD_CONFIG_MACH_CORRENAB = 6049; // 12 +static const uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE1 = 6050; // 12 +static const uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE2 = 6051; // 12 +static const uint64_t SH_FLD_CONFIG_MAX_MACHINES = 6052; // 12 +static const uint64_t SH_FLD_CONFIG_MAX_MACHINES_LEN = 6053; // 12 +static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR = 6054; // 12 +static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG = 6055; // 12 +static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR = 6056; // 12 +static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE = 6057; // 12 +static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA = 6058; // 12 +static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ = 6059; // 12 +static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_WRP = 6060; // 12 +static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_B = 6061; // 12 +static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_C = 6062; // 12 +static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM = 6063; // 12 +static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 6064; // 12 +static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_A = 6065; // 12 +static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_B = 6066; // 12 +static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_C = 6067; // 12 +static const uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ = 6068; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 6069; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 6070; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL = 6071; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN = 6072; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH1 = 6073; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH1_LEN = 6074; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH2 = 6075; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH2_LEN = 6076; // 3 +static const uint64_t SH_FLD_CONFIG_MRBGP_TRACK_ALL = 6077; // 12 +static const uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ = 6078; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 6079; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 6080; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL = 6081; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN = 6082; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH1 = 6083; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH1_LEN = 6084; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH2 = 6085; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH2_LEN = 6086; // 3 +static const uint64_t SH_FLD_CONFIG_MRBSP_TRACK_ALL = 6087; // 12 +static const uint64_t SH_FLD_CONFIG_OPT_SNOOP_CP = 6088; // 12 +static const uint64_t SH_FLD_CONFIG_P9P9_MODE = 6089; // 12 +static const uint64_t SH_FLD_CONFIG_PARITY = 6090; // 43 +static const uint64_t SH_FLD_CONFIG_PCKT_BLK_PRB = 6091; // 12 +static const uint64_t SH_FLD_CONFIG_PRB0 = 6092; // 24 +static const uint64_t SH_FLD_CONFIG_PRB0_LEN = 6093; // 24 +static const uint64_t SH_FLD_CONFIG_PRB1 = 6094; // 24 +static const uint64_t SH_FLD_CONFIG_PRB1_LEN = 6095; // 24 +static const uint64_t SH_FLD_CONFIG_PREALLOC2_PRB0 = 6096; // 12 +static const uint64_t SH_FLD_CONFIG_PREALLOC2_PRB1 = 6097; // 12 +static const uint64_t SH_FLD_CONFIG_PREALLOC2_REQ0 = 6098; // 12 +static const uint64_t SH_FLD_CONFIG_PREALLOC2_REQ1 = 6099; // 12 +static const uint64_t SH_FLD_CONFIG_PREALLOC2_XATS = 6100; // 12 +static const uint64_t SH_FLD_CONFIG_PWR0 = 6101; // 24 +static const uint64_t SH_FLD_CONFIG_PWR0_LEN = 6102; // 24 +static const uint64_t SH_FLD_CONFIG_PWR1 = 6103; // 24 +static const uint64_t SH_FLD_CONFIG_PWR1_LEN = 6104; // 24 +static const uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK = 6105; // 12 +static const uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 6106; // 12 +static const uint64_t SH_FLD_CONFIG_REQ0 = 6107; // 24 +static const uint64_t SH_FLD_CONFIG_REQ0_LEN = 6108; // 24 +static const uint64_t SH_FLD_CONFIG_REQ1 = 6109; // 24 +static const uint64_t SH_FLD_CONFIG_REQ1_LEN = 6110; // 24 +static const uint64_t SH_FLD_CONFIG_RESERVED4 = 6111; // 12 +static const uint64_t SH_FLD_CONFIG_RSI_CORRENAB = 6112; // 12 +static const uint64_t SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 6113; // 12 +static const uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE1 = 6114; // 12 +static const uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE2 = 6115; // 12 +static const uint64_t SH_FLD_CONFIG_RXO_CORRENAB = 6116; // 12 +static const uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE1 = 6117; // 12 +static const uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE2 = 6118; // 12 +static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_DATA = 6119; // 12 +static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN = 6120; // 12 +static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_POLL = 6121; // 12 +static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN = 6122; // 12 +static const uint64_t SH_FLD_CONFIG_SKIP_G = 6123; // 12 +static const uint64_t SH_FLD_CONFIG_SYNC_WAIT = 6124; // 1 +static const uint64_t SH_FLD_CONFIG_SYNC_WAIT_LEN = 6125; // 1 +static const uint64_t SH_FLD_CONFIG_XATS = 6126; // 24 +static const uint64_t SH_FLD_CONFIG_XATS_LEN = 6127; // 24 +static const uint64_t SH_FLD_CONFIRMED = 6128; // 64 +static const uint64_t SH_FLD_CONFLICT = 6129; // 2 +static const uint64_t SH_FLD_CONG = 6130; // 1 +static const uint64_t SH_FLD_CONG_LEN = 6131; // 1 +static const uint64_t SH_FLD_CONSEQ_PASS = 6132; // 8 +static const uint64_t SH_FLD_CONSEQ_PASS_LEN = 6133; // 8 +static const uint64_t SH_FLD_CONSUMED_BUF_COUNT = 6134; // 1 +static const uint64_t SH_FLD_CONSUMED_BUF_COUNT_LEN = 6135; // 1 +static const uint64_t SH_FLD_CONTENT = 6136; // 3 +static const uint64_t SH_FLD_CONTENT_LEN = 6137; // 3 +static const uint64_t SH_FLD_CONTINUOUS = 6138; // 4 +static const uint64_t SH_FLD_CONTROL = 6139; // 15 +static const uint64_t SH_FLD_CONTROL_ERR = 6140; // 12 +static const uint64_t SH_FLD_CONTROL_LEN = 6141; // 15 +static const uint64_t SH_FLD_CONTROL_N = 6142; // 2 +static const uint64_t SH_FLD_CONTROL_REGISTER_RESET = 6143; // 3 +static const uint64_t SH_FLD_CONVERGED_END_COUNT = 6144; // 6 +static const uint64_t SH_FLD_CONVERGED_END_COUNT_LEN = 6145; // 6 +static const uint64_t SH_FLD_COPY_CKE_TO_SPARE_CKE = 6146; // 2 +static const uint64_t SH_FLD_COPY_LENGTH = 6147; // 2 +static const uint64_t SH_FLD_COPY_LENGTH_LEN = 6148; // 2 +static const uint64_t SH_FLD_CORE0_REQ_ACTIVE = 6149; // 12 +static const uint64_t SH_FLD_CORE1_REQ_ACTIVE = 6150; // 12 +static const uint64_t SH_FLD_COREID = 6151; // 1 +static const uint64_t SH_FLD_COREID_LEN = 6152; // 1 +static const uint64_t SH_FLD_CORES_ENABLED_0_23 = 6153; // 1 +static const uint64_t SH_FLD_CORES_ENABLED_0_23_LEN = 6154; // 1 +static const uint64_t SH_FLD_CORE_CHECKSTOP = 6155; // 12 +static const uint64_t SH_FLD_CORE_CONFIG = 6156; // 2 +static const uint64_t SH_FLD_CORE_CONFIG_LEN = 6157; // 2 +static const uint64_t SH_FLD_CORE_DROPOUT_ENABLE = 6158; // 12 +static const uint64_t SH_FLD_CORE_DROPOUT_ENABLE_LEN = 6159; // 12 +static const uint64_t SH_FLD_CORE_EXT_INTR = 6160; // 1 +static const uint64_t SH_FLD_CORE_LIMIT = 6161; // 24 +static const uint64_t SH_FLD_CORE_LIMIT_LEN = 6162; // 24 +static const uint64_t SH_FLD_CORE_MEM_HIER_A = 6163; // 24 +static const uint64_t SH_FLD_CORE_MEM_HIER_A_LEN = 6164; // 24 +static const uint64_t SH_FLD_CORE_MEM_HIER_B = 6165; // 24 +static const uint64_t SH_FLD_CORE_MEM_HIER_B_LEN = 6166; // 24 +static const uint64_t SH_FLD_CORE_MEM_HIER_C = 6167; // 24 +static const uint64_t SH_FLD_CORE_MEM_HIER_C_LEN = 6168; // 24 +static const uint64_t SH_FLD_CORE_OR_SNP_REQ_ACTIVE = 6169; // 12 +static const uint64_t SH_FLD_CORE_RAS0_TRIG_SEL = 6170; // 43 +static const uint64_t SH_FLD_CORE_RAS0_TRIG_SEL_LEN = 6171; // 43 +static const uint64_t SH_FLD_CORE_RAS1_TRIG_SEL = 6172; // 43 +static const uint64_t SH_FLD_CORE_RAS1_TRIG_SEL_LEN = 6173; // 43 +static const uint64_t SH_FLD_CORE_RESET = 6174; // 1 +static const uint64_t SH_FLD_CORE_STEP = 6175; // 1 +static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_ENABLE = 6176; // 1 +static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE = 6177; // 1 +static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_TRIGGER = 6178; // 1 +static const uint64_t SH_FLD_CORE_WORKRATE_BUSY = 6179; // 24 +static const uint64_t SH_FLD_CORE_WORKRATE_BUSY_LEN = 6180; // 24 +static const uint64_t SH_FLD_CORE_WORKRATE_FINISH = 6181; // 24 +static const uint64_t SH_FLD_CORE_WORKRATE_FINISH_LEN = 6182; // 24 +static const uint64_t SH_FLD_CORR_DIS_BR = 6183; // 3 +static const uint64_t SH_FLD_CORR_DIS_IR = 6184; // 3 +static const uint64_t SH_FLD_CORR_DIS_OR = 6185; // 3 +static const uint64_t SH_FLD_CORR_DIS_PR = 6186; // 3 +static const uint64_t SH_FLD_CORR_DIS_PT = 6187; // 3 +static const uint64_t SH_FLD_CORR_ERR = 6188; // 1 +static const uint64_t SH_FLD_COUNT = 6189; // 44 +static const uint64_t SH_FLD_COUNT0_EVENT = 6190; // 6 +static const uint64_t SH_FLD_COUNT0_EVENT_LEN = 6191; // 6 +static const uint64_t SH_FLD_COUNT0_VALUE = 6192; // 6 +static const uint64_t SH_FLD_COUNT0_VALUE_LEN = 6193; // 6 +static const uint64_t SH_FLD_COUNT1_EVENT = 6194; // 6 +static const uint64_t SH_FLD_COUNT1_EVENT_LEN = 6195; // 6 +static const uint64_t SH_FLD_COUNT1_VALUE = 6196; // 6 +static const uint64_t SH_FLD_COUNT1_VALUE_LEN = 6197; // 6 +static const uint64_t SH_FLD_COUNT2_EVENT = 6198; // 6 +static const uint64_t SH_FLD_COUNT2_EVENT_LEN = 6199; // 6 +static const uint64_t SH_FLD_COUNT2_VALUE = 6200; // 6 +static const uint64_t SH_FLD_COUNT2_VALUE_LEN = 6201; // 6 +static const uint64_t SH_FLD_COUNT3_EVENT = 6202; // 6 +static const uint64_t SH_FLD_COUNT3_EVENT_LEN = 6203; // 6 +static const uint64_t SH_FLD_COUNT3_VALUE = 6204; // 6 +static const uint64_t SH_FLD_COUNT3_VALUE_LEN = 6205; // 6 +static const uint64_t SH_FLD_COUNTER = 6206; // 43 +static const uint64_t SH_FLD_COUNTER0 = 6207; // 16 +static const uint64_t SH_FLD_COUNTER0_LEN = 6208; // 16 +static const uint64_t SH_FLD_COUNTER1 = 6209; // 16 +static const uint64_t SH_FLD_COUNTER1_LEN = 6210; // 16 +static const uint64_t SH_FLD_COUNTER2 = 6211; // 16 +static const uint64_t SH_FLD_COUNTER2_LEN = 6212; // 16 +static const uint64_t SH_FLD_COUNTER3 = 6213; // 16 +static const uint64_t SH_FLD_COUNTER3_LEN = 6214; // 16 +static const uint64_t SH_FLD_COUNTERA_0 = 6215; // 2 +static const uint64_t SH_FLD_COUNTERA_0_LEN = 6216; // 2 +static const uint64_t SH_FLD_COUNTERA_1 = 6217; // 2 +static const uint64_t SH_FLD_COUNTERA_1_LEN = 6218; // 2 +static const uint64_t SH_FLD_COUNTERA_2 = 6219; // 2 +static const uint64_t SH_FLD_COUNTERA_2_LEN = 6220; // 2 +static const uint64_t SH_FLD_COUNTERA_3 = 6221; // 2 +static const uint64_t SH_FLD_COUNTERA_3_LEN = 6222; // 2 +static const uint64_t SH_FLD_COUNTERB_0 = 6223; // 2 +static const uint64_t SH_FLD_COUNTERB_0_LEN = 6224; // 2 +static const uint64_t SH_FLD_COUNTERB_1 = 6225; // 2 +static const uint64_t SH_FLD_COUNTERB_1_LEN = 6226; // 2 +static const uint64_t SH_FLD_COUNTERB_2 = 6227; // 2 +static const uint64_t SH_FLD_COUNTERB_2_LEN = 6228; // 2 +static const uint64_t SH_FLD_COUNTERB_3 = 6229; // 2 +static const uint64_t SH_FLD_COUNTERB_3_LEN = 6230; // 2 +static const uint64_t SH_FLD_COUNTER_LEN = 6231; // 43 +static const uint64_t SH_FLD_COUNTER_LOAD_FLAG = 6232; // 2 +static const uint64_t SH_FLD_COUNTER_LOAD_VALUE = 6233; // 2 +static const uint64_t SH_FLD_COUNTER_LOAD_VALUE_LEN = 6234; // 2 +static const uint64_t SH_FLD_COUNTER_VALUE = 6235; // 1 +static const uint64_t SH_FLD_COUNTER_VALUE_LEN = 6236; // 1 +static const uint64_t SH_FLD_COUNT_0_47 = 6237; // 7 +static const uint64_t SH_FLD_COUNT_0_47_LEN = 6238; // 7 +static const uint64_t SH_FLD_COUNT_47 = 6239; // 1 +static const uint64_t SH_FLD_COUNT_47_LEN = 6240; // 1 +static const uint64_t SH_FLD_COUNT_LEN = 6241; // 44 +static const uint64_t SH_FLD_COUNT_STATE_ERR_HOLD = 6242; // 43 +static const uint64_t SH_FLD_COUNT_STATE_LT = 6243; // 43 +static const uint64_t SH_FLD_COUNT_STATE_LT_LEN = 6244; // 43 +static const uint64_t SH_FLD_COUNT_STATE_MASK = 6245; // 43 +static const uint64_t SH_FLD_COURSE_DIR_FLUSH_FAILED = 6246; // 2 +static const uint64_t SH_FLD_CO_CRESP_ACK_DEAD = 6247; // 12 +static const uint64_t SH_FLD_CO_DROP_COUNTER_FULL = 6248; // 4 +static const uint64_t SH_FLD_CO_MACHINE_HANG = 6249; // 12 +static const uint64_t SH_FLD_CO_PROT_ERR_CHK_DIS = 6250; // 1 +static const uint64_t SH_FLD_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR = 6251; // 12 +static const uint64_t SH_FLD_CO_SM_CTL_ERR_DET = 6252; // 1 +static const uint64_t SH_FLD_CO_TIMEOUT_CHK_DIS = 6253; // 1 +static const uint64_t SH_FLD_CO_TIMEOUT_ERR_DET = 6254; // 1 +static const uint64_t SH_FLD_CO_UNSOLICITED_CRESP = 6255; // 12 +static const uint64_t SH_FLD_CP = 6256; // 2 +static const uint64_t SH_FLD_CP0_LXSTOP_ERR_DET = 6257; // 1 +static const uint64_t SH_FLD_CP1_LXSTOP_ERR_DET = 6258; // 1 +static const uint64_t SH_FLD_CPG = 6259; // 8 +static const uint64_t SH_FLD_CPHA = 6260; // 1 +static const uint64_t SH_FLD_CPISEL = 6261; // 20 +static const uint64_t SH_FLD_CPISEL_LEN = 6262; // 20 +static const uint64_t SH_FLD_CPI_TYPE = 6263; // 12 +static const uint64_t SH_FLD_CPI_TYPE_LEN = 6264; // 12 +static const uint64_t SH_FLD_CPLITE = 6265; // 2 +static const uint64_t SH_FLD_CPLITE_LEN = 6266; // 2 +static const uint64_t SH_FLD_CPLTMASK0 = 6267; // 43 +static const uint64_t SH_FLD_CPLTMASK0_LEN = 6268; // 43 +static const uint64_t SH_FLD_CPLT_DCTRL = 6269; // 43 +static const uint64_t SH_FLD_CPLT_RCTRL = 6270; // 43 +static const uint64_t SH_FLD_CPMC1SEL = 6271; // 24 +static const uint64_t SH_FLD_CPMC1SEL_LEN = 6272; // 24 +static const uint64_t SH_FLD_CPMC2SEL = 6273; // 24 +static const uint64_t SH_FLD_CPMC2SEL_LEN = 6274; // 24 +static const uint64_t SH_FLD_CPMC_LOAD = 6275; // 24 +static const uint64_t SH_FLD_CPMC_LOAD_LEN = 6276; // 24 +static const uint64_t SH_FLD_CPM_CAL_SET = 6277; // 43 +static const uint64_t SH_FLD_CPOL = 6278; // 1 +static const uint64_t SH_FLD_CPS = 6279; // 1 +static const uint64_t SH_FLD_CPS_LEN = 6280; // 1 +static const uint64_t SH_FLD_CP_LEN = 6281; // 2 +static const uint64_t SH_FLD_CP_RETRY_THRESH = 6282; // 4 +static const uint64_t SH_FLD_CP_RETRY_THRESH_LEN = 6283; // 4 +static const uint64_t SH_FLD_CQ_CERR_BIT10 = 6284; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT11 = 6285; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT12 = 6286; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT13 = 6287; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT14 = 6288; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT15 = 6289; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT16 = 6290; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT17 = 6291; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT18 = 6292; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT19 = 6293; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT20 = 6294; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT21 = 6295; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT22 = 6296; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT23 = 6297; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT24 = 6298; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT25 = 6299; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT26 = 6300; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT27 = 6301; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT28 = 6302; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT29 = 6303; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT30 = 6304; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT31 = 6305; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT32 = 6306; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT33 = 6307; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT34 = 6308; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT35 = 6309; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT36 = 6310; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT37 = 6311; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT38 = 6312; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT39 = 6313; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT4 = 6314; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT5 = 6315; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT6 = 6316; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT7 = 6317; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT8 = 6318; // 1 +static const uint64_t SH_FLD_CQ_CERR_BIT9 = 6319; // 1 +static const uint64_t SH_FLD_CQ_CERR_RESET = 6320; // 1 +static const uint64_t SH_FLD_CQ_DRAIN_THRESHOLD = 6321; // 1 +static const uint64_t SH_FLD_CQ_DRAIN_THRESHOLD_LEN = 6322; // 1 +static const uint64_t SH_FLD_CQ_ECC_CE_ERROR = 6323; // 2 +static const uint64_t SH_FLD_CQ_ECC_SUE_ERROR = 6324; // 2 +static const uint64_t SH_FLD_CQ_ECC_UE_ERROR = 6325; // 2 +static const uint64_t SH_FLD_CQ_FILL_THRESHOLD = 6326; // 1 +static const uint64_t SH_FLD_CQ_FILL_THRESHOLD_LEN = 6327; // 1 +static const uint64_t SH_FLD_CQ_LFSR_RESEED_EN = 6328; // 1 +static const uint64_t SH_FLD_CQ_LOGIC_HW_ERROR = 6329; // 2 +static const uint64_t SH_FLD_CQ_PB_LINK_ABORT = 6330; // 2 +static const uint64_t SH_FLD_CQ_PB_MASTER_FSM_HANG = 6331; // 2 +static const uint64_t SH_FLD_CQ_PB_OB_CE_ERROR = 6332; // 2 +static const uint64_t SH_FLD_CQ_PB_OB_UE_ERROR = 6333; // 2 +static const uint64_t SH_FLD_CQ_PB_PARITY_ERROR = 6334; // 2 +static const uint64_t SH_FLD_CQ_PB_RD_ADDR_ERROR = 6335; // 2 +static const uint64_t SH_FLD_CQ_PB_RD_LINK_ERROR = 6336; // 2 +static const uint64_t SH_FLD_CQ_PB_WR_ADDR_ERROR = 6337; // 2 +static const uint64_t SH_FLD_CQ_PB_WR_LINK_ERROR = 6338; // 2 +static const uint64_t SH_FLD_CQ_READ_RTY_RATIO = 6339; // 1 +static const uint64_t SH_FLD_CQ_READ_RTY_RATIO_LEN = 6340; // 1 +static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI = 6341; // 1 +static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN = 6342; // 1 +static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO = 6343; // 1 +static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN = 6344; // 1 +static const uint64_t SH_FLD_CQ_TRACE_INT_DATA_HI = 6345; // 1 +static const uint64_t SH_FLD_CQ_TRACE_INT_DATA_LO = 6346; // 1 +static const uint64_t SH_FLD_CQ_TRACE_INT_TRIG_01 = 6347; // 1 +static const uint64_t SH_FLD_CQ_TRACE_INT_TRIG_23 = 6348; // 1 +static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01 = 6349; // 1 +static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN = 6350; // 1 +static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23 = 6351; // 1 +static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN = 6352; // 1 +static const uint64_t SH_FLD_CR0_ATAG_PERR = 6353; // 1 +static const uint64_t SH_FLD_CR0_TTAG_PERR = 6354; // 1 +static const uint64_t SH_FLD_CR1_ATAG_PERR = 6355; // 1 +static const uint64_t SH_FLD_CR1_TTAG_PERR = 6356; // 1 +static const uint64_t SH_FLD_CR2_ATAG_PERR = 6357; // 1 +static const uint64_t SH_FLD_CR2_TTAG_PERR = 6358; // 1 +static const uint64_t SH_FLD_CR3_ATAG_PERR = 6359; // 1 +static const uint64_t SH_FLD_CR3_TTAG_PERR = 6360; // 1 +static const uint64_t SH_FLD_CRB_ECC_SUE = 6361; // 1 +static const uint64_t SH_FLD_CRB_ECC_UE = 6362; // 1 +static const uint64_t SH_FLD_CRB_READS_ENBL = 6363; // 1 +static const uint64_t SH_FLD_CRB_READS_HALTED = 6364; // 1 +static const uint64_t SH_FLD_CRC_ERROR_COUNT = 6365; // 27 +static const uint64_t SH_FLD_CRC_ERROR_COUNT_LEN = 6366; // 27 +static const uint64_t SH_FLD_CRC_ERR_CTR = 6367; // 2 +static const uint64_t SH_FLD_CRC_ERR_CTR_LEN = 6368; // 2 +static const uint64_t SH_FLD_CRC_LANE_ID = 6369; // 5 +static const uint64_t SH_FLD_CRC_MODE = 6370; // 2 +static const uint64_t SH_FLD_CRD_INIT_REQUEST = 6371; // 1 +static const uint64_t SH_FLD_CRD_REQUEST = 6372; // 1 +static const uint64_t SH_FLD_CREDIT_CUR = 6373; // 36 +static const uint64_t SH_FLD_CREDIT_CUR_LEN = 6374; // 36 +static const uint64_t SH_FLD_CREDIT_MAX = 6375; // 36 +static const uint64_t SH_FLD_CREDIT_MAX_LEN = 6376; // 36 +static const uint64_t SH_FLD_CREDIT_RCV_CUR = 6377; // 12 +static const uint64_t SH_FLD_CREDIT_RCV_CUR_LEN = 6378; // 12 +static const uint64_t SH_FLD_CREDIT_RCV_UPD = 6379; // 12 +static const uint64_t SH_FLD_CREDIT_SEND = 6380; // 36 +static const uint64_t SH_FLD_CREDIT_SEND_LEN = 6381; // 36 +static const uint64_t SH_FLD_CREDIT_TIMEOUT_ERRHOLD = 6382; // 2 +static const uint64_t SH_FLD_CREDIT_UPD = 6383; // 36 +static const uint64_t SH_FLD_CREDIT_UPDATE_PENDING = 6384; // 6 +static const uint64_t SH_FLD_CREQ0 = 6385; // 12 +static const uint64_t SH_FLD_CREQ1 = 6386; // 12 +static const uint64_t SH_FLD_CREQ_AE_ALWAYS = 6387; // 6 +static const uint64_t SH_FLD_CREQ_BE_128 = 6388; // 6 +static const uint64_t SH_FLD_CRESP = 6389; // 24 +static const uint64_t SH_FLD_CRESP_0_4 = 6390; // 1 +static const uint64_t SH_FLD_CRESP_0_4_LEN = 6391; // 1 +static const uint64_t SH_FLD_CRESP_ADDR = 6392; // 2 +static const uint64_t SH_FLD_CRESP_ADDR_ERROR = 6393; // 2 +static const uint64_t SH_FLD_CRESP_ERROR = 6394; // 2 +static const uint64_t SH_FLD_CRESP_HANG = 6395; // 1 +static const uint64_t SH_FLD_CRESP_LEN = 6396; // 24 +static const uint64_t SH_FLD_CRITICAL_INTERRUPT = 6397; // 1 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_A = 6398; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN = 6399; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B = 6400; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN = 6401; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_A = 6402; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_A_LEN = 6403; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_B = 6404; // 86 +static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_B_LEN = 6405; // 86 +static const uint64_t SH_FLD_CRSP0_REGS_ATAG_PERR = 6406; // 2 +static const uint64_t SH_FLD_CRSP0_REGS_CE_ERR = 6407; // 2 +static const uint64_t SH_FLD_CRSP0_REGS_TTAG_PERR = 6408; // 2 +static const uint64_t SH_FLD_CRSP0_REGS_UE_ERR = 6409; // 2 +static const uint64_t SH_FLD_CRSP1_REGS_ATAG_PERR = 6410; // 2 +static const uint64_t SH_FLD_CRSP1_REGS_CE_ERR = 6411; // 2 +static const uint64_t SH_FLD_CRSP1_REGS_TTAG_PERR = 6412; // 2 +static const uint64_t SH_FLD_CRSP1_REGS_UE_ERR = 6413; // 2 +static const uint64_t SH_FLD_CRSP2_REGS_ATAG_PERR = 6414; // 2 +static const uint64_t SH_FLD_CRSP2_REGS_CE_ERR = 6415; // 2 +static const uint64_t SH_FLD_CRSP2_REGS_TTAG_PERR = 6416; // 2 +static const uint64_t SH_FLD_CRSP2_REGS_UE_ERR = 6417; // 2 +static const uint64_t SH_FLD_CRSP3_REGS_ATAG_PERR = 6418; // 2 +static const uint64_t SH_FLD_CRSP3_REGS_CE_ERR = 6419; // 2 +static const uint64_t SH_FLD_CRSP3_REGS_TTAG_PERR = 6420; // 2 +static const uint64_t SH_FLD_CRSP3_REGS_UE_ERR = 6421; // 2 +static const uint64_t SH_FLD_CR_ATAG_PAR = 6422; // 1 +static const uint64_t SH_FLD_CR_TTAG_PAR = 6423; // 1 +static const uint64_t SH_FLD_CS = 6424; // 6 +static const uint64_t SH_FLD_CS0_INIT_CAL_VALUE = 6425; // 8 +static const uint64_t SH_FLD_CS1_INIT_CAL_VALUE = 6426; // 8 +static const uint64_t SH_FLD_CS2_INIT_CAL_VALUE = 6427; // 8 +static const uint64_t SH_FLD_CS3_INIT_CAL_VALUE = 6428; // 8 +static const uint64_t SH_FLD_CS4_INIT_CAL_VALUE = 6429; // 8 +static const uint64_t SH_FLD_CS5_INIT_CAL_VALUE = 6430; // 8 +static const uint64_t SH_FLD_CS6_INIT_CAL_VALUE = 6431; // 8 +static const uint64_t SH_FLD_CS7_INIT_CAL_VALUE = 6432; // 8 +static const uint64_t SH_FLD_CSEL = 6433; // 10 +static const uint64_t SH_FLD_CSEL_LEN = 6434; // 10 +static const uint64_t SH_FLD_CS_LEN = 6435; // 6 +static const uint64_t SH_FLD_CTL = 6436; // 1 +static const uint64_t SH_FLD_CTLE_GAIN_MAX = 6437; // 6 +static const uint64_t SH_FLD_CTLE_GAIN_MAX_LEN = 6438; // 6 +static const uint64_t SH_FLD_CTLE_UPDATE_MODE = 6439; // 6 +static const uint64_t SH_FLD_CTLR_HP_THRESH = 6440; // 3 +static const uint64_t SH_FLD_CTLR_HP_THRESH_LEN = 6441; // 3 +static const uint64_t SH_FLD_CTLW_HP_THRESH = 6442; // 3 +static const uint64_t SH_FLD_CTLW_HP_THRESH_LEN = 6443; // 3 +static const uint64_t SH_FLD_CTL_ARRAY_CE = 6444; // 1 +static const uint64_t SH_FLD_CTL_ARRAY_UE = 6445; // 1 +static const uint64_t SH_FLD_CTL_CLKDIST_PDWN = 6446; // 6 +static const uint64_t SH_FLD_CTL_FWD_PROGRESS_ERR = 6447; // 1 +static const uint64_t SH_FLD_CTL_LEN = 6448; // 1 +static const uint64_t SH_FLD_CTL_LOGIC_ERR = 6449; // 1 +static const uint64_t SH_FLD_CTL_MMIO_ST_DATA_UE = 6450; // 1 +static const uint64_t SH_FLD_CTL_NVL_CFG_ERR = 6451; // 1 +static const uint64_t SH_FLD_CTL_NVL_FATAL_ERR = 6452; // 1 +static const uint64_t SH_FLD_CTL_PBUS_CONFIG_ERR = 6453; // 1 +static const uint64_t SH_FLD_CTL_PBUS_FATAL_ERR = 6454; // 1 +static const uint64_t SH_FLD_CTL_PBUS_PERR = 6455; // 1 +static const uint64_t SH_FLD_CTL_PBUS_RECOV_ERR = 6456; // 1 +static const uint64_t SH_FLD_CTL_PEF = 6457; // 1 +static const uint64_t SH_FLD_CTL_PEST_DIS = 6458; // 1 +static const uint64_t SH_FLD_CTL_RING_ERR = 6459; // 1 +static const uint64_t SH_FLD_CTL_RSVD_15 = 6460; // 1 +static const uint64_t SH_FLD_CTL_SM_0 = 6461; // 6 +static const uint64_t SH_FLD_CTL_SM_1 = 6462; // 6 +static const uint64_t SH_FLD_CTL_SM_2 = 6463; // 6 +static const uint64_t SH_FLD_CTL_SM_3 = 6464; // 6 +static const uint64_t SH_FLD_CTL_SM_4 = 6465; // 6 +static const uint64_t SH_FLD_CTL_SM_5 = 6466; // 6 +static const uint64_t SH_FLD_CTL_SM_6 = 6467; // 6 +static const uint64_t SH_FLD_CTL_SM_7 = 6468; // 6 +static const uint64_t SH_FLD_CTL_TICK = 6469; // 12 +static const uint64_t SH_FLD_CTL_TICK_LEN = 6470; // 12 +static const uint64_t SH_FLD_CTL_TRACE_EN = 6471; // 1 +static const uint64_t SH_FLD_CTL_TRACE_SEL = 6472; // 1 +static const uint64_t SH_FLD_CTR = 6473; // 104 +static const uint64_t SH_FLD_CTRLR_PERR_ESR = 6474; // 1 +static const uint64_t SH_FLD_CTRL_BUSY = 6475; // 1 +static const uint64_t SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC = 6476; // 43 +static const uint64_t SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC = 6477; // 43 +static const uint64_t SH_FLD_CTRL_CC_DCTEST_DC = 6478; // 43 +static const uint64_t SH_FLD_CTRL_CC_FLUSHMODE_INH_DC = 6479; // 43 +static const uint64_t SH_FLD_CTRL_CC_FORCE_ALIGN_DC = 6480; // 43 +static const uint64_t SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 6481; // 43 +static const uint64_t SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC = 6482; // 43 +static const uint64_t SH_FLD_CTRL_CC_OTP_PRGMODE_DC = 6483; // 43 +static const uint64_t SH_FLD_CTRL_CC_PIN_LBIST_DC = 6484; // 43 +static const uint64_t SH_FLD_CTRL_CC_SCAN_PROTECT_DC = 6485; // 43 +static const uint64_t SH_FLD_CTRL_CC_SDIS_DC_N = 6486; // 43 +static const uint64_t SH_FLD_CTRL_CC_SSS_CALIBRATE_DC = 6487; // 43 +static const uint64_t SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 6488; // 43 +static const uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC = 6489; // 43 +static const uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN = 6490; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC = 6491; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN = 6492; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC = 6493; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN = 6494; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC = 6495; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN = 6496; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC = 6497; // 43 +static const uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN = 6498; // 43 +static const uint64_t SH_FLD_CTRL_PARITY = 6499; // 43 +static const uint64_t SH_FLD_CTR_LEN = 6500; // 96 +static const uint64_t SH_FLD_CTR_VREF_COUNTER_RESET_VAL = 6501; // 8 +static const uint64_t SH_FLD_CTR_VREF_COUNTER_RESET_VAL_LEN = 6502; // 8 +static const uint64_t SH_FLD_CT_COMPARE_VECTOR = 6503; // 2 +static const uint64_t SH_FLD_CT_COMPARE_VECTOR_LEN = 6504; // 2 +static const uint64_t SH_FLD_CURRENT_OPCG_MODE = 6505; // 43 +static const uint64_t SH_FLD_CURRENT_OPCG_MODE_LEN = 6506; // 43 +static const uint64_t SH_FLD_CUR_RD_ADDR = 6507; // 6 +static const uint64_t SH_FLD_CUR_RD_ADDR_LEN = 6508; // 6 +static const uint64_t SH_FLD_CUSTOM_INIT_WRITE = 6509; // 8 +static const uint64_t SH_FLD_CUSTOM_RD = 6510; // 8 +static const uint64_t SH_FLD_CUSTOM_WR = 6511; // 8 +static const uint64_t SH_FLD_CW_MIRROR = 6512; // 8 +static const uint64_t SH_FLD_CW_TYPE = 6513; // 12 +static const uint64_t SH_FLD_CW_TYPE_LEN = 6514; // 12 +static const uint64_t SH_FLD_CXACQPB_MUX_ECC_CE_ERRHOLD = 6515; // 2 +static const uint64_t SH_FLD_CXACQPB_MUX_ECC_UE_ERRHOLD = 6516; // 2 +static const uint64_t SH_FLD_CYCLECNT = 6517; // 3 +static const uint64_t SH_FLD_CYCLECNT_LEN = 6518; // 3 +static const uint64_t SH_FLD_CYCLES = 6519; // 12 +static const uint64_t SH_FLD_CYCLES_LEN = 6520; // 12 +static const uint64_t SH_FLD_CYCLE_COUNT = 6521; // 24 +static const uint64_t SH_FLD_CYCLE_COUNT_LEN = 6522; // 24 +static const uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA = 6523; // 2 +static const uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA_LEN = 6524; // 2 +static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 6525; // 4 +static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 6526; // 4 +static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 6527; // 4 +static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 6528; // 4 +static const uint64_t SH_FLD_DACTEST_HLMT = 6529; // 6 +static const uint64_t SH_FLD_DACTEST_HLMT_LEN = 6530; // 6 +static const uint64_t SH_FLD_DACTEST_LLMT = 6531; // 6 +static const uint64_t SH_FLD_DACTEST_LLMT_LEN = 6532; // 6 +static const uint64_t SH_FLD_DACTEST_RESET = 6533; // 6 +static const uint64_t SH_FLD_DACTEST_START = 6534; // 6 +static const uint64_t SH_FLD_DAC_BO_CFG = 6535; // 6 +static const uint64_t SH_FLD_DAC_BO_CFG_LEN = 6536; // 6 +static const uint64_t SH_FLD_DARN_ADDR_ERR = 6537; // 12 +static const uint64_t SH_FLD_DARN_DATA_TIMEOUT = 6538; // 12 +static const uint64_t SH_FLD_DARN_EN_ERR = 6539; // 12 +static const uint64_t SH_FLD_DAT0 = 6540; // 1 +static const uint64_t SH_FLD_DAT0_LEN = 6541; // 1 +static const uint64_t SH_FLD_DAT1 = 6542; // 1 +static const uint64_t SH_FLD_DAT1_LEN = 6543; // 1 +static const uint64_t SH_FLD_DATA = 6544; // 665 +static const uint64_t SH_FLD_DATA0 = 6545; // 6 +static const uint64_t SH_FLD_DATA0_LEN = 6546; // 6 +static const uint64_t SH_FLD_DATA1 = 6547; // 6 +static const uint64_t SH_FLD_DATA1_LEN = 6548; // 6 +static const uint64_t SH_FLD_DATA2 = 6549; // 6 +static const uint64_t SH_FLD_DATA2_LEN = 6550; // 6 +static const uint64_t SH_FLD_DATA_0_63 = 6551; // 2 +static const uint64_t SH_FLD_DATA_0_63_LEN = 6552; // 2 +static const uint64_t SH_FLD_DATA_64_79 = 6553; // 2 +static const uint64_t SH_FLD_DATA_64_79_LEN = 6554; // 2 +static const uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG = 6555; // 1 +static const uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG_LEN = 6556; // 1 +static const uint64_t SH_FLD_DATA_BUFF0 = 6557; // 2 +static const uint64_t SH_FLD_DATA_BUFF0_LEN = 6558; // 2 +static const uint64_t SH_FLD_DATA_BUFF1 = 6559; // 2 +static const uint64_t SH_FLD_DATA_BUFF1_LEN = 6560; // 2 +static const uint64_t SH_FLD_DATA_BUFFER = 6561; // 43 +static const uint64_t SH_FLD_DATA_BYTES = 6562; // 32 +static const uint64_t SH_FLD_DATA_BYTES_LEN = 6563; // 32 +static const uint64_t SH_FLD_DATA_COMPARE_BURST_SEL = 6564; // 2 +static const uint64_t SH_FLD_DATA_COMPARE_BURST_SEL_LEN = 6565; // 2 +static const uint64_t SH_FLD_DATA_DLY = 6566; // 1 +static const uint64_t SH_FLD_DATA_DLY_LEN = 6567; // 1 +static const uint64_t SH_FLD_DATA_HANG_DETECT = 6568; // 4 +static const uint64_t SH_FLD_DATA_HANG_DETECTED = 6569; // 2 +static const uint64_t SH_FLD_DATA_HANG_POLL_SCALE = 6570; // 2 +static const uint64_t SH_FLD_DATA_HANG_POLL_SCALE_LEN = 6571; // 2 +static const uint64_t SH_FLD_DATA_LEN = 6572; // 665 +static const uint64_t SH_FLD_DATA_MUX4_1MODE = 6573; // 8 +static const uint64_t SH_FLD_DATA_PARITY_ERR = 6574; // 4 +static const uint64_t SH_FLD_DATA_PIPE_CLR_ON_READ_MODE = 6575; // 6 +static const uint64_t SH_FLD_DATA_POISON_SUE_ENA = 6576; // 6 +static const uint64_t SH_FLD_DATA_POLL_PULSE_DIV = 6577; // 12 +static const uint64_t SH_FLD_DATA_POLL_PULSE_DIV_LEN = 6578; // 12 +static const uint64_t SH_FLD_DATA_REG0 = 6579; // 8 +static const uint64_t SH_FLD_DATA_REG0_LEN = 6580; // 8 +static const uint64_t SH_FLD_DATA_REG1 = 6581; // 8 +static const uint64_t SH_FLD_DATA_REG1_LEN = 6582; // 8 +static const uint64_t SH_FLD_DATA_REG_0_31 = 6583; // 1 +static const uint64_t SH_FLD_DATA_REG_0_31_LEN = 6584; // 1 +static const uint64_t SH_FLD_DATA_REQ = 6585; // 1 +static const uint64_t SH_FLD_DATA_REQUEST_0 = 6586; // 4 +static const uint64_t SH_FLD_DATA_REQUEST_1 = 6587; // 2 +static const uint64_t SH_FLD_DATA_REQUEST_2 = 6588; // 2 +static const uint64_t SH_FLD_DATA_REQUEST_3 = 6589; // 2 +static const uint64_t SH_FLD_DATA_ROUTE_ERROR = 6590; // 2 +static const uint64_t SH_FLD_DATA_RTAG_P = 6591; // 12 +static const uint64_t SH_FLD_DATA_SEL = 6592; // 1 +static const uint64_t SH_FLD_DATA_V_LT = 6593; // 43 +static const uint64_t SH_FLD_DAT_ARR_ECC_CORR_ENA = 6594; // 6 +static const uint64_t SH_FLD_DAT_ARR_ECC_SUE_ENA = 6595; // 6 +static const uint64_t SH_FLD_DAT_BUFFER_PAR_ERR = 6596; // 4 +static const uint64_t SH_FLD_DAT_CREG_PERR = 6597; // 1 +static const uint64_t SH_FLD_DAT_DATA_BE_CE = 6598; // 1 +static const uint64_t SH_FLD_DAT_DATA_BE_PERR = 6599; // 1 +static const uint64_t SH_FLD_DAT_DATA_BE_SUE = 6600; // 1 +static const uint64_t SH_FLD_DAT_DATA_BE_UE = 6601; // 1 +static const uint64_t SH_FLD_DAT_LOGIC_ERR = 6602; // 1 +static const uint64_t SH_FLD_DAT_PBRX_SUE = 6603; // 1 +static const uint64_t SH_FLD_DAT_RSVD_10 = 6604; // 1 +static const uint64_t SH_FLD_DAT_RSVD_9 = 6605; // 1 +static const uint64_t SH_FLD_DAT_RTAG_PERR = 6606; // 1 +static const uint64_t SH_FLD_DAT_STATE_PERR = 6607; // 1 +static const uint64_t SH_FLD_DBG_BUS0_STG0_SEL = 6608; // 2 +static const uint64_t SH_FLD_DBG_BUS0_STG0_SEL_LEN = 6609; // 2 +static const uint64_t SH_FLD_DBG_BUS1_STG0_SEL = 6610; // 2 +static const uint64_t SH_FLD_DBG_BUS1_STG0_SEL_LEN = 6611; // 2 +static const uint64_t SH_FLD_DBG_BUS_BIT = 6612; // 8 +static const uint64_t SH_FLD_DBG_CC_ERROR = 6613; // 1 +static const uint64_t SH_FLD_DBG_CHIPLET_IS_ALIGNED = 6614; // 1 +static const uint64_t SH_FLD_DBG_CLR_MAX_HANG_STAGE = 6615; // 3 +static const uint64_t SH_FLD_DBG_CMD = 6616; // 1 +static const uint64_t SH_FLD_DBG_CMD_LEN = 6617; // 1 +static const uint64_t SH_FLD_DBG_CTL_REG_PARITY_ERRHOLD = 6618; // 2 +static const uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE = 6619; // 1 +static const uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE_LEN = 6620; // 1 +static const uint64_t SH_FLD_DBG_HALT = 6621; // 1 +static const uint64_t SH_FLD_DBG_LAST_OPCG_MODE = 6622; // 1 +static const uint64_t SH_FLD_DBG_LAST_OPCG_MODE_LEN = 6623; // 1 +static const uint64_t SH_FLD_DBG_LEVEL = 6624; // 1 +static const uint64_t SH_FLD_DBG_LEVEL_LEN = 6625; // 1 +static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS0 = 6626; // 1 +static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS0_LEN = 6627; // 1 +static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS1 = 6628; // 1 +static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS1_LEN = 6629; // 1 +static const uint64_t SH_FLD_DBG_OPCG_IP = 6630; // 1 +static const uint64_t SH_FLD_DBG_PARANOIA_TEST_ENABLE_CHANGE = 6631; // 1 +static const uint64_t SH_FLD_DBG_PARANOIA_VITL_CLKOFF_CHANGE = 6632; // 1 +static const uint64_t SH_FLD_DBG_PARITY_ERROR = 6633; // 1 +static const uint64_t SH_FLD_DBG_PCB_ERROR = 6634; // 1 +static const uint64_t SH_FLD_DBG_PCB_IDLE = 6635; // 1 +static const uint64_t SH_FLD_DBG_PCB_REQUEST_SINCE_RESET = 6636; // 1 +static const uint64_t SH_FLD_DBG_PROTOCOL_ERROR = 6637; // 1 +static const uint64_t SH_FLD_DBG_REQ = 6638; // 1 +static const uint64_t SH_FLD_DBG_RESET_EP = 6639; // 1 +static const uint64_t SH_FLD_DBG_SECURITY_DEBUG_MODE = 6640; // 1 +static const uint64_t SH_FLD_DBG_SEL_IN = 6641; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWCTL_DEBUG = 6642; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 = 6643; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 = 6644; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 = 6645; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 = 6646; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 = 6647; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 = 6648; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 = 6649; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 = 6650; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 = 6651; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 = 6652; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 = 6653; // 8 +static const uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 = 6654; // 8 +static const uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 = 6655; // 8 +static const uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 = 6656; // 8 +static const uint64_t SH_FLD_DBG_SEL_WDF = 6657; // 8 +static const uint64_t SH_FLD_DBG_SEL_WDFMGR_DEBUG = 6658; // 8 +static const uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_0 = 6659; // 8 +static const uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_1 = 6660; // 8 +static const uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_0 = 6661; // 8 +static const uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_1 = 6662; // 8 +static const uint64_t SH_FLD_DBG_SPARE = 6663; // 8 +static const uint64_t SH_FLD_DBG_SPARE_LEN = 6664; // 8 +static const uint64_t SH_FLD_DBG_SPARE_MCA = 6665; // 8 +static const uint64_t SH_FLD_DBG_SPARE_MCA_LEN = 6666; // 8 +static const uint64_t SH_FLD_DBG_SPARE_NEST = 6667; // 8 +static const uint64_t SH_FLD_DBG_SPARE_NEST_LEN = 6668; // 8 +static const uint64_t SH_FLD_DBG_STATE = 6669; // 1 +static const uint64_t SH_FLD_DBG_STATE_LEN = 6670; // 1 +static const uint64_t SH_FLD_DBG_TEST_ENABLE = 6671; // 1 +static const uint64_t SH_FLD_DBG_THRDID = 6672; // 1 +static const uint64_t SH_FLD_DBG_THRDID_LEN = 6673; // 1 +static const uint64_t SH_FLD_DBG_THRDID_MASK = 6674; // 1 +static const uint64_t SH_FLD_DBG_THRDID_MASK_LEN = 6675; // 1 +static const uint64_t SH_FLD_DBG_TP_TPFSI_ACK = 6676; // 1 +static const uint64_t SH_FLD_DBG_UNCONDITIONAL_EVENT = 6677; // 1 +static const uint64_t SH_FLD_DBG_VITL_CLKOFF = 6678; // 1 +static const uint64_t SH_FLD_DBG_VLD = 6679; // 1 +static const uint64_t SH_FLD_DBLERR = 6680; // 2 +static const uint64_t SH_FLD_DCACHE_ERR = 6681; // 4 +static const uint64_t SH_FLD_DCACHE_MODE = 6682; // 2 +static const uint64_t SH_FLD_DCACHE_POPULATE_PENDING = 6683; // 4 +static const uint64_t SH_FLD_DCACHE_REPORTS_PHYSICAL = 6684; // 2 +static const uint64_t SH_FLD_DCACHE_TAG_ADDR = 6685; // 4 +static const uint64_t SH_FLD_DCACHE_TAG_ADDR_LEN = 6686; // 4 +static const uint64_t SH_FLD_DCACHE_VALID = 6687; // 4 +static const uint64_t SH_FLD_DCACHE_VALID_LEN = 6688; // 4 +static const uint64_t SH_FLD_DCADJ_DCS_CHOP_INT = 6689; // 36 +static const uint64_t SH_FLD_DCADJ_DCS_POL_INT = 6690; // 36 +static const uint64_t SH_FLD_DCC_CHANGE = 6691; // 36 +static const uint64_t SH_FLD_DCC_CHANGE_LEN = 6692; // 36 +static const uint64_t SH_FLD_DCC_LOCK_SIGNAL = 6693; // 36 +static const uint64_t SH_FLD_DCC_OVERFLOW_SIGNAL = 6694; // 36 +static const uint64_t SH_FLD_DCC_UNDERFLOW_SIGNAL = 6695; // 36 +static const uint64_t SH_FLD_DCLKSEL = 6696; // 6 +static const uint64_t SH_FLD_DCLKSEL_LEN = 6697; // 6 +static const uint64_t SH_FLD_DCOMP_ENABLE = 6698; // 1 +static const uint64_t SH_FLD_DCOMP_ENGINE_BUSY = 6699; // 1 +static const uint64_t SH_FLD_DCOMP_ERR = 6700; // 1 +static const uint64_t SH_FLD_DCO_DECR = 6701; // 6 +static const uint64_t SH_FLD_DCO_INCR = 6702; // 6 +static const uint64_t SH_FLD_DCO_OVERRIDE = 6703; // 6 +static const uint64_t SH_FLD_DCS_DCADJ_SENSE_INT = 6704; // 36 +static const uint64_t SH_FLD_DCU_RNW = 6705; // 1 +static const uint64_t SH_FLD_DCU_TIMEOUT_ERROR = 6706; // 1 +static const uint64_t SH_FLD_DC_CALIBRATE_DONE = 6707; // 4 +static const uint64_t SH_FLD_DC_ENABLE_CM_COARSE_CAL = 6708; // 6 +static const uint64_t SH_FLD_DC_ENABLE_CM_FINE_CAL = 6709; // 6 +static const uint64_t SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 6710; // 6 +static const uint64_t SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 6711; // 6 +static const uint64_t SH_FLD_DC_ENABLE_DAC_H1_CAL = 6712; // 4 +static const uint64_t SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL = 6713; // 4 +static const uint64_t SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 6714; // 6 +static const uint64_t SH_FLD_DC_RLD_QUAL = 6715; // 96 +static const uint64_t SH_FLD_DC_T0_CLEAR_MAINT = 6716; // 24 +static const uint64_t SH_FLD_DC_T0_CORE_START = 6717; // 24 +static const uint64_t SH_FLD_DC_T0_CORE_STEP = 6718; // 24 +static const uint64_t SH_FLD_DC_T0_CORE_STOP = 6719; // 24 +static const uint64_t SH_FLD_DC_T0_SRESET_REQUEST = 6720; // 24 +static const uint64_t SH_FLD_DC_T1_CLEAR_MAINT = 6721; // 24 +static const uint64_t SH_FLD_DC_T1_CORE_START = 6722; // 24 +static const uint64_t SH_FLD_DC_T1_CORE_STEP = 6723; // 24 +static const uint64_t SH_FLD_DC_T1_CORE_STOP = 6724; // 24 +static const uint64_t SH_FLD_DC_T1_SRESET_REQUEST = 6725; // 24 +static const uint64_t SH_FLD_DC_T2_CLEAR_MAINT = 6726; // 24 +static const uint64_t SH_FLD_DC_T2_CORE_START = 6727; // 24 +static const uint64_t SH_FLD_DC_T2_CORE_STEP = 6728; // 24 +static const uint64_t SH_FLD_DC_T2_CORE_STOP = 6729; // 24 +static const uint64_t SH_FLD_DC_T2_SRESET_REQUEST = 6730; // 24 +static const uint64_t SH_FLD_DC_T3_CLEAR_MAINT = 6731; // 24 +static const uint64_t SH_FLD_DC_T3_CORE_START = 6732; // 24 +static const uint64_t SH_FLD_DC_T3_CORE_STEP = 6733; // 24 +static const uint64_t SH_FLD_DC_T3_CORE_STOP = 6734; // 24 +static const uint64_t SH_FLD_DC_T3_SRESET_REQUEST = 6735; // 24 +static const uint64_t SH_FLD_DD1_STRETCH_TRIGGER_PULSES = 6736; // 90 +static const uint64_t SH_FLD_DD2_FIX_DIS = 6737; // 8 +static const uint64_t SH_FLD_DDC_CFG = 6738; // 120 +static const uint64_t SH_FLD_DDC_CFG_LEN = 6739; // 120 +static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM = 6740; // 72 +static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN = 6741; // 72 +static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP = 6742; // 72 +static const uint64_t SH_FLD_DDR0 = 6743; // 24 +static const uint64_t SH_FLD_DDR01_PARITY_ERR = 6744; // 8 +static const uint64_t SH_FLD_DDR0_CALIBRATION_ERROR = 6745; // 8 +static const uint64_t SH_FLD_DDR0_FSM_CKSTP = 6746; // 8 +static const uint64_t SH_FLD_DDR0_FSM_ERR = 6747; // 8 +static const uint64_t SH_FLD_DDR0_LEN = 6748; // 24 +static const uint64_t SH_FLD_DDR0_PARITY_CKSTP = 6749; // 8 +static const uint64_t SH_FLD_DDR0_PARITY_ERR = 6750; // 8 +static const uint64_t SH_FLD_DDR1 = 6751; // 24 +static const uint64_t SH_FLD_DDR1_CALIBRATION_ERROR = 6752; // 8 +static const uint64_t SH_FLD_DDR1_FSM_CKSTP = 6753; // 8 +static const uint64_t SH_FLD_DDR1_FSM_ERR = 6754; // 8 +static const uint64_t SH_FLD_DDR1_LEN = 6755; // 24 +static const uint64_t SH_FLD_DDR1_PARITY_CKSTP = 6756; // 8 +static const uint64_t SH_FLD_DDR1_PARITY_ERR = 6757; // 8 +static const uint64_t SH_FLD_DDR4_CMD_SIG_REDUCTION = 6758; // 8 +static const uint64_t SH_FLD_DDR4_IPW_LOOP_DIS = 6759; // 8 +static const uint64_t SH_FLD_DDR4_LATENCY_SW = 6760; // 8 +static const uint64_t SH_FLD_DDR4_VLEVEL_BANK_GROUP = 6761; // 8 +static const uint64_t SH_FLD_DDR_ACTN = 6762; // 64 +static const uint64_t SH_FLD_DDR_ADDRESS = 6763; // 8 +static const uint64_t SH_FLD_DDR_ADDRESS_0 = 6764; // 2 +static const uint64_t SH_FLD_DDR_ADDRESS_0_13 = 6765; // 62 +static const uint64_t SH_FLD_DDR_ADDRESS_0_13_LEN = 6766; // 62 +static const uint64_t SH_FLD_DDR_ADDRESS_0_LEN = 6767; // 2 +static const uint64_t SH_FLD_DDR_ADDRESS_14 = 6768; // 62 +static const uint64_t SH_FLD_DDR_ADDRESS_15 = 6769; // 62 +static const uint64_t SH_FLD_DDR_ADDRESS_16 = 6770; // 62 +static const uint64_t SH_FLD_DDR_ADDRESS_17 = 6771; // 62 +static const uint64_t SH_FLD_DDR_BANK_0_1 = 6772; // 64 +static const uint64_t SH_FLD_DDR_BANK_0_1_LEN = 6773; // 64 +static const uint64_t SH_FLD_DDR_BANK_2 = 6774; // 64 +static const uint64_t SH_FLD_DDR_BANK_GROUP_0 = 6775; // 64 +static const uint64_t SH_FLD_DDR_BANK_GROUP_1 = 6776; // 64 +static const uint64_t SH_FLD_DDR_CALIBRATION_ENABLE = 6777; // 64 +static const uint64_t SH_FLD_DDR_CAL_RANK = 6778; // 64 +static const uint64_t SH_FLD_DDR_CAL_RANK_LEN = 6779; // 64 +static const uint64_t SH_FLD_DDR_CAL_RESET_TIMEOUT = 6780; // 16 +static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT = 6781; // 2 +static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN = 6782; // 2 +static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT = 6783; // 2 +static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 6784; // 2 +static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_ERR = 6785; // 16 +static const uint64_t SH_FLD_DDR_CAL_TYPE = 6786; // 64 +static const uint64_t SH_FLD_DDR_CAL_TYPE_LEN = 6787; // 64 +static const uint64_t SH_FLD_DDR_CID_0_1 = 6788; // 64 +static const uint64_t SH_FLD_DDR_CID_0_1_LEN = 6789; // 64 +static const uint64_t SH_FLD_DDR_CID_2 = 6790; // 64 +static const uint64_t SH_FLD_DDR_CKE = 6791; // 64 +static const uint64_t SH_FLD_DDR_CKE_LEN = 6792; // 64 +static const uint64_t SH_FLD_DDR_CSN_0_1 = 6793; // 64 +static const uint64_t SH_FLD_DDR_CSN_0_1_LEN = 6794; // 64 +static const uint64_t SH_FLD_DDR_CSN_2_3 = 6795; // 64 +static const uint64_t SH_FLD_DDR_CSN_2_3_LEN = 6796; // 64 +static const uint64_t SH_FLD_DDR_IF_SM_1HOT = 6797; // 8 +static const uint64_t SH_FLD_DDR_MBA_EVENT_N = 6798; // 16 +static const uint64_t SH_FLD_DDR_ODT = 6799; // 64 +static const uint64_t SH_FLD_DDR_ODT_LEN = 6800; // 64 +static const uint64_t SH_FLD_DDR_PARITY = 6801; // 64 +static const uint64_t SH_FLD_DDR_PARITY_ENABLE = 6802; // 2 +static const uint64_t SH_FLD_DDR_RESETN = 6803; // 64 +static const uint64_t SH_FLD_DEAD = 6804; // 43 +static const uint64_t SH_FLD_DEBUG = 6805; // 2 +static const uint64_t SH_FLD_DEBUG0_CONFIG_P = 6806; // 1 +static const uint64_t SH_FLD_DEBUG1_CONFIG_P = 6807; // 1 +static const uint64_t SH_FLD_DEBUGGER = 6808; // 25 +static const uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS = 6809; // 1 +static const uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 6810; // 1 +static const uint64_t SH_FLD_DEBUG_BUS_0_63 = 6811; // 4 +static const uint64_t SH_FLD_DEBUG_BUS_0_63_LEN = 6812; // 4 +static const uint64_t SH_FLD_DEBUG_BUS_64_87 = 6813; // 4 +static const uint64_t SH_FLD_DEBUG_BUS_64_87_LEN = 6814; // 4 +static const uint64_t SH_FLD_DEBUG_BUS_SEL = 6815; // 8 +static const uint64_t SH_FLD_DEBUG_BUS_SEL2 = 6816; // 8 +static const uint64_t SH_FLD_DEBUG_BUS_SEL2_LEN = 6817; // 8 +static const uint64_t SH_FLD_DEBUG_BUS_SEL_LEN = 6818; // 8 +static const uint64_t SH_FLD_DEBUG_COUNTER_CONTROLS = 6819; // 4 +static const uint64_t SH_FLD_DEBUG_COUNTER_CONTROLS_LEN = 6820; // 4 +static const uint64_t SH_FLD_DEBUG_COUNTER_EN = 6821; // 4 +static const uint64_t SH_FLD_DEBUG_COUNTER_RESET = 6822; // 4 +static const uint64_t SH_FLD_DEBUG_LEN = 6823; // 2 +static const uint64_t SH_FLD_DEBUG_OCI_MODE = 6824; // 1 +static const uint64_t SH_FLD_DEBUG_OCI_MODE_LEN = 6825; // 1 +static const uint64_t SH_FLD_DEBUG_PB_NOT_OCI = 6826; // 1 +static const uint64_t SH_FLD_DEBUG_TRIGGER = 6827; // 25 +static const uint64_t SH_FLD_DEC = 6828; // 2 +static const uint64_t SH_FLD_DECAY_ADDR = 6829; // 1 +static const uint64_t SH_FLD_DECAY_ADDR_COND = 6830; // 1 +static const uint64_t SH_FLD_DECAY_ADDR_COND_LEN = 6831; // 1 +static const uint64_t SH_FLD_DECAY_ADDR_LEN = 6832; // 1 +static const uint64_t SH_FLD_DECAY_SCOM_COUNT = 6833; // 1 +static const uint64_t SH_FLD_DECAY_SCOM_COUNT_LEN = 6834; // 1 +static const uint64_t SH_FLD_DECAY_SCOM_DELAY = 6835; // 1 +static const uint64_t SH_FLD_DECAY_SCOM_DELAY_LEN = 6836; // 1 +static const uint64_t SH_FLD_DECAY_SCOM_VALID = 6837; // 1 +static const uint64_t SH_FLD_DECONFIGURED_INTR = 6838; // 24 +static const uint64_t SH_FLD_DECOUPLE_EDGE_A = 6839; // 48 +static const uint64_t SH_FLD_DECOUPLE_EDGE_B = 6840; // 48 +static const uint64_t SH_FLD_DEC_EXIT_ENABLE = 6841; // 96 +static const uint64_t SH_FLD_DEC_LEN = 6842; // 2 +static const uint64_t SH_FLD_DEC_PARITY_ERROR = 6843; // 96 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP = 6844; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN = 6845; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP = 6846; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN = 6847; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC = 6848; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN = 6849; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR = 6850; // 30 +static const uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN = 6851; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP = 6852; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN = 6853; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP = 6854; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN = 6855; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC = 6856; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN = 6857; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR = 6858; // 30 +static const uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN = 6859; // 30 +static const uint64_t SH_FLD_DEF_VALUES = 6860; // 8 +static const uint64_t SH_FLD_DEF_VALUES_LEN = 6861; // 8 +static const uint64_t SH_FLD_DEGLITCH_CLK_DLY = 6862; // 1 +static const uint64_t SH_FLD_DEGLITCH_CLK_DLY_LEN = 6863; // 1 +static const uint64_t SH_FLD_DEGLITCH_DATA_DLY = 6864; // 1 +static const uint64_t SH_FLD_DEGLITCH_DATA_DLY_LEN = 6865; // 1 +static const uint64_t SH_FLD_DELAY = 6866; // 1 +static const uint64_t SH_FLD_DELAY1_ID = 6867; // 12 +static const uint64_t SH_FLD_DELAY1_ID_LEN = 6868; // 12 +static const uint64_t SH_FLD_DELAY1_VALID = 6869; // 12 +static const uint64_t SH_FLD_DELAY2_ID = 6870; // 12 +static const uint64_t SH_FLD_DELAY2_ID_LEN = 6871; // 12 +static const uint64_t SH_FLD_DELAY2_VALID = 6872; // 12 +static const uint64_t SH_FLD_DELAY3_ID = 6873; // 12 +static const uint64_t SH_FLD_DELAY3_ID_LEN = 6874; // 12 +static const uint64_t SH_FLD_DELAY3_VALID = 6875; // 12 +static const uint64_t SH_FLD_DELAY4_ID = 6876; // 12 +static const uint64_t SH_FLD_DELAY4_ID_LEN = 6877; // 12 +static const uint64_t SH_FLD_DELAY4_VALID = 6878; // 12 +static const uint64_t SH_FLD_DELAY5_ID = 6879; // 12 +static const uint64_t SH_FLD_DELAY5_ID_LEN = 6880; // 12 +static const uint64_t SH_FLD_DELAY5_VALID = 6881; // 12 +static const uint64_t SH_FLD_DELAY6_ID = 6882; // 12 +static const uint64_t SH_FLD_DELAY6_ID_LEN = 6883; // 12 +static const uint64_t SH_FLD_DELAY6_VALID = 6884; // 12 +static const uint64_t SH_FLD_DELAY7_ID = 6885; // 12 +static const uint64_t SH_FLD_DELAY7_ID_LEN = 6886; // 12 +static const uint64_t SH_FLD_DELAY7_VALID = 6887; // 12 +static const uint64_t SH_FLD_DELAY8_ID = 6888; // 12 +static const uint64_t SH_FLD_DELAY8_ID_LEN = 6889; // 12 +static const uint64_t SH_FLD_DELAY8_VALID = 6890; // 12 +static const uint64_t SH_FLD_DELAYED_PAR = 6891; // 8 +static const uint64_t SH_FLD_DELAYG = 6892; // 32 +static const uint64_t SH_FLD_DELAYG_LEN = 6893; // 32 +static const uint64_t SH_FLD_DELAY_ADJUST_DISABLE = 6894; // 1 +static const uint64_t SH_FLD_DELAY_ADJUST_VALUE = 6895; // 1 +static const uint64_t SH_FLD_DELAY_ADJUST_VALUE_LEN = 6896; // 1 +static const uint64_t SH_FLD_DELAY_AFTER_BLOCK = 6897; // 24 +static const uint64_t SH_FLD_DELAY_DISABLE = 6898; // 1 +static const uint64_t SH_FLD_DELAY_LCLKR = 6899; // 43 +static const uint64_t SH_FLD_DELAY_LEN = 6900; // 1 +static const uint64_t SH_FLD_DELAY_LINE_CTL_OVERRIDE = 6901; // 8 +static const uint64_t SH_FLD_DEQUEUED_EOT_FLAG = 6902; // 1 +static const uint64_t SH_FLD_DESKEW_BUMP_AFTER = 6903; // 4 +static const uint64_t SH_FLD_DESKEW_DONE = 6904; // 4 +static const uint64_t SH_FLD_DESKEW_FAILED = 6905; // 4 +static const uint64_t SH_FLD_DESKEW_MAXSKEW_GRP = 6906; // 4 +static const uint64_t SH_FLD_DESKEW_MAXSKEW_GRP_LEN = 6907; // 4 +static const uint64_t SH_FLD_DESKEW_MAX_LIMIT = 6908; // 4 +static const uint64_t SH_FLD_DESKEW_MAX_LIMIT_LEN = 6909; // 4 +static const uint64_t SH_FLD_DESKEW_MINSKEW_GRP = 6910; // 4 +static const uint64_t SH_FLD_DESKEW_MINSKEW_GRP_LEN = 6911; // 4 +static const uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL = 6912; // 4 +static const uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 6913; // 4 +static const uint64_t SH_FLD_DESKEW_RATE = 6914; // 8 +static const uint64_t SH_FLD_DESKEW_SEQ_GCRMSG = 6915; // 4 +static const uint64_t SH_FLD_DESKEW_SEQ_GCRMSG_LEN = 6916; // 4 +static const uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG = 6917; // 4 +static const uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG_LEN = 6918; // 4 +static const uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG = 6919; // 4 +static const uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG_LEN = 6920; // 4 +static const uint64_t SH_FLD_DEST = 6921; // 1 +static const uint64_t SH_FLD_DEST0 = 6922; // 24 +static const uint64_t SH_FLD_DEST0_LEN = 6923; // 24 +static const uint64_t SH_FLD_DEST1 = 6924; // 24 +static const uint64_t SH_FLD_DEST1_LEN = 6925; // 24 +static const uint64_t SH_FLD_DEST_CHIPID = 6926; // 1 +static const uint64_t SH_FLD_DEST_CHIPID_LEN = 6927; // 1 +static const uint64_t SH_FLD_DEST_GROUPID = 6928; // 1 +static const uint64_t SH_FLD_DEST_GROUPID_LEN = 6929; // 1 +static const uint64_t SH_FLD_DEST_LEN = 6930; // 1 +static const uint64_t SH_FLD_DETAIL = 6931; // 2 +static const uint64_t SH_FLD_DETAIL_LEN = 6932; // 2 +static const uint64_t SH_FLD_DEVICE = 6933; // 1 +static const uint64_t SH_FLD_DEVICE_ADDRESS_0 = 6934; // 2 +static const uint64_t SH_FLD_DEVICE_ADDRESS_0_LEN = 6935; // 2 +static const uint64_t SH_FLD_DEVICE_ADDRESS_1 = 6936; // 1 +static const uint64_t SH_FLD_DEVICE_ADDRESS_1_LEN = 6937; // 1 +static const uint64_t SH_FLD_DEVICE_ADDRESS_2 = 6938; // 1 +static const uint64_t SH_FLD_DEVICE_ADDRESS_2_LEN = 6939; // 1 +static const uint64_t SH_FLD_DEVICE_ADDRESS_3 = 6940; // 1 +static const uint64_t SH_FLD_DEVICE_ADDRESS_3_LEN = 6941; // 1 +static const uint64_t SH_FLD_DEVICE_ID = 6942; // 4 +static const uint64_t SH_FLD_DEVICE_ID_LEN = 6943; // 4 +static const uint64_t SH_FLD_DFE12_EN = 6944; // 4 +static const uint64_t SH_FLD_DFEHISPD_EN = 6945; // 4 +static const uint64_t SH_FLD_DFE_CA_CFG = 6946; // 6 +static const uint64_t SH_FLD_DFE_CA_CFG_LEN = 6947; // 6 +static const uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX = 6948; // 6 +static const uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX_LEN = 6949; // 6 +static const uint64_t SH_FLD_DFE_FORCE_LOAD_SEED = 6950; // 72 +static const uint64_t SH_FLD_DFE_HTAP_CFG = 6951; // 4 +static const uint64_t SH_FLD_DFE_HTAP_CFG_LEN = 6952; // 4 +static const uint64_t SH_FLD_DFE_INIT_TIMEOUT = 6953; // 4 +static const uint64_t SH_FLD_DFE_INIT_TIMEOUT_LEN = 6954; // 4 +static const uint64_t SH_FLD_DFE_RECAL_TIMEOUT = 6955; // 4 +static const uint64_t SH_FLD_DFE_RECAL_TIMEOUT_LEN = 6956; // 4 +static const uint64_t SH_FLD_DFREEZE = 6957; // 9 +static const uint64_t SH_FLD_DFREEZE_LEN = 6958; // 9 +static const uint64_t SH_FLD_DFS_SM_ERRHOLD = 6959; // 2 +static const uint64_t SH_FLD_DGD_AE_ALWAYS = 6960; // 6 +static const uint64_t SH_FLD_DGD_BE_128 = 6961; // 6 +static const uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING = 6962; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN = 6963; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_SEED0 = 6964; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_SEED0_LEN = 6965; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_SEED1 = 6966; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_SEED1_LEN = 6967; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_SEED2 = 6968; // 2 +static const uint64_t SH_FLD_DGEN_RNDD_SEED2_LEN = 6969; // 2 +static const uint64_t SH_FLD_DIAG_0 = 6970; // 2 +static const uint64_t SH_FLD_DIAG_1 = 6971; // 1 +static const uint64_t SH_FLD_DIAG_2 = 6972; // 1 +static const uint64_t SH_FLD_DIAG_3 = 6973; // 1 +static const uint64_t SH_FLD_DIB01_ERR = 6974; // 4 +static const uint64_t SH_FLD_DIB01_SPARE = 6975; // 1 +static const uint64_t SH_FLD_DIB01_SPARE_LEN = 6976; // 1 +static const uint64_t SH_FLD_DIB23_ERR = 6977; // 4 +static const uint64_t SH_FLD_DIB45_ERR = 6978; // 4 +static const uint64_t SH_FLD_DIB67_ERR = 6979; // 2 +static const uint64_t SH_FLD_DIB67_SPARE = 6980; // 1 +static const uint64_t SH_FLD_DIB67_SPARE_LEN = 6981; // 1 +static const uint64_t SH_FLD_DIGITAL_EYE = 6982; // 8 +static const uint64_t SH_FLD_DIN_0 = 6983; // 1 +static const uint64_t SH_FLD_DIN_1 = 6984; // 1 +static const uint64_t SH_FLD_DIN_2 = 6985; // 1 +static const uint64_t SH_FLD_DIO_INTERRUPT_HIGH = 6986; // 1 +static const uint64_t SH_FLD_DIO_INTERRUPT_PENDING = 6987; // 1 +static const uint64_t SH_FLD_DIRECT_BRIDGE_SOURCE = 6988; // 1 +static const uint64_t SH_FLD_DIR_CE_DETECTED = 6989; // 12 +static const uint64_t SH_FLD_DIR_PERR_CHK_DIS = 6990; // 2 +static const uint64_t SH_FLD_DIR_SBCE_REPAIR_FAILED = 6991; // 12 +static const uint64_t SH_FLD_DIR_STUCK_BIT_CE = 6992; // 12 +static const uint64_t SH_FLD_DIR_UE_DETECTED = 6993; // 12 +static const uint64_t SH_FLD_DISABLE = 6994; // 2 +static const uint64_t SH_FLD_DISABLED = 6995; // 4 +static const uint64_t SH_FLD_DISABLED_LEN = 6996; // 4 +static const uint64_t SH_FLD_DISABLE_1 = 6997; // 1 +static const uint64_t SH_FLD_DISABLE_1_LEN = 6998; // 1 +static const uint64_t SH_FLD_DISABLE_2 = 6999; // 1 +static const uint64_t SH_FLD_DISABLE_2K_SPEC_FILTER = 7000; // 4 +static const uint64_t SH_FLD_DISABLE_2N_MODE = 7001; // 2 +static const uint64_t SH_FLD_DISABLE_2TO12_CLEAR = 7002; // 4 +static const uint64_t SH_FLD_DISABLE_2_LEN = 7003; // 1 +static const uint64_t SH_FLD_DISABLE_ALL_SPEC_OPS = 7004; // 4 +static const uint64_t SH_FLD_DISABLE_ARY_CLK_DURING_FILL = 7005; // 43 +static const uint64_t SH_FLD_DISABLE_BAD_LANE_COUNT = 7006; // 2 +static const uint64_t SH_FLD_DISABLE_BANK_PDWN = 7007; // 2 +static const uint64_t SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW = 7008; // 4 +static const uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH = 7009; // 4 +static const uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 7010; // 4 +static const uint64_t SH_FLD_DISABLE_CHARB_BYPASS = 7011; // 4 +static const uint64_t SH_FLD_DISABLE_CHECKIN_HANG_TIMER = 7012; // 1 +static const uint64_t SH_FLD_DISABLE_CHECKOUT_HANG_TIMER = 7013; // 1 +static const uint64_t SH_FLD_DISABLE_CHECKSTOP = 7014; // 1 +static const uint64_t SH_FLD_DISABLE_CI = 7015; // 4 +static const uint64_t SH_FLD_DISABLE_CI_LEN = 7016; // 4 +static const uint64_t SH_FLD_DISABLE_CLEAR_BAD_LANE_COUNT = 7017; // 2 +static const uint64_t SH_FLD_DISABLE_COMMAND_BYPASS = 7018; // 4 +static const uint64_t SH_FLD_DISABLE_COMMAND_BYPASS_LEN = 7019; // 4 +static const uint64_t SH_FLD_DISABLE_COMPRESSION = 7020; // 162 +static const uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS = 7021; // 4 +static const uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN = 7022; // 4 +static const uint64_t SH_FLD_DISABLE_CRC_ECC_FP_BYPASS = 7023; // 4 +static const uint64_t SH_FLD_DISABLE_DROPABLE = 7024; // 8 +static const uint64_t SH_FLD_DISABLE_ECC = 7025; // 1 +static const uint64_t SH_FLD_DISABLE_ECC_ARRAY_CHK = 7026; // 2 +static const uint64_t SH_FLD_DISABLE_ECC_ARRAY_CORRECTION = 7027; // 2 +static const uint64_t SH_FLD_DISABLE_ECC_CHK = 7028; // 1 +static const uint64_t SH_FLD_DISABLE_ECC_CORRECTION = 7029; // 1 +static const uint64_t SH_FLD_DISABLE_ECC_COR_GXC_PSI = 7030; // 1 +static const uint64_t SH_FLD_DISABLE_ECC_COR_RXRF_PSI = 7031; // 1 +static const uint64_t SH_FLD_DISABLE_ECC_COR_TXRF_PSI = 7032; // 1 +static const uint64_t SH_FLD_DISABLE_ERR_CMD = 7033; // 1 +static const uint64_t SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES = 7034; // 1 +static const uint64_t SH_FLD_DISABLE_EXTRA_HASH_ACCESSES = 7035; // 1 +static const uint64_t SH_FLD_DISABLE_FAR_HISTORY = 7036; // 1 +static const uint64_t SH_FLD_DISABLE_FASTPATH = 7037; // 4 +static const uint64_t SH_FLD_DISABLE_FENCE_RESET = 7038; // 4 +static const uint64_t SH_FLD_DISABLE_FLOW_SCOPE = 7039; // 1 +static const uint64_t SH_FLD_DISABLE_FP_COMMAND_BYPASS = 7040; // 4 +static const uint64_t SH_FLD_DISABLE_FP_M_BIT = 7041; // 4 +static const uint64_t SH_FLD_DISABLE_G = 7042; // 1 +static const uint64_t SH_FLD_DISABLE_GAP = 7043; // 2 +static const uint64_t SH_FLD_DISABLE_G_RD = 7044; // 1 +static const uint64_t SH_FLD_DISABLE_G_WR = 7045; // 1 +static const uint64_t SH_FLD_DISABLE_H1_CLEAR = 7046; // 6 +static const uint64_t SH_FLD_DISABLE_HIGH_PRIORITY = 7047; // 4 +static const uint64_t SH_FLD_DISABLE_HIGH_PRIORITY_LEN = 7048; // 4 +static const uint64_t SH_FLD_DISABLE_HIT_UNDER_BARRIER = 7049; // 1 +static const uint64_t SH_FLD_DISABLE_HTM_CMD = 7050; // 1 +static const uint64_t SH_FLD_DISABLE_IDX_IN_AIBTAG = 7051; // 1 +static const uint64_t SH_FLD_DISABLE_INJECT = 7052; // 1 +static const uint64_t SH_FLD_DISABLE_LFSR = 7053; // 1 +static const uint64_t SH_FLD_DISABLE_LINK_FAIL_COUNT = 7054; // 2 +static const uint64_t SH_FLD_DISABLE_LN = 7055; // 1 +static const uint64_t SH_FLD_DISABLE_LN_RD = 7056; // 1 +static const uint64_t SH_FLD_DISABLE_LN_WR = 7057; // 1 +static const uint64_t SH_FLD_DISABLE_LPC_CMDS = 7058; // 3 +static const uint64_t SH_FLD_DISABLE_MDI0 = 7059; // 4 +static const uint64_t SH_FLD_DISABLE_MDI0_LEN = 7060; // 4 +static const uint64_t SH_FLD_DISABLE_MEMCTL_CAL = 7061; // 8 +static const uint64_t SH_FLD_DISABLE_NEAR_HISTORY = 7062; // 1 +static const uint64_t SH_FLD_DISABLE_NN_RD = 7063; // 1 +static const uint64_t SH_FLD_DISABLE_NN_RN = 7064; // 1 +static const uint64_t SH_FLD_DISABLE_NN_WR = 7065; // 1 +static const uint64_t SH_FLD_DISABLE_PARITY_CHECKER = 7066; // 8 +static const uint64_t SH_FLD_DISABLE_PCB_ITR = 7067; // 43 +static const uint64_t SH_FLD_DISABLE_PERFMON_RESET_ON_START = 7068; // 4 +static const uint64_t SH_FLD_DISABLE_PMISC = 7069; // 9 +static const uint64_t SH_FLD_DISABLE_PMU_SNOOPING = 7070; // 1 +static const uint64_t SH_FLD_DISABLE_PROMOTE = 7071; // 1 +static const uint64_t SH_FLD_DISABLE_RCMD_CLKGATE = 7072; // 3 +static const uint64_t SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 7073; // 4 +static const uint64_t SH_FLD_DISABLE_RETRY_LOST_CLAIM = 7074; // 4 +static const uint64_t SH_FLD_DISABLE_SHARD_PRESP_ABORT = 7075; // 4 +static const uint64_t SH_FLD_DISABLE_SL_ECC = 7076; // 5 +static const uint64_t SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT = 7077; // 4 +static const uint64_t SH_FLD_DISABLE_SPEC_OP = 7078; // 4 +static const uint64_t SH_FLD_DISABLE_SPEC_OP_LEN = 7079; // 4 +static const uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE = 7080; // 4 +static const uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN = 7081; // 4 +static const uint64_t SH_FLD_DISABLE_STICKINESS = 7082; // 43 +static const uint64_t SH_FLD_DISABLE_TIMEOUT = 7083; // 1 +static const uint64_t SH_FLD_DISABLE_TIMEOUT_AND_RETRY = 7084; // 1 +static const uint64_t SH_FLD_DISABLE_TOD_CMD = 7085; // 1 +static const uint64_t SH_FLD_DISABLE_TRACE_CMD = 7086; // 1 +static const uint64_t SH_FLD_DISABLE_VG_NOT_SYS = 7087; // 1 +static const uint64_t SH_FLD_DISABLE_VG_RD = 7088; // 1 +static const uint64_t SH_FLD_DISABLE_VG_WR = 7089; // 1 +static const uint64_t SH_FLD_DISABLE_WRAP = 7090; // 24 +static const uint64_t SH_FLD_DISABLE_WRP = 7091; // 1 +static const uint64_t SH_FLD_DISABLE_XSCOM_CMD = 7092; // 1 +static const uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT = 7093; // 1 +static const uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN = 7094; // 1 +static const uint64_t SH_FLD_DISP_DEBUG_SEL = 7095; // 8 +static const uint64_t SH_FLD_DISP_DEBUG_SEL_LEN = 7096; // 8 +static const uint64_t SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE = 7097; // 1 +static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_DISABLE = 7098; // 1 +static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 7099; // 1 +static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER = 7100; // 1 +static const uint64_t SH_FLD_DIS_AIB_IN_ECC_CORRECTION = 7101; // 1 +static const uint64_t SH_FLD_DIS_ARX_DAT_CORR = 7102; // 1 +static const uint64_t SH_FLD_DIS_ARX_DAT_CORR_LEN = 7103; // 1 +static const uint64_t SH_FLD_DIS_ARX_ECC_CORRECTION = 7104; // 1 +static const uint64_t SH_FLD_DIS_ARX_TAG_CORR = 7105; // 1 +static const uint64_t SH_FLD_DIS_ATX_AT_CORR = 7106; // 1 +static const uint64_t SH_FLD_DIS_ATX_BAR_CORR = 7107; // 1 +static const uint64_t SH_FLD_DIS_ATX_CMD_CORR = 7108; // 1 +static const uint64_t SH_FLD_DIS_AT_SRAM_ECC_CORRECTION = 7109; // 1 +static const uint64_t SH_FLD_DIS_AVX_CORR = 7110; // 1 +static const uint64_t SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION = 7111; // 1 +static const uint64_t SH_FLD_DIS_CHGRATE_COUNT = 7112; // 1 +static const uint64_t SH_FLD_DIS_CPM_BUBBLE_CORR = 7113; // 43 +static const uint64_t SH_FLD_DIS_CRESP_CORR = 7114; // 1 +static const uint64_t SH_FLD_DIS_CTRLBUF_ECC_CORRECTION = 7115; // 1 +static const uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION = 7116; // 4 +static const uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION_LEN = 7117; // 4 +static const uint64_t SH_FLD_DIS_DMA_W = 7118; // 1 +static const uint64_t SH_FLD_DIS_DROPABLE_HP = 7119; // 8 +static const uint64_t SH_FLD_DIS_ECCCHK = 7120; // 1 +static const uint64_t SH_FLD_DIS_ECCCHK_CLO = 7121; // 1 +static const uint64_t SH_FLD_DIS_ECCCHK_IN = 7122; // 1 +static const uint64_t SH_FLD_DIS_ECCCHK_LDO = 7123; // 1 +static const uint64_t SH_FLD_DIS_ECCCHK_STO = 7124; // 1 +static const uint64_t SH_FLD_DIS_ECCCHK_WRO = 7125; // 1 +static const uint64_t SH_FLD_DIS_GLOB_SCOM = 7126; // 2 +static const uint64_t SH_FLD_DIS_IRQ_ECC_CORRECTION = 7127; // 1 +static const uint64_t SH_FLD_DIS_LD_ECC_CORRECTION = 7128; // 1 +static const uint64_t SH_FLD_DIS_MASTER_RD_PIPE = 7129; // 1 +static const uint64_t SH_FLD_DIS_MASTER_WR_PIPE = 7130; // 1 +static const uint64_t SH_FLD_DIS_MMIO_LDST_CORR = 7131; // 1 +static const uint64_t SH_FLD_DIS_MMIO_RSP_CORR = 7132; // 1 +static const uint64_t SH_FLD_DIS_MSTID_MATCH_PREF_INV = 7133; // 1 +static const uint64_t SH_FLD_DIS_NCNP = 7134; // 1 +static const uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION = 7135; // 1 +static const uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN = 7136; // 1 +static const uint64_t SH_FLD_DIS_REARB = 7137; // 1 +static const uint64_t SH_FLD_DIS_RECOVERY = 7138; // 24 +static const uint64_t SH_FLD_DIS_REREQUEST_TO = 7139; // 1 +static const uint64_t SH_FLD_DIS_SLAVE_RDPIPE = 7140; // 1 +static const uint64_t SH_FLD_DIS_SLAVE_WRPIPE = 7141; // 1 +static const uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION = 7142; // 4 +static const uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION_LEN = 7143; // 2 +static const uint64_t SH_FLD_DIS_SYND_TALLYING = 7144; // 4 +static const uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION = 7145; // 4 +static const uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION_LEN = 7146; // 4 +static const uint64_t SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION = 7147; // 1 +static const uint64_t SH_FLD_DIS_TRACE_SPR = 7148; // 24 +static const uint64_t SH_FLD_DIS_VRQ_QUEUE_CORR = 7149; // 1 +static const uint64_t SH_FLD_DIS_WRITE_GATHER = 7150; // 4 +static const uint64_t SH_FLD_DIVIDER_MODE = 7151; // 12 +static const uint64_t SH_FLD_DIVIDER_MODE_LEN = 7152; // 12 +static const uint64_t SH_FLD_DIVSELB = 7153; // 10 +static const uint64_t SH_FLD_DIVSELB_LEN = 7154; // 10 +static const uint64_t SH_FLD_DIVSELFB = 7155; // 10 +static const uint64_t SH_FLD_DIVSELFB_LEN = 7156; // 10 +static const uint64_t SH_FLD_DIV_PARITY = 7157; // 43 +static const uint64_t SH_FLD_DLL = 7158; // 8 +static const uint64_t SH_FLD_DLL_CLOCK_GATE = 7159; // 8 +static const uint64_t SH_FLD_DL_RETURN_P0 = 7160; // 43 +static const uint64_t SH_FLD_DL_RETURN_WDATA_PARITY = 7161; // 43 +static const uint64_t SH_FLD_DMAG0_FIN_RF_PARITY_HOLD_OUT = 7162; // 24 +static const uint64_t SH_FLD_DMAG1_FIN_RF_PARITY_HOLD_OUT = 7163; // 24 +static const uint64_t SH_FLD_DMAG2_RP2_RF_PARITY_HOLD_OUT = 7164; // 24 +static const uint64_t SH_FLD_DMAG3_RP2_RF_PARITY_HOLD_OUT = 7165; // 24 +static const uint64_t SH_FLD_DMAP_MODE_EN = 7166; // 2 +static const uint64_t SH_FLD_DMA_CH0_IDLE = 7167; // 1 +static const uint64_t SH_FLD_DMA_CH1_IDLE = 7168; // 1 +static const uint64_t SH_FLD_DMA_CH2_IDLE = 7169; // 1 +static const uint64_t SH_FLD_DMA_CH3_IDLE = 7170; // 1 +static const uint64_t SH_FLD_DMA_CH4_IDLE = 7171; // 1 +static const uint64_t SH_FLD_DMA_CRBARRAY_ACTION = 7172; // 1 +static const uint64_t SH_FLD_DMA_CRBARRAY_ENA = 7173; // 1 +static const uint64_t SH_FLD_DMA_CRBARRAY_SELECT = 7174; // 1 +static const uint64_t SH_FLD_DMA_CRBARRAY_TYPE = 7175; // 1 +static const uint64_t SH_FLD_DMA_EGRARRAY_ACTION = 7176; // 1 +static const uint64_t SH_FLD_DMA_EGRARRAY_ENA = 7177; // 1 +static const uint64_t SH_FLD_DMA_EGRARRAY_SELECT = 7178; // 1 +static const uint64_t SH_FLD_DMA_EGRARRAY_SELECT_LEN = 7179; // 1 +static const uint64_t SH_FLD_DMA_EGRARRAY_TYPE = 7180; // 1 +static const uint64_t SH_FLD_DMA_INGARRAY_ACTION = 7181; // 1 +static const uint64_t SH_FLD_DMA_INGARRAY_ENA = 7182; // 1 +static const uint64_t SH_FLD_DMA_INGARRAY_SELECT = 7183; // 1 +static const uint64_t SH_FLD_DMA_INGARRAY_SELECT_LEN = 7184; // 1 +static const uint64_t SH_FLD_DMA_INGARRAY_TYPE = 7185; // 1 +static const uint64_t SH_FLD_DMA_INWR_ACTION = 7186; // 1 +static const uint64_t SH_FLD_DMA_INWR_ENA = 7187; // 1 +static const uint64_t SH_FLD_DMA_INWR_TYPE = 7188; // 1 +static const uint64_t SH_FLD_DMA_MUX_SELECT = 7189; // 1 +static const uint64_t SH_FLD_DMA_MUX_SELECT_LEN = 7190; // 1 +static const uint64_t SH_FLD_DMA_OUTWR_ACTION = 7191; // 1 +static const uint64_t SH_FLD_DMA_OUTWR_ENA = 7192; // 1 +static const uint64_t SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA = 7193; // 1 +static const uint64_t SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA = 7194; // 1 +static const uint64_t SH_FLD_DMA_OUTWR_TYPE = 7195; // 1 +static const uint64_t SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT = 7196; // 1 +static const uint64_t SH_FLD_DMA_PART_WR_NOT_INJ = 7197; // 1 +static const uint64_t SH_FLD_DMA_RD_DISABLE_GROUP = 7198; // 2 +static const uint64_t SH_FLD_DMA_RD_DISABLE_LN = 7199; // 2 +static const uint64_t SH_FLD_DMA_RD_DISABLE_NN_RN = 7200; // 2 +static const uint64_t SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS = 7201; // 2 +static const uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK = 7202; // 2 +static const uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN = 7203; // 2 +static const uint64_t SH_FLD_DMA_RD_VG_RST_TMASK = 7204; // 1 +static const uint64_t SH_FLD_DMA_RD_VG_RST_TMASK_LEN = 7205; // 1 +static const uint64_t SH_FLD_DMA_READ = 7206; // 3 +static const uint64_t SH_FLD_DMA_READ_LEN = 7207; // 3 +static const uint64_t SH_FLD_DMA_REQUEST_1_SELECT = 7208; // 2 +static const uint64_t SH_FLD_DMA_REQUEST_1_SELECT_LEN = 7209; // 2 +static const uint64_t SH_FLD_DMA_REQUEST_2_SELECT = 7210; // 2 +static const uint64_t SH_FLD_DMA_REQUEST_2_SELECT_LEN = 7211; // 2 +static const uint64_t SH_FLD_DMA_STOPPED_STATE = 7212; // 32 +static const uint64_t SH_FLD_DMA_STOPPED_STATE_LEN = 7213; // 16 +static const uint64_t SH_FLD_DMA_TIMER_ENBL = 7214; // 1 +static const uint64_t SH_FLD_DMA_TIMER_REF_DIV = 7215; // 1 +static const uint64_t SH_FLD_DMA_TIMER_REF_DIV_LEN = 7216; // 1 +static const uint64_t SH_FLD_DMA_WRITE = 7217; // 3 +static const uint64_t SH_FLD_DMA_WRITE_LEN = 7218; // 2 +static const uint64_t SH_FLD_DMA_WR_DISABLE_GROUP = 7219; // 2 +static const uint64_t SH_FLD_DMA_WR_DISABLE_LN = 7220; // 2 +static const uint64_t SH_FLD_DMA_WR_DISABLE_NN_RN = 7221; // 2 +static const uint64_t SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS = 7222; // 2 +static const uint64_t SH_FLD_DMA_WR_NOT_INJ = 7223; // 1 +static const uint64_t SH_FLD_DMA_WR_NOT_INJECT = 7224; // 1 +static const uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK = 7225; // 2 +static const uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN = 7226; // 2 +static const uint64_t SH_FLD_DMA_WR_VG_RST_TMASK = 7227; // 1 +static const uint64_t SH_FLD_DMA_WR_VG_RST_TMASK_LEN = 7228; // 1 +static const uint64_t SH_FLD_DNFIFO_ACK = 7229; // 1 +static const uint64_t SH_FLD_DNFIFO_DATA_IN_PORT = 7230; // 1 +static const uint64_t SH_FLD_DNFIFO_DATA_IN_PORT_LEN = 7231; // 1 +static const uint64_t SH_FLD_DNFIFO_DATA_OUT_PORT = 7232; // 1 +static const uint64_t SH_FLD_DNFIFO_DATA_OUT_PORT_LEN = 7233; // 1 +static const uint64_t SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG = 7234; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_EMPTY = 7235; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT = 7236; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN = 7237; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS = 7238; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN = 7239; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_FULL = 7240; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS = 7241; // 1 +static const uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN = 7242; // 1 +static const uint64_t SH_FLD_DNFIFO_MCT = 7243; // 1 +static const uint64_t SH_FLD_DNFIFO_MCT_LEN = 7244; // 1 +static const uint64_t SH_FLD_DNFIFO_REQ_RESET = 7245; // 1 +static const uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SBE = 7246; // 1 +static const uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SP = 7247; // 1 +static const uint64_t SH_FLD_DNFIFO_RESET = 7248; // 1 +static const uint64_t SH_FLD_DNFIFO_SIGNAL = 7249; // 1 +static const uint64_t SH_FLD_DOB00_SCOM_SYN0 = 7250; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN0_LEN = 7251; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN1 = 7252; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN1_LEN = 7253; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN2 = 7254; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN2_LEN = 7255; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN3 = 7256; // 2 +static const uint64_t SH_FLD_DOB00_SCOM_SYN3_LEN = 7257; // 2 +static const uint64_t SH_FLD_DOB01_CE = 7258; // 6 +static const uint64_t SH_FLD_DOB01_CE_LEN = 7259; // 2 +static const uint64_t SH_FLD_DOB01_ERR = 7260; // 4 +static const uint64_t SH_FLD_DOB01_SCOM_SYN0 = 7261; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN0_LEN = 7262; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN1 = 7263; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN1_LEN = 7264; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN2 = 7265; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN2_LEN = 7266; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN3 = 7267; // 2 +static const uint64_t SH_FLD_DOB01_SCOM_SYN3_LEN = 7268; // 2 +static const uint64_t SH_FLD_DOB01_SUE = 7269; // 6 +static const uint64_t SH_FLD_DOB01_SUE_LEN = 7270; // 2 +static const uint64_t SH_FLD_DOB01_UE = 7271; // 6 +static const uint64_t SH_FLD_DOB01_UE_LEN = 7272; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN0 = 7273; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN0_LEN = 7274; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN1 = 7275; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN1_LEN = 7276; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN2 = 7277; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN2_LEN = 7278; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN3 = 7279; // 2 +static const uint64_t SH_FLD_DOB02_SCOM_SYN3_LEN = 7280; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN0 = 7281; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN0_LEN = 7282; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN1 = 7283; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN1_LEN = 7284; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN2 = 7285; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN2_LEN = 7286; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN3 = 7287; // 2 +static const uint64_t SH_FLD_DOB03_SCOM_SYN3_LEN = 7288; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN0 = 7289; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN0_LEN = 7290; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN1 = 7291; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN1_LEN = 7292; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN2 = 7293; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN2_LEN = 7294; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN3 = 7295; // 2 +static const uint64_t SH_FLD_DOB04_SCOM_SYN3_LEN = 7296; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN0 = 7297; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN0_LEN = 7298; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN1 = 7299; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN1_LEN = 7300; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN2 = 7301; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN2_LEN = 7302; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN3 = 7303; // 2 +static const uint64_t SH_FLD_DOB05_SCOM_SYN3_LEN = 7304; // 2 +static const uint64_t SH_FLD_DOB06_SCOM_SYN0 = 7305; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN0_LEN = 7306; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN1 = 7307; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN1_LEN = 7308; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN2 = 7309; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN2_LEN = 7310; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN3 = 7311; // 1 +static const uint64_t SH_FLD_DOB06_SCOM_SYN3_LEN = 7312; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN0 = 7313; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN0_LEN = 7314; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN1 = 7315; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN1_LEN = 7316; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN2 = 7317; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN2_LEN = 7318; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN3 = 7319; // 1 +static const uint64_t SH_FLD_DOB07_SCOM_SYN3_LEN = 7320; // 1 +static const uint64_t SH_FLD_DOB23_CE = 7321; // 6 +static const uint64_t SH_FLD_DOB23_CE_LEN = 7322; // 2 +static const uint64_t SH_FLD_DOB23_ERR = 7323; // 4 +static const uint64_t SH_FLD_DOB23_SUE = 7324; // 6 +static const uint64_t SH_FLD_DOB23_SUE_LEN = 7325; // 2 +static const uint64_t SH_FLD_DOB23_UE = 7326; // 6 +static const uint64_t SH_FLD_DOB23_UE_LEN = 7327; // 2 +static const uint64_t SH_FLD_DOB45_CE = 7328; // 6 +static const uint64_t SH_FLD_DOB45_CE_LEN = 7329; // 2 +static const uint64_t SH_FLD_DOB45_ERR = 7330; // 4 +static const uint64_t SH_FLD_DOB45_SUE = 7331; // 6 +static const uint64_t SH_FLD_DOB45_SUE_LEN = 7332; // 2 +static const uint64_t SH_FLD_DOB45_UE = 7333; // 6 +static const uint64_t SH_FLD_DOB45_UE_LEN = 7334; // 2 +static const uint64_t SH_FLD_DOB67_CE = 7335; // 3 +static const uint64_t SH_FLD_DOB67_CE_LEN = 7336; // 1 +static const uint64_t SH_FLD_DOB67_ERR = 7337; // 2 +static const uint64_t SH_FLD_DOB67_SUE = 7338; // 3 +static const uint64_t SH_FLD_DOB67_SUE_LEN = 7339; // 1 +static const uint64_t SH_FLD_DOB67_UE = 7340; // 3 +static const uint64_t SH_FLD_DOB67_UE_LEN = 7341; // 1 +static const uint64_t SH_FLD_DOMESTIC_OP_HANG = 7342; // 2 +static const uint64_t SH_FLD_DONE = 7343; // 31 +static const uint64_t SH_FLD_DOORBELL0_C0 = 7344; // 12 +static const uint64_t SH_FLD_DOORBELL0_C1 = 7345; // 12 +static const uint64_t SH_FLD_DOORBELL1_C0 = 7346; // 12 +static const uint64_t SH_FLD_DOORBELL1_C1 = 7347; // 12 +static const uint64_t SH_FLD_DOORBELL2_C0 = 7348; // 12 +static const uint64_t SH_FLD_DOORBELL2_C1 = 7349; // 12 +static const uint64_t SH_FLD_DOORBELL3_C0 = 7350; // 12 +static const uint64_t SH_FLD_DOORBELL3_C1 = 7351; // 12 +static const uint64_t SH_FLD_DOUBLE_EPSILON_LENGTH = 7352; // 4 +static const uint64_t SH_FLD_DO_0 = 7353; // 1 +static const uint64_t SH_FLD_DO_1 = 7354; // 1 +static const uint64_t SH_FLD_DO_2 = 7355; // 1 +static const uint64_t SH_FLD_DO_DR = 7356; // 1 +static const uint64_t SH_FLD_DO_EN_0 = 7357; // 1 +static const uint64_t SH_FLD_DO_EN_1 = 7358; // 1 +static const uint64_t SH_FLD_DO_EN_2 = 7359; // 1 +static const uint64_t SH_FLD_DO_IR = 7360; // 1 +static const uint64_t SH_FLD_DO_TAP_RESET = 7361; // 1 +static const uint64_t SH_FLD_DPFD = 7362; // 96 +static const uint64_t SH_FLD_DPFD_LEN = 7363; // 96 +static const uint64_t SH_FLD_DPLL_DCO_EMPTY = 7364; // 6 +static const uint64_t SH_FLD_DPLL_DCO_FULL = 7365; // 6 +static const uint64_t SH_FLD_DPLL_DYN_FMIN = 7366; // 6 +static const uint64_t SH_FLD_DPLL_INT = 7367; // 6 +static const uint64_t SH_FLD_DPLL_TEST_SEL = 7368; // 43 +static const uint64_t SH_FLD_DPLL_TEST_SEL_LEN = 7369; // 43 +static const uint64_t SH_FLD_DPX0_DAT_CE = 7370; // 4 +static const uint64_t SH_FLD_DPX0_DAT_SUE = 7371; // 4 +static const uint64_t SH_FLD_DPX0_DAT_UE = 7372; // 4 +static const uint64_t SH_FLD_DP_DLL_CAL_ERROR = 7373; // 8 +static const uint64_t SH_FLD_DP_DLL_CAL_ERROR_FINE = 7374; // 8 +static const uint64_t SH_FLD_DP_ERROR = 7375; // 8 +static const uint64_t SH_FLD_DP_ERROR_FINE = 7376; // 8 +static const uint64_t SH_FLD_DP_GOOD = 7377; // 8 +static const uint64_t SH_FLD_DP_TX_TRISTATE = 7378; // 8 +static const uint64_t SH_FLD_DQS = 7379; // 8 +static const uint64_t SH_FLD_DQS_ALIGN = 7380; // 8 +static const uint64_t SH_FLD_DQ_SEL_LANE = 7381; // 8 +static const uint64_t SH_FLD_DQ_SEL_LANE_LEN = 7382; // 8 +static const uint64_t SH_FLD_DQ_SEL_QUAD = 7383; // 8 +static const uint64_t SH_FLD_DQ_SEL_QUAD_LEN = 7384; // 8 +static const uint64_t SH_FLD_DR = 7385; // 96 +static const uint64_t SH_FLD_DRAM_ABIST_DONE_DC = 7386; // 43 +static const uint64_t SH_FLD_DROOP_CHAR_MODE = 7387; // 12 +static const uint64_t SH_FLD_DROOP_NOTIFY_ENABLE = 7388; // 12 +static const uint64_t SH_FLD_DROOP_PROFILE_TYPE = 7389; // 12 +static const uint64_t SH_FLD_DROOP_PROFILE_TYPE_LEN = 7390; // 12 +static const uint64_t SH_FLD_DROOP_PROTECT_DATA = 7391; // 6 +static const uint64_t SH_FLD_DROOP_PROTECT_DATA_LEN = 7392; // 6 +static const uint64_t SH_FLD_DROOP_SAMPLE_RATE = 7393; // 12 +static const uint64_t SH_FLD_DROOP_SAMPLE_RATE_LEN = 7394; // 12 +static const uint64_t SH_FLD_DROOP_THROTTLE_ACTIVE = 7395; // 24 +static const uint64_t SH_FLD_DROOP_THROTTLE_ACTIVE_LEN = 7396; // 24 +static const uint64_t SH_FLD_DROOP_TIMER_MODE = 7397; // 12 +static const uint64_t SH_FLD_DROPOUT_CHAR_MODE = 7398; // 12 +static const uint64_t SH_FLD_DROPOUT_DETECT = 7399; // 12 +static const uint64_t SH_FLD_DROPOUT_EVENT_THRESHOLD = 7400; // 12 +static const uint64_t SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN = 7401; // 12 +static const uint64_t SH_FLD_DROPOUT_INAROW_THRESHOLD = 7402; // 12 +static const uint64_t SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN = 7403; // 12 +static const uint64_t SH_FLD_DROPOUT_NOTIFY_ENABLE = 7404; // 12 +static const uint64_t SH_FLD_DROPOUT_SAMPLE = 7405; // 12 +static const uint64_t SH_FLD_DROPOUT_SAMPLE_LEN = 7406; // 12 +static const uint64_t SH_FLD_DROPOUT_SAMPLE_RATE = 7407; // 12 +static const uint64_t SH_FLD_DROPOUT_SAMPLE_RATE_LEN = 7408; // 12 +static const uint64_t SH_FLD_DROPOUT_TIMER_MODE = 7409; // 12 +static const uint64_t SH_FLD_DROP_COUNTER_FULL = 7410; // 4 +static const uint64_t SH_FLD_DROP_MASK_0_5 = 7411; // 1 +static const uint64_t SH_FLD_DROP_MASK_0_5_LEN = 7412; // 1 +static const uint64_t SH_FLD_DROP_PLS_DIV00 = 7413; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV00_LEN = 7414; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV01 = 7415; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV01_LEN = 7416; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV10 = 7417; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV10_LEN = 7418; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV11 = 7419; // 8 +static const uint64_t SH_FLD_DROP_PLS_DIV11_LEN = 7420; // 8 +static const uint64_t SH_FLD_DROP_PRIORITY_MASK = 7421; // 12 +static const uint64_t SH_FLD_DROP_PRIORITY_MASK_LEN = 7422; // 12 +static const uint64_t SH_FLD_DROP_PRIORITY_MODE = 7423; // 2 +static const uint64_t SH_FLD_DROP_PRI_DMA = 7424; // 1 +static const uint64_t SH_FLD_DROP_PRI_HPC_READ = 7425; // 1 +static const uint64_t SH_FLD_DROP_PRI_INTRP = 7426; // 1 +static const uint64_t SH_FLD_DRTM_REQ = 7427; // 5 +static const uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG = 7428; // 4 +static const uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN = 7429; // 4 +static const uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG = 7430; // 6 +static const uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN = 7431; // 6 +static const uint64_t SH_FLD_DRV_PATTERN_EN = 7432; // 1 +static const uint64_t SH_FLD_DSC1_ABORT_1 = 7433; // 1 +static const uint64_t SH_FLD_DSC1_DATA_COUNT = 7434; // 1 +static const uint64_t SH_FLD_DSC1_DATA_COUNT_1B = 7435; // 1 +static const uint64_t SH_FLD_DSC1_DATA_COUNT_1B_LEN = 7436; // 1 +static const uint64_t SH_FLD_DSC1_DATA_COUNT_LEN = 7437; // 1 +static const uint64_t SH_FLD_DSC1_HEADER_COUNT = 7438; // 1 +static const uint64_t SH_FLD_DSC1_HEADER_COUNT_1B = 7439; // 1 +static const uint64_t SH_FLD_DSC1_HEADER_COUNT_1B_LEN = 7440; // 1 +static const uint64_t SH_FLD_DSC1_HEADER_COUNT_LEN = 7441; // 1 +static const uint64_t SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING = 7442; // 1 +static const uint64_t SH_FLD_DSC1_PERMISSION_TO_SEND_1 = 7443; // 1 +static const uint64_t SH_FLD_DSC1_PIB_SLAVE_PENDING = 7444; // 1 +static const uint64_t SH_FLD_DSC1_UNUSED_24 = 7445; // 1 +static const uint64_t SH_FLD_DSC1_UNUSED_27 = 7446; // 1 +static const uint64_t SH_FLD_DSC1_XDN_1 = 7447; // 1 +static const uint64_t SH_FLD_DSC1_XUP_1 = 7448; // 1 +static const uint64_t SH_FLD_DSC2_ABORT_2 = 7449; // 1 +static const uint64_t SH_FLD_DSC2_DATA_COUNT = 7450; // 1 +static const uint64_t SH_FLD_DSC2_DATA_COUNT_2B = 7451; // 1 +static const uint64_t SH_FLD_DSC2_DATA_COUNT_2B_LEN = 7452; // 1 +static const uint64_t SH_FLD_DSC2_DATA_COUNT_LEN = 7453; // 1 +static const uint64_t SH_FLD_DSC2_HEADER_COUNT = 7454; // 1 +static const uint64_t SH_FLD_DSC2_HEADER_COUNT_2B = 7455; // 1 +static const uint64_t SH_FLD_DSC2_HEADER_COUNT_2B_LEN = 7456; // 1 +static const uint64_t SH_FLD_DSC2_HEADER_COUNT_LEN = 7457; // 1 +static const uint64_t SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING = 7458; // 1 +static const uint64_t SH_FLD_DSC2_PERMISSION_TO_SEND_2 = 7459; // 1 +static const uint64_t SH_FLD_DSC2_PIB_SLAVE_PENDING = 7460; // 1 +static const uint64_t SH_FLD_DSC2_UNUSED_24 = 7461; // 1 +static const uint64_t SH_FLD_DSC2_UNUSED_27 = 7462; // 1 +static const uint64_t SH_FLD_DSC2_XDN_2 = 7463; // 1 +static const uint64_t SH_FLD_DSC2_XUP_2 = 7464; // 1 +static const uint64_t SH_FLD_DSM_CMD_PE_HOLD_OUT = 7465; // 8 +static const uint64_t SH_FLD_DSM_PE = 7466; // 8 +static const uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL = 7467; // 4 +static const uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN = 7468; // 4 +static const uint64_t SH_FLD_DS_TIMEOUT_SEL = 7469; // 4 +static const uint64_t SH_FLD_DS_TIMEOUT_SEL_LEN = 7470; // 4 +static const uint64_t SH_FLD_DTS_ENABLE_L1 = 7471; // 43 +static const uint64_t SH_FLD_DTS_ENABLE_L1_LEN = 7472; // 43 +static const uint64_t SH_FLD_DTS_READ_SEL = 7473; // 43 +static const uint64_t SH_FLD_DTS_READ_SEL_LEN = 7474; // 43 +static const uint64_t SH_FLD_DTS_SAMPLE_ENA = 7475; // 43 +static const uint64_t SH_FLD_DTS_TRIGGER = 7476; // 43 +static const uint64_t SH_FLD_DTS_TRIGGER_SEL = 7477; // 43 +static const uint64_t SH_FLD_DW0_ERR_TYPE = 7478; // 16 +static const uint64_t SH_FLD_DW0_ERR_TYPE_LEN = 7479; // 16 +static const uint64_t SH_FLD_DW0_SYNDROME = 7480; // 16 +static const uint64_t SH_FLD_DW0_SYNDROME_LEN = 7481; // 16 +static const uint64_t SH_FLD_DW1_ERR_TYPE = 7482; // 16 +static const uint64_t SH_FLD_DW1_ERR_TYPE_LEN = 7483; // 16 +static const uint64_t SH_FLD_DW1_SYNDROME = 7484; // 16 +static const uint64_t SH_FLD_DW1_SYNDROME_LEN = 7485; // 16 +static const uint64_t SH_FLD_DW2_ERR_TYPE = 7486; // 16 +static const uint64_t SH_FLD_DW2_ERR_TYPE_LEN = 7487; // 16 +static const uint64_t SH_FLD_DW2_SYNDROME = 7488; // 16 +static const uint64_t SH_FLD_DW2_SYNDROME_LEN = 7489; // 16 +static const uint64_t SH_FLD_DW3_ERR_TYPE = 7490; // 16 +static const uint64_t SH_FLD_DW3_ERR_TYPE_LEN = 7491; // 16 +static const uint64_t SH_FLD_DW3_SYNDROME = 7492; // 16 +static const uint64_t SH_FLD_DW3_SYNDROME_LEN = 7493; // 16 +static const uint64_t SH_FLD_DW_TYPE = 7494; // 12 +static const uint64_t SH_FLD_DW_TYPE_LEN = 7495; // 12 +static const uint64_t SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED = 7496; // 8 +static const uint64_t SH_FLD_DYNAMIC_REPAIR_ERROR = 7497; // 8 +static const uint64_t SH_FLD_DYNAMIC_SPARE_DEPLOYED = 7498; // 8 +static const uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT = 7499; // 8 +static const uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT_LEN = 7500; // 8 +static const uint64_t SH_FLD_DYNAM_SET_DELETED_HOLD_OUT = 7501; // 24 +static const uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 7502; // 8 +static const uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 7503; // 8 +static const uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL = 7504; // 4 +static const uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 7505; // 4 +static const uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 7506; // 8 +static const uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 7507; // 8 +static const uint64_t SH_FLD_DYN_RECAL_SUSPEND = 7508; // 4 +static const uint64_t SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG = 7509; // 4 +static const uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX = 7510; // 4 +static const uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN = 7511; // 4 +static const uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX = 7512; // 4 +static const uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN = 7513; // 4 +static const uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR1 = 7514; // 4 +static const uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR2 = 7515; // 4 +static const uint64_t SH_FLD_DYN_RPR_DISABLE = 7516; // 4 +static const uint64_t SH_FLD_DYN_RPR_DISABLE2 = 7517; // 4 +static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 7518; // 4 +static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 7519; // 4 +static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 7520; // 4 +static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 7521; // 4 +static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION = 7522; // 4 +static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN = 7523; // 4 +static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE = 7524; // 4 +static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 7525; // 4 +static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION = 7526; // 4 +static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN = 7527; // 4 +static const uint64_t SH_FLD_DYN_RPR_REQ_MANUAL = 7528; // 4 +static const uint64_t SH_FLD_DYN_RPR_SM_MANUAL = 7529; // 4 +static const uint64_t SH_FLD_DYN_ST_FREQ_MULT = 7530; // 2 +static const uint64_t SH_FLD_DYN_ST_FREQ_MULT_LEN = 7531; // 1 +static const uint64_t SH_FLD_DYN_ST_MODE_EN = 7532; // 1 +static const uint64_t SH_FLD_DYN_ST_MODE_HANGP_EN = 7533; // 1 +static const uint64_t SH_FLD_DYN_ST_MODE_THRESHOLD = 7534; // 2 +static const uint64_t SH_FLD_DYN_ST_MODE_THRESHOLD_LEN = 7535; // 2 +static const uint64_t SH_FLD_D_BIT_MAP = 7536; // 8 +static const uint64_t SH_FLD_D_BIT_MAP_LEN = 7537; // 8 +static const uint64_t SH_FLD_EA = 7538; // 96 +static const uint64_t SH_FLD_EAINJ = 7539; // 1 +static const uint64_t SH_FLD_EARLY_REQ = 7540; // 8 +static const uint64_t SH_FLD_EARLY_REQ_ERR_MASK = 7541; // 8 +static const uint64_t SH_FLD_EARLY_REQ_SOURCE = 7542; // 8 +static const uint64_t SH_FLD_EARLY_REQ_SOURCE_LEN = 7543; // 8 +static const uint64_t SH_FLD_EA_LEN = 7544; // 96 +static const uint64_t SH_FLD_EA_RANGE_CHK_DIS = 7545; // 1 +static const uint64_t SH_FLD_EBBRR = 7546; // 96 +static const uint64_t SH_FLD_EBBRR_LEN = 7547; // 96 +static const uint64_t SH_FLD_EBB_INTR_PRESENT = 7548; // 24 +static const uint64_t SH_FLD_EBB_INTR_PRESENT_LEN = 7549; // 24 +static const uint64_t SH_FLD_EBE = 7550; // 96 +static const uint64_t SH_FLD_EBUS_16A_SELECT = 7551; // 4 +static const uint64_t SH_FLD_EBUS_ENABLE_0_15 = 7552; // 1 +static const uint64_t SH_FLD_EBUS_ENABLE_0_15_LEN = 7553; // 1 +static const uint64_t SH_FLD_EC = 7554; // 96 +static const uint64_t SH_FLD_ECA_0 = 7555; // 24 +static const uint64_t SH_FLD_ECA_1 = 7556; // 24 +static const uint64_t SH_FLD_ECA_2 = 7557; // 24 +static const uint64_t SH_FLD_ECC = 7558; // 3 +static const uint64_t SH_FLD_ECCCHK_DISABLE_0 = 7559; // 1 +static const uint64_t SH_FLD_ECCCHK_DISABLE_1 = 7560; // 1 +static const uint64_t SH_FLD_ECCCHK_DISABLE_2 = 7561; // 1 +static const uint64_t SH_FLD_ECCCHK_DISABLE_3 = 7562; // 1 +static const uint64_t SH_FLD_ECCGEN = 7563; // 8 +static const uint64_t SH_FLD_ECC_CE = 7564; // 3 +static const uint64_t SH_FLD_ECC_CHK_DISABLE = 7565; // 1 +static const uint64_t SH_FLD_ECC_CLEAR = 7566; // 2 +static const uint64_t SH_FLD_ECC_CONFIG_ERROR_0 = 7567; // 1 +static const uint64_t SH_FLD_ECC_CONFIG_ERROR_1 = 7568; // 1 +static const uint64_t SH_FLD_ECC_CONFIG_ERROR_2 = 7569; // 1 +static const uint64_t SH_FLD_ECC_CONFIG_ERROR_3 = 7570; // 1 +static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_0 = 7571; // 1 +static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_1 = 7572; // 1 +static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_2 = 7573; // 1 +static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_3 = 7574; // 1 +static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_FACES = 7575; // 1 +static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_PIB = 7576; // 1 +static const uint64_t SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 7577; // 8 +static const uint64_t SH_FLD_ECC_CORRECT_DIS = 7578; // 16 +static const uint64_t SH_FLD_ECC_CTL_AF_PERR = 7579; // 8 +static const uint64_t SH_FLD_ECC_CTL_CMPMODE_ERR = 7580; // 8 +static const uint64_t SH_FLD_ECC_CTL_PCTL_PERR = 7581; // 8 +static const uint64_t SH_FLD_ECC_CTL_RPD_PERR = 7582; // 8 +static const uint64_t SH_FLD_ECC_CTL_RPTR_PERR = 7583; // 8 +static const uint64_t SH_FLD_ECC_CTL_SCHCTL_PERR = 7584; // 8 +static const uint64_t SH_FLD_ECC_CTL_SCHTAB_PERR = 7585; // 8 +static const uint64_t SH_FLD_ECC_CTL_TCHN_PERR = 7586; // 8 +static const uint64_t SH_FLD_ECC_CTL_TGST_PERR = 7587; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT = 7588; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT_LEN = 7589; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_ENABLE = 7590; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT = 7591; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT_LEN = 7592; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT = 7593; // 8 +static const uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT_LEN = 7594; // 8 +static const uint64_t SH_FLD_ECC_DETECT_DIS = 7595; // 16 +static const uint64_t SH_FLD_ECC_ENABLE = 7596; // 6 +static const uint64_t SH_FLD_ECC_ENABLE_0 = 7597; // 1 +static const uint64_t SH_FLD_ECC_ENABLE_1 = 7598; // 1 +static const uint64_t SH_FLD_ECC_ENABLE_2 = 7599; // 1 +static const uint64_t SH_FLD_ECC_ENABLE_3 = 7600; // 1 +static const uint64_t SH_FLD_ECC_ERROR_ADDR = 7601; // 2 +static const uint64_t SH_FLD_ECC_ERROR_ADDR_LEN = 7602; // 2 +static const uint64_t SH_FLD_ECC_ERROR_COUNT = 7603; // 2 +static const uint64_t SH_FLD_ECC_ERROR_COUNT_LEN = 7604; // 2 +static const uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL = 7605; // 4 +static const uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN = 7606; // 4 +static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA = 7607; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ = 7608; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP = 7609; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED = 7610; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN = 7611; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL = 7612; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN = 7613; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SELECTION = 7614; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SELECTION_LEN = 7615; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA = 7616; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ = 7617; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL = 7618; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP = 7619; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED = 7620; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN = 7621; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA = 7622; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ = 7623; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL = 7624; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN = 7625; // 1 +static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP = 7626; // 1 +static const uint64_t SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 7627; // 8 +static const uint64_t SH_FLD_ECC_INJECT_ERR = 7628; // 16 +static const uint64_t SH_FLD_ECC_INJECT_TYPE = 7629; // 16 +static const uint64_t SH_FLD_ECC_LEN = 7630; // 3 +static const uint64_t SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 7631; // 2 +static const uint64_t SH_FLD_ECC_PIPE_2SYM_PERR = 7632; // 8 +static const uint64_t SH_FLD_ECC_PIPE_CPLX_PERR = 7633; // 8 +static const uint64_t SH_FLD_ECC_PIPE_EP2_PERR = 7634; // 8 +static const uint64_t SH_FLD_ECC_PIPE_PCX_PERR = 7635; // 8 +static const uint64_t SH_FLD_ECC_PIPE_SYND_PERR = 7636; // 8 +static const uint64_t SH_FLD_ECC_SYNDROME = 7637; // 2 +static const uint64_t SH_FLD_ECC_SYNDROME_LEN = 7638; // 2 +static const uint64_t SH_FLD_ECC_S_BIT_ERROR = 7639; // 1 +static const uint64_t SH_FLD_ECC_UE = 7640; // 3 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_0 = 7641; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_1 = 7642; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_2 = 7643; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_3 = 7644; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_FACES = 7645; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_PIB = 7646; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERR_FACES = 7647; // 1 +static const uint64_t SH_FLD_ECC_UNCORRECTED_ERR_PIB = 7648; // 1 +static const uint64_t SH_FLD_ECC_WAT_ACTION_SELECT = 7649; // 8 +static const uint64_t SH_FLD_ECC_WAT_ENABLE = 7650; // 8 +static const uint64_t SH_FLD_ECC_WAT_SOURCE = 7651; // 8 +static const uint64_t SH_FLD_ECC_WAT_SOURCE_LEN = 7652; // 8 +static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE = 7653; // 8 +static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN = 7654; // 8 +static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT = 7655; // 8 +static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 7656; // 8 +static const uint64_t SH_FLD_ECHO_DELAY_CYCLES = 7657; // 2 +static const uint64_t SH_FLD_ECHO_DELAY_CYCLES_LEN = 7658; // 2 +static const uint64_t SH_FLD_ECH_0 = 7659; // 24 +static const uint64_t SH_FLD_ECH_1 = 7660; // 24 +static const uint64_t SH_FLD_ECH_2 = 7661; // 24 +static const uint64_t SH_FLD_ECONL_0 = 7662; // 24 +static const uint64_t SH_FLD_ECONL_1 = 7663; // 24 +static const uint64_t SH_FLD_ECONL_2 = 7664; // 24 +static const uint64_t SH_FLD_ECP_0 = 7665; // 24 +static const uint64_t SH_FLD_ECP_1 = 7666; // 24 +static const uint64_t SH_FLD_ECP_2 = 7667; // 24 +static const uint64_t SH_FLD_ECRESP_HASH_MODE = 7668; // 4 +static const uint64_t SH_FLD_ECRL_0 = 7669; // 24 +static const uint64_t SH_FLD_ECRL_1 = 7670; // 24 +static const uint64_t SH_FLD_ECRL_2 = 7671; // 24 +static const uint64_t SH_FLD_ECS_0 = 7672; // 24 +static const uint64_t SH_FLD_ECS_1 = 7673; // 24 +static const uint64_t SH_FLD_ECS_2 = 7674; // 24 +static const uint64_t SH_FLD_ECTA0_0 = 7675; // 24 +static const uint64_t SH_FLD_ECTA0_1 = 7676; // 24 +static const uint64_t SH_FLD_ECTA0_2 = 7677; // 24 +static const uint64_t SH_FLD_ECTA1_0 = 7678; // 24 +static const uint64_t SH_FLD_ECTA1_1 = 7679; // 24 +static const uint64_t SH_FLD_ECTA1_2 = 7680; // 24 +static const uint64_t SH_FLD_ECUS0_0 = 7681; // 24 +static const uint64_t SH_FLD_ECUS0_1 = 7682; // 24 +static const uint64_t SH_FLD_ECUS0_2 = 7683; // 24 +static const uint64_t SH_FLD_ECUS1_0 = 7684; // 24 +static const uint64_t SH_FLD_ECUS1_1 = 7685; // 24 +static const uint64_t SH_FLD_ECUS1_2 = 7686; // 24 +static const uint64_t SH_FLD_EDGE_TRIGGER_MODE1 = 7687; // 86 +static const uint64_t SH_FLD_EDGE_TRIGGER_MODE2 = 7688; // 86 +static const uint64_t SH_FLD_EDPL_LANE_ID = 7689; // 5 +static const uint64_t SH_FLD_EDPL_RATE = 7690; // 5 +static const uint64_t SH_FLD_EDPL_RATE_LEN = 7691; // 5 +static const uint64_t SH_FLD_EDR = 7692; // 21 +static const uint64_t SH_FLD_EDRAM_PGATE = 7693; // 6 +static const uint64_t SH_FLD_EDRAM_SEQUENCE = 7694; // 6 +static const uint64_t SH_FLD_EDRAM_SEQUENCE_ERR = 7695; // 43 +static const uint64_t SH_FLD_EDR_LEN = 7696; // 21 +static const uint64_t SH_FLD_EE = 7697; // 96 +static const uint64_t SH_FLD_EECNT = 7698; // 1 +static const uint64_t SH_FLD_EECNT_LEN = 7699; // 1 +static const uint64_t SH_FLD_EFTCOMP_MAX_INRD = 7700; // 1 +static const uint64_t SH_FLD_EFTCOMP_MAX_INRD_LEN = 7701; // 1 +static const uint64_t SH_FLD_EFTDECOMP_MAX_INRD = 7702; // 1 +static const uint64_t SH_FLD_EFTDECOMP_MAX_INRD_LEN = 7703; // 1 +static const uint64_t SH_FLD_EFT_COMP_PREFETCH_ENABLE = 7704; // 1 +static const uint64_t SH_FLD_EFT_DECOMP_PREFETCH_ENABLE = 7705; // 1 +static const uint64_t SH_FLD_EFT_MUX_SELECT = 7706; // 1 +static const uint64_t SH_FLD_EFT_MUX_SELECT_LEN = 7707; // 1 +static const uint64_t SH_FLD_EFT_SPBC_ENABLE = 7708; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT10 = 7709; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT11 = 7710; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT4 = 7711; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT5 = 7712; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT6 = 7713; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT7 = 7714; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT8 = 7715; // 1 +static const uint64_t SH_FLD_EG_CERR_BIT9 = 7716; // 1 +static const uint64_t SH_FLD_EG_CERR_RESET = 7717; // 1 +static const uint64_t SH_FLD_EG_CERR_UNUSEDBITS = 7718; // 1 +static const uint64_t SH_FLD_EG_CERR_UNUSEDBITS_LEN = 7719; // 1 +static const uint64_t SH_FLD_EG_ECC_CE_ERROR = 7720; // 2 +static const uint64_t SH_FLD_EG_ECC_SUE_ERROR = 7721; // 2 +static const uint64_t SH_FLD_EG_ECC_UE_ERROR = 7722; // 2 +static const uint64_t SH_FLD_EG_LOGIC_HW_ERROR = 7723; // 2 +static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI = 7724; // 1 +static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN = 7725; // 1 +static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO = 7726; // 1 +static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN = 7727; // 1 +static const uint64_t SH_FLD_EG_TRACE_INT_DATA_HI = 7728; // 2 +static const uint64_t SH_FLD_EG_TRACE_INT_DATA_LO = 7729; // 2 +static const uint64_t SH_FLD_EG_TRACE_INT_TRIG_01 = 7730; // 2 +static const uint64_t SH_FLD_EG_TRACE_INT_TRIG_23 = 7731; // 2 +static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01 = 7732; // 1 +static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN = 7733; // 1 +static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23 = 7734; // 1 +static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN = 7735; // 1 +static const uint64_t SH_FLD_EICR_PE = 7736; // 8 +static const uint64_t SH_FLD_ELEVEN_LANE_MODE = 7737; // 2 +static const uint64_t SH_FLD_EMBRDY = 7738; // 48 +static const uint64_t SH_FLD_EMBUMP = 7739; // 48 +static const uint64_t SH_FLD_EMCEN = 7740; // 48 +static const uint64_t SH_FLD_EMCNT = 7741; // 48 +static const uint64_t SH_FLD_EMCNT_LEN = 7742; // 48 +static const uint64_t SH_FLD_EMCRST = 7743; // 48 +static const uint64_t SH_FLD_EMEN = 7744; // 48 +static const uint64_t SH_FLD_EMERGENCY_M = 7745; // 8 +static const uint64_t SH_FLD_EMERGENCY_M_LEN = 7746; // 8 +static const uint64_t SH_FLD_EMERGENCY_N = 7747; // 8 +static const uint64_t SH_FLD_EMERGENCY_N_LEN = 7748; // 8 +static const uint64_t SH_FLD_EMERGENCY_THROTTLE = 7749; // 16 +static const uint64_t SH_FLD_EMER_THROTTLE_IP = 7750; // 8 +static const uint64_t SH_FLD_EMF8 = 7751; // 48 +static const uint64_t SH_FLD_EMMD = 7752; // 48 +static const uint64_t SH_FLD_EMMD_LEN = 7753; // 48 +static const uint64_t SH_FLD_EMOFLO = 7754; // 48 +static const uint64_t SH_FLD_EMSF = 7755; // 48 +static const uint64_t SH_FLD_EN = 7756; // 55 +static const uint64_t SH_FLD_ENA = 7757; // 1 +static const uint64_t SH_FLD_ENABLE = 7758; // 283 +static const uint64_t SH_FLD_ENABLE_0 = 7759; // 5 +static const uint64_t SH_FLD_ENABLE_0_7 = 7760; // 1 +static const uint64_t SH_FLD_ENABLE_0_7_LEN = 7761; // 1 +static const uint64_t SH_FLD_ENABLE_0_LEN = 7762; // 5 +static const uint64_t SH_FLD_ENABLE_1 = 7763; // 5 +static const uint64_t SH_FLD_ENABLE_1_LEN = 7764; // 5 +static const uint64_t SH_FLD_ENABLE_2 = 7765; // 5 +static const uint64_t SH_FLD_ENABLE_2_LEN = 7766; // 5 +static const uint64_t SH_FLD_ENABLE_3 = 7767; // 5 +static const uint64_t SH_FLD_ENABLE_3_LEN = 7768; // 5 +static const uint64_t SH_FLD_ENABLE_4 = 7769; // 5 +static const uint64_t SH_FLD_ENABLE_4_LEN = 7770; // 5 +static const uint64_t SH_FLD_ENABLE_5 = 7771; // 5 +static const uint64_t SH_FLD_ENABLE_5_LEN = 7772; // 5 +static const uint64_t SH_FLD_ENABLE_6 = 7773; // 5 +static const uint64_t SH_FLD_ENABLE_64_128B_READ = 7774; // 4 +static const uint64_t SH_FLD_ENABLE_6_LEN = 7775; // 5 +static const uint64_t SH_FLD_ENABLE_7 = 7776; // 5 +static const uint64_t SH_FLD_ENABLE_7_LEN = 7777; // 5 +static const uint64_t SH_FLD_ENABLE_AGGRESSIVE_BUSY = 7778; // 8 +static const uint64_t SH_FLD_ENABLE_APO_HANG = 7779; // 4 +static const uint64_t SH_FLD_ENABLE_AUX_PORT_UNUSED = 7780; // 2 +static const uint64_t SH_FLD_ENABLE_BER_TEST = 7781; // 4 +static const uint64_t SH_FLD_ENABLE_BUSY_COUNTERS = 7782; // 8 +static const uint64_t SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 7783; // 4 +static const uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND = 7784; // 4 +static const uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND = 7785; // 4 +static const uint64_t SH_FLD_ENABLE_CENTAUR_SYNC = 7786; // 4 +static const uint64_t SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND = 7787; // 4 +static const uint64_t SH_FLD_ENABLE_CLEAN = 7788; // 8 +static const uint64_t SH_FLD_ENABLE_CLIB_HANG = 7789; // 4 +static const uint64_t SH_FLD_ENABLE_CLR_ERR_CMD = 7790; // 1 +static const uint64_t SH_FLD_ENABLE_CM_COARSE_CAL = 7791; // 6 +static const uint64_t SH_FLD_ENABLE_CM_FINE_CAL = 7792; // 6 +static const uint64_t SH_FLD_ENABLE_CQ_PMU_COUNTING = 7793; // 1 +static const uint64_t SH_FLD_ENABLE_CQ_TRACE = 7794; // 1 +static const uint64_t SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY = 7795; // 4 +static const uint64_t SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 7796; // 6 +static const uint64_t SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 7797; // 6 +static const uint64_t SH_FLD_ENABLE_CTLE_COARSE_CAL = 7798; // 6 +static const uint64_t SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL = 7799; // 2 +static const uint64_t SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY = 7800; // 4 +static const uint64_t SH_FLD_ENABLE_DAC_H1_CAL = 7801; // 6 +static const uint64_t SH_FLD_ENABLE_DAC_H1_TO_A_CAL = 7802; // 4 +static const uint64_t SH_FLD_ENABLE_DDC = 7803; // 6 +static const uint64_t SH_FLD_ENABLE_DEBUG_BUS = 7804; // 1 +static const uint64_t SH_FLD_ENABLE_DFE_H1_CAL = 7805; // 6 +static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_CAL = 7806; // 4 +static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP = 7807; // 4 +static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 7808; // 4 +static const uint64_t SH_FLD_ENABLE_DFE_H6_H12_FAST_MODE = 7809; // 4 +static const uint64_t SH_FLD_ENABLE_DFE_VOLTAGE_MODE = 7810; // 4 +static const uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 7811; // 4 +static const uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 7812; // 4 +static const uint64_t SH_FLD_ENABLE_DONE_SIGNALING = 7813; // 4 +static const uint64_t SH_FLD_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS = 7814; // 6 +static const uint64_t SH_FLD_ENABLE_DYNAMIC_PF_USAGE = 7815; // 8 +static const uint64_t SH_FLD_ENABLE_DYNAMIC_WR_USAGE = 7816; // 8 +static const uint64_t SH_FLD_ENABLE_EG_PMU_COUNTING = 7817; // 1 +static const uint64_t SH_FLD_ENABLE_EG_TRACE = 7818; // 1 +static const uint64_t SH_FLD_ENABLE_EMER_THROTTLE = 7819; // 4 +static const uint64_t SH_FLD_ENABLE_ENABLE_CRESP_PE = 7820; // 4 +static const uint64_t SH_FLD_ENABLE_ERR_INJ = 7821; // 5 +static const uint64_t SH_FLD_ENABLE_FINAL_L2U_ADJ = 7822; // 4 +static const uint64_t SH_FLD_ENABLE_FIR_HOST_ATTN = 7823; // 4 +static const uint64_t SH_FLD_ENABLE_FIR_SPEC_ATTN = 7824; // 4 +static const uint64_t SH_FLD_ENABLE_FMAX_TARGET = 7825; // 6 +static const uint64_t SH_FLD_ENABLE_FMIN_TARGET = 7826; // 6 +static const uint64_t SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 7827; // 6 +static const uint64_t SH_FLD_ENABLE_GCR_OFL_BUFF = 7828; // 4 +static const uint64_t SH_FLD_ENABLE_GLB_PULSE = 7829; // 1 +static const uint64_t SH_FLD_ENABLE_GLOBAL_RUN = 7830; // 2 +static const uint64_t SH_FLD_ENABLE_H1AP_TWEAK = 7831; // 6 +static const uint64_t SH_FLD_ENABLE_HW_ERROR_RECOVERY = 7832; // 5 +static const uint64_t SH_FLD_ENABLE_INDIRECT_PMU_SCOM = 7833; // 24 +static const uint64_t SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL = 7834; // 6 +static const uint64_t SH_FLD_ENABLE_IN_PMU_COUNTING = 7835; // 1 +static const uint64_t SH_FLD_ENABLE_IN_TRACE = 7836; // 1 +static const uint64_t SH_FLD_ENABLE_IPOLL_AND_DMA = 7837; // 3 +static const uint64_t SH_FLD_ENABLE_JUMP_PROTECT = 7838; // 6 +static const uint64_t SH_FLD_ENABLE_JUMP_TARGET_UPDATE = 7839; // 6 +static const uint64_t SH_FLD_ENABLE_LEN = 7840; // 71 +static const uint64_t SH_FLD_ENABLE_MEMORY_BACKING = 7841; // 6 +static const uint64_t SH_FLD_ENABLE_MIRROR_HANG = 7842; // 4 +static const uint64_t SH_FLD_ENABLE_NONMIRROR_HANG = 7843; // 4 +static const uint64_t SH_FLD_ENABLE_OP_HIT_ERROR = 7844; // 4 +static const uint64_t SH_FLD_ENABLE_PARITY_CHECK = 7845; // 3 +static const uint64_t SH_FLD_ENABLE_PB_SWITCH_AB = 7846; // 1 +static const uint64_t SH_FLD_ENABLE_PB_SWITCH_CD = 7847; // 1 +static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_EXTREME_DROOP = 7848; // 6 +static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS = 7849; // 6 +static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT = 7850; // 6 +static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_LARGE_DROOP = 7851; // 6 +static const uint64_t SH_FLD_ENABLE_PECE = 7852; // 24 +static const uint64_t SH_FLD_ENABLE_PFETS_UPON_IVRM_DROPOUT = 7853; // 6 +static const uint64_t SH_FLD_ENABLE_PF_DROP_CMDLIST = 7854; // 4 +static const uint64_t SH_FLD_ENABLE_PF_DROP_SRQ = 7855; // 4 +static const uint64_t SH_FLD_ENABLE_PREFETCH_PROMOTE = 7856; // 4 +static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TOD = 7857; // 1 +static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER = 7858; // 1 +static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 7859; // 1 +static const uint64_t SH_FLD_ENABLE_REDUCE_SPEC = 7860; // 24 +static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_DISP = 7861; // 8 +static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_NSQ = 7862; // 8 +static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_SQ = 7863; // 8 +static const uint64_t SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS = 7864; // 3 +static const uint64_t SH_FLD_ENABLE_REMAP = 7865; // 1 +static const uint64_t SH_FLD_ENABLE_RESULT_CHECK = 7866; // 4 +static const uint64_t SH_FLD_ENABLE_RG_PMU_COUNTING = 7867; // 1 +static const uint64_t SH_FLD_ENABLE_RG_TRACE = 7868; // 1 +static const uint64_t SH_FLD_ENABLE_SCRD_FR_RXRF = 7869; // 1 +static const uint64_t SH_FLD_ENABLE_SCWR_TO_RXRF = 7870; // 1 +static const uint64_t SH_FLD_ENABLE_SCWR_TO_TXRF = 7871; // 1 +static const uint64_t SH_FLD_ENABLE_STREAMING_MODE = 7872; // 2 +static const uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG0 = 7873; // 1 +static const uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG1 = 7874; // 1 +static const uint64_t SH_FLD_ENABLE_TTYPE_DECODE = 7875; // 2 +static const uint64_t SH_FLD_ENABLE_VGA_AMAX_MODE = 7876; // 6 +static const uint64_t SH_FLD_ENABLE_VGA_CAL = 7877; // 6 +static const uint64_t SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL = 7878; // 2 +static const uint64_t SH_FLD_ENABLE_VITL_ALIGN_CHECK = 7879; // 43 +static const uint64_t SH_FLD_ENABLE_WAT = 7880; // 4 +static const uint64_t SH_FLD_ENABLE_WC_TRACE = 7881; // 1 +static const uint64_t SH_FLD_ENABLE_ZCAL = 7882; // 8 +static const uint64_t SH_FLD_ENA_COARSE_RD = 7883; // 8 +static const uint64_t SH_FLD_ENA_CUSTOM_RD = 7884; // 8 +static const uint64_t SH_FLD_ENA_CUSTOM_WR = 7885; // 8 +static const uint64_t SH_FLD_ENA_DIGITAL_EYE = 7886; // 8 +static const uint64_t SH_FLD_ENA_DQS_ALIGN = 7887; // 16 +static const uint64_t SH_FLD_ENA_INITIAL_COARSE_WR = 7888; // 8 +static const uint64_t SH_FLD_ENA_INITIAL_PAT_WR = 7889; // 8 +static const uint64_t SH_FLD_ENA_RANK = 7890; // 8 +static const uint64_t SH_FLD_ENA_RANK_LEN = 7891; // 8 +static const uint64_t SH_FLD_ENA_RANK_PAIR = 7892; // 16 +static const uint64_t SH_FLD_ENA_RANK_PAIR_LEN = 7893; // 16 +static const uint64_t SH_FLD_ENA_RDCLK_ALIGN = 7894; // 16 +static const uint64_t SH_FLD_ENA_READ_CTR = 7895; // 16 +static const uint64_t SH_FLD_ENA_SYSCLK_ALIGN = 7896; // 8 +static const uint64_t SH_FLD_ENA_WRITE_CTR = 7897; // 8 +static const uint64_t SH_FLD_ENA_WR_LEVEL = 7898; // 8 +static const uint64_t SH_FLD_ENA_ZCAL = 7899; // 8 +static const uint64_t SH_FLD_ENCD_ARRAY_SELECT = 7900; // 2 +static const uint64_t SH_FLD_ENC_BUS_LANE2RPR_MANUAL = 7901; // 4 +static const uint64_t SH_FLD_ENC_BUS_LANE2RPR_MANUAL_LEN = 7902; // 4 +static const uint64_t SH_FLD_END = 7903; // 100 +static const uint64_t SH_FLD_ENDABLE_PMU_CNT_RESET = 7904; // 1 +static const uint64_t SH_FLD_ENDPOINTS = 7905; // 1 +static const uint64_t SH_FLD_END_LANE_ID = 7906; // 8 +static const uint64_t SH_FLD_END_LANE_ID_LEN = 7907; // 8 +static const uint64_t SH_FLD_END_LEN = 7908; // 36 +static const uint64_t SH_FLD_ENH_MODE = 7909; // 162 +static const uint64_t SH_FLD_ENH_MODE_0 = 7910; // 1 +static const uint64_t SH_FLD_ENH_MODE_1 = 7911; // 1 +static const uint64_t SH_FLD_ENH_MODE_2 = 7912; // 1 +static const uint64_t SH_FLD_ENH_MODE_3 = 7913; // 1 +static const uint64_t SH_FLD_ENOP = 7914; // 43 +static const uint64_t SH_FLD_ENOP_FORCE_SG = 7915; // 43 +static const uint64_t SH_FLD_ENOP_LEN = 7916; // 43 +static const uint64_t SH_FLD_ENOP_WAIT = 7917; // 43 +static const uint64_t SH_FLD_ENOP_WAIT_LEN = 7918; // 43 +static const uint64_t SH_FLD_ENTRIES = 7919; // 1 +static const uint64_t SH_FLD_ENTRIES_LEN = 7920; // 1 +static const uint64_t SH_FLD_ENTRY = 7921; // 3 +static const uint64_t SH_FLD_ENTRY_LEN = 7922; // 3 +static const uint64_t SH_FLD_ENTRY_SEL_0_5 = 7923; // 1 +static const uint64_t SH_FLD_ENTRY_SEL_0_5_LEN = 7924; // 1 +static const uint64_t SH_FLD_EN_64_128_PB_READ = 7925; // 8 +static const uint64_t SH_FLD_EN_ALT_CR = 7926; // 8 +static const uint64_t SH_FLD_EN_ALT_ECR_ERR = 7927; // 8 +static const uint64_t SH_FLD_EN_ALT_ECR_NO_ERR = 7928; // 8 +static const uint64_t SH_FLD_EN_ARX = 7929; // 1 +static const uint64_t SH_FLD_EN_ARX_LEN = 7930; // 1 +static const uint64_t SH_FLD_EN_ATTN = 7931; // 24 +static const uint64_t SH_FLD_EN_CHARB_CMD_STALL = 7932; // 8 +static const uint64_t SH_FLD_EN_CHARB_MERGE_STALL = 7933; // 8 +static const uint64_t SH_FLD_EN_CHARB_RRQ_STALL = 7934; // 8 +static const uint64_t SH_FLD_EN_CHARB_STALL = 7935; // 4 +static const uint64_t SH_FLD_EN_CHARB_WRQ_STALL = 7936; // 8 +static const uint64_t SH_FLD_EN_CMD = 7937; // 1 +static const uint64_t SH_FLD_EN_CMD_LEN = 7938; // 1 +static const uint64_t SH_FLD_EN_CRESP = 7939; // 1 +static const uint64_t SH_FLD_EN_CRESP_LEN = 7940; // 1 +static const uint64_t SH_FLD_EN_DBG = 7941; // 4 +static const uint64_t SH_FLD_EN_DROP_PLS_F_FULL = 7942; // 8 +static const uint64_t SH_FLD_EN_EVENT_COUNT = 7943; // 1 +static const uint64_t SH_FLD_EN_FULL_SPEED = 7944; // 17 +static const uint64_t SH_FLD_EN_INSTRUC_TRACE = 7945; // 24 +static const uint64_t SH_FLD_EN_INTR_ADDR = 7946; // 17 +static const uint64_t SH_FLD_EN_MARKER_ACK = 7947; // 1 +static const uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION = 7948; // 1 +static const uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN = 7949; // 1 +static const uint64_t SH_FLD_EN_PF_CONF_RETRY = 7950; // 8 +static const uint64_t SH_FLD_EN_POLL_BACKOFF = 7951; // 1 +static const uint64_t SH_FLD_EN_RANDOM_BACKOFF = 7952; // 1 +static const uint64_t SH_FLD_EN_RESET_DD2_FIX_DIS = 7953; // 8 +static const uint64_t SH_FLD_EN_RESET_WR_DELAY_WL = 7954; // 8 +static const uint64_t SH_FLD_EN_SCRD = 7955; // 1 +static const uint64_t SH_FLD_EN_SECOND_WRBUF = 7956; // 1 +static const uint64_t SH_FLD_EN_SLV_FAIRNESS = 7957; // 1 +static const uint64_t SH_FLD_EN_SPEC_CILD_EQD = 7958; // 1 +static const uint64_t SH_FLD_EN_SPEC_CILD_IVE = 7959; // 1 +static const uint64_t SH_FLD_EN_SPEC_CILD_VPC_HW = 7960; // 1 +static const uint64_t SH_FLD_EN_SPEC_CILD_VPC_SW = 7961; // 1 +static const uint64_t SH_FLD_EN_TRACE_EXTRA = 7962; // 17 +static const uint64_t SH_FLD_EN_TRACE_STALL = 7963; // 17 +static const uint64_t SH_FLD_EN_WAIT_CYCLES = 7964; // 17 +static const uint64_t SH_FLD_EN_WRITE_MDI1_RETRY_UE = 7965; // 8 +static const uint64_t SH_FLD_EN_WT4CR_EPS_ON_LCO = 7966; // 12 +static const uint64_t SH_FLD_EN_WT4CR_EXTENDED_MODE = 7967; // 12 +static const uint64_t SH_FLD_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD = 7968; // 2 +static const uint64_t SH_FLD_EPOCH_TEST_VECTOR = 7969; // 2 +static const uint64_t SH_FLD_EPOCH_TEST_VECTOR_LEN = 7970; // 2 +static const uint64_t SH_FLD_EPOCH_VALUE = 7971; // 2 +static const uint64_t SH_FLD_EPOCH_VALUE_LEN = 7972; // 2 +static const uint64_t SH_FLD_EPSILON_COUNT = 7973; // 1 +static const uint64_t SH_FLD_EPSILON_COUNT_LEN = 7974; // 1 +static const uint64_t SH_FLD_EPSILON_DIVIDER = 7975; // 1 +static const uint64_t SH_FLD_EPSILON_DIVIDER_LEN = 7976; // 1 +static const uint64_t SH_FLD_EPS_CNT_USE_DIVIDER_EN = 7977; // 12 +static const uint64_t SH_FLD_EPS_DIVIDER_MODE = 7978; // 12 +static const uint64_t SH_FLD_EPS_DIVIDER_MODE_LEN = 7979; // 12 +static const uint64_t SH_FLD_EPS_MODE_SEL = 7980; // 12 +static const uint64_t SH_FLD_EPS_STEP_MODE = 7981; // 12 +static const uint64_t SH_FLD_EPS_STEP_MODE_LEN = 7982; // 12 +static const uint64_t SH_FLD_EQC_ARX_DATA_ECC_UE = 7983; // 1 +static const uint64_t SH_FLD_EQC_CILOAD = 7984; // 1 +static const uint64_t SH_FLD_EQC_CILOAD_LEN = 7985; // 1 +static const uint64_t SH_FLD_EQC_CISTORE = 7986; // 1 +static const uint64_t SH_FLD_EQC_CISTORE_LEN = 7987; // 1 +static const uint64_t SH_FLD_EQC_CL_INDEX_ERROR = 7988; // 1 +static const uint64_t SH_FLD_EQC_CONFIG_ERROR = 7989; // 1 +static const uint64_t SH_FLD_EQC_CRD_OR_RESP_ERROR = 7990; // 1 +static const uint64_t SH_FLD_EQC_CTRL_SRAM_ECC_UE = 7991; // 1 +static const uint64_t SH_FLD_EQC_DATA_SRAM_ECC_UE = 7992; // 1 +static const uint64_t SH_FLD_EQC_DMA = 7993; // 1 +static const uint64_t SH_FLD_EQC_DMA_LEN = 7994; // 1 +static const uint64_t SH_FLD_EQC_EOI_EQP = 7995; // 1 +static const uint64_t SH_FLD_EQC_EOI_EQP_LEN = 7996; // 1 +static const uint64_t SH_FLD_EQC_EOI_ESBE = 7997; // 1 +static const uint64_t SH_FLD_EQC_EOI_ESBE_LEN = 7998; // 1 +static const uint64_t SH_FLD_EQC_EOI_OVERFLOW = 7999; // 1 +static const uint64_t SH_FLD_EQC_EOI_TAG_ERROR = 8000; // 1 +static const uint64_t SH_FLD_EQC_PARITY_ERROR = 8001; // 1 +static const uint64_t SH_FLD_EQC_PROCESSING_ERROR = 8002; // 1 +static const uint64_t SH_FLD_EQC_PTAG_ASSIGN_ERROR = 8003; // 1 +static const uint64_t SH_FLD_EQC_PTAG_RELEASE_ERROR = 8004; // 1 +static const uint64_t SH_FLD_EQC_REPLAY_ERROR = 8005; // 1 +static const uint64_t SH_FLD_EQC_SRAM_ECC_CE = 8006; // 1 +static const uint64_t SH_FLD_EQC_STATE_SRAM_ECC_UE = 8007; // 1 +static const uint64_t SH_FLD_EQC_TAG_SRAM_ECC_UE = 8008; // 1 +static const uint64_t SH_FLD_EQC_UNLOCK_FIFO_OVERFLOW = 8009; // 1 +static const uint64_t SH_FLD_EQC_WATCH_ERROR = 8010; // 1 +static const uint64_t SH_FLD_EQD_BLOCK = 8011; // 1 +static const uint64_t SH_FLD_EQD_BLOCK_LEN = 8012; // 1 +static const uint64_t SH_FLD_EQD_DMA_READ = 8013; // 1 +static const uint64_t SH_FLD_EQD_DMA_READ_LEN = 8014; // 1 +static const uint64_t SH_FLD_EQD_DMA_WRITE = 8015; // 1 +static const uint64_t SH_FLD_EQD_DMA_WRITE_LEN = 8016; // 1 +static const uint64_t SH_FLD_EQD_INDEX = 8017; // 1 +static const uint64_t SH_FLD_EQD_INDEX_LEN = 8018; // 1 +static const uint64_t SH_FLD_EQ_POST = 8019; // 1 +static const uint64_t SH_FLD_EQ_POST_LEN = 8020; // 1 +static const uint64_t SH_FLD_ERAT_ARRAY_CE = 8021; // 1 +static const uint64_t SH_FLD_ERAT_ARRAY_PE = 8022; // 1 +static const uint64_t SH_FLD_ERAT_ARRAY_SUE = 8023; // 1 +static const uint64_t SH_FLD_ERAT_ARRAY_UE = 8024; // 1 +static const uint64_t SH_FLD_ERAT_CICO_HANG = 8025; // 1 +static const uint64_t SH_FLD_ERAT_CNTRL_ERR = 8026; // 1 +static const uint64_t SH_FLD_ERAT_DATA_POLL_SCALE = 8027; // 1 +static const uint64_t SH_FLD_ERAT_DATA_POLL_SCALE_LEN = 8028; // 1 +static const uint64_t SH_FLD_ERAT_LOCAL_CSTOP = 8029; // 1 +static const uint64_t SH_FLD_ERAT_MUX_SELECT = 8030; // 1 +static const uint64_t SH_FLD_ERAT_MUX_SELECT_LEN = 8031; // 1 +static const uint64_t SH_FLD_ERR = 8032; // 24 +static const uint64_t SH_FLD_ERR0_REG_DP16 = 8033; // 8 +static const uint64_t SH_FLD_ERR0_REG_DP16_LEN = 8034; // 8 +static const uint64_t SH_FLD_ERR1_REG_DP16 = 8035; // 8 +static const uint64_t SH_FLD_ERR1_REG_DP16_LEN = 8036; // 8 +static const uint64_t SH_FLD_ERR4_REG_DP16 = 8037; // 8 +static const uint64_t SH_FLD_ERR4_REG_DP16_LEN = 8038; // 8 +static const uint64_t SH_FLD_ERR5_REG_DP16 = 8039; // 8 +static const uint64_t SH_FLD_ERR5_REG_DP16_LEN = 8040; // 8 +static const uint64_t SH_FLD_ERROR = 8041; // 125 +static const uint64_t SH_FLD_ERROR_0 = 8042; // 9 +static const uint64_t SH_FLD_ERROR_1 = 8043; // 9 +static const uint64_t SH_FLD_ERROR_2 = 8044; // 9 +static const uint64_t SH_FLD_ERROR_3 = 8045; // 9 +static const uint64_t SH_FLD_ERROR_4 = 8046; // 9 +static const uint64_t SH_FLD_ERROR_5 = 8047; // 9 +static const uint64_t SH_FLD_ERROR_6 = 8048; // 8 +static const uint64_t SH_FLD_ERROR_7 = 8049; // 8 +static const uint64_t SH_FLD_ERROR_ADDR = 8050; // 4 +static const uint64_t SH_FLD_ERROR_ADDRESS = 8051; // 2 +static const uint64_t SH_FLD_ERROR_ADDRESS_LEN = 8052; // 2 +static const uint64_t SH_FLD_ERROR_ADDR_LEN = 8053; // 4 +static const uint64_t SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK = 8054; // 162 +static const uint64_t SH_FLD_ERROR_COARSE_RD = 8055; // 8 +static const uint64_t SH_FLD_ERROR_CONFIG = 8056; // 6 +static const uint64_t SH_FLD_ERROR_CONFIG0 = 8057; // 4 +static const uint64_t SH_FLD_ERROR_CONFIG0_LEN = 8058; // 4 +static const uint64_t SH_FLD_ERROR_CONFIG_LEN = 8059; // 6 +static const uint64_t SH_FLD_ERROR_COUNT_0 = 8060; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_0_LEN = 8061; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_1 = 8062; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_10 = 8063; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_10_LEN = 8064; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_11 = 8065; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_11_LEN = 8066; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_1_LEN = 8067; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_2 = 8068; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_2_LEN = 8069; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_3 = 8070; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_3_LEN = 8071; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_4 = 8072; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_4_LEN = 8073; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_5 = 8074; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_5_LEN = 8075; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_6 = 8076; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_6_LEN = 8077; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_7 = 8078; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_7_LEN = 8079; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_8 = 8080; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_8_LEN = 8081; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_9 = 8082; // 10 +static const uint64_t SH_FLD_ERROR_COUNT_9_LEN = 8083; // 10 +static const uint64_t SH_FLD_ERROR_CUSTOM_RD = 8084; // 8 +static const uint64_t SH_FLD_ERROR_CUSTOM_WR = 8085; // 8 +static const uint64_t SH_FLD_ERROR_DIGITAL_EYE = 8086; // 8 +static const uint64_t SH_FLD_ERROR_DQS_ALIGN = 8087; // 8 +static const uint64_t SH_FLD_ERROR_INITIAL_COARSE_WR = 8088; // 8 +static const uint64_t SH_FLD_ERROR_INITIAL_PAT_WRITE = 8089; // 8 +static const uint64_t SH_FLD_ERROR_INJECT = 8090; // 1 +static const uint64_t SH_FLD_ERROR_INJECT_ENABLE = 8091; // 1 +static const uint64_t SH_FLD_ERROR_INJECT_LEN = 8092; // 1 +static const uint64_t SH_FLD_ERROR_INJ_DCACHE = 8093; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DCSET0 = 8094; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DCSET1 = 8095; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DCSET2 = 8096; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DDIR = 8097; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DERAT = 8098; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DERAT_MULTIHIT = 8099; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DTLB = 8100; // 24 +static const uint64_t SH_FLD_ERROR_INJ_DTLB_MULTIHIT = 8101; // 24 +static const uint64_t SH_FLD_ERROR_INJ_ITLB = 8102; // 24 +static const uint64_t SH_FLD_ERROR_INJ_SETP = 8103; // 24 +static const uint64_t SH_FLD_ERROR_INJ_SLB = 8104; // 24 +static const uint64_t SH_FLD_ERROR_INJ_SLB_MULTIHIT = 8105; // 24 +static const uint64_t SH_FLD_ERROR_INJ_SLICE_DCD0 = 8106; // 24 +static const uint64_t SH_FLD_ERROR_INJ_SLICE_DCD1 = 8107; // 24 +static const uint64_t SH_FLD_ERROR_INJ_SLICE_DCD2 = 8108; // 24 +static const uint64_t SH_FLD_ERROR_LEN = 8109; // 27 +static const uint64_t SH_FLD_ERROR_MASK = 8110; // 43 +static const uint64_t SH_FLD_ERROR_MASK_LEN = 8111; // 43 +static const uint64_t SH_FLD_ERROR_MODE_LT = 8112; // 162 +static const uint64_t SH_FLD_ERROR_MODE_LT_LEN = 8113; // 162 +static const uint64_t SH_FLD_ERROR_PULSE_OR_LEVEL = 8114; // 24 +static const uint64_t SH_FLD_ERROR_RATE = 8115; // 10 +static const uint64_t SH_FLD_ERROR_RATE_LEN = 8116; // 10 +static const uint64_t SH_FLD_ERROR_RDCLK_ALIGN = 8117; // 8 +static const uint64_t SH_FLD_ERROR_READ_CTR = 8118; // 8 +static const uint64_t SH_FLD_ERROR_RECOVERY_COMPLETE = 8119; // 2 +static const uint64_t SH_FLD_ERROR_RECOVERY_INITIATED = 8120; // 2 +static const uint64_t SH_FLD_ERROR_STATE = 8121; // 4 +static const uint64_t SH_FLD_ERROR_VREF = 8122; // 8 +static const uint64_t SH_FLD_ERROR_WRITE_CTR = 8123; // 8 +static const uint64_t SH_FLD_ERROR_WR_LEVEL = 8124; // 8 +static const uint64_t SH_FLD_ERRS = 8125; // 256 +static const uint64_t SH_FLD_ERRS_INJ = 8126; // 4 +static const uint64_t SH_FLD_ERRS_INJ_LEN = 8127; // 4 +static const uint64_t SH_FLD_ERRS_LEN = 8128; // 140 +static const uint64_t SH_FLD_ERR_ADDR_BEYOND_RANGE = 8129; // 1 +static const uint64_t SH_FLD_ERR_ADDR_OVERLAP = 8130; // 1 +static const uint64_t SH_FLD_ERR_BRK0 = 8131; // 1 +static const uint64_t SH_FLD_ERR_BRK0_LEN = 8132; // 1 +static const uint64_t SH_FLD_ERR_BRK1 = 8133; // 1 +static const uint64_t SH_FLD_ERR_BRK1_LEN = 8134; // 1 +static const uint64_t SH_FLD_ERR_BRK2 = 8135; // 1 +static const uint64_t SH_FLD_ERR_BRK2_LEN = 8136; // 1 +static const uint64_t SH_FLD_ERR_BRK3 = 8137; // 1 +static const uint64_t SH_FLD_ERR_BRK3_LEN = 8138; // 1 +static const uint64_t SH_FLD_ERR_BRK4 = 8139; // 1 +static const uint64_t SH_FLD_ERR_BRK4_LEN = 8140; // 1 +static const uint64_t SH_FLD_ERR_BRK5 = 8141; // 1 +static const uint64_t SH_FLD_ERR_BRK5_LEN = 8142; // 1 +static const uint64_t SH_FLD_ERR_CMD_OVERRUN = 8143; // 1 +static const uint64_t SH_FLD_ERR_CQ = 8144; // 16 +static const uint64_t SH_FLD_ERR_CQ_LEN = 8145; // 16 +static const uint64_t SH_FLD_ERR_DETAIL = 8146; // 16 +static const uint64_t SH_FLD_ERR_DETAIL_LEN = 8147; // 16 +static const uint64_t SH_FLD_ERR_FSM_DP16 = 8148; // 8 +static const uint64_t SH_FLD_ERR_FSM_DP16_LEN = 8149; // 8 +static const uint64_t SH_FLD_ERR_INJ = 8150; // 252 +static const uint64_t SH_FLD_ERR_INJ_ACTION = 8151; // 2 +static const uint64_t SH_FLD_ERR_INJ_ARRAY_SEL = 8152; // 2 +static const uint64_t SH_FLD_ERR_INJ_ARRAY_SEL_LEN = 8153; // 2 +static const uint64_t SH_FLD_ERR_INJ_A_BER_SEL = 8154; // 6 +static const uint64_t SH_FLD_ERR_INJ_A_BER_SEL_LEN = 8155; // 6 +static const uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL = 8156; // 6 +static const uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL_LEN = 8157; // 6 +static const uint64_t SH_FLD_ERR_INJ_A_ENABLE = 8158; // 116 +static const uint64_t SH_FLD_ERR_INJ_A_FINE_SEL = 8159; // 6 +static const uint64_t SH_FLD_ERR_INJ_A_FINE_SEL_LEN = 8160; // 6 +static const uint64_t SH_FLD_ERR_INJ_B_BER_SEL = 8161; // 6 +static const uint64_t SH_FLD_ERR_INJ_B_BER_SEL_LEN = 8162; // 6 +static const uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL = 8163; // 6 +static const uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL_LEN = 8164; // 6 +static const uint64_t SH_FLD_ERR_INJ_B_ENABLE = 8165; // 116 +static const uint64_t SH_FLD_ERR_INJ_B_FINE_SEL = 8166; // 6 +static const uint64_t SH_FLD_ERR_INJ_B_FINE_SEL_LEN = 8167; // 6 +static const uint64_t SH_FLD_ERR_INJ_CLOCK_ENABLE = 8168; // 6 +static const uint64_t SH_FLD_ERR_INJ_ENABLE = 8169; // 8 +static const uint64_t SH_FLD_ERR_INJ_LEN = 8170; // 136 +static const uint64_t SH_FLD_ERR_INJ_RECOV = 8171; // 24 +static const uint64_t SH_FLD_ERR_INJ_SLS_ALL_CMD = 8172; // 4 +static const uint64_t SH_FLD_ERR_INJ_SLS_CMD = 8173; // 4 +static const uint64_t SH_FLD_ERR_INJ_SLS_CMD_LEN = 8174; // 4 +static const uint64_t SH_FLD_ERR_INJ_SLS_MODE = 8175; // 4 +static const uint64_t SH_FLD_ERR_INJ_SLS_RECAL = 8176; // 4 +static const uint64_t SH_FLD_ERR_INJ_STATUS = 8177; // 2 +static const uint64_t SH_FLD_ERR_INJ_TYPE = 8178; // 2 +static const uint64_t SH_FLD_ERR_LVL = 8179; // 16 +static const uint64_t SH_FLD_ERR_LVL_LEN = 8180; // 16 +static const uint64_t SH_FLD_ERR_RSVD0 = 8181; // 16 +static const uint64_t SH_FLD_ERR_RSVD0_LEN = 8182; // 16 +static const uint64_t SH_FLD_ERR_SET0 = 8183; // 8 +static const uint64_t SH_FLD_ERR_SET1 = 8184; // 8 +static const uint64_t SH_FLD_ERR_SET2 = 8185; // 8 +static const uint64_t SH_FLD_ERR_SET3 = 8186; // 8 +static const uint64_t SH_FLD_ERR_SET4 = 8187; // 8 +static const uint64_t SH_FLD_ERR_SET5 = 8188; // 8 +static const uint64_t SH_FLD_ERR_VLD = 8189; // 16 +static const uint64_t SH_FLD_ESB_OR_LSI_INTERRUPTS = 8190; // 1 +static const uint64_t SH_FLD_ESC1_PRIORITY = 8191; // 1 +static const uint64_t SH_FLD_ESC1_PRIORITY_LEN = 8192; // 1 +static const uint64_t SH_FLD_ESC1_RSD = 8193; // 1 +static const uint64_t SH_FLD_ESC1_RSD_LEN = 8194; // 1 +static const uint64_t SH_FLD_ESC2_PRIORITY = 8195; // 1 +static const uint64_t SH_FLD_ESC2_PRIORITY_LEN = 8196; // 1 +static const uint64_t SH_FLD_ESC2_RSD = 8197; // 1 +static const uint64_t SH_FLD_ESC2_RSD_LEN = 8198; // 1 +static const uint64_t SH_FLD_ESCAPE_ADDRESS = 8199; // 1 +static const uint64_t SH_FLD_ESCAPE_ADDRESS_LEN = 8200; // 1 +static const uint64_t SH_FLD_ESL = 8201; // 96 +static const uint64_t SH_FLD_ESR_RSVD_19 = 8202; // 1 +static const uint64_t SH_FLD_EVENT = 8203; // 6 +static const uint64_t SH_FLD_EVENT0 = 8204; // 21 +static const uint64_t SH_FLD_EVENT0_COUNTER = 8205; // 8 +static const uint64_t SH_FLD_EVENT0_COUNTER_LEN = 8206; // 8 +static const uint64_t SH_FLD_EVENT0_LEN = 8207; // 21 +static const uint64_t SH_FLD_EVENT0_SEL = 8208; // 2 +static const uint64_t SH_FLD_EVENT1 = 8209; // 21 +static const uint64_t SH_FLD_EVENT1_COUNTER = 8210; // 8 +static const uint64_t SH_FLD_EVENT1_COUNTER_LEN = 8211; // 8 +static const uint64_t SH_FLD_EVENT1_LEN = 8212; // 21 +static const uint64_t SH_FLD_EVENT1_SEL = 8213; // 2 +static const uint64_t SH_FLD_EVENT1_SEL_LEN = 8214; // 2 +static const uint64_t SH_FLD_EVENT2 = 8215; // 21 +static const uint64_t SH_FLD_EVENT2HALT_DELAY = 8216; // 1 +static const uint64_t SH_FLD_EVENT2HALT_DELAY_LEN = 8217; // 1 +static const uint64_t SH_FLD_EVENT2HALT_EN = 8218; // 1 +static const uint64_t SH_FLD_EVENT2HALT_EN_LEN = 8219; // 1 +static const uint64_t SH_FLD_EVENT2HALT_GPE0 = 8220; // 1 +static const uint64_t SH_FLD_EVENT2HALT_GPE1 = 8221; // 1 +static const uint64_t SH_FLD_EVENT2HALT_GPE2 = 8222; // 1 +static const uint64_t SH_FLD_EVENT2HALT_GPE3 = 8223; // 1 +static const uint64_t SH_FLD_EVENT2HALT_HALT_STATE = 8224; // 1 +static const uint64_t SH_FLD_EVENT2HALT_MODE = 8225; // 1 +static const uint64_t SH_FLD_EVENT2HALT_MODE_LEN = 8226; // 1 +static const uint64_t SH_FLD_EVENT2HALT_OCC = 8227; // 1 +static const uint64_t SH_FLD_EVENT2_COUNTER = 8228; // 8 +static const uint64_t SH_FLD_EVENT2_COUNTER_LEN = 8229; // 8 +static const uint64_t SH_FLD_EVENT2_LEN = 8230; // 21 +static const uint64_t SH_FLD_EVENT2_SEL = 8231; // 2 +static const uint64_t SH_FLD_EVENT2_SEL_LEN = 8232; // 2 +static const uint64_t SH_FLD_EVENT3 = 8233; // 21 +static const uint64_t SH_FLD_EVENT3_COUNTER = 8234; // 8 +static const uint64_t SH_FLD_EVENT3_COUNTER_LEN = 8235; // 8 +static const uint64_t SH_FLD_EVENT3_LEN = 8236; // 21 +static const uint64_t SH_FLD_EVENT3_SEL = 8237; // 2 +static const uint64_t SH_FLD_EVENT3_SEL_LEN = 8238; // 2 +static const uint64_t SH_FLD_EVENTCNT = 8239; // 3 +static const uint64_t SH_FLD_EVENTCNT_LEN = 8240; // 3 +static const uint64_t SH_FLD_EVENT_BUS_EN = 8241; // 4 +static const uint64_t SH_FLD_EVENT_BUS_ENABLE = 8242; // 4 +static const uint64_t SH_FLD_EVENT_BUS_EN_LEN = 8243; // 4 +static const uint64_t SH_FLD_EVENT_BUS_SELECTS = 8244; // 12 +static const uint64_t SH_FLD_EVENT_BUS_SELECTS_LEN = 8245; // 12 +static const uint64_t SH_FLD_EVENT_LEN = 8246; // 6 +static const uint64_t SH_FLD_EVENT_MUX_SELECTS = 8247; // 24 +static const uint64_t SH_FLD_EVENT_MUX_SELECTS_LEN = 8248; // 24 +static const uint64_t SH_FLD_EVIRT = 8249; // 96 +static const uint64_t SH_FLD_EXACT_RESET_C3_ON_TO = 8250; // 86 +static const uint64_t SH_FLD_EXACT_TO_MODE = 8251; // 86 +static const uint64_t SH_FLD_EXBIST_MODE = 8252; // 6 +static const uint64_t SH_FLD_EXIT_1 = 8253; // 128 +static const uint64_t SH_FLD_EXIT_CRITERION_A_N = 8254; // 96 +static const uint64_t SH_FLD_EXTADDR = 8255; // 6 +static const uint64_t SH_FLD_EXTADDR_LEN = 8256; // 6 +static const uint64_t SH_FLD_EXTENDED_STORE_ON_TRIG_MODE = 8257; // 72 +static const uint64_t SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN = 8258; // 72 +static const uint64_t SH_FLD_EXTEND_TIMO = 8259; // 2 +static const uint64_t SH_FLD_EXTEND_TRIG_MODE = 8260; // 90 +static const uint64_t SH_FLD_EXTEND_TRIG_MODE_LEN = 8261; // 90 +static const uint64_t SH_FLD_EXTERNAL_ERROR = 8262; // 1 +static const uint64_t SH_FLD_EXTERNAL_TRAP = 8263; // 2 +static const uint64_t SH_FLD_EXTERNAL_TRAP_MASK = 8264; // 1 +static const uint64_t SH_FLD_EXTERNAL_XSTOP = 8265; // 4 +static const uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2 = 8266; // 1 +static const uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2_LEN = 8267; // 1 +static const uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3 = 8268; // 1 +static const uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3_LEN = 8269; // 1 +static const uint64_t SH_FLD_EXTREME_DROOP_ERR = 8270; // 12 +static const uint64_t SH_FLD_EXTREME_DROOP_EVENT_CTR = 8271; // 12 +static const uint64_t SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN = 8272; // 12 +static const uint64_t SH_FLD_EXTREME_EVENT_THRESHOLD = 8273; // 12 +static const uint64_t SH_FLD_EXTREME_EVENT_THRESHOLD_LEN = 8274; // 12 +static const uint64_t SH_FLD_EXT_EBB_EXIT_ENABLE = 8275; // 96 +static const uint64_t SH_FLD_EXT_EXIT_ENABLE = 8276; // 96 +static const uint64_t SH_FLD_EXT_INTERRUPT = 8277; // 1 +static const uint64_t SH_FLD_EXT_RESUME_EXIT_ENABLE = 8278; // 96 +static const uint64_t SH_FLD_EXT_TRIG_ON_FREEZE = 8279; // 43 +static const uint64_t SH_FLD_EXT_TRIG_ON_STOP = 8280; // 43 +static const uint64_t SH_FLD_EYE_OPT_DONE = 8281; // 4 +static const uint64_t SH_FLD_EYE_OPT_FAILED = 8282; // 4 +static const uint64_t SH_FLD_E_BIST_EN = 8283; // 2 +static const uint64_t SH_FLD_E_CONTROLS = 8284; // 48 +static const uint64_t SH_FLD_E_CONTROLS_LEN = 8285; // 48 +static const uint64_t SH_FLD_E_CTLE_COARSE = 8286; // 48 +static const uint64_t SH_FLD_E_CTLE_COARSE_LEN = 8287; // 48 +static const uint64_t SH_FLD_E_CTLE_GAIN = 8288; // 48 +static const uint64_t SH_FLD_E_CTLE_GAIN_LEN = 8289; // 48 +static const uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN = 8290; // 48 +static const uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN = 8291; // 48 +static const uint64_t SH_FLD_E_INTEG_COARSE_GAIN = 8292; // 48 +static const uint64_t SH_FLD_E_INTEG_COARSE_GAIN_LEN = 8293; // 48 +static const uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN = 8294; // 48 +static const uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN = 8295; // 48 +static const uint64_t SH_FLD_E_OFFSET = 8296; // 48 +static const uint64_t SH_FLD_E_OFFSET_E = 8297; // 48 +static const uint64_t SH_FLD_E_OFFSET_E_LEN = 8298; // 48 +static const uint64_t SH_FLD_E_OFFSET_LEN = 8299; // 48 +static const uint64_t SH_FLD_E_TARG_MIN = 8300; // 1 +static const uint64_t SH_FLD_E_TARG_MIN_LEN = 8301; // 1 +static const uint64_t SH_FLD_FAB_CRESP_MATCH = 8302; // 96 +static const uint64_t SH_FLD_FAB_CRESP_MATCH_LEN = 8303; // 96 +static const uint64_t SH_FLD_FAB_TYPE_MATCH = 8304; // 96 +static const uint64_t SH_FLD_FAB_TYPE_MATCH_LEN = 8305; // 96 +static const uint64_t SH_FLD_FACTOR = 8306; // 24 +static const uint64_t SH_FLD_FACTOR_LEN = 8307; // 24 +static const uint64_t SH_FLD_FAIL = 8308; // 4 +static const uint64_t SH_FLD_FAILED = 8309; // 8 +static const uint64_t SH_FLD_FAILED_LEN = 8310; // 8 +static const uint64_t SH_FLD_FAILED_LINK_ON_INTERRUPT = 8311; // 1 +static const uint64_t SH_FLD_FAILING_OPB_MASTER_ACT = 8312; // 3 +static const uint64_t SH_FLD_FAILING_OPB_MASTER_ACT_LEN = 8313; // 3 +static const uint64_t SH_FLD_FAILING_OPB_MASTER_FRST = 8314; // 3 +static const uint64_t SH_FLD_FAILING_OPB_MASTER_FRST_LEN = 8315; // 3 +static const uint64_t SH_FLD_FAIL_RCD = 8316; // 2 +static const uint64_t SH_FLD_FAIL_REG = 8317; // 1 +static const uint64_t SH_FLD_FAIL_REG_LEN = 8318; // 1 +static const uint64_t SH_FLD_FAIL_TYPE = 8319; // 2 +static const uint64_t SH_FLD_FAIL_TYPE_LEN = 8320; // 2 +static const uint64_t SH_FLD_FARB_CAL_RECVFSM_1HOT = 8321; // 8 +static const uint64_t SH_FLD_FARB_CMD_PE_HOLD_OUT = 8322; // 8 +static const uint64_t SH_FLD_FARB_PE = 8323; // 8 +static const uint64_t SH_FLD_FARR = 8324; // 43 +static const uint64_t SH_FLD_FASTPATH_LIMIT = 8325; // 8 +static const uint64_t SH_FLD_FASTPATH_LIMIT_LEN = 8326; // 8 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 = 8327; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN = 8328; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 = 8329; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN = 8330; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 = 8331; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN = 8332; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 = 8333; // 1 +static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN = 8334; // 1 +static const uint64_t SH_FLD_FAST_SB_LOOKUP_DISABLE = 8335; // 1 +static const uint64_t SH_FLD_FAST_SIM_CNTR = 8336; // 8 +static const uint64_t SH_FLD_FATAL_CNFG_HOLD_OUT = 8337; // 2 +static const uint64_t SH_FLD_FBC = 8338; // 2 +static const uint64_t SH_FLD_FBC_ADDRESS = 8339; // 1 +static const uint64_t SH_FLD_FBC_ADDRESS_ERROR = 8340; // 1 +static const uint64_t SH_FLD_FBC_ADDRESS_LEN = 8341; // 1 +static const uint64_t SH_FLD_FBC_ADDR_DONE = 8342; // 1 +static const uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT = 8343; // 1 +static const uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 8344; // 1 +static const uint64_t SH_FLD_FBC_ALTD_BUSY = 8345; // 1 +static const uint64_t SH_FLD_FBC_AUTOINC_ERROR = 8346; // 1 +static const uint64_t SH_FLD_FBC_AUTO_INC = 8347; // 1 +static const uint64_t SH_FLD_FBC_AXTYPE = 8348; // 1 +static const uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT = 8349; // 1 +static const uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 8350; // 1 +static const uint64_t SH_FLD_FBC_BUS0_STG0_SEL = 8351; // 1 +static const uint64_t SH_FLD_FBC_BUS0_STG0_SEL_LEN = 8352; // 1 +static const uint64_t SH_FLD_FBC_BUS0_STG1_SEL = 8353; // 1 +static const uint64_t SH_FLD_FBC_BUS0_STG2_SEL = 8354; // 1 +static const uint64_t SH_FLD_FBC_BUS1_STG0_SEL = 8355; // 1 +static const uint64_t SH_FLD_FBC_BUS1_STG0_SEL_LEN = 8356; // 1 +static const uint64_t SH_FLD_FBC_BUS1_STG1_SEL = 8357; // 1 +static const uint64_t SH_FLD_FBC_BUS1_STG2_SEL = 8358; // 1 +static const uint64_t SH_FLD_FBC_CLEAR_STATUS = 8359; // 1 +static const uint64_t SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS = 8360; // 1 +static const uint64_t SH_FLD_FBC_COMMAND_ERROR = 8361; // 1 +static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_CE_DET = 8362; // 1 +static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_SUE_DET = 8363; // 1 +static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_UE_DET = 8364; // 1 +static const uint64_t SH_FLD_FBC_CRESP_VALUE = 8365; // 1 +static const uint64_t SH_FLD_FBC_CRESP_VALUE_LEN = 8366; // 1 +static const uint64_t SH_FLD_FBC_DATA_DONE = 8367; // 1 +static const uint64_t SH_FLD_FBC_DATA_ONLY = 8368; // 1 +static const uint64_t SH_FLD_FBC_DIN_ECC_CHK_DIS = 8369; // 1 +static const uint64_t SH_FLD_FBC_DISABLE = 8370; // 1 +static const uint64_t SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT = 8371; // 1 +static const uint64_t SH_FLD_FBC_DROP_PRIORITY = 8372; // 1 +static const uint64_t SH_FLD_FBC_DROP_PRIORITY_MAX = 8373; // 1 +static const uint64_t SH_FLD_FBC_ECC_CE = 8374; // 1 +static const uint64_t SH_FLD_FBC_ECC_SUE = 8375; // 1 +static const uint64_t SH_FLD_FBC_ECC_UE = 8376; // 1 +static const uint64_t SH_FLD_FBC_INV_AMORT_DIS = 8377; // 1 +static const uint64_t SH_FLD_FBC_LEN = 8378; // 2 +static const uint64_t SH_FLD_FBC_LFSR_DIS = 8379; // 1 +static const uint64_t SH_FLD_FBC_LOCKED = 8380; // 1 +static const uint64_t SH_FLD_FBC_LOCK_ID = 8381; // 1 +static const uint64_t SH_FLD_FBC_LOCK_ID_LEN = 8382; // 1 +static const uint64_t SH_FLD_FBC_LOCK_PICK = 8383; // 1 +static const uint64_t SH_FLD_FBC_LXSTOP_ERR_DET = 8384; // 1 +static const uint64_t SH_FLD_FBC_OVERRUN_ERROR = 8385; // 1 +static const uint64_t SH_FLD_FBC_OVERWRITE_PBINIT = 8386; // 1 +static const uint64_t SH_FLD_FBC_PBINIT_MISSING = 8387; // 1 +static const uint64_t SH_FLD_FBC_PB_DATA_HANG_ERR = 8388; // 1 +static const uint64_t SH_FLD_FBC_PB_OP_HANG_ERR = 8389; // 1 +static const uint64_t SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR = 8390; // 1 +static const uint64_t SH_FLD_FBC_PB_UNEXPECT_DATA_ERR = 8391; // 1 +static const uint64_t SH_FLD_FBC_PIB_DIRECT = 8392; // 1 +static const uint64_t SH_FLD_FBC_PIB_DIRECT_DONE = 8393; // 1 +static const uint64_t SH_FLD_FBC_PIB_ERROR = 8394; // 1 +static const uint64_t SH_FLD_FBC_PIB_ERROR_LEN = 8395; // 1 +static const uint64_t SH_FLD_FBC_RESET = 8396; // 1 +static const uint64_t SH_FLD_FBC_RESET_FSM = 8397; // 1 +static const uint64_t SH_FLD_FBC_RNW = 8398; // 1 +static const uint64_t SH_FLD_FBC_SCOPE = 8399; // 1 +static const uint64_t SH_FLD_FBC_SCOPE_LEN = 8400; // 1 +static const uint64_t SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS = 8401; // 1 +static const uint64_t SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS = 8402; // 1 +static const uint64_t SH_FLD_FBC_START_OP = 8403; // 1 +static const uint64_t SH_FLD_FBC_TSIZE = 8404; // 1 +static const uint64_t SH_FLD_FBC_TSIZE_LEN = 8405; // 1 +static const uint64_t SH_FLD_FBC_TTYPE = 8406; // 1 +static const uint64_t SH_FLD_FBC_TTYPE_LEN = 8407; // 1 +static const uint64_t SH_FLD_FBC_WAIT_CMD_ARBIT = 8408; // 1 +static const uint64_t SH_FLD_FBC_WAIT_PIB_DIRECT = 8409; // 1 +static const uint64_t SH_FLD_FBC_WAIT_RESP = 8410; // 1 +static const uint64_t SH_FLD_FBC_WITH_PBINIT_LOW_WAIT = 8411; // 1 +static const uint64_t SH_FLD_FBC_WITH_POST_INIT = 8412; // 1 +static const uint64_t SH_FLD_FBC_WITH_PRE_QUIESCE = 8413; // 1 +static const uint64_t SH_FLD_FBC_WITH_TM_QUIESCE = 8414; // 1 +static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_CE_DET = 8415; // 1 +static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_SUE_DET = 8416; // 1 +static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_UE_DET = 8417; // 1 +static const uint64_t SH_FLD_FBC_XLAT_ECC_CHK_DIS = 8418; // 1 +static const uint64_t SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS = 8419; // 1 +static const uint64_t SH_FLD_FBC_XLAT_PROT_ERR_DET = 8420; // 1 +static const uint64_t SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS = 8421; // 1 +static const uint64_t SH_FLD_FBC_XLAT_TIMEOUT_DET = 8422; // 1 +static const uint64_t SH_FLD_FC = 8423; // 96 +static const uint64_t SH_FLD_FC1H = 8424; // 96 +static const uint64_t SH_FLD_FC1M0 = 8425; // 96 +static const uint64_t SH_FLD_FC1M1 = 8426; // 96 +static const uint64_t SH_FLD_FC1P = 8427; // 96 +static const uint64_t SH_FLD_FC1PC = 8428; // 96 +static const uint64_t SH_FLD_FC1S = 8429; // 96 +static const uint64_t SH_FLD_FC1TA = 8430; // 96 +static const uint64_t SH_FLD_FC1TI = 8431; // 96 +static const uint64_t SH_FLD_FC1WAIT = 8432; // 96 +static const uint64_t SH_FLD_FC1_4 = 8433; // 96 +static const uint64_t SH_FLD_FC2H = 8434; // 96 +static const uint64_t SH_FLD_FC2M0 = 8435; // 96 +static const uint64_t SH_FLD_FC2M1 = 8436; // 96 +static const uint64_t SH_FLD_FC2P = 8437; // 96 +static const uint64_t SH_FLD_FC2PC = 8438; // 96 +static const uint64_t SH_FLD_FC2S = 8439; // 96 +static const uint64_t SH_FLD_FC2TA = 8440; // 96 +static const uint64_t SH_FLD_FC2TI = 8441; // 96 +static const uint64_t SH_FLD_FC2WAIT = 8442; // 96 +static const uint64_t SH_FLD_FC3H = 8443; // 96 +static const uint64_t SH_FLD_FC3M0 = 8444; // 96 +static const uint64_t SH_FLD_FC3M1 = 8445; // 96 +static const uint64_t SH_FLD_FC3P = 8446; // 96 +static const uint64_t SH_FLD_FC3PC = 8447; // 96 +static const uint64_t SH_FLD_FC3S = 8448; // 96 +static const uint64_t SH_FLD_FC3TA = 8449; // 96 +static const uint64_t SH_FLD_FC3TI = 8450; // 96 +static const uint64_t SH_FLD_FC3WAIT = 8451; // 96 +static const uint64_t SH_FLD_FC4H = 8452; // 96 +static const uint64_t SH_FLD_FC4M0 = 8453; // 96 +static const uint64_t SH_FLD_FC4M1 = 8454; // 96 +static const uint64_t SH_FLD_FC4P = 8455; // 96 +static const uint64_t SH_FLD_FC4PC = 8456; // 96 +static const uint64_t SH_FLD_FC4S = 8457; // 96 +static const uint64_t SH_FLD_FC4TA = 8458; // 96 +static const uint64_t SH_FLD_FC4TI = 8459; // 96 +static const uint64_t SH_FLD_FC4WAIT = 8460; // 96 +static const uint64_t SH_FLD_FC56WAIT = 8461; // 96 +static const uint64_t SH_FLD_FC5H = 8462; // 96 +static const uint64_t SH_FLD_FC5M0 = 8463; // 96 +static const uint64_t SH_FLD_FC5M1 = 8464; // 96 +static const uint64_t SH_FLD_FC5P = 8465; // 96 +static const uint64_t SH_FLD_FC5PC = 8466; // 96 +static const uint64_t SH_FLD_FC5S = 8467; // 96 +static const uint64_t SH_FLD_FC5TA = 8468; // 96 +static const uint64_t SH_FLD_FC5TI = 8469; // 96 +static const uint64_t SH_FLD_FC5WAIT = 8470; // 96 +static const uint64_t SH_FLD_FC5_6 = 8471; // 96 +static const uint64_t SH_FLD_FC6H = 8472; // 96 +static const uint64_t SH_FLD_FC6M0 = 8473; // 96 +static const uint64_t SH_FLD_FC6M1 = 8474; // 96 +static const uint64_t SH_FLD_FC6P = 8475; // 96 +static const uint64_t SH_FLD_FC6PC = 8476; // 96 +static const uint64_t SH_FLD_FC6S = 8477; // 96 +static const uint64_t SH_FLD_FC6TA = 8478; // 96 +static const uint64_t SH_FLD_FC6TI = 8479; // 96 +static const uint64_t SH_FLD_FC6WAIT = 8480; // 96 +static const uint64_t SH_FLD_FCECE = 8481; // 96 +static const uint64_t SH_FLD_FCH = 8482; // 96 +static const uint64_t SH_FLD_FCM0 = 8483; // 96 +static const uint64_t SH_FLD_FCM1 = 8484; // 96 +static const uint64_t SH_FLD_FCNTS = 8485; // 96 +static const uint64_t SH_FLD_FCP = 8486; // 96 +static const uint64_t SH_FLD_FCPC = 8487; // 96 +static const uint64_t SH_FLD_FCS = 8488; // 96 +static const uint64_t SH_FLD_FCSS = 8489; // 96 +static const uint64_t SH_FLD_FCTA = 8490; // 96 +static const uint64_t SH_FLD_FCTI = 8491; // 96 +static const uint64_t SH_FLD_FCTM = 8492; // 96 +static const uint64_t SH_FLD_FCWAIT = 8493; // 96 +static const uint64_t SH_FLD_FE0 = 8494; // 96 +static const uint64_t SH_FLD_FE1 = 8495; // 96 +static const uint64_t SH_FLD_FENCE = 8496; // 4 +static const uint64_t SH_FLD_FENCE0 = 8497; // 15 +static const uint64_t SH_FLD_FENCE0_DC = 8498; // 3 +static const uint64_t SH_FLD_FENCE0_LEN = 8499; // 15 +static const uint64_t SH_FLD_FENCE1 = 8500; // 15 +static const uint64_t SH_FLD_FENCE1_DC = 8501; // 3 +static const uint64_t SH_FLD_FENCE1_LEN = 8502; // 15 +static const uint64_t SH_FLD_FENCE2_DC = 8503; // 3 +static const uint64_t SH_FLD_FENCE3_DC = 8504; // 3 +static const uint64_t SH_FLD_FENCE4_DC = 8505; // 3 +static const uint64_t SH_FLD_FENCE5_DC = 8506; // 3 +static const uint64_t SH_FLD_FENCE6_DC = 8507; // 3 +static const uint64_t SH_FLD_FENCE_EISR = 8508; // 12 +static const uint64_t SH_FLD_FENCE_EN = 8509; // 43 +static const uint64_t SH_FLD_FENCE_GX_INTERFACE = 8510; // 1 +static const uint64_t SH_FLD_FENCE_IO_INTERFACE = 8511; // 1 +static const uint64_t SH_FLD_FENCE_TLBIE = 8512; // 12 +static const uint64_t SH_FLD_FFE_BOOST_EN = 8513; // 6 +static const uint64_t SH_FLD_FF_BYPASS = 8514; // 6 +static const uint64_t SH_FLD_FF_SLEWRATE = 8515; // 6 +static const uint64_t SH_FLD_FF_SLEWRATE_LEN = 8516; // 6 +static const uint64_t SH_FLD_FGAT_0 = 8517; // 2 +static const uint64_t SH_FLD_FGAT_1 = 8518; // 1 +static const uint64_t SH_FLD_FGAT_2 = 8519; // 1 +static const uint64_t SH_FLD_FGAT_3 = 8520; // 1 +static const uint64_t SH_FLD_FIELD = 8521; // 9 +static const uint64_t SH_FLD_FIELD_LEN = 8522; // 9 +static const uint64_t SH_FLD_FIFO_BITS_READ0_0 = 8523; // 3 +static const uint64_t SH_FLD_FIFO_BITS_READ0_0_LEN = 8524; // 3 +static const uint64_t SH_FLD_FIFO_BITS_READ0_1 = 8525; // 2 +static const uint64_t SH_FLD_FIFO_BITS_READ0_1_LEN = 8526; // 2 +static const uint64_t SH_FLD_FIFO_BITS_READ0_2 = 8527; // 2 +static const uint64_t SH_FLD_FIFO_BITS_READ0_2_LEN = 8528; // 2 +static const uint64_t SH_FLD_FIFO_BITS_READ0_3 = 8529; // 2 +static const uint64_t SH_FLD_FIFO_BITS_READ0_3_LEN = 8530; // 2 +static const uint64_t SH_FLD_FIFO_BITS_READ2_0 = 8531; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_0_LEN = 8532; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_1 = 8533; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_1_LEN = 8534; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_2 = 8535; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_2_LEN = 8536; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_3 = 8537; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ2_3_LEN = 8538; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_0 = 8539; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_0_LEN = 8540; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_1 = 8541; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_1_LEN = 8542; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_2 = 8543; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_2_LEN = 8544; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_3 = 8545; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ3_3_LEN = 8546; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_0 = 8547; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_0_LEN = 8548; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_1 = 8549; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_1_LEN = 8550; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_2 = 8551; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_2_LEN = 8552; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_3 = 8553; // 1 +static const uint64_t SH_FLD_FIFO_BITS_READ4_3_LEN = 8554; // 1 +static const uint64_t SH_FLD_FIFO_DLY_CFG = 8555; // 120 +static const uint64_t SH_FLD_FIFO_DLY_CFG_LEN = 8556; // 120 +static const uint64_t SH_FLD_FIFO_EMPTY = 8557; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT = 8558; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_0 = 8559; // 2 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_0_LEN = 8560; // 2 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_1 = 8561; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_1_LEN = 8562; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_2 = 8563; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_2_LEN = 8564; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_3 = 8565; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_3_LEN = 8566; // 1 +static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_LEN = 8567; // 1 +static const uint64_t SH_FLD_FIFO_EOT_FLAGS = 8568; // 1 +static const uint64_t SH_FLD_FIFO_EOT_FLAGS_LEN = 8569; // 1 +static const uint64_t SH_FLD_FIFO_FINAL_L2U_DLY = 8570; // 4 +static const uint64_t SH_FLD_FIFO_FINAL_L2U_DLY_LEN = 8571; // 4 +static const uint64_t SH_FLD_FIFO_FULL = 8572; // 7 +static const uint64_t SH_FLD_FIFO_HALF_WIDTH_MODE = 8573; // 140 +static const uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY = 8574; // 4 +static const uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY_LEN = 8575; // 4 +static const uint64_t SH_FLD_FIFO_L2U_DLY = 8576; // 188 +static const uint64_t SH_FLD_FIFO_L2U_DLY_LEN = 8577; // 188 +static const uint64_t SH_FLD_FIFO_VALID_FLAGS = 8578; // 1 +static const uint64_t SH_FLD_FIFO_VALID_FLAGS_LEN = 8579; // 1 +static const uint64_t SH_FLD_FILTDIVSEL = 8580; // 3 +static const uint64_t SH_FLD_FILTDIVSEL_LEN = 8581; // 3 +static const uint64_t SH_FLD_FILTER = 8582; // 2 +static const uint64_t SH_FLD_FILTER_LEN = 8583; // 2 +static const uint64_t SH_FLD_FILTER_MODE = 8584; // 6 +static const uint64_t SH_FLD_FILTER_MODE_LEN = 8585; // 6 +static const uint64_t SH_FLD_FINAL_VDM_DATA01 = 8586; // 12 +static const uint64_t SH_FLD_FINAL_VDM_DATA01_LEN = 8587; // 12 +static const uint64_t SH_FLD_FINE_CAL_STEP_SIZE = 8588; // 8 +static const uint64_t SH_FLD_FINE_CAL_STEP_SIZE_LEN = 8589; // 8 +static const uint64_t SH_FLD_FIR = 8590; // 48 +static const uint64_t SH_FLD_FIR0_CR0_ATAG_PERR = 8591; // 12 +static const uint64_t SH_FLD_FIR0_CR0_TTAG_PERR = 8592; // 12 +static const uint64_t SH_FLD_FIR0_CR1_ATAG_PERR = 8593; // 12 +static const uint64_t SH_FLD_FIR0_CR1_TTAG_PERR = 8594; // 12 +static const uint64_t SH_FLD_FIR0_CR2_ATAG_PERR = 8595; // 12 +static const uint64_t SH_FLD_FIR0_CR2_TTAG_PERR = 8596; // 12 +static const uint64_t SH_FLD_FIR0_CR3_ATAG_PERR = 8597; // 12 +static const uint64_t SH_FLD_FIR0_CR3_TTAG_PERR = 8598; // 12 +static const uint64_t SH_FLD_FIR0_ILLEGAL_STORE_SIZE = 8599; // 12 +static const uint64_t SH_FLD_FIR0_IMA_FSM_TIMEOUT = 8600; // 12 +static const uint64_t SH_FLD_FIR0_LD_AMO_SEQ = 8601; // 12 +static const uint64_t SH_FLD_FIR0_OVERFLOW = 8602; // 12 +static const uint64_t SH_FLD_FIR0_PBARB_TRASHMODE = 8603; // 12 +static const uint64_t SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT = 8604; // 12 +static const uint64_t SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT = 8605; // 12 +static const uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 = 8606; // 12 +static const uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 = 8607; // 12 +static const uint64_t SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 = 8608; // 12 +static const uint64_t SH_FLD_FIR0_PURGE_LVL_ERR1 = 8609; // 12 +static const uint64_t SH_FLD_FIR0_PURGE_LVL_ERR2 = 8610; // 12 +static const uint64_t SH_FLD_FIR0_SNP0_ADDR_PERR = 8611; // 12 +static const uint64_t SH_FLD_FIR0_SNP0_TTAG_PERR = 8612; // 12 +static const uint64_t SH_FLD_FIR0_SNP1_ADDR_PERR = 8613; // 12 +static const uint64_t SH_FLD_FIR0_SNP1_TTAG_PERR = 8614; // 12 +static const uint64_t SH_FLD_FIR0_TLB_DATA_PAR = 8615; // 12 +static const uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_ABCD = 8616; // 12 +static const uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_EFGH = 8617; // 12 +static const uint64_t SH_FLD_FIR14_B01_BOTH_ACTIVE = 8618; // 12 +static const uint64_t SH_FLD_FIR14_B0_SD_DIR_MULT_HIT = 8619; // 12 +static const uint64_t SH_FLD_FIR14_B1_SD_DIR_MULT_HIT = 8620; // 12 +static const uint64_t SH_FLD_FIR14_B2_SD_DIR_MULT_HIT = 8621; // 12 +static const uint64_t SH_FLD_FIR14_B3_SD_DIR_MULT_HIT = 8622; // 12 +static const uint64_t SH_FLD_FIR14_BAD_FP_MATE = 8623; // 12 +static const uint64_t SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP = 8624; // 12 +static const uint64_t SH_FLD_FIR14_CR0_ATAG_PERR = 8625; // 12 +static const uint64_t SH_FLD_FIR14_CR0_TTAG_PERR = 8626; // 12 +static const uint64_t SH_FLD_FIR14_CR1_ATAG_PERR = 8627; // 12 +static const uint64_t SH_FLD_FIR14_CR1_TTAG_PERR = 8628; // 12 +static const uint64_t SH_FLD_FIR14_CR2_ATAG_PERR = 8629; // 12 +static const uint64_t SH_FLD_FIR14_CR2_TTAG_PERR = 8630; // 12 +static const uint64_t SH_FLD_FIR14_CR3_ATAG_PERR = 8631; // 12 +static const uint64_t SH_FLD_FIR14_CR3_TTAG_PERR = 8632; // 12 +static const uint64_t SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 8633; // 12 +static const uint64_t SH_FLD_FIR14_DW_SET_SI_BY_MACH = 8634; // 24 +static const uint64_t SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE = 8635; // 12 +static const uint64_t SH_FLD_FIR14_IFU_MULT_REQ = 8636; // 12 +static const uint64_t SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN = 8637; // 12 +static const uint64_t SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE = 8638; // 12 +static const uint64_t SH_FLD_FIR14_L3PF_MACH_DONE = 8639; // 12 +static const uint64_t SH_FLD_FIR14_L3PF_REQ = 8640; // 12 +static const uint64_t SH_FLD_FIR14_LSU_TAG_REUSE = 8641; // 12 +static const uint64_t SH_FLD_FIR14_NCCTL_RLD_BARRIER = 8642; // 12 +static const uint64_t SH_FLD_FIR14_NCCTL_SNP = 8643; // 12 +static const uint64_t SH_FLD_FIR14_NCCTL_SYNC = 8644; // 12 +static const uint64_t SH_FLD_FIR14_NCCTL_TLBIE_ACK = 8645; // 12 +static const uint64_t SH_FLD_FIR14_NCCTL_VSYNC = 8646; // 12 +static const uint64_t SH_FLD_FIR14_NCU_TID_DONE = 8647; // 12 +static const uint64_t SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW = 8648; // 12 +static const uint64_t SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ = 8649; // 12 +static const uint64_t SH_FLD_FIR14_PD_DIR_MULT_HIT = 8650; // 12 +static const uint64_t SH_FLD_FIR14_PHANTOM_B01_REQ = 8651; // 12 +static const uint64_t SH_FLD_FIR14_RCMD0_ADDR_PERR = 8652; // 12 +static const uint64_t SH_FLD_FIR14_RCMD0_TTAG_PERR = 8653; // 12 +static const uint64_t SH_FLD_FIR14_RCMD1_ADDR_PERR = 8654; // 12 +static const uint64_t SH_FLD_FIR14_RCMD1_TTAG_PERR = 8655; // 12 +static const uint64_t SH_FLD_FIR14_RCMD2_ADDR_PERR = 8656; // 12 +static const uint64_t SH_FLD_FIR14_RCMD2_TTAG_PERR = 8657; // 12 +static const uint64_t SH_FLD_FIR14_RCMD3_ADDR_PERR = 8658; // 12 +static const uint64_t SH_FLD_FIR14_RCMD3_TTAG_PERR = 8659; // 12 +static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 8660; // 12 +static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 8661; // 12 +static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 8662; // 12 +static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 8663; // 12 +static const uint64_t SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 8664; // 12 +static const uint64_t SH_FLD_FIR14_RC_PBBUS_SFSTAT = 8665; // 12 +static const uint64_t SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 8666; // 12 +static const uint64_t SH_FLD_FIR14_RC_UNEXP_F2_DATA = 8667; // 12 +static const uint64_t SH_FLD_FIR14_RC_UNEXP_PURG_HIT = 8668; // 12 +static const uint64_t SH_FLD_FIR14_RVCTL = 8669; // 12 +static const uint64_t SH_FLD_FIR14_SRCTL0_BAD_HPC = 8670; // 12 +static const uint64_t SH_FLD_FIR14_SRCTL1_BAD_HPC = 8671; // 12 +static const uint64_t SH_FLD_FIR14_SRCTL2_BAD_HPC = 8672; // 12 +static const uint64_t SH_FLD_FIR14_SRCTL3_BAD_HPC = 8673; // 12 +static const uint64_t SH_FLD_FIR14_STQ_COMING = 8674; // 12 +static const uint64_t SH_FLD_FIR14_STQ_OVERFLOW = 8675; // 12 +static const uint64_t SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV = 8676; // 12 +static const uint64_t SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 8677; // 12 +static const uint64_t SH_FLD_FIR14_XLT_QUEUE_OVRFLW = 8678; // 12 +static const uint64_t SH_FLD_FIR14_XPF_MULT_REQ = 8679; // 12 +static const uint64_t SH_FLD_FIR19_LD_TGT_NODAL_DINC = 8680; // 12 +static const uint64_t SH_FLD_FIR19_ST_TGT_NODAL_DINC = 8681; // 12 +static const uint64_t SH_FLD_FIR1_MASTER_SEQ_ID_PAR = 8682; // 12 +static const uint64_t SH_FLD_FIR1_RSVD_37 = 8683; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_38 = 8684; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_39 = 8685; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_40 = 8686; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_41 = 8687; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_42 = 8688; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_43 = 8689; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_44 = 8690; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_45 = 8691; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_46 = 8692; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_47 = 8693; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_48 = 8694; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_49 = 8695; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_50 = 8696; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_51 = 8697; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_52 = 8698; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_53 = 8699; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_54 = 8700; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_55 = 8701; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_56 = 8702; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_57 = 8703; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_58 = 8704; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_59 = 8705; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_60 = 8706; // 1 +static const uint64_t SH_FLD_FIR1_RSVD_61 = 8707; // 1 +static const uint64_t SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY = 8708; // 12 +static const uint64_t SH_FLD_FIR1_TLBIE_BAD_OP = 8709; // 12 +static const uint64_t SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 8710; // 12 +static const uint64_t SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 8711; // 12 +static const uint64_t SH_FLD_FIR9_PEC_PHASE3_TIMEOUT = 8712; // 12 +static const uint64_t SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 8713; // 12 +static const uint64_t SH_FLD_FIR9_PEC_PHASE4_SAME = 8714; // 12 +static const uint64_t SH_FLD_FIR9_PEC_PHASE5_TIMEOUT = 8715; // 12 +static const uint64_t SH_FLD_FIRMWARE_CONTROL_ERROR = 8716; // 98 +static const uint64_t SH_FLD_FIRMWARE_FAULT = 8717; // 1 +static const uint64_t SH_FLD_FIRMWARE_NOTIFY = 8718; // 1 +static const uint64_t SH_FLD_FIRST_ERROR = 8719; // 3 +static const uint64_t SH_FLD_FIRST_ERROR_CAPTURED = 8720; // 1 +static const uint64_t SH_FLD_FIRST_ERROR_DECODE = 8721; // 1 +static const uint64_t SH_FLD_FIRST_ERROR_DECODE_LEN = 8722; // 1 +static const uint64_t SH_FLD_FIRST_ERROR_INFO = 8723; // 1 +static const uint64_t SH_FLD_FIRST_ERROR_INFO_LEN = 8724; // 1 +static const uint64_t SH_FLD_FIRST_ERROR_LEN = 8725; // 3 +static const uint64_t SH_FLD_FIRST_ERROR_SPARE = 8726; // 1 +static const uint64_t SH_FLD_FIRST_ERROR_SPARE_LEN = 8727; // 1 +static const uint64_t SH_FLD_FIR_ACTION0 = 8728; // 17 +static const uint64_t SH_FLD_FIR_ACTION0_LEN = 8729; // 17 +static const uint64_t SH_FLD_FIR_ACTION1 = 8730; // 19 +static const uint64_t SH_FLD_FIR_ACTION1_LEN = 8731; // 17 +static const uint64_t SH_FLD_FIR_ACTION2 = 8732; // 2 +static const uint64_t SH_FLD_FIR_ACTION3 = 8733; // 2 +static const uint64_t SH_FLD_FIR_LEN = 8734; // 48 +static const uint64_t SH_FLD_FIR_MASK = 8735; // 20 +static const uint64_t SH_FLD_FIR_MASK_LEN = 8736; // 20 +static const uint64_t SH_FLD_FIR_PARITY_ERR = 8737; // 16 +static const uint64_t SH_FLD_FIR_PARITY_ERR2 = 8738; // 1 +static const uint64_t SH_FLD_FIR_PARITY_ERR2_MASK = 8739; // 1 +static const uint64_t SH_FLD_FIR_PARITY_ERR_DUP = 8740; // 14 +static const uint64_t SH_FLD_FIR_PARITY_ERR_DUP_MASK = 8741; // 1 +static const uint64_t SH_FLD_FIR_PARITY_ERR_MASK = 8742; // 2 +static const uint64_t SH_FLD_FIR_RESET = 8743; // 6 +static const uint64_t SH_FLD_FIR_TRIGGER = 8744; // 17 +static const uint64_t SH_FLD_FIT_SEL = 8745; // 17 +static const uint64_t SH_FLD_FIT_SEL_LEN = 8746; // 17 +static const uint64_t SH_FLD_FLAG_DMD = 8747; // 1 +static const uint64_t SH_FLD_FLAG_FENCE = 8748; // 1 +static const uint64_t SH_FLD_FLAG_MAP = 8749; // 1 +static const uint64_t SH_FLD_FLAG_OTHER = 8750; // 1 +static const uint64_t SH_FLD_FLAG_PREF = 8751; // 1 +static const uint64_t SH_FLD_FLSH_FFN_AND_NOT_UC_HOLD_OUT = 8752; // 24 +static const uint64_t SH_FLD_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT = 8753; // 24 +static const uint64_t SH_FLD_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT = 8754; // 24 +static const uint64_t SH_FLD_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT = 8755; // 24 +static const uint64_t SH_FLD_FLSH_INVALID_FLUSH_CASE_HOLD_OUT = 8756; // 24 +static const uint64_t SH_FLD_FLUSH_ALIGN_OVR = 8757; // 43 +static const uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP = 8758; // 2 +static const uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN = 8759; // 2 +static const uint64_t SH_FLD_FLUSH_IC = 8760; // 24 +static const uint64_t SH_FLD_FLUSH_SCAN_N = 8761; // 43 +static const uint64_t SH_FLD_FLUSH_SUE_STATE_MAP = 8762; // 2 +static const uint64_t SH_FLD_FLUSH_SUE_STATE_MAP_LEN = 8763; // 2 +static const uint64_t SH_FLD_FMAX = 8764; // 6 +static const uint64_t SH_FLD_FMAX_LEN = 8765; // 6 +static const uint64_t SH_FLD_FMIN = 8766; // 6 +static const uint64_t SH_FLD_FMIN_LEN = 8767; // 6 +static const uint64_t SH_FLD_FMR00_TRAINED = 8768; // 4 +static const uint64_t SH_FLD_FMR01_TRAINED = 8769; // 4 +static const uint64_t SH_FLD_FMR02_TRAINED = 8770; // 4 +static const uint64_t SH_FLD_FMR03_TRAINED = 8771; // 4 +static const uint64_t SH_FLD_FMR04_TRAINED = 8772; // 4 +static const uint64_t SH_FLD_FMR05_TRAINED = 8773; // 4 +static const uint64_t SH_FLD_FMR06_TRAINED = 8774; // 2 +static const uint64_t SH_FLD_FMR07_TRAINED = 8775; // 2 +static const uint64_t SH_FLD_FMR0_ADDR_PERR = 8776; // 2 +static const uint64_t SH_FLD_FMR0_CC0_CREDITERR = 8777; // 2 +static const uint64_t SH_FLD_FMR0_CC1_CREDITERR = 8778; // 2 +static const uint64_t SH_FLD_FMR0_CC2_CREDITERR = 8779; // 2 +static const uint64_t SH_FLD_FMR0_CC3_CREDITERR = 8780; // 2 +static const uint64_t SH_FLD_FMR0_CONTROL_ERROR = 8781; // 2 +static const uint64_t SH_FLD_FMR0_DAT_HI_PERR = 8782; // 2 +static const uint64_t SH_FLD_FMR0_DAT_LO_PERR = 8783; // 2 +static const uint64_t SH_FLD_FMR0_FRAME_CREDITERR = 8784; // 2 +static const uint64_t SH_FLD_FMR0_LINK_DELAY = 8785; // 2 +static const uint64_t SH_FLD_FMR0_LINK_DELAY_LEN = 8786; // 2 +static const uint64_t SH_FLD_FMR0_PC0_CREDITERR = 8787; // 2 +static const uint64_t SH_FLD_FMR0_PC1_CREDITERR = 8788; // 2 +static const uint64_t SH_FLD_FMR0_PRSP_PTYERR = 8789; // 2 +static const uint64_t SH_FLD_FMR0_RTAG_PTYERR = 8790; // 2 +static const uint64_t SH_FLD_FMR0_TTAG_PERR = 8791; // 2 +static const uint64_t SH_FLD_FMR0_VC0_CREDITERR = 8792; // 2 +static const uint64_t SH_FLD_FMR0_VC1_CREDITERR = 8793; // 2 +static const uint64_t SH_FLD_FMR1_ADDR_PERR = 8794; // 2 +static const uint64_t SH_FLD_FMR1_CC0_CREDITERR = 8795; // 2 +static const uint64_t SH_FLD_FMR1_CC1_CREDITERR = 8796; // 2 +static const uint64_t SH_FLD_FMR1_CC2_CREDITERR = 8797; // 2 +static const uint64_t SH_FLD_FMR1_CC3_CREDITERR = 8798; // 2 +static const uint64_t SH_FLD_FMR1_CONTROL_ERROR = 8799; // 2 +static const uint64_t SH_FLD_FMR1_DAT_HI_PERR = 8800; // 2 +static const uint64_t SH_FLD_FMR1_DAT_LO_PERR = 8801; // 2 +static const uint64_t SH_FLD_FMR1_FRAME_CREDITERR = 8802; // 2 +static const uint64_t SH_FLD_FMR1_LINK_DELAY = 8803; // 2 +static const uint64_t SH_FLD_FMR1_LINK_DELAY_LEN = 8804; // 2 +static const uint64_t SH_FLD_FMR1_PC0_CREDITERR = 8805; // 2 +static const uint64_t SH_FLD_FMR1_PC1_CREDITERR = 8806; // 2 +static const uint64_t SH_FLD_FMR1_PRSP_PTYERR = 8807; // 2 +static const uint64_t SH_FLD_FMR1_RTAG_PTYERR = 8808; // 2 +static const uint64_t SH_FLD_FMR1_TTAG_PERR = 8809; // 2 +static const uint64_t SH_FLD_FMR1_VC0_CREDITERR = 8810; // 2 +static const uint64_t SH_FLD_FMR1_VC1_CREDITERR = 8811; // 2 +static const uint64_t SH_FLD_FMR2_ADDR_PERR = 8812; // 2 +static const uint64_t SH_FLD_FMR2_CC0_CREDITERR = 8813; // 2 +static const uint64_t SH_FLD_FMR2_CC1_CREDITERR = 8814; // 2 +static const uint64_t SH_FLD_FMR2_CC2_CREDITERR = 8815; // 2 +static const uint64_t SH_FLD_FMR2_CC3_CREDITERR = 8816; // 2 +static const uint64_t SH_FLD_FMR2_CONTROL_ERROR = 8817; // 2 +static const uint64_t SH_FLD_FMR2_DAT_HI_PERR = 8818; // 2 +static const uint64_t SH_FLD_FMR2_DAT_LO_PERR = 8819; // 2 +static const uint64_t SH_FLD_FMR2_FRAME_CREDITERR = 8820; // 2 +static const uint64_t SH_FLD_FMR2_LINK_DELAY = 8821; // 2 +static const uint64_t SH_FLD_FMR2_LINK_DELAY_LEN = 8822; // 2 +static const uint64_t SH_FLD_FMR2_PC0_CREDITERR = 8823; // 2 +static const uint64_t SH_FLD_FMR2_PC1_CREDITERR = 8824; // 2 +static const uint64_t SH_FLD_FMR2_PRSP_PTYERR = 8825; // 2 +static const uint64_t SH_FLD_FMR2_RTAG_PTYERR = 8826; // 2 +static const uint64_t SH_FLD_FMR2_TTAG_PERR = 8827; // 2 +static const uint64_t SH_FLD_FMR2_VC0_CREDITERR = 8828; // 2 +static const uint64_t SH_FLD_FMR2_VC1_CREDITERR = 8829; // 2 +static const uint64_t SH_FLD_FMR3_ADDR_PERR = 8830; // 2 +static const uint64_t SH_FLD_FMR3_CC0_CREDITERR = 8831; // 2 +static const uint64_t SH_FLD_FMR3_CC1_CREDITERR = 8832; // 2 +static const uint64_t SH_FLD_FMR3_CC2_CREDITERR = 8833; // 2 +static const uint64_t SH_FLD_FMR3_CC3_CREDITERR = 8834; // 2 +static const uint64_t SH_FLD_FMR3_CONTROL_ERROR = 8835; // 2 +static const uint64_t SH_FLD_FMR3_DAT_HI_PERR = 8836; // 2 +static const uint64_t SH_FLD_FMR3_DAT_LO_PERR = 8837; // 2 +static const uint64_t SH_FLD_FMR3_FRAME_CREDITERR = 8838; // 2 +static const uint64_t SH_FLD_FMR3_LINK_DELAY = 8839; // 2 +static const uint64_t SH_FLD_FMR3_LINK_DELAY_LEN = 8840; // 2 +static const uint64_t SH_FLD_FMR3_PC0_CREDITERR = 8841; // 2 +static const uint64_t SH_FLD_FMR3_PC1_CREDITERR = 8842; // 2 +static const uint64_t SH_FLD_FMR3_PRSP_PTYERR = 8843; // 2 +static const uint64_t SH_FLD_FMR3_RTAG_PTYERR = 8844; // 2 +static const uint64_t SH_FLD_FMR3_TTAG_PERR = 8845; // 2 +static const uint64_t SH_FLD_FMR3_VC0_CREDITERR = 8846; // 2 +static const uint64_t SH_FLD_FMR3_VC1_CREDITERR = 8847; // 2 +static const uint64_t SH_FLD_FMR4_ADDR_PERR = 8848; // 2 +static const uint64_t SH_FLD_FMR4_CC0_CREDITERR = 8849; // 2 +static const uint64_t SH_FLD_FMR4_CC1_CREDITERR = 8850; // 2 +static const uint64_t SH_FLD_FMR4_CC2_CREDITERR = 8851; // 2 +static const uint64_t SH_FLD_FMR4_CC3_CREDITERR = 8852; // 2 +static const uint64_t SH_FLD_FMR4_CONTROL_ERROR = 8853; // 2 +static const uint64_t SH_FLD_FMR4_DAT_HI_PERR = 8854; // 2 +static const uint64_t SH_FLD_FMR4_DAT_LO_PERR = 8855; // 2 +static const uint64_t SH_FLD_FMR4_FRAME_CREDITERR = 8856; // 2 +static const uint64_t SH_FLD_FMR4_LINK_DELAY = 8857; // 2 +static const uint64_t SH_FLD_FMR4_LINK_DELAY_LEN = 8858; // 2 +static const uint64_t SH_FLD_FMR4_PC0_CREDITERR = 8859; // 2 +static const uint64_t SH_FLD_FMR4_PC1_CREDITERR = 8860; // 2 +static const uint64_t SH_FLD_FMR4_PRSP_PTYERR = 8861; // 2 +static const uint64_t SH_FLD_FMR4_RTAG_PTYERR = 8862; // 2 +static const uint64_t SH_FLD_FMR4_TTAG_PERR = 8863; // 2 +static const uint64_t SH_FLD_FMR4_VC0_CREDITERR = 8864; // 2 +static const uint64_t SH_FLD_FMR4_VC1_CREDITERR = 8865; // 2 +static const uint64_t SH_FLD_FMR5_ADDR_PERR = 8866; // 2 +static const uint64_t SH_FLD_FMR5_CC0_CREDITERR = 8867; // 2 +static const uint64_t SH_FLD_FMR5_CC1_CREDITERR = 8868; // 2 +static const uint64_t SH_FLD_FMR5_CC2_CREDITERR = 8869; // 2 +static const uint64_t SH_FLD_FMR5_CC3_CREDITERR = 8870; // 2 +static const uint64_t SH_FLD_FMR5_CONTROL_ERROR = 8871; // 2 +static const uint64_t SH_FLD_FMR5_DAT_HI_PERR = 8872; // 2 +static const uint64_t SH_FLD_FMR5_DAT_LO_PERR = 8873; // 2 +static const uint64_t SH_FLD_FMR5_FRAME_CREDITERR = 8874; // 2 +static const uint64_t SH_FLD_FMR5_LINK_DELAY = 8875; // 2 +static const uint64_t SH_FLD_FMR5_LINK_DELAY_LEN = 8876; // 2 +static const uint64_t SH_FLD_FMR5_PC0_CREDITERR = 8877; // 2 +static const uint64_t SH_FLD_FMR5_PC1_CREDITERR = 8878; // 2 +static const uint64_t SH_FLD_FMR5_PRSP_PTYERR = 8879; // 2 +static const uint64_t SH_FLD_FMR5_RTAG_PTYERR = 8880; // 2 +static const uint64_t SH_FLD_FMR5_TTAG_PERR = 8881; // 2 +static const uint64_t SH_FLD_FMR5_VC0_CREDITERR = 8882; // 2 +static const uint64_t SH_FLD_FMR5_VC1_CREDITERR = 8883; // 2 +static const uint64_t SH_FLD_FMR6_ADDR_PERR = 8884; // 1 +static const uint64_t SH_FLD_FMR6_CC0_CREDITERR = 8885; // 1 +static const uint64_t SH_FLD_FMR6_CC1_CREDITERR = 8886; // 1 +static const uint64_t SH_FLD_FMR6_CC2_CREDITERR = 8887; // 1 +static const uint64_t SH_FLD_FMR6_CC3_CREDITERR = 8888; // 1 +static const uint64_t SH_FLD_FMR6_CONTROL_ERROR = 8889; // 1 +static const uint64_t SH_FLD_FMR6_DAT_HI_PERR = 8890; // 1 +static const uint64_t SH_FLD_FMR6_DAT_LO_PERR = 8891; // 1 +static const uint64_t SH_FLD_FMR6_FRAME_CREDITERR = 8892; // 1 +static const uint64_t SH_FLD_FMR6_LINK_DELAY = 8893; // 1 +static const uint64_t SH_FLD_FMR6_LINK_DELAY_LEN = 8894; // 1 +static const uint64_t SH_FLD_FMR6_PC0_CREDITERR = 8895; // 1 +static const uint64_t SH_FLD_FMR6_PC1_CREDITERR = 8896; // 1 +static const uint64_t SH_FLD_FMR6_PRSP_PTYERR = 8897; // 1 +static const uint64_t SH_FLD_FMR6_RTAG_PTYERR = 8898; // 1 +static const uint64_t SH_FLD_FMR6_TTAG_PERR = 8899; // 1 +static const uint64_t SH_FLD_FMR6_VC0_CREDITERR = 8900; // 1 +static const uint64_t SH_FLD_FMR6_VC1_CREDITERR = 8901; // 1 +static const uint64_t SH_FLD_FMR7_ADDR_PERR = 8902; // 1 +static const uint64_t SH_FLD_FMR7_CC0_CREDITERR = 8903; // 1 +static const uint64_t SH_FLD_FMR7_CC1_CREDITERR = 8904; // 1 +static const uint64_t SH_FLD_FMR7_CC2_CREDITERR = 8905; // 1 +static const uint64_t SH_FLD_FMR7_CC3_CREDITERR = 8906; // 1 +static const uint64_t SH_FLD_FMR7_CONTROL_ERROR = 8907; // 1 +static const uint64_t SH_FLD_FMR7_DAT_HI_PERR = 8908; // 1 +static const uint64_t SH_FLD_FMR7_DAT_LO_PERR = 8909; // 1 +static const uint64_t SH_FLD_FMR7_FRAME_CREDITERR = 8910; // 1 +static const uint64_t SH_FLD_FMR7_LINK_DELAY = 8911; // 1 +static const uint64_t SH_FLD_FMR7_LINK_DELAY_LEN = 8912; // 1 +static const uint64_t SH_FLD_FMR7_PC0_CREDITERR = 8913; // 1 +static const uint64_t SH_FLD_FMR7_PC1_CREDITERR = 8914; // 1 +static const uint64_t SH_FLD_FMR7_PRSP_PTYERR = 8915; // 1 +static const uint64_t SH_FLD_FMR7_RTAG_PTYERR = 8916; // 1 +static const uint64_t SH_FLD_FMR7_TTAG_PERR = 8917; // 1 +static const uint64_t SH_FLD_FMR7_VC0_CREDITERR = 8918; // 1 +static const uint64_t SH_FLD_FMR7_VC1_CREDITERR = 8919; // 1 +static const uint64_t SH_FLD_FMULT = 8920; // 6 +static const uint64_t SH_FLD_FMULT_LEN = 8921; // 6 +static const uint64_t SH_FLD_FMU_KVREF_DATAREG = 8922; // 1 +static const uint64_t SH_FLD_FMU_KVREF_DATAREG_LEN = 8923; // 1 +static const uint64_t SH_FLD_FMU_KVREF_TUNE_DATA = 8924; // 1 +static const uint64_t SH_FLD_FMU_KVREF_TUNE_DATA_LEN = 8925; // 1 +static const uint64_t SH_FLD_FMU_MODEREG_P_ERR = 8926; // 2 +static const uint64_t SH_FLD_FMU_PULSE_GEN_REG_ERR = 8927; // 2 +static const uint64_t SH_FLD_FORCE_ALL_RINGS = 8928; // 43 +static const uint64_t SH_FLD_FORCE_ANY_BAR_ACTIVE = 8929; // 4 +static const uint64_t SH_FLD_FORCE_ANY_CL_ACTIVE = 8930; // 4 +static const uint64_t SH_FLD_FORCE_BYPASS = 8931; // 1 +static const uint64_t SH_FLD_FORCE_CL_INJECT = 8932; // 1 +static const uint64_t SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR = 8933; // 5 +static const uint64_t SH_FLD_FORCE_DOUBLE_BIT_ERR = 8934; // 1 +static const uint64_t SH_FLD_FORCE_DROOP_DATA = 8935; // 6 +static const uint64_t SH_FLD_FORCE_DROOP_DATA_LEN = 8936; // 6 +static const uint64_t SH_FLD_FORCE_ECC_CE = 8937; // 2 +static const uint64_t SH_FLD_FORCE_ECC_SEL = 8938; // 1 +static const uint64_t SH_FLD_FORCE_ECC_SEL_0_1 = 8939; // 1 +static const uint64_t SH_FLD_FORCE_ECC_SEL_0_1_LEN = 8940; // 1 +static const uint64_t SH_FLD_FORCE_ECC_UE = 8941; // 2 +static const uint64_t SH_FLD_FORCE_FMU_SM_RESET = 8942; // 1 +static const uint64_t SH_FLD_FORCE_FSAFE = 8943; // 6 +static const uint64_t SH_FLD_FORCE_LBUS_OWNERSHIP = 8944; // 2 +static const uint64_t SH_FLD_FORCE_MAX_SCOPE_INTRP = 8945; // 1 +static const uint64_t SH_FLD_FORCE_MEASURE = 8946; // 1 +static const uint64_t SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE = 8947; // 43 +static const uint64_t SH_FLD_FORCE_MPR = 8948; // 8 +static const uint64_t SH_FLD_FORCE_MP_IPL = 8949; // 2 +static const uint64_t SH_FLD_FORCE_ON_CLK_GATE = 8950; // 8 +static const uint64_t SH_FLD_FORCE_PF_DROP0 = 8951; // 8 +static const uint64_t SH_FLD_FORCE_PF_DROP1 = 8952; // 8 +static const uint64_t SH_FLD_FORCE_PR_INJECT = 8953; // 1 +static const uint64_t SH_FLD_FORCE_QUIESCE = 8954; // 2 +static const uint64_t SH_FLD_FORCE_RESERVED = 8955; // 8 +static const uint64_t SH_FLD_FORCE_RESET = 8956; // 1 +static const uint64_t SH_FLD_FORCE_RESET_MEASURE_VOLT = 8957; // 43 +static const uint64_t SH_FLD_FORCE_RESET_THRES_L1RESULTS = 8958; // 43 +static const uint64_t SH_FLD_FORCE_RESET_THRES_L2RESULTS = 8959; // 43 +static const uint64_t SH_FLD_FORCE_RESET_THRES_L3RESULTS = 8960; // 43 +static const uint64_t SH_FLD_FORCE_SAMPLE_DTS = 8961; // 43 +static const uint64_t SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE = 8962; // 43 +static const uint64_t SH_FLD_FORCE_SFSTAT_ACTIVE = 8963; // 4 +static const uint64_t SH_FLD_FORCE_SHIFT_SENSOR = 8964; // 43 +static const uint64_t SH_FLD_FORCE_SINGLE_BIT_ECC_ERR = 8965; // 5 +static const uint64_t SH_FLD_FORCE_SINGLE_BIT_ERR = 8966; // 1 +static const uint64_t SH_FLD_FORCE_TEST = 8967; // 43 +static const uint64_t SH_FLD_FORCE_TEST_MODE = 8968; // 86 +static const uint64_t SH_FLD_FORCE_THRES_ACT = 8969; // 43 +static const uint64_t SH_FLD_FORCE_VG_SYS_INTRP = 8970; // 1 +static const uint64_t SH_FLD_FOREIGN_LINK_HANG_ERROR = 8971; // 4 +static const uint64_t SH_FLD_FOREIGN_OP_HANG = 8972; // 2 +static const uint64_t SH_FLD_FOURTH_ERROR = 8973; // 24 +static const uint64_t SH_FLD_FOURTH_ERROR_LEN = 8974; // 24 +static const uint64_t SH_FLD_FP = 8975; // 96 +static const uint64_t SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 = 8976; // 2 +static const uint64_t SH_FLD_FP0_DISABLE_CMD_COMPRESSION = 8977; // 2 +static const uint64_t SH_FLD_FP0_DISABLE_GATHERING = 8978; // 2 +static const uint64_t SH_FLD_FP0_DISABLE_PRSP_COMPRESSION = 8979; // 2 +static const uint64_t SH_FLD_FP0_FMR_DISABLE = 8980; // 2 +static const uint64_t SH_FLD_FP0_FMR_SPARE = 8981; // 2 +static const uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT = 8982; // 2 +static const uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN = 8983; // 2 +static const uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT = 8984; // 2 +static const uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN = 8985; // 2 +static const uint64_t SH_FLD_FP0_PRS_DISABLE = 8986; // 2 +static const uint64_t SH_FLD_FP0_PRS_SPARE = 8987; // 2 +static const uint64_t SH_FLD_FP0_PRS_SPARE_LEN = 8988; // 2 +static const uint64_t SH_FLD_FP0_RUN_AFTER_FRAME_ERROR = 8989; // 2 +static const uint64_t SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 = 8990; // 2 +static const uint64_t SH_FLD_FP1_DISABLE_CMD_COMPRESSION = 8991; // 2 +static const uint64_t SH_FLD_FP1_DISABLE_GATHERING = 8992; // 2 +static const uint64_t SH_FLD_FP1_DISABLE_PRSP_COMPRESSION = 8993; // 2 +static const uint64_t SH_FLD_FP1_FMR_DISABLE = 8994; // 2 +static const uint64_t SH_FLD_FP1_FMR_SPARE = 8995; // 2 +static const uint64_t SH_FLD_FP1_FMR_SPARE_LEN = 8996; // 2 +static const uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT = 8997; // 2 +static const uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN = 8998; // 2 +static const uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT = 8999; // 2 +static const uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN = 9000; // 2 +static const uint64_t SH_FLD_FP1_PRS_DISABLE = 9001; // 2 +static const uint64_t SH_FLD_FP1_PRS_SPARE = 9002; // 2 +static const uint64_t SH_FLD_FP1_PRS_SPARE_LEN = 9003; // 2 +static const uint64_t SH_FLD_FP1_RUN_AFTER_FRAME_ERROR = 9004; // 2 +static const uint64_t SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 = 9005; // 2 +static const uint64_t SH_FLD_FP2_DISABLE_CMD_COMPRESSION = 9006; // 2 +static const uint64_t SH_FLD_FP2_DISABLE_GATHERING = 9007; // 2 +static const uint64_t SH_FLD_FP2_DISABLE_PRSP_COMPRESSION = 9008; // 2 +static const uint64_t SH_FLD_FP2_FMR_DISABLE = 9009; // 2 +static const uint64_t SH_FLD_FP2_FMR_SPARE = 9010; // 2 +static const uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT = 9011; // 2 +static const uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN = 9012; // 2 +static const uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT = 9013; // 2 +static const uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN = 9014; // 2 +static const uint64_t SH_FLD_FP2_PRS_DISABLE = 9015; // 2 +static const uint64_t SH_FLD_FP2_PRS_SPARE = 9016; // 2 +static const uint64_t SH_FLD_FP2_PRS_SPARE_LEN = 9017; // 2 +static const uint64_t SH_FLD_FP2_RUN_AFTER_FRAME_ERROR = 9018; // 2 +static const uint64_t SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 = 9019; // 2 +static const uint64_t SH_FLD_FP3_DISABLE_CMD_COMPRESSION = 9020; // 2 +static const uint64_t SH_FLD_FP3_DISABLE_GATHERING = 9021; // 2 +static const uint64_t SH_FLD_FP3_DISABLE_PRSP_COMPRESSION = 9022; // 2 +static const uint64_t SH_FLD_FP3_FMR_DISABLE = 9023; // 2 +static const uint64_t SH_FLD_FP3_FMR_SPARE = 9024; // 2 +static const uint64_t SH_FLD_FP3_FMR_SPARE_LEN = 9025; // 2 +static const uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT = 9026; // 2 +static const uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN = 9027; // 2 +static const uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT = 9028; // 2 +static const uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN = 9029; // 2 +static const uint64_t SH_FLD_FP3_PRS_DISABLE = 9030; // 2 +static const uint64_t SH_FLD_FP3_PRS_SPARE = 9031; // 2 +static const uint64_t SH_FLD_FP3_PRS_SPARE_LEN = 9032; // 2 +static const uint64_t SH_FLD_FP3_RUN_AFTER_FRAME_ERROR = 9033; // 2 +static const uint64_t SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 = 9034; // 2 +static const uint64_t SH_FLD_FP4_DISABLE_CMD_COMPRESSION = 9035; // 2 +static const uint64_t SH_FLD_FP4_DISABLE_GATHERING = 9036; // 2 +static const uint64_t SH_FLD_FP4_DISABLE_PRSP_COMPRESSION = 9037; // 2 +static const uint64_t SH_FLD_FP4_FMR_DISABLE = 9038; // 2 +static const uint64_t SH_FLD_FP4_FMR_SPARE = 9039; // 2 +static const uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT = 9040; // 2 +static const uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN = 9041; // 2 +static const uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT = 9042; // 2 +static const uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN = 9043; // 2 +static const uint64_t SH_FLD_FP4_PRS_DISABLE = 9044; // 2 +static const uint64_t SH_FLD_FP4_PRS_SPARE = 9045; // 2 +static const uint64_t SH_FLD_FP4_PRS_SPARE_LEN = 9046; // 2 +static const uint64_t SH_FLD_FP4_RUN_AFTER_FRAME_ERROR = 9047; // 2 +static const uint64_t SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 = 9048; // 2 +static const uint64_t SH_FLD_FP5_DISABLE_CMD_COMPRESSION = 9049; // 2 +static const uint64_t SH_FLD_FP5_DISABLE_GATHERING = 9050; // 2 +static const uint64_t SH_FLD_FP5_DISABLE_PRSP_COMPRESSION = 9051; // 2 +static const uint64_t SH_FLD_FP5_FMR_DISABLE = 9052; // 2 +static const uint64_t SH_FLD_FP5_FMR_SPARE = 9053; // 2 +static const uint64_t SH_FLD_FP5_FMR_SPARE_LEN = 9054; // 2 +static const uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT = 9055; // 2 +static const uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN = 9056; // 2 +static const uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT = 9057; // 2 +static const uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN = 9058; // 2 +static const uint64_t SH_FLD_FP5_PRS_DISABLE = 9059; // 2 +static const uint64_t SH_FLD_FP5_PRS_SPARE = 9060; // 2 +static const uint64_t SH_FLD_FP5_PRS_SPARE_LEN = 9061; // 2 +static const uint64_t SH_FLD_FP5_RUN_AFTER_FRAME_ERROR = 9062; // 2 +static const uint64_t SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 = 9063; // 1 +static const uint64_t SH_FLD_FP6_DISABLE_CMD_COMPRESSION = 9064; // 1 +static const uint64_t SH_FLD_FP6_DISABLE_GATHERING = 9065; // 1 +static const uint64_t SH_FLD_FP6_DISABLE_PRSP_COMPRESSION = 9066; // 1 +static const uint64_t SH_FLD_FP6_FMR_DISABLE = 9067; // 1 +static const uint64_t SH_FLD_FP6_FMR_SPARE = 9068; // 1 +static const uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT = 9069; // 1 +static const uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN = 9070; // 1 +static const uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT = 9071; // 1 +static const uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN = 9072; // 1 +static const uint64_t SH_FLD_FP6_PRS_DISABLE = 9073; // 1 +static const uint64_t SH_FLD_FP6_PRS_SPARE = 9074; // 1 +static const uint64_t SH_FLD_FP6_PRS_SPARE_LEN = 9075; // 1 +static const uint64_t SH_FLD_FP6_RUN_AFTER_FRAME_ERROR = 9076; // 1 +static const uint64_t SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 = 9077; // 1 +static const uint64_t SH_FLD_FP7_DISABLE_CMD_COMPRESSION = 9078; // 1 +static const uint64_t SH_FLD_FP7_DISABLE_GATHERING = 9079; // 1 +static const uint64_t SH_FLD_FP7_DISABLE_PRSP_COMPRESSION = 9080; // 1 +static const uint64_t SH_FLD_FP7_FMR_DISABLE = 9081; // 1 +static const uint64_t SH_FLD_FP7_FMR_SPARE = 9082; // 1 +static const uint64_t SH_FLD_FP7_FMR_SPARE_LEN = 9083; // 1 +static const uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT = 9084; // 1 +static const uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN = 9085; // 1 +static const uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT = 9086; // 1 +static const uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN = 9087; // 1 +static const uint64_t SH_FLD_FP7_PRS_DISABLE = 9088; // 1 +static const uint64_t SH_FLD_FP7_PRS_SPARE = 9089; // 1 +static const uint64_t SH_FLD_FP7_PRS_SPARE_LEN = 9090; // 1 +static const uint64_t SH_FLD_FP7_RUN_AFTER_FRAME_ERROR = 9091; // 1 +static const uint64_t SH_FLD_FP_THROTTLE_EN = 9092; // 24 +static const uint64_t SH_FLD_FRAC1 = 9093; // 3 +static const uint64_t SH_FLD_FRAC1_LEN = 9094; // 3 +static const uint64_t SH_FLD_FRAC2 = 9095; // 3 +static const uint64_t SH_FLD_FRAC2_LEN = 9096; // 3 +static const uint64_t SH_FLD_FRAMER00_ATTN = 9097; // 4 +static const uint64_t SH_FLD_FRAMER01_ATTN = 9098; // 4 +static const uint64_t SH_FLD_FRAMER02_ATTN = 9099; // 4 +static const uint64_t SH_FLD_FRAMER03_ATTN = 9100; // 4 +static const uint64_t SH_FLD_FRAMER04_ATTN = 9101; // 4 +static const uint64_t SH_FLD_FRAMER05_ATTN = 9102; // 4 +static const uint64_t SH_FLD_FRAMER06_ATTN = 9103; // 2 +static const uint64_t SH_FLD_FRAMER07_ATTN = 9104; // 2 +static const uint64_t SH_FLD_FRAME_CAP_ADDR = 9105; // 10 +static const uint64_t SH_FLD_FRAME_CAP_ADDR_LEN = 9106; // 10 +static const uint64_t SH_FLD_FRAME_CAP_INST = 9107; // 10 +static const uint64_t SH_FLD_FRAME_CAP_SYN = 9108; // 10 +static const uint64_t SH_FLD_FRAME_CAP_SYN_LEN = 9109; // 10 +static const uint64_t SH_FLD_FRAME_CAP_VALID = 9110; // 10 +static const uint64_t SH_FLD_FRAME_COUNT = 9111; // 8 +static const uint64_t SH_FLD_FRAME_COUNT_LEN = 9112; // 8 +static const uint64_t SH_FLD_FRAME_SIZE = 9113; // 1 +static const uint64_t SH_FLD_FRAME_SIZE_LEN = 9114; // 1 +static const uint64_t SH_FLD_FRCERR = 9115; // 48 +static const uint64_t SH_FLD_FRCLEL = 9116; // 48 +static const uint64_t SH_FLD_FREE = 9117; // 12 +static const uint64_t SH_FLD_FREEZE = 9118; // 10 +static const uint64_t SH_FLD_FREEZEMODE = 9119; // 9 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR1 = 9120; // 1 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR2 = 9121; // 1 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR3 = 9122; // 1 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR4 = 9123; // 1 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR5 = 9124; // 1 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR6 = 9125; // 1 +static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR7 = 9126; // 1 +static const uint64_t SH_FLD_FREEZE_ON_OVERFLOW = 9127; // 2 +static const uint64_t SH_FLD_FREEZE_SEL = 9128; // 43 +static const uint64_t SH_FLD_FREE_USAGE = 9129; // 1 +static const uint64_t SH_FLD_FREE_USAGE_10E = 9130; // 19 +static const uint64_t SH_FLD_FREE_USAGE_11E = 9131; // 19 +static const uint64_t SH_FLD_FREE_USAGE_12D = 9132; // 30 +static const uint64_t SH_FLD_FREE_USAGE_12E = 9133; // 39 +static const uint64_t SH_FLD_FREE_USAGE_13D = 9134; // 37 +static const uint64_t SH_FLD_FREE_USAGE_13E = 9135; // 39 +static const uint64_t SH_FLD_FREE_USAGE_14D = 9136; // 37 +static const uint64_t SH_FLD_FREE_USAGE_14E = 9137; // 41 +static const uint64_t SH_FLD_FREE_USAGE_15D = 9138; // 37 +static const uint64_t SH_FLD_FREE_USAGE_15E = 9139; // 41 +static const uint64_t SH_FLD_FREE_USAGE_16D = 9140; // 35 +static const uint64_t SH_FLD_FREE_USAGE_16E = 9141; // 41 +static const uint64_t SH_FLD_FREE_USAGE_17D = 9142; // 37 +static const uint64_t SH_FLD_FREE_USAGE_17E = 9143; // 41 +static const uint64_t SH_FLD_FREE_USAGE_18D = 9144; // 40 +static const uint64_t SH_FLD_FREE_USAGE_18E = 9145; // 41 +static const uint64_t SH_FLD_FREE_USAGE_19D = 9146; // 41 +static const uint64_t SH_FLD_FREE_USAGE_19E = 9147; // 41 +static const uint64_t SH_FLD_FREE_USAGE_20D = 9148; // 41 +static const uint64_t SH_FLD_FREE_USAGE_20E = 9149; // 41 +static const uint64_t SH_FLD_FREE_USAGE_21D = 9150; // 41 +static const uint64_t SH_FLD_FREE_USAGE_21E = 9151; // 43 +static const uint64_t SH_FLD_FREE_USAGE_22D = 9152; // 41 +static const uint64_t SH_FLD_FREE_USAGE_22E = 9153; // 43 +static const uint64_t SH_FLD_FREE_USAGE_23D = 9154; // 41 +static const uint64_t SH_FLD_FREE_USAGE_23E = 9155; // 43 +static const uint64_t SH_FLD_FREE_USAGE_24D = 9156; // 41 +static const uint64_t SH_FLD_FREE_USAGE_25D = 9157; // 41 +static const uint64_t SH_FLD_FREE_USAGE_26D = 9158; // 42 +static const uint64_t SH_FLD_FREE_USAGE_27D = 9159; // 42 +static const uint64_t SH_FLD_FREE_USAGE_28D = 9160; // 40 +static const uint64_t SH_FLD_FREE_USAGE_29D = 9161; // 40 +static const uint64_t SH_FLD_FREE_USAGE_30D = 9162; // 40 +static const uint64_t SH_FLD_FREE_USAGE_31D = 9163; // 42 +static const uint64_t SH_FLD_FREE_USAGE_3D = 9164; // 1 +static const uint64_t SH_FLD_FREE_USAGE_44C = 9165; // 43 +static const uint64_t SH_FLD_FREE_USAGE_45C = 9166; // 43 +static const uint64_t SH_FLD_FREE_USAGE_46C = 9167; // 43 +static const uint64_t SH_FLD_FREE_USAGE_47C = 9168; // 43 +static const uint64_t SH_FLD_FREE_USAGE_48A = 9169; // 43 +static const uint64_t SH_FLD_FREE_USAGE_49A = 9170; // 43 +static const uint64_t SH_FLD_FREE_USAGE_50A = 9171; // 43 +static const uint64_t SH_FLD_FREE_USAGE_51A = 9172; // 43 +static const uint64_t SH_FLD_FREE_USAGE_52A = 9173; // 43 +static const uint64_t SH_FLD_FREE_USAGE_53A = 9174; // 43 +static const uint64_t SH_FLD_FREE_USAGE_54A = 9175; // 43 +static const uint64_t SH_FLD_FREE_USAGE_55A = 9176; // 43 +static const uint64_t SH_FLD_FREE_USAGE_56A = 9177; // 43 +static const uint64_t SH_FLD_FREE_USAGE_57A = 9178; // 43 +static const uint64_t SH_FLD_FREE_USAGE_58A = 9179; // 43 +static const uint64_t SH_FLD_FREE_USAGE_59A = 9180; // 43 +static const uint64_t SH_FLD_FREE_USAGE_60A = 9181; // 43 +static const uint64_t SH_FLD_FREE_USAGE_61A = 9182; // 43 +static const uint64_t SH_FLD_FREE_USAGE_62A = 9183; // 43 +static const uint64_t SH_FLD_FREE_USAGE_63A = 9184; // 43 +static const uint64_t SH_FLD_FREE_USAGE_6A = 9185; // 37 +static const uint64_t SH_FLD_FREE_USAGE_7A = 9186; // 43 +static const uint64_t SH_FLD_FREE_USAGE_9A = 9187; // 43 +static const uint64_t SH_FLD_FREQFW = 9188; // 48 +static const uint64_t SH_FLD_FREQFW_LEN = 9189; // 48 +static const uint64_t SH_FLD_FREQIN_AVG = 9190; // 6 +static const uint64_t SH_FLD_FREQIN_AVG_LEN = 9191; // 6 +static const uint64_t SH_FLD_FREQIN_MAX = 9192; // 6 +static const uint64_t SH_FLD_FREQIN_MAX_LEN = 9193; // 6 +static const uint64_t SH_FLD_FREQIN_MIN = 9194; // 6 +static const uint64_t SH_FLD_FREQIN_MIN_LEN = 9195; // 6 +static const uint64_t SH_FLD_FREQOUT = 9196; // 6 +static const uint64_t SH_FLD_FREQOUT_AVG = 9197; // 6 +static const uint64_t SH_FLD_FREQOUT_AVG_LEN = 9198; // 6 +static const uint64_t SH_FLD_FREQOUT_LEN = 9199; // 6 +static const uint64_t SH_FLD_FREQOUT_MAX = 9200; // 6 +static const uint64_t SH_FLD_FREQOUT_MAX_LEN = 9201; // 6 +static const uint64_t SH_FLD_FREQOUT_MIN = 9202; // 6 +static const uint64_t SH_FLD_FREQOUT_MIN_LEN = 9203; // 6 +static const uint64_t SH_FLD_FREQUENCY_REFERENCE = 9204; // 24 +static const uint64_t SH_FLD_FREQUENCY_REFERENCE_LEN = 9205; // 24 +static const uint64_t SH_FLD_FREQ_CHANGE = 9206; // 6 +static const uint64_t SH_FLD_FREQ_LCL_SAMPLE_EN = 9207; // 12 +static const uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD = 9208; // 24 +static const uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN = 9209; // 24 +static const uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD = 9210; // 24 +static const uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN = 9211; // 24 +static const uint64_t SH_FLD_FRZ_COUNT_ON_FRZ = 9212; // 43 +static const uint64_t SH_FLD_FSAFE = 9213; // 6 +static const uint64_t SH_FLD_FSAFE_ACTIVE = 9214; // 6 +static const uint64_t SH_FLD_FSAFE_LEN = 9215; // 6 +static const uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR = 9216; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN = 9217; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_0_ENABLE = 9218; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_1_ENABLE = 9219; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_2_ENABLE = 9220; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_3_ENABLE = 9221; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_4_ENABLE = 9222; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_5_ENABLE = 9223; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_6_ENABLE = 9224; // 1 +static const uint64_t SH_FLD_FSI_A_MST_0_PORT_7_ENABLE = 9225; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR = 9226; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN = 9227; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_PORT_0_ENABLE = 9228; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_PORT_1_ENABLE = 9229; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_PORT_2_ENABLE = 9230; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_PORT_3_ENABLE = 9231; // 1 +static const uint64_t SH_FLD_FSI_A_MST_1_PORT_4_ENABLE = 9232; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR = 9233; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN = 9234; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_0_ENABLE = 9235; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_1_ENABLE = 9236; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_2_ENABLE = 9237; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_3_ENABLE = 9238; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_4_ENABLE = 9239; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_5_ENABLE = 9240; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_6_ENABLE = 9241; // 1 +static const uint64_t SH_FLD_FSI_B_MST_0_PORT_7_ENABLE = 9242; // 1 +static const uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD = 9243; // 3 +static const uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD_LEN = 9244; // 3 +static const uint64_t SH_FLD_FSI_CC_VSB_CBS_REQ = 9245; // 3 +static const uint64_t SH_FLD_FSI_INTERRUPT_HIGH = 9246; // 1 +static const uint64_t SH_FLD_FSI_INTERRUPT_PENDING = 9247; // 1 +static const uint64_t SH_FLD_FSI_SCRATCH_PAD1 = 9248; // 1 +static const uint64_t SH_FLD_FSI_SCRATCH_PAD1_LEN = 9249; // 1 +static const uint64_t SH_FLD_FSI_SCRATCH_PAD2 = 9250; // 1 +static const uint64_t SH_FLD_FSI_SCRATCH_PAD2_LEN = 9251; // 1 +static const uint64_t SH_FLD_FSI_SCRATCH_PAD3 = 9252; // 1 +static const uint64_t SH_FLD_FSI_SCRATCH_PAD3_LEN = 9253; // 1 +static const uint64_t SH_FLD_FSM = 9254; // 1 +static const uint64_t SH_FLD_FSM0 = 9255; // 1 +static const uint64_t SH_FLD_FSM0_LEN = 9256; // 1 +static const uint64_t SH_FLD_FSM1 = 9257; // 1 +static const uint64_t SH_FLD_FSM1_LEN = 9258; // 1 +static const uint64_t SH_FLD_FSMJ_EVENT = 9259; // 2 +static const uint64_t SH_FLD_FSMJ_EVENT_LEN = 9260; // 2 +static const uint64_t SH_FLD_FSMJ_EVENT_SEL = 9261; // 2 +static const uint64_t SH_FLD_FSMJ_EVENT_SEL_LEN = 9262; // 2 +static const uint64_t SH_FLD_FSMJ_FSM = 9263; // 2 +static const uint64_t SH_FLD_FSMJ_FSM_LEN = 9264; // 2 +static const uint64_t SH_FLD_FSMJ_FSM_SEL = 9265; // 2 +static const uint64_t SH_FLD_FSMJ_FSM_SEL_LEN = 9266; // 2 +static const uint64_t SH_FLD_FSM_DATA02 = 9267; // 1 +static const uint64_t SH_FLD_FSM_ERR = 9268; // 5 +static const uint64_t SH_FLD_FSM_ERROR = 9269; // 1 +static const uint64_t SH_FLD_FSM_LEN = 9270; // 1 +static const uint64_t SH_FLD_FSM_PARITY_ERROR = 9271; // 3 +static const uint64_t SH_FLD_FSM_PERR = 9272; // 1 +static const uint64_t SH_FLD_FSM_PRESENT_STATE = 9273; // 1 +static const uint64_t SH_FLD_FSM_PRESENT_STATE_LEN = 9274; // 1 +static const uint64_t SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 9275; // 43 +static const uint64_t SH_FLD_FSM_SM_ERROR = 9276; // 2 +static const uint64_t SH_FLD_FSM_SYNC_ENABLE = 9277; // 1 +static const uint64_t SH_FLD_FSM_TRIGGER = 9278; // 2 +static const uint64_t SH_FLD_FSP_ACCESS_TRUSTED_SPACE = 9279; // 4 +static const uint64_t SH_FLD_FSP_CMD_ENABLE = 9280; // 1 +static const uint64_t SH_FLD_FSP_ECC_ERR_CE = 9281; // 4 +static const uint64_t SH_FLD_FSP_ECC_ERR_UE = 9282; // 4 +static const uint64_t SH_FLD_FSP_ERR_RSP_ENABLE = 9283; // 1 +static const uint64_t SH_FLD_FSP_INBOUND_ACTIVE = 9284; // 1 +static const uint64_t SH_FLD_FSP_INTERRUPT = 9285; // 1 +static const uint64_t SH_FLD_FSP_INT_ENABLE = 9286; // 1 +static const uint64_t SH_FLD_FSP_INV_READ = 9287; // 1 +static const uint64_t SH_FLD_FSP_LINK_ACTIVE = 9288; // 1 +static const uint64_t SH_FLD_FSP_MMIO_ENABLE = 9289; // 1 +static const uint64_t SH_FLD_FSP_MMIO_MASK = 9290; // 1 +static const uint64_t SH_FLD_FSP_MMIO_MASK_LEN = 9291; // 1 +static const uint64_t SH_FLD_FSP_OUTBOUND_ACTIVE = 9292; // 1 +static const uint64_t SH_FLD_FSP_RESET = 9293; // 1 +static const uint64_t SH_FLD_FSP_SPECIAL_WKUP = 9294; // 30 +static const uint64_t SH_FLD_FSP_TCE_ENABLE = 9295; // 1 +static const uint64_t SH_FLD_FULL = 9296; // 2 +static const uint64_t SH_FLD_FULLMASK = 9297; // 1 +static const uint64_t SH_FLD_FULLMASK_LEN = 9298; // 1 +static const uint64_t SH_FLD_FULL_CHARGE_ON_DISPATCH_MODE = 9299; // 24 +static const uint64_t SH_FLD_FULL_WRITEBACK_ENABLE = 9300; // 6 +static const uint64_t SH_FLD_FUNC = 9301; // 43 +static const uint64_t SH_FLD_FUNCTION = 9302; // 6 +static const uint64_t SH_FLD_FUNCTION_LEN = 9303; // 6 +static const uint64_t SH_FLD_FUNC_MODE_DONE = 9304; // 4 +static const uint64_t SH_FLD_FUSED_CORE_MODE = 9305; // 24 +static const uint64_t SH_FLD_FW0 = 9306; // 1 +static const uint64_t SH_FLD_FW0_MASK = 9307; // 1 +static const uint64_t SH_FLD_FW1 = 9308; // 1 +static const uint64_t SH_FLD_FW1_MASK = 9309; // 1 +static const uint64_t SH_FLD_FWD_PROG_RATE2 = 9310; // 12 +static const uint64_t SH_FLD_FWD_PROG_RATE2_LEN = 9311; // 12 +static const uint64_t SH_FLD_FWD_PROG_THOLD = 9312; // 24 +static const uint64_t SH_FLD_FWD_PROG_THOLD_LEN = 9313; // 24 +static const uint64_t SH_FLD_FWMSX_PE = 9314; // 8 +static const uint64_t SH_FLD_FWMSX_PE_LEN = 9315; // 8 +static const uint64_t SH_FLD_FWSNAP = 9316; // 48 +static const uint64_t SH_FLD_FW_RD_WR = 9317; // 8 +static const uint64_t SH_FLD_FW_RD_WR_LEN = 9318; // 8 +static const uint64_t SH_FLD_FW_WR_RD = 9319; // 8 +static const uint64_t SH_FLD_FW_WR_RD_LEN = 9320; // 8 +static const uint64_t SH_FLD_F_READ = 9321; // 43 +static const uint64_t SH_FLD_F_RESET_CPM_RD = 9322; // 43 +static const uint64_t SH_FLD_F_RESET_CPM_WR = 9323; // 43 +static const uint64_t SH_FLD_F_SKITTER_ERR_HOLD = 9324; // 43 +static const uint64_t SH_FLD_F_SKITTER_READ_MASK = 9325; // 43 +static const uint64_t SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL = 9326; // 4 +static const uint64_t SH_FLD_GCR_HANG_DET_SEL = 9327; // 4 +static const uint64_t SH_FLD_GCR_HANG_DET_SEL_LEN = 9328; // 4 +static const uint64_t SH_FLD_GCR_HANG_ERROR = 9329; // 8 +static const uint64_t SH_FLD_GCR_HANG_ERROR_INJ = 9330; // 4 +static const uint64_t SH_FLD_GCR_HANG_ERROR_MASK = 9331; // 4 +static const uint64_t SH_FLD_GCR_TEST = 9332; // 4 +static const uint64_t SH_FLD_GENERAL_TIMEOUT = 9333; // 43 +static const uint64_t SH_FLD_GENERATE_MPIPL_SEQUENCE = 9334; // 4 +static const uint64_t SH_FLD_GLB_BRCST = 9335; // 43 +static const uint64_t SH_FLD_GLB_BRCST_LEN = 9336; // 43 +static const uint64_t SH_FLD_GLOBAL_EP_RESET_DC = 9337; // 3 +static const uint64_t SH_FLD_GLOBAL_PHY_OFFSET = 9338; // 8 +static const uint64_t SH_FLD_GLOBAL_PHY_OFFSET_LEN = 9339; // 8 +static const uint64_t SH_FLD_GLOBAL_RUN_MODE = 9340; // 2 +static const uint64_t SH_FLD_GLOB_FRZ_PMU_01 = 9341; // 24 +static const uint64_t SH_FLD_GLOB_FRZ_PMU_23 = 9342; // 24 +static const uint64_t SH_FLD_GLOB_FRZ_PMU_45 = 9343; // 24 +static const uint64_t SH_FLD_GLOB_FRZ_PMU_67 = 9344; // 24 +static const uint64_t SH_FLD_GND = 9345; // 24 +static const uint64_t SH_FLD_GND_LEN = 9346; // 24 +static const uint64_t SH_FLD_GO = 9347; // 43 +static const uint64_t SH_FLD_GO2 = 9348; // 43 +static const uint64_t SH_FLD_GOTO_CMD = 9349; // 64 +static const uint64_t SH_FLD_GOTO_CMD_LEN = 9350; // 64 +static const uint64_t SH_FLD_GP = 9351; // 2 +static const uint64_t SH_FLD_GPE0_ERROR = 9352; // 2 +static const uint64_t SH_FLD_GPE0_ERROR_MASK = 9353; // 1 +static const uint64_t SH_FLD_GPE0_HALTED = 9354; // 1 +static const uint64_t SH_FLD_GPE0_HALTED_MASK = 9355; // 1 +static const uint64_t SH_FLD_GPE0_OCISLV_ERR = 9356; // 2 +static const uint64_t SH_FLD_GPE0_OCISLV_ERR_LEN = 9357; // 1 +static const uint64_t SH_FLD_GPE0_OCISLV_ERR_MASK = 9358; // 1 +static const uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT = 9359; // 1 +static const uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT_MASK = 9360; // 1 +static const uint64_t SH_FLD_GPE1_ERROR = 9361; // 2 +static const uint64_t SH_FLD_GPE1_ERROR_MASK = 9362; // 1 +static const uint64_t SH_FLD_GPE1_HALTED = 9363; // 1 +static const uint64_t SH_FLD_GPE1_HALTED_MASK = 9364; // 1 +static const uint64_t SH_FLD_GPE1_OCISLV_ERR = 9365; // 2 +static const uint64_t SH_FLD_GPE1_OCISLV_ERR_LEN = 9366; // 1 +static const uint64_t SH_FLD_GPE1_OCISLV_ERR_MASK = 9367; // 1 +static const uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT = 9368; // 1 +static const uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT_MASK = 9369; // 1 +static const uint64_t SH_FLD_GPE2_ERROR = 9370; // 2 +static const uint64_t SH_FLD_GPE2_ERROR_MASK = 9371; // 1 +static const uint64_t SH_FLD_GPE2_HALTED = 9372; // 1 +static const uint64_t SH_FLD_GPE2_HALTED_MASK = 9373; // 1 +static const uint64_t SH_FLD_GPE2_OCISLV_ERR = 9374; // 2 +static const uint64_t SH_FLD_GPE2_OCISLV_ERR_LEN = 9375; // 1 +static const uint64_t SH_FLD_GPE2_OCISLV_ERR_MASK = 9376; // 1 +static const uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT = 9377; // 1 +static const uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT_MASK = 9378; // 1 +static const uint64_t SH_FLD_GPE3_ERROR = 9379; // 2 +static const uint64_t SH_FLD_GPE3_ERROR_MASK = 9380; // 1 +static const uint64_t SH_FLD_GPE3_HALTED = 9381; // 1 +static const uint64_t SH_FLD_GPE3_HALTED_MASK = 9382; // 1 +static const uint64_t SH_FLD_GPE3_OCISLV_ERR = 9383; // 2 +static const uint64_t SH_FLD_GPE3_OCISLV_ERR_LEN = 9384; // 1 +static const uint64_t SH_FLD_GPE3_OCISLV_ERR_MASK = 9385; // 1 +static const uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT = 9386; // 1 +static const uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT_MASK = 9387; // 1 +static const uint64_t SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 9388; // 3 +static const uint64_t SH_FLD_GRANTED_PACKET = 9389; // 30 +static const uint64_t SH_FLD_GRANTED_PACKET_LEN = 9390; // 30 +static const uint64_t SH_FLD_GRANTED_SOURCE = 9391; // 30 +static const uint64_t SH_FLD_GRANTED_SOURCE_LEN = 9392; // 30 +static const uint64_t SH_FLD_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 9393; // 24 +static const uint64_t SH_FLD_GROUP = 9394; // 9 +static const uint64_t SH_FLD_GROUPING = 9395; // 8 +static const uint64_t SH_FLD_GROUPING_LEN = 9396; // 8 +static const uint64_t SH_FLD_GROUP_BASE_ADDRESS = 9397; // 8 +static const uint64_t SH_FLD_GROUP_BASE_ADDRESS_LEN = 9398; // 8 +static const uint64_t SH_FLD_GROUP_EPSILON = 9399; // 8 +static const uint64_t SH_FLD_GROUP_EPSILON_LEN = 9400; // 8 +static const uint64_t SH_FLD_GROUP_LEN = 9401; // 9 +static const uint64_t SH_FLD_GROUP_SEL_0_4 = 9402; // 1 +static const uint64_t SH_FLD_GROUP_SEL_0_4_LEN = 9403; // 1 +static const uint64_t SH_FLD_GROUP_SIZE = 9404; // 8 +static const uint64_t SH_FLD_GROUP_SIZE_LEN = 9405; // 8 +static const uint64_t SH_FLD_GRPSEL = 9406; // 2 +static const uint64_t SH_FLD_GRPSEL_LEN = 9407; // 2 +static const uint64_t SH_FLD_GRP_BASE = 9408; // 8 +static const uint64_t SH_FLD_GRP_BASE_LEN = 9409; // 8 +static const uint64_t SH_FLD_GRP_MBR_ID = 9410; // 8 +static const uint64_t SH_FLD_GRP_SIZE = 9411; // 8 +static const uint64_t SH_FLD_GRP_SIZE_LEN = 9412; // 8 +static const uint64_t SH_FLD_GTSE = 9413; // 96 +static const uint64_t SH_FLD_GUESS_WAIT_TIME = 9414; // 8 +static const uint64_t SH_FLD_GUESS_WAIT_TIME_LEN = 9415; // 8 +static const uint64_t SH_FLD_GUEST_PREF_PGSZ = 9416; // 1 +static const uint64_t SH_FLD_GUEST_PREF_PGSZ_LEN = 9417; // 1 +static const uint64_t SH_FLD_GX = 9418; // 2 +static const uint64_t SH_FLD_GXDATAAVAIL_Q = 9419; // 1 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN0 = 9420; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN1 = 9421; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN10 = 9422; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN11 = 9423; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN2 = 9424; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN3 = 9425; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN4 = 9426; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN5 = 9427; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN6 = 9428; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN7 = 9429; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN8 = 9430; // 43 +static const uint64_t SH_FLD_GXSTP0_TRIG_IN9 = 9431; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN0 = 9432; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN1 = 9433; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN10 = 9434; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN11 = 9435; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN2 = 9436; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN3 = 9437; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN4 = 9438; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN5 = 9439; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN6 = 9440; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN7 = 9441; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN8 = 9442; // 43 +static const uint64_t SH_FLD_GXSTP1_TRIG_IN9 = 9443; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN0 = 9444; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN1 = 9445; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN10 = 9446; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN11 = 9447; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN2 = 9448; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN3 = 9449; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN4 = 9450; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN5 = 9451; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN6 = 9452; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN7 = 9453; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN8 = 9454; // 43 +static const uint64_t SH_FLD_GXSTP2_TRIG_IN9 = 9455; // 43 +static const uint64_t SH_FLD_GXSTP_IN0 = 9456; // 43 +static const uint64_t SH_FLD_GXSTP_IN1 = 9457; // 43 +static const uint64_t SH_FLD_GXSTP_IN10 = 9458; // 43 +static const uint64_t SH_FLD_GXSTP_IN11 = 9459; // 43 +static const uint64_t SH_FLD_GXSTP_IN2 = 9460; // 43 +static const uint64_t SH_FLD_GXSTP_IN3 = 9461; // 43 +static const uint64_t SH_FLD_GXSTP_IN4 = 9462; // 43 +static const uint64_t SH_FLD_GXSTP_IN5 = 9463; // 43 +static const uint64_t SH_FLD_GXSTP_IN6 = 9464; // 43 +static const uint64_t SH_FLD_GXSTP_IN7 = 9465; // 43 +static const uint64_t SH_FLD_GXSTP_IN8 = 9466; // 43 +static const uint64_t SH_FLD_GXSTP_IN9 = 9467; // 43 +static const uint64_t SH_FLD_GX_ENABLE_OVERWRITE = 9468; // 1 +static const uint64_t SH_FLD_GX_LEN = 9469; // 2 +static const uint64_t SH_FLD_GZIPCOMP_MAX_INRD = 9470; // 1 +static const uint64_t SH_FLD_GZIPCOMP_MAX_INRD_LEN = 9471; // 1 +static const uint64_t SH_FLD_GZIPDECOMP_MAX_INRD = 9472; // 1 +static const uint64_t SH_FLD_GZIPDECOMP_MAX_INRD_LEN = 9473; // 1 +static const uint64_t SH_FLD_GZIP_COMP_PREFETCH_ENABLE = 9474; // 1 +static const uint64_t SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE = 9475; // 1 +static const uint64_t SH_FLD_GZIP_FC_SELECT = 9476; // 1 +static const uint64_t SH_FLD_GZIP_FC_SELECT_LEN = 9477; // 1 +static const uint64_t SH_FLD_GZIP_LATENCY_CFG = 9478; // 1 +static const uint64_t SH_FLD_GZIP_MUX_SELECT = 9479; // 1 +static const uint64_t SH_FLD_GZIP_MUX_SELECT_LEN = 9480; // 1 +static const uint64_t SH_FLD_H1AP_CFG = 9481; // 6 +static const uint64_t SH_FLD_H1AP_CFG_LEN = 9482; // 6 +static const uint64_t SH_FLD_HALF_RATE_MODE = 9483; // 12 +static const uint64_t SH_FLD_HALTED = 9484; // 7 +static const uint64_t SH_FLD_HALT_INPUT = 9485; // 13 +static const uint64_t SH_FLD_HALT_ON_TRIG = 9486; // 17 +static const uint64_t SH_FLD_HALT_ON_XSTOP = 9487; // 17 +static const uint64_t SH_FLD_HALT_ROTATION = 9488; // 8 +static const uint64_t SH_FLD_HANDSHAKE_STATE = 9489; // 2 +static const uint64_t SH_FLD_HANDSHAKE_STATE_LEN = 9490; // 2 +static const uint64_t SH_FLD_HANG_DATA_SCALE = 9491; // 5 +static const uint64_t SH_FLD_HANG_DATA_SCALE_LEN = 9492; // 5 +static const uint64_t SH_FLD_HANG_DIVIDER_CMD = 9493; // 1 +static const uint64_t SH_FLD_HANG_DIVIDER_CMD_LEN = 9494; // 1 +static const uint64_t SH_FLD_HANG_DIVIDER_DATA = 9495; // 1 +static const uint64_t SH_FLD_HANG_DIVIDER_DATA_LEN = 9496; // 1 +static const uint64_t SH_FLD_HANG_ON_ACK_DEAD = 9497; // 1 +static const uint64_t SH_FLD_HANG_ON_ADDR_ERROR = 9498; // 1 +static const uint64_t SH_FLD_HANG_PE_SCALE = 9499; // 3 +static const uint64_t SH_FLD_HANG_PE_SCALE_LEN = 9500; // 3 +static const uint64_t SH_FLD_HANG_PIB_RESET = 9501; // 1 +static const uint64_t SH_FLD_HANG_PLS_MULT = 9502; // 1 +static const uint64_t SH_FLD_HANG_PLS_MULT_LEN = 9503; // 1 +static const uint64_t SH_FLD_HANG_POLL_ENABLE = 9504; // 2 +static const uint64_t SH_FLD_HANG_POLL_PULSE_DIV = 9505; // 24 +static const uint64_t SH_FLD_HANG_POLL_PULSE_DIV_LEN = 9506; // 24 +static const uint64_t SH_FLD_HANG_POLL_SCALE = 9507; // 7 +static const uint64_t SH_FLD_HANG_POLL_SCALE_LEN = 9508; // 7 +static const uint64_t SH_FLD_HANG_RECOVERY_GTE_LEVEL1 = 9509; // 2 +static const uint64_t SH_FLD_HANG_RECOVERY_LIMIT_ERROR = 9510; // 2 +static const uint64_t SH_FLD_HANG_RESET = 9511; // 1 +static const uint64_t SH_FLD_HANG_SHM_SCALE = 9512; // 2 +static const uint64_t SH_FLD_HANG_SHM_SCALE_LEN = 9513; // 2 +static const uint64_t SH_FLD_HANG_SM_ON_ARE = 9514; // 2 +static const uint64_t SH_FLD_HANG_SM_ON_LINK_FAIL = 9515; // 2 +static const uint64_t SH_FLD_HARD_CE_COUNT = 9516; // 2 +static const uint64_t SH_FLD_HARD_CE_COUNT_LEN = 9517; // 2 +static const uint64_t SH_FLD_HARD_MCE_COUNT = 9518; // 2 +static const uint64_t SH_FLD_HARD_MCE_COUNT_LEN = 9519; // 2 +static const uint64_t SH_FLD_HARD_NCE_ETE_ATTN = 9520; // 2 +static const uint64_t SH_FLD_HASH_LPID_DIS = 9521; // 1 +static const uint64_t SH_FLD_HASH_PID_DIS = 9522; // 1 +static const uint64_t SH_FLD_HASH_SIZE_MASK = 9523; // 1 +static const uint64_t SH_FLD_HASH_SIZE_MASK_LEN = 9524; // 1 +static const uint64_t SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS = 9525; // 4 +static const uint64_t SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS = 9526; // 4 +static const uint64_t SH_FLD_HB_ERROR = 9527; // 1 +static const uint64_t SH_FLD_HB_MALF_MASK = 9528; // 1 +static const uint64_t SH_FLD_HDEC = 9529; // 96 +static const uint64_t SH_FLD_HDEC_LEN = 9530; // 96 +static const uint64_t SH_FLD_HDEC_PARITY_ERROR = 9531; // 96 +static const uint64_t SH_FLD_HDICE = 9532; // 192 +static const uint64_t SH_FLD_HDR_ARR_ECC_CORR_ENA = 9533; // 6 +static const uint64_t SH_FLD_HDR_ARR_ECC_SUE_ENA = 9534; // 6 +static const uint64_t SH_FLD_HEIC = 9535; // 96 +static const uint64_t SH_FLD_HI = 9536; // 1 +static const uint64_t SH_FLD_HIGH = 9537; // 1 +static const uint64_t SH_FLD_HIGH_IDLE_COUNT = 9538; // 8 +static const uint64_t SH_FLD_HIGH_IDLE_COUNT_LEN = 9539; // 8 +static const uint64_t SH_FLD_HIGH_IDLE_THRESHOLD = 9540; // 8 +static const uint64_t SH_FLD_HIGH_IDLE_THRESHOLD_LEN = 9541; // 8 +static const uint64_t SH_FLD_HIGH_LEN = 9542; // 1 +static const uint64_t SH_FLD_HILE = 9543; // 24 +static const uint64_t SH_FLD_HIRES_FMAX = 9544; // 6 +static const uint64_t SH_FLD_HIRES_FMAX_LEN = 9545; // 6 +static const uint64_t SH_FLD_HIRES_FMIN = 9546; // 6 +static const uint64_t SH_FLD_HIRES_FMIN_LEN = 9547; // 6 +static const uint64_t SH_FLD_HIRES_FMULT = 9548; // 6 +static const uint64_t SH_FLD_HIRES_FMULT_LEN = 9549; // 6 +static const uint64_t SH_FLD_HIRES_FREQIN_AVG = 9550; // 6 +static const uint64_t SH_FLD_HIRES_FREQIN_AVG_LEN = 9551; // 6 +static const uint64_t SH_FLD_HIRES_FREQIN_MAX = 9552; // 6 +static const uint64_t SH_FLD_HIRES_FREQIN_MAX_LEN = 9553; // 6 +static const uint64_t SH_FLD_HIRES_FREQIN_MIN = 9554; // 6 +static const uint64_t SH_FLD_HIRES_FREQIN_MIN_LEN = 9555; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT = 9556; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_AVG = 9557; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_AVG_LEN = 9558; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_LEN = 9559; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_MAX = 9560; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_MAX_LEN = 9561; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_MIN = 9562; // 6 +static const uint64_t SH_FLD_HIRES_FREQOUT_MIN_LEN = 9563; // 6 +static const uint64_t SH_FLD_HIST = 9564; // 6 +static const uint64_t SH_FLD_HISTORY_PRBS_POWER_UP = 9565; // 72 +static const uint64_t SH_FLD_HIST_ADDRESS = 9566; // 1 +static const uint64_t SH_FLD_HIST_ADDRESS_LEN = 9567; // 1 +static const uint64_t SH_FLD_HIST_DONE = 9568; // 1 +static const uint64_t SH_FLD_HIST_FREEZE_HISTORY = 9569; // 1 +static const uint64_t SH_FLD_HIST_LEN = 9570; // 6 +static const uint64_t SH_FLD_HIST_MANUAL_MODE_EN = 9571; // 1 +static const uint64_t SH_FLD_HIST_MASK = 9572; // 1 +static const uint64_t SH_FLD_HIST_MASK_LEN = 9573; // 1 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT = 9574; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE = 9575; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN = 9576; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LEN = 9577; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE = 9578; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN = 9579; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_VALID = 9580; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH = 9581; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE = 9582; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN = 9583; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LEN = 9584; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE = 9585; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN = 9586; // 6 +static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_VALID = 9587; // 6 +static const uint64_t SH_FLD_HIST_RESERVED = 9588; // 1 +static const uint64_t SH_FLD_HIST_RESERVED_LEN = 9589; // 1 +static const uint64_t SH_FLD_HIST_RESET_HISTORY = 9590; // 1 +static const uint64_t SH_FLD_HIST_START_NOT_STOP = 9591; // 1 +static const uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT = 9592; // 1 +static const uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT_LEN = 9593; // 1 +static const uint64_t SH_FLD_HIST_TRACE_TRAFFIC = 9594; // 1 +static const uint64_t SH_FLD_HI_ENABLE = 9595; // 2 +static const uint64_t SH_FLD_HI_FIXED_WINDOW_MODE = 9596; // 2 +static const uint64_t SH_FLD_HI_PRESCALE_MODE = 9597; // 2 +static const uint64_t SH_FLD_HI_SELECT = 9598; // 2 +static const uint64_t SH_FLD_HI_SELECT_LEN = 9599; // 2 +static const uint64_t SH_FLD_HMI_ACTIVE = 9600; // 1 +static const uint64_t SH_FLD_HMI_EXIT_ENABLE = 9601; // 96 +static const uint64_t SH_FLD_HMI_REQUEST_C0 = 9602; // 12 +static const uint64_t SH_FLD_HMI_REQUEST_C1 = 9603; // 12 +static const uint64_t SH_FLD_HOLD = 9604; // 2 +static const uint64_t SH_FLD_HOLD_0 = 9605; // 8 +static const uint64_t SH_FLD_HOLD_0_48 = 9606; // 1 +static const uint64_t SH_FLD_HOLD_0_48_LEN = 9607; // 1 +static const uint64_t SH_FLD_HOLD_1 = 9608; // 8 +static const uint64_t SH_FLD_HOLD_ADDRESS = 9609; // 162 +static const uint64_t SH_FLD_HOLD_ADDRESS_LEN = 9610; // 162 +static const uint64_t SH_FLD_HOLD_DBGTRIG_SEL = 9611; // 43 +static const uint64_t SH_FLD_HOLD_DBGTRIG_SEL_LEN = 9612; // 43 +static const uint64_t SH_FLD_HOLD_LEN = 9613; // 2 +static const uint64_t SH_FLD_HOLD_SAMPLE = 9614; // 43 +static const uint64_t SH_FLD_HOLD_SAMPLE_WITH_TRIGGER = 9615; // 43 +static const uint64_t SH_FLD_HOLE0_LOWER_ADDRESS = 9616; // 8 +static const uint64_t SH_FLD_HOLE0_LOWER_ADDRESS_LEN = 9617; // 8 +static const uint64_t SH_FLD_HOLE0_UPPER_ADDRESS = 9618; // 8 +static const uint64_t SH_FLD_HOLE0_UPPER_ADDRESS_LEN = 9619; // 8 +static const uint64_t SH_FLD_HOLE0_VALID = 9620; // 8 +static const uint64_t SH_FLD_HOLE1_LOWER_ADDRESS = 9621; // 8 +static const uint64_t SH_FLD_HOLE1_LOWER_ADDRESS_LEN = 9622; // 8 +static const uint64_t SH_FLD_HOLE1_UPPER_ADDRESS = 9623; // 8 +static const uint64_t SH_FLD_HOLE1_UPPER_ADDRESS_LEN = 9624; // 8 +static const uint64_t SH_FLD_HOLE1_VALID = 9625; // 8 +static const uint64_t SH_FLD_HOST_PREF_PGSZ = 9626; // 1 +static const uint64_t SH_FLD_HOST_PREF_PGSZ_LEN = 9627; // 1 +static const uint64_t SH_FLD_HOTNESS_RESET = 9628; // 96 +static const uint64_t SH_FLD_HOTNESS_RESET_LEN = 9629; // 96 +static const uint64_t SH_FLD_HOTNESS_THRESH = 9630; // 96 +static const uint64_t SH_FLD_HOTNESS_THRESH_LEN = 9631; // 96 +static const uint64_t SH_FLD_HOT_PLUG_FLAG = 9632; // 24 +static const uint64_t SH_FLD_HRMOR = 9633; // 1 +static const uint64_t SH_FLD_HRMOR_LEN = 9634; // 1 +static const uint64_t SH_FLD_HSRR0 = 9635; // 144 +static const uint64_t SH_FLD_HSRR0_LEN = 9636; // 144 +static const uint64_t SH_FLD_HSSCALERR = 9637; // 6 +static const uint64_t SH_FLD_HSSPLLAERR = 9638; // 6 +static const uint64_t SH_FLD_HSSPLLBERR = 9639; // 6 +static const uint64_t SH_FLD_HS_PROBE_TOP_SEL = 9640; // 8 +static const uint64_t SH_FLD_HTABORG = 9641; // 96 +static const uint64_t SH_FLD_HTABORG_LEN = 9642; // 96 +static const uint64_t SH_FLD_HTABSIZE = 9643; // 96 +static const uint64_t SH_FLD_HTABSIZE_LEN = 9644; // 96 +static const uint64_t SH_FLD_HTB_EXTEST = 9645; // 43 +static const uint64_t SH_FLD_HTB_INTEST = 9646; // 43 +static const uint64_t SH_FLD_HTMCO_STATUS_ADDR_ERROR = 9647; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_BUF_WAIT = 9648; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_COMPLETE = 9649; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_CRESP_OV = 9650; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_ENABLE = 9651; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_FLUSH = 9652; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_INIT = 9653; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_PAUSED = 9654; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_PREREQ = 9655; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_PURGE_DONE = 9656; // 24 +static const uint64_t SH_FLD_HTMCO_STATUS_PURGE_IN_PROG = 9657; // 24 +static const uint64_t SH_FLD_HTMCO_STATUS_READY = 9658; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_REPAIR = 9659; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_SPARE = 9660; // 2 +static const uint64_t SH_FLD_HTMCO_STATUS_SPARE_LEN = 9661; // 2 +static const uint64_t SH_FLD_HTMCO_STATUS_STAMP = 9662; // 26 +static const uint64_t SH_FLD_HTMCO_STATUS_TRACING = 9663; // 26 +static const uint64_t SH_FLD_HTMSC = 9664; // 24 +static const uint64_t SH_FLD_HTMSC_ALLOC = 9665; // 26 +static const uint64_t SH_FLD_HTMSC_BASE = 9666; // 26 +static const uint64_t SH_FLD_HTMSC_BASE_LEN = 9667; // 26 +static const uint64_t SH_FLD_HTMSC_CAPTURE = 9668; // 26 +static const uint64_t SH_FLD_HTMSC_CAPTURE_LEN = 9669; // 26 +static const uint64_t SH_FLD_HTMSC_CHIP0_STOP = 9670; // 24 +static const uint64_t SH_FLD_HTMSC_CHIP1_STOP = 9671; // 24 +static const uint64_t SH_FLD_HTMSC_CONTENT_SEL = 9672; // 26 +static const uint64_t SH_FLD_HTMSC_CONTENT_SEL_LEN = 9673; // 26 +static const uint64_t SH_FLD_HTMSC_COUNT = 9674; // 24 +static const uint64_t SH_FLD_HTMSC_COUNT_LEN = 9675; // 24 +static const uint64_t SH_FLD_HTMSC_CRESPFILT_INVERT = 9676; // 2 +static const uint64_t SH_FLD_HTMSC_CRESP_MASK = 9677; // 2 +static const uint64_t SH_FLD_HTMSC_CRESP_MASK_LEN = 9678; // 2 +static const uint64_t SH_FLD_HTMSC_CRESP_PAT = 9679; // 2 +static const uint64_t SH_FLD_HTMSC_CRESP_PAT_LEN = 9680; // 2 +static const uint64_t SH_FLD_HTMSC_DBG0_STOP = 9681; // 26 +static const uint64_t SH_FLD_HTMSC_DBG1_STOP = 9682; // 26 +static const uint64_t SH_FLD_HTMSC_DD1EQUIV = 9683; // 24 +static const uint64_t SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR = 9684; // 2 +static const uint64_t SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE = 9685; // 2 +static const uint64_t SH_FLD_HTMSC_DIS_GROUP = 9686; // 24 +static const uint64_t SH_FLD_HTMSC_DIS_OPER_HANG = 9687; // 2 +static const uint64_t SH_FLD_HTMSC_DIS_RETRY_BACKOFF = 9688; // 2 +static const uint64_t SH_FLD_HTMSC_DIS_STALL = 9689; // 24 +static const uint64_t SH_FLD_HTMSC_DIS_TSTAMP = 9690; // 26 +static const uint64_t SH_FLD_HTMSC_ENABLE = 9691; // 26 +static const uint64_t SH_FLD_HTMSC_ENABLE_SPLIT_CORE = 9692; // 24 +static const uint64_t SH_FLD_HTMSC_ERROR = 9693; // 24 +static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0 = 9694; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN = 9695; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1 = 9696; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN = 9697; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2 = 9698; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN = 9699; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0 = 9700; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN = 9701; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1 = 9702; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN = 9703; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2 = 9704; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN = 9705; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3 = 9706; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN = 9707; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4 = 9708; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN = 9709; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5 = 9710; // 2 +static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN = 9711; // 2 +static const uint64_t SH_FLD_HTMSC_FSM = 9712; // 24 +static const uint64_t SH_FLD_HTMSC_FSM_LEN = 9713; // 24 +static const uint64_t SH_FLD_HTMSC_INVERT = 9714; // 2 +static const uint64_t SH_FLD_HTMSC_LEN = 9715; // 24 +static const uint64_t SH_FLD_HTMSC_MARK = 9716; // 26 +static const uint64_t SH_FLD_HTMSC_MARKERS_ONLY = 9717; // 26 +static const uint64_t SH_FLD_HTMSC_MARK_LEN = 9718; // 26 +static const uint64_t SH_FLD_HTMSC_MARK_TYPE = 9719; // 26 +static const uint64_t SH_FLD_HTMSC_MARK_TYPE_LEN = 9720; // 26 +static const uint64_t SH_FLD_HTMSC_MARK_VALID = 9721; // 26 +static const uint64_t SH_FLD_HTMSC_MASK = 9722; // 4 +static const uint64_t SH_FLD_HTMSC_MASK_LEN = 9723; // 4 +static const uint64_t SH_FLD_HTMSC_MTSPR_MARK = 9724; // 24 +static const uint64_t SH_FLD_HTMSC_MTSPR_TRIG = 9725; // 24 +static const uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO = 9726; // 2 +static const uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN = 9727; // 2 +static const uint64_t SH_FLD_HTMSC_OTHER_DBG0_STOP = 9728; // 2 +static const uint64_t SH_FLD_HTMSC_PAT = 9729; // 4 +static const uint64_t SH_FLD_HTMSC_PAT_LEN = 9730; // 4 +static const uint64_t SH_FLD_HTMSC_PAUSE = 9731; // 26 +static const uint64_t SH_FLD_HTMSC_PDBAR_ERROR = 9732; // 24 +static const uint64_t SH_FLD_HTMSC_PRIORITY = 9733; // 26 +static const uint64_t SH_FLD_HTMSC_RESERVED = 9734; // 24 +static const uint64_t SH_FLD_HTMSC_RESERVED_LEN = 9735; // 24 +static const uint64_t SH_FLD_HTMSC_RESET = 9736; // 26 +static const uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT = 9737; // 2 +static const uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT_LEN = 9738; // 2 +static const uint64_t SH_FLD_HTMSC_RUN_STOP = 9739; // 26 +static const uint64_t SH_FLD_HTMSC_SCOPE = 9740; // 50 +static const uint64_t SH_FLD_HTMSC_SCOPE_LEN = 9741; // 50 +static const uint64_t SH_FLD_HTMSC_SINGLE_TSTAMP = 9742; // 26 +static const uint64_t SH_FLD_HTMSC_SIZE = 9743; // 26 +static const uint64_t SH_FLD_HTMSC_SIZE_LEN = 9744; // 26 +static const uint64_t SH_FLD_HTMSC_SIZE_SMALL = 9745; // 26 +static const uint64_t SH_FLD_HTMSC_SPARE = 9746; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE0 = 9747; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE1012 = 9748; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE1012_LEN = 9749; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE1112 = 9750; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE1112_LEN = 9751; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE1415 = 9752; // 26 +static const uint64_t SH_FLD_HTMSC_SPARE1415_LEN = 9753; // 26 +static const uint64_t SH_FLD_HTMSC_SPARE16 = 9754; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE23 = 9755; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE2TO4 = 9756; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE2TO4_LEN = 9757; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE3 = 9758; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE4043 = 9759; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE4043_LEN = 9760; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE67 = 9761; // 2 +static const uint64_t SH_FLD_HTMSC_SPARE67_LEN = 9762; // 2 +static const uint64_t SH_FLD_HTMSC_SPARES = 9763; // 24 +static const uint64_t SH_FLD_HTMSC_SPARES_LEN = 9764; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE_1TO2 = 9765; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE_1TO2_LEN = 9766; // 24 +static const uint64_t SH_FLD_HTMSC_SPARE_LEN = 9767; // 24 +static const uint64_t SH_FLD_HTMSC_START = 9768; // 26 +static const uint64_t SH_FLD_HTMSC_STOP = 9769; // 26 +static const uint64_t SH_FLD_HTMSC_STOP_ALT = 9770; // 26 +static const uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE = 9771; // 2 +static const uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN = 9772; // 2 +static const uint64_t SH_FLD_HTMSC_TRACE_ACTIVE = 9773; // 24 +static const uint64_t SH_FLD_HTMSC_TRIG = 9774; // 26 +static const uint64_t SH_FLD_HTMSC_TRIG_LEN = 9775; // 26 +static const uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK = 9776; // 2 +static const uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK_LEN = 9777; // 2 +static const uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT = 9778; // 2 +static const uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT_LEN = 9779; // 2 +static const uint64_t SH_FLD_HTMSC_VGTARGET = 9780; // 26 +static const uint64_t SH_FLD_HTMSC_VGTARGET_LEN = 9781; // 26 +static const uint64_t SH_FLD_HTMSC_WRAP = 9782; // 26 +static const uint64_t SH_FLD_HTMSC_WRITETOIO = 9783; // 2 +static const uint64_t SH_FLD_HTMSC_XSTOP_STOP = 9784; // 26 +static const uint64_t SH_FLD_HTM_CMD_OVERRUN = 9785; // 1 +static const uint64_t SH_FLD_HTM_GPE_SRC_SEL = 9786; // 1 +static const uint64_t SH_FLD_HTM_GPE_SRC_SEL_LEN = 9787; // 1 +static const uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS = 9788; // 1 +static const uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN = 9789; // 1 +static const uint64_t SH_FLD_HTM_QUEUE_LIMIT = 9790; // 12 +static const uint64_t SH_FLD_HTM_QUEUE_LIMIT_LEN = 9791; // 12 +static const uint64_t SH_FLD_HTM_SRC_SEL = 9792; // 1 +static const uint64_t SH_FLD_HTM_SRC_SEL_LEN = 9793; // 1 +static const uint64_t SH_FLD_HTM_STOP = 9794; // 1 +static const uint64_t SH_FLD_HUC = 9795; // 1 +static const uint64_t SH_FLD_HUC_LEN = 9796; // 1 +static const uint64_t SH_FLD_HUT = 9797; // 1 +static const uint64_t SH_FLD_HUT_LEN = 9798; // 1 +static const uint64_t SH_FLD_HV = 9799; // 96 +static const uint64_t SH_FLD_HVICE = 9800; // 96 +static const uint64_t SH_FLD_HV_AUTO_INC = 9801; // 6 +static const uint64_t SH_FLD_HV_REQ_4B = 9802; // 6 +static const uint64_t SH_FLD_HV_REQ_ADDR_VALUE = 9803; // 6 +static const uint64_t SH_FLD_HV_REQ_ADDR_VALUE_LEN = 9804; // 6 +static const uint64_t SH_FLD_HV_REQ_ADDR_VLD = 9805; // 6 +static const uint64_t SH_FLD_HWCTRL = 9806; // 2 +static const uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER = 9807; // 1 +static const uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN = 9808; // 1 +static const uint64_t SH_FLD_HWCTRL_CPHA = 9809; // 1 +static const uint64_t SH_FLD_HWCTRL_CPOL = 9810; // 1 +static const uint64_t SH_FLD_HWCTRL_DEVICE = 9811; // 1 +static const uint64_t SH_FLD_HWCTRL_FRAME_SIZE = 9812; // 1 +static const uint64_t SH_FLD_HWCTRL_FRAME_SIZE_LEN = 9813; // 1 +static const uint64_t SH_FLD_HWCTRL_FSM_ENABLE = 9814; // 1 +static const uint64_t SH_FLD_HWCTRL_FSM_ERR = 9815; // 1 +static const uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY = 9816; // 1 +static const uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN = 9817; // 1 +static const uint64_t SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES = 9818; // 1 +static const uint64_t SH_FLD_HWCTRL_IN_COUNT = 9819; // 1 +static const uint64_t SH_FLD_HWCTRL_IN_COUNT_LEN = 9820; // 1 +static const uint64_t SH_FLD_HWCTRL_IN_DELAY = 9821; // 1 +static const uint64_t SH_FLD_HWCTRL_IN_DELAY_LEN = 9822; // 1 +static const uint64_t SH_FLD_HWCTRL_LEN = 9823; // 2 +static const uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES = 9824; // 1 +static const uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES_LEN = 9825; // 1 +static const uint64_t SH_FLD_HWCTRL_ONGOING = 9826; // 1 +static const uint64_t SH_FLD_HWCTRL_OUT_COUNT = 9827; // 1 +static const uint64_t SH_FLD_HWCTRL_OUT_COUNT_LEN = 9828; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA0 = 9829; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA0_LEN = 9830; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA1 = 9831; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA1_LEN = 9832; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA2 = 9833; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA2_LEN = 9834; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA3 = 9835; // 1 +static const uint64_t SH_FLD_HWCTRL_RDATA3_LEN = 9836; // 1 +static const uint64_t SH_FLD_HWCTRL_START_SAMPLING = 9837; // 1 +static const uint64_t SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 9838; // 1 +static const uint64_t SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 9839; // 1 +static const uint64_t SH_FLD_HWD = 9840; // 1 +static const uint64_t SH_FLD_HWD_0 = 9841; // 1 +static const uint64_t SH_FLD_HWD_0_LEN = 9842; // 1 +static const uint64_t SH_FLD_HWD_10 = 9843; // 1 +static const uint64_t SH_FLD_HWD_10_LEN = 9844; // 1 +static const uint64_t SH_FLD_HWD_11 = 9845; // 1 +static const uint64_t SH_FLD_HWD_11_LEN = 9846; // 1 +static const uint64_t SH_FLD_HWD_12 = 9847; // 1 +static const uint64_t SH_FLD_HWD_12_LEN = 9848; // 1 +static const uint64_t SH_FLD_HWD_13 = 9849; // 1 +static const uint64_t SH_FLD_HWD_13_LEN = 9850; // 1 +static const uint64_t SH_FLD_HWD_14 = 9851; // 1 +static const uint64_t SH_FLD_HWD_14_LEN = 9852; // 1 +static const uint64_t SH_FLD_HWD_15 = 9853; // 1 +static const uint64_t SH_FLD_HWD_15_LEN = 9854; // 1 +static const uint64_t SH_FLD_HWD_2 = 9855; // 1 +static const uint64_t SH_FLD_HWD_2_LEN = 9856; // 1 +static const uint64_t SH_FLD_HWD_3 = 9857; // 1 +static const uint64_t SH_FLD_HWD_3_LEN = 9858; // 1 +static const uint64_t SH_FLD_HWD_4 = 9859; // 1 +static const uint64_t SH_FLD_HWD_4_LEN = 9860; // 1 +static const uint64_t SH_FLD_HWD_5 = 9861; // 1 +static const uint64_t SH_FLD_HWD_5_LEN = 9862; // 1 +static const uint64_t SH_FLD_HWD_6 = 9863; // 1 +static const uint64_t SH_FLD_HWD_6_LEN = 9864; // 1 +static const uint64_t SH_FLD_HWD_7 = 9865; // 1 +static const uint64_t SH_FLD_HWD_7_LEN = 9866; // 1 +static const uint64_t SH_FLD_HWD_8 = 9867; // 1 +static const uint64_t SH_FLD_HWD_8_LEN = 9868; // 1 +static const uint64_t SH_FLD_HWD_9 = 9869; // 1 +static const uint64_t SH_FLD_HWD_9_LEN = 9870; // 1 +static const uint64_t SH_FLD_HWD_LEN = 9871; // 1 +static const uint64_t SH_FLD_HWD_PRIORITY = 9872; // 1 +static const uint64_t SH_FLD_HWD_PRIORITY_LEN = 9873; // 1 +static const uint64_t SH_FLD_HWD_RSD = 9874; // 1 +static const uint64_t SH_FLD_HWD_RSD_LEN = 9875; // 1 +static const uint64_t SH_FLD_HWMSX_PE = 9876; // 8 +static const uint64_t SH_FLD_HWMSX_PE_LEN = 9877; // 8 +static const uint64_t SH_FLD_HW_CONTROL_ERROR = 9878; // 12 +static const uint64_t SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 9879; // 12 +static const uint64_t SH_FLD_HW_PARITY_ERROR = 9880; // 2 +static const uint64_t SH_FLD_HYPERVISOR = 9881; // 4 +static const uint64_t SH_FLD_HYP_BLOCK = 9882; // 24 +static const uint64_t SH_FLD_HYP_BLOCK_LEN = 9883; // 24 +static const uint64_t SH_FLD_HYP_INTR_PRESENT = 9884; // 24 +static const uint64_t SH_FLD_HYP_INTR_PRESENT_LEN = 9885; // 24 +static const uint64_t SH_FLD_HYP_INTR_REQUESTED = 9886; // 24 +static const uint64_t SH_FLD_HYP_INTR_REQUESTED_LEN = 9887; // 24 +static const uint64_t SH_FLD_HYP_RECOURCE_ERR = 9888; // 96 +static const uint64_t SH_FLD_HYP_SPECIAL_WKUP = 9889; // 30 +static const uint64_t SH_FLD_HYP_VIRT_EXIT_ENABLE = 9890; // 96 +static const uint64_t SH_FLD_I2CM_ECC_ERRORS = 9891; // 1 +static const uint64_t SH_FLD_I2CM_ECC_ERRORS_LEN = 9892; // 1 +static const uint64_t SH_FLD_I2CM_I2C_ERRORS = 9893; // 1 +static const uint64_t SH_FLD_I2CM_I2C_ERRORS_LEN = 9894; // 1 +static const uint64_t SH_FLD_I2CM_INTER = 9895; // 1 +static const uint64_t SH_FLD_I2CM_INTR_STATUS = 9896; // 1 +static const uint64_t SH_FLD_I2CM_INTR_STATUS_LEN = 9897; // 1 +static const uint64_t SH_FLD_I2CM_PIB_ERRORS = 9898; // 1 +static const uint64_t SH_FLD_I2CM_PIB_ERRORS_LEN = 9899; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0 = 9900; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN = 9901; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1 = 9902; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN = 9903; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2 = 9904; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN = 9905; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3 = 9906; // 1 +static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN = 9907; // 1 +static const uint64_t SH_FLD_I2CM_TPM_DECONFIG_PROTECT = 9908; // 1 +static const uint64_t SH_FLD_I2C_BUS_HELD_MODE_ENABLE = 9909; // 1 +static const uint64_t SH_FLD_I2C_C_INTERRUPT_HIGH = 9910; // 1 +static const uint64_t SH_FLD_I2C_D_INTERRUPT_HIGH = 9911; // 1 +static const uint64_t SH_FLD_I2C_E_INTERRUPT_HIGH = 9912; // 1 +static const uint64_t SH_FLD_I2C_SPEED_MUX = 9913; // 1 +static const uint64_t SH_FLD_I2C_SPEED_MUX_LEN = 9914; // 1 +static const uint64_t SH_FLD_I2C_TIMEOUT_VALUE = 9915; // 1 +static const uint64_t SH_FLD_I2C_TIMEOUT_VALUE_LEN = 9916; // 1 +static const uint64_t SH_FLD_IAR = 9917; // 25 +static const uint64_t SH_FLD_IAR_LEN = 9918; // 25 +static const uint64_t SH_FLD_IBUF_ABANK = 9919; // 3 +static const uint64_t SH_FLD_IBUF_ABANK_LEN = 9920; // 3 +static const uint64_t SH_FLD_IBUF_AIDX = 9921; // 3 +static const uint64_t SH_FLD_IBUF_AIDX_LEN = 9922; // 3 +static const uint64_t SH_FLD_IBUF_RSRC = 9923; // 3 +static const uint64_t SH_FLD_IBUF_RSRC_LEN = 9924; // 3 +static const uint64_t SH_FLD_IBUF_WSRC = 9925; // 3 +static const uint64_t SH_FLD_IBUF_WSRC_LEN = 9926; // 3 +static const uint64_t SH_FLD_IBWR_MASK = 9927; // 3 +static const uint64_t SH_FLD_IBWR_MASK_LEN = 9928; // 3 +static const uint64_t SH_FLD_ICACHE_ERR = 9929; // 21 +static const uint64_t SH_FLD_ICACHE_LINE2_ERR = 9930; // 21 +static const uint64_t SH_FLD_ICACHE_LINE2_VALID = 9931; // 21 +static const uint64_t SH_FLD_ICACHE_LINE2_VALID_LEN = 9932; // 21 +static const uint64_t SH_FLD_ICACHE_LINE_PTR = 9933; // 21 +static const uint64_t SH_FLD_ICACHE_PARITY_ERROR_INJECT = 9934; // 24 +static const uint64_t SH_FLD_ICACHE_PREFETCH_PENDING = 9935; // 21 +static const uint64_t SH_FLD_ICACHE_TAG_ADDR = 9936; // 21 +static const uint64_t SH_FLD_ICACHE_TAG_ADDR_LEN = 9937; // 21 +static const uint64_t SH_FLD_ICACHE_VALID = 9938; // 21 +static const uint64_t SH_FLD_ICACHE_VALID_LEN = 9939; // 21 +static const uint64_t SH_FLD_ICE_COUNT = 9940; // 2 +static const uint64_t SH_FLD_ICE_COUNT_LEN = 9941; // 2 +static const uint64_t SH_FLD_ICE_ETE_ATTN = 9942; // 2 +static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_IN = 9943; // 12 +static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN = 9944; // 12 +static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_OUT = 9945; // 12 +static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN = 9946; // 12 +static const uint64_t SH_FLD_ICS_INVALID_STATE = 9947; // 1 +static const uint64_t SH_FLD_ICU_RNW = 9948; // 1 +static const uint64_t SH_FLD_ICU_TIMEOUT_ERROR = 9949; // 1 +static const uint64_t SH_FLD_IC_RLD_QUAL = 9950; // 96 +static const uint64_t SH_FLD_IC_TAP = 9951; // 24 +static const uint64_t SH_FLD_IC_TAP_LEN = 9952; // 24 +static const uint64_t SH_FLD_ID = 9953; // 131 +static const uint64_t SH_FLD_IDIAL = 9954; // 35 +static const uint64_t SH_FLD_IDIAL_AMO_ADDR = 9955; // 3 +static const uint64_t SH_FLD_IDIAL_ATS = 9956; // 1 +static const uint64_t SH_FLD_IDIAL_ATS_ESR_MSK = 9957; // 1 +static const uint64_t SH_FLD_IDIAL_ATS_ESR_MSK_LEN = 9958; // 1 +static const uint64_t SH_FLD_IDIAL_ATS_FER_MSK = 9959; // 1 +static const uint64_t SH_FLD_IDIAL_ATS_FER_MSK_LEN = 9960; // 1 +static const uint64_t SH_FLD_IDIAL_ATS_LEN = 9961; // 1 +static const uint64_t SH_FLD_IDIAL_BBRD = 9962; // 3 +static const uint64_t SH_FLD_IDIAL_BBRD_LEN = 9963; // 3 +static const uint64_t SH_FLD_IDIAL_BBUF_RDWR = 9964; // 3 +static const uint64_t SH_FLD_IDIAL_BR_CE = 9965; // 3 +static const uint64_t SH_FLD_IDIAL_BR_CE_LEN = 9966; // 3 +static const uint64_t SH_FLD_IDIAL_BR_SUE = 9967; // 3 +static const uint64_t SH_FLD_IDIAL_BR_SUE_LEN = 9968; // 3 +static const uint64_t SH_FLD_IDIAL_BR_UE = 9969; // 3 +static const uint64_t SH_FLD_IDIAL_BR_UE_LEN = 9970; // 3 +static const uint64_t SH_FLD_IDIAL_CNTL_ERRP = 9971; // 1 +static const uint64_t SH_FLD_IDIAL_CONFIG1 = 9972; // 3 +static const uint64_t SH_FLD_IDIAL_COUNT0 = 9973; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT0_LEN = 9974; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT1 = 9975; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT1_LEN = 9976; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT2 = 9977; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT2_LEN = 9978; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT3 = 9979; // 9 +static const uint64_t SH_FLD_IDIAL_COUNT3_LEN = 9980; // 9 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_0 = 9981; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_1 = 9982; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_2 = 9983; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_3 = 9984; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_4 = 9985; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_5 = 9986; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_6 = 9987; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_7 = 9988; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_0 = 9989; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_1 = 9990; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_2 = 9991; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_3 = 9992; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_4 = 9993; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_5 = 9994; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_6 = 9995; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_7 = 9996; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_0 = 9997; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_1 = 9998; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_2 = 9999; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_3 = 10000; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_0 = 10001; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_1 = 10002; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_2 = 10003; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_3 = 10004; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_4 = 10005; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_5 = 10006; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_6 = 10007; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_7 = 10008; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_0 = 10009; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_1 = 10010; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_2 = 10011; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_3 = 10012; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_4 = 10013; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_5 = 10014; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_6 = 10015; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_7 = 10016; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_0 = 10017; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_1 = 10018; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_10 = 10019; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_11 = 10020; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_12 = 10021; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_13 = 10022; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_14 = 10023; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_15 = 10024; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_2 = 10025; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_3 = 10026; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_4 = 10027; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_5 = 10028; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_6 = 10029; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_7 = 10030; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_8 = 10031; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_9 = 10032; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_0 = 10033; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_1 = 10034; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_10 = 10035; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_11 = 10036; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_12 = 10037; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_13 = 10038; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_14 = 10039; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_15 = 10040; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_16 = 10041; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_17 = 10042; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_18 = 10043; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_19 = 10044; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_2 = 10045; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_20 = 10046; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_21 = 10047; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_22 = 10048; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_23 = 10049; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_3 = 10050; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_4 = 10051; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_5 = 10052; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_6 = 10053; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_7 = 10054; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_8 = 10055; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_9 = 10056; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_0 = 10057; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_1 = 10058; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_2 = 10059; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_3 = 10060; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_4 = 10061; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_5 = 10062; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_6 = 10063; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_7 = 10064; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_0 = 10065; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_1 = 10066; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_2 = 10067; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_3 = 10068; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_4 = 10069; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_5 = 10070; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_6 = 10071; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_7 = 10072; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_0 = 10073; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_1 = 10074; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_2 = 10075; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_3 = 10076; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_4 = 10077; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_5 = 10078; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_6 = 10079; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_7 = 10080; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_0 = 10081; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_1 = 10082; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_2 = 10083; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_3 = 10084; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_4 = 10085; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_5 = 10086; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_6 = 10087; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_7 = 10088; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_0 = 10089; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_1 = 10090; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_2 = 10091; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_3 = 10092; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_0 = 10093; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_1 = 10094; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_2 = 10095; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_3 = 10096; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_0 = 10097; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_1 = 10098; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_2 = 10099; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_3 = 10100; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_0 = 10101; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_1 = 10102; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_2 = 10103; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_3 = 10104; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_0 = 10105; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_1 = 10106; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_2 = 10107; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_3 = 10108; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_0 = 10109; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_1 = 10110; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_2 = 10111; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_3 = 10112; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_4 = 10113; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_5 = 10114; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_6 = 10115; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_7 = 10116; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_0 = 10117; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_1 = 10118; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_2 = 10119; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_3 = 10120; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_4 = 10121; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_5 = 10122; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_6 = 10123; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_7 = 10124; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_0 = 10125; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_1 = 10126; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_2 = 10127; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_3 = 10128; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_0 = 10129; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_1 = 10130; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_2 = 10131; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_3 = 10132; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_4 = 10133; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_5 = 10134; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_6 = 10135; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_7 = 10136; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_0 = 10137; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_1 = 10138; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_2 = 10139; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_3 = 10140; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_4 = 10141; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_5 = 10142; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_6 = 10143; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_7 = 10144; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_0 = 10145; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_1 = 10146; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_10 = 10147; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_11 = 10148; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_12 = 10149; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_13 = 10150; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_14 = 10151; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_15 = 10152; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_2 = 10153; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_3 = 10154; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_4 = 10155; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_5 = 10156; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_6 = 10157; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_7 = 10158; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_8 = 10159; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_9 = 10160; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_0 = 10161; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_1 = 10162; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_10 = 10163; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_11 = 10164; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_12 = 10165; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_13 = 10166; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_14 = 10167; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_15 = 10168; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_16 = 10169; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_17 = 10170; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_18 = 10171; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_19 = 10172; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_2 = 10173; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_20 = 10174; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_21 = 10175; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_22 = 10176; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_23 = 10177; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_3 = 10178; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_4 = 10179; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_5 = 10180; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_6 = 10181; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_7 = 10182; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_8 = 10183; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_9 = 10184; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_0 = 10185; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_1 = 10186; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_2 = 10187; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_3 = 10188; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_4 = 10189; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_5 = 10190; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_6 = 10191; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_7 = 10192; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_0 = 10193; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_1 = 10194; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_2 = 10195; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_3 = 10196; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_4 = 10197; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_5 = 10198; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_6 = 10199; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_7 = 10200; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_0 = 10201; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_1 = 10202; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_2 = 10203; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_3 = 10204; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_4 = 10205; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_5 = 10206; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_6 = 10207; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_7 = 10208; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_0 = 10209; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_1 = 10210; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_2 = 10211; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_3 = 10212; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_4 = 10213; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_5 = 10214; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_6 = 10215; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_7 = 10216; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_0 = 10217; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_1 = 10218; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_2 = 10219; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_3 = 10220; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_0 = 10221; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_1 = 10222; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_2 = 10223; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_3 = 10224; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_0 = 10225; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_1 = 10226; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_2 = 10227; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_3 = 10228; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_0 = 10229; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_1 = 10230; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_2 = 10231; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_3 = 10232; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_0 = 10233; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_1 = 10234; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_2 = 10235; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_3 = 10236; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_0 = 10237; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_1 = 10238; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_2 = 10239; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_3 = 10240; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_4 = 10241; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_5 = 10242; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_6 = 10243; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_7 = 10244; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_0 = 10245; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_1 = 10246; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_2 = 10247; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_3 = 10248; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_4 = 10249; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_5 = 10250; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_6 = 10251; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_7 = 10252; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_0 = 10253; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_1 = 10254; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_2 = 10255; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_3 = 10256; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_0 = 10257; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_1 = 10258; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_2 = 10259; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_3 = 10260; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_4 = 10261; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_5 = 10262; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_6 = 10263; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_7 = 10264; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_0 = 10265; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_1 = 10266; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_2 = 10267; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_3 = 10268; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_4 = 10269; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_5 = 10270; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_6 = 10271; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_7 = 10272; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_0 = 10273; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_1 = 10274; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_10 = 10275; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_11 = 10276; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_12 = 10277; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_13 = 10278; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_14 = 10279; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_15 = 10280; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_2 = 10281; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_3 = 10282; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_4 = 10283; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_5 = 10284; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_6 = 10285; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_7 = 10286; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_8 = 10287; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_9 = 10288; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_0 = 10289; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_1 = 10290; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_10 = 10291; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_11 = 10292; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_12 = 10293; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_13 = 10294; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_14 = 10295; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_15 = 10296; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_16 = 10297; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_17 = 10298; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_18 = 10299; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_19 = 10300; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_2 = 10301; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_20 = 10302; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_21 = 10303; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_22 = 10304; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_23 = 10305; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_3 = 10306; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_4 = 10307; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_5 = 10308; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_6 = 10309; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_7 = 10310; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_8 = 10311; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_9 = 10312; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_0 = 10313; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_1 = 10314; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_2 = 10315; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_3 = 10316; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_4 = 10317; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_5 = 10318; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_6 = 10319; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_7 = 10320; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_0 = 10321; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_1 = 10322; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_2 = 10323; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_3 = 10324; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_4 = 10325; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_5 = 10326; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_6 = 10327; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_7 = 10328; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_0 = 10329; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_1 = 10330; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_2 = 10331; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_3 = 10332; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_4 = 10333; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_5 = 10334; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_6 = 10335; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_7 = 10336; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_0 = 10337; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_1 = 10338; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_2 = 10339; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_3 = 10340; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_4 = 10341; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_5 = 10342; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_6 = 10343; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_7 = 10344; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_0 = 10345; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_1 = 10346; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_2 = 10347; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_3 = 10348; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_0 = 10349; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_1 = 10350; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_2 = 10351; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_3 = 10352; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_0 = 10353; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_1 = 10354; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_2 = 10355; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_3 = 10356; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_0 = 10357; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_1 = 10358; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_2 = 10359; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_3 = 10360; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_0 = 10361; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_1 = 10362; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_2 = 10363; // 3 +static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_3 = 10364; // 3 +static const uint64_t SH_FLD_IDIAL_DEBUG0_CONFIG = 10365; // 3 +static const uint64_t SH_FLD_IDIAL_DEBUG1_CONFIG = 10366; // 3 +static const uint64_t SH_FLD_IDIAL_EA = 10367; // 2 +static const uint64_t SH_FLD_IDIAL_EA_LEN = 10368; // 2 +static const uint64_t SH_FLD_IDIAL_ECC_CONFIG = 10369; // 3 +static const uint64_t SH_FLD_IDIAL_ERRINJ = 10370; // 3 +static const uint64_t SH_FLD_IDIAL_IBAR_ERRP = 10371; // 1 +static const uint64_t SH_FLD_IDIAL_IBRD = 10372; // 3 +static const uint64_t SH_FLD_IDIAL_IBRD_LEN = 10373; // 3 +static const uint64_t SH_FLD_IDIAL_IBUF_CTL_PIPE = 10374; // 3 +static const uint64_t SH_FLD_IDIAL_IBUF_RDWR = 10375; // 3 +static const uint64_t SH_FLD_IDIAL_IBUF_STATE = 10376; // 3 +static const uint64_t SH_FLD_IDIAL_IBUF_WARB = 10377; // 3 +static const uint64_t SH_FLD_IDIAL_IBUF_WRITE = 10378; // 3 +static const uint64_t SH_FLD_IDIAL_INHIBIT_CONFIG = 10379; // 3 +static const uint64_t SH_FLD_IDIAL_IR_CE = 10380; // 3 +static const uint64_t SH_FLD_IDIAL_IR_CE_LEN = 10381; // 3 +static const uint64_t SH_FLD_IDIAL_IR_SUE = 10382; // 3 +static const uint64_t SH_FLD_IDIAL_IR_SUE_LEN = 10383; // 3 +static const uint64_t SH_FLD_IDIAL_IR_UE = 10384; // 3 +static const uint64_t SH_FLD_IDIAL_IR_UE_LEN = 10385; // 3 +static const uint64_t SH_FLD_IDIAL_ISSYNC = 10386; // 1 +static const uint64_t SH_FLD_IDIAL_ISSYNC_LEN = 10387; // 1 +static const uint64_t SH_FLD_IDIAL_LEN = 10388; // 35 +static const uint64_t SH_FLD_IDIAL_MISC_STATE = 10389; // 3 +static const uint64_t SH_FLD_IDIAL_MM_LOCAL_XSTOP = 10390; // 1 +static const uint64_t SH_FLD_IDIAL_MRG_IR_PIPE = 10391; // 3 +static const uint64_t SH_FLD_IDIAL_MRG_OR_PIPE = 10392; // 3 +static const uint64_t SH_FLD_IDIAL_MRG_STATE = 10393; // 3 +static const uint64_t SH_FLD_IDIAL_NDL0_NOSTALL = 10394; // 1 +static const uint64_t SH_FLD_IDIAL_NDL0_STALL = 10395; // 1 +static const uint64_t SH_FLD_IDIAL_NDL1_NOSTALL = 10396; // 1 +static const uint64_t SH_FLD_IDIAL_NDL1_STALL = 10397; // 1 +static const uint64_t SH_FLD_IDIAL_NDL2_NOSTALL = 10398; // 1 +static const uint64_t SH_FLD_IDIAL_NDL2_STALL = 10399; // 1 +static const uint64_t SH_FLD_IDIAL_NDL3_NOSTALL = 10400; // 1 +static const uint64_t SH_FLD_IDIAL_NDL3_STALL = 10401; // 1 +static const uint64_t SH_FLD_IDIAL_NDL4_NOSTALL = 10402; // 1 +static const uint64_t SH_FLD_IDIAL_NDL4_STALL = 10403; // 1 +static const uint64_t SH_FLD_IDIAL_NDL5_NOSTALL = 10404; // 1 +static const uint64_t SH_FLD_IDIAL_NDL5_STALL = 10405; // 1 +static const uint64_t SH_FLD_IDIAL_OBRD = 10406; // 3 +static const uint64_t SH_FLD_IDIAL_OBRD_LEN = 10407; // 3 +static const uint64_t SH_FLD_IDIAL_OBUF_RDWR = 10408; // 3 +static const uint64_t SH_FLD_IDIAL_OBUF_STATE = 10409; // 3 +static const uint64_t SH_FLD_IDIAL_OR_CE = 10410; // 3 +static const uint64_t SH_FLD_IDIAL_OR_CE_LEN = 10411; // 3 +static const uint64_t SH_FLD_IDIAL_OR_SUE = 10412; // 3 +static const uint64_t SH_FLD_IDIAL_OR_SUE_LEN = 10413; // 3 +static const uint64_t SH_FLD_IDIAL_OR_UE = 10414; // 3 +static const uint64_t SH_FLD_IDIAL_OR_UE_LEN = 10415; // 3 +static const uint64_t SH_FLD_IDIAL_PAR = 10416; // 1 +static const uint64_t SH_FLD_IDIAL_PAR_LEN = 10417; // 1 +static const uint64_t SH_FLD_IDIAL_PBRX_RTAG = 10418; // 6 +static const uint64_t SH_FLD_IDIAL_PBTX_AMO = 10419; // 3 +static const uint64_t SH_FLD_IDIAL_PBTX_AMO_LEN = 10420; // 3 +static const uint64_t SH_FLD_IDIAL_PBTX_PIPE = 10421; // 3 +static const uint64_t SH_FLD_IDIAL_PBTX_STATE = 10422; // 3 +static const uint64_t SH_FLD_IDIAL_PC = 10423; // 2 +static const uint64_t SH_FLD_IDIAL_PC_LEN = 10424; // 2 +static const uint64_t SH_FLD_IDIAL_PE = 10425; // 2 +static const uint64_t SH_FLD_IDIAL_PE_LEN = 10426; // 2 +static const uint64_t SH_FLD_IDIAL_PR_CE = 10427; // 3 +static const uint64_t SH_FLD_IDIAL_PR_CE_LEN = 10428; // 3 +static const uint64_t SH_FLD_IDIAL_PR_SUE = 10429; // 3 +static const uint64_t SH_FLD_IDIAL_PR_SUE_LEN = 10430; // 3 +static const uint64_t SH_FLD_IDIAL_PR_UE = 10431; // 3 +static const uint64_t SH_FLD_IDIAL_PR_UE_LEN = 10432; // 3 +static const uint64_t SH_FLD_IDIAL_PT_CE = 10433; // 3 +static const uint64_t SH_FLD_IDIAL_PT_CE_LEN = 10434; // 3 +static const uint64_t SH_FLD_IDIAL_PT_SUE = 10435; // 3 +static const uint64_t SH_FLD_IDIAL_PT_SUE_LEN = 10436; // 3 +static const uint64_t SH_FLD_IDIAL_PT_UE = 10437; // 3 +static const uint64_t SH_FLD_IDIAL_PT_UE_LEN = 10438; // 3 +static const uint64_t SH_FLD_IDIAL_RA = 10439; // 2 +static const uint64_t SH_FLD_IDIAL_RA_LEN = 10440; // 2 +static const uint64_t SH_FLD_IDIAL_RING_ERRP = 10441; // 1 +static const uint64_t SH_FLD_IDIAL_RNW = 10442; // 1 +static const uint64_t SH_FLD_IDIAL_RQIN_OVF = 10443; // 3 +static const uint64_t SH_FLD_IDIAL_RQIN_OVF_LEN = 10444; // 3 +static const uint64_t SH_FLD_IDIAL_RQIN_STATE = 10445; // 3 +static const uint64_t SH_FLD_IDIAL_RSVD0 = 10446; // 4 +static const uint64_t SH_FLD_IDIAL_RSVD0_LEN = 10447; // 4 +static const uint64_t SH_FLD_IDIAL_RSVD1 = 10448; // 2 +static const uint64_t SH_FLD_IDIAL_RSVD1_LEN = 10449; // 2 +static const uint64_t SH_FLD_IDIAL_SCOMDAA_ERRP = 10450; // 1 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_0 = 10451; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_1 = 10452; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_2 = 10453; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_3 = 10454; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_0 = 10455; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_1 = 10456; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_2 = 10457; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_3 = 10458; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_0 = 10459; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_1 = 10460; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_2 = 10461; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_3 = 10462; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_0 = 10463; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_1 = 10464; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_2 = 10465; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_3 = 10466; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_4 = 10467; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_5 = 10468; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_6 = 10469; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_7 = 10470; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_0 = 10471; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_1 = 10472; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_10 = 10473; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_11 = 10474; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_12 = 10475; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_13 = 10476; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_14 = 10477; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_15 = 10478; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_2 = 10479; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_3 = 10480; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_4 = 10481; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_5 = 10482; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_6 = 10483; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_7 = 10484; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_8 = 10485; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_9 = 10486; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_0 = 10487; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_1 = 10488; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_10 = 10489; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_11 = 10490; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_12 = 10491; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_13 = 10492; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_14 = 10493; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_15 = 10494; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_16 = 10495; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_17 = 10496; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_18 = 10497; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_19 = 10498; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_2 = 10499; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_20 = 10500; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_21 = 10501; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_22 = 10502; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_23 = 10503; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_24 = 10504; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_25 = 10505; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_26 = 10506; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_27 = 10507; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_28 = 10508; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_29 = 10509; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_3 = 10510; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_30 = 10511; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_31 = 10512; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_32 = 10513; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_33 = 10514; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_34 = 10515; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_35 = 10516; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_36 = 10517; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_37 = 10518; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_38 = 10519; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_39 = 10520; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_4 = 10521; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_40 = 10522; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_41 = 10523; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_42 = 10524; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_43 = 10525; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_44 = 10526; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_45 = 10527; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_46 = 10528; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_47 = 10529; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_48 = 10530; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_49 = 10531; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_5 = 10532; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_50 = 10533; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_51 = 10534; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_52 = 10535; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_53 = 10536; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_54 = 10537; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_55 = 10538; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_56 = 10539; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_57 = 10540; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_58 = 10541; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_59 = 10542; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_6 = 10543; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_60 = 10544; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_61 = 10545; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_62 = 10546; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_63 = 10547; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_7 = 10548; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_8 = 10549; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_9 = 10550; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_0 = 10551; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_1 = 10552; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_10 = 10553; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_11 = 10554; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_12 = 10555; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_13 = 10556; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_14 = 10557; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_15 = 10558; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_16 = 10559; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_17 = 10560; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_18 = 10561; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_19 = 10562; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_2 = 10563; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_20 = 10564; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_21 = 10565; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_22 = 10566; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_23 = 10567; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_24 = 10568; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_25 = 10569; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_26 = 10570; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_27 = 10571; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_28 = 10572; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_29 = 10573; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_3 = 10574; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_30 = 10575; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_31 = 10576; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_4 = 10577; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_5 = 10578; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_6 = 10579; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_7 = 10580; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_8 = 10581; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_9 = 10582; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_0 = 10583; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_1 = 10584; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_10 = 10585; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_11 = 10586; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_2 = 10587; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_3 = 10588; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_4 = 10589; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_5 = 10590; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_6 = 10591; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_7 = 10592; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_8 = 10593; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_9 = 10594; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_0 = 10595; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_1 = 10596; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_10 = 10597; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_11 = 10598; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_2 = 10599; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_3 = 10600; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_4 = 10601; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_5 = 10602; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_6 = 10603; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_7 = 10604; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_8 = 10605; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_9 = 10606; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_0 = 10607; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_1 = 10608; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_2 = 10609; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_3 = 10610; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_4 = 10611; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_5 = 10612; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_6 = 10613; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_7 = 10614; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_0 = 10615; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_1 = 10616; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_2 = 10617; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_3 = 10618; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_4 = 10619; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_5 = 10620; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_6 = 10621; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_7 = 10622; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_0 = 10623; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_1 = 10624; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_2 = 10625; // 12 +static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_3 = 10626; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_0 = 10627; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_1 = 10628; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_2 = 10629; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_3 = 10630; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_0 = 10631; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_1 = 10632; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_2 = 10633; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_3 = 10634; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_0 = 10635; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_1 = 10636; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_2 = 10637; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_3 = 10638; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_0 = 10639; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_1 = 10640; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_2 = 10641; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_3 = 10642; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_4 = 10643; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_5 = 10644; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_6 = 10645; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_7 = 10646; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_0 = 10647; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_1 = 10648; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_10 = 10649; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_11 = 10650; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_12 = 10651; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_13 = 10652; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_14 = 10653; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_15 = 10654; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_2 = 10655; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_3 = 10656; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_4 = 10657; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_5 = 10658; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_6 = 10659; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_7 = 10660; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_8 = 10661; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_9 = 10662; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_0 = 10663; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_1 = 10664; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_10 = 10665; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_11 = 10666; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_12 = 10667; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_13 = 10668; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_14 = 10669; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_15 = 10670; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_16 = 10671; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_17 = 10672; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_18 = 10673; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_19 = 10674; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_2 = 10675; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_20 = 10676; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_21 = 10677; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_22 = 10678; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_23 = 10679; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_24 = 10680; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_25 = 10681; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_26 = 10682; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_27 = 10683; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_28 = 10684; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_29 = 10685; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_3 = 10686; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_30 = 10687; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_31 = 10688; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_32 = 10689; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_33 = 10690; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_34 = 10691; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_35 = 10692; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_36 = 10693; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_37 = 10694; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_38 = 10695; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_39 = 10696; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_4 = 10697; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_40 = 10698; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_41 = 10699; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_42 = 10700; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_43 = 10701; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_44 = 10702; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_45 = 10703; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_46 = 10704; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_47 = 10705; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_48 = 10706; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_49 = 10707; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_5 = 10708; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_50 = 10709; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_51 = 10710; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_52 = 10711; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_53 = 10712; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_54 = 10713; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_55 = 10714; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_56 = 10715; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_57 = 10716; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_58 = 10717; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_59 = 10718; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_6 = 10719; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_60 = 10720; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_61 = 10721; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_62 = 10722; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_63 = 10723; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_7 = 10724; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_8 = 10725; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_9 = 10726; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_0 = 10727; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_1 = 10728; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_10 = 10729; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_11 = 10730; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_12 = 10731; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_13 = 10732; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_14 = 10733; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_15 = 10734; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_16 = 10735; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_17 = 10736; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_18 = 10737; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_19 = 10738; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_2 = 10739; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_20 = 10740; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_21 = 10741; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_22 = 10742; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_23 = 10743; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_24 = 10744; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_25 = 10745; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_26 = 10746; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_27 = 10747; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_28 = 10748; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_29 = 10749; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_3 = 10750; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_30 = 10751; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_31 = 10752; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_4 = 10753; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_5 = 10754; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_6 = 10755; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_7 = 10756; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_8 = 10757; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_9 = 10758; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_0 = 10759; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_1 = 10760; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_10 = 10761; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_11 = 10762; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_2 = 10763; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_3 = 10764; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_4 = 10765; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_5 = 10766; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_6 = 10767; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_7 = 10768; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_8 = 10769; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_9 = 10770; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_0 = 10771; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_1 = 10772; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_10 = 10773; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_11 = 10774; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_2 = 10775; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_3 = 10776; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_4 = 10777; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_5 = 10778; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_6 = 10779; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_7 = 10780; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_8 = 10781; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_9 = 10782; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_0 = 10783; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_1 = 10784; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_2 = 10785; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_3 = 10786; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_4 = 10787; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_5 = 10788; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_6 = 10789; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_7 = 10790; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_0 = 10791; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_1 = 10792; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_2 = 10793; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_3 = 10794; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_4 = 10795; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_5 = 10796; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_6 = 10797; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_7 = 10798; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_0 = 10799; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_1 = 10800; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_2 = 10801; // 12 +static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_3 = 10802; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_0 = 10803; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_1 = 10804; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_2 = 10805; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_3 = 10806; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_0 = 10807; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_1 = 10808; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_2 = 10809; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_3 = 10810; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_0 = 10811; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_1 = 10812; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_2 = 10813; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_3 = 10814; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_0 = 10815; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_1 = 10816; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_2 = 10817; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_3 = 10818; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_4 = 10819; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_5 = 10820; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_6 = 10821; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_7 = 10822; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_0 = 10823; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_1 = 10824; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_10 = 10825; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_11 = 10826; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_12 = 10827; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_13 = 10828; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_14 = 10829; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_15 = 10830; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_2 = 10831; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_3 = 10832; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_4 = 10833; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_5 = 10834; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_6 = 10835; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_7 = 10836; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_8 = 10837; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_9 = 10838; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_0 = 10839; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_1 = 10840; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_10 = 10841; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_11 = 10842; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_12 = 10843; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_13 = 10844; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_14 = 10845; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_15 = 10846; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_16 = 10847; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_17 = 10848; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_18 = 10849; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_19 = 10850; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_2 = 10851; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_20 = 10852; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_21 = 10853; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_22 = 10854; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_23 = 10855; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_24 = 10856; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_25 = 10857; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_26 = 10858; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_27 = 10859; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_28 = 10860; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_29 = 10861; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_3 = 10862; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_30 = 10863; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_31 = 10864; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_32 = 10865; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_33 = 10866; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_34 = 10867; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_35 = 10868; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_36 = 10869; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_37 = 10870; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_38 = 10871; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_39 = 10872; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_4 = 10873; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_40 = 10874; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_41 = 10875; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_42 = 10876; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_43 = 10877; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_44 = 10878; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_45 = 10879; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_46 = 10880; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_47 = 10881; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_48 = 10882; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_49 = 10883; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_5 = 10884; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_50 = 10885; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_51 = 10886; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_52 = 10887; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_53 = 10888; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_54 = 10889; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_55 = 10890; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_56 = 10891; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_57 = 10892; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_58 = 10893; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_59 = 10894; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_6 = 10895; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_60 = 10896; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_61 = 10897; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_62 = 10898; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_63 = 10899; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_7 = 10900; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_8 = 10901; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_9 = 10902; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_0 = 10903; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_1 = 10904; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_10 = 10905; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_11 = 10906; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_12 = 10907; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_13 = 10908; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_14 = 10909; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_15 = 10910; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_16 = 10911; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_17 = 10912; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_18 = 10913; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_19 = 10914; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_2 = 10915; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_20 = 10916; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_21 = 10917; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_22 = 10918; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_23 = 10919; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_24 = 10920; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_25 = 10921; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_26 = 10922; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_27 = 10923; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_28 = 10924; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_29 = 10925; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_3 = 10926; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_30 = 10927; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_31 = 10928; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_4 = 10929; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_5 = 10930; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_6 = 10931; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_7 = 10932; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_8 = 10933; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_9 = 10934; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_0 = 10935; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_1 = 10936; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_10 = 10937; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_11 = 10938; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_2 = 10939; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_3 = 10940; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_4 = 10941; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_5 = 10942; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_6 = 10943; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_7 = 10944; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_8 = 10945; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_9 = 10946; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_0 = 10947; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_1 = 10948; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_10 = 10949; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_11 = 10950; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_2 = 10951; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_3 = 10952; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_4 = 10953; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_5 = 10954; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_6 = 10955; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_7 = 10956; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_8 = 10957; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_9 = 10958; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_0 = 10959; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_1 = 10960; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_2 = 10961; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_3 = 10962; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_4 = 10963; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_5 = 10964; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_6 = 10965; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_7 = 10966; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_0 = 10967; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_1 = 10968; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_2 = 10969; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_3 = 10970; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_4 = 10971; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_5 = 10972; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_6 = 10973; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_7 = 10974; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_0 = 10975; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_1 = 10976; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_2 = 10977; // 12 +static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_3 = 10978; // 12 +static const uint64_t SH_FLD_IDIAL_TAG = 10979; // 1 +static const uint64_t SH_FLD_IDIAL_TAG_LEN = 10980; // 1 +static const uint64_t SH_FLD_IDIAL_VLD = 10981; // 1 +static const uint64_t SH_FLD_IDIR_ERROR_INJECT = 10982; // 24 +static const uint64_t SH_FLD_IDLE = 10983; // 2 +static const uint64_t SH_FLD_IDLES = 10984; // 64 +static const uint64_t SH_FLD_IDLES_LEN = 10985; // 64 +static const uint64_t SH_FLD_IDLE_DELAY = 10986; // 96 +static const uint64_t SH_FLD_IDLE_DELAY_LEN = 10987; // 96 +static const uint64_t SH_FLD_IDLE_INDICATION = 10988; // 1 +static const uint64_t SH_FLD_IDLE_PAT_ACTN = 10989; // 2 +static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13 = 10990; // 2 +static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN = 10991; // 2 +static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_14 = 10992; // 2 +static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_15 = 10993; // 2 +static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_16 = 10994; // 2 +static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_17 = 10995; // 2 +static const uint64_t SH_FLD_IDLE_PAT_BANK_0_1 = 10996; // 2 +static const uint64_t SH_FLD_IDLE_PAT_BANK_0_1_LEN = 10997; // 2 +static const uint64_t SH_FLD_IDLE_PAT_BANK_2 = 10998; // 2 +static const uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_0 = 10999; // 2 +static const uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_1 = 11000; // 2 +static const uint64_t SH_FLD_IDLE_PAT_PARITY = 11001; // 2 +static const uint64_t SH_FLD_IDR_LCL_SAMPLE_EN = 11002; // 12 +static const uint64_t SH_FLD_ID_DIRTY = 11003; // 2 +static const uint64_t SH_FLD_ID_LEN = 11004; // 129 +static const uint64_t SH_FLD_IERAT_EA_INJECT = 11005; // 24 +static const uint64_t SH_FLD_IERAT_RA_INJECT = 11006; // 24 +static const uint64_t SH_FLD_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 = 11007; // 24 +static const uint64_t SH_FLD_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 = 11008; // 24 +static const uint64_t SH_FLD_IFBBC_BREX_PRED_CHECKER_HOLD_OUT = 11009; // 24 +static const uint64_t SH_FLD_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT = 11010; // 24 +static const uint64_t SH_FLD_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 = 11011; // 24 +static const uint64_t SH_FLD_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 = 11012; // 24 +static const uint64_t SH_FLD_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 = 11013; // 24 +static const uint64_t SH_FLD_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 = 11014; // 24 +static const uint64_t SH_FLD_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 = 11015; // 24 +static const uint64_t SH_FLD_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 = 11016; // 24 +static const uint64_t SH_FLD_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT = 11017; // 24 +static const uint64_t SH_FLD_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT = 11018; // 24 +static const uint64_t SH_FLD_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT = 11019; // 24 +static const uint64_t SH_FLD_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT = 11020; // 24 +static const uint64_t SH_FLD_IFC_REG_CERR0 = 11021; // 1 +static const uint64_t SH_FLD_IFC_REG_CERR1 = 11022; // 1 +static const uint64_t SH_FLD_IFC_REG_CERR2 = 11023; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR0 = 11024; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR1 = 11025; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR2 = 11026; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR3 = 11027; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR4 = 11028; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR5 = 11029; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR6 = 11030; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR7 = 11031; // 1 +static const uint64_t SH_FLD_IFC_REG_ERR8 = 11032; // 1 +static const uint64_t SH_FLD_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 = 11033; // 24 +static const uint64_t SH_FLD_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 = 11034; // 24 +static const uint64_t SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2 = 11035; // 24 +static const uint64_t SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 = 11036; // 24 +static const uint64_t SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 = 11037; // 24 +static const uint64_t SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 = 11038; // 24 +static const uint64_t SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 = 11039; // 24 +static const uint64_t SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 = 11040; // 24 +static const uint64_t SH_FLD_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 = 11041; // 24 +static const uint64_t SH_FLD_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT = 11042; // 24 +static const uint64_t SH_FLD_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT = 11043; // 24 +static const uint64_t SH_FLD_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT = 11044; // 24 +static const uint64_t SH_FLD_IFFAC_S0_NIA_P_HOLD_OUT = 11045; // 24 +static const uint64_t SH_FLD_IFFAC_S0_TAIL_P_HOLD_OUT = 11046; // 24 +static const uint64_t SH_FLD_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 = 11047; // 24 +static const uint64_t SH_FLD_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 = 11048; // 24 +static const uint64_t SH_FLD_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 = 11049; // 24 +static const uint64_t SH_FLD_IFFBC_IFAR_PARITY_HOLD_OUT_2 = 11050; // 24 +static const uint64_t SH_FLD_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 = 11051; // 24 +static const uint64_t SH_FLD_IFFBC_MULTI_THREAD_HOLD_OUT_2 = 11052; // 24 +static const uint64_t SH_FLD_IFFCP_CIABR_PERR_HOLD_OUT = 11053; // 24 +static const uint64_t SH_FLD_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT = 11054; // 24 +static const uint64_t SH_FLD_IFFEC_EADIR_ILLEGAL_HOLD_OUT = 11055; // 24 +static const uint64_t SH_FLD_IFFEC_ERAT_PTY_HOLD_OUT = 11056; // 24 +static const uint64_t SH_FLD_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT = 11057; // 24 +static const uint64_t SH_FLD_IFFEC_ICACHE_PE_HOLD_OUT = 11058; // 24 +static const uint64_t SH_FLD_IFFEC_IDIR_EA_PTY_HOLD_OUT = 11059; // 24 +static const uint64_t SH_FLD_IFFEC_IDIR_PTY_HOLD_OUT = 11060; // 24 +static const uint64_t SH_FLD_IFFEC_IERAT_WRT_EA_HOLD_OUT = 11061; // 24 +static const uint64_t SH_FLD_IFFEC_IFAR_CHECK1_HOLD_OUT = 11062; // 24 +static const uint64_t SH_FLD_IFFEC_IFAR_CHECK2_HOLD_OUT = 11063; // 24 +static const uint64_t SH_FLD_IFFEC_IFFIW_IDIR_HOLD_OUT = 11064; // 24 +static const uint64_t SH_FLD_IFFLC_WRITE_COLL_HOLD_OUT_2 = 11065; // 24 +static const uint64_t SH_FLD_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 = 11066; // 24 +static const uint64_t SH_FLD_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT = 11067; // 24 +static const uint64_t SH_FLD_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT = 11068; // 24 +static const uint64_t SH_FLD_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT = 11069; // 24 +static const uint64_t SH_FLD_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT = 11070; // 24 +static const uint64_t SH_FLD_IFFRC_REFETCH_EAT_P_HOLD_OUT = 11071; // 24 +static const uint64_t SH_FLD_IFFRC_REFETCH_SPR_P_HOLD_OUT = 11072; // 24 +static const uint64_t SH_FLD_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT = 11073; // 24 +static const uint64_t SH_FLD_IFFSE_SPR_PARITY_HOLD_OUT_2 = 11074; // 24 +static const uint64_t SH_FLD_IFREQ = 11075; // 1 +static const uint64_t SH_FLD_IF_LOG_REC_ERROR = 11076; // 24 +static const uint64_t SH_FLD_IF_LOG_XSTOP_ERROR = 11077; // 24 +static const uint64_t SH_FLD_IF_RFILE_REC_ERROR = 11078; // 24 +static const uint64_t SH_FLD_IF_RFILE_XSTOP_ERROR = 11079; // 24 +static const uint64_t SH_FLD_IF_SRAM_REC_ERROR = 11080; // 24 +static const uint64_t SH_FLD_IF_THROTTLE_ACTIVE = 11081; // 24 +static const uint64_t SH_FLD_IF_THROTTLE_ACTIVE_LEN = 11082; // 24 +static const uint64_t SH_FLD_IF_THROTTLE_BLK_FETCH = 11083; // 24 +static const uint64_t SH_FLD_IF_THROTTLE_BLK_FETCH_LEN = 11084; // 24 +static const uint64_t SH_FLD_ILE = 11085; // 96 +static const uint64_t SH_FLD_ILLEGAL_CACHE_OP = 11086; // 1 +static const uint64_t SH_FLD_ILLEGAL_CACHE_OP_MASK = 11087; // 1 +static const uint64_t SH_FLD_ILLEGAL_LPC_BAR_ACCESS = 11088; // 4 +static const uint64_t SH_FLD_ILL_CRESP = 11089; // 1 +static const uint64_t SH_FLD_IMA_ACK_DEAD = 11090; // 12 +static const uint64_t SH_FLD_IMA_CRESP_ADDR_ERR = 11091; // 12 +static const uint64_t SH_FLD_IMA_HOLD_OUT = 11092; // 24 +static const uint64_t SH_FLD_IMM_FREEZE = 11093; // 43 +static const uint64_t SH_FLD_IMPLEMENTATION = 11094; // 96 +static const uint64_t SH_FLD_IMPLEMENTATION_DEPENDENT = 11095; // 24 +static const uint64_t SH_FLD_IMPLEMENTATION_DEPENDENT_LEN = 11096; // 24 +static const uint64_t SH_FLD_IN = 11097; // 264 +static const uint64_t SH_FLD_IN0 = 11098; // 339 +static const uint64_t SH_FLD_IN1 = 11099; // 296 +static const uint64_t SH_FLD_IN10 = 11100; // 208 +static const uint64_t SH_FLD_IN11 = 11101; // 208 +static const uint64_t SH_FLD_IN11_LEN = 11102; // 3 +static const uint64_t SH_FLD_IN12 = 11103; // 162 +static const uint64_t SH_FLD_IN12_LEN = 11104; // 6 +static const uint64_t SH_FLD_IN13 = 11105; // 156 +static const uint64_t SH_FLD_IN13_LEN = 11106; // 12 +static const uint64_t SH_FLD_IN14 = 11107; // 144 +static const uint64_t SH_FLD_IN14_LEN = 11108; // 3 +static const uint64_t SH_FLD_IN15 = 11109; // 141 +static const uint64_t SH_FLD_IN16 = 11110; // 141 +static const uint64_t SH_FLD_IN17 = 11111; // 141 +static const uint64_t SH_FLD_IN17_LEN = 11112; // 6 +static const uint64_t SH_FLD_IN18 = 11113; // 135 +static const uint64_t SH_FLD_IN18_LEN = 11114; // 3 +static const uint64_t SH_FLD_IN19 = 11115; // 132 +static const uint64_t SH_FLD_IN2 = 11116; // 296 +static const uint64_t SH_FLD_IN20 = 11117; // 132 +static const uint64_t SH_FLD_IN21 = 11118; // 132 +static const uint64_t SH_FLD_IN21_LEN = 11119; // 3 +static const uint64_t SH_FLD_IN22 = 11120; // 129 +static const uint64_t SH_FLD_IN23 = 11121; // 43 +static const uint64_t SH_FLD_IN24 = 11122; // 43 +static const uint64_t SH_FLD_IN25 = 11123; // 43 +static const uint64_t SH_FLD_IN26 = 11124; // 129 +static const uint64_t SH_FLD_IN27 = 11125; // 43 +static const uint64_t SH_FLD_IN28 = 11126; // 43 +static const uint64_t SH_FLD_IN29 = 11127; // 43 +static const uint64_t SH_FLD_IN3 = 11128; // 296 +static const uint64_t SH_FLD_IN30 = 11129; // 43 +static const uint64_t SH_FLD_IN31 = 11130; // 43 +static const uint64_t SH_FLD_IN32 = 11131; // 43 +static const uint64_t SH_FLD_IN33 = 11132; // 43 +static const uint64_t SH_FLD_IN34 = 11133; // 43 +static const uint64_t SH_FLD_IN35 = 11134; // 43 +static const uint64_t SH_FLD_IN36 = 11135; // 43 +static const uint64_t SH_FLD_IN37 = 11136; // 43 +static const uint64_t SH_FLD_IN38 = 11137; // 43 +static const uint64_t SH_FLD_IN39 = 11138; // 43 +static const uint64_t SH_FLD_IN3_LEN = 11139; // 1 +static const uint64_t SH_FLD_IN4 = 11140; // 338 +static const uint64_t SH_FLD_IN40 = 11141; // 43 +static const uint64_t SH_FLD_IN41 = 11142; // 43 +static const uint64_t SH_FLD_IN4_LEN = 11143; // 1 +static const uint64_t SH_FLD_IN5 = 11144; // 337 +static const uint64_t SH_FLD_IN5_LEN = 11145; // 78 +static const uint64_t SH_FLD_IN6 = 11146; // 260 +static const uint64_t SH_FLD_IN6_LEN = 11147; // 3 +static const uint64_t SH_FLD_IN7 = 11148; // 257 +static const uint64_t SH_FLD_IN7_LEN = 11149; // 9 +static const uint64_t SH_FLD_IN8 = 11150; // 248 +static const uint64_t SH_FLD_IN8_LEN = 11151; // 3 +static const uint64_t SH_FLD_IN9 = 11152; // 245 +static const uint64_t SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE = 11153; // 4 +static const uint64_t SH_FLD_INBD_ARRAY_ECC_CE = 11154; // 2 +static const uint64_t SH_FLD_INBD_ARRAY_ECC_UE = 11155; // 2 +static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_CE = 11156; // 1 +static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_SUE = 11157; // 1 +static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_UE = 11158; // 1 +static const uint64_t SH_FLD_INC = 11159; // 2 +static const uint64_t SH_FLD_INCLUDE_TRAFFIC = 11160; // 1 +static const uint64_t SH_FLD_INCOMING_PB_PARITY_ERR = 11161; // 2 +static const uint64_t SH_FLD_INC_LEN = 11162; // 2 +static const uint64_t SH_FLD_INDEX = 11163; // 1 +static const uint64_t SH_FLD_INDEX_LEN = 11164; // 1 +static const uint64_t SH_FLD_INDIRECT_BRIDGE_0_SOURCE = 11165; // 1 +static const uint64_t SH_FLD_INDIRECT_BRIDGE_1_SOURCE = 11166; // 1 +static const uint64_t SH_FLD_INDIRECT_BRIDGE_2_SOURCE = 11167; // 1 +static const uint64_t SH_FLD_INDIRECT_BRIDGE_3_SOURCE = 11168; // 1 +static const uint64_t SH_FLD_INDIRECT_MODE = 11169; // 2 +static const uint64_t SH_FLD_INDIR_THRDID = 11170; // 4 +static const uint64_t SH_FLD_INDIR_THRDID_LEN = 11171; // 4 +static const uint64_t SH_FLD_INDIR_VLD = 11172; // 4 +static const uint64_t SH_FLD_INEX = 11173; // 43 +static const uint64_t SH_FLD_INFINITE_MODE = 11174; // 43 +static const uint64_t SH_FLD_INFO = 11175; // 43 +static const uint64_t SH_FLD_INFORMATION = 11176; // 8 +static const uint64_t SH_FLD_INFORMATION_LEN = 11177; // 8 +static const uint64_t SH_FLD_INFO_CAPTURED = 11178; // 4 +static const uint64_t SH_FLD_INH0_TICK = 11179; // 12 +static const uint64_t SH_FLD_INH0_TICK_LEN = 11180; // 12 +static const uint64_t SH_FLD_INH1_TICK = 11181; // 12 +static const uint64_t SH_FLD_INH1_TICK_LEN = 11182; // 12 +static const uint64_t SH_FLD_INIT = 11183; // 1 +static const uint64_t SH_FLD_INITIAL_COARSE_WR = 11184; // 8 +static const uint64_t SH_FLD_INITIAL_PAT_WRITE = 11185; // 8 +static const uint64_t SH_FLD_INIT_DONE_DL_MASK = 11186; // 2 +static const uint64_t SH_FLD_INIT_REQUEST = 11187; // 1 +static const uint64_t SH_FLD_INIT_TIMER = 11188; // 1 +static const uint64_t SH_FLD_INIT_TIMER_LEN = 11189; // 1 +static const uint64_t SH_FLD_INJ = 11190; // 1 +static const uint64_t SH_FLD_INJECT_1HOT_SM_ERROR = 11191; // 8 +static const uint64_t SH_FLD_INJECT_ENABLE = 11192; // 1 +static const uint64_t SH_FLD_INJECT_ERR = 11193; // 12 +static const uint64_t SH_FLD_INJECT_FIR_ERR = 11194; // 8 +static const uint64_t SH_FLD_INJECT_FIR_ERR0_4 = 11195; // 8 +static const uint64_t SH_FLD_INJECT_FIR_ERR1_5 = 11196; // 8 +static const uint64_t SH_FLD_INJECT_FIR_ERR2_6 = 11197; // 8 +static const uint64_t SH_FLD_INJECT_FIR_ERR3_7 = 11198; // 8 +static const uint64_t SH_FLD_INJECT_MODE = 11199; // 2 +static const uint64_t SH_FLD_INJECT_MODE_LEN = 11200; // 2 +static const uint64_t SH_FLD_INJECT_TYPE = 11201; // 2 +static const uint64_t SH_FLD_INJECT_TYPE_LEN = 11202; // 2 +static const uint64_t SH_FLD_INJ_LEN = 11203; // 1 +static const uint64_t SH_FLD_INOP = 11204; // 43 +static const uint64_t SH_FLD_INOP_FORCE_SG = 11205; // 43 +static const uint64_t SH_FLD_INOP_LEN = 11206; // 43 +static const uint64_t SH_FLD_INOP_WAIT = 11207; // 43 +static const uint64_t SH_FLD_INOP_WAIT_LEN = 11208; // 43 +static const uint64_t SH_FLD_INPROG_WR_ERR = 11209; // 1 +static const uint64_t SH_FLD_INRD_DONE_ERR = 11210; // 1 +static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK = 11211; // 43 +static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO = 11212; // 43 +static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN = 11213; // 43 +static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN = 11214; // 43 +static const uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL = 11215; // 43 +static const uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 11216; // 43 +static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT = 11217; // 43 +static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN = 11218; // 43 +static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR = 11219; // 43 +static const uint64_t SH_FLD_INST1_COND3_ENABLE = 11220; // 43 +static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_BANK = 11221; // 43 +static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO = 11222; // 43 +static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO_LEN = 11223; // 43 +static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_WAITN = 11224; // 43 +static const uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL = 11225; // 43 +static const uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN = 11226; // 43 +static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_BANK = 11227; // 43 +static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO = 11228; // 43 +static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO_LEN = 11229; // 43 +static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_WAITN = 11230; // 43 +static const uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL = 11231; // 43 +static const uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN = 11232; // 43 +static const uint64_t SH_FLD_INST1_SLOW_LFSR_MODE = 11233; // 43 +static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK = 11234; // 43 +static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO = 11235; // 43 +static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN = 11236; // 43 +static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN = 11237; // 43 +static const uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL = 11238; // 43 +static const uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 11239; // 43 +static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT = 11240; // 43 +static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN = 11241; // 43 +static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR = 11242; // 43 +static const uint64_t SH_FLD_INST2_COND3_ENABLE = 11243; // 43 +static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_BANK = 11244; // 43 +static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO = 11245; // 43 +static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO_LEN = 11246; // 43 +static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_WAITN = 11247; // 43 +static const uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL = 11248; // 43 +static const uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN = 11249; // 43 +static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_BANK = 11250; // 43 +static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO = 11251; // 43 +static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO_LEN = 11252; // 43 +static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_WAITN = 11253; // 43 +static const uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL = 11254; // 43 +static const uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN = 11255; // 43 +static const uint64_t SH_FLD_INST2_SLOW_LFSR_MODE = 11256; // 43 +static const uint64_t SH_FLD_INST3_COND3_ENABLE = 11257; // 43 +static const uint64_t SH_FLD_INST3_SLOW_LFSR_MODE = 11258; // 43 +static const uint64_t SH_FLD_INST4_COND3_ENABLE = 11259; // 43 +static const uint64_t SH_FLD_INST4_SLOW_LFSR_MODE = 11260; // 43 +static const uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA = 11261; // 12 +static const uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA_LEN = 11262; // 12 +static const uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA = 11263; // 12 +static const uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA_LEN = 11264; // 12 +static const uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA = 11265; // 12 +static const uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA_LEN = 11266; // 12 +static const uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA = 11267; // 12 +static const uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA_LEN = 11268; // 12 +static const uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA = 11269; // 12 +static const uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA_LEN = 11270; // 12 +static const uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY = 11271; // 12 +static const uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN = 11272; // 12 +static const uint64_t SH_FLD_INSTR0_BUSYCNT_RUNNING = 11273; // 1 +static const uint64_t SH_FLD_INSTR0_CYCLECNT_RUNNING = 11274; // 1 +static const uint64_t SH_FLD_INSTR0_MODE = 11275; // 1 +static const uint64_t SH_FLD_INSTR0_MODE_LEN = 11276; // 1 +static const uint64_t SH_FLD_INSTR0_RESET = 11277; // 1 +static const uint64_t SH_FLD_INSTR0_START = 11278; // 1 +static const uint64_t SH_FLD_INSTR0_STOP = 11279; // 1 +static const uint64_t SH_FLD_INSTR0_STOPPED_ON_ERROR = 11280; // 1 +static const uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT = 11281; // 1 +static const uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN = 11282; // 1 +static const uint64_t SH_FLD_INSTR0_STOP_TIMER_EN = 11283; // 1 +static const uint64_t SH_FLD_INSTR1_BUSYCNT_RUNNING = 11284; // 1 +static const uint64_t SH_FLD_INSTR1_CYCLECNT_RUNNING = 11285; // 1 +static const uint64_t SH_FLD_INSTR1_MODE = 11286; // 1 +static const uint64_t SH_FLD_INSTR1_MODE_LEN = 11287; // 1 +static const uint64_t SH_FLD_INSTR1_RESET = 11288; // 1 +static const uint64_t SH_FLD_INSTR1_START = 11289; // 1 +static const uint64_t SH_FLD_INSTR1_STOP = 11290; // 1 +static const uint64_t SH_FLD_INSTR1_STOPPED_ON_ERROR = 11291; // 1 +static const uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT = 11292; // 1 +static const uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN = 11293; // 1 +static const uint64_t SH_FLD_INSTR1_STOP_TIMER_EN = 11294; // 1 +static const uint64_t SH_FLD_INSTR2_BUSYCNT_RUNNING = 11295; // 1 +static const uint64_t SH_FLD_INSTR2_CYCLECNT_RUNNING = 11296; // 1 +static const uint64_t SH_FLD_INSTR2_MODE = 11297; // 1 +static const uint64_t SH_FLD_INSTR2_MODE_LEN = 11298; // 1 +static const uint64_t SH_FLD_INSTR2_RESET = 11299; // 1 +static const uint64_t SH_FLD_INSTR2_START = 11300; // 1 +static const uint64_t SH_FLD_INSTR2_STOP = 11301; // 1 +static const uint64_t SH_FLD_INSTR2_STOPPED_ON_ERROR = 11302; // 1 +static const uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT = 11303; // 1 +static const uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN = 11304; // 1 +static const uint64_t SH_FLD_INSTR2_STOP_TIMER_EN = 11305; // 1 +static const uint64_t SH_FLD_INST_CYCLE_SAMPLE = 11306; // 12 +static const uint64_t SH_FLD_INST_CYCLE_SAMPLE_LEN = 11307; // 12 +static const uint64_t SH_FLD_INTERCME_DIRECT_IN_0 = 11308; // 12 +static const uint64_t SH_FLD_INTERCME_DIRECT_IN_1_2 = 11309; // 12 +static const uint64_t SH_FLD_INTERCME_DIRECT_IN_1_2_LEN = 11310; // 12 +static const uint64_t SH_FLD_INTERMITTENT_CE_COUNT = 11311; // 2 +static const uint64_t SH_FLD_INTERMITTENT_CE_COUNT_LEN = 11312; // 2 +static const uint64_t SH_FLD_INTERMITTENT_MCE_COUNT = 11313; // 2 +static const uint64_t SH_FLD_INTERMITTENT_MCE_COUNT_LEN = 11314; // 2 +static const uint64_t SH_FLD_INTERNAL = 11315; // 14 +static const uint64_t SH_FLD_INTERNAL_ERR = 11316; // 1 +static const uint64_t SH_FLD_INTERNAL_ERROR = 11317; // 9 +static const uint64_t SH_FLD_INTERNAL_ERR_MASK = 11318; // 1 +static const uint64_t SH_FLD_INTERNAL_FSM_ERROR = 11319; // 2 +static const uint64_t SH_FLD_INTERNAL_LEN = 11320; // 14 +static const uint64_t SH_FLD_INTERNAL_PARITY_ERROR = 11321; // 6 +static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR = 11322; // 39 +static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR_CLONE = 11323; // 15 +static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR_COPY = 11324; // 24 +static const uint64_t SH_FLD_INTERNAL_STATE_VECTOR = 11325; // 1 +static const uint64_t SH_FLD_INTERNAL_STATE_VECTOR_LEN = 11326; // 1 +static const uint64_t SH_FLD_INTERRUPT = 11327; // 3 +static const uint64_t SH_FLD_INTERRUPT0_ADDRESS_ERROR = 11328; // 4 +static const uint64_t SH_FLD_INTERRUPT1 = 11329; // 1 +static const uint64_t SH_FLD_INTERRUPT1_ADDRESS_ERROR = 11330; // 4 +static const uint64_t SH_FLD_INTERRUPT1_LEN = 11331; // 1 +static const uint64_t SH_FLD_INTERRUPT2 = 11332; // 1 +static const uint64_t SH_FLD_INTERRUPT2_ADDRESS_ERROR = 11333; // 4 +static const uint64_t SH_FLD_INTERRUPT2_LEN = 11334; // 1 +static const uint64_t SH_FLD_INTERRUPT3 = 11335; // 1 +static const uint64_t SH_FLD_INTERRUPT3_ADDRESS_ERROR = 11336; // 4 +static const uint64_t SH_FLD_INTERRUPT3_LEN = 11337; // 1 +static const uint64_t SH_FLD_INTERRUPT4 = 11338; // 1 +static const uint64_t SH_FLD_INTERRUPT4_ADDRESS_ERROR = 11339; // 4 +static const uint64_t SH_FLD_INTERRUPT4_LEN = 11340; // 1 +static const uint64_t SH_FLD_INTERRUPT5_ADDRESS_ERROR = 11341; // 4 +static const uint64_t SH_FLD_INTERRUPT_00 = 11342; // 1 +static const uint64_t SH_FLD_INTERRUPT_01 = 11343; // 1 +static const uint64_t SH_FLD_INTERRUPT_02 = 11344; // 1 +static const uint64_t SH_FLD_INTERRUPT_03 = 11345; // 1 +static const uint64_t SH_FLD_INTERRUPT_04 = 11346; // 1 +static const uint64_t SH_FLD_INTERRUPT_05 = 11347; // 1 +static const uint64_t SH_FLD_INTERRUPT_06 = 11348; // 1 +static const uint64_t SH_FLD_INTERRUPT_07 = 11349; // 1 +static const uint64_t SH_FLD_INTERRUPT_08 = 11350; // 1 +static const uint64_t SH_FLD_INTERRUPT_09 = 11351; // 1 +static const uint64_t SH_FLD_INTERRUPT_10 = 11352; // 1 +static const uint64_t SH_FLD_INTERRUPT_11 = 11353; // 1 +static const uint64_t SH_FLD_INTERRUPT_12 = 11354; // 1 +static const uint64_t SH_FLD_INTERRUPT_13 = 11355; // 1 +static const uint64_t SH_FLD_INTERRUPT_14 = 11356; // 1 +static const uint64_t SH_FLD_INTERRUPT_15 = 11357; // 1 +static const uint64_t SH_FLD_INTERRUPT_16 = 11358; // 1 +static const uint64_t SH_FLD_INTERRUPT_17 = 11359; // 1 +static const uint64_t SH_FLD_INTERRUPT_18 = 11360; // 1 +static const uint64_t SH_FLD_INTERRUPT_19 = 11361; // 1 +static const uint64_t SH_FLD_INTERRUPT_20 = 11362; // 1 +static const uint64_t SH_FLD_INTERRUPT_21 = 11363; // 1 +static const uint64_t SH_FLD_INTERRUPT_22 = 11364; // 1 +static const uint64_t SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE = 11365; // 4 +static const uint64_t SH_FLD_INTERRUPT_CONDITION_PENDING = 11366; // 1 +static const uint64_t SH_FLD_INTERRUPT_CRIT_STATUS_N = 11367; // 2 +static const uint64_t SH_FLD_INTERRUPT_CRIT_STATUS_N_LEN = 11368; // 2 +static const uint64_t SH_FLD_INTERRUPT_DEBUG_STATUS_N = 11369; // 2 +static const uint64_t SH_FLD_INTERRUPT_DEBUG_STATUS_N_LEN = 11370; // 2 +static const uint64_t SH_FLD_INTERRUPT_DISABLE = 11371; // 1 +static const uint64_t SH_FLD_INTERRUPT_DISABLE_LEN = 11372; // 1 +static const uint64_t SH_FLD_INTERRUPT_EDGE_POL_N = 11373; // 2 +static const uint64_t SH_FLD_INTERRUPT_EDGE_POL_N_LEN = 11374; // 2 +static const uint64_t SH_FLD_INTERRUPT_ENABLED = 11375; // 1 +static const uint64_t SH_FLD_INTERRUPT_FROM_ERROR = 11376; // 4 +static const uint64_t SH_FLD_INTERRUPT_FROM_FSP = 11377; // 4 +static const uint64_t SH_FLD_INTERRUPT_GPE0_STATUS_N = 11378; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE0_STATUS_N_LEN = 11379; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE1_STATUS_N = 11380; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE1_STATUS_N_LEN = 11381; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE2_STATUS_N = 11382; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE2_STATUS_N_LEN = 11383; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE3_STATUS_N = 11384; // 2 +static const uint64_t SH_FLD_INTERRUPT_GPE3_STATUS_N_LEN = 11385; // 2 +static const uint64_t SH_FLD_INTERRUPT_INPUT = 11386; // 12 +static const uint64_t SH_FLD_INTERRUPT_INPUT_LEN = 11387; // 12 +static const uint64_t SH_FLD_INTERRUPT_MASK = 11388; // 12 +static const uint64_t SH_FLD_INTERRUPT_MASK_LEN = 11389; // 12 +static const uint64_t SH_FLD_INTERRUPT_MASK_N = 11390; // 2 +static const uint64_t SH_FLD_INTERRUPT_MASK_N_LEN = 11391; // 2 +static const uint64_t SH_FLD_INTERRUPT_NONCRIT_STATUS_N = 11392; // 2 +static const uint64_t SH_FLD_INTERRUPT_NONCRIT_STATUS_N_LEN = 11393; // 2 +static const uint64_t SH_FLD_INTERRUPT_POLARITY = 11394; // 12 +static const uint64_t SH_FLD_INTERRUPT_POLARITY_LEN = 11395; // 12 +static const uint64_t SH_FLD_INTERRUPT_ROUTE_A_N = 11396; // 6 +static const uint64_t SH_FLD_INTERRUPT_ROUTE_A_N_LEN = 11397; // 6 +static const uint64_t SH_FLD_INTERRUPT_S0 = 11398; // 1 +static const uint64_t SH_FLD_INTERRUPT_S1 = 11399; // 1 +static const uint64_t SH_FLD_INTERRUPT_SENT = 11400; // 1 +static const uint64_t SH_FLD_INTERRUPT_STATUS = 11401; // 13 +static const uint64_t SH_FLD_INTERRUPT_STATUS_LEN = 11402; // 13 +static const uint64_t SH_FLD_INTERRUPT_TYPE = 11403; // 12 +static const uint64_t SH_FLD_INTERRUPT_TYPE_LEN = 11404; // 12 +static const uint64_t SH_FLD_INTERRUPT_TYPE_N = 11405; // 2 +static const uint64_t SH_FLD_INTERRUPT_TYPE_N_LEN = 11406; // 2 +static const uint64_t SH_FLD_INTERRUPT_UNCON_STATUS_N = 11407; // 2 +static const uint64_t SH_FLD_INTERRUPT_UNCON_STATUS_N_LEN = 11408; // 2 +static const uint64_t SH_FLD_INTER_FRAME_DELAY = 11409; // 1 +static const uint64_t SH_FLD_INTER_FRAME_DELAY_LEN = 11410; // 1 +static const uint64_t SH_FLD_INTQ_BAD_CRESP = 11411; // 1 +static const uint64_t SH_FLD_INTQ_FSM_PERR = 11412; // 1 +static const uint64_t SH_FLD_INTQ_OP_HANG = 11413; // 1 +static const uint64_t SH_FLD_INTQ_OVERFLOW = 11414; // 1 +static const uint64_t SH_FLD_INTR0 = 11415; // 5 +static const uint64_t SH_FLD_INTR1 = 11416; // 5 +static const uint64_t SH_FLD_INTR_GRANTED = 11417; // 30 +static const uint64_t SH_FLD_INT_0 = 11418; // 4 +static const uint64_t SH_FLD_INT_0_LEN = 11419; // 4 +static const uint64_t SH_FLD_INT_1 = 11420; // 2 +static const uint64_t SH_FLD_INT_1_LEN = 11421; // 2 +static const uint64_t SH_FLD_INT_2 = 11422; // 2 +static const uint64_t SH_FLD_INT_2_LEN = 11423; // 2 +static const uint64_t SH_FLD_INT_3 = 11424; // 2 +static const uint64_t SH_FLD_INT_3_LEN = 11425; // 2 +static const uint64_t SH_FLD_INT_CNTR_REF = 11426; // 1 +static const uint64_t SH_FLD_INT_CNTR_REF_LEN = 11427; // 1 +static const uint64_t SH_FLD_INT_COND_0 = 11428; // 1 +static const uint64_t SH_FLD_INT_COND_1 = 11429; // 1 +static const uint64_t SH_FLD_INT_COND_2 = 11430; // 1 +static const uint64_t SH_FLD_INT_CURRENT_STATE = 11431; // 6 +static const uint64_t SH_FLD_INT_CURRENT_STATE_LEN = 11432; // 6 +static const uint64_t SH_FLD_INT_ENA = 11433; // 1 +static const uint64_t SH_FLD_INT_ENABLE_ENC = 11434; // 6 +static const uint64_t SH_FLD_INT_ENABLE_ENC_LEN = 11435; // 6 +static const uint64_t SH_FLD_INT_EN_0 = 11436; // 1 +static const uint64_t SH_FLD_INT_EN_1 = 11437; // 1 +static const uint64_t SH_FLD_INT_EN_2 = 11438; // 1 +static const uint64_t SH_FLD_INT_GOTO_STATE = 11439; // 6 +static const uint64_t SH_FLD_INT_GOTO_STATE_LEN = 11440; // 6 +static const uint64_t SH_FLD_INT_MODE = 11441; // 30 +static const uint64_t SH_FLD_INT_MODE_LEN = 11442; // 6 +static const uint64_t SH_FLD_INT_NCE_ETE_ATTN = 11443; // 2 +static const uint64_t SH_FLD_INT_NEXT_STATE = 11444; // 6 +static const uint64_t SH_FLD_INT_NEXT_STATE_LEN = 11445; // 6 +static const uint64_t SH_FLD_INT_POL_0 = 11446; // 1 +static const uint64_t SH_FLD_INT_POL_1 = 11447; // 1 +static const uint64_t SH_FLD_INT_POL_2 = 11448; // 1 +static const uint64_t SH_FLD_INT_RETURN_STATE = 11449; // 6 +static const uint64_t SH_FLD_INT_RETURN_STATE_LEN = 11450; // 6 +static const uint64_t SH_FLD_INT_RX_FSM = 11451; // 43 +static const uint64_t SH_FLD_INT_STATE_ERR = 11452; // 1 +static const uint64_t SH_FLD_INT_STAT_0 = 11453; // 1 +static const uint64_t SH_FLD_INT_STAT_1 = 11454; // 1 +static const uint64_t SH_FLD_INT_STAT_2 = 11455; // 1 +static const uint64_t SH_FLD_INT_TIMEOUT = 11456; // 43 +static const uint64_t SH_FLD_INT_TIMEOUT_LEN = 11457; // 43 +static const uint64_t SH_FLD_INT_TX_FSM = 11458; // 43 +static const uint64_t SH_FLD_INT_TYPE = 11459; // 43 +static const uint64_t SH_FLD_INVALIDATE_ADDRESS = 11460; // 1 +static const uint64_t SH_FLD_INVALIDATE_ADDRESS_LEN = 11461; // 1 +static const uint64_t SH_FLD_INVALIDATE_ALL = 11462; // 1 +static const uint64_t SH_FLD_INVALIDATE_ERAT = 11463; // 24 +static const uint64_t SH_FLD_INVALIDATE_ONE = 11464; // 1 +static const uint64_t SH_FLD_INVALIDATE_PE_NUMBER = 11465; // 1 +static const uint64_t SH_FLD_INVALIDATE_PE_NUMBER_LEN = 11466; // 1 +static const uint64_t SH_FLD_INVALID_ADDRESS = 11467; // 15 +static const uint64_t SH_FLD_INVALID_ADDRESS_ALIGNMENT = 11468; // 4 +static const uint64_t SH_FLD_INVALID_ADDRESS_MASK = 11469; // 8 +static const uint64_t SH_FLD_INVALID_CMD_0 = 11470; // 4 +static const uint64_t SH_FLD_INVALID_CMD_1 = 11471; // 2 +static const uint64_t SH_FLD_INVALID_CMD_2 = 11472; // 2 +static const uint64_t SH_FLD_INVALID_CMD_3 = 11473; // 2 +static const uint64_t SH_FLD_INVALID_COMMAND = 11474; // 4 +static const uint64_t SH_FLD_INVALID_CRESP = 11475; // 4 +static const uint64_t SH_FLD_INVALID_CRESP_ERR = 11476; // 1 +static const uint64_t SH_FLD_INVALID_CRESP_ERROR = 11477; // 2 +static const uint64_t SH_FLD_INVALID_MAINT_ADDRESS = 11478; // 4 +static const uint64_t SH_FLD_INVALID_MAINT_ADDRESS_LEN = 11479; // 2 +static const uint64_t SH_FLD_INVALID_REQTYPE = 11480; // 16 +static const uint64_t SH_FLD_INVALID_REQTYPE_ERR_MASK = 11481; // 8 +static const uint64_t SH_FLD_INVALID_REQTYPE_LEN = 11482; // 8 +static const uint64_t SH_FLD_INVALID_REQ_SOURCE = 11483; // 8 +static const uint64_t SH_FLD_INVALID_REQ_SOURCE_LEN = 11484; // 8 +static const uint64_t SH_FLD_INVALID_STATE_RECOV = 11485; // 1 +static const uint64_t SH_FLD_INVALID_STATE_UNRECOV = 11486; // 1 +static const uint64_t SH_FLD_INVALID_TRANSFER_SIZE = 11487; // 4 +static const uint64_t SH_FLD_INVALID_TTYPE = 11488; // 4 +static const uint64_t SH_FLD_INVAL_IODA_TBL_SEL_ESR = 11489; // 1 +static const uint64_t SH_FLD_INVERTED_VDM_DATA = 11490; // 6 +static const uint64_t SH_FLD_INVERTED_VDM_DATA_LEN = 11491; // 6 +static const uint64_t SH_FLD_INVERT_SENSE = 11492; // 36 +static const uint64_t SH_FLD_INVLD_CMD_ERR = 11493; // 1 +static const uint64_t SH_FLD_INVLD_PRGM_ERR = 11494; // 1 +static const uint64_t SH_FLD_INV_PROT_ERR_CHK_DIS = 11495; // 1 +static const uint64_t SH_FLD_INV_SH_ERROR_RATE = 11496; // 2 +static const uint64_t SH_FLD_INV_SH_ERROR_RATE_LEN = 11497; // 2 +static const uint64_t SH_FLD_INV_SINGLE_THREAD_EN = 11498; // 1 +static const uint64_t SH_FLD_INV_SM_CTL_ERR_DET = 11499; // 1 +static const uint64_t SH_FLD_INV_TIMEOUT_CHK_DIS = 11500; // 1 +static const uint64_t SH_FLD_INV_TIMEOUT_ERR_DET = 11501; // 1 +static const uint64_t SH_FLD_IN_BAD_OP_ERR = 11502; // 2 +static const uint64_t SH_FLD_IN_CERR_BIT10 = 11503; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT11 = 11504; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT12 = 11505; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT13 = 11506; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT14 = 11507; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT15 = 11508; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT16 = 11509; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT17 = 11510; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT18 = 11511; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT19 = 11512; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT20 = 11513; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT21 = 11514; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT22 = 11515; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT23 = 11516; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT24 = 11517; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT25 = 11518; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT26 = 11519; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT27 = 11520; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT28 = 11521; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT29 = 11522; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT30 = 11523; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT31 = 11524; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT4 = 11525; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT5 = 11526; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT6 = 11527; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT7 = 11528; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT8 = 11529; // 1 +static const uint64_t SH_FLD_IN_CERR_BIT9 = 11530; // 1 +static const uint64_t SH_FLD_IN_CERR_RESET = 11531; // 1 +static const uint64_t SH_FLD_IN_COUNT1 = 11532; // 1 +static const uint64_t SH_FLD_IN_COUNT1_LEN = 11533; // 1 +static const uint64_t SH_FLD_IN_COUNT2 = 11534; // 1 +static const uint64_t SH_FLD_IN_COUNT2_LEN = 11535; // 1 +static const uint64_t SH_FLD_IN_DELAY1 = 11536; // 1 +static const uint64_t SH_FLD_IN_DELAY1_LEN = 11537; // 1 +static const uint64_t SH_FLD_IN_DELAY2 = 11538; // 1 +static const uint64_t SH_FLD_IN_DELAY2_LEN = 11539; // 1 +static const uint64_t SH_FLD_IN_ECC_CE_ERROR = 11540; // 2 +static const uint64_t SH_FLD_IN_ECC_SUE_ERROR = 11541; // 2 +static const uint64_t SH_FLD_IN_ECC_UE_ERROR = 11542; // 2 +static const uint64_t SH_FLD_IN_LEN = 11543; // 264 +static const uint64_t SH_FLD_IN_LOGIC_HW_ERROR = 11544; // 2 +static const uint64_t SH_FLD_IN_MASTER_MODE = 11545; // 43 +static const uint64_t SH_FLD_IN_PARITY_ERROR = 11546; // 2 +static const uint64_t SH_FLD_IN_PROG = 11547; // 1 +static const uint64_t SH_FLD_IN_PROG_LEN = 11548; // 1 +static const uint64_t SH_FLD_IN_SEQ_ERR = 11549; // 2 +static const uint64_t SH_FLD_IN_SEQ_PERR = 11550; // 2 +static const uint64_t SH_FLD_IN_SLAVE_MODE = 11551; // 43 +static const uint64_t SH_FLD_IN_SNP_ADDR_PERR = 11552; // 2 +static const uint64_t SH_FLD_IN_SNP_TTAG_PERR = 11553; // 2 +static const uint64_t SH_FLD_IN_SW_CAST_ERROR = 11554; // 2 +static const uint64_t SH_FLD_IN_TIMEOUT = 11555; // 2 +static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI = 11556; // 1 +static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN = 11557; // 1 +static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO = 11558; // 1 +static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN = 11559; // 1 +static const uint64_t SH_FLD_IN_TRACE_INT_DATA_HI = 11560; // 1 +static const uint64_t SH_FLD_IN_TRACE_INT_DATA_LO = 11561; // 1 +static const uint64_t SH_FLD_IN_TRACE_INT_TRIG_01 = 11562; // 1 +static const uint64_t SH_FLD_IN_TRACE_INT_TRIG_23 = 11563; // 1 +static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01 = 11564; // 1 +static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN = 11565; // 1 +static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23 = 11566; // 1 +static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN = 11567; // 1 +static const uint64_t SH_FLD_IOCLK_SLIP = 11568; // 72 +static const uint64_t SH_FLD_IOCLK_SLIP_LEN = 11569; // 72 +static const uint64_t SH_FLD_IOCLK_SLIP_STROBE = 11570; // 72 +static const uint64_t SH_FLD_IODA_ADDR_PERR_ESR = 11571; // 1 +static const uint64_t SH_FLD_IOE01_IS_LOGICAL_PAIR = 11572; // 1 +static const uint64_t SH_FLD_IOE23_IS_LOGICAL_PAIR = 11573; // 1 +static const uint64_t SH_FLD_IOE45_IS_LOGICAL_PAIR = 11574; // 1 +static const uint64_t SH_FLD_IOO01_IS_LOGICAL_PAIR = 11575; // 1 +static const uint64_t SH_FLD_IOO23_IS_LOGICAL_PAIR = 11576; // 1 +static const uint64_t SH_FLD_IOO45_IS_LOGICAL_PAIR = 11577; // 1 +static const uint64_t SH_FLD_IOO67_IS_LOGICAL_PAIR = 11578; // 1 +static const uint64_t SH_FLD_IORESET = 11579; // 107 +static const uint64_t SH_FLD_IORESET_HARD_BUS0 = 11580; // 4 +static const uint64_t SH_FLD_IOVALID_10D = 11581; // 35 +static const uint64_t SH_FLD_IOVALID_11D = 11582; // 36 +static const uint64_t SH_FLD_IOVALID_4D = 11583; // 31 +static const uint64_t SH_FLD_IOVALID_5D = 11584; // 32 +static const uint64_t SH_FLD_IOVALID_6D = 11585; // 35 +static const uint64_t SH_FLD_IOVALID_7D = 11586; // 35 +static const uint64_t SH_FLD_IOVALID_8D = 11587; // 35 +static const uint64_t SH_FLD_IOVALID_9D = 11588; // 35 +static const uint64_t SH_FLD_IP = 11589; // 4 +static const uint64_t SH_FLD_IPB = 11590; // 1 +static const uint64_t SH_FLD_IPB_LEN = 11591; // 1 +static const uint64_t SH_FLD_IPI = 11592; // 1 +static const uint64_t SH_FLD_IPI0_HI_PRIORITY = 11593; // 1 +static const uint64_t SH_FLD_IPI0_LO_PRIORITY = 11594; // 1 +static const uint64_t SH_FLD_IPI1_HI_PRIORITY = 11595; // 1 +static const uint64_t SH_FLD_IPI1_LO_PRIORITY = 11596; // 1 +static const uint64_t SH_FLD_IPI2_HI_PRIORITY = 11597; // 1 +static const uint64_t SH_FLD_IPI2_LO_PRIORITY = 11598; // 1 +static const uint64_t SH_FLD_IPI3_HI_PRIORITY = 11599; // 1 +static const uint64_t SH_FLD_IPI3_LO_PRIORITY = 11600; // 1 +static const uint64_t SH_FLD_IPI4_HI_PRIORITY = 11601; // 1 +static const uint64_t SH_FLD_IPI4_LO_PRIORITY = 11602; // 1 +static const uint64_t SH_FLD_IPI_LEN = 11603; // 1 +static const uint64_t SH_FLD_IPI_OS = 11604; // 1 +static const uint64_t SH_FLD_IPI_PRIORITY = 11605; // 1 +static const uint64_t SH_FLD_IPI_PRIORITY_LEN = 11606; // 1 +static const uint64_t SH_FLD_IPI_PS = 11607; // 1 +static const uint64_t SH_FLD_IPI_RSD = 11608; // 1 +static const uint64_t SH_FLD_IPI_RSD_LEN = 11609; // 1 +static const uint64_t SH_FLD_IPOLL_0 = 11610; // 1 +static const uint64_t SH_FLD_IPOLL_1 = 11611; // 1 +static const uint64_t SH_FLD_IPOLL_2 = 11612; // 1 +static const uint64_t SH_FLD_IPOLL_3 = 11613; // 1 +static const uint64_t SH_FLD_IPOLL_4 = 11614; // 1 +static const uint64_t SH_FLD_IPOLL_5 = 11615; // 1 +static const uint64_t SH_FLD_IPW_SIDEAB_SEL = 11616; // 8 +static const uint64_t SH_FLD_IPW_WR_WR = 11617; // 8 +static const uint64_t SH_FLD_IPW_WR_WR_LEN = 11618; // 8 +static const uint64_t SH_FLD_IQSPD_CFG = 11619; // 4 +static const uint64_t SH_FLD_IQSPD_CFG_LEN = 11620; // 4 +static const uint64_t SH_FLD_IR = 11621; // 117 +static const uint64_t SH_FLD_IREF_BYPASS = 11622; // 2 +static const uint64_t SH_FLD_IREF_PDWN_B = 11623; // 2 +static const uint64_t SH_FLD_IREF_RES_DAC = 11624; // 2 +static const uint64_t SH_FLD_IREF_RES_DAC_LEN = 11625; // 2 +static const uint64_t SH_FLD_IRQ = 11626; // 1 +static const uint64_t SH_FLD_IRQENA = 11627; // 1 +static const uint64_t SH_FLD_IRQ_EFIFO_DIN_ERROR = 11628; // 1 +static const uint64_t SH_FLD_IRQ_EQC_CREDIT_ERROR = 11629; // 1 +static const uint64_t SH_FLD_IRQ_EQPQ_ERROR = 11630; // 1 +static const uint64_t SH_FLD_IRQ_EQ_ERROR = 11631; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_ACCESS_ERROR = 11632; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_CRD_ERROR = 11633; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_DATA_ERROR = 11634; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_DIR_RD_ERROR = 11635; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_DIR_STATE_ERROR = 11636; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_DIR_WR_ERROR = 11637; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_ECC_CE = 11638; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_ECC_UE = 11639; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_IDX_ERROR = 11640; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_INVALID_STATE = 11641; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_OFFSET_ERROR = 11642; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_OVERFLOW = 11643; // 1 +static const uint64_t SH_FLD_IRQ_FIFO_UNDERFLOW = 11644; // 1 +static const uint64_t SH_FLD_IRQ_INPUT_BUF_ERROR = 11645; // 1 +static const uint64_t SH_FLD_IRQ_LEN = 11646; // 1 +static const uint64_t SH_FLD_IRQ_PQ_ERROR = 11647; // 1 +static const uint64_t SH_FLD_IRQ_TRACE_ENABLE = 11648; // 1 +static const uint64_t SH_FLD_IRQ_TRIG_CRD_ERROR = 11649; // 1 +static const uint64_t SH_FLD_IR_DR_EQ0_ERR = 11650; // 1 +static const uint64_t SH_FLD_IR_LEN = 11651; // 21 +static const uint64_t SH_FLD_IS = 11652; // 8 +static const uint64_t SH_FLD_ISS426_FIX_DIS = 11653; // 1 +static const uint64_t SH_FLD_ISS486_FIX_DIS = 11654; // 1 +static const uint64_t SH_FLD_ISS487_EN = 11655; // 1 +static const uint64_t SH_FLD_ISS505_FIX_DIS = 11656; // 2 +static const uint64_t SH_FLD_ISS510_FIX_DIS = 11657; // 2 +static const uint64_t SH_FLD_ISS511_FIX_DIS = 11658; // 1 +static const uint64_t SH_FLD_ISS512_FIX_DIS = 11659; // 1 +static const uint64_t SH_FLD_ISS526_EN = 11660; // 1 +static const uint64_t SH_FLD_ISS534_FIX_DIS = 11661; // 1 +static const uint64_t SH_FLD_ISS537_FIX_DIS = 11662; // 1 +static const uint64_t SH_FLD_ISS540_FIX_DIS = 11663; // 1 +static const uint64_t SH_FLD_ISS542_FIX_DIS = 11664; // 2 +static const uint64_t SH_FLD_ISS543B_FIX_EN = 11665; // 1 +static const uint64_t SH_FLD_ISS543_FIX_DIS = 11666; // 1 +static const uint64_t SH_FLD_ISS544_FIX_DIS = 11667; // 1 +static const uint64_t SH_FLD_ISS554_FIX_DIS = 11668; // 1 +static const uint64_t SH_FLD_ISS567_FIX_DIS = 11669; // 1 +static const uint64_t SH_FLD_ISU_HLD_OUT_REG6 = 11670; // 24 +static const uint64_t SH_FLD_ISU_HLD_OUT_REG6_LEN = 11671; // 24 +static const uint64_t SH_FLD_IS_ACTIVE_MASTER = 11672; // 1 +static const uint64_t SH_FLD_IS_BACKUP_MASTER = 11673; // 1 +static const uint64_t SH_FLD_IS_LEN = 11674; // 8 +static const uint64_t SH_FLD_IS_PRIMARY = 11675; // 1 +static const uint64_t SH_FLD_IS_RUNNING = 11676; // 2 +static const uint64_t SH_FLD_IS_SECONDARY = 11677; // 1 +static const uint64_t SH_FLD_IS_SLAVE = 11678; // 1 +static const uint64_t SH_FLD_IS_SPECIAL = 11679; // 1 +static const uint64_t SH_FLD_ITUNE = 11680; // 4 +static const uint64_t SH_FLD_ITUNE_LEN = 11681; // 4 +static const uint64_t SH_FLD_IVC = 11682; // 1 +static const uint64_t SH_FLD_IVC_AIB_RESP_ERROR = 11683; // 1 +static const uint64_t SH_FLD_IVC_DATA_SRAM_ECC_UE = 11684; // 1 +static const uint64_t SH_FLD_IVC_INTF_DISABLE = 11685; // 6 +static const uint64_t SH_FLD_IVC_LEN = 11686; // 1 +static const uint64_t SH_FLD_IVC_PARITY_ERROR = 11687; // 1 +static const uint64_t SH_FLD_IVC_PROCESSING_ERROR = 11688; // 1 +static const uint64_t SH_FLD_IVC_PTAG_ASSIGN_ERROR = 11689; // 1 +static const uint64_t SH_FLD_IVC_PTAG_RELEASE_ERROR = 11690; // 1 +static const uint64_t SH_FLD_IVC_REPLAY_ERROR = 11691; // 1 +static const uint64_t SH_FLD_IVC_SRAM_ECC_CE = 11692; // 1 +static const uint64_t SH_FLD_IVC_STATE_SRAM_ECC_UE = 11693; // 1 +static const uint64_t SH_FLD_IVC_TAG_SRAM_ECC_UE = 11694; // 1 +static const uint64_t SH_FLD_IVC_UNLOCK_FIFO_OVERFLOW = 11695; // 1 +static const uint64_t SH_FLD_IVE_BLOCK = 11696; // 1 +static const uint64_t SH_FLD_IVE_BLOCK_LEN = 11697; // 1 +static const uint64_t SH_FLD_IVE_INDEX = 11698; // 1 +static const uint64_t SH_FLD_IVE_INDEX_LEN = 11699; // 1 +static const uint64_t SH_FLD_IVPR = 11700; // 5 +static const uint64_t SH_FLD_IVPR_LEN = 11701; // 5 +static const uint64_t SH_FLD_IVRM_BYPASS_B = 11702; // 60 +static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY = 11703; // 6 +static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY_FSP = 11704; // 30 +static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY_HYP = 11705; // 30 +static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY_OCC = 11706; // 30 +static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY_OTR = 11707; // 30 +static const uint64_t SH_FLD_IVRM_IVID = 11708; // 60 +static const uint64_t SH_FLD_IVRM_IVID_LEN = 11709; // 60 +static const uint64_t SH_FLD_IVRM_LOCAL_CONTROL = 11710; // 24 +static const uint64_t SH_FLD_IVRM_PFET_STRENGTH = 11711; // 30 +static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE = 11712; // 30 +static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN = 11713; // 30 +static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE = 11714; // 30 +static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN = 11715; // 30 +static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_LEN = 11716; // 30 +static const uint64_t SH_FLD_IVRM_POWERON = 11717; // 60 +static const uint64_t SH_FLD_IVRM_PROTECT_ACTIVE = 11718; // 30 +static const uint64_t SH_FLD_IVRM_PVREF_ERROR = 11719; // 1 +static const uint64_t SH_FLD_IVRM_UREG_TEST_EN = 11720; // 24 +static const uint64_t SH_FLD_IVRM_UREG_TEST_ID = 11721; // 24 +static const uint64_t SH_FLD_IVRM_UREG_TEST_ID_LEN = 11722; // 24 +static const uint64_t SH_FLD_IVRM_VID_DONE = 11723; // 30 +static const uint64_t SH_FLD_IVRM_VID_VALID = 11724; // 60 +static const uint64_t SH_FLD_IVRM_VREG_SLOW_DC = 11725; // 60 +static const uint64_t SH_FLD_I_DELAY_ADJUST_RATIO = 11726; // 1 +static const uint64_t SH_FLD_I_DELAY_ADJUST_RATIO_LEN = 11727; // 1 +static const uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT = 11728; // 1 +static const uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 11729; // 1 +static const uint64_t SH_FLD_I_PATH_DELAY_ADJUST = 11730; // 1 +static const uint64_t SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY = 11731; // 4 +static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD = 11732; // 1 +static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 11733; // 1 +static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 11734; // 1 +static const uint64_t SH_FLD_I_PATH_DELAY_VALUE = 11735; // 2 +static const uint64_t SH_FLD_I_PATH_DELAY_VALUE_LEN = 11736; // 2 +static const uint64_t SH_FLD_I_PATH_FSM_STATE_PARITY = 11737; // 4 +static const uint64_t SH_FLD_I_PATH_STATE = 11738; // 1 +static const uint64_t SH_FLD_I_PATH_STATE_LEN = 11739; // 1 +static const uint64_t SH_FLD_I_PATH_STEP_CHECK = 11740; // 4 +static const uint64_t SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 11741; // 1 +static const uint64_t SH_FLD_I_PATH_STEP_CHECK_VALID = 11742; // 1 +static const uint64_t SH_FLD_I_PATH_SYNC_CHECK = 11743; // 4 +static const uint64_t SH_FLD_I_PATH_SYNC_CHECK_DISABLE = 11744; // 1 +static const uint64_t SH_FLD_I_PATH_TIME_OVERFLOW = 11745; // 3 +static const uint64_t SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 11746; // 1 +static const uint64_t SH_FLD_I_PATH_TIME_PARITY = 11747; // 4 +static const uint64_t SH_FLD_JITTER_EPSILON = 11748; // 8 +static const uint64_t SH_FLD_JITTER_EPSILON_LEN = 11749; // 8 +static const uint64_t SH_FLD_JTAGACC_CERRPT = 11750; // 1 +static const uint64_t SH_FLD_JTAGACC_CERRPT_LEN = 11751; // 1 +static const uint64_t SH_FLD_JTAGACC_ERR = 11752; // 1 +static const uint64_t SH_FLD_JTAGACC_ERR_MASK = 11753; // 1 +static const uint64_t SH_FLD_JTAG_INPROG = 11754; // 1 +static const uint64_t SH_FLD_JTAG_INSTR = 11755; // 1 +static const uint64_t SH_FLD_JTAG_INSTR_LEN = 11756; // 1 +static const uint64_t SH_FLD_JTAG_SRC_SEL = 11757; // 1 +static const uint64_t SH_FLD_JTAG_TDI = 11758; // 1 +static const uint64_t SH_FLD_JTAG_TDI_LEN = 11759; // 1 +static const uint64_t SH_FLD_JTAG_TDO = 11760; // 1 +static const uint64_t SH_FLD_JTAG_TDO_LEN = 11761; // 1 +static const uint64_t SH_FLD_JTAG_TRST_B = 11762; // 1 +static const uint64_t SH_FLD_KEEP_MS_MODE = 11763; // 43 +static const uint64_t SH_FLD_KPRIME = 11764; // 8 +static const uint64_t SH_FLD_L = 11765; // 8 +static const uint64_t SH_FLD_L2 = 11766; // 12 +static const uint64_t SH_FLD_L2N_INCDECFSM_STATE_HISTORY_Q = 11767; // 6 +static const uint64_t SH_FLD_L2N_INCDECFSM_STATE_HISTORY_Q_LEN = 11768; // 6 +static const uint64_t SH_FLD_L2N_PDLYFSM_STATE_HISTORY_Q = 11769; // 6 +static const uint64_t SH_FLD_L2N_PDLYFSM_STATE_HISTORY_Q_LEN = 11770; // 6 +static const uint64_t SH_FLD_L2S_INCDECFSM_STATE_HISTORY_Q = 11771; // 6 +static const uint64_t SH_FLD_L2S_INCDECFSM_STATE_HISTORY_Q_LEN = 11772; // 6 +static const uint64_t SH_FLD_L2S_PDLYFSM_STATE_HISTORY_Q = 11773; // 6 +static const uint64_t SH_FLD_L2S_PDLYFSM_STATE_HISTORY_Q_LEN = 11774; // 6 +static const uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C0 = 11775; // 12 +static const uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C1 = 11776; // 12 +static const uint64_t SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET = 11777; // 6 +static const uint64_t SH_FLD_L2_EX0_CLKGLM_SEL = 11778; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_OVERRIDE = 11779; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE = 11780; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN = 11781; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN = 11782; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_SPARE0 = 11783; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH = 11784; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN = 11785; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SW_OVERRIDE = 11786; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK = 11787; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN = 11788; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SW_SPARE1 = 11789; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SYNC = 11790; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SYNC_DONE = 11791; // 6 +static const uint64_t SH_FLD_L2_EX0_CLK_SYNC_ENABLE = 11792; // 6 +static const uint64_t SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET = 11793; // 6 +static const uint64_t SH_FLD_L2_EX1_CLKGLM_SEL = 11794; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_OVERRIDE = 11795; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE = 11796; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN = 11797; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN = 11798; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_SPARE0 = 11799; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH = 11800; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN = 11801; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SW_OVERRIDE = 11802; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK = 11803; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN = 11804; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SW_SPARE1 = 11805; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SYNC = 11806; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SYNC_DONE = 11807; // 6 +static const uint64_t SH_FLD_L2_EX1_CLK_SYNC_ENABLE = 11808; // 6 +static const uint64_t SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 = 11809; // 12 +static const uint64_t SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 11810; // 12 +static const uint64_t SH_FLD_L2_LEN = 11811; // 12 +static const uint64_t SH_FLD_L2_PURGE = 11812; // 12 +static const uint64_t SH_FLD_L2_PURGE_ABORT = 11813; // 12 +static const uint64_t SH_FLD_L2_PURGE_DONE = 11814; // 24 +static const uint64_t SH_FLD_L2_STEP_MODE = 11815; // 12 +static const uint64_t SH_FLD_L2_STEP_MODE_LEN = 11816; // 12 +static const uint64_t SH_FLD_L2_STOPPED = 11817; // 1 +static const uint64_t SH_FLD_L2_STOPPED_LEN = 11818; // 1 +static const uint64_t SH_FLD_L3 = 11819; // 24 +static const uint64_t SH_FLD_L3CERRS_CFG_DCACHE_CAPP = 11820; // 12 +static const uint64_t SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS = 11821; // 12 +static const uint64_t SH_FLD_L3CICTL_CI_OVERRUN_CK = 11822; // 12 +static const uint64_t SH_FLD_L3CORTR_NO_LCO_TGTS = 11823; // 12 +static const uint64_t SH_FLD_L3L2CTL_PF_OVERRUN_CK = 11824; // 12 +static const uint64_t SH_FLD_L3L2CTL_RD_OVERRUN_CK = 11825; // 12 +static const uint64_t SH_FLD_L3PBEXCA0_OVERFLOW = 11826; // 12 +static const uint64_t SH_FLD_L3PBEXCA0_UNDERFLOW = 11827; // 12 +static const uint64_t SH_FLD_L3PBEXCA1_OVERFLOW = 11828; // 12 +static const uint64_t SH_FLD_L3PBEXCA1_UNDERFLOW = 11829; // 12 +static const uint64_t SH_FLD_L3SDRTL0_BAD_HPC = 11830; // 12 +static const uint64_t SH_FLD_L3SDRTL0_CACHE_INHIBIT = 11831; // 12 +static const uint64_t SH_FLD_L3SDRTL1_BAD_HPC = 11832; // 12 +static const uint64_t SH_FLD_L3SDRTL1_CACHE_INHIBIT = 11833; // 12 +static const uint64_t SH_FLD_L3SDRTL2_BAD_HPC = 11834; // 12 +static const uint64_t SH_FLD_L3SDRTL2_CACHE_INHIBIT = 11835; // 12 +static const uint64_t SH_FLD_L3SDRTL3_BAD_HPC = 11836; // 12 +static const uint64_t SH_FLD_L3SDRTL3_CACHE_INHIBIT = 11837; // 12 +static const uint64_t SH_FLD_L3XMEMA0_CRW_DIR_HIT = 11838; // 12 +static const uint64_t SH_FLD_L3XMEMA0_DW_DIR_HIT = 11839; // 12 +static const uint64_t SH_FLD_L3XMEMA1_CRW_DIR_HIT = 11840; // 12 +static const uint64_t SH_FLD_L3XMEMA1_DW_DIR_HIT = 11841; // 12 +static const uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME = 11842; // 12 +static const uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME_LEN = 11843; // 12 +static const uint64_t SH_FLD_L3_1ST_BEAT_UE = 11844; // 12 +static const uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME = 11845; // 12 +static const uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME_LEN = 11846; // 12 +static const uint64_t SH_FLD_L3_2ND_BEAT_UE = 11847; // 12 +static const uint64_t SH_FLD_L3_ABORT = 11848; // 12 +static const uint64_t SH_FLD_L3_ADDR_HANG_DETECTED = 11849; // 12 +static const uint64_t SH_FLD_L3_ADDR_HANG_DETECTED_MASK = 11850; // 12 +static const uint64_t SH_FLD_L3_ADDR_HASH_EN_CFG = 11851; // 12 +static const uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR = 11852; // 12 +static const uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR_MASK = 11853; // 12 +static const uint64_t SH_FLD_L3_BANK = 11854; // 12 +static const uint64_t SH_FLD_L3_BANK_LEN = 11855; // 12 +static const uint64_t SH_FLD_L3_BUSY_ERR = 11856; // 36 +static const uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 11857; // 12 +static const uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ_MASK = 11858; // 12 +static const uint64_t SH_FLD_L3_CAC_RD_SUE_DET = 11859; // 12 +static const uint64_t SH_FLD_L3_CAC_RD_SUE_DET_MASK = 11860; // 12 +static const uint64_t SH_FLD_L3_CAC_RD_UE_DET = 11861; // 12 +static const uint64_t SH_FLD_L3_CAC_RD_UE_DET_MASK = 11862; // 12 +static const uint64_t SH_FLD_L3_CAC_TYPE = 11863; // 12 +static const uint64_t SH_FLD_L3_CAC_TYPE_LEN = 11864; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 = 11865; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2_MASK = 11866; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB = 11867; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB_MASK = 11868; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 11869; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC_MASK = 11870; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB = 11871; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB_MASK = 11872; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 = 11873; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2_MASK = 11874; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB = 11875; // 12 +static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB_MASK = 11876; // 12 +static const uint64_t SH_FLD_L3_CFG = 11877; // 36 +static const uint64_t SH_FLD_L3_CFG_LEN = 11878; // 12 +static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE = 11879; // 6 +static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_EN = 11880; // 6 +static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_LEN = 11881; // 6 +static const uint64_t SH_FLD_L3_CLK_SB_SPARE0 = 11882; // 6 +static const uint64_t SH_FLD_L3_CLK_SB_STRENGTH = 11883; // 6 +static const uint64_t SH_FLD_L3_CLK_SB_STRENGTH_LEN = 11884; // 6 +static const uint64_t SH_FLD_L3_COLUMN_MD_CFG = 11885; // 12 +static const uint64_t SH_FLD_L3_COLUMN_MD_CFG_LEN = 11886; // 12 +static const uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG = 11887; // 12 +static const uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN = 11888; // 12 +static const uint64_t SH_FLD_L3_CP_UTIL_EN_DC = 11889; // 12 +static const uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL = 11890; // 12 +static const uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL_LEN = 11891; // 12 +static const uint64_t SH_FLD_L3_CP_UTIL_SEL_DC = 11892; // 12 +static const uint64_t SH_FLD_L3_CP_UTIL_SEL_DC_LEN = 11893; // 12 +static const uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV = 11894; // 12 +static const uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN = 11895; // 12 +static const uint64_t SH_FLD_L3_DIR_ADDR = 11896; // 24 +static const uint64_t SH_FLD_L3_DIR_ADDR_LEN = 11897; // 24 +static const uint64_t SH_FLD_L3_DIR_RD_CE_DET = 11898; // 12 +static const uint64_t SH_FLD_L3_DIR_RD_CE_DET_MASK = 11899; // 12 +static const uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR = 11900; // 12 +static const uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR_MASK = 11901; // 12 +static const uint64_t SH_FLD_L3_DIR_RD_UE_DET = 11902; // 12 +static const uint64_t SH_FLD_L3_DIR_RD_UE_DET_MASK = 11903; // 12 +static const uint64_t SH_FLD_L3_DIR_TYPE = 11904; // 12 +static const uint64_t SH_FLD_L3_DISABLED_CFG = 11905; // 12 +static const uint64_t SH_FLD_L3_DMAP_CI_EN_CFG = 11906; // 12 +static const uint64_t SH_FLD_L3_DRAM_ERROR = 11907; // 12 +static const uint64_t SH_FLD_L3_DRAM_ERROR_MASK = 11908; // 12 +static const uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL = 11909; // 12 +static const uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL_MASK = 11910; // 12 +static const uint64_t SH_FLD_L3_DW = 11911; // 12 +static const uint64_t SH_FLD_L3_DW_LEN = 11912; // 12 +static const uint64_t SH_FLD_L3_DYN_LCO_BLK_DIS_CFG = 11913; // 12 +static const uint64_t SH_FLD_L3_EDRAM_PGATE_ERR = 11914; // 6 +static const uint64_t SH_FLD_L3_EDRAM_SEQ_ERR = 11915; // 6 +static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL = 11916; // 6 +static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN = 11917; // 6 +static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE = 11918; // 6 +static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE_LEN = 11919; // 6 +static const uint64_t SH_FLD_L3_EX0_EDRAM_UNLOCKED = 11920; // 6 +static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL = 11921; // 6 +static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN = 11922; // 6 +static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE = 11923; // 6 +static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE_LEN = 11924; // 6 +static const uint64_t SH_FLD_L3_EX1_EDRAM_UNLOCKED = 11925; // 6 +static const uint64_t SH_FLD_L3_FIR_SPARE1_MASK = 11926; // 12 +static const uint64_t SH_FLD_L3_FIR_SPARE2_MASK = 11927; // 12 +static const uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV = 11928; // 12 +static const uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN = 11929; // 12 +static const uint64_t SH_FLD_L3_HW_CONTROL_ERR = 11930; // 12 +static const uint64_t SH_FLD_L3_HW_CONTROL_ERR_MASK = 11931; // 12 +static const uint64_t SH_FLD_L3_INCDECFSM_STATE_HISTORY_Q = 11932; // 6 +static const uint64_t SH_FLD_L3_INCDECFSM_STATE_HISTORY_Q_LEN = 11933; // 6 +static const uint64_t SH_FLD_L3_LCO_ADDR_TGT_ENABLE = 11934; // 12 +static const uint64_t SH_FLD_L3_LCO_ENABLE_CFG = 11935; // 12 +static const uint64_t SH_FLD_L3_LCO_RTY_LIMIT_DISABLE = 11936; // 12 +static const uint64_t SH_FLD_L3_LCO_TARGET_GROUP = 11937; // 12 +static const uint64_t SH_FLD_L3_LCO_TARGET_ID = 11938; // 12 +static const uint64_t SH_FLD_L3_LCO_TARGET_ID_LEN = 11939; // 12 +static const uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS = 11940; // 12 +static const uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS_LEN = 11941; // 12 +static const uint64_t SH_FLD_L3_LEN = 11942; // 24 +static const uint64_t SH_FLD_L3_LINE_DEL_CE_DONE = 11943; // 12 +static const uint64_t SH_FLD_L3_LINE_DEL_CE_DONE_MASK = 11944; // 12 +static const uint64_t SH_FLD_L3_LINE_DEL_ON_ALL_CE = 11945; // 24 +static const uint64_t SH_FLD_L3_LINE_DEL_ON_NEXT_CE = 11946; // 24 +static const uint64_t SH_FLD_L3_LRU_ERROR = 11947; // 12 +static const uint64_t SH_FLD_L3_LRU_ERROR_MASK = 11948; // 12 +static const uint64_t SH_FLD_L3_LRU_INVAL_CNT = 11949; // 12 +static const uint64_t SH_FLD_L3_LRU_INVAL_CNT_MASK = 11950; // 12 +static const uint64_t SH_FLD_L3_MACH_HANG_DETECTED = 11951; // 12 +static const uint64_t SH_FLD_L3_MACH_HANG_DETECTED_MASK = 11952; // 12 +static const uint64_t SH_FLD_L3_MEMBER = 11953; // 24 +static const uint64_t SH_FLD_L3_MEMBER_LEN = 11954; // 24 +static const uint64_t SH_FLD_L3_NO_ALLOCATE_ACTIVE = 11955; // 12 +static const uint64_t SH_FLD_L3_NO_ALLOCATE_EN = 11956; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_RD_ACK_DEAD = 11957; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_RD_ACK_DEAD_MASK = 11958; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_RD_ADDR_ERR = 11959; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_RD_ADDR_ERR_MASK = 11960; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_WR_ACK_DEAD = 11961; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_WR_ACK_DEAD_MASK = 11962; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_WR_ADDR_ERR = 11963; // 12 +static const uint64_t SH_FLD_L3_PB_MAST_WR_ADDR_ERR_MASK = 11964; // 12 +static const uint64_t SH_FLD_L3_PDLYFSM_STATE_HISTORY_Q = 11965; // 6 +static const uint64_t SH_FLD_L3_PDLYFSM_STATE_HISTORY_Q_LEN = 11966; // 6 +static const uint64_t SH_FLD_L3_PHYP_PURGE_RESERVED_1 = 11967; // 12 +static const uint64_t SH_FLD_L3_PHYP_PURGE_RESERVED_1_LEN = 11968; // 12 +static const uint64_t SH_FLD_L3_PHYP_PURGE_RESERVED_2 = 11969; // 12 +static const uint64_t SH_FLD_L3_PHYP_PURGE_RESERVED_2_LEN = 11970; // 12 +static const uint64_t SH_FLD_L3_PPE_RD_CE_DET = 11971; // 12 +static const uint64_t SH_FLD_L3_PPE_RD_CE_DET_MASK = 11972; // 12 +static const uint64_t SH_FLD_L3_PPE_RD_SUE_DET = 11973; // 12 +static const uint64_t SH_FLD_L3_PPE_RD_SUE_DET_MASK = 11974; // 12 +static const uint64_t SH_FLD_L3_PPE_RD_UE_DET = 11975; // 12 +static const uint64_t SH_FLD_L3_PPE_RD_UE_DET_MASK = 11976; // 12 +static const uint64_t SH_FLD_L3_PRD_PURGE_RESERVED_1 = 11977; // 12 +static const uint64_t SH_FLD_L3_PRD_PURGE_RESERVED_1_LEN = 11978; // 12 +static const uint64_t SH_FLD_L3_PRD_PURGE_RESERVED_2 = 11979; // 12 +static const uint64_t SH_FLD_L3_PRD_PURGE_RESERVED_2_LEN = 11980; // 12 +static const uint64_t SH_FLD_L3_RA = 11981; // 12 +static const uint64_t SH_FLD_L3_RA_LEN = 11982; // 12 +static const uint64_t SH_FLD_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR = 11983; // 12 +static const uint64_t SH_FLD_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR_MASK = 11984; // 12 +static const uint64_t SH_FLD_L3_RDSN_LINEDEL_UE_EN = 11985; // 12 +static const uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR = 11986; // 12 +static const uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR_MASK = 11987; // 12 +static const uint64_t SH_FLD_L3_REQ = 11988; // 36 +static const uint64_t SH_FLD_L3_SCOM_CINJ_LCO_DIS = 11989; // 12 +static const uint64_t SH_FLD_L3_SCOM_INIT = 11990; // 12 +static const uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE = 11991; // 12 +static const uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR = 11992; // 12 +static const uint64_t SH_FLD_L3_SCOM_QUIESCE_REFRESH = 11993; // 12 +static const uint64_t SH_FLD_L3_SINGLE_CAC = 11994; // 12 +static const uint64_t SH_FLD_L3_SINGLE_DIR = 11995; // 12 +static const uint64_t SH_FLD_L3_SINGLE_LRU = 11996; // 12 +static const uint64_t SH_FLD_L3_SNP_CACHE_INHIBIT_ERR = 11997; // 12 +static const uint64_t SH_FLD_L3_SNP_CACHE_INHIBIT_ERR_MASK = 11998; // 12 +static const uint64_t SH_FLD_L3_SOLID_CAC = 11999; // 12 +static const uint64_t SH_FLD_L3_SOLID_DIR = 12000; // 12 +static const uint64_t SH_FLD_L3_SOLID_LRU = 12001; // 12 +static const uint64_t SH_FLD_L3_SPARE1 = 12002; // 12 +static const uint64_t SH_FLD_L3_SPARE2 = 12003; // 12 +static const uint64_t SH_FLD_L3_SPARE3 = 12004; // 24 +static const uint64_t SH_FLD_L3_SPARE5 = 12005; // 12 +static const uint64_t SH_FLD_L3_SPARE6 = 12006; // 12 +static const uint64_t SH_FLD_L3_SPARE7 = 12007; // 12 +static const uint64_t SH_FLD_L3_STOPPED = 12008; // 1 +static const uint64_t SH_FLD_L3_STOPPED_LEN = 12009; // 1 +static const uint64_t SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL = 12010; // 12 +static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR = 12011; // 12 +static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN = 12012; // 12 +static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR = 12013; // 12 +static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN = 12014; // 12 +static const uint64_t SH_FLD_L3_TTYPE = 12015; // 24 +static const uint64_t SH_FLD_L3_TTYPE_LEN = 12016; // 24 +static const uint64_t SH_FLD_L3_UTIL_MON_BITS = 12017; // 12 +static const uint64_t SH_FLD_L3_UTIL_MON_BITS_LEN = 12018; // 12 +static const uint64_t SH_FLD_L3_VAL = 12019; // 12 +static const uint64_t SH_FLD_LANE00 = 12020; // 4 +static const uint64_t SH_FLD_LANE00_LEN = 12021; // 4 +static const uint64_t SH_FLD_LANE01 = 12022; // 4 +static const uint64_t SH_FLD_LANE01_LEN = 12023; // 4 +static const uint64_t SH_FLD_LANE02 = 12024; // 4 +static const uint64_t SH_FLD_LANE02_LEN = 12025; // 4 +static const uint64_t SH_FLD_LANE03 = 12026; // 4 +static const uint64_t SH_FLD_LANE03_LEN = 12027; // 4 +static const uint64_t SH_FLD_LANE04 = 12028; // 4 +static const uint64_t SH_FLD_LANE04_LEN = 12029; // 4 +static const uint64_t SH_FLD_LANE05 = 12030; // 4 +static const uint64_t SH_FLD_LANE05_LEN = 12031; // 4 +static const uint64_t SH_FLD_LANE06 = 12032; // 4 +static const uint64_t SH_FLD_LANE06_LEN = 12033; // 4 +static const uint64_t SH_FLD_LANE07 = 12034; // 4 +static const uint64_t SH_FLD_LANE07_LEN = 12035; // 4 +static const uint64_t SH_FLD_LANE08 = 12036; // 4 +static const uint64_t SH_FLD_LANE08_LEN = 12037; // 4 +static const uint64_t SH_FLD_LANE09 = 12038; // 4 +static const uint64_t SH_FLD_LANE09_LEN = 12039; // 4 +static const uint64_t SH_FLD_LANE10 = 12040; // 4 +static const uint64_t SH_FLD_LANE10_LEN = 12041; // 4 +static const uint64_t SH_FLD_LANE11 = 12042; // 4 +static const uint64_t SH_FLD_LANE11_LEN = 12043; // 4 +static const uint64_t SH_FLD_LANE_ANA_PDWN = 12044; // 120 +static const uint64_t SH_FLD_LANE_BAD_VEC_0_15 = 12045; // 4 +static const uint64_t SH_FLD_LANE_BAD_VEC_0_15_LEN = 12046; // 4 +static const uint64_t SH_FLD_LANE_BAD_VEC_16_23 = 12047; // 4 +static const uint64_t SH_FLD_LANE_BAD_VEC_16_23_LEN = 12048; // 4 +static const uint64_t SH_FLD_LANE_BIST_ACTVITY_DET = 12049; // 116 +static const uint64_t SH_FLD_LANE_BIST_ERR = 12050; // 116 +static const uint64_t SH_FLD_LANE_DIG_PDWN = 12051; // 120 +static const uint64_t SH_FLD_LANE_DISABLED = 12052; // 48 +static const uint64_t SH_FLD_LANE_DISABLED_VEC_0_15 = 12053; // 8 +static const uint64_t SH_FLD_LANE_DISABLED_VEC_0_15_LEN = 12054; // 8 +static const uint64_t SH_FLD_LANE_DISABLED_VEC_16_23 = 12055; // 8 +static const uint64_t SH_FLD_LANE_DISABLED_VEC_16_23_LEN = 12056; // 8 +static const uint64_t SH_FLD_LANE_INVALID = 12057; // 72 +static const uint64_t SH_FLD_LANE_INVERT = 12058; // 190 +static const uint64_t SH_FLD_LANE_PDWN = 12059; // 116 +static const uint64_t SH_FLD_LANE_QUIESCE = 12060; // 117 +static const uint64_t SH_FLD_LANE_QUIESCE_LEN = 12061; // 117 +static const uint64_t SH_FLD_LANE_SCRAMBLE_DISABLE = 12062; // 140 +static const uint64_t SH_FLD_LARGER_DROOP_EVENT_CTR = 12063; // 12 +static const uint64_t SH_FLD_LARGER_DROOP_EVENT_CTR_LEN = 12064; // 12 +static const uint64_t SH_FLD_LARGE_DROOP_ERR = 12065; // 12 +static const uint64_t SH_FLD_LARGE_EVENT_PROFILE_CTR = 12066; // 12 +static const uint64_t SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN = 12067; // 12 +static const uint64_t SH_FLD_LARGE_EVENT_THRESHOLD = 12068; // 12 +static const uint64_t SH_FLD_LARGE_EVENT_THRESHOLD_LEN = 12069; // 12 +static const uint64_t SH_FLD_LAST_BANK = 12070; // 162 +static const uint64_t SH_FLD_LAST_BANK_LEN = 12071; // 162 +static const uint64_t SH_FLD_LAST_BANK_VALID = 12072; // 162 +static const uint64_t SH_FLD_LAST_DISPATCH_ACCUMULATION_MODE = 12073; // 24 +static const uint64_t SH_FLD_LAST_OPCG_MODE = 12074; // 43 +static const uint64_t SH_FLD_LAST_OPCG_MODE_LEN = 12075; // 43 +static const uint64_t SH_FLD_LATCANCEL = 12076; // 15 +static const uint64_t SH_FLD_LATCANCEL_LEN = 12077; // 15 +static const uint64_t SH_FLD_LATENCY = 12078; // 6 +static const uint64_t SH_FLD_LATENCY_LEN = 12079; // 6 +static const uint64_t SH_FLD_LATE_LAUNCH_PRIMARY = 12080; // 1 +static const uint64_t SH_FLD_LATE_LAUNCH_SECONDARY = 12081; // 1 +static const uint64_t SH_FLD_LATFINISH = 12082; // 15 +static const uint64_t SH_FLD_LATFINISH_LEN = 12083; // 15 +static const uint64_t SH_FLD_LATSTART = 12084; // 15 +static const uint64_t SH_FLD_LATSTART_LEN = 12085; // 15 +static const uint64_t SH_FLD_LAT_THRESHA = 12086; // 8 +static const uint64_t SH_FLD_LAT_THRESHA_LEN = 12087; // 8 +static const uint64_t SH_FLD_LAT_THRESHB = 12088; // 8 +static const uint64_t SH_FLD_LAT_THRESHB_LEN = 12089; // 8 +static const uint64_t SH_FLD_LAT_THRESHC = 12090; // 8 +static const uint64_t SH_FLD_LAT_THRESHC_LEN = 12091; // 8 +static const uint64_t SH_FLD_LBIST = 12092; // 43 +static const uint64_t SH_FLD_LBIST_SKITTER_CTL = 12093; // 43 +static const uint64_t SH_FLD_LBIST_SKITTER_CTL_LEN = 12094; // 43 +static const uint64_t SH_FLD_LBUS_BUSY = 12095; // 2 +static const uint64_t SH_FLD_LBUS_CLOCK_DIVIDER = 12096; // 2 +static const uint64_t SH_FLD_LBUS_CLOCK_DIVIDER_LEN = 12097; // 2 +static const uint64_t SH_FLD_LBUS_GNT = 12098; // 2 +static const uint64_t SH_FLD_LBUS_GNT_LEN = 12099; // 2 +static const uint64_t SH_FLD_LBUS_LOCK = 12100; // 2 +static const uint64_t SH_FLD_LBUS_PARITY_ERR1_0 = 12101; // 12 +static const uint64_t SH_FLD_LBUS_PARITY_ERR1_1 = 12102; // 12 +static const uint64_t SH_FLD_LBUS_PARITY_ERR1_2 = 12103; // 12 +static const uint64_t SH_FLD_LBUS_PARITY_ERR1_3 = 12104; // 12 +static const uint64_t SH_FLD_LBUS_PARITY_ERROR_0 = 12105; // 4 +static const uint64_t SH_FLD_LBUS_PARITY_ERROR_1 = 12106; // 2 +static const uint64_t SH_FLD_LBUS_PARITY_ERROR_2 = 12107; // 2 +static const uint64_t SH_FLD_LBUS_PARITY_ERROR_3 = 12108; // 2 +static const uint64_t SH_FLD_LBUS_REQ_SYNC_FR_LEFT = 12109; // 2 +static const uint64_t SH_FLD_LBUS_REQ_SYNC_FR_RIGHT = 12110; // 2 +static const uint64_t SH_FLD_LCK_STATUS_PARITY_ERROR = 12111; // 3 +static const uint64_t SH_FLD_LCL_CLK_GATE_CTRL = 12112; // 72 +static const uint64_t SH_FLD_LCL_CLK_GATE_CTRL_LEN = 12113; // 72 +static const uint64_t SH_FLD_LCL_FIRST_GRPSCAN_ENA = 12114; // 1 +static const uint64_t SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA = 12115; // 1 +static const uint64_t SH_FLD_LCO_CRED_MASK = 12116; // 1 +static const uint64_t SH_FLD_LCO_CRED_MASK_LEN = 12117; // 1 +static const uint64_t SH_FLD_LCO_TARG_CONFIG = 12118; // 1 +static const uint64_t SH_FLD_LCO_TARG_CONFIG_LEN = 12119; // 1 +static const uint64_t SH_FLD_LCO_TARG_MIN = 12120; // 1 +static const uint64_t SH_FLD_LCO_TARG_MIN_LEN = 12121; // 1 +static const uint64_t SH_FLD_LD = 12122; // 192 +static const uint64_t SH_FLD_LDQ_DATA_HANG = 12123; // 1 +static const uint64_t SH_FLD_LDQ_EQD_MAX_0_4 = 12124; // 1 +static const uint64_t SH_FLD_LDQ_EQD_MAX_0_4_LEN = 12125; // 1 +static const uint64_t SH_FLD_LDQ_EQD_MIN_0_4 = 12126; // 1 +static const uint64_t SH_FLD_LDQ_EQD_MIN_0_4_LEN = 12127; // 1 +static const uint64_t SH_FLD_LDQ_FSM_PERR = 12128; // 1 +static const uint64_t SH_FLD_LDQ_IVE_MAX_0_4 = 12129; // 1 +static const uint64_t SH_FLD_LDQ_IVE_MAX_0_4_LEN = 12130; // 1 +static const uint64_t SH_FLD_LDQ_IVE_MIN_0_4 = 12131; // 1 +static const uint64_t SH_FLD_LDQ_IVE_MIN_0_4_LEN = 12132; // 1 +static const uint64_t SH_FLD_LDQ_REG_MAX_0_4 = 12133; // 1 +static const uint64_t SH_FLD_LDQ_REG_MAX_0_4_LEN = 12134; // 1 +static const uint64_t SH_FLD_LDQ_REG_MIN_0_4 = 12135; // 1 +static const uint64_t SH_FLD_LDQ_REG_MIN_0_4_LEN = 12136; // 1 +static const uint64_t SH_FLD_LDQ_REG_ORDER_ALL = 12137; // 1 +static const uint64_t SH_FLD_LDQ_THR_MAX_0_4 = 12138; // 1 +static const uint64_t SH_FLD_LDQ_THR_MAX_0_4_LEN = 12139; // 1 +static const uint64_t SH_FLD_LDQ_THR_MIN_0_4 = 12140; // 1 +static const uint64_t SH_FLD_LDQ_THR_MIN_0_4_LEN = 12141; // 1 +static const uint64_t SH_FLD_LDQ_VPC_MAX_0_4 = 12142; // 1 +static const uint64_t SH_FLD_LDQ_VPC_MAX_0_4_LEN = 12143; // 1 +static const uint64_t SH_FLD_LDQ_VPC_MIN_0_4 = 12144; // 1 +static const uint64_t SH_FLD_LDQ_VPC_MIN_0_4_LEN = 12145; // 1 +static const uint64_t SH_FLD_LD_ACK_DEAD = 12146; // 12 +static const uint64_t SH_FLD_LD_ADDR_ERR = 12147; // 12 +static const uint64_t SH_FLD_LD_CLASS_ACK_DEAD = 12148; // 2 +static const uint64_t SH_FLD_LD_CLASS_ARE_ERROR = 12149; // 2 +static const uint64_t SH_FLD_LD_CLASS_CMD_ADDR_ERR = 12150; // 4 +static const uint64_t SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 12151; // 4 +static const uint64_t SH_FLD_LD_ECC_CE = 12152; // 1 +static const uint64_t SH_FLD_LD_ECC_UE = 12153; // 1 +static const uint64_t SH_FLD_LD_UNLD_DLY = 12154; // 1 +static const uint64_t SH_FLD_LD_UNLD_DLY_LEN = 12155; // 1 +static const uint64_t SH_FLD_LE = 12156; // 96 +static const uint64_t SH_FLD_LEM_FIR_INTERNAL_PARITY_ERROR = 12157; // 24 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_0 = 12158; // 2 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_0_LEN = 12159; // 2 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_1 = 12160; // 1 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_1_LEN = 12161; // 1 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_2 = 12162; // 1 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_2_LEN = 12163; // 1 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_3 = 12164; // 1 +static const uint64_t SH_FLD_LENGTH_IN_BYTES_3_LEN = 12165; // 1 +static const uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N = 12166; // 96 +static const uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN = 12167; // 96 +static const uint64_t SH_FLD_LFIR_IN = 12168; // 43 +static const uint64_t SH_FLD_LFIR_IN_LEN = 12169; // 43 +static const uint64_t SH_FLD_LFIR_RECOV_ERR = 12170; // 43 +static const uint64_t SH_FLD_LFIR_WOF = 12171; // 1 +static const uint64_t SH_FLD_LFIR_WOF_LEN = 12172; // 1 +static const uint64_t SH_FLD_LFREQ = 12173; // 1 +static const uint64_t SH_FLD_LFREQ0 = 12174; // 24 +static const uint64_t SH_FLD_LFREQ0_LEN = 12175; // 24 +static const uint64_t SH_FLD_LFREQ1 = 12176; // 24 +static const uint64_t SH_FLD_LFREQ1_LEN = 12177; // 24 +static const uint64_t SH_FLD_LFREQ_LEN = 12178; // 1 +static const uint64_t SH_FLD_LFSR = 12179; // 5 +static const uint64_t SH_FLD_LFSR_ARB_MODE = 12180; // 3 +static const uint64_t SH_FLD_LFSR_DIS = 12181; // 1 +static const uint64_t SH_FLD_LFSR_FAIRNESS_MASK = 12182; // 1 +static const uint64_t SH_FLD_LFSR_FAIRNESS_MASK_LEN = 12183; // 1 +static const uint64_t SH_FLD_LFSR_LEN = 12184; // 5 +static const uint64_t SH_FLD_LIMIT = 12185; // 2 +static const uint64_t SH_FLD_LIMIT_LEN = 12186; // 2 +static const uint64_t SH_FLD_LIM_PS = 12187; // 1 +static const uint64_t SH_FLD_LINEAR_WINDOW_BAR = 12188; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_BAR_LEN = 12189; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_BASE = 12190; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_BASE_LEN = 12191; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_ENABLE = 12192; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_MASK = 12193; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_MASK_LEN = 12194; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_REGION = 12195; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_REGION_LEN = 12196; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_SCRESP = 12197; // 4 +static const uint64_t SH_FLD_LINEAR_WINDOW_SCRESP_LEN = 12198; // 4 +static const uint64_t SH_FLD_LINK00_HI = 12199; // 2 +static const uint64_t SH_FLD_LINK00_HI_LEN = 12200; // 2 +static const uint64_t SH_FLD_LINK00_LO = 12201; // 2 +static const uint64_t SH_FLD_LINK00_LO_LEN = 12202; // 2 +static const uint64_t SH_FLD_LINK01_CAPP_MODE = 12203; // 1 +static const uint64_t SH_FLD_LINK01_DIB_VC_LIMIT = 12204; // 2 +static const uint64_t SH_FLD_LINK01_DIB_VC_LIMIT_LEN = 12205; // 2 +static const uint64_t SH_FLD_LINK01_HI = 12206; // 2 +static const uint64_t SH_FLD_LINK01_HI_LEN = 12207; // 2 +static const uint64_t SH_FLD_LINK01_HRB_INIT_STATE = 12208; // 1 +static const uint64_t SH_FLD_LINK01_LO = 12209; // 2 +static const uint64_t SH_FLD_LINK01_LO_LEN = 12210; // 2 +static const uint64_t SH_FLD_LINK02_HI = 12211; // 2 +static const uint64_t SH_FLD_LINK02_HI_LEN = 12212; // 2 +static const uint64_t SH_FLD_LINK02_LO = 12213; // 2 +static const uint64_t SH_FLD_LINK02_LO_LEN = 12214; // 2 +static const uint64_t SH_FLD_LINK03_HI = 12215; // 2 +static const uint64_t SH_FLD_LINK03_HI_LEN = 12216; // 2 +static const uint64_t SH_FLD_LINK03_LO = 12217; // 2 +static const uint64_t SH_FLD_LINK03_LO_LEN = 12218; // 2 +static const uint64_t SH_FLD_LINK04_HI = 12219; // 2 +static const uint64_t SH_FLD_LINK04_HI_LEN = 12220; // 2 +static const uint64_t SH_FLD_LINK04_LO = 12221; // 2 +static const uint64_t SH_FLD_LINK04_LO_LEN = 12222; // 2 +static const uint64_t SH_FLD_LINK05_HI = 12223; // 2 +static const uint64_t SH_FLD_LINK05_HI_LEN = 12224; // 2 +static const uint64_t SH_FLD_LINK05_LO = 12225; // 2 +static const uint64_t SH_FLD_LINK05_LO_LEN = 12226; // 2 +static const uint64_t SH_FLD_LINK06_HI = 12227; // 1 +static const uint64_t SH_FLD_LINK06_HI_LEN = 12228; // 1 +static const uint64_t SH_FLD_LINK06_LO = 12229; // 1 +static const uint64_t SH_FLD_LINK06_LO_LEN = 12230; // 1 +static const uint64_t SH_FLD_LINK07_HI = 12231; // 1 +static const uint64_t SH_FLD_LINK07_HI_LEN = 12232; // 1 +static const uint64_t SH_FLD_LINK07_LO = 12233; // 1 +static const uint64_t SH_FLD_LINK07_LO_LEN = 12234; // 1 +static const uint64_t SH_FLD_LINK0_ACK_QUEUE_OVERFLOW = 12235; // 4 +static const uint64_t SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW = 12236; // 4 +static const uint64_t SH_FLD_LINK0_COMMAND = 12237; // 5 +static const uint64_t SH_FLD_LINK0_COMMAND_LEN = 12238; // 5 +static const uint64_t SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR = 12239; // 10 +static const uint64_t SH_FLD_LINK0_CRC_ERROR = 12240; // 10 +static const uint64_t SH_FLD_LINK0_CURRENT_STATE = 12241; // 5 +static const uint64_t SH_FLD_LINK0_CURRENT_STATE_LEN = 12242; // 5 +static const uint64_t SH_FLD_LINK0_DESKEW_ERROR = 12243; // 4 +static const uint64_t SH_FLD_LINK0_DESKEW_OVERFLOW = 12244; // 4 +static const uint64_t SH_FLD_LINK0_DOB_LIMIT = 12245; // 1 +static const uint64_t SH_FLD_LINK0_DOB_LIMIT_LEN = 12246; // 1 +static const uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT = 12247; // 2 +static const uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT_LEN = 12248; // 2 +static const uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT = 12249; // 2 +static const uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT_LEN = 12250; // 2 +static const uint64_t SH_FLD_LINK0_ELEVEN_LANE_SHIFT = 12251; // 2 +static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND = 12252; // 5 +static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LANES = 12253; // 5 +static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN = 12254; // 5 +static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LEN = 12255; // 5 +static const uint64_t SH_FLD_LINK0_HOLD_PATT_A = 12256; // 2 +static const uint64_t SH_FLD_LINK0_HOLD_PATT_B = 12257; // 2 +static const uint64_t SH_FLD_LINK0_IGNORE_FENCE = 12258; // 2 +static const uint64_t SH_FLD_LINK0_IGNORE_PHY = 12259; // 2 +static const uint64_t SH_FLD_LINK0_INTERNAL_ERROR = 12260; // 10 +static const uint64_t SH_FLD_LINK0_INVALID_BLOCK = 12261; // 4 +static const uint64_t SH_FLD_LINK0_LOSS_BLOCK_ALIGN = 12262; // 4 +static const uint64_t SH_FLD_LINK0_MAX_PKT_TIMER = 12263; // 5 +static const uint64_t SH_FLD_LINK0_MAX_PKT_TIMER_LEN = 12264; // 5 +static const uint64_t SH_FLD_LINK0_NAK_RECEIVED = 12265; // 10 +static const uint64_t SH_FLD_LINK0_NPU_ERROR = 12266; // 4 +static const uint64_t SH_FLD_LINK0_NUM_REPLAY = 12267; // 4 +static const uint64_t SH_FLD_LINK0_OLL_ENABLED = 12268; // 2 +static const uint64_t SH_FLD_LINK0_OPTICS_IRQ = 12269; // 2 +static const uint64_t SH_FLD_LINK0_OPTICS_RST_B = 12270; // 2 +static const uint64_t SH_FLD_LINK0_OP_IRQ = 12271; // 4 +static const uint64_t SH_FLD_LINK0_PHY_TRAINING = 12272; // 2 +static const uint64_t SH_FLD_LINK0_PRBS_SELECT_ERROR = 12273; // 4 +static const uint64_t SH_FLD_LINK0_PRIOR_STATE = 12274; // 5 +static const uint64_t SH_FLD_LINK0_PRIOR_STATE_LEN = 12275; // 5 +static const uint64_t SH_FLD_LINK0_REPLAY_BUFFER_FULL = 12276; // 10 +static const uint64_t SH_FLD_LINK0_REPLAY_THRESHOLD = 12277; // 10 +static const uint64_t SH_FLD_LINK0_RETRAIN_THRESHOLD = 12278; // 4 +static const uint64_t SH_FLD_LINK0_ROUND_TRIP = 12279; // 5 +static const uint64_t SH_FLD_LINK0_ROUND_TRIP_LEN = 12280; // 5 +static const uint64_t SH_FLD_LINK0_ROUND_TRIP_VALID = 12281; // 5 +static const uint64_t SH_FLD_LINK0_RUN_LANE_DISABLE = 12282; // 2 +static const uint64_t SH_FLD_LINK0_RUN_LANE_OVERRIDE = 12283; // 2 +static const uint64_t SH_FLD_LINK0_RX_LANE_SWAP = 12284; // 2 +static const uint64_t SH_FLD_LINK0_SL_ECC_CORRECTABLE = 12285; // 10 +static const uint64_t SH_FLD_LINK0_SL_ECC_THRESHOLD = 12286; // 10 +static const uint64_t SH_FLD_LINK0_SL_ECC_UE = 12287; // 10 +static const uint64_t SH_FLD_LINK0_SPARE = 12288; // 1 +static const uint64_t SH_FLD_LINK0_SPARE_DONE = 12289; // 10 +static const uint64_t SH_FLD_LINK0_SPARE_LEN = 12290; // 1 +static const uint64_t SH_FLD_LINK0_STARTUP = 12291; // 5 +static const uint64_t SH_FLD_LINK0_SW_RETRAIN = 12292; // 4 +static const uint64_t SH_FLD_LINK0_TCOMPLETE_BAD = 12293; // 10 +static const uint64_t SH_FLD_LINK0_TOD_LATENCY = 12294; // 5 +static const uint64_t SH_FLD_LINK0_TOD_LATENCY_LEN = 12295; // 5 +static const uint64_t SH_FLD_LINK0_TOO_MANY_CRC_ERRORS = 12296; // 10 +static const uint64_t SH_FLD_LINK0_TRAINED = 12297; // 10 +static const uint64_t SH_FLD_LINK0_TRAINING = 12298; // 2 +static const uint64_t SH_FLD_LINK0_TRAINING_FAILED = 12299; // 10 +static const uint64_t SH_FLD_LINK0_TRAINING_SET_RECEIVED = 12300; // 4 +static const uint64_t SH_FLD_LINK0_TX_LANE_SWAP = 12301; // 2 +static const uint64_t SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR = 12302; // 10 +static const uint64_t SH_FLD_LINK0_UNRECOVERABLE_ERROR = 12303; // 10 +static const uint64_t SH_FLD_LINK1_ACK_QUEUE_OVERFLOW = 12304; // 4 +static const uint64_t SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW = 12305; // 4 +static const uint64_t SH_FLD_LINK1_COMMAND = 12306; // 5 +static const uint64_t SH_FLD_LINK1_COMMAND_LEN = 12307; // 5 +static const uint64_t SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR = 12308; // 10 +static const uint64_t SH_FLD_LINK1_CRC_ERROR = 12309; // 10 +static const uint64_t SH_FLD_LINK1_CURRENT_STATE = 12310; // 5 +static const uint64_t SH_FLD_LINK1_CURRENT_STATE_LEN = 12311; // 5 +static const uint64_t SH_FLD_LINK1_DESKEW_ERROR = 12312; // 4 +static const uint64_t SH_FLD_LINK1_DESKEW_OVERFLOW = 12313; // 4 +static const uint64_t SH_FLD_LINK1_DOB_LIMIT = 12314; // 1 +static const uint64_t SH_FLD_LINK1_DOB_LIMIT_LEN = 12315; // 1 +static const uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT = 12316; // 2 +static const uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT_LEN = 12317; // 2 +static const uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT = 12318; // 2 +static const uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT_LEN = 12319; // 2 +static const uint64_t SH_FLD_LINK1_ELEVEN_LANE_SHIFT = 12320; // 2 +static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND = 12321; // 5 +static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LANES = 12322; // 5 +static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN = 12323; // 5 +static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LEN = 12324; // 5 +static const uint64_t SH_FLD_LINK1_HOLD_PATT_A = 12325; // 2 +static const uint64_t SH_FLD_LINK1_HOLD_PATT_B = 12326; // 2 +static const uint64_t SH_FLD_LINK1_IGNORE_FENCE = 12327; // 2 +static const uint64_t SH_FLD_LINK1_IGNORE_PHY = 12328; // 2 +static const uint64_t SH_FLD_LINK1_INTERNAL_ERROR = 12329; // 10 +static const uint64_t SH_FLD_LINK1_INVALID_BLOCK = 12330; // 4 +static const uint64_t SH_FLD_LINK1_LOSS_BLOCK_ALIGN = 12331; // 4 +static const uint64_t SH_FLD_LINK1_MAX_PKT_TIMER = 12332; // 5 +static const uint64_t SH_FLD_LINK1_MAX_PKT_TIMER_LEN = 12333; // 5 +static const uint64_t SH_FLD_LINK1_NAK_RECEIVED = 12334; // 10 +static const uint64_t SH_FLD_LINK1_NPU_ERROR = 12335; // 4 +static const uint64_t SH_FLD_LINK1_NUM_REPLAY = 12336; // 4 +static const uint64_t SH_FLD_LINK1_OLL_ENABLED = 12337; // 2 +static const uint64_t SH_FLD_LINK1_OPTICS_IRQ = 12338; // 2 +static const uint64_t SH_FLD_LINK1_OPTICS_RST_B = 12339; // 2 +static const uint64_t SH_FLD_LINK1_OP_IRQ = 12340; // 4 +static const uint64_t SH_FLD_LINK1_PHY_TRAINING = 12341; // 2 +static const uint64_t SH_FLD_LINK1_PRBS_SELECT_ERROR = 12342; // 4 +static const uint64_t SH_FLD_LINK1_PRIOR_STATE = 12343; // 5 +static const uint64_t SH_FLD_LINK1_PRIOR_STATE_LEN = 12344; // 5 +static const uint64_t SH_FLD_LINK1_REPLAY_BUFFER_FULL = 12345; // 10 +static const uint64_t SH_FLD_LINK1_REPLAY_THRESHOLD = 12346; // 10 +static const uint64_t SH_FLD_LINK1_RETRAIN_THRESHOLD = 12347; // 4 +static const uint64_t SH_FLD_LINK1_ROUND_TRIP = 12348; // 5 +static const uint64_t SH_FLD_LINK1_ROUND_TRIP_LEN = 12349; // 5 +static const uint64_t SH_FLD_LINK1_ROUND_TRIP_VALID = 12350; // 5 +static const uint64_t SH_FLD_LINK1_RUN_LANE_DISABLE = 12351; // 2 +static const uint64_t SH_FLD_LINK1_RUN_LANE_OVERRIDE = 12352; // 2 +static const uint64_t SH_FLD_LINK1_RX_LANE_SWAP = 12353; // 2 +static const uint64_t SH_FLD_LINK1_SL_ECC_CORRECTABLE = 12354; // 10 +static const uint64_t SH_FLD_LINK1_SL_ECC_THRESHOLD = 12355; // 10 +static const uint64_t SH_FLD_LINK1_SL_ECC_UE = 12356; // 10 +static const uint64_t SH_FLD_LINK1_SPARE = 12357; // 1 +static const uint64_t SH_FLD_LINK1_SPARE_DONE = 12358; // 10 +static const uint64_t SH_FLD_LINK1_SPARE_LEN = 12359; // 1 +static const uint64_t SH_FLD_LINK1_STARTUP = 12360; // 5 +static const uint64_t SH_FLD_LINK1_SW_RETRAIN = 12361; // 4 +static const uint64_t SH_FLD_LINK1_TCOMPLETE_BAD = 12362; // 10 +static const uint64_t SH_FLD_LINK1_TOD_LATENCY = 12363; // 5 +static const uint64_t SH_FLD_LINK1_TOD_LATENCY_LEN = 12364; // 5 +static const uint64_t SH_FLD_LINK1_TOO_MANY_CRC_ERRORS = 12365; // 10 +static const uint64_t SH_FLD_LINK1_TRAINED = 12366; // 10 +static const uint64_t SH_FLD_LINK1_TRAINING = 12367; // 2 +static const uint64_t SH_FLD_LINK1_TRAINING_FAILED = 12368; // 10 +static const uint64_t SH_FLD_LINK1_TRAINING_SET_RECEIVED = 12369; // 4 +static const uint64_t SH_FLD_LINK1_TX_LANE_SWAP = 12370; // 2 +static const uint64_t SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR = 12371; // 10 +static const uint64_t SH_FLD_LINK1_UNRECOVERABLE_ERROR = 12372; // 10 +static const uint64_t SH_FLD_LINK23_DIB_VC_LIMIT = 12373; // 2 +static const uint64_t SH_FLD_LINK23_DIB_VC_LIMIT_LEN = 12374; // 2 +static const uint64_t SH_FLD_LINK2_DOB_LIMIT = 12375; // 2 +static const uint64_t SH_FLD_LINK2_DOB_LIMIT_LEN = 12376; // 2 +static const uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT = 12377; // 2 +static const uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT_LEN = 12378; // 2 +static const uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT = 12379; // 2 +static const uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT_LEN = 12380; // 2 +static const uint64_t SH_FLD_LINK3_DOB_LIMIT = 12381; // 2 +static const uint64_t SH_FLD_LINK3_DOB_LIMIT_LEN = 12382; // 2 +static const uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT = 12383; // 2 +static const uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT_LEN = 12384; // 2 +static const uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT = 12385; // 2 +static const uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT_LEN = 12386; // 2 +static const uint64_t SH_FLD_LINK45_DIB_VC_LIMIT = 12387; // 2 +static const uint64_t SH_FLD_LINK45_DIB_VC_LIMIT_LEN = 12388; // 2 +static const uint64_t SH_FLD_LINK4_DOB_LIMIT = 12389; // 2 +static const uint64_t SH_FLD_LINK4_DOB_LIMIT_LEN = 12390; // 2 +static const uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT = 12391; // 2 +static const uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT_LEN = 12392; // 2 +static const uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT = 12393; // 2 +static const uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT_LEN = 12394; // 2 +static const uint64_t SH_FLD_LINK5_DOB_LIMIT = 12395; // 2 +static const uint64_t SH_FLD_LINK5_DOB_LIMIT_LEN = 12396; // 2 +static const uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT = 12397; // 2 +static const uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT_LEN = 12398; // 2 +static const uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT = 12399; // 2 +static const uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT_LEN = 12400; // 2 +static const uint64_t SH_FLD_LINK67_CAPP_MODE = 12401; // 1 +static const uint64_t SH_FLD_LINK67_DIB_VC_LIMIT = 12402; // 1 +static const uint64_t SH_FLD_LINK67_DIB_VC_LIMIT_LEN = 12403; // 1 +static const uint64_t SH_FLD_LINK67_HRB_INIT_STATE = 12404; // 1 +static const uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT = 12405; // 1 +static const uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT_LEN = 12406; // 1 +static const uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT = 12407; // 1 +static const uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT_LEN = 12408; // 1 +static const uint64_t SH_FLD_LINK6_SPARE = 12409; // 1 +static const uint64_t SH_FLD_LINK6_SPARE_LEN = 12410; // 1 +static const uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT = 12411; // 1 +static const uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT_LEN = 12412; // 1 +static const uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT = 12413; // 1 +static const uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT_LEN = 12414; // 1 +static const uint64_t SH_FLD_LINK7_SPARE = 12415; // 1 +static const uint64_t SH_FLD_LINK7_SPARE_LEN = 12416; // 1 +static const uint64_t SH_FLD_LINKS01_TOD_ENABLE = 12417; // 1 +static const uint64_t SH_FLD_LINKS23_TOD_ENABLE = 12418; // 1 +static const uint64_t SH_FLD_LINKS45_TOD_ENABLE = 12419; // 1 +static const uint64_t SH_FLD_LINKS67_TOD_ENABLE = 12420; // 1 +static const uint64_t SH_FLD_LINKX_NPU_ERROR = 12421; // 4 +static const uint64_t SH_FLD_LINK_AVP_MODE = 12422; // 2 +static const uint64_t SH_FLD_LINK_CAP_CRC = 12423; // 10 +static const uint64_t SH_FLD_LINK_CAP_CRC_LANE = 12424; // 10 +static const uint64_t SH_FLD_LINK_CAP_CRC_LANE_LEN = 12425; // 10 +static const uint64_t SH_FLD_LINK_CAP_CRC_LEN = 12426; // 10 +static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED1 = 12427; // 6 +static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED1_LEN = 12428; // 6 +static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED2 = 12429; // 6 +static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED2_LEN = 12430; // 6 +static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED3 = 12431; // 6 +static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED3_LEN = 12432; // 6 +static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN0 = 12433; // 10 +static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN0_LEN = 12434; // 10 +static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN1 = 12435; // 10 +static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN1_LEN = 12436; // 10 +static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN2 = 12437; // 4 +static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN2_LEN = 12438; // 4 +static const uint64_t SH_FLD_LINK_CAP_VALID = 12439; // 6 +static const uint64_t SH_FLD_LINK_FAIL_DURATION = 12440; // 2 +static const uint64_t SH_FLD_LINK_FAIL_DURATION_LEN = 12441; // 2 +static const uint64_t SH_FLD_LINK_FAIL_MAX = 12442; // 2 +static const uint64_t SH_FLD_LINK_FAIL_MAX_LEN = 12443; // 2 +static const uint64_t SH_FLD_LINK_PAIR = 12444; // 5 +static const uint64_t SH_FLD_LINUX_TRIG_MODE = 12445; // 1 +static const uint64_t SH_FLD_LISTEN_TO_PULSE_DIS = 12446; // 43 +static const uint64_t SH_FLD_LNK_RSP_PKT_DISCARDED_ERRHOLD = 12447; // 2 +static const uint64_t SH_FLD_LO = 12448; // 1 +static const uint64_t SH_FLD_LOAD_CI_BUFF = 12449; // 2 +static const uint64_t SH_FLD_LOAD_RSVD_VALUES = 12450; // 8 +static const uint64_t SH_FLD_LOAD_TOD_MOD = 12451; // 98 +static const uint64_t SH_FLD_LOCALITY_4_ACCESS = 12452; // 1 +static const uint64_t SH_FLD_LOCAL_CLOCK_GATE_CONTROL = 12453; // 90 +static const uint64_t SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN = 12454; // 90 +static const uint64_t SH_FLD_LOCAL_HANG_COMP = 12455; // 4 +static const uint64_t SH_FLD_LOCAL_HANG_COMP_LEN = 12456; // 4 +static const uint64_t SH_FLD_LOCAL_HIGH_PRIORITY = 12457; // 4 +static const uint64_t SH_FLD_LOCAL_HIGH_PRIORITY_LEN = 12458; // 4 +static const uint64_t SH_FLD_LOCAL_INTERRUPT_HIGH = 12459; // 1 +static const uint64_t SH_FLD_LOCAL_INTERRUPT_PENDING = 12460; // 1 +static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE = 12461; // 5 +static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN = 12462; // 5 +static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID = 12463; // 5 +static const uint64_t SH_FLD_LOCAL_LATENCY_LONGER_LINK = 12464; // 5 +static const uint64_t SH_FLD_LOCAL_LOW_PRIORITY = 12465; // 4 +static const uint64_t SH_FLD_LOCAL_LOW_PRIORITY_LEN = 12466; // 4 +static const uint64_t SH_FLD_LOCAL_NODE_EPSILON = 12467; // 8 +static const uint64_t SH_FLD_LOCAL_NODE_EPSILON_LEN = 12468; // 8 +static const uint64_t SH_FLD_LOCAL_QUIESCE_ACHIEVED = 12469; // 1 +static const uint64_t SH_FLD_LOCK = 12470; // 59 +static const uint64_t SH_FLD_LOCKED = 12471; // 4 +static const uint64_t SH_FLD_LOCKED_FSM_RESET_ONGOING = 12472; // 1 +static const uint64_t SH_FLD_LOCKED_FSM_STATE = 12473; // 1 +static const uint64_t SH_FLD_LOCKED_FSM_STATE_LEN = 12474; // 1 +static const uint64_t SH_FLD_LOCKED_LEN = 12475; // 4 +static const uint64_t SH_FLD_LOCKED_PIBM_ADDR = 12476; // 1 +static const uint64_t SH_FLD_LOCKED_PIBM_ADDR_LEN = 12477; // 1 +static const uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS = 12478; // 1 +static const uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN = 12479; // 1 +static const uint64_t SH_FLD_LOCK_LBUS_ACCESS = 12480; // 2 +static const uint64_t SH_FLD_LOCK_LBUS_ACCESS_LEN = 12481; // 2 +static const uint64_t SH_FLD_LOCK_LEN = 12482; // 43 +static const uint64_t SH_FLD_LOCK_PCB_ON_ERR = 12483; // 12 +static const uint64_t SH_FLD_LOCK_SEL = 12484; // 6 +static const uint64_t SH_FLD_LOFF_AMP_EN = 12485; // 6 +static const uint64_t SH_FLD_LOG = 12486; // 1 +static const uint64_t SH_FLD_LOGICAL_THREAD_ID = 12487; // 24 +static const uint64_t SH_FLD_LOGICAL_THREAD_ID_LEN = 12488; // 24 +static const uint64_t SH_FLD_LOG_FULL = 12489; // 8 +static const uint64_t SH_FLD_LOG_LEN = 12490; // 1 +static const uint64_t SH_FLD_LOG_POINTER = 12491; // 8 +static const uint64_t SH_FLD_LOG_POINTER_LEN = 12492; // 8 +static const uint64_t SH_FLD_LOOP_BREAK_MODE = 12493; // 64 +static const uint64_t SH_FLD_LOOP_BREAK_MODE_LEN = 12494; // 64 +static const uint64_t SH_FLD_LOOP_COUNT = 12495; // 43 +static const uint64_t SH_FLD_LOOP_COUNT_LEN = 12496; // 43 +static const uint64_t SH_FLD_LOW = 12497; // 1 +static const uint64_t SH_FLD_LOW_IDLE_COUNT = 12498; // 8 +static const uint64_t SH_FLD_LOW_IDLE_COUNT_LEN = 12499; // 8 +static const uint64_t SH_FLD_LOW_IDLE_THRESHOLD = 12500; // 8 +static const uint64_t SH_FLD_LOW_IDLE_THRESHOLD_LEN = 12501; // 8 +static const uint64_t SH_FLD_LOW_LATENCY = 12502; // 8 +static const uint64_t SH_FLD_LOW_LEN = 12503; // 1 +static const uint64_t SH_FLD_LOW_ORDER_STEP_VALUE = 12504; // 1 +static const uint64_t SH_FLD_LOW_ORDER_STEP_VALUE_LEN = 12505; // 1 +static const uint64_t SH_FLD_LOW_PROBE_TRACE_GATE = 12506; // 8 +static const uint64_t SH_FLD_LO_ENABLE = 12507; // 2 +static const uint64_t SH_FLD_LO_FIXED_WINDOW_MODE = 12508; // 2 +static const uint64_t SH_FLD_LO_PRESCALE_MODE = 12509; // 2 +static const uint64_t SH_FLD_LO_SELECT = 12510; // 2 +static const uint64_t SH_FLD_LO_SELECT_LEN = 12511; // 2 +static const uint64_t SH_FLD_LP = 12512; // 8 +static const uint64_t SH_FLD_LPARID = 12513; // 24 +static const uint64_t SH_FLD_LPARID_LEN = 12514; // 24 +static const uint64_t SH_FLD_LPARSHORT = 12515; // 272 +static const uint64_t SH_FLD_LPARSHORT_LEN = 12516; // 272 +static const uint64_t SH_FLD_LPAR_FUSED_CORE_MODE = 12517; // 24 +static const uint64_t SH_FLD_LPCR_BOT = 12518; // 16 +static const uint64_t SH_FLD_LPCR_ISL = 12519; // 16 +static const uint64_t SH_FLD_LPCR_PS = 12520; // 16 +static const uint64_t SH_FLD_LPCR_PS_LEN = 12521; // 16 +static const uint64_t SH_FLD_LPCR_SC = 12522; // 16 +static const uint64_t SH_FLD_LPCR_TC = 12523; // 16 +static const uint64_t SH_FLD_LPCTH = 12524; // 3 +static const uint64_t SH_FLD_LPCTH_LEN = 12525; // 3 +static const uint64_t SH_FLD_LPC_INTERRUPT_HIGH = 12526; // 1 +static const uint64_t SH_FLD_LPC_INTERRUPT_PENDING = 12527; // 1 +static const uint64_t SH_FLD_LPC_MODE = 12528; // 2 +static const uint64_t SH_FLD_LPC_MODE_LEN = 12529; // 2 +static const uint64_t SH_FLD_LPC_OTHER_INTERRUPT_HIGH = 12530; // 1 +static const uint64_t SH_FLD_LPC_OTHER_INTERRUPT_HIGH_LEN = 12531; // 1 +static const uint64_t SH_FLD_LPC_OTHER_INTERRUPT_PENDING = 12532; // 1 +static const uint64_t SH_FLD_LPC_OTHER_INTERRUPT_PENDING_LEN = 12533; // 1 +static const uint64_t SH_FLD_LPES = 12534; // 96 +static const uint64_t SH_FLD_LPID = 12535; // 41 +static const uint64_t SH_FLD_LPID_LEN = 12536; // 41 +static const uint64_t SH_FLD_LPID_MASK = 12537; // 1 +static const uint64_t SH_FLD_LPID_MASK_LEN = 12538; // 1 +static const uint64_t SH_FLD_LP_CNT_THRESH = 12539; // 6 +static const uint64_t SH_FLD_LP_CNT_THRESH_LEN = 12540; // 6 +static const uint64_t SH_FLD_LP_LEN = 12541; // 8 +static const uint64_t SH_FLD_LP_MAX_CRED_THRESH = 12542; // 6 +static const uint64_t SH_FLD_LP_MAX_CRED_THRESH_LEN = 12543; // 6 +static const uint64_t SH_FLD_LP_MIN_CRED_THRESH = 12544; // 6 +static const uint64_t SH_FLD_LP_MIN_CRED_THRESH_LEN = 12545; // 6 +static const uint64_t SH_FLD_LP_MODE_ENABLE = 12546; // 6 +static const uint64_t SH_FLD_LP_ONLY_MODE = 12547; // 6 +static const uint64_t SH_FLD_LP_TIMER_TICK_CONFIG = 12548; // 6 +static const uint64_t SH_FLD_LP_TIMER_TICK_CONFIG_LEN = 12549; // 6 +static const uint64_t SH_FLD_LR = 12550; // 96 +static const uint64_t SH_FLD_LRDIMM = 12551; // 2 +static const uint64_t SH_FLD_LRDIMM_CONTEXT = 12552; // 8 +static const uint64_t SH_FLD_LRDIMM_LEN = 12553; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD1 = 12554; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD10 = 12555; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD10_LEN = 12556; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD11 = 12557; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD11_LEN = 12558; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD12 = 12559; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD12_LEN = 12560; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD13 = 12561; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD13_LEN = 12562; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD14 = 12563; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD14_LEN = 12564; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD15 = 12565; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD15_LEN = 12566; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD1_LEN = 12567; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD2 = 12568; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD2_LEN = 12569; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD3 = 12570; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD3_LEN = 12571; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD4 = 12572; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD4_LEN = 12573; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD5 = 12574; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD5_LEN = 12575; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD6 = 12576; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD6_LEN = 12577; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD7 = 12578; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD7_LEN = 12579; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD8 = 12580; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD8_LEN = 12581; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD9 = 12582; // 2 +static const uint64_t SH_FLD_LRDIMM_WORD9_LEN = 12583; // 2 +static const uint64_t SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED = 12584; // 12 +static const uint64_t SH_FLD_LRU_EN = 12585; // 12 +static const uint64_t SH_FLD_LRU_PERR_CHK_DIS = 12586; // 2 +static const uint64_t SH_FLD_LRU_READ_ERROR_DETECTED = 12587; // 12 +static const uint64_t SH_FLD_LR_LEN = 12588; // 96 +static const uint64_t SH_FLD_LS0_DCAC_FIN_PERR_HOLD_OUT = 12589; // 24 +static const uint64_t SH_FLD_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT = 12590; // 24 +static const uint64_t SH_FLD_LS1_DCAC_FIN_PERR_HOLD_OUT = 12591; // 24 +static const uint64_t SH_FLD_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT = 12592; // 24 +static const uint64_t SH_FLD_LS2_DCAC_FIN_PERR_HOLD_OUT = 12593; // 24 +static const uint64_t SH_FLD_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT = 12594; // 24 +static const uint64_t SH_FLD_LS3_DCAC_FIN_PERR_HOLD_OUT = 12595; // 24 +static const uint64_t SH_FLD_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT = 12596; // 24 +static const uint64_t SH_FLD_LSAMRD_SPR_PERR_HOLD_OUT = 12597; // 24 +static const uint64_t SH_FLD_LSAMRS_SPR_PERR_HOLD_OUT = 12598; // 24 +static const uint64_t SH_FLD_LSERTD_FIN_ERATMHE_HOLD_OUT = 12599; // 24 +static const uint64_t SH_FLD_LSERTD_FIN_P_HOLD_OUT = 12600; // 24 +static const uint64_t SH_FLD_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT = 12601; // 24 +static const uint64_t SH_FLD_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT = 12602; // 24 +static const uint64_t SH_FLD_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT = 12603; // 24 +static const uint64_t SH_FLD_LSINTR_SPR_PERR_HOLD_OUT = 12604; // 24 +static const uint64_t SH_FLD_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT = 12605; // 24 +static const uint64_t SH_FLD_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT = 12606; // 24 +static const uint64_t SH_FLD_LSLMQE_INV_RD_ERR_HOLD_OUT = 12607; // 24 +static const uint64_t SH_FLD_LSLRQE_CI_CDF_STUCK_HOLD_OUT = 12608; // 24 +static const uint64_t SH_FLD_LSLRQE_OVERFLOW_HOLD_OUT = 12609; // 24 +static const uint64_t SH_FLD_LSLRQF_OVERFLOW_HOLD_OUT = 12610; // 24 +static const uint64_t SH_FLD_LSLSAQ_OVERFLOW_HOLD_OUT = 12611; // 24 +static const uint64_t SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA = 12612; // 1 +static const uint64_t SH_FLD_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT = 12613; // 24 +static const uint64_t SH_FLD_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT = 12614; // 24 +static const uint64_t SH_FLD_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT = 12615; // 24 +static const uint64_t SH_FLD_LSPRQ_SPR_PERR_HOLD_OUT = 12616; // 24 +static const uint64_t SH_FLD_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT = 12617; // 24 +static const uint64_t SH_FLD_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT = 12618; // 24 +static const uint64_t SH_FLD_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT = 12619; // 24 +static const uint64_t SH_FLD_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT = 12620; // 24 +static const uint64_t SH_FLD_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT = 12621; // 24 +static const uint64_t SH_FLD_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT = 12622; // 24 +static const uint64_t SH_FLD_LSSRQ_RES_OVERFLOW_HOLD_OUT = 12623; // 24 +static const uint64_t SH_FLD_LSU_EMPTY = 12624; // 24 +static const uint64_t SH_FLD_LSU_SPARE = 12625; // 24 +static const uint64_t SH_FLD_LSXREG_SPR_PERR_HOLD_OUT = 12626; // 24 +static const uint64_t SH_FLD_LS_DERAT_MULTIHIT_ERROR = 12627; // 24 +static const uint64_t SH_FLD_LS_LOG_REC_ERROR = 12628; // 24 +static const uint64_t SH_FLD_LS_LOG_XSTOP_ERROR = 12629; // 24 +static const uint64_t SH_FLD_LS_NOT_MT_REC_ERROR = 12630; // 24 +static const uint64_t SH_FLD_LS_RFILE_REC_ERROR = 12631; // 24 +static const uint64_t SH_FLD_LS_RFILE_XSTOP_ERROR = 12632; // 24 +static const uint64_t SH_FLD_LS_S2QR_PERR_P2_HOLD_OUT = 12633; // 24 +static const uint64_t SH_FLD_LS_SETDELETE_ERROR = 12634; // 24 +static const uint64_t SH_FLD_LS_SLB_MULTIHIT_ERROR = 12635; // 24 +static const uint64_t SH_FLD_LS_SLB_MULTIHIT_HOLD_OUT = 12636; // 24 +static const uint64_t SH_FLD_LS_SLB_P_HOLD_OUT = 12637; // 24 +static const uint64_t SH_FLD_LS_SRAM_PARITY_ERROR = 12638; // 24 +static const uint64_t SH_FLD_LS_SYS_XSTOP_ERROR = 12639; // 24 +static const uint64_t SH_FLD_LS_TLB_MULTIHIT_ERROR = 12640; // 24 +static const uint64_t SH_FLD_LS_TLB_MULTIHIT_HOLD_OUT = 12641; // 24 +static const uint64_t SH_FLD_LS_TLB_P_HOLD_OUT = 12642; // 24 +static const uint64_t SH_FLD_LT0_ATTN_COMPLETE = 12643; // 24 +static const uint64_t SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12644; // 24 +static const uint64_t SH_FLD_LT0_CORE_CODE_TO_SP = 12645; // 24 +static const uint64_t SH_FLD_LT0_DPDES = 12646; // 24 +static const uint64_t SH_FLD_LT0_SPATTN_MASK = 12647; // 24 +static const uint64_t SH_FLD_LT0_SPATTN_MASK_LEN = 12648; // 24 +static const uint64_t SH_FLD_LT0_SPR_INSTR_STOP = 12649; // 24 +static const uint64_t SH_FLD_LT1_ATTN_COMPLETE = 12650; // 24 +static const uint64_t SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12651; // 24 +static const uint64_t SH_FLD_LT1_CORE_CODE_TO_SP = 12652; // 24 +static const uint64_t SH_FLD_LT1_DPDES = 12653; // 24 +static const uint64_t SH_FLD_LT1_SPATTN_MASK = 12654; // 24 +static const uint64_t SH_FLD_LT1_SPATTN_MASK_LEN = 12655; // 24 +static const uint64_t SH_FLD_LT1_SPR_INSTR_STOP = 12656; // 24 +static const uint64_t SH_FLD_LT2_ATTN_COMPLETE = 12657; // 24 +static const uint64_t SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12658; // 24 +static const uint64_t SH_FLD_LT2_CORE_CODE_TO_SP = 12659; // 24 +static const uint64_t SH_FLD_LT2_DPDES = 12660; // 24 +static const uint64_t SH_FLD_LT2_SPATTN_MASK = 12661; // 24 +static const uint64_t SH_FLD_LT2_SPATTN_MASK_LEN = 12662; // 24 +static const uint64_t SH_FLD_LT2_SPR_INSTR_STOP = 12663; // 24 +static const uint64_t SH_FLD_LT3_ATTN_COMPLETE = 12664; // 24 +static const uint64_t SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12665; // 24 +static const uint64_t SH_FLD_LT3_CORE_CODE_TO_SP = 12666; // 24 +static const uint64_t SH_FLD_LT3_DPDES = 12667; // 24 +static const uint64_t SH_FLD_LT3_SPATTN_MASK = 12668; // 24 +static const uint64_t SH_FLD_LT3_SPATTN_MASK_LEN = 12669; // 24 +static const uint64_t SH_FLD_LT3_SPR_INSTR_STOP = 12670; // 24 +static const uint64_t SH_FLD_LT4_ATTN_COMPLETE = 12671; // 24 +static const uint64_t SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12672; // 24 +static const uint64_t SH_FLD_LT4_CORE_CODE_TO_SP = 12673; // 24 +static const uint64_t SH_FLD_LT4_DPDES = 12674; // 24 +static const uint64_t SH_FLD_LT4_SPATTN_MASK = 12675; // 24 +static const uint64_t SH_FLD_LT4_SPATTN_MASK_LEN = 12676; // 24 +static const uint64_t SH_FLD_LT4_SPR_INSTR_STOP = 12677; // 24 +static const uint64_t SH_FLD_LT5_ATTN_COMPLETE = 12678; // 24 +static const uint64_t SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12679; // 24 +static const uint64_t SH_FLD_LT5_CORE_CODE_TO_SP = 12680; // 24 +static const uint64_t SH_FLD_LT5_DPDES = 12681; // 24 +static const uint64_t SH_FLD_LT5_SPATTN_MASK = 12682; // 24 +static const uint64_t SH_FLD_LT5_SPATTN_MASK_LEN = 12683; // 24 +static const uint64_t SH_FLD_LT5_SPR_INSTR_STOP = 12684; // 24 +static const uint64_t SH_FLD_LT6_ATTN_COMPLETE = 12685; // 24 +static const uint64_t SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12686; // 24 +static const uint64_t SH_FLD_LT6_CORE_CODE_TO_SP = 12687; // 24 +static const uint64_t SH_FLD_LT6_DPDES = 12688; // 24 +static const uint64_t SH_FLD_LT6_SPATTN_MASK = 12689; // 24 +static const uint64_t SH_FLD_LT6_SPATTN_MASK_LEN = 12690; // 24 +static const uint64_t SH_FLD_LT6_SPR_INSTR_STOP = 12691; // 24 +static const uint64_t SH_FLD_LT7_ATTN_COMPLETE = 12692; // 24 +static const uint64_t SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 12693; // 24 +static const uint64_t SH_FLD_LT7_CORE_CODE_TO_SP = 12694; // 24 +static const uint64_t SH_FLD_LT7_DPDES = 12695; // 24 +static const uint64_t SH_FLD_LT7_SPATTN_MASK = 12696; // 24 +static const uint64_t SH_FLD_LT7_SPATTN_MASK_LEN = 12697; // 24 +static const uint64_t SH_FLD_LT7_SPR_INSTR_STOP = 12698; // 24 +static const uint64_t SH_FLD_LTE_EN = 12699; // 4 +static const uint64_t SH_FLD_LUC = 12700; // 1 +static const uint64_t SH_FLD_LUC_LEN = 12701; // 1 +static const uint64_t SH_FLD_LUT = 12702; // 1 +static const uint64_t SH_FLD_LUT_LEN = 12703; // 1 +static const uint64_t SH_FLD_LVALID = 12704; // 32 +static const uint64_t SH_FLD_LVDIR_EN = 12705; // 12 +static const uint64_t SH_FLD_LVDIR_PERR = 12706; // 12 +static const uint64_t SH_FLD_LVLTRANS_FENCE = 12707; // 43 +static const uint64_t SH_FLD_M = 12708; // 1 +static const uint64_t SH_FLD_M0_BIT_MAP = 12709; // 8 +static const uint64_t SH_FLD_M0_BIT_MAP_LEN = 12710; // 8 +static const uint64_t SH_FLD_M0_PRIORITY = 12711; // 1 +static const uint64_t SH_FLD_M0_PRIORITY_LEN = 12712; // 1 +static const uint64_t SH_FLD_M0_PRIORITY_SEL = 12713; // 1 +static const uint64_t SH_FLD_M1HC0A = 12714; // 1 +static const uint64_t SH_FLD_M1HC0A_LEN = 12715; // 1 +static const uint64_t SH_FLD_M1HC0B = 12716; // 1 +static const uint64_t SH_FLD_M1HC0B_LEN = 12717; // 1 +static const uint64_t SH_FLD_M1HC1A = 12718; // 1 +static const uint64_t SH_FLD_M1HC1A_LEN = 12719; // 1 +static const uint64_t SH_FLD_M1HC1B = 12720; // 1 +static const uint64_t SH_FLD_M1HC1B_LEN = 12721; // 1 +static const uint64_t SH_FLD_M1HC2A = 12722; // 1 +static const uint64_t SH_FLD_M1HC2A_LEN = 12723; // 1 +static const uint64_t SH_FLD_M1HC2B = 12724; // 1 +static const uint64_t SH_FLD_M1HC2B_LEN = 12725; // 1 +static const uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_ERROR = 12726; // 1 +static const uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_PENDING = 12727; // 1 +static const uint64_t SH_FLD_M1SASIM1_ENABLE_XUP = 12728; // 1 +static const uint64_t SH_FLD_M1_BIT_MAP = 12729; // 8 +static const uint64_t SH_FLD_M1_BIT_MAP_LEN = 12730; // 8 +static const uint64_t SH_FLD_M1_PRIORITY = 12731; // 1 +static const uint64_t SH_FLD_M1_PRIORITY_LEN = 12732; // 1 +static const uint64_t SH_FLD_M1_PRIORITY_SEL = 12733; // 1 +static const uint64_t SH_FLD_M2HC0A = 12734; // 1 +static const uint64_t SH_FLD_M2HC0A_LEN = 12735; // 1 +static const uint64_t SH_FLD_M2HC0B = 12736; // 1 +static const uint64_t SH_FLD_M2HC0B_LEN = 12737; // 1 +static const uint64_t SH_FLD_M2HC1A = 12738; // 1 +static const uint64_t SH_FLD_M2HC1A_LEN = 12739; // 1 +static const uint64_t SH_FLD_M2HC1B = 12740; // 1 +static const uint64_t SH_FLD_M2HC1B_LEN = 12741; // 1 +static const uint64_t SH_FLD_M2HC2A = 12742; // 1 +static const uint64_t SH_FLD_M2HC2A_LEN = 12743; // 1 +static const uint64_t SH_FLD_M2HC2B = 12744; // 1 +static const uint64_t SH_FLD_M2HC2B_LEN = 12745; // 1 +static const uint64_t SH_FLD_M2_PRIORITY = 12746; // 1 +static const uint64_t SH_FLD_M2_PRIORITY_LEN = 12747; // 1 +static const uint64_t SH_FLD_M2_PRIORITY_SEL = 12748; // 1 +static const uint64_t SH_FLD_M3_PRIORITY = 12749; // 1 +static const uint64_t SH_FLD_M3_PRIORITY_LEN = 12750; // 1 +static const uint64_t SH_FLD_M3_PRIORITY_SEL = 12751; // 1 +static const uint64_t SH_FLD_M4_PRIORITY = 12752; // 1 +static const uint64_t SH_FLD_M4_PRIORITY_LEN = 12753; // 1 +static const uint64_t SH_FLD_M5_PRIORITY = 12754; // 1 +static const uint64_t SH_FLD_M5_PRIORITY_LEN = 12755; // 1 +static const uint64_t SH_FLD_M5_PRIORITY_SEL = 12756; // 1 +static const uint64_t SH_FLD_M6_PRIORITY = 12757; // 1 +static const uint64_t SH_FLD_M6_PRIORITY_LEN = 12758; // 1 +static const uint64_t SH_FLD_M7_PRIORITY = 12759; // 1 +static const uint64_t SH_FLD_M7_PRIORITY_LEN = 12760; // 1 +static const uint64_t SH_FLD_M7_PRIORITY_SEL = 12761; // 1 +static const uint64_t SH_FLD_MAGIC_COOKIE = 12762; // 1 +static const uint64_t SH_FLD_MAGIC_COOKIE_LEN = 12763; // 1 +static const uint64_t SH_FLD_MAIL_DELIVERED_TO_LEFT = 12764; // 2 +static const uint64_t SH_FLD_MAIL_DELIVERED_TO_RIGHT = 12765; // 2 +static const uint64_t SH_FLD_MAIL_RECEIVED_FR_LEFT = 12766; // 2 +static const uint64_t SH_FLD_MAIL_RECEIVED_FR_RIGHT = 12767; // 2 +static const uint64_t SH_FLD_MAINLINE_AUE = 12768; // 8 +static const uint64_t SH_FLD_MAINLINE_IAUE = 12769; // 8 +static const uint64_t SH_FLD_MAINLINE_IMPE = 12770; // 8 +static const uint64_t SH_FLD_MAINLINE_IRCD = 12771; // 8 +static const uint64_t SH_FLD_MAINLINE_IUE = 12772; // 8 +static const uint64_t SH_FLD_MAINLINE_MCE = 12773; // 8 +static const uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7 = 12774; // 8 +static const uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN = 12775; // 8 +static const uint64_t SH_FLD_MAINLINE_NCE = 12776; // 8 +static const uint64_t SH_FLD_MAINLINE_RCD = 12777; // 8 +static const uint64_t SH_FLD_MAINLINE_SCE = 12778; // 8 +static const uint64_t SH_FLD_MAINLINE_SUE = 12779; // 8 +static const uint64_t SH_FLD_MAINLINE_TCE = 12780; // 8 +static const uint64_t SH_FLD_MAINLINE_UE = 12781; // 8 +static const uint64_t SH_FLD_MAINTENANCE_AUE = 12782; // 8 +static const uint64_t SH_FLD_MAINTENANCE_IAUE = 12783; // 8 +static const uint64_t SH_FLD_MAINTENANCE_IMPE = 12784; // 8 +static const uint64_t SH_FLD_MAINTENANCE_IRCD = 12785; // 8 +static const uint64_t SH_FLD_MAINTENANCE_IUE = 12786; // 8 +static const uint64_t SH_FLD_MAINTENANCE_MCE = 12787; // 8 +static const uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 = 12788; // 8 +static const uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 12789; // 8 +static const uint64_t SH_FLD_MAINTENANCE_NCE = 12790; // 8 +static const uint64_t SH_FLD_MAINTENANCE_RCD = 12791; // 8 +static const uint64_t SH_FLD_MAINTENANCE_SCE = 12792; // 8 +static const uint64_t SH_FLD_MAINTENANCE_SUE = 12793; // 8 +static const uint64_t SH_FLD_MAINTENANCE_TCE = 12794; // 8 +static const uint64_t SH_FLD_MAINTENANCE_UE = 12795; // 8 +static const uint64_t SH_FLD_MAINT_CCS_PE_HOLD_OUT = 12796; // 2 +static const uint64_t SH_FLD_MAIN_SLICE_EN_ENC = 12797; // 1 +static const uint64_t SH_FLD_MAIN_SLICE_EN_ENC_LEN = 12798; // 1 +static const uint64_t SH_FLD_MAJOR = 12799; // 25 +static const uint64_t SH_FLD_MAJOR_LEN = 12800; // 25 +static const uint64_t SH_FLD_MALFUNCTION_ALERT = 12801; // 96 +static const uint64_t SH_FLD_MALF_ALERT_PRESENT = 12802; // 24 +static const uint64_t SH_FLD_MALF_ALERT_REQUESTED = 12803; // 24 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP0 = 12804; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP0_LEN = 12805; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP1 = 12806; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP10 = 12807; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP10_LEN = 12808; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP11 = 12809; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP11_LEN = 12810; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP12 = 12811; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP12_LEN = 12812; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP13 = 12813; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP13_LEN = 12814; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP14 = 12815; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP14_LEN = 12816; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP15 = 12817; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP15_LEN = 12818; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP1_LEN = 12819; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP2 = 12820; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP2_LEN = 12821; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP3 = 12822; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP3_LEN = 12823; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP4 = 12824; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP4_LEN = 12825; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP5 = 12826; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP5_LEN = 12827; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP6 = 12828; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP6_LEN = 12829; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP7 = 12830; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP7_LEN = 12831; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP8 = 12832; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP8_LEN = 12833; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP9 = 12834; // 1 +static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP9_LEN = 12835; // 1 +static const uint64_t SH_FLD_MANUAL_CLR_PB_STOP = 12836; // 1 +static const uint64_t SH_FLD_MANUAL_PB_SWITCH_ABCD = 12837; // 1 +static const uint64_t SH_FLD_MANUAL_RECAL_LANE = 12838; // 6 +static const uint64_t SH_FLD_MANUAL_RECAL_LANE_LEN = 12839; // 6 +static const uint64_t SH_FLD_MANUAL_RECAL_REQUEST = 12840; // 6 +static const uint64_t SH_FLD_MANUAL_SET_PB_STOP = 12841; // 1 +static const uint64_t SH_FLD_MANUFACTURER_ID = 12842; // 24 +static const uint64_t SH_FLD_MANUFACTURER_ID_LEN = 12843; // 24 +static const uint64_t SH_FLD_MAP_ERR_INJ_PEND = 12844; // 1 +static const uint64_t SH_FLD_MAP_REG_CERR0 = 12845; // 1 +static const uint64_t SH_FLD_MAP_REG_CERR1 = 12846; // 1 +static const uint64_t SH_FLD_MAP_REG_ERR0 = 12847; // 1 +static const uint64_t SH_FLD_MAP_REG_ERR1 = 12848; // 1 +static const uint64_t SH_FLD_MAP_REG_ERR2 = 12849; // 1 +static const uint64_t SH_FLD_MAP_REG_ERR3 = 12850; // 1 +static const uint64_t SH_FLD_MAP_REG_ERR4 = 12851; // 1 +static const uint64_t SH_FLD_MARGINPD_SEL = 12852; // 6 +static const uint64_t SH_FLD_MARGINPD_SEL_LEN = 12853; // 6 +static const uint64_t SH_FLD_MARGINPU_SEL = 12854; // 6 +static const uint64_t SH_FLD_MARGINPU_SEL_LEN = 12855; // 6 +static const uint64_t SH_FLD_MARK = 12856; // 64 +static const uint64_t SH_FLD_MARK_LEN = 12857; // 64 +static const uint64_t SH_FLD_MASK = 12858; // 69 +static const uint64_t SH_FLD_MASKA = 12859; // 162 +static const uint64_t SH_FLD_MASKA_LEN = 12860; // 162 +static const uint64_t SH_FLD_MASKB = 12861; // 162 +static const uint64_t SH_FLD_MASKB_LEN = 12862; // 162 +static const uint64_t SH_FLD_MASKC = 12863; // 162 +static const uint64_t SH_FLD_MASKC_LEN = 12864; // 162 +static const uint64_t SH_FLD_MASKD = 12865; // 162 +static const uint64_t SH_FLD_MASKD_LEN = 12866; // 162 +static const uint64_t SH_FLD_MASK_AGV_DISABLE_MODE = 12867; // 2 +static const uint64_t SH_FLD_MASK_B = 12868; // 129 +static const uint64_t SH_FLD_MASK_HMI = 12869; // 96 +static const uint64_t SH_FLD_MASK_IF_LOG_REC_ERROR = 12870; // 24 +static const uint64_t SH_FLD_MASK_IF_LOG_XSTOP_ERROR = 12871; // 24 +static const uint64_t SH_FLD_MASK_IF_RFILE_REC_ERROR = 12872; // 24 +static const uint64_t SH_FLD_MASK_IF_RFILE_XSTOP_ERROR = 12873; // 24 +static const uint64_t SH_FLD_MASK_IF_SRAM_REC_ERROR = 12874; // 24 +static const uint64_t SH_FLD_MASK_LEN = 12875; // 61 +static const uint64_t SH_FLD_MASK_LS_DERAT_MULTIHIT_ERROR = 12876; // 24 +static const uint64_t SH_FLD_MASK_LS_LOG_REC_ERROR = 12877; // 24 +static const uint64_t SH_FLD_MASK_LS_LOG_XSTOP_ERROR = 12878; // 24 +static const uint64_t SH_FLD_MASK_LS_NOT_MT_REC_ERROR = 12879; // 24 +static const uint64_t SH_FLD_MASK_LS_RFILE_REC_ERROR = 12880; // 24 +static const uint64_t SH_FLD_MASK_LS_RFILE_XSTOP_ERROR = 12881; // 24 +static const uint64_t SH_FLD_MASK_LS_SETDELETE_ERROR = 12882; // 24 +static const uint64_t SH_FLD_MASK_LS_SLB_MULTIHIT_ERROR = 12883; // 24 +static const uint64_t SH_FLD_MASK_LS_SRAM_PARITY_ERROR = 12884; // 24 +static const uint64_t SH_FLD_MASK_LS_SYS_XSTOP_ERROR = 12885; // 24 +static const uint64_t SH_FLD_MASK_LS_TLB_MULTIHIT_ERROR = 12886; // 24 +static const uint64_t SH_FLD_MASK_PC_FWD_PROGRESS_ERROR = 12887; // 24 +static const uint64_t SH_FLD_MASK_PC_FW_INJ_REC_ERROR = 12888; // 24 +static const uint64_t SH_FLD_MASK_PC_FW_INJ_XSTOP_ERROR = 12889; // 24 +static const uint64_t SH_FLD_MASK_PC_HANG_DETECT_ERROR = 12890; // 24 +static const uint64_t SH_FLD_MASK_PC_HANG_RECOVERY_FAILED = 12891; // 24 +static const uint64_t SH_FLD_MASK_PC_HYP_RES_ERROR = 12892; // 24 +static const uint64_t SH_FLD_MASK_PC_LOG_XSTOP_ERROR = 12893; // 24 +static const uint64_t SH_FLD_MASK_PC_NEST_HANG_DETECT_ERROR = 12894; // 24 +static const uint64_t SH_FLD_MASK_PC_OTHER_CHIPLET_REC_ERROR = 12895; // 24 +static const uint64_t SH_FLD_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 12896; // 24 +static const uint64_t SH_FLD_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR = 12897; // 24 +static const uint64_t SH_FLD_MASK_PC_PHYP_XSTOP_ERROR = 12898; // 24 +static const uint64_t SH_FLD_MASK_PC_RECOV_IN_MAINT_ERROR = 12899; // 24 +static const uint64_t SH_FLD_MASK_PC_RECOV_XSTOP_ERROR = 12900; // 24 +static const uint64_t SH_FLD_MASK_PC_SCOM_ERROR = 12901; // 24 +static const uint64_t SH_FLD_MASK_PC_SYS_XSTOP_ERROR = 12902; // 24 +static const uint64_t SH_FLD_MASK_PC_TFAC_XSTOP_ERROR = 12903; // 24 +static const uint64_t SH_FLD_MASK_PC_THREAD_HANG_REC_ERROR = 12904; // 24 +static const uint64_t SH_FLD_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 12905; // 24 +static const uint64_t SH_FLD_MASK_PURGE_INTERFACE = 12906; // 12 +static const uint64_t SH_FLD_MASK_SD_CI_UE_ERROR = 12907; // 24 +static const uint64_t SH_FLD_MASK_SD_L2_UE_ERROR = 12908; // 24 +static const uint64_t SH_FLD_MASK_SD_L2_UE_OVER_THRES_ERROR = 12909; // 24 +static const uint64_t SH_FLD_MASK_SD_LOG_REC_ERROR = 12910; // 24 +static const uint64_t SH_FLD_MASK_SD_LOG_XSTOP_ERROR = 12911; // 24 +static const uint64_t SH_FLD_MASK_SD_MCHK_AND_ME_EQ_0_ERROR = 12912; // 24 +static const uint64_t SH_FLD_MASK_SD_NOT_MT_CI_REC_ERROR = 12913; // 24 +static const uint64_t SH_FLD_MASK_SD_RFILE_REC_ERROR = 12914; // 24 +static const uint64_t SH_FLD_MASK_SD_RFILE_XSTOP_ERROR = 12915; // 24 +static const uint64_t SH_FLD_MASK_SD_SYS_XSTOP_ERROR = 12916; // 24 +static const uint64_t SH_FLD_MASK_TC_FIR_XSTOP_ERROR = 12917; // 24 +static const uint64_t SH_FLD_MASK_TOGGLE_ENABLE = 12918; // 1 +static const uint64_t SH_FLD_MASK_UNUSED_18 = 12919; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_19 = 12920; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_21 = 12921; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_22 = 12922; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_23 = 12923; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_40 = 12924; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_42 = 12925; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_44 = 12926; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_46 = 12927; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_49 = 12928; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_50 = 12929; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_51 = 12930; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_54 = 12931; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_6 = 12932; // 24 +static const uint64_t SH_FLD_MASK_UNUSED_7 = 12933; // 24 +static const uint64_t SH_FLD_MASK_VS_DU_LOG_REC_ERROR = 12934; // 24 +static const uint64_t SH_FLD_MASK_VS_LOG_REC_ERROR = 12935; // 24 +static const uint64_t SH_FLD_MASK_VS_LOG_XSTOP_ERROR = 12936; // 24 +static const uint64_t SH_FLD_MASTER = 12937; // 8 +static const uint64_t SH_FLD_MASTERID = 12938; // 6 +static const uint64_t SH_FLD_MASTERID_LEN = 12939; // 6 +static const uint64_t SH_FLD_MASTER_ARRAY_CE = 12940; // 4 +static const uint64_t SH_FLD_MASTER_ARRAY_UE = 12941; // 4 +static const uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV = 12942; // 12 +static const uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 12943; // 12 +static const uint64_t SH_FLD_MASTER_ERROR_CODE = 12944; // 1 +static const uint64_t SH_FLD_MASTER_ERROR_CODE_LEN = 12945; // 1 +static const uint64_t SH_FLD_MASTER_IDLE = 12946; // 1 +static const uint64_t SH_FLD_MASTER_MODE = 12947; // 47 +static const uint64_t SH_FLD_MASTER_RECOVERABLE_ERROR = 12948; // 4 +static const uint64_t SH_FLD_MASTER_RESPONSE_BIT = 12949; // 1 +static const uint64_t SH_FLD_MASTER_SYS_XSTOP_ERROR = 12950; // 4 +static const uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV = 12951; // 12 +static const uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 12952; // 12 +static const uint64_t SH_FLD_MATCH = 12953; // 12 +static const uint64_t SH_FLD_MATCHA_MUXSEL = 12954; // 162 +static const uint64_t SH_FLD_MATCHA_MUXSEL_LEN = 12955; // 162 +static const uint64_t SH_FLD_MATCHB_MUXSEL = 12956; // 162 +static const uint64_t SH_FLD_MATCHB_MUXSEL_LEN = 12957; // 162 +static const uint64_t SH_FLD_MATCHC_MUXSEL = 12958; // 162 +static const uint64_t SH_FLD_MATCHC_MUXSEL_LEN = 12959; // 162 +static const uint64_t SH_FLD_MATCHD_MUXSEL = 12960; // 162 +static const uint64_t SH_FLD_MATCHD_MUXSEL_LEN = 12961; // 162 +static const uint64_t SH_FLD_MATCH_LEN = 12962; // 12 +static const uint64_t SH_FLD_MATCH_NOT_MODE = 12963; // 162 +static const uint64_t SH_FLD_MATCH_NOT_MODE_LEN = 12964; // 162 +static const uint64_t SH_FLD_MAX = 12965; // 1 +static const uint64_t SH_FLD_MAXCYCLECNT = 12966; // 3 +static const uint64_t SH_FLD_MAXCYCLECNT_LEN = 12967; // 3 +static const uint64_t SH_FLD_MAX_BAD_LANES = 12968; // 4 +static const uint64_t SH_FLD_MAX_BAD_LANES_LEN = 12969; // 4 +static const uint64_t SH_FLD_MAX_BER_CHECK_COUNT = 12970; // 4 +static const uint64_t SH_FLD_MAX_BER_CHECK_COUNT_LEN = 12971; // 4 +static const uint64_t SH_FLD_MAX_CRD_TO_CQ = 12972; // 6 +static const uint64_t SH_FLD_MAX_CRD_TO_CQ_LEN = 12973; // 6 +static const uint64_t SH_FLD_MAX_CRD_TO_PC = 12974; // 6 +static const uint64_t SH_FLD_MAX_CRD_TO_PC_LEN = 12975; // 6 +static const uint64_t SH_FLD_MAX_CYCLE_SAMPLE = 12976; // 12 +static const uint64_t SH_FLD_MAX_CYCLE_SAMPLE_LEN = 12977; // 12 +static const uint64_t SH_FLD_MAX_CYC_BET_STEPS = 12978; // 98 +static const uint64_t SH_FLD_MAX_CYC_BET_STEPS_LEN = 12979; // 98 +static const uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED = 12980; // 3 +static const uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN = 12981; // 3 +static const uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 12982; // 2 +static const uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 12983; // 2 +static const uint64_t SH_FLD_MAX_OUTSTANDING = 12984; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD = 12985; // 2 +static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN = 12986; // 2 +static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE = 12987; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN = 12988; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EOI = 12989; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EOI_LEN = 12990; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH = 12991; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN = 12992; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE = 12993; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN = 12994; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EQP = 12995; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_EQP_LEN = 12996; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH = 12997; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN = 12998; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE = 12999; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN = 13000; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH = 13001; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN = 13002; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_LEN = 13003; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP = 13004; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 13005; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI = 13006; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN = 13007; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT = 13008; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN = 13009; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC = 13010; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN = 13011; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH = 13012; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN = 13013; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_WB = 13014; // 1 +static const uint64_t SH_FLD_MAX_OUTSTANDING_WB_LEN = 13015; // 1 +static const uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4 = 13016; // 1 +static const uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4_LEN = 13017; // 1 +static const uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4 = 13018; // 1 +static const uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4_LEN = 13019; // 1 +static const uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4 = 13020; // 1 +static const uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4_LEN = 13021; // 1 +static const uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N = 13022; // 96 +static const uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN = 13023; // 96 +static const uint64_t SH_FLD_MAX_PTAG_IN_USE = 13024; // 7 +static const uint64_t SH_FLD_MAX_PTAG_IN_USE_LEN = 13025; // 7 +static const uint64_t SH_FLD_MAX_TIMEOUT = 13026; // 10 +static const uint64_t SH_FLD_MAX_TIMEOUT_LEN = 13027; // 10 +static const uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO = 13028; // 4 +static const uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO_LEN = 13029; // 4 +static const uint64_t SH_FLD_MB00_SPATTN = 13030; // 4 +static const uint64_t SH_FLD_MB01_SPATTN = 13031; // 4 +static const uint64_t SH_FLD_MB10_SPATTN = 13032; // 4 +static const uint64_t SH_FLD_MB11_SPATTN = 13033; // 4 +static const uint64_t SH_FLD_MB20_SPATTN = 13034; // 4 +static const uint64_t SH_FLD_MB21_SPATTN = 13035; // 4 +static const uint64_t SH_FLD_MB30_SPATTN = 13036; // 4 +static const uint64_t SH_FLD_MB31_SPATTN = 13037; // 4 +static const uint64_t SH_FLD_MB40_SPATTN = 13038; // 4 +static const uint64_t SH_FLD_MB41_SPATTN = 13039; // 4 +static const uint64_t SH_FLD_MB50_SPATTN = 13040; // 4 +static const uint64_t SH_FLD_MB51_SPATTN = 13041; // 4 +static const uint64_t SH_FLD_MB60_SPATTN = 13042; // 2 +static const uint64_t SH_FLD_MB61_SPATTN = 13043; // 2 +static const uint64_t SH_FLD_MB70_SPATTN = 13044; // 2 +static const uint64_t SH_FLD_MB71_SPATTN = 13045; // 2 +static const uint64_t SH_FLD_MBACALFIRQ_PORT_FAIL = 13046; // 8 +static const uint64_t SH_FLD_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 13047; // 8 +static const uint64_t SH_FLD_MBASE = 13048; // 12 +static const uint64_t SH_FLD_MBASE_LEN = 13049; // 12 +static const uint64_t SH_FLD_MBA_NONRECOVERABLE_ERROR = 13050; // 16 +static const uint64_t SH_FLD_MBA_RECOVERABLE_ERROR = 13051; // 16 +static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 13052; // 8 +static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN = 13053; // 8 +static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 13054; // 8 +static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 13055; // 8 +static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 13056; // 8 +static const uint64_t SH_FLD_MBA_WRD_MODE_RESERVED_4 = 13057; // 8 +static const uint64_t SH_FLD_MBOX0 = 13058; // 1 +static const uint64_t SH_FLD_MBOX0_LEN = 13059; // 1 +static const uint64_t SH_FLD_MBOX1 = 13060; // 1 +static const uint64_t SH_FLD_MBOX1_LEN = 13061; // 1 +static const uint64_t SH_FLD_MBOX2 = 13062; // 1 +static const uint64_t SH_FLD_MBOX2_LEN = 13063; // 1 +static const uint64_t SH_FLD_MBOX3 = 13064; // 1 +static const uint64_t SH_FLD_MBOX3_LEN = 13065; // 1 +static const uint64_t SH_FLD_MBOX4 = 13066; // 1 +static const uint64_t SH_FLD_MBOX4_LEN = 13067; // 1 +static const uint64_t SH_FLD_MBOX5 = 13068; // 1 +static const uint64_t SH_FLD_MBOX5_LEN = 13069; // 1 +static const uint64_t SH_FLD_MBOX6 = 13070; // 1 +static const uint64_t SH_FLD_MBOX6_LEN = 13071; // 1 +static const uint64_t SH_FLD_MBOX7 = 13072; // 1 +static const uint64_t SH_FLD_MBOX7_LEN = 13073; // 1 +static const uint64_t SH_FLD_MBR_DIS = 13074; // 2 +static const uint64_t SH_FLD_MBR_DIS_LEN = 13075; // 2 +static const uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE = 13076; // 8 +static const uint64_t SH_FLD_MBSECCQ_DATA_INVERSION = 13077; // 8 +static const uint64_t SH_FLD_MBSECCQ_DATA_INVERSION_LEN = 13078; // 8 +static const uint64_t SH_FLD_MBSECCQ_DELAY_NONBYPASS = 13079; // 8 +static const uint64_t SH_FLD_MBSECCQ_DELAY_VALID_1X = 13080; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_BYPASS_TEMPLATE_A = 13081; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE = 13082; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 13083; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 13084; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_MPE_CONFIRM = 13085; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 13086; // 8 +static const uint64_t SH_FLD_MBSECCQ_DISABLE_UE_RETRY = 13087; // 8 +static const uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY = 13088; // 8 +static const uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 13089; // 8 +static const uint64_t SH_FLD_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 13090; // 8 +static const uint64_t SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION = 13091; // 8 +static const uint64_t SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 13092; // 8 +static const uint64_t SH_FLD_MBSECCQ_ENABLE_TCE_CORRECTION = 13093; // 8 +static const uint64_t SH_FLD_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 13094; // 8 +static const uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE = 13095; // 8 +static const uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN = 13096; // 8 +static const uint64_t SH_FLD_MBSECCQ_HWMARK_EXIT1 = 13097; // 8 +static const uint64_t SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE = 13098; // 8 +static const uint64_t SH_FLD_MBSECCQ_MAINT_NO_RETRY_MPE = 13099; // 8 +static const uint64_t SH_FLD_MBSECCQ_MAINT_NO_RETRY_UE = 13100; // 8 +static const uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 13101; // 8 +static const uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 13102; // 8 +static const uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY = 13103; // 8 +static const uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN = 13104; // 8 +static const uint64_t SH_FLD_MBSECCQ_RESERVED_36_43 = 13105; // 8 +static const uint64_t SH_FLD_MBSECCQ_RESERVED_36_43_LEN = 13106; // 8 +static const uint64_t SH_FLD_MBSECCQ_SLOW_EXIT_REDUCTION = 13107; // 8 +static const uint64_t SH_FLD_MBSECCQ_USE_ADDRESS_HASH = 13108; // 8 +static const uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY = 13109; // 8 +static const uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 13110; // 8 +static const uint64_t SH_FLD_MB_BAD_ADDR = 13111; // 2 +static const uint64_t SH_FLD_MB_BAD_WRITE = 13112; // 2 +static const uint64_t SH_FLD_MB_CORRUPT = 13113; // 2 +static const uint64_t SH_FLD_MB_LINK_DOWN = 13114; // 2 +static const uint64_t SH_FLD_MB_LINK_ID = 13115; // 2 +static const uint64_t SH_FLD_MB_LINK_ID_LEN = 13116; // 2 +static const uint64_t SH_FLD_MB_RESET = 13117; // 2 +static const uint64_t SH_FLD_MB_SENT = 13118; // 2 +static const uint64_t SH_FLD_MB_SPARE = 13119; // 2 +static const uint64_t SH_FLD_MB_SPARE_LEN = 13120; // 2 +static const uint64_t SH_FLD_MB_VALID = 13121; // 2 +static const uint64_t SH_FLD_MB_WR_NOT_RD = 13122; // 2 +static const uint64_t SH_FLD_MCA_DBG_SEL_IN = 13123; // 8 +static const uint64_t SH_FLD_MCA_DBG_SEL_WRT = 13124; // 8 +static const uint64_t SH_FLD_MCBAGEN_PE_HOLD_OUT = 13125; // 2 +static const uint64_t SH_FLD_MCBCM_PE = 13126; // 8 +static const uint64_t SH_FLD_MCBCNTL_PE_HOLD_OUT = 13127; // 2 +static const uint64_t SH_FLD_MCBCNTL_PORT_SEL = 13128; // 2 +static const uint64_t SH_FLD_MCBCNTL_PORT_SEL_LEN = 13129; // 2 +static const uint64_t SH_FLD_MCBDGEN_PE_HOLD_OUT = 13130; // 2 +static const uint64_t SH_FLD_MCBERR_SCOM_PE_HOLD_OUT = 13131; // 2 +static const uint64_t SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC = 13132; // 2 +static const uint64_t SH_FLD_MCBIST_CCS_SUBTEST_DONE = 13133; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 13134; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK = 13135; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 13136; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 13137; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME = 13138; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN = 13139; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 13140; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE = 13141; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL = 13142; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 13143; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 13144; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 13145; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 13146; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE = 13147; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN = 13148; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DONE = 13149; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ECC_MODE = 13150; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE = 13151; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN = 13152; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 13153; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE = 13154; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL = 13155; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 13156; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 13157; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 13158; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 13159; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE = 13160; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN = 13161; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DONE = 13162; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ECC_MODE = 13163; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE = 13164; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN = 13165; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 13166; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE = 13167; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL = 13168; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 13169; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 13170; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 13171; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 13172; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE = 13173; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN = 13174; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DONE = 13175; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ECC_MODE = 13176; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE = 13177; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN = 13178; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 13179; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE = 13180; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL = 13181; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 13182; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 13183; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 13184; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 13185; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE = 13186; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN = 13187; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DONE = 13188; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ECC_MODE = 13189; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE = 13190; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN = 13191; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 13192; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE = 13193; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL = 13194; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 13195; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 13196; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 13197; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 13198; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE = 13199; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN = 13200; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DONE = 13201; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ECC_MODE = 13202; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE = 13203; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN = 13204; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 13205; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE = 13206; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL = 13207; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 13208; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 13209; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 13210; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 13211; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE = 13212; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN = 13213; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DONE = 13214; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ECC_MODE = 13215; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE = 13216; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN = 13217; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 13218; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE = 13219; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL = 13220; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 13221; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 13222; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 13223; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 13224; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE = 13225; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN = 13226; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DONE = 13227; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ECC_MODE = 13228; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE = 13229; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN = 13230; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 13231; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE = 13232; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL = 13233; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 13234; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 13235; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 13236; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 13237; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE = 13238; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN = 13239; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DONE = 13240; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ECC_MODE = 13241; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE = 13242; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN = 13243; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 13244; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE = 13245; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL = 13246; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 13247; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 13248; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 13249; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 13250; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE = 13251; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN = 13252; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DONE = 13253; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ECC_MODE = 13254; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE = 13255; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN = 13256; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 13257; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE = 13258; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL = 13259; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 13260; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 13261; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 13262; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 13263; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE = 13264; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN = 13265; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DONE = 13266; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ECC_MODE = 13267; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE = 13268; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN = 13269; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 13270; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE = 13271; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL = 13272; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 13273; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 13274; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 13275; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 13276; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE = 13277; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN = 13278; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DONE = 13279; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ECC_MODE = 13280; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE = 13281; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN = 13282; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 13283; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE = 13284; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL = 13285; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 13286; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 13287; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 13288; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 13289; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE = 13290; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN = 13291; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DONE = 13292; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ECC_MODE = 13293; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE = 13294; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN = 13295; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 13296; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE = 13297; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL = 13298; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 13299; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 13300; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 13301; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 13302; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE = 13303; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN = 13304; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DONE = 13305; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ECC_MODE = 13306; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE = 13307; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN = 13308; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 13309; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE = 13310; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL = 13311; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 13312; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 13313; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 13314; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 13315; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE = 13316; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN = 13317; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DONE = 13318; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ECC_MODE = 13319; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE = 13320; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN = 13321; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 13322; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE = 13323; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL = 13324; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 13325; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 13326; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 13327; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 13328; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE = 13329; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN = 13330; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DONE = 13331; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ECC_MODE = 13332; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE = 13333; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN = 13334; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 13335; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE = 13336; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL = 13337; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 13338; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 13339; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 13340; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 13341; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE = 13342; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN = 13343; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DONE = 13344; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ECC_MODE = 13345; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE = 13346; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN = 13347; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 13348; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE = 13349; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL = 13350; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 13351; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 13352; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 13353; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 13354; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE = 13355; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN = 13356; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DONE = 13357; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ECC_MODE = 13358; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE = 13359; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN = 13360; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 13361; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE = 13362; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL = 13363; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 13364; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 13365; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 13366; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 13367; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE = 13368; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN = 13369; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DONE = 13370; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ECC_MODE = 13371; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE = 13372; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN = 13373; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 13374; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE = 13375; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL = 13376; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 13377; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 13378; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 13379; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 13380; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE = 13381; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN = 13382; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DONE = 13383; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ECC_MODE = 13384; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE = 13385; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN = 13386; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 13387; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE = 13388; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL = 13389; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 13390; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 13391; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 13392; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 13393; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE = 13394; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN = 13395; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DONE = 13396; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ECC_MODE = 13397; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE = 13398; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN = 13399; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 13400; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE = 13401; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL = 13402; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 13403; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 13404; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 13405; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 13406; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE = 13407; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN = 13408; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DONE = 13409; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ECC_MODE = 13410; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE = 13411; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN = 13412; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 13413; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE = 13414; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL = 13415; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 13416; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 13417; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 13418; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 13419; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE = 13420; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN = 13421; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DONE = 13422; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ECC_MODE = 13423; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE = 13424; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN = 13425; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 13426; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE = 13427; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL = 13428; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 13429; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 13430; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 13431; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 13432; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE = 13433; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN = 13434; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DONE = 13435; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ECC_MODE = 13436; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE = 13437; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN = 13438; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 13439; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE = 13440; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL = 13441; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 13442; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 13443; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 13444; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 13445; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE = 13446; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN = 13447; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DONE = 13448; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ECC_MODE = 13449; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE = 13450; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN = 13451; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 13452; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE = 13453; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL = 13454; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 13455; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 13456; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 13457; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 13458; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE = 13459; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN = 13460; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DONE = 13461; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ECC_MODE = 13462; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE = 13463; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN = 13464; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 13465; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE = 13466; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL = 13467; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 13468; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 13469; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 13470; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 13471; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE = 13472; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN = 13473; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DONE = 13474; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ECC_MODE = 13475; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE = 13476; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN = 13477; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 13478; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE = 13479; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL = 13480; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 13481; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 13482; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 13483; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 13484; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE = 13485; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN = 13486; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DONE = 13487; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ECC_MODE = 13488; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE = 13489; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN = 13490; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 13491; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE = 13492; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL = 13493; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 13494; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 13495; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 13496; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 13497; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE = 13498; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN = 13499; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DONE = 13500; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ECC_MODE = 13501; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE = 13502; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN = 13503; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 13504; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE = 13505; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL = 13506; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 13507; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 13508; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 13509; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 13510; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE = 13511; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN = 13512; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DONE = 13513; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ECC_MODE = 13514; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE = 13515; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN = 13516; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 13517; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE = 13518; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL = 13519; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 13520; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 13521; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 13522; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 13523; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE = 13524; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN = 13525; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DONE = 13526; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ECC_MODE = 13527; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE = 13528; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN = 13529; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 13530; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE = 13531; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL = 13532; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 13533; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 13534; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 13535; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 13536; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE = 13537; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN = 13538; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DONE = 13539; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ECC_MODE = 13540; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE = 13541; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN = 13542; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 13543; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE = 13544; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL = 13545; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 13546; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 13547; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 13548; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 13549; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE = 13550; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN = 13551; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DONE = 13552; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ECC_MODE = 13553; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE = 13554; // 2 +static const uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN = 13555; // 2 +static const uint64_t SH_FLD_MCBIST_DATA_ERROR = 13556; // 2 +static const uint64_t SH_FLD_MCBIST_FSM_INJ_MODE = 13557; // 2 +static const uint64_t SH_FLD_MCBIST_FSM_INJ_REG = 13558; // 2 +static const uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK = 13559; // 8 +static const uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN = 13560; // 8 +static const uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 13561; // 2 +static const uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 13562; // 2 +static const uint64_t SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR = 13563; // 8 +static const uint64_t SH_FLD_MCBIST_PROGRAM_COMPLETE = 13564; // 2 +static const uint64_t SH_FLD_MCBIST_SUBTEST_IP = 13565; // 2 +static const uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR = 13566; // 2 +static const uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 13567; // 2 +static const uint64_t SH_FLD_MCBIST_TRAP_CE_ENABLE = 13568; // 8 +static const uint64_t SH_FLD_MCBIST_TRAP_MPE_ENABLE = 13569; // 8 +static const uint64_t SH_FLD_MCBIST_TRAP_NONSTOP = 13570; // 8 +static const uint64_t SH_FLD_MCBIST_TRAP_UE_ENABLE = 13571; // 8 +static const uint64_t SH_FLD_MCB_CNTLQ_PE_HOLD_OUT = 13572; // 2 +static const uint64_t SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT = 13573; // 2 +static const uint64_t SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 13574; // 2 +static const uint64_t SH_FLD_MCD_ACK_DEAD_CRESP_ERR = 13575; // 2 +static const uint64_t SH_FLD_MCD_ARRAY_ECC_CE_ERR = 13576; // 2 +static const uint64_t SH_FLD_MCD_ARRAY_ECC_UE_ERR = 13577; // 2 +static const uint64_t SH_FLD_MCD_CHICKEN_SWITCH = 13578; // 2 +static const uint64_t SH_FLD_MCD_CL_PROBE_PB_HANG_ERR = 13579; // 2 +static const uint64_t SH_FLD_MCD_CRESP_ADDR_ERR = 13580; // 2 +static const uint64_t SH_FLD_MCD_PB_ADDR_PARITY_ERR = 13581; // 2 +static const uint64_t SH_FLD_MCD_SCOM_ERR = 13582; // 2 +static const uint64_t SH_FLD_MCD_SCOM_ERR_DUP = 13583; // 2 +static const uint64_t SH_FLD_MCD_SM_OR_CASE_ERR = 13584; // 2 +static const uint64_t SH_FLD_MCD_TTAG_PARITY_ERR = 13585; // 2 +static const uint64_t SH_FLD_MCD_UNSOLICITED_CRESP_ERR = 13586; // 2 +static const uint64_t SH_FLD_MCD_UPDATE_ERR = 13587; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL0_COUNT = 13588; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL0_COUNT_LEN = 13589; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL1_COUNT = 13590; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL1_COUNT_LEN = 13591; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL2_COUNT = 13592; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL2_COUNT_LEN = 13593; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL3_COUNT = 13594; // 2 +static const uint64_t SH_FLD_MCE_SYMBOL3_COUNT_LEN = 13595; // 2 +static const uint64_t SH_FLD_MCMD = 13596; // 24 +static const uint64_t SH_FLD_MCMD_LEN = 13597; // 24 +static const uint64_t SH_FLD_MCMODE0_64B_WR_IS_PWRT = 13598; // 4 +static const uint64_t SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS = 13599; // 4 +static const uint64_t SH_FLD_MCRSP0_PARITY_CHECK = 13600; // 3 +static const uint64_t SH_FLD_MCS01_TC_0_FIR_HOST_ATTN = 13601; // 1 +static const uint64_t SH_FLD_MCS01_TC_1_FIR_HOST_ATTN = 13602; // 1 +static const uint64_t SH_FLD_MCS23_TC_0_FIR_HOST_ATTN = 13603; // 1 +static const uint64_t SH_FLD_MCS23_TC_1_FIR_HOST_ATTN = 13604; // 1 +static const uint64_t SH_FLD_MCS_RESET_KEEPER = 13605; // 4 +static const uint64_t SH_FLD_MCS_WAT0 = 13606; // 4 +static const uint64_t SH_FLD_MCS_WAT1 = 13607; // 4 +static const uint64_t SH_FLD_MCS_WAT2 = 13608; // 4 +static const uint64_t SH_FLD_MCS_WAT3 = 13609; // 4 +static const uint64_t SH_FLD_MCWATDATA0 = 13610; // 4 +static const uint64_t SH_FLD_MCWATDATA0_LEN = 13611; // 4 +static const uint64_t SH_FLD_MC_CHANNELS_PER_GROUP = 13612; // 4 +static const uint64_t SH_FLD_MC_CHANNELS_PER_GROUP_LEN = 13613; // 4 +static const uint64_t SH_FLD_MC_FP_MATE_CMD_ERR0 = 13614; // 12 +static const uint64_t SH_FLD_MC_FP_MATE_CMD_ERR1 = 13615; // 12 +static const uint64_t SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR = 13616; // 4 +static const uint64_t SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR = 13617; // 4 +static const uint64_t SH_FLD_MC_TC_0_FIR_HOST_ATTN = 13618; // 2 +static const uint64_t SH_FLD_MC_TC_1_FIR_HOST_ATTN = 13619; // 2 +static const uint64_t SH_FLD_MC_TC_2_FIR_HOST_ATTN = 13620; // 2 +static const uint64_t SH_FLD_MC_TC_3_FIR_HOST_ATTN = 13621; // 2 +static const uint64_t SH_FLD_MC_TC_4_FIR_HOST_ATTN = 13622; // 2 +static const uint64_t SH_FLD_MC_TC_5_FIR_HOST_ATTN = 13623; // 2 +static const uint64_t SH_FLD_MC_TC_6_FIR_HOST_ATTN = 13624; // 2 +static const uint64_t SH_FLD_MC_TC_7_FIR_HOST_ATTN = 13625; // 2 +static const uint64_t SH_FLD_MC_TC_8_FIR_HOST_ATTN = 13626; // 2 +static const uint64_t SH_FLD_MD5_LATENCY_CFG = 13627; // 1 +static const uint64_t SH_FLD_MDA_M1A_DATA_AREA = 13628; // 16 +static const uint64_t SH_FLD_MDA_M1A_DATA_AREA_LEN = 13629; // 16 +static const uint64_t SH_FLD_MDA_M1B_DATA_AREA = 13630; // 16 +static const uint64_t SH_FLD_MDA_M1B_DATA_AREA_LEN = 13631; // 16 +static const uint64_t SH_FLD_MDA_M2A_DATA_AREA = 13632; // 16 +static const uint64_t SH_FLD_MDA_M2A_DATA_AREA_LEN = 13633; // 16 +static const uint64_t SH_FLD_MDA_M2B_DATA_AREA = 13634; // 16 +static const uint64_t SH_FLD_MDA_M2B_DATA_AREA_LEN = 13635; // 16 +static const uint64_t SH_FLD_MDI_0 = 13636; // 8 +static const uint64_t SH_FLD_MDI_1 = 13637; // 8 +static const uint64_t SH_FLD_MDLYR_PARITY_CHECK = 13638; // 3 +static const uint64_t SH_FLD_ME = 13639; // 96 +static const uint64_t SH_FLD_MEASURE = 13640; // 1 +static const uint64_t SH_FLD_MEASURE_VOLT_LT = 13641; // 43 +static const uint64_t SH_FLD_MED_IDLE_COUNT = 13642; // 8 +static const uint64_t SH_FLD_MED_IDLE_COUNT_LEN = 13643; // 8 +static const uint64_t SH_FLD_MED_IDLE_THRESHOLD = 13644; // 8 +static const uint64_t SH_FLD_MED_IDLE_THRESHOLD_LEN = 13645; // 8 +static const uint64_t SH_FLD_MEGAMOUTH = 13646; // 24 +static const uint64_t SH_FLD_MEM = 13647; // 26 +static const uint64_t SH_FLD_MEMCTL_CIC_FAST = 13648; // 8 +static const uint64_t SH_FLD_MEMCTL_CTRN_IGNORE = 13649; // 8 +static const uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP = 13650; // 4 +static const uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 13651; // 4 +static const uint64_t SH_FLD_MEMORY_TYPE = 13652; // 8 +static const uint64_t SH_FLD_MEMORY_TYPE_LEN = 13653; // 8 +static const uint64_t SH_FLD_MEM_ADDR = 13654; // 21 +static const uint64_t SH_FLD_MEM_ADDR_LEN = 13655; // 21 +static const uint64_t SH_FLD_MEM_BUSY = 13656; // 21 +static const uint64_t SH_FLD_MEM_BYTE_ENABLE = 13657; // 21 +static const uint64_t SH_FLD_MEM_BYTE_ENABLE_LEN = 13658; // 21 +static const uint64_t SH_FLD_MEM_CRDT_WINDOW = 13659; // 24 +static const uint64_t SH_FLD_MEM_CRDT_WINDOW_LEN = 13660; // 24 +static const uint64_t SH_FLD_MEM_DATAOP_PENDING = 13661; // 21 +static const uint64_t SH_FLD_MEM_ERROR = 13662; // 21 +static const uint64_t SH_FLD_MEM_ERROR_LEN = 13663; // 21 +static const uint64_t SH_FLD_MEM_HIGH_PRIORITY = 13664; // 4 +static const uint64_t SH_FLD_MEM_HIGH_PRIORITY_LEN = 13665; // 4 +static const uint64_t SH_FLD_MEM_IFETCH_PENDING = 13666; // 21 +static const uint64_t SH_FLD_MEM_IMPRECISE_ERROR_PENDING = 13667; // 21 +static const uint64_t SH_FLD_MEM_LEN = 13668; // 26 +static const uint64_t SH_FLD_MEM_LINE_MODE = 13669; // 21 +static const uint64_t SH_FLD_MEM_LOW_PRIORITY = 13670; // 4 +static const uint64_t SH_FLD_MEM_LOW_PRIORITY_LEN = 13671; // 4 +static const uint64_t SH_FLD_MEM_OP_LIMIT = 13672; // 24 +static const uint64_t SH_FLD_MEM_OP_LIMIT_LEN = 13673; // 24 +static const uint64_t SH_FLD_MEM_R_NW = 13674; // 21 +static const uint64_t SH_FLD_MEM_SIZE = 13675; // 6 +static const uint64_t SH_FLD_MEM_SIZE_LEN = 13676; // 6 +static const uint64_t SH_FLD_MENP0_PARITY_CHECK = 13677; // 3 +static const uint64_t SH_FLD_MER = 13678; // 96 +static const uint64_t SH_FLD_MERGE_CAPACITY_LIMIT = 13679; // 12 +static const uint64_t SH_FLD_MERGE_CAPACITY_LIMIT_LEN = 13680; // 12 +static const uint64_t SH_FLD_MESSAGE_BITS0 = 13681; // 15 +static const uint64_t SH_FLD_MESSAGE_BITS0_LEN = 13682; // 15 +static const uint64_t SH_FLD_MESSAGE_BITS1 = 13683; // 15 +static const uint64_t SH_FLD_MESSAGE_BITS1_LEN = 13684; // 15 +static const uint64_t SH_FLD_MESSAGE_BITS2 = 13685; // 12 +static const uint64_t SH_FLD_MESSAGE_BITS2_LEN = 13686; // 12 +static const uint64_t SH_FLD_MESSAGE_BITS3 = 13687; // 12 +static const uint64_t SH_FLD_MESSAGE_BITS3_LEN = 13688; // 12 +static const uint64_t SH_FLD_MESSAGE_BITS4 = 13689; // 12 +static const uint64_t SH_FLD_MESSAGE_BITS4_LEN = 13690; // 12 +static const uint64_t SH_FLD_MFSI_PORT_ID_SELECT = 13691; // 2 +static const uint64_t SH_FLD_MFSI_PORT_ID_SELECT_LEN = 13692; // 2 +static const uint64_t SH_FLD_MFSI_SLAVE_ID_SELECT = 13693; // 2 +static const uint64_t SH_FLD_MFSI_SLAVE_ID_SELECT_LEN = 13694; // 2 +static const uint64_t SH_FLD_MGR_CREDIT = 13695; // 3 +static const uint64_t SH_FLD_MGR_CREDIT_LEN = 13696; // 3 +static const uint64_t SH_FLD_MIB_GPIO = 13697; // 13 +static const uint64_t SH_FLD_MIB_GPIO_LEN = 13698; // 13 +static const uint64_t SH_FLD_MID_CARE_MASK = 13699; // 4 +static const uint64_t SH_FLD_MID_CARE_MASK_LEN = 13700; // 4 +static const uint64_t SH_FLD_MID_MATCH_VALUE = 13701; // 4 +static const uint64_t SH_FLD_MID_MATCH_VALUE_LEN = 13702; // 4 +static const uint64_t SH_FLD_MIG_REG = 13703; // 1 +static const uint64_t SH_FLD_MIG_REG_LEN = 13704; // 1 +static const uint64_t SH_FLD_MIN = 13705; // 1 +static const uint64_t SH_FLD_MINCYCLECNT = 13706; // 3 +static const uint64_t SH_FLD_MINCYCLECNT_LEN = 13707; // 3 +static const uint64_t SH_FLD_MINIKERF = 13708; // 2 +static const uint64_t SH_FLD_MINIKERF_LEN = 13709; // 2 +static const uint64_t SH_FLD_MINOR = 13710; // 25 +static const uint64_t SH_FLD_MINOR_LEN = 13711; // 25 +static const uint64_t SH_FLD_MIN_CYCLE_SAMPLE = 13712; // 12 +static const uint64_t SH_FLD_MIN_CYCLE_SAMPLE_LEN = 13713; // 12 +static const uint64_t SH_FLD_MIN_EYE_HEIGHT = 13714; // 6 +static const uint64_t SH_FLD_MIN_EYE_HEIGHT_LEN = 13715; // 6 +static const uint64_t SH_FLD_MIN_EYE_WIDTH = 13716; // 6 +static const uint64_t SH_FLD_MIN_EYE_WIDTH_LEN = 13717; // 6 +static const uint64_t SH_FLD_MIRROR_ACTION_OCCURRED = 13718; // 4 +static const uint64_t SH_FLD_MISC = 13719; // 10 +static const uint64_t SH_FLD_MISC_BUS0BYTE0 = 13720; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE0_LEN = 13721; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE1 = 13722; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE10 = 13723; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE10_LEN = 13724; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE1_LEN = 13725; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE2 = 13726; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE2_LEN = 13727; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE3 = 13728; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE3_LEN = 13729; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE4 = 13730; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE4_LEN = 13731; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE5 = 13732; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE5_LEN = 13733; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE6 = 13734; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE6_LEN = 13735; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE7 = 13736; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE7_LEN = 13737; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE8 = 13738; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE8_LEN = 13739; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE9 = 13740; // 1 +static const uint64_t SH_FLD_MISC_BUS0BYTE9_LEN = 13741; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE0 = 13742; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE0_LEN = 13743; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE1 = 13744; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE10 = 13745; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE10_LEN = 13746; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE1_LEN = 13747; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE2 = 13748; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE2_LEN = 13749; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE3 = 13750; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE3_LEN = 13751; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE4 = 13752; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE4_LEN = 13753; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE5 = 13754; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE5_LEN = 13755; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE6 = 13756; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE6_LEN = 13757; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE7 = 13758; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE7_LEN = 13759; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE8 = 13760; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE8_LEN = 13761; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE9 = 13762; // 1 +static const uint64_t SH_FLD_MISC_BUS1BYTE9_LEN = 13763; // 1 +static const uint64_t SH_FLD_MISC_CFG = 13764; // 6 +static const uint64_t SH_FLD_MISC_CFG_LEN = 13765; // 6 +static const uint64_t SH_FLD_MISC_CTL_4VS64 = 13766; // 1 +static const uint64_t SH_FLD_MISC_CTL_ACCEPT_PASTE = 13767; // 1 +static const uint64_t SH_FLD_MISC_CTL_CAM_INVAL_DONE = 13768; // 1 +static const uint64_t SH_FLD_MISC_CTL_CAM_LOCATION = 13769; // 1 +static const uint64_t SH_FLD_MISC_CTL_CAM_LOCATION_LEN = 13770; // 1 +static const uint64_t SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT = 13771; // 1 +static const uint64_t SH_FLD_MISC_CTL_ENABLE_WRMON = 13772; // 1 +static const uint64_t SH_FLD_MISC_CTL_HMI_ACTIVE = 13773; // 1 +static const uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL = 13774; // 1 +static const uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC = 13775; // 1 +static const uint64_t SH_FLD_MISC_CTL_PREFETCH_DISABLE = 13776; // 1 +static const uint64_t SH_FLD_MISC_CTL_QUIESCE_REQUEST = 13777; // 1 +static const uint64_t SH_FLD_MISC_CTL_RG_IS_IDLE = 13778; // 1 +static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS = 13779; // 1 +static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS2 = 13780; // 1 +static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS_LEN = 13781; // 1 +static const uint64_t SH_FLD_MISC_CTRL_PERR = 13782; // 1 +static const uint64_t SH_FLD_MISC_DA_ADDR_PERR = 13783; // 1 +static const uint64_t SH_FLD_MISC_DA_OP = 13784; // 1 +static const uint64_t SH_FLD_MISC_INT_RA_PERR = 13785; // 1 +static const uint64_t SH_FLD_MISC_LEN = 13786; // 10 +static const uint64_t SH_FLD_MISC_LENGTH = 13787; // 1 +static const uint64_t SH_FLD_MISC_LENGTH_LEN = 13788; // 1 +static const uint64_t SH_FLD_MISC_LENR = 13789; // 1 +static const uint64_t SH_FLD_MISC_LENR_LEN = 13790; // 1 +static const uint64_t SH_FLD_MISC_NMMU_ERR = 13791; // 1 +static const uint64_t SH_FLD_MISC_RESYNC_OSC_FROM = 13792; // 1 +static const uint64_t SH_FLD_MISC_RING_ERR = 13793; // 1 +static const uint64_t SH_FLD_MISC_RNW = 13794; // 1 +static const uint64_t SH_FLD_MISC_RSVD = 13795; // 1 +static const uint64_t SH_FLD_MISC_RSVD_LEN = 13796; // 1 +static const uint64_t SH_FLD_MISR_A_VAL = 13797; // 43 +static const uint64_t SH_FLD_MISR_A_VAL_LEN = 13798; // 43 +static const uint64_t SH_FLD_MISR_B_VAL = 13799; // 43 +static const uint64_t SH_FLD_MISR_B_VAL_LEN = 13800; // 43 +static const uint64_t SH_FLD_MISR_INIT_WAIT = 13801; // 43 +static const uint64_t SH_FLD_MISR_INIT_WAIT_LEN = 13802; // 43 +static const uint64_t SH_FLD_MISR_MODE = 13803; // 43 +static const uint64_t SH_FLD_MLC_ACCESS_ERR_ESR = 13804; // 1 +static const uint64_t SH_FLD_MMCR0 = 13805; // 24 +static const uint64_t SH_FLD_MMCR1 = 13806; // 24 +static const uint64_t SH_FLD_MMCR2 = 13807; // 24 +static const uint64_t SH_FLD_MMCRA = 13808; // 24 +static const uint64_t SH_FLD_MMCRC = 13809; // 24 +static const uint64_t SH_FLD_MMIO = 13810; // 15 +static const uint64_t SH_FLD_MMIOSD = 13811; // 1 +static const uint64_t SH_FLD_MMIO_BAR_PE = 13812; // 1 +static const uint64_t SH_FLD_MMIO_CTL_ACTYPE = 13813; // 1 +static const uint64_t SH_FLD_MMIO_CTL_COMP = 13814; // 1 +static const uint64_t SH_FLD_MMIO_CTL_INIT = 13815; // 1 +static const uint64_t SH_FLD_MMIO_CTL_OFFSET = 13816; // 1 +static const uint64_t SH_FLD_MMIO_CTL_OFFSET_LEN = 13817; // 1 +static const uint64_t SH_FLD_MMIO_CTL_OPTYPE = 13818; // 1 +static const uint64_t SH_FLD_MMIO_CTL_OP_ERR = 13819; // 1 +static const uint64_t SH_FLD_MMIO_CTL_UNUSED = 13820; // 1 +static const uint64_t SH_FLD_MMIO_CTL_UNUSED_LEN = 13821; // 1 +static const uint64_t SH_FLD_MMIO_CTL_WINID = 13822; // 1 +static const uint64_t SH_FLD_MMIO_CTL_WINID_LEN = 13823; // 1 +static const uint64_t SH_FLD_MMIO_DATA = 13824; // 1 +static const uint64_t SH_FLD_MMIO_DATA_IN = 13825; // 6 +static const uint64_t SH_FLD_MMIO_DATA_LEN = 13826; // 1 +static const uint64_t SH_FLD_MMIO_ECC = 13827; // 1 +static const uint64_t SH_FLD_MMIO_ECC_LEN = 13828; // 1 +static const uint64_t SH_FLD_MMIO_HYP_RD_ADDR_ERR = 13829; // 2 +static const uint64_t SH_FLD_MMIO_HYP_WR_ADDR_ERR = 13830; // 2 +static const uint64_t SH_FLD_MMIO_LDST_TIMEOUT = 13831; // 1 +static const uint64_t SH_FLD_MMIO_LDST_TIMEOUT_LEN = 13832; // 1 +static const uint64_t SH_FLD_MMIO_NON8B_HYP_ERR = 13833; // 2 +static const uint64_t SH_FLD_MMIO_NON8B_OS_ERR = 13834; // 2 +static const uint64_t SH_FLD_MMIO_OS_RD_ADDR_ERR = 13835; // 2 +static const uint64_t SH_FLD_MMIO_OS_WR_ADDR_ERR = 13836; // 2 +static const uint64_t SH_FLD_MMIO_PG_REG_ACCESS = 13837; // 4 +static const uint64_t SH_FLD_MMIO_REQUEST_TIMEOUT = 13838; // 30 +static const uint64_t SH_FLD_MMODE_PARITY_CHECK = 13839; // 3 +static const uint64_t SH_FLD_MMR = 13840; // 1 +static const uint64_t SH_FLD_MMR_LEN = 13841; // 1 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00 = 13842; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN = 13843; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01 = 13844; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN = 13845; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02 = 13846; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN = 13847; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03 = 13848; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN = 13849; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04 = 13850; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN = 13851; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05 = 13852; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN = 13853; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06 = 13854; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN = 13855; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07 = 13856; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN = 13857; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08 = 13858; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN = 13859; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09 = 13860; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN = 13861; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10 = 13862; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN = 13863; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11 = 13864; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN = 13865; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12 = 13866; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN = 13867; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13 = 13868; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN = 13869; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14 = 13870; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN = 13871; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15 = 13872; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN = 13873; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16 = 13874; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN = 13875; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17 = 13876; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN = 13877; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18 = 13878; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN = 13879; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19 = 13880; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN = 13881; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20 = 13882; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN = 13883; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21 = 13884; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN = 13885; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22 = 13886; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN = 13887; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23 = 13888; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN = 13889; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24 = 13890; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN = 13891; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25 = 13892; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN = 13893; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26 = 13894; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN = 13895; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27 = 13896; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN = 13897; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28 = 13898; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN = 13899; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29 = 13900; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN = 13901; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30 = 13902; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN = 13903; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31 = 13904; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN = 13905; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32 = 13906; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN = 13907; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33 = 13908; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN = 13909; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34 = 13910; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN = 13911; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35 = 13912; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN = 13913; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36 = 13914; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN = 13915; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37 = 13916; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN = 13917; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38 = 13918; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN = 13919; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39 = 13920; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN = 13921; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40 = 13922; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN = 13923; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41 = 13924; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN = 13925; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42 = 13926; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN = 13927; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43 = 13928; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN = 13929; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44 = 13930; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN = 13931; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45 = 13932; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN = 13933; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46 = 13934; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN = 13935; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47 = 13936; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN = 13937; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48 = 13938; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN = 13939; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49 = 13940; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN = 13941; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50 = 13942; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN = 13943; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51 = 13944; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN = 13945; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52 = 13946; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN = 13947; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53 = 13948; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN = 13949; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54 = 13950; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN = 13951; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55 = 13952; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN = 13953; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56 = 13954; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN = 13955; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57 = 13956; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN = 13957; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58 = 13958; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN = 13959; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59 = 13960; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN = 13961; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60 = 13962; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN = 13963; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61 = 13964; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN = 13965; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62 = 13966; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN = 13967; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63 = 13968; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN = 13969; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64 = 13970; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN = 13971; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65 = 13972; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN = 13973; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66 = 13974; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN = 13975; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67 = 13976; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN = 13977; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68 = 13978; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN = 13979; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69 = 13980; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN = 13981; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70 = 13982; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN = 13983; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71 = 13984; // 2 +static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN = 13985; // 2 +static const uint64_t SH_FLD_MODE = 13986; // 9 +static const uint64_t SH_FLD_MODEFSM = 13987; // 36 +static const uint64_t SH_FLD_MODEFSM_LEN = 13988; // 36 +static const uint64_t SH_FLD_MODEREG_SPRC_LT0_SEL = 13989; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT1_SEL = 13990; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT2_SEL = 13991; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT3_SEL = 13992; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT4_SEL = 13993; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT5_SEL = 13994; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT6_SEL = 13995; // 24 +static const uint64_t SH_FLD_MODEREG_SPRC_LT7_SEL = 13996; // 24 +static const uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ = 13997; // 24 +static const uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ_LEN = 13998; // 24 +static const uint64_t SH_FLD_MODE_128K_VP = 13999; // 1 +static const uint64_t SH_FLD_MODE_CX = 14000; // 144 +static const uint64_t SH_FLD_MODE_CX_LEN = 14001; // 144 +static const uint64_t SH_FLD_MODE_ENABLE = 14002; // 24 +static const uint64_t SH_FLD_MODE_LEN = 14003; // 7 +static const uint64_t SH_FLD_MODE_REG0_SPARE = 14004; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE0 = 14005; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE0_LEN = 14006; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE1 = 14007; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE1_LEN = 14008; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE2 = 14009; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE2_LEN = 14010; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE3 = 14011; // 12 +static const uint64_t SH_FLD_MODE_REG1_SPARE3_LEN = 14012; // 12 +static const uint64_t SH_FLD_MODE_REGISTER_0_VALUE = 14013; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_0_VALUE_LEN = 14014; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_1_VALUE = 14015; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_1_VALUE_LEN = 14016; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_2_VALUE = 14017; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_2_VALUE_LEN = 14018; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_3_VALUE = 14019; // 64 +static const uint64_t SH_FLD_MODE_REGISTER_3_VALUE_LEN = 14020; // 64 +static const uint64_t SH_FLD_MODE_SEL = 14021; // 12 +static const uint64_t SH_FLD_MON = 14022; // 12 +static const uint64_t SH_FLD_MON_LEN = 14023; // 12 +static const uint64_t SH_FLD_MOVE_CHIP_TOD_TO_TB = 14024; // 98 +static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS = 14025; // 1 +static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 14026; // 1 +static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN = 14027; // 1 +static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ID = 14028; // 1 +static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ID_LEN = 14029; // 1 +static const uint64_t SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 14030; // 1 +static const uint64_t SH_FLD_MPIPL = 14031; // 8 +static const uint64_t SH_FLD_MPR_PAGE = 14032; // 8 +static const uint64_t SH_FLD_MPR_PAGE_LEN = 14033; // 8 +static const uint64_t SH_FLD_MPR_PATTERN_BIT = 14034; // 8 +static const uint64_t SH_FLD_MPSS_DIS = 14035; // 1 +static const uint64_t SH_FLD_MPW1 = 14036; // 43 +static const uint64_t SH_FLD_MPW2 = 14037; // 43 +static const uint64_t SH_FLD_MPW3 = 14038; // 43 +static const uint64_t SH_FLD_MRBGP = 14039; // 15 +static const uint64_t SH_FLD_MRBGP_LEN = 14040; // 15 +static const uint64_t SH_FLD_MRBSP = 14041; // 15 +static const uint64_t SH_FLD_MRBSP_LEN = 14042; // 15 +static const uint64_t SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR = 14043; // 30 +static const uint64_t SH_FLD_MRG_BBRD_NBUF = 14044; // 3 +static const uint64_t SH_FLD_MRG_BBRD_NBUF_LEN = 14045; // 3 +static const uint64_t SH_FLD_MRG_COMMON_FATAL_ERROR = 14046; // 30 +static const uint64_t SH_FLD_MRG_CR_DIS = 14047; // 3 +static const uint64_t SH_FLD_MRG_CTLW_CR_DIS = 14048; // 3 +static const uint64_t SH_FLD_MRG_ECC_CORRECTABLE_ERROR = 14049; // 30 +static const uint64_t SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR = 14050; // 30 +static const uint64_t SH_FLD_MRG_IBRD_NBUF = 14051; // 3 +static const uint64_t SH_FLD_MRG_IBRD_NBUF_LEN = 14052; // 3 +static const uint64_t SH_FLD_MRG_IBWR_NBUF = 14053; // 3 +static const uint64_t SH_FLD_MRG_IBWR_NBUF_LEN = 14054; // 3 +static const uint64_t SH_FLD_MRG_MRT_ERROR = 14055; // 30 +static const uint64_t SH_FLD_MRG_OBRD_NBUF = 14056; // 3 +static const uint64_t SH_FLD_MRG_OBRD_NBUF_LEN = 14057; // 3 +static const uint64_t SH_FLD_MRG_PBTX_NBUF = 14058; // 3 +static const uint64_t SH_FLD_MRG_PBTX_NBUF_LEN = 14059; // 3 +static const uint64_t SH_FLD_MRG_RDBF_NBUF = 14060; // 3 +static const uint64_t SH_FLD_MRG_RDBF_NBUF_LEN = 14061; // 3 +static const uint64_t SH_FLD_MRG_RESERVED01 = 14062; // 30 +static const uint64_t SH_FLD_MRG_RESERVED02 = 14063; // 30 +static const uint64_t SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR = 14064; // 30 +static const uint64_t SH_FLD_MRS_CMD_DQ_OFF = 14065; // 8 +static const uint64_t SH_FLD_MRS_CMD_DQ_OFF_LEN = 14066; // 8 +static const uint64_t SH_FLD_MRS_CMD_DQ_ON = 14067; // 8 +static const uint64_t SH_FLD_MRS_CMD_DQ_ON_LEN = 14068; // 8 +static const uint64_t SH_FLD_MRT_ERR_NOT_VALID = 14069; // 1 +static const uint64_t SH_FLD_MRT_ERR_PSIZE = 14070; // 1 +static const uint64_t SH_FLD_MR_BLOCK_HMI_IN_MAINT = 14071; // 24 +static const uint64_t SH_FLD_MR_DIS_PMON_INTR = 14072; // 24 +static const uint64_t SH_FLD_MR_FENCE_INTERRUPTS = 14073; // 24 +static const uint64_t SH_FLD_MR_FENCE_INTR_ON_CHECKSTOP = 14074; // 24 +static const uint64_t SH_FLD_MR_MASK_EN = 14075; // 8 +static const uint64_t SH_FLD_MR_MASK_EN_LEN = 14076; // 8 +static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 14077; // 1 +static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 14078; // 1 +static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 14079; // 1 +static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 14080; // 1 +static const uint64_t SH_FLD_MSADES_CLEAR_1 = 14081; // 1 +static const uint64_t SH_FLD_MSADES_CLEAR_2 = 14082; // 1 +static const uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 14083; // 1 +static const uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 14084; // 1 +static const uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 14085; // 1 +static const uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 14086; // 1 +static const uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_1 = 14087; // 1 +static const uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_2 = 14088; // 1 +static const uint64_t SH_FLD_MSADES_UNUSED_15_12 = 14089; // 1 +static const uint64_t SH_FLD_MSADES_UNUSED_15_12_LEN = 14090; // 1 +static const uint64_t SH_FLD_MSADES_UNUSED_31_28 = 14091; // 1 +static const uint64_t SH_FLD_MSADES_UNUSED_31_28_LEN = 14092; // 1 +static const uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_1 = 14093; // 1 +static const uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_2 = 14094; // 1 +static const uint64_t SH_FLD_MSADI_PIB_ERROR_1 = 14095; // 1 +static const uint64_t SH_FLD_MSADI_PIB_ERROR_2 = 14096; // 1 +static const uint64_t SH_FLD_MSADI_PIB_PENDING_1 = 14097; // 1 +static const uint64_t SH_FLD_MSADI_PIB_PENDING_2 = 14098; // 1 +static const uint64_t SH_FLD_MSADI_UNUSED_31_11 = 14099; // 4 +static const uint64_t SH_FLD_MSADI_UNUSED_31_11_LEN = 14100; // 4 +static const uint64_t SH_FLD_MSADI_UNUSED_7_3 = 14101; // 1 +static const uint64_t SH_FLD_MSADI_UNUSED_7_3_LEN = 14102; // 1 +static const uint64_t SH_FLD_MSADI_XUP_1 = 14103; // 1 +static const uint64_t SH_FLD_MSADI_XUP_2 = 14104; // 1 +static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 14105; // 1 +static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 14106; // 1 +static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 14107; // 1 +static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 14108; // 1 +static const uint64_t SH_FLD_MSBDES_CLEAR_1 = 14109; // 1 +static const uint64_t SH_FLD_MSBDES_CLEAR_2 = 14110; // 1 +static const uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 14111; // 1 +static const uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 14112; // 1 +static const uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 14113; // 1 +static const uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 14114; // 1 +static const uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 = 14115; // 1 +static const uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 = 14116; // 1 +static const uint64_t SH_FLD_MSBDES_UNUSED_15_12 = 14117; // 1 +static const uint64_t SH_FLD_MSBDES_UNUSED_15_12_LEN = 14118; // 1 +static const uint64_t SH_FLD_MSBDES_UNUSED_31_28 = 14119; // 1 +static const uint64_t SH_FLD_MSBDES_UNUSED_31_28_LEN = 14120; // 1 +static const uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 = 14121; // 1 +static const uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 = 14122; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT = 14123; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT_2 = 14124; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR = 14125; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 = 14126; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING = 14127; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 = 14128; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_XDN = 14129; // 1 +static const uint64_t SH_FLD_MSBDIM1_ENABLE_XDN_2 = 14130; // 1 +static const uint64_t SH_FLD_MSBDI_ABORT_MAILBOX_1 = 14131; // 1 +static const uint64_t SH_FLD_MSBDI_ABORT_MAILBOX_2 = 14132; // 1 +static const uint64_t SH_FLD_MSBDI_LBUS_ERROR_1 = 14133; // 1 +static const uint64_t SH_FLD_MSBDI_LBUS_ERROR_2 = 14134; // 1 +static const uint64_t SH_FLD_MSBDI_LBUS_PENDING_1 = 14135; // 1 +static const uint64_t SH_FLD_MSBDI_LBUS_PENDING_2 = 14136; // 1 +static const uint64_t SH_FLD_MSBDI_XDN_1 = 14137; // 1 +static const uint64_t SH_FLD_MSBDI_XDN_2 = 14138; // 1 +static const uint64_t SH_FLD_MSBSWAP = 14139; // 4 +static const uint64_t SH_FLD_MSC_BUS0_STG0_SEL = 14140; // 1 +static const uint64_t SH_FLD_MSC_BUS0_STG0_SEL_LEN = 14141; // 1 +static const uint64_t SH_FLD_MSC_BUS0_STG1_SEL = 14142; // 1 +static const uint64_t SH_FLD_MSC_BUS0_STG2_SEL = 14143; // 1 +static const uint64_t SH_FLD_MSC_BUS1_STG0_SEL = 14144; // 1 +static const uint64_t SH_FLD_MSC_BUS1_STG0_SEL_LEN = 14145; // 1 +static const uint64_t SH_FLD_MSC_BUS1_STG1_SEL = 14146; // 1 +static const uint64_t SH_FLD_MSC_BUS1_STG2_SEL = 14147; // 1 +static const uint64_t SH_FLD_MSGSND_ACK = 14148; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_INJECT = 14149; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_INJECT_LEN = 14150; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_PRESENT = 14151; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_PRESENT_LEN = 14152; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_REQUESTED = 14153; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_REQUESTED_LEN = 14154; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_SAMPLE = 14155; // 24 +static const uint64_t SH_FLD_MSGSND_INTR_SAMPLE_LEN = 14156; // 24 +static const uint64_t SH_FLD_MSG_ADDR_ERR = 14157; // 12 +static const uint64_t SH_FLD_MSIEP0_PARITY_CHECK = 14158; // 3 +static const uint64_t SH_FLD_MSK = 14159; // 5 +static const uint64_t SH_FLD_MSK_LEN = 14160; // 5 +static const uint64_t SH_FLD_MSM_CURR_STATE_0 = 14161; // 2 +static const uint64_t SH_FLD_MSM_CURR_STATE_0_LEN = 14162; // 2 +static const uint64_t SH_FLD_MSM_CURR_STATE_1 = 14163; // 1 +static const uint64_t SH_FLD_MSM_CURR_STATE_1_LEN = 14164; // 1 +static const uint64_t SH_FLD_MSM_CURR_STATE_2 = 14165; // 1 +static const uint64_t SH_FLD_MSM_CURR_STATE_2_LEN = 14166; // 1 +static const uint64_t SH_FLD_MSM_CURR_STATE_3 = 14167; // 1 +static const uint64_t SH_FLD_MSM_CURR_STATE_3_LEN = 14168; // 1 +static const uint64_t SH_FLD_MSR_DR = 14169; // 256 +static const uint64_t SH_FLD_MSR_HV = 14170; // 256 +static const uint64_t SH_FLD_MSR_PE = 14171; // 8 +static const uint64_t SH_FLD_MSR_PR = 14172; // 256 +static const uint64_t SH_FLD_MSR_SF = 14173; // 256 +static const uint64_t SH_FLD_MSR_TA = 14174; // 256 +static const uint64_t SH_FLD_MSR_US = 14175; // 256 +static const uint64_t SH_FLD_MSR_UV = 14176; // 256 +static const uint64_t SH_FLD_MSSIEP0_PARITY_CHECK = 14177; // 3 +static const uint64_t SH_FLD_MST_DIS_ABUSPAREN = 14178; // 1 +static const uint64_t SH_FLD_MST_DIS_BEPAREN = 14179; // 1 +static const uint64_t SH_FLD_MST_DIS_RDDBUSPAR = 14180; // 1 +static const uint64_t SH_FLD_MST_DIS_WRDBUSPAREN = 14181; // 1 +static const uint64_t SH_FLD_MST_SPARE = 14182; // 1 +static const uint64_t SH_FLD_MS_GROUP_CHIP = 14183; // 2 +static const uint64_t SH_FLD_MS_GROUP_CHIP_LEN = 14184; // 2 +static const uint64_t SH_FLD_MS_WAT_DEBUG_CONFIG_REG_ERROR = 14185; // 4 +static const uint64_t SH_FLD_MTL = 14186; // 96 +static const uint64_t SH_FLD_MTL_LEN = 14187; // 96 +static const uint64_t SH_FLD_MULTICAST1 = 14188; // 43 +static const uint64_t SH_FLD_MULTICAST1_LEN = 14189; // 43 +static const uint64_t SH_FLD_MULTICAST2 = 14190; // 43 +static const uint64_t SH_FLD_MULTICAST2_LEN = 14191; // 43 +static const uint64_t SH_FLD_MULTICAST3 = 14192; // 43 +static const uint64_t SH_FLD_MULTICAST3_LEN = 14193; // 43 +static const uint64_t SH_FLD_MULTICAST4 = 14194; // 43 +static const uint64_t SH_FLD_MULTICAST4_LEN = 14195; // 43 +static const uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER = 14196; // 2 +static const uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER_LEN = 14197; // 2 +static const uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER = 14198; // 1 +static const uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 14199; // 1 +static const uint64_t SH_FLD_MULTIHIT_CHK_DIS = 14200; // 2 +static const uint64_t SH_FLD_MULTIPLE_BAR = 14201; // 4 +static const uint64_t SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED = 14202; // 12 +static const uint64_t SH_FLD_MULTIPLE_REQ = 14203; // 8 +static const uint64_t SH_FLD_MULTIPLE_REQ_SOURCE = 14204; // 8 +static const uint64_t SH_FLD_MULTIPLE_REQ_SOURCE_LEN = 14205; // 8 +static const uint64_t SH_FLD_MULT_REQ_ERR_MASK = 14206; // 8 +static const uint64_t SH_FLD_MUOP_ERROR_1 = 14207; // 4 +static const uint64_t SH_FLD_MUOP_ERROR_2 = 14208; // 4 +static const uint64_t SH_FLD_MUOP_ERROR_3 = 14209; // 4 +static const uint64_t SH_FLD_MUXEN = 14210; // 4 +static const uint64_t SH_FLD_MUXSEL = 14211; // 4 +static const uint64_t SH_FLD_MUXSEL_LEN = 14212; // 4 +static const uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE = 14213; // 1 +static const uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN = 14214; // 1 +static const uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE = 14215; // 1 +static const uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN = 14216; // 1 +static const uint64_t SH_FLD_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 14217; // 3 +static const uint64_t SH_FLD_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 14218; // 3 +static const uint64_t SH_FLD_M_ANY_MASTER_ERROR = 14219; // 3 +static const uint64_t SH_FLD_M_ANY_PORT_INTERRUPT = 14220; // 3 +static const uint64_t SH_FLD_M_CONTROL_REGISTER_PARITY_INTERRUPT = 14221; // 3 +static const uint64_t SH_FLD_M_CPS_ENABLE = 14222; // 1 +static const uint64_t SH_FLD_M_HOT_PLUG_EVENT = 14223; // 3 +static const uint64_t SH_FLD_M_PATH_0_OSC_NOT_VALID = 14224; // 1 +static const uint64_t SH_FLD_M_PATH_0_PARITY = 14225; // 4 +static const uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 14226; // 1 +static const uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 14227; // 1 +static const uint64_t SH_FLD_M_PATH_0_STEP_CHECK = 14228; // 4 +static const uint64_t SH_FLD_M_PATH_0_STEP_CHECK_VALID = 14229; // 1 +static const uint64_t SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 14230; // 1 +static const uint64_t SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 14231; // 1 +static const uint64_t SH_FLD_M_PATH_1_OSC_NOT_VALID = 14232; // 1 +static const uint64_t SH_FLD_M_PATH_1_PARITY = 14233; // 4 +static const uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 14234; // 1 +static const uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 14235; // 1 +static const uint64_t SH_FLD_M_PATH_1_STEP_CHECK = 14236; // 4 +static const uint64_t SH_FLD_M_PATH_1_STEP_CHECK_VALID = 14237; // 1 +static const uint64_t SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 14238; // 1 +static const uint64_t SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 14239; // 1 +static const uint64_t SH_FLD_M_PATH_CLOCK_OFF_ENABLE = 14240; // 1 +static const uint64_t SH_FLD_M_PATH_SELECT = 14241; // 1 +static const uint64_t SH_FLD_M_PATH_SWITCH_TRIGGER = 14242; // 1 +static const uint64_t SH_FLD_N0DGD = 14243; // 12 +static const uint64_t SH_FLD_N0REQ = 14244; // 12 +static const uint64_t SH_FLD_N0RSP = 14245; // 12 +static const uint64_t SH_FLD_N1DGD = 14246; // 12 +static const uint64_t SH_FLD_N1REQ = 14247; // 12 +static const uint64_t SH_FLD_N1RSP = 14248; // 12 +static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_0 = 14249; // 4 +static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_1 = 14250; // 2 +static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_2 = 14251; // 2 +static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_3 = 14252; // 2 +static const uint64_t SH_FLD_NB_CLEAN_SLOT = 14253; // 6 +static const uint64_t SH_FLD_NB_CLEAN_SLOT_LEN = 14254; // 6 +static const uint64_t SH_FLD_NB_WRITE_SLOT = 14255; // 6 +static const uint64_t SH_FLD_NB_WRITE_SLOT_LEN = 14256; // 6 +static const uint64_t SH_FLD_NCU_POWERBUS_DATA_TIMEOUT = 14257; // 12 +static const uint64_t SH_FLD_NCU_PURGE = 14258; // 12 +static const uint64_t SH_FLD_NCU_PURGE_ABORT = 14259; // 12 +static const uint64_t SH_FLD_NCU_PURGE_DONE = 14260; // 24 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH = 14261; // 1 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN = 14262; // 1 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE = 14263; // 1 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN = 14264; // 1 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE = 14265; // 1 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN = 14266; // 1 +static const uint64_t SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN = 14267; // 1 +static const uint64_t SH_FLD_NCU_TLBIE_QUIESCE = 14268; // 12 +static const uint64_t SH_FLD_NC_N_INDIRECT = 14269; // 48 +static const uint64_t SH_FLD_NC_N_INDIRECT_LEN = 14270; // 48 +static const uint64_t SH_FLD_NDL = 14271; // 6 +static const uint64_t SH_FLD_NDLMUX_BRK0TO2 = 14272; // 1 +static const uint64_t SH_FLD_NDLMUX_BRK0TO2_LEN = 14273; // 1 +static const uint64_t SH_FLD_NDL_BRK0_NOSTALL = 14274; // 1 +static const uint64_t SH_FLD_NDL_BRK0_STALL = 14275; // 1 +static const uint64_t SH_FLD_NDL_BRK1_NOSTALL = 14276; // 1 +static const uint64_t SH_FLD_NDL_BRK1_STALL = 14277; // 1 +static const uint64_t SH_FLD_NDL_BRK2_NOSTALL = 14278; // 1 +static const uint64_t SH_FLD_NDL_BRK2_STALL = 14279; // 1 +static const uint64_t SH_FLD_NDL_BRK3_NOSTALL = 14280; // 1 +static const uint64_t SH_FLD_NDL_BRK3_STALL = 14281; // 1 +static const uint64_t SH_FLD_NDL_BRK4_NOSTALL = 14282; // 1 +static const uint64_t SH_FLD_NDL_BRK4_STALL = 14283; // 1 +static const uint64_t SH_FLD_NDL_BRK5_NOSTALL = 14284; // 1 +static const uint64_t SH_FLD_NDL_BRK5_STALL = 14285; // 1 +static const uint64_t SH_FLD_NDL_LEN = 14286; // 6 +static const uint64_t SH_FLD_NDL_PRI_PARITY_ENA = 14287; // 6 +static const uint64_t SH_FLD_NDL_RX_PARITY_ENA = 14288; // 6 +static const uint64_t SH_FLD_NDL_TX_PARITY_ENA = 14289; // 6 +static const uint64_t SH_FLD_NEAR_NODAL_EPSILON = 14290; // 8 +static const uint64_t SH_FLD_NEAR_NODAL_EPSILON_LEN = 14291; // 8 +static const uint64_t SH_FLD_NEST_DBG_SEL_IN = 14292; // 8 +static const uint64_t SH_FLD_NEST_DBG_SEL_WRT = 14293; // 8 +static const uint64_t SH_FLD_NEST_LIMIT = 14294; // 24 +static const uint64_t SH_FLD_NEST_LIMIT_LEN = 14295; // 24 +static const uint64_t SH_FLD_NETWORK_RESET_OCCURRED = 14296; // 30 +static const uint64_t SH_FLD_NEXT_CAL_LANE_SEL = 14297; // 68 +static const uint64_t SH_FLD_NEXT_RANK = 14298; // 8 +static const uint64_t SH_FLD_NEXT_RANK_LEN = 14299; // 8 +static const uint64_t SH_FLD_NEXT_RANK_PAIR = 14300; // 8 +static const uint64_t SH_FLD_NEXT_RANK_PAIR_LEN = 14301; // 8 +static const uint64_t SH_FLD_NFIRACTION0 = 14302; // 9 +static const uint64_t SH_FLD_NFIRACTION0_LEN = 14303; // 9 +static const uint64_t SH_FLD_NFIRACTION1 = 14304; // 9 +static const uint64_t SH_FLD_NFIRACTION1_LEN = 14305; // 9 +static const uint64_t SH_FLD_NFIRMASK = 14306; // 9 +static const uint64_t SH_FLD_NFIRMASK_LEN = 14307; // 9 +static const uint64_t SH_FLD_NFIRNFIR = 14308; // 9 +static const uint64_t SH_FLD_NFIRNFIR_LEN = 14309; // 9 +static const uint64_t SH_FLD_NHTM_SCON_E = 14310; // 4 +static const uint64_t SH_FLD_NMCMD = 14311; // 6 +static const uint64_t SH_FLD_NMCMD_LEN = 14312; // 6 +static const uint64_t SH_FLD_NMEXCMD = 14313; // 6 +static const uint64_t SH_FLD_NMEXCMD_LEN = 14314; // 6 +static const uint64_t SH_FLD_NMMU = 14315; // 3 +static const uint64_t SH_FLD_NMMU_LOCAL_XSTOP = 14316; // 1 +static const uint64_t SH_FLD_NODE_ID = 14317; // 24 +static const uint64_t SH_FLD_NODE_ID_LEN = 14318; // 24 +static const uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS = 14319; // 4 +static const uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS_LEN = 14320; // 4 +static const uint64_t SH_FLD_NONZERO_CSB_CC = 14321; // 1 +static const uint64_t SH_FLD_NOTIFY_FAILED_ERR = 14322; // 2 +static const uint64_t SH_FLD_NOT_TRIGGER_MODE1 = 14323; // 86 +static const uint64_t SH_FLD_NOT_TRIGGER_MODE2 = 14324; // 86 +static const uint64_t SH_FLD_NOT_USED_0 = 14325; // 2 +static const uint64_t SH_FLD_NOT_USED_0_LEN = 14326; // 2 +static const uint64_t SH_FLD_NOT_USED_1 = 14327; // 1 +static const uint64_t SH_FLD_NOT_USED_1_LEN = 14328; // 1 +static const uint64_t SH_FLD_NOT_USED_2 = 14329; // 1 +static const uint64_t SH_FLD_NOT_USED_2_LEN = 14330; // 1 +static const uint64_t SH_FLD_NOT_USED_3 = 14331; // 1 +static const uint64_t SH_FLD_NOT_USED_3_LEN = 14332; // 1 +static const uint64_t SH_FLD_NO_CLK = 14333; // 2 +static const uint64_t SH_FLD_NO_WAIT_ON_CLK_CMD = 14334; // 43 +static const uint64_t SH_FLD_NPU_LXSTOP_ERR_DET = 14335; // 1 +static const uint64_t SH_FLD_NPU_TRANSPORT_SWAP = 14336; // 2 +static const uint64_t SH_FLD_NR_OF_FRAMES = 14337; // 1 +static const uint64_t SH_FLD_NSEG_MAIN_EN = 14338; // 6 +static const uint64_t SH_FLD_NSEG_MAIN_EN_LEN = 14339; // 6 +static const uint64_t SH_FLD_NSEG_MARGINPD_EN = 14340; // 6 +static const uint64_t SH_FLD_NSEG_MARGINPD_EN_LEN = 14341; // 6 +static const uint64_t SH_FLD_NSEG_MARGINPU_EN = 14342; // 6 +static const uint64_t SH_FLD_NSEG_MARGINPU_EN_LEN = 14343; // 6 +static const uint64_t SH_FLD_NSEG_POST_EN = 14344; // 2 +static const uint64_t SH_FLD_NSEG_POST_EN_LEN = 14345; // 2 +static const uint64_t SH_FLD_NSEG_POST_SEL = 14346; // 2 +static const uint64_t SH_FLD_NSEG_POST_SEL_LEN = 14347; // 2 +static const uint64_t SH_FLD_NSEG_PRE_EN = 14348; // 6 +static const uint64_t SH_FLD_NSEG_PRE_EN_LEN = 14349; // 6 +static const uint64_t SH_FLD_NSEG_PRE_SEL = 14350; // 6 +static const uint64_t SH_FLD_NSEG_PRE_SEL_LEN = 14351; // 6 +static const uint64_t SH_FLD_NSL_FILL_COUNT = 14352; // 43 +static const uint64_t SH_FLD_NSL_FILL_COUNT_LEN = 14353; // 43 +static const uint64_t SH_FLD_NSQ_LFSR_CNTL = 14354; // 8 +static const uint64_t SH_FLD_NSQ_LFSR_CNTL_LEN = 14355; // 8 +static const uint64_t SH_FLD_NTLR_PAUSE_THRESH = 14356; // 3 +static const uint64_t SH_FLD_NTLR_PAUSE_THRESH_LEN = 14357; // 3 +static const uint64_t SH_FLD_NTLW_PAUSE_THRESH = 14358; // 3 +static const uint64_t SH_FLD_NTLW_PAUSE_THRESH_LEN = 14359; // 3 +static const uint64_t SH_FLD_NTL_0 = 14360; // 48 +static const uint64_t SH_FLD_NTL_1 = 14361; // 48 +static const uint64_t SH_FLD_NTL_10 = 14362; // 48 +static const uint64_t SH_FLD_NTL_11 = 14363; // 48 +static const uint64_t SH_FLD_NTL_12 = 14364; // 48 +static const uint64_t SH_FLD_NTL_13 = 14365; // 48 +static const uint64_t SH_FLD_NTL_14 = 14366; // 48 +static const uint64_t SH_FLD_NTL_15 = 14367; // 48 +static const uint64_t SH_FLD_NTL_16 = 14368; // 48 +static const uint64_t SH_FLD_NTL_17 = 14369; // 48 +static const uint64_t SH_FLD_NTL_18 = 14370; // 48 +static const uint64_t SH_FLD_NTL_19 = 14371; // 48 +static const uint64_t SH_FLD_NTL_2 = 14372; // 48 +static const uint64_t SH_FLD_NTL_20 = 14373; // 48 +static const uint64_t SH_FLD_NTL_21 = 14374; // 48 +static const uint64_t SH_FLD_NTL_22 = 14375; // 48 +static const uint64_t SH_FLD_NTL_23 = 14376; // 48 +static const uint64_t SH_FLD_NTL_24 = 14377; // 48 +static const uint64_t SH_FLD_NTL_25 = 14378; // 48 +static const uint64_t SH_FLD_NTL_26 = 14379; // 48 +static const uint64_t SH_FLD_NTL_27 = 14380; // 48 +static const uint64_t SH_FLD_NTL_28 = 14381; // 48 +static const uint64_t SH_FLD_NTL_29 = 14382; // 48 +static const uint64_t SH_FLD_NTL_3 = 14383; // 48 +static const uint64_t SH_FLD_NTL_30 = 14384; // 48 +static const uint64_t SH_FLD_NTL_31 = 14385; // 48 +static const uint64_t SH_FLD_NTL_32 = 14386; // 48 +static const uint64_t SH_FLD_NTL_33 = 14387; // 48 +static const uint64_t SH_FLD_NTL_34 = 14388; // 48 +static const uint64_t SH_FLD_NTL_35 = 14389; // 48 +static const uint64_t SH_FLD_NTL_36 = 14390; // 48 +static const uint64_t SH_FLD_NTL_37 = 14391; // 48 +static const uint64_t SH_FLD_NTL_38 = 14392; // 48 +static const uint64_t SH_FLD_NTL_39 = 14393; // 48 +static const uint64_t SH_FLD_NTL_4 = 14394; // 48 +static const uint64_t SH_FLD_NTL_40 = 14395; // 48 +static const uint64_t SH_FLD_NTL_41 = 14396; // 48 +static const uint64_t SH_FLD_NTL_42 = 14397; // 48 +static const uint64_t SH_FLD_NTL_43 = 14398; // 48 +static const uint64_t SH_FLD_NTL_44 = 14399; // 48 +static const uint64_t SH_FLD_NTL_45 = 14400; // 48 +static const uint64_t SH_FLD_NTL_46 = 14401; // 48 +static const uint64_t SH_FLD_NTL_47 = 14402; // 48 +static const uint64_t SH_FLD_NTL_48 = 14403; // 48 +static const uint64_t SH_FLD_NTL_49 = 14404; // 48 +static const uint64_t SH_FLD_NTL_5 = 14405; // 48 +static const uint64_t SH_FLD_NTL_50 = 14406; // 48 +static const uint64_t SH_FLD_NTL_51 = 14407; // 48 +static const uint64_t SH_FLD_NTL_52 = 14408; // 48 +static const uint64_t SH_FLD_NTL_53 = 14409; // 48 +static const uint64_t SH_FLD_NTL_54 = 14410; // 48 +static const uint64_t SH_FLD_NTL_55 = 14411; // 48 +static const uint64_t SH_FLD_NTL_56 = 14412; // 48 +static const uint64_t SH_FLD_NTL_57 = 14413; // 48 +static const uint64_t SH_FLD_NTL_58 = 14414; // 48 +static const uint64_t SH_FLD_NTL_59 = 14415; // 48 +static const uint64_t SH_FLD_NTL_6 = 14416; // 48 +static const uint64_t SH_FLD_NTL_60 = 14417; // 48 +static const uint64_t SH_FLD_NTL_61 = 14418; // 48 +static const uint64_t SH_FLD_NTL_62 = 14419; // 48 +static const uint64_t SH_FLD_NTL_63 = 14420; // 48 +static const uint64_t SH_FLD_NTL_7 = 14421; // 48 +static const uint64_t SH_FLD_NTL_8 = 14422; // 48 +static const uint64_t SH_FLD_NTL_9 = 14423; // 48 +static const uint64_t SH_FLD_NTL_ARRAY_CE = 14424; // 1 +static const uint64_t SH_FLD_NTL_ARRAY_DATA_SUE = 14425; // 1 +static const uint64_t SH_FLD_NTL_ARRAY_DATA_UE = 14426; // 1 +static const uint64_t SH_FLD_NTL_ARRAY_HDR_UE = 14427; // 1 +static const uint64_t SH_FLD_NTL_LMD_POISON = 14428; // 1 +static const uint64_t SH_FLD_NTL_LOGIC_ERR = 14429; // 1 +static const uint64_t SH_FLD_NTL_NVL_CONFIG_ERR = 14430; // 1 +static const uint64_t SH_FLD_NTL_NVL_CRC_ERR = 14431; // 1 +static const uint64_t SH_FLD_NTL_NVL_DATA_PERR = 14432; // 1 +static const uint64_t SH_FLD_NTL_NVL_FLIT_PERR = 14433; // 1 +static const uint64_t SH_FLD_NTL_NVL_PKT_MALFOR = 14434; // 1 +static const uint64_t SH_FLD_NTL_NVL_PKT_UNSUPPORTED = 14435; // 1 +static const uint64_t SH_FLD_NTL_PRI_ERR = 14436; // 1 +static const uint64_t SH_FLD_NTL_RESET = 14437; // 6 +static const uint64_t SH_FLD_NTL_RESET_LEN = 14438; // 6 +static const uint64_t SH_FLD_NTTM_MODE = 14439; // 2 +static const uint64_t SH_FLD_NTTM_RW_DATA_DLY = 14440; // 2 +static const uint64_t SH_FLD_NTTM_RW_DATA_DLY_LEN = 14441; // 2 +static const uint64_t SH_FLD_NULL_MSR_LP = 14442; // 46 +static const uint64_t SH_FLD_NULL_MSR_SIBRC = 14443; // 46 +static const uint64_t SH_FLD_NULL_MSR_SIBRC_LEN = 14444; // 46 +static const uint64_t SH_FLD_NULL_MSR_WE = 14445; // 46 +static const uint64_t SH_FLD_NUM_BLOCKS = 14446; // 12 +static const uint64_t SH_FLD_NUM_BLOCKS_LEN = 14447; // 12 +static const uint64_t SH_FLD_NUM_CLEAN = 14448; // 8 +static const uint64_t SH_FLD_NUM_CLEAN_LEN = 14449; // 8 +static const uint64_t SH_FLD_NUM_CL_ACTIVE = 14450; // 8 +static const uint64_t SH_FLD_NUM_CL_ACTIVE_LEN = 14451; // 8 +static const uint64_t SH_FLD_NUM_GPIO_PORTS = 14452; // 1 +static const uint64_t SH_FLD_NUM_GPIO_PORTS_LEN = 14453; // 1 +static const uint64_t SH_FLD_NUM_HA_RSVD = 14454; // 8 +static const uint64_t SH_FLD_NUM_HA_RSVD_LEN = 14455; // 8 +static const uint64_t SH_FLD_NUM_HA_RSVD_SEL = 14456; // 8 +static const uint64_t SH_FLD_NUM_HA_RSVD_SEL_LEN = 14457; // 8 +static const uint64_t SH_FLD_NUM_HPC_RD_RSVD = 14458; // 8 +static const uint64_t SH_FLD_NUM_HPC_RD_RSVD_LEN = 14459; // 8 +static const uint64_t SH_FLD_NUM_HTM_RSVD = 14460; // 8 +static const uint64_t SH_FLD_NUM_HTM_RSVD_LEN = 14461; // 8 +static const uint64_t SH_FLD_NUM_HTM_RSVD_SEL = 14462; // 8 +static const uint64_t SH_FLD_NUM_HTM_RSVD_SEL_LEN = 14463; // 8 +static const uint64_t SH_FLD_NUM_RMW_BUF = 14464; // 8 +static const uint64_t SH_FLD_NUM_RMW_BUF_LEN = 14465; // 8 +static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD = 14466; // 8 +static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_LEN = 14467; // 8 +static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL = 14468; // 8 +static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN = 14469; // 8 +static const uint64_t SH_FLD_NUM_VALID_SAMPLES = 14470; // 8 +static const uint64_t SH_FLD_NUM_VALID_SAMPLES_LEN = 14471; // 8 +static const uint64_t SH_FLD_NV0_NPU_ENABLED = 14472; // 2 +static const uint64_t SH_FLD_NV1_NPU_ENABLED = 14473; // 2 +static const uint64_t SH_FLD_NV2_NPU_ENABLED = 14474; // 2 +static const uint64_t SH_FLD_NVBE = 14475; // 24 +static const uint64_t SH_FLD_NVDGD0 = 14476; // 3 +static const uint64_t SH_FLD_NVDGD1 = 14477; // 3 +static const uint64_t SH_FLD_NVREQ0 = 14478; // 3 +static const uint64_t SH_FLD_NVREQ1 = 14479; // 3 +static const uint64_t SH_FLD_NVRS0 = 14480; // 3 +static const uint64_t SH_FLD_NVRS1 = 14481; // 3 +static const uint64_t SH_FLD_NV_RESP_RATE1 = 14482; // 12 +static const uint64_t SH_FLD_NV_RESP_RATE1_LEN = 14483; // 12 +static const uint64_t SH_FLD_NV_RESP_RATE2 = 14484; // 12 +static const uint64_t SH_FLD_NV_RESP_RATE2_LEN = 14485; // 12 +static const uint64_t SH_FLD_NX0_LXSTOP_ERR_DET = 14486; // 1 +static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ACTION = 14487; // 1 +static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ENABLE = 14488; // 1 +static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT = 14489; // 1 +static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN = 14490; // 1 +static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_TYPE = 14491; // 1 +static const uint64_t SH_FLD_NXCQ_HANG_SM_ON_ARE = 14492; // 1 +static const uint64_t SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL = 14493; // 1 +static const uint64_t SH_FLD_NXCQ_INJECT_MODE = 14494; // 2 +static const uint64_t SH_FLD_NXCQ_INJECT_MODE_LEN = 14495; // 2 +static const uint64_t SH_FLD_NXCQ_INJECT_TYPE = 14496; // 2 +static const uint64_t SH_FLD_NXCQ_INJECT_TYPE_LEN = 14497; // 2 +static const uint64_t SH_FLD_NXCQ_PBCQ_ARRAY = 14498; // 2 +static const uint64_t SH_FLD_NXCQ_PBCQ_ARRAY_LEN = 14499; // 2 +static const uint64_t SH_FLD_NXCQ_PBCQ_INJECT_ENABLE = 14500; // 2 +static const uint64_t SH_FLD_NXCQ_RNG_INJECT_ACTION = 14501; // 1 +static const uint64_t SH_FLD_NXCQ_RNG_INJECT_ENABLE = 14502; // 1 +static const uint64_t SH_FLD_NXCQ_TRACE_CNTL = 14503; // 2 +static const uint64_t SH_FLD_NXCQ_TRACE_CNTL_LEN = 14504; // 2 +static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_CE_ERRHOLD = 14505; // 2 +static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD = 14506; // 2 +static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_UE_ERRHOLD = 14507; // 2 +static const uint64_t SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD = 14508; // 2 +static const uint64_t SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD = 14509; // 2 +static const uint64_t SH_FLD_NX_DATA_RTAG_PARITY_ERRHOLD = 14510; // 2 +static const uint64_t SH_FLD_NX_FREEZE_MODES = 14511; // 2 +static const uint64_t SH_FLD_NX_FREEZE_MODES_LEN = 14512; // 2 +static const uint64_t SH_FLD_NX_LOCAL_XSTOP = 14513; // 2 +static const uint64_t SH_FLD_NX_PBI_ERR_RPT_OUT = 14514; // 3 +static const uint64_t SH_FLD_NX_PBI_ERR_RPT_OUT_LEN = 14515; // 3 +static const uint64_t SH_FLD_NX_RAND_NUM_GEN_LOCK = 14516; // 1 +static const uint64_t SH_FLD_N_CLKS_PER_STEP = 14517; // 98 +static const uint64_t SH_FLD_N_CLKS_PER_STEP_LEN = 14518; // 98 +static const uint64_t SH_FLD_N_RD_STACK0_OVERRIDE = 14519; // 3 +static const uint64_t SH_FLD_N_RD_STACK0_OVERRIDE_LEN = 14520; // 3 +static const uint64_t SH_FLD_N_RD_STACK1_OVERRIDE = 14521; // 3 +static const uint64_t SH_FLD_N_RD_STACK1_OVERRIDE_LEN = 14522; // 3 +static const uint64_t SH_FLD_N_RD_STACK_OVERRIDE_ENABLE = 14523; // 3 +static const uint64_t SH_FLD_N_ST_STACK0_OVERRIDE = 14524; // 3 +static const uint64_t SH_FLD_N_ST_STACK0_OVERRIDE_LEN = 14525; // 3 +static const uint64_t SH_FLD_N_ST_STACK1_OVERRIDE = 14526; // 3 +static const uint64_t SH_FLD_N_ST_STACK1_OVERRIDE_LEN = 14527; // 3 +static const uint64_t SH_FLD_N_ST_STACK_OVERRIDE_ENABLE = 14528; // 3 +static const uint64_t SH_FLD_N_WR_STACK0_OVERRIDE = 14529; // 6 +static const uint64_t SH_FLD_N_WR_STACK0_OVERRIDE_LEN = 14530; // 6 +static const uint64_t SH_FLD_N_WR_STACK1_OVERRIDE = 14531; // 6 +static const uint64_t SH_FLD_N_WR_STACK1_OVERRIDE_LEN = 14532; // 6 +static const uint64_t SH_FLD_N_WR_STACK_OVERRIDE_ENABLE = 14533; // 6 +static const uint64_t SH_FLD_O = 14534; // 1 +static const uint64_t SH_FLD_O2SCMD_A_N_RESERVED_0 = 14535; // 4 +static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_1 = 14536; // 4 +static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 = 14537; // 4 +static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN = 14538; // 4 +static const uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4 = 14539; // 4 +static const uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4_LEN = 14540; // 4 +static const uint64_t SH_FLD_O2SST_A_N_RESERVED_6 = 14541; // 4 +static const uint64_t SH_FLD_O2S_BRIDGE_ENABLE_A_N = 14542; // 4 +static const uint64_t SH_FLD_O2S_CLEAR_STICKY_BITS_A_N = 14543; // 4 +static const uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N = 14544; // 4 +static const uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN = 14545; // 4 +static const uint64_t SH_FLD_O2S_CPHA_A_N = 14546; // 4 +static const uint64_t SH_FLD_O2S_CPOL_A_N = 14547; // 4 +static const uint64_t SH_FLD_O2S_FRAME_SIZE_A_N = 14548; // 4 +static const uint64_t SH_FLD_O2S_FRAME_SIZE_A_N_LEN = 14549; // 4 +static const uint64_t SH_FLD_O2S_FSM_ERR_A_N = 14550; // 4 +static const uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N = 14551; // 4 +static const uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN = 14552; // 4 +static const uint64_t SH_FLD_O2S_IN_COUNT1_A_N = 14553; // 4 +static const uint64_t SH_FLD_O2S_IN_COUNT1_A_N_LEN = 14554; // 4 +static const uint64_t SH_FLD_O2S_IN_COUNT2_A_N = 14555; // 4 +static const uint64_t SH_FLD_O2S_IN_COUNT2_A_N_LEN = 14556; // 4 +static const uint64_t SH_FLD_O2S_IN_DELAY1_A_N = 14557; // 4 +static const uint64_t SH_FLD_O2S_IN_DELAY1_A_N_LEN = 14558; // 4 +static const uint64_t SH_FLD_O2S_IN_DELAY2_A_N = 14559; // 4 +static const uint64_t SH_FLD_O2S_IN_DELAY2_A_N_LEN = 14560; // 4 +static const uint64_t SH_FLD_O2S_NR_OF_FRAMES_A_N = 14561; // 4 +static const uint64_t SH_FLD_O2S_ONGOING_A_N = 14562; // 4 +static const uint64_t SH_FLD_O2S_OUT_COUNT1_A_N = 14563; // 4 +static const uint64_t SH_FLD_O2S_OUT_COUNT1_A_N_LEN = 14564; // 4 +static const uint64_t SH_FLD_O2S_OUT_COUNT2_A_N = 14565; // 4 +static const uint64_t SH_FLD_O2S_OUT_COUNT2_A_N_LEN = 14566; // 4 +static const uint64_t SH_FLD_O2S_RDATA_A_N = 14567; // 4 +static const uint64_t SH_FLD_O2S_RDATA_A_N_LEN = 14568; // 4 +static const uint64_t SH_FLD_O2S_WDATA_A_N = 14569; // 4 +static const uint64_t SH_FLD_O2S_WDATA_A_N_LEN = 14570; // 4 +static const uint64_t SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 14571; // 4 +static const uint64_t SH_FLD_OBUF_ABANK = 14572; // 3 +static const uint64_t SH_FLD_OBUF_ABANK_LEN = 14573; // 3 +static const uint64_t SH_FLD_OBUF_AIDX = 14574; // 3 +static const uint64_t SH_FLD_OBUF_AIDX_LEN = 14575; // 3 +static const uint64_t SH_FLD_OBUF_RSRC = 14576; // 3 +static const uint64_t SH_FLD_OBUF_RSRC_LEN = 14577; // 3 +static const uint64_t SH_FLD_OBUF_WSRC = 14578; // 3 +static const uint64_t SH_FLD_OBUF_WSRC_LEN = 14579; // 3 +static const uint64_t SH_FLD_OBWR_MASK = 14580; // 3 +static const uint64_t SH_FLD_OBWR_MASK_LEN = 14581; // 3 +static const uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY = 14582; // 1 +static const uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY_MASK = 14583; // 1 +static const uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR = 14584; // 1 +static const uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR_MASK = 14585; // 1 +static const uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT = 14586; // 1 +static const uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT_MASK = 14587; // 1 +static const uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR = 14588; // 1 +static const uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR_MASK = 14589; // 1 +static const uint64_t SH_FLD_OCB_ERROR = 14590; // 1 +static const uint64_t SH_FLD_OCB_ERROR_MASK = 14591; // 1 +static const uint64_t SH_FLD_OCB_IDC0_ERROR = 14592; // 1 +static const uint64_t SH_FLD_OCB_IDC0_ERROR_MASK = 14593; // 1 +static const uint64_t SH_FLD_OCB_IDC1_ERROR = 14594; // 1 +static const uint64_t SH_FLD_OCB_IDC1_ERROR_MASK = 14595; // 1 +static const uint64_t SH_FLD_OCB_IDC2_ERROR = 14596; // 1 +static const uint64_t SH_FLD_OCB_IDC2_ERROR_MASK = 14597; // 1 +static const uint64_t SH_FLD_OCB_IDC3_ERROR = 14598; // 1 +static const uint64_t SH_FLD_OCB_IDC3_ERROR_MASK = 14599; // 1 +static const uint64_t SH_FLD_OCB_OCISLV_ERR = 14600; // 1 +static const uint64_t SH_FLD_OCB_OCISLV_ERR_LEN = 14601; // 1 +static const uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR = 14602; // 1 +static const uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR_MASK = 14603; // 1 +static const uint64_t SH_FLD_OCC_ACTION_SET = 14604; // 1 +static const uint64_t SH_FLD_OCC_ACTION_SET_LEN = 14605; // 1 +static const uint64_t SH_FLD_OCC_DBG_HALT = 14606; // 1 +static const uint64_t SH_FLD_OCC_ERROR = 14607; // 1 +static const uint64_t SH_FLD_OCC_FLAGS = 14608; // 1 +static const uint64_t SH_FLD_OCC_FLAGS_LEN = 14609; // 1 +static const uint64_t SH_FLD_OCC_HEARTBEAT_COUNT = 14610; // 7 +static const uint64_t SH_FLD_OCC_HEARTBEAT_COUNT_LEN = 14611; // 7 +static const uint64_t SH_FLD_OCC_HEARTBEAT_EN = 14612; // 1 +static const uint64_t SH_FLD_OCC_HEARTBEAT_ENABLE = 14613; // 6 +static const uint64_t SH_FLD_OCC_HEARTBEAT_LOSS = 14614; // 6 +static const uint64_t SH_FLD_OCC_HEARTBEAT_LOST = 14615; // 12 +static const uint64_t SH_FLD_OCC_INTERRUPT_HIGH = 14616; // 1 +static const uint64_t SH_FLD_OCC_INTERRUPT_PENDING = 14617; // 1 +static const uint64_t SH_FLD_OCC_MALF_ALERT = 14618; // 1 +static const uint64_t SH_FLD_OCC_SCRATCH_N = 14619; // 3 +static const uint64_t SH_FLD_OCC_SCRATCH_N_LEN = 14620; // 3 +static const uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR = 14621; // 1 +static const uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN = 14622; // 1 +static const uint64_t SH_FLD_OCC_SPECIAL_WKUP = 14623; // 30 +static const uint64_t SH_FLD_OCC_STRM0_PULL = 14624; // 1 +static const uint64_t SH_FLD_OCC_STRM0_PUSH = 14625; // 1 +static const uint64_t SH_FLD_OCC_STRM1_PULL = 14626; // 1 +static const uint64_t SH_FLD_OCC_STRM1_PUSH = 14627; // 1 +static const uint64_t SH_FLD_OCC_STRM2_PULL = 14628; // 1 +static const uint64_t SH_FLD_OCC_STRM2_PUSH = 14629; // 1 +static const uint64_t SH_FLD_OCC_STRM3_PULL = 14630; // 1 +static const uint64_t SH_FLD_OCC_STRM3_PUSH = 14631; // 1 +static const uint64_t SH_FLD_OCC_TIMER0 = 14632; // 1 +static const uint64_t SH_FLD_OCC_TIMER1 = 14633; // 1 +static const uint64_t SH_FLD_OCC_TRACE_MUX_SEL = 14634; // 1 +static const uint64_t SH_FLD_OCC_TRACE_MUX_SEL_LEN = 14635; // 1 +static const uint64_t SH_FLD_OCICFG_RESERVED_20 = 14636; // 1 +static const uint64_t SH_FLD_OCICFG_RESERVED_23 = 14637; // 1 +static const uint64_t SH_FLD_OCISLV_FAIRNESS_MASK = 14638; // 1 +static const uint64_t SH_FLD_OCISLV_FAIRNESS_MASK_LEN = 14639; // 1 +static const uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV = 14640; // 1 +static const uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV_LEN = 14641; // 1 +static const uint64_t SH_FLD_OCI_APAR_ERR = 14642; // 1 +static const uint64_t SH_FLD_OCI_APAR_ERR_MASK = 14643; // 1 +static const uint64_t SH_FLD_OCI_ARB_RESET = 14644; // 1 +static const uint64_t SH_FLD_OCI_BAD_REG_ADDR = 14645; // 1 +static const uint64_t SH_FLD_OCI_BAD_REG_ADDR_MASK = 14646; // 1 +static const uint64_t SH_FLD_OCI_ERR_INJ_CE_UE = 14647; // 1 +static const uint64_t SH_FLD_OCI_ERR_INJ_DCU = 14648; // 1 +static const uint64_t SH_FLD_OCI_ERR_INJ_ICU = 14649; // 1 +static const uint64_t SH_FLD_OCI_ERR_INJ_SINGL_CONT = 14650; // 1 +static const uint64_t SH_FLD_OCI_HI_BUS_MODE = 14651; // 1 +static const uint64_t SH_FLD_OCI_M0_FLCK = 14652; // 1 +static const uint64_t SH_FLD_OCI_M0_OEAR_LOCK = 14653; // 1 +static const uint64_t SH_FLD_OCI_M0_RW_STATUS = 14654; // 1 +static const uint64_t SH_FLD_OCI_M0_TIMEOUT_ERROR = 14655; // 1 +static const uint64_t SH_FLD_OCI_M1_FLCK = 14656; // 1 +static const uint64_t SH_FLD_OCI_M1_OEAR_LOCK = 14657; // 1 +static const uint64_t SH_FLD_OCI_M1_RW_STATUS = 14658; // 1 +static const uint64_t SH_FLD_OCI_M1_TIMEOUT_ERROR = 14659; // 1 +static const uint64_t SH_FLD_OCI_M2_FLCK = 14660; // 1 +static const uint64_t SH_FLD_OCI_M2_OEAR_LOCK = 14661; // 1 +static const uint64_t SH_FLD_OCI_M2_RW_STATUS = 14662; // 1 +static const uint64_t SH_FLD_OCI_M2_TIMEOUT_ERROR = 14663; // 1 +static const uint64_t SH_FLD_OCI_M3_FLCK = 14664; // 1 +static const uint64_t SH_FLD_OCI_M3_OEAR_LOCK = 14665; // 1 +static const uint64_t SH_FLD_OCI_M3_RW_STATUS = 14666; // 1 +static const uint64_t SH_FLD_OCI_M3_TIMEOUT_ERROR = 14667; // 1 +static const uint64_t SH_FLD_OCI_M4_FLCK = 14668; // 1 +static const uint64_t SH_FLD_OCI_M4_OEAR_LOCK = 14669; // 1 +static const uint64_t SH_FLD_OCI_M4_RW_STATUS = 14670; // 1 +static const uint64_t SH_FLD_OCI_M4_TIMEOUT_ERROR = 14671; // 1 +static const uint64_t SH_FLD_OCI_M5_FLCK = 14672; // 1 +static const uint64_t SH_FLD_OCI_M5_OEAR_LOCK = 14673; // 1 +static const uint64_t SH_FLD_OCI_M5_RW_STATUS = 14674; // 1 +static const uint64_t SH_FLD_OCI_M5_TIMEOUT_ERROR = 14675; // 1 +static const uint64_t SH_FLD_OCI_M6_FLCK = 14676; // 1 +static const uint64_t SH_FLD_OCI_M6_OEAR_LOCK = 14677; // 1 +static const uint64_t SH_FLD_OCI_M6_RW_STATUS = 14678; // 1 +static const uint64_t SH_FLD_OCI_M6_TIMEOUT_ERROR = 14679; // 1 +static const uint64_t SH_FLD_OCI_M7_FLCK = 14680; // 1 +static const uint64_t SH_FLD_OCI_M7_OEAR_LOCK = 14681; // 1 +static const uint64_t SH_FLD_OCI_M7_RW_STATUS = 14682; // 1 +static const uint64_t SH_FLD_OCI_M7_TIMEOUT_ERROR = 14683; // 1 +static const uint64_t SH_FLD_OCI_MARKER_SPACE = 14684; // 1 +static const uint64_t SH_FLD_OCI_MARKER_SPACE_LEN = 14685; // 1 +static const uint64_t SH_FLD_OCI_PRIORITY_MODE = 14686; // 1 +static const uint64_t SH_FLD_OCI_PRIORITY_ORDER = 14687; // 1 +static const uint64_t SH_FLD_OCI_PRIORITY_ORDER_LEN = 14688; // 1 +static const uint64_t SH_FLD_OCI_READ_DATA_PARITY = 14689; // 4 +static const uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL = 14690; // 1 +static const uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN = 14691; // 1 +static const uint64_t SH_FLD_OCI_REGION = 14692; // 4 +static const uint64_t SH_FLD_OCI_REGION_LEN = 14693; // 4 +static const uint64_t SH_FLD_OCI_SLAVE_ERROR = 14694; // 4 +static const uint64_t SH_FLD_OCI_SLAVE_INIT = 14695; // 1 +static const uint64_t SH_FLD_OCI_SLAVE_INIT_MASK = 14696; // 1 +static const uint64_t SH_FLD_OCI_TIMEOUT = 14697; // 4 +static const uint64_t SH_FLD_OCI_TIMEOUT_ADDR = 14698; // 1 +static const uint64_t SH_FLD_OCI_TIMEOUT_ADDR_LEN = 14699; // 1 +static const uint64_t SH_FLD_OCI_TRACE_MUX_SEL = 14700; // 1 +static const uint64_t SH_FLD_OCI_TRACE_MUX_SEL_LEN = 14701; // 1 +static const uint64_t SH_FLD_OCI_WRITE_PIPELINE_CONTROL = 14702; // 1 +static const uint64_t SH_FLD_OCI_WRPAR_ERR = 14703; // 1 +static const uint64_t SH_FLD_OCI_WRPAR_ERR_MASK = 14704; // 1 +static const uint64_t SH_FLD_OCTANT_SELECT = 14705; // 2 +static const uint64_t SH_FLD_OCTANT_SELECT_LEN = 14706; // 2 +static const uint64_t SH_FLD_OFFSET = 14707; // 15 +static const uint64_t SH_FLD_OFFSET_LEN = 14708; // 15 +static const uint64_t SH_FLD_OFF_INIT_CFG = 14709; // 6 +static const uint64_t SH_FLD_OFF_INIT_CFG_LEN = 14710; // 6 +static const uint64_t SH_FLD_OFF_INIT_TIMEOUT = 14711; // 6 +static const uint64_t SH_FLD_OFF_INIT_TIMEOUT_LEN = 14712; // 6 +static const uint64_t SH_FLD_OFF_RECAL_CFG = 14713; // 6 +static const uint64_t SH_FLD_OFF_RECAL_CFG_LEN = 14714; // 6 +static const uint64_t SH_FLD_OFF_RECAL_TIMEOUT = 14715; // 6 +static const uint64_t SH_FLD_OFF_RECAL_TIMEOUT_LEN = 14716; // 6 +static const uint64_t SH_FLD_OJCFG_DBG_HALT = 14717; // 1 +static const uint64_t SH_FLD_OJCFG_JTAG_SRC_SEL = 14718; // 1 +static const uint64_t SH_FLD_OJCFG_JTAG_TRST_B = 14719; // 1 +static const uint64_t SH_FLD_OJCFG_RUN_TCK = 14720; // 1 +static const uint64_t SH_FLD_OJCFG_TCK_WIDTH = 14721; // 1 +static const uint64_t SH_FLD_OJCFG_TCK_WIDTH_LEN = 14722; // 1 +static const uint64_t SH_FLD_OJIC_DO_DR = 14723; // 1 +static const uint64_t SH_FLD_OJIC_DO_IR = 14724; // 1 +static const uint64_t SH_FLD_OJIC_DO_TAP_RESET = 14725; // 1 +static const uint64_t SH_FLD_OJIC_JTAG_INSTR = 14726; // 1 +static const uint64_t SH_FLD_OJIC_JTAG_INSTR_LEN = 14727; // 1 +static const uint64_t SH_FLD_OJIC_WR_VALID = 14728; // 1 +static const uint64_t SH_FLD_OJSTAT_FSM_ERROR = 14729; // 1 +static const uint64_t SH_FLD_OJSTAT_INPROG_WR_ERR = 14730; // 1 +static const uint64_t SH_FLD_OJSTAT_IR_DR_EQ0_ERR = 14731; // 1 +static const uint64_t SH_FLD_OJSTAT_JTAG_INPROG = 14732; // 1 +static const uint64_t SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR = 14733; // 1 +static const uint64_t SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR = 14734; // 1 +static const uint64_t SH_FLD_OJSTAT_TRST_B_EQ0_ERR = 14735; // 1 +static const uint64_t SH_FLD_ONESHOT0 = 14736; // 24 +static const uint64_t SH_FLD_ONESHOT1 = 14737; // 24 +static const uint64_t SH_FLD_ONE_PPC = 14738; // 24 +static const uint64_t SH_FLD_ONE_SHOT_STATE = 14739; // 36 +static const uint64_t SH_FLD_ONGOING = 14740; // 1 +static const uint64_t SH_FLD_ONL = 14741; // 192 +static const uint64_t SH_FLD_OOB_MUX = 14742; // 3 +static const uint64_t SH_FLD_OPB_BUSY = 14743; // 2 +static const uint64_t SH_FLD_OPB_BUSY_FLAG = 14744; // 3 +static const uint64_t SH_FLD_OPB_BUS_ACCESS_FSM_CHECK = 14745; // 3 +static const uint64_t SH_FLD_OPB_COMMAND_OVERRUN_ERROR = 14746; // 3 +static const uint64_t SH_FLD_OPB_ERRACK = 14747; // 3 +static const uint64_t SH_FLD_OPB_ERROR = 14748; // 4 +static const uint64_t SH_FLD_OPB_MASTER_HANG_TIMEOUT = 14749; // 4 +static const uint64_t SH_FLD_OPB_PARITY_ERROR = 14750; // 3 +static const uint64_t SH_FLD_OPB_PROTOCOL_ERROR = 14751; // 3 +static const uint64_t SH_FLD_OPB_TIMEOUT = 14752; // 4 +static const uint64_t SH_FLD_OPB_TIMEOUT_BIT = 14753; // 3 +static const uint64_t SH_FLD_OPCG_IP = 14754; // 43 +static const uint64_t SH_FLD_OPCG_TRIGGER_ERR = 14755; // 43 +static const uint64_t SH_FLD_OPCODE = 14756; // 1 +static const uint64_t SH_FLD_OPCODE_LEN = 14757; // 1 +static const uint64_t SH_FLD_OPER = 14758; // 1 +static const uint64_t SH_FLD_OPER_LEN = 14759; // 1 +static const uint64_t SH_FLD_OPTION_PREVENT_SBE_START = 14760; // 1 +static const uint64_t SH_FLD_OPTION_SKIP_SCAN0_CLOCKSTART = 14761; // 1 +static const uint64_t SH_FLD_OPT_UNUSED1 = 14762; // 2 +static const uint64_t SH_FLD_OPT_UNUSED1_LEN = 14763; // 2 +static const uint64_t SH_FLD_OPT_UNUSED2 = 14764; // 2 +static const uint64_t SH_FLD_OPT_UNUSED3 = 14765; // 2 +static const uint64_t SH_FLD_OPT_UNUSED3_LEN = 14766; // 2 +static const uint64_t SH_FLD_OPT_UNUSED4 = 14767; // 2 +static const uint64_t SH_FLD_OPT_UNUSED5 = 14768; // 2 +static const uint64_t SH_FLD_OPT_UNUSED5_LEN = 14769; // 2 +static const uint64_t SH_FLD_OSC = 14770; // 4 +static const uint64_t SH_FLD_OSCILLATOR = 14771; // 1 +static const uint64_t SH_FLD_OSCILLATOR_LEN = 14772; // 1 +static const uint64_t SH_FLD_OSCSWITCH_CNTL0_DC = 14773; // 3 +static const uint64_t SH_FLD_OSCSWITCH_CNTL0_DC_LEN = 14774; // 3 +static const uint64_t SH_FLD_OSCSWITCH_CNTL1_DC = 14775; // 3 +static const uint64_t SH_FLD_OSCSWITCH_CNTL1_DC_LEN = 14776; // 3 +static const uint64_t SH_FLD_OSCSWITCH_INTERRUPT = 14777; // 4 +static const uint64_t SH_FLD_OSC_LEN = 14778; // 4 +static const uint64_t SH_FLD_OSC_SWITCH = 14779; // 4 +static const uint64_t SH_FLD_OS_INTR_PRESENT = 14780; // 24 +static const uint64_t SH_FLD_OS_INTR_PRESENT_LEN = 14781; // 24 +static const uint64_t SH_FLD_OS_INTR_REQUESTED = 14782; // 24 +static const uint64_t SH_FLD_OS_INTR_REQUESTED_LEN = 14783; // 24 +static const uint64_t SH_FLD_OS_STATUS_DISABLE_A_N = 14784; // 96 +static const uint64_t SH_FLD_OTHER_SCOM_SAT = 14785; // 1 +static const uint64_t SH_FLD_OTP = 14786; // 1 +static const uint64_t SH_FLD_OTP_LEN = 14787; // 1 +static const uint64_t SH_FLD_OTR_SPECIAL_WKUP = 14788; // 30 +static const uint64_t SH_FLD_OUT = 14789; // 1 +static const uint64_t SH_FLD_OUTER_LOOP_CNT = 14790; // 8 +static const uint64_t SH_FLD_OUTER_LOOP_CNT_LEN = 14791; // 8 +static const uint64_t SH_FLD_OUTWR_INRD_ECC_CE = 14792; // 1 +static const uint64_t SH_FLD_OUTWR_INRD_ECC_SUE = 14793; // 1 +static const uint64_t SH_FLD_OUTWR_INRD_ECC_UE = 14794; // 1 +static const uint64_t SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR = 14795; // 30 +static const uint64_t SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR = 14796; // 30 +static const uint64_t SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR = 14797; // 30 +static const uint64_t SH_FLD_OUT_COUNT1 = 14798; // 1 +static const uint64_t SH_FLD_OUT_COUNT1_LEN = 14799; // 1 +static const uint64_t SH_FLD_OUT_COUNT2 = 14800; // 1 +static const uint64_t SH_FLD_OUT_COUNT2_LEN = 14801; // 1 +static const uint64_t SH_FLD_OUT_LEN = 14802; // 1 +static const uint64_t SH_FLD_OUT_RRB_SOURCED_ERROR = 14803; // 30 +static const uint64_t SH_FLD_OVERFLOW_CHECKSTOP = 14804; // 2 +static const uint64_t SH_FLD_OVERFLOW_ERR = 14805; // 43 +static const uint64_t SH_FLD_OVERFLOW_ERROR = 14806; // 2 +static const uint64_t SH_FLD_OVERFLOW_MASK = 14807; // 43 +static const uint64_t SH_FLD_OVERRIDE_EN = 14808; // 24 +static const uint64_t SH_FLD_OVERRIDE_PBINIT_ERR_CMD = 14809; // 1 +static const uint64_t SH_FLD_OVERRIDE_PBINIT_HTM_CMD = 14810; // 1 +static const uint64_t SH_FLD_OVERRIDE_PBINIT_TOD_CMD = 14811; // 1 +static const uint64_t SH_FLD_OVERRIDE_PBINIT_TRACE_CMD = 14812; // 1 +static const uint64_t SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD = 14813; // 1 +static const uint64_t SH_FLD_OVERRUN = 14814; // 8 +static const uint64_t SH_FLD_OVER_OR_UNDERRUN_ERR = 14815; // 1 +static const uint64_t SH_FLD_OVRBIT = 14816; // 72 +static const uint64_t SH_FLD_OVRVALUE = 14817; // 72 +static const uint64_t SH_FLD_OVRVALUE_LEN = 14818; // 72 +static const uint64_t SH_FLD_OVR_BITS = 14819; // 12 +static const uint64_t SH_FLD_OVR_BITS_LEN = 14820; // 12 +static const uint64_t SH_FLD_OVR_CTRL_BITS = 14821; // 12 +static const uint64_t SH_FLD_OVR_CTRL_BITS_LEN = 14822; // 12 +static const uint64_t SH_FLD_OVR_PM = 14823; // 1 +static const uint64_t SH_FLD_OWNERSHIP_FF1 = 14824; // 2 +static const uint64_t SH_FLD_OWNERSHIP_FF2 = 14825; // 2 +static const uint64_t SH_FLD_OWN_ID_THIS_SLAVE = 14826; // 2 +static const uint64_t SH_FLD_OWN_ID_THIS_SLAVE_LEN = 14827; // 2 +static const uint64_t SH_FLD_P0_BACK2BACK_MODE_ENA = 14828; // 1 +static const uint64_t SH_FLD_P0_BACK2BACK_MODE_ENA_LEN = 14829; // 1 +static const uint64_t SH_FLD_P0_IS_IDLE = 14830; // 4 +static const uint64_t SH_FLD_P1_IS_IDLE = 14831; // 4 +static const uint64_t SH_FLD_P9_TO_P9_MODE = 14832; // 6 +static const uint64_t SH_FLD_PACE = 14833; // 2 +static const uint64_t SH_FLD_PACE_LEN = 14834; // 2 +static const uint64_t SH_FLD_PACE_RATE = 14835; // 1 +static const uint64_t SH_FLD_PACE_RATE_LEN = 14836; // 1 +static const uint64_t SH_FLD_PACING_ALLOW_0 = 14837; // 2 +static const uint64_t SH_FLD_PACING_ALLOW_1 = 14838; // 1 +static const uint64_t SH_FLD_PACING_ALLOW_2 = 14839; // 1 +static const uint64_t SH_FLD_PACING_ALLOW_3 = 14840; // 1 +static const uint64_t SH_FLD_PACKET_DELAY_LIMIT = 14841; // 5 +static const uint64_t SH_FLD_PACKET_DELAY_LIMIT_LEN = 14842; // 5 +static const uint64_t SH_FLD_PAGE_OFFSET_CFG = 14843; // 1 +static const uint64_t SH_FLD_PAGE_OFFSET_CFG_LEN = 14844; // 1 +static const uint64_t SH_FLD_PAGE_SIZE_64K = 14845; // 5 +static const uint64_t SH_FLD_PAGE_SIZE_64K_PC = 14846; // 1 +static const uint64_t SH_FLD_PAGE_SIZE_64K_VC = 14847; // 1 +static const uint64_t SH_FLD_PAIR0_QUA = 14848; // 8 +static const uint64_t SH_FLD_PAIR0_QUA_LEN = 14849; // 8 +static const uint64_t SH_FLD_PAIR0_QUA_V = 14850; // 8 +static const uint64_t SH_FLD_PAIR0_TER = 14851; // 8 +static const uint64_t SH_FLD_PAIR0_TER_LEN = 14852; // 8 +static const uint64_t SH_FLD_PAIR0_TER_V = 14853; // 8 +static const uint64_t SH_FLD_PAIR1_PRI = 14854; // 8 +static const uint64_t SH_FLD_PAIR1_PRI_LEN = 14855; // 8 +static const uint64_t SH_FLD_PAIR1_PRI_V = 14856; // 8 +static const uint64_t SH_FLD_PAIR1_QUA = 14857; // 8 +static const uint64_t SH_FLD_PAIR1_QUA_LEN = 14858; // 8 +static const uint64_t SH_FLD_PAIR1_QUA_V = 14859; // 8 +static const uint64_t SH_FLD_PAIR1_SEC = 14860; // 8 +static const uint64_t SH_FLD_PAIR1_SEC_LEN = 14861; // 8 +static const uint64_t SH_FLD_PAIR1_SEC_V = 14862; // 8 +static const uint64_t SH_FLD_PAIR1_TER = 14863; // 8 +static const uint64_t SH_FLD_PAIR1_TER_LEN = 14864; // 8 +static const uint64_t SH_FLD_PAIR1_TER_V = 14865; // 8 +static const uint64_t SH_FLD_PAIR2_PRI = 14866; // 8 +static const uint64_t SH_FLD_PAIR2_PRI_LEN = 14867; // 8 +static const uint64_t SH_FLD_PAIR2_PRI_V = 14868; // 8 +static const uint64_t SH_FLD_PAIR2_QUA = 14869; // 8 +static const uint64_t SH_FLD_PAIR2_QUA_LEN = 14870; // 8 +static const uint64_t SH_FLD_PAIR2_QUA_V = 14871; // 8 +static const uint64_t SH_FLD_PAIR2_SEC = 14872; // 8 +static const uint64_t SH_FLD_PAIR2_SEC_LEN = 14873; // 8 +static const uint64_t SH_FLD_PAIR2_SEC_V = 14874; // 8 +static const uint64_t SH_FLD_PAIR2_TER = 14875; // 8 +static const uint64_t SH_FLD_PAIR2_TER_LEN = 14876; // 8 +static const uint64_t SH_FLD_PAIR2_TER_V = 14877; // 8 +static const uint64_t SH_FLD_PAIR3_PRI = 14878; // 8 +static const uint64_t SH_FLD_PAIR3_PRI_LEN = 14879; // 8 +static const uint64_t SH_FLD_PAIR3_PRI_V = 14880; // 8 +static const uint64_t SH_FLD_PAIR3_SEC = 14881; // 8 +static const uint64_t SH_FLD_PAIR3_SEC_LEN = 14882; // 8 +static const uint64_t SH_FLD_PAIR3_SEC_V = 14883; // 8 +static const uint64_t SH_FLD_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED = 14884; // 24 +static const uint64_t SH_FLD_PAPR_INBOUND_INJECT_ERROR = 14885; // 6 +static const uint64_t SH_FLD_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED = 14886; // 24 +static const uint64_t SH_FLD_PAPR_OUTBOUND_INJECT_ERROR = 14887; // 6 +static const uint64_t SH_FLD_PARALLEL_ADDR_INVALID = 14888; // 43 +static const uint64_t SH_FLD_PARALLEL_READ_NVLD = 14889; // 43 +static const uint64_t SH_FLD_PARALLEL_WRITE_NVLD = 14890; // 43 +static const uint64_t SH_FLD_PARANOIA_TEST_ENABLE_CHANGE = 14891; // 43 +static const uint64_t SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE = 14892; // 43 +static const uint64_t SH_FLD_PARITY = 14893; // 45 +static const uint64_t SH_FLD_PARITY_CHECK = 14894; // 1 +static const uint64_t SH_FLD_PARITY_ERR = 14895; // 4 +static const uint64_t SH_FLD_PARITY_ERR2 = 14896; // 3 +static const uint64_t SH_FLD_PARITY_ERROR = 14897; // 55 +static const uint64_t SH_FLD_PARITY_ERROR_RESET = 14898; // 3 +static const uint64_t SH_FLD_PARITY_ERROR_SUE_ENA = 14899; // 6 +static const uint64_t SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR = 14900; // 43 +static const uint64_t SH_FLD_PARITY_ON_GPIO_REG_ERR = 14901; // 43 +static const uint64_t SH_FLD_PARITY_ON_INTERFACE_MACHINE = 14902; // 43 +static const uint64_t SH_FLD_PARITY_ON_OPCG_REG_ERR = 14903; // 43 +static const uint64_t SH_FLD_PARITY_ON_OPCG_SM_ERR = 14904; // 43 +static const uint64_t SH_FLD_PARITY_ON_P2S_MACHINE = 14905; // 43 +static const uint64_t SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR = 14906; // 43 +static const uint64_t SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR = 14907; // 43 +static const uint64_t SH_FLD_PARITY_ON_XSTOP_REG_ERR = 14908; // 43 +static const uint64_t SH_FLD_PARSER00_ATTN = 14909; // 4 +static const uint64_t SH_FLD_PARSER01_ATTN = 14910; // 4 +static const uint64_t SH_FLD_PARSER02_ATTN = 14911; // 4 +static const uint64_t SH_FLD_PARSER03_ATTN = 14912; // 4 +static const uint64_t SH_FLD_PARSER04_ATTN = 14913; // 4 +static const uint64_t SH_FLD_PARSER05_ATTN = 14914; // 4 +static const uint64_t SH_FLD_PARSER06_ATTN = 14915; // 2 +static const uint64_t SH_FLD_PARSER07_ATTN = 14916; // 2 +static const uint64_t SH_FLD_PART_0 = 14917; // 2 +static const uint64_t SH_FLD_PART_0_LEN = 14918; // 2 +static const uint64_t SH_FLD_PART_1 = 14919; // 2 +static const uint64_t SH_FLD_PART_10 = 14920; // 2 +static const uint64_t SH_FLD_PART_10_LEN = 14921; // 2 +static const uint64_t SH_FLD_PART_11 = 14922; // 2 +static const uint64_t SH_FLD_PART_11_LEN = 14923; // 2 +static const uint64_t SH_FLD_PART_12 = 14924; // 2 +static const uint64_t SH_FLD_PART_12_LEN = 14925; // 2 +static const uint64_t SH_FLD_PART_13 = 14926; // 2 +static const uint64_t SH_FLD_PART_13_LEN = 14927; // 2 +static const uint64_t SH_FLD_PART_14 = 14928; // 2 +static const uint64_t SH_FLD_PART_14_LEN = 14929; // 2 +static const uint64_t SH_FLD_PART_15 = 14930; // 2 +static const uint64_t SH_FLD_PART_15_LEN = 14931; // 2 +static const uint64_t SH_FLD_PART_16 = 14932; // 2 +static const uint64_t SH_FLD_PART_16_LEN = 14933; // 2 +static const uint64_t SH_FLD_PART_17 = 14934; // 2 +static const uint64_t SH_FLD_PART_17_LEN = 14935; // 2 +static const uint64_t SH_FLD_PART_18 = 14936; // 2 +static const uint64_t SH_FLD_PART_18_LEN = 14937; // 2 +static const uint64_t SH_FLD_PART_19 = 14938; // 2 +static const uint64_t SH_FLD_PART_19_LEN = 14939; // 2 +static const uint64_t SH_FLD_PART_1_LEN = 14940; // 2 +static const uint64_t SH_FLD_PART_2 = 14941; // 2 +static const uint64_t SH_FLD_PART_20 = 14942; // 2 +static const uint64_t SH_FLD_PART_20_LEN = 14943; // 2 +static const uint64_t SH_FLD_PART_21 = 14944; // 2 +static const uint64_t SH_FLD_PART_21_LEN = 14945; // 2 +static const uint64_t SH_FLD_PART_22 = 14946; // 2 +static const uint64_t SH_FLD_PART_22_LEN = 14947; // 2 +static const uint64_t SH_FLD_PART_23 = 14948; // 2 +static const uint64_t SH_FLD_PART_23_LEN = 14949; // 2 +static const uint64_t SH_FLD_PART_24 = 14950; // 2 +static const uint64_t SH_FLD_PART_24_LEN = 14951; // 2 +static const uint64_t SH_FLD_PART_25 = 14952; // 2 +static const uint64_t SH_FLD_PART_25_LEN = 14953; // 2 +static const uint64_t SH_FLD_PART_26 = 14954; // 2 +static const uint64_t SH_FLD_PART_26_LEN = 14955; // 2 +static const uint64_t SH_FLD_PART_27 = 14956; // 2 +static const uint64_t SH_FLD_PART_27_LEN = 14957; // 2 +static const uint64_t SH_FLD_PART_28 = 14958; // 2 +static const uint64_t SH_FLD_PART_28_LEN = 14959; // 2 +static const uint64_t SH_FLD_PART_29 = 14960; // 2 +static const uint64_t SH_FLD_PART_29_LEN = 14961; // 2 +static const uint64_t SH_FLD_PART_2_LEN = 14962; // 2 +static const uint64_t SH_FLD_PART_3 = 14963; // 2 +static const uint64_t SH_FLD_PART_30 = 14964; // 2 +static const uint64_t SH_FLD_PART_30_LEN = 14965; // 2 +static const uint64_t SH_FLD_PART_31 = 14966; // 2 +static const uint64_t SH_FLD_PART_31_LEN = 14967; // 2 +static const uint64_t SH_FLD_PART_32 = 14968; // 2 +static const uint64_t SH_FLD_PART_32_LEN = 14969; // 2 +static const uint64_t SH_FLD_PART_33 = 14970; // 2 +static const uint64_t SH_FLD_PART_33_LEN = 14971; // 2 +static const uint64_t SH_FLD_PART_34 = 14972; // 2 +static const uint64_t SH_FLD_PART_34_LEN = 14973; // 2 +static const uint64_t SH_FLD_PART_35 = 14974; // 2 +static const uint64_t SH_FLD_PART_35_LEN = 14975; // 2 +static const uint64_t SH_FLD_PART_36 = 14976; // 2 +static const uint64_t SH_FLD_PART_36_LEN = 14977; // 2 +static const uint64_t SH_FLD_PART_37 = 14978; // 2 +static const uint64_t SH_FLD_PART_37_LEN = 14979; // 2 +static const uint64_t SH_FLD_PART_38 = 14980; // 2 +static const uint64_t SH_FLD_PART_38_LEN = 14981; // 2 +static const uint64_t SH_FLD_PART_39 = 14982; // 2 +static const uint64_t SH_FLD_PART_39_LEN = 14983; // 2 +static const uint64_t SH_FLD_PART_3_LEN = 14984; // 2 +static const uint64_t SH_FLD_PART_4 = 14985; // 2 +static const uint64_t SH_FLD_PART_40 = 14986; // 2 +static const uint64_t SH_FLD_PART_40_LEN = 14987; // 2 +static const uint64_t SH_FLD_PART_41 = 14988; // 2 +static const uint64_t SH_FLD_PART_41_LEN = 14989; // 2 +static const uint64_t SH_FLD_PART_42 = 14990; // 2 +static const uint64_t SH_FLD_PART_42_LEN = 14991; // 2 +static const uint64_t SH_FLD_PART_43 = 14992; // 2 +static const uint64_t SH_FLD_PART_43_LEN = 14993; // 2 +static const uint64_t SH_FLD_PART_44 = 14994; // 2 +static const uint64_t SH_FLD_PART_44_LEN = 14995; // 2 +static const uint64_t SH_FLD_PART_45 = 14996; // 2 +static const uint64_t SH_FLD_PART_45_LEN = 14997; // 2 +static const uint64_t SH_FLD_PART_46 = 14998; // 2 +static const uint64_t SH_FLD_PART_46_LEN = 14999; // 2 +static const uint64_t SH_FLD_PART_47 = 15000; // 2 +static const uint64_t SH_FLD_PART_47_LEN = 15001; // 2 +static const uint64_t SH_FLD_PART_48 = 15002; // 2 +static const uint64_t SH_FLD_PART_48_LEN = 15003; // 2 +static const uint64_t SH_FLD_PART_49 = 15004; // 2 +static const uint64_t SH_FLD_PART_49_LEN = 15005; // 2 +static const uint64_t SH_FLD_PART_4_LEN = 15006; // 2 +static const uint64_t SH_FLD_PART_5 = 15007; // 2 +static const uint64_t SH_FLD_PART_50 = 15008; // 2 +static const uint64_t SH_FLD_PART_50_LEN = 15009; // 2 +static const uint64_t SH_FLD_PART_51 = 15010; // 2 +static const uint64_t SH_FLD_PART_51_LEN = 15011; // 2 +static const uint64_t SH_FLD_PART_52 = 15012; // 2 +static const uint64_t SH_FLD_PART_52_LEN = 15013; // 2 +static const uint64_t SH_FLD_PART_53 = 15014; // 2 +static const uint64_t SH_FLD_PART_53_LEN = 15015; // 2 +static const uint64_t SH_FLD_PART_54 = 15016; // 2 +static const uint64_t SH_FLD_PART_54_LEN = 15017; // 2 +static const uint64_t SH_FLD_PART_55 = 15018; // 2 +static const uint64_t SH_FLD_PART_55_LEN = 15019; // 2 +static const uint64_t SH_FLD_PART_56 = 15020; // 2 +static const uint64_t SH_FLD_PART_56_LEN = 15021; // 2 +static const uint64_t SH_FLD_PART_57 = 15022; // 2 +static const uint64_t SH_FLD_PART_57_LEN = 15023; // 2 +static const uint64_t SH_FLD_PART_58 = 15024; // 2 +static const uint64_t SH_FLD_PART_58_LEN = 15025; // 2 +static const uint64_t SH_FLD_PART_59 = 15026; // 2 +static const uint64_t SH_FLD_PART_59_LEN = 15027; // 2 +static const uint64_t SH_FLD_PART_5_LEN = 15028; // 2 +static const uint64_t SH_FLD_PART_6 = 15029; // 2 +static const uint64_t SH_FLD_PART_60 = 15030; // 2 +static const uint64_t SH_FLD_PART_60_LEN = 15031; // 2 +static const uint64_t SH_FLD_PART_61 = 15032; // 2 +static const uint64_t SH_FLD_PART_61_LEN = 15033; // 2 +static const uint64_t SH_FLD_PART_62 = 15034; // 2 +static const uint64_t SH_FLD_PART_62_LEN = 15035; // 2 +static const uint64_t SH_FLD_PART_63 = 15036; // 2 +static const uint64_t SH_FLD_PART_63_LEN = 15037; // 2 +static const uint64_t SH_FLD_PART_6_LEN = 15038; // 2 +static const uint64_t SH_FLD_PART_7 = 15039; // 2 +static const uint64_t SH_FLD_PART_7_LEN = 15040; // 2 +static const uint64_t SH_FLD_PART_8 = 15041; // 2 +static const uint64_t SH_FLD_PART_8_LEN = 15042; // 2 +static const uint64_t SH_FLD_PART_9 = 15043; // 2 +static const uint64_t SH_FLD_PART_9_LEN = 15044; // 2 +static const uint64_t SH_FLD_PAR_17_MASK = 15045; // 8 +static const uint64_t SH_FLD_PAR_ERR_ONLY = 15046; // 8 +static const uint64_t SH_FLD_PAR_INVERT = 15047; // 8 +static const uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_HI = 15048; // 1 +static const uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_LO = 15049; // 1 +static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_HI = 15050; // 1 +static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_LO = 15051; // 1 +static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 = 15052; // 1 +static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 = 15053; // 1 +static const uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_HI = 15054; // 1 +static const uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_LO = 15055; // 1 +static const uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_01 = 15056; // 1 +static const uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_23 = 15057; // 1 +static const uint64_t SH_FLD_PASTE_ADDR_ALIGN = 15058; // 1 +static const uint64_t SH_FLD_PASTE_REJECT = 15059; // 1 +static const uint64_t SH_FLD_PATSEL = 15060; // 48 +static const uint64_t SH_FLD_PATSEL_LEN = 15061; // 48 +static const uint64_t SH_FLD_PATTERNA = 15062; // 162 +static const uint64_t SH_FLD_PATTERNA_LEN = 15063; // 162 +static const uint64_t SH_FLD_PATTERNB = 15064; // 162 +static const uint64_t SH_FLD_PATTERNB_LEN = 15065; // 162 +static const uint64_t SH_FLD_PATTERNC = 15066; // 162 +static const uint64_t SH_FLD_PATTERNC_LEN = 15067; // 162 +static const uint64_t SH_FLD_PATTERND = 15068; // 162 +static const uint64_t SH_FLD_PATTERND_LEN = 15069; // 162 +static const uint64_t SH_FLD_PATTERN_CHECK_EN = 15070; // 1 +static const uint64_t SH_FLD_PATTERN_SEL = 15071; // 2 +static const uint64_t SH_FLD_PATTERN_SEL_LEN = 15072; // 2 +static const uint64_t SH_FLD_PAYLOAD = 15073; // 1 +static const uint64_t SH_FLD_PAYLOAD_LEN = 15074; // 1 +static const uint64_t SH_FLD_PBAIBHWCFG_PE = 15075; // 9 +static const uint64_t SH_FLD_PBAIBTXCCR_PE = 15076; // 9 +static const uint64_t SH_FLD_PBAIBTXCITR_PE = 15077; // 9 +static const uint64_t SH_FLD_PBAIBTXDCR_PE = 15078; // 9 +static const uint64_t SH_FLD_PBAIB_FENCE_PCIE = 15079; // 9 +static const uint64_t SH_FLD_PBASE = 15080; // 4 +static const uint64_t SH_FLD_PBASE_LEN = 15081; // 4 +static const uint64_t SH_FLD_PBAX_EN = 15082; // 1 +static const uint64_t SH_FLD_PBAX_OCC_PUSH0 = 15083; // 1 +static const uint64_t SH_FLD_PBAX_OCC_PUSH1 = 15084; // 1 +static const uint64_t SH_FLD_PBAX_OCC_SEND_ATTN = 15085; // 1 +static const uint64_t SH_FLD_PBA_BCDE_ATTN = 15086; // 1 +static const uint64_t SH_FLD_PBA_BCUE_ATTN = 15087; // 1 +static const uint64_t SH_FLD_PBA_ERROR = 15088; // 1 +static const uint64_t SH_FLD_PBA_REGION = 15089; // 1 +static const uint64_t SH_FLD_PBA_REGION_LEN = 15090; // 1 +static const uint64_t SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH = 15091; // 1 +static const uint64_t SH_FLD_PBCFG_0_EPSILON = 15092; // 1 +static const uint64_t SH_FLD_PBCFG_0_EPSILON_LEN = 15093; // 1 +static const uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT = 15094; // 1 +static const uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN = 15095; // 1 +static const uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT = 15096; // 1 +static const uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 15097; // 1 +static const uint64_t SH_FLD_PBCFG_0_INJ_ARRAY_SEL = 15098; // 1 +static const uint64_t SH_FLD_PBCFG_0_INJ_CE = 15099; // 1 +static const uint64_t SH_FLD_PBCFG_0_INJ_FREQ = 15100; // 1 +static const uint64_t SH_FLD_PBCFG_0_INJ_SUE = 15101; // 1 +static const uint64_t SH_FLD_PBCFG_0_INJ_UE = 15102; // 1 +static const uint64_t SH_FLD_PBCFG_0_UNUSED1 = 15103; // 1 +static const uint64_t SH_FLD_PBCFG_0_UNUSED1_LEN = 15104; // 1 +static const uint64_t SH_FLD_PBCFG_0_UNUSED2 = 15105; // 1 +static const uint64_t SH_FLD_PBCFG_0_UNUSED2_LEN = 15106; // 1 +static const uint64_t SH_FLD_PBCFG_1_UNUSED1 = 15107; // 1 +static const uint64_t SH_FLD_PBCFG_1_UNUSED1_LEN = 15108; // 1 +static const uint64_t SH_FLD_PBCFG_1_UNUSED2 = 15109; // 1 +static const uint64_t SH_FLD_PBCFG_1_UNUSED2_LEN = 15110; // 1 +static const uint64_t SH_FLD_PBCQ_CNTRL_LOGIC_ERR = 15111; // 1 +static const uint64_t SH_FLD_PBDATA_HANG = 15112; // 1 +static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR0 = 15113; // 12 +static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR1 = 15114; // 12 +static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR2 = 15115; // 12 +static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR0 = 15116; // 12 +static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR1 = 15117; // 12 +static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR2 = 15118; // 12 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER0 = 15119; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN = 15120; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER1 = 15121; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN = 15122; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER2 = 15123; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN = 15124; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER3 = 15125; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN = 15126; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER0 = 15127; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN = 15128; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER1 = 15129; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN = 15130; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER2 = 15131; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN = 15132; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER3 = 15133; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN = 15134; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER0 = 15135; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN = 15136; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER1 = 15137; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN = 15138; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER2 = 15139; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN = 15140; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER3 = 15141; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN = 15142; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER0 = 15143; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN = 15144; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER1 = 15145; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN = 15146; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER2 = 15147; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN = 15148; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER3 = 15149; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN = 15150; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER0 = 15151; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN = 15152; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER1 = 15153; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN = 15154; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER2 = 15155; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN = 15156; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER3 = 15157; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN = 15158; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER0 = 15159; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN = 15160; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER1 = 15161; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN = 15162; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER2 = 15163; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN = 15164; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER3 = 15165; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN = 15166; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER0 = 15167; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN = 15168; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER1 = 15169; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN = 15170; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER2 = 15171; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN = 15172; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER3 = 15173; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN = 15174; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER0 = 15175; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN = 15176; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER1 = 15177; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN = 15178; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER2 = 15179; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN = 15180; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER3 = 15181; // 1 +static const uint64_t SH_FLD_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN = 15182; // 1 +static const uint64_t SH_FLD_PBIEQ00_PBH_HW1_ERROR = 15183; // 2 +static const uint64_t SH_FLD_PBIEQ00_PBH_HW2_ERROR = 15184; // 2 +static const uint64_t SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR = 15185; // 2 +static const uint64_t SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR = 15186; // 2 +static const uint64_t SH_FLD_PBIEQ01_PBH_HW1_ERROR = 15187; // 2 +static const uint64_t SH_FLD_PBIEQ01_PBH_HW2_ERROR = 15188; // 2 +static const uint64_t SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR = 15189; // 2 +static const uint64_t SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR = 15190; // 2 +static const uint64_t SH_FLD_PBIEQ02_PBH_HW1_ERROR = 15191; // 2 +static const uint64_t SH_FLD_PBIEQ02_PBH_HW2_ERROR = 15192; // 2 +static const uint64_t SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR = 15193; // 2 +static const uint64_t SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR = 15194; // 2 +static const uint64_t SH_FLD_PBIEQ03_PBH_HW1_ERROR = 15195; // 2 +static const uint64_t SH_FLD_PBIEQ03_PBH_HW2_ERROR = 15196; // 2 +static const uint64_t SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR = 15197; // 2 +static const uint64_t SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR = 15198; // 2 +static const uint64_t SH_FLD_PBIEQ04_PBH_HW1_ERROR = 15199; // 2 +static const uint64_t SH_FLD_PBIEQ04_PBH_HW2_ERROR = 15200; // 2 +static const uint64_t SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR = 15201; // 2 +static const uint64_t SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR = 15202; // 2 +static const uint64_t SH_FLD_PBIEQ05_PBH_HW1_ERROR = 15203; // 2 +static const uint64_t SH_FLD_PBIEQ05_PBH_HW2_ERROR = 15204; // 2 +static const uint64_t SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR = 15205; // 2 +static const uint64_t SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR = 15206; // 2 +static const uint64_t SH_FLD_PBI_DEBUG_SEL = 15207; // 4 +static const uint64_t SH_FLD_PBI_DEBUG_SEL_LEN = 15208; // 4 +static const uint64_t SH_FLD_PBI_IDLE = 15209; // 1 +static const uint64_t SH_FLD_PBI_INTERNAL_HANG = 15210; // 1 +static const uint64_t SH_FLD_PBI_MUX_SELECT = 15211; // 1 +static const uint64_t SH_FLD_PBI_MUX_SELECT_LEN = 15212; // 1 +static const uint64_t SH_FLD_PBI_PE = 15213; // 2 +static const uint64_t SH_FLD_PBI_WRITE_IDLE = 15214; // 2 +static const uint64_t SH_FLD_PBLN = 15215; // 15 +static const uint64_t SH_FLD_PBM_STATE = 15216; // 3 +static const uint64_t SH_FLD_PBM_STATE_LEN = 15217; // 3 +static const uint64_t SH_FLD_PBNNG = 15218; // 15 +static const uint64_t SH_FLD_PBREQ_BCE_MAX_PRIORITY = 15219; // 1 +static const uint64_t SH_FLD_PBREQ_DATA_HANG_DIV = 15220; // 1 +static const uint64_t SH_FLD_PBREQ_DATA_HANG_DIV_LEN = 15221; // 1 +static const uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK = 15222; // 1 +static const uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN = 15223; // 1 +static const uint64_t SH_FLD_PBREQ_EVENT_MUX = 15224; // 1 +static const uint64_t SH_FLD_PBREQ_EVENT_MUX_LEN = 15225; // 1 +static const uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV = 15226; // 1 +static const uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV_LEN = 15227; // 1 +static const uint64_t SH_FLD_PBREQ_EXIT_ON_HANG = 15228; // 1 +static const uint64_t SH_FLD_PBREQ_EXIT_ON_HANG_PBAX = 15229; // 1 +static const uint64_t SH_FLD_PBREQ_OPER_HANG_DIV = 15230; // 1 +static const uint64_t SH_FLD_PBREQ_OPER_HANG_DIV_LEN = 15231; // 1 +static const uint64_t SH_FLD_PBREQ_SLVFW_MAX_PRIORITY = 15232; // 1 +static const uint64_t SH_FLD_PBRNVG = 15233; // 15 +static const uint64_t SH_FLD_PBRS = 15234; // 3 +static const uint64_t SH_FLD_PBRSP = 15235; // 12 +static const uint64_t SH_FLD_PBRX_MASK = 15236; // 3 +static const uint64_t SH_FLD_PBRX_MASK_LEN = 15237; // 3 +static const uint64_t SH_FLD_PBRX_RTAG = 15238; // 3 +static const uint64_t SH_FLD_PBRX_RTAG_LEN = 15239; // 3 +static const uint64_t SH_FLD_PBTX_AMO_IGNORE_XUE = 15240; // 3 +static const uint64_t SH_FLD_PBTX_DELAY_BDONE = 15241; // 3 +static const uint64_t SH_FLD_PBTX_EARLY_AFTAG = 15242; // 3 +static const uint64_t SH_FLD_PBTX_FLIP_IMIN_BIG = 15243; // 3 +static const uint64_t SH_FLD_PBTX_FLIP_IMIN_LITTLE = 15244; // 3 +static const uint64_t SH_FLD_PBTX_REDUCE_RTAG = 15245; // 3 +static const uint64_t SH_FLD_PBUS_CMD_HANG = 15246; // 2 +static const uint64_t SH_FLD_PBUS_ECC_CE = 15247; // 2 +static const uint64_t SH_FLD_PBUS_ECC_SUE = 15248; // 2 +static const uint64_t SH_FLD_PBUS_ECC_UE = 15249; // 2 +static const uint64_t SH_FLD_PBUS_LINK_ABORT = 15250; // 2 +static const uint64_t SH_FLD_PBUS_LOAD_LINK_ERR = 15251; // 2 +static const uint64_t SH_FLD_PBUS_MISC_HW = 15252; // 2 +static const uint64_t SH_FLD_PBUS_READ_ARE = 15253; // 2 +static const uint64_t SH_FLD_PBUS_STORE_LINK_ERR = 15254; // 2 +static const uint64_t SH_FLD_PBUS_WRITE_ARE = 15255; // 2 +static const uint64_t SH_FLD_PBUS_XLAT_ECC_SUE = 15256; // 1 +static const uint64_t SH_FLD_PBUS_XLAT_ECC_UE = 15257; // 1 +static const uint64_t SH_FLD_PBXMIT_DXMIT_SEQ_ERRHOLD = 15258; // 2 +static const uint64_t SH_FLD_PBXMIT_MSGQ_SEQ_ERRHOLD = 15259; // 2 +static const uint64_t SH_FLD_PB_16_1 = 15260; // 1 +static const uint64_t SH_FLD_PB_32_1 = 15261; // 1 +static const uint64_t SH_FLD_PB_ACKDEAD_FW_RD = 15262; // 1 +static const uint64_t SH_FLD_PB_ACKDEAD_FW_RD_MASK = 15263; // 1 +static const uint64_t SH_FLD_PB_ACKDEAD_FW_WR = 15264; // 1 +static const uint64_t SH_FLD_PB_ACKDEAD_FW_WR_MASK = 15265; // 1 +static const uint64_t SH_FLD_PB_ADDR_PARITY = 15266; // 2 +static const uint64_t SH_FLD_PB_APM_EXTDATARCV_CNT = 15267; // 1 +static const uint64_t SH_FLD_PB_APM_EXTDATARCV_CNT_LEN = 15268; // 1 +static const uint64_t SH_FLD_PB_APM_EXTDATASND_CNT = 15269; // 1 +static const uint64_t SH_FLD_PB_APM_EXTDATASND_CNT_LEN = 15270; // 1 +static const uint64_t SH_FLD_PB_APM_INTDATA_CNT = 15271; // 1 +static const uint64_t SH_FLD_PB_APM_INTDATA_CNT_LEN = 15272; // 1 +static const uint64_t SH_FLD_PB_APM_LM_HI_CNT = 15273; // 1 +static const uint64_t SH_FLD_PB_APM_LM_HI_CNT_LEN = 15274; // 1 +static const uint64_t SH_FLD_PB_APM_LM_LO_CNT = 15275; // 1 +static const uint64_t SH_FLD_PB_APM_LM_LO_CNT_LEN = 15276; // 1 +static const uint64_t SH_FLD_PB_APM_NM_HI_CNT = 15277; // 1 +static const uint64_t SH_FLD_PB_APM_NM_HI_CNT_LEN = 15278; // 1 +static const uint64_t SH_FLD_PB_APM_NM_LO_CNT = 15279; // 1 +static const uint64_t SH_FLD_PB_APM_NM_LO_CNT_LEN = 15280; // 1 +static const uint64_t SH_FLD_PB_APM_RCMD_CNT = 15281; // 1 +static const uint64_t SH_FLD_PB_APM_RCMD_CNT_LEN = 15282; // 1 +static const uint64_t SH_FLD_PB_BADCRESP = 15283; // 1 +static const uint64_t SH_FLD_PB_BADCRESP_MASK = 15284; // 1 +static const uint64_t SH_FLD_PB_BAR_RESET = 15285; // 1 +static const uint64_t SH_FLD_PB_CENT_DBG_MAX_HANG_STAGE_REACHED = 15286; // 1 +static const uint64_t SH_FLD_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN = 15287; // 1 +static const uint64_t SH_FLD_PB_CENT_PBIXXX_INIT = 15288; // 1 +static const uint64_t SH_FLD_PB_CE_FW = 15289; // 1 +static const uint64_t SH_FLD_PB_CE_FW_MASK = 15290; // 1 +static const uint64_t SH_FLD_PB_CFG_CENT_A_INDIRECT_EN = 15291; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA0_EN = 15292; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID = 15293; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN = 15294; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA1_EN = 15295; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID = 15296; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN = 15297; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA2_EN = 15298; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID = 15299; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN = 15300; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA3_EN = 15301; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID = 15302; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN = 15303; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA0_EN = 15304; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID = 15305; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN = 15306; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA1_EN = 15307; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID = 15308; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN = 15309; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA2_EN = 15310; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID = 15311; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN = 15312; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA3_EN = 15313; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID = 15314; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN = 15315; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA0_EN = 15316; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID = 15317; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN = 15318; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA1_EN = 15319; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID = 15320; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN = 15321; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA2_EN = 15322; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID = 15323; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN = 15324; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA3_EN = 15325; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID = 15326; // 2 +static const uint64_t SH_FLD_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN = 15327; // 2 +static const uint64_t SH_FLD_PB_CFG_CNPME_MASK = 15328; // 1 +static const uint64_t SH_FLD_PB_CFG_CNPMW_MASK = 15329; // 2 +static const uint64_t SH_FLD_PB_CFG_CRESP = 15330; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_ERROR_OTHER = 15331; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_LEN = 15332; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_SCOPE = 15333; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_SCOPE_LEN = 15334; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_TSIZE = 15335; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_TSIZE_LEN = 15336; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_TTAG = 15337; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_TTAG_LEN = 15338; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_TTYPE = 15339; // 1 +static const uint64_t SH_FLD_PB_CFG_CRESP_TTYPE_LEN = 15340; // 1 +static const uint64_t SH_FLD_PB_CFG_EAST_A_INDIRECT_EN = 15341; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_CPU_RATIO_OVERRIDE = 15342; // 1 +static const uint64_t SH_FLD_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN = 15343; // 1 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA0_EN = 15344; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID = 15345; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN = 15346; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA1_EN = 15347; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID = 15348; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN = 15349; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA2_EN = 15350; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID = 15351; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN = 15352; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA3_EN = 15353; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID = 15354; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN = 15355; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA0_EN = 15356; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID = 15357; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN = 15358; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA1_EN = 15359; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID = 15360; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN = 15361; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA2_EN = 15362; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID = 15363; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN = 15364; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA3_EN = 15365; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID = 15366; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN = 15367; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA0_EN = 15368; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID = 15369; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN = 15370; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA1_EN = 15371; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID = 15372; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN = 15373; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA2_EN = 15374; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID = 15375; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN = 15376; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA3_EN = 15377; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID = 15378; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN = 15379; // 2 +static const uint64_t SH_FLD_PB_CFG_EAST_RESET_ERROR_CAPTURE = 15380; // 1 +static const uint64_t SH_FLD_PB_CFG_PRESP = 15381; // 1 +static const uint64_t SH_FLD_PB_CFG_PRESP_LEN = 15382; // 1 +static const uint64_t SH_FLD_PB_CFG_WEST_A_INDIRECT_EN = 15383; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_CPU_RATIO_OVERRIDE = 15384; // 1 +static const uint64_t SH_FLD_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN = 15385; // 1 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA0_EN = 15386; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID = 15387; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN = 15388; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA1_EN = 15389; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID = 15390; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN = 15391; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA2_EN = 15392; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID = 15393; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN = 15394; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA3_EN = 15395; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID = 15396; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN = 15397; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA0_EN = 15398; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID = 15399; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN = 15400; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA1_EN = 15401; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID = 15402; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN = 15403; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA2_EN = 15404; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID = 15405; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN = 15406; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA3_EN = 15407; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID = 15408; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN = 15409; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA0_EN = 15410; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID = 15411; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN = 15412; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA1_EN = 15413; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID = 15414; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN = 15415; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA2_EN = 15416; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID = 15417; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN = 15418; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA3_EN = 15419; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID = 15420; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN = 15421; // 2 +static const uint64_t SH_FLD_PB_CFG_WEST_RESET_ERROR_CAPTURE = 15422; // 1 +static const uint64_t SH_FLD_PB_CRESP_ADDR_ERROR = 15423; // 1 +static const uint64_t SH_FLD_PB_CRESP_ERROR = 15424; // 1 +static const uint64_t SH_FLD_PB_DATA_TIME_OUT = 15425; // 4 +static const uint64_t SH_FLD_PB_EAST_FW_SCRATCH0 = 15426; // 1 +static const uint64_t SH_FLD_PB_EAST_FW_SCRATCH0_LEN = 15427; // 1 +static const uint64_t SH_FLD_PB_EAST_FW_SCRATCH1 = 15428; // 1 +static const uint64_t SH_FLD_PB_EAST_FW_SCRATCH1_LEN = 15429; // 1 +static const uint64_t SH_FLD_PB_EAST_PBIXXX_INIT = 15430; // 1 +static const uint64_t SH_FLD_PB_ECC_CE = 15431; // 1 +static const uint64_t SH_FLD_PB_ECC_ERR_CE = 15432; // 4 +static const uint64_t SH_FLD_PB_ECC_ERR_SUE = 15433; // 4 +static const uint64_t SH_FLD_PB_ECC_ERR_UE = 15434; // 4 +static const uint64_t SH_FLD_PB_ECC_SUE = 15435; // 1 +static const uint64_t SH_FLD_PB_ECC_UE = 15436; // 1 +static const uint64_t SH_FLD_PB_NOCI_EVENT_SEL = 15437; // 1 +static const uint64_t SH_FLD_PB_OFFSET = 15438; // 2 +static const uint64_t SH_FLD_PB_OFFSET_LEN = 15439; // 2 +static const uint64_t SH_FLD_PB_OPERTO = 15440; // 1 +static const uint64_t SH_FLD_PB_OPERTO_MASK = 15441; // 1 +static const uint64_t SH_FLD_PB_OP_HANG_ERR = 15442; // 1 +static const uint64_t SH_FLD_PB_PARITY_ERR = 15443; // 1 +static const uint64_t SH_FLD_PB_PARITY_ERROR = 15444; // 5 +static const uint64_t SH_FLD_PB_PARITY_ERR_MASK = 15445; // 1 +static const uint64_t SH_FLD_PB_PURGE_DONE_LVL = 15446; // 6 +static const uint64_t SH_FLD_PB_PURGE_REQ = 15447; // 6 +static const uint64_t SH_FLD_PB_RCMDX_CI_ERR1 = 15448; // 1 +static const uint64_t SH_FLD_PB_RCMDX_CI_ERR2 = 15449; // 1 +static const uint64_t SH_FLD_PB_RCMDX_CI_ERR3 = 15450; // 1 +static const uint64_t SH_FLD_PB_RDADRERR_FW = 15451; // 1 +static const uint64_t SH_FLD_PB_RDADRERR_FW_MASK = 15452; // 1 +static const uint64_t SH_FLD_PB_RDDATATO_FW = 15453; // 1 +static const uint64_t SH_FLD_PB_RDDATATO_FW_MASK = 15454; // 1 +static const uint64_t SH_FLD_PB_SCOPE = 15455; // 96 +static const uint64_t SH_FLD_PB_SCOPE_LEN = 15456; // 96 +static const uint64_t SH_FLD_PB_STOP = 15457; // 1 +static const uint64_t SH_FLD_PB_SUE_FW = 15458; // 1 +static const uint64_t SH_FLD_PB_SUE_FW_MASK = 15459; // 1 +static const uint64_t SH_FLD_PB_UE_FW = 15460; // 1 +static const uint64_t SH_FLD_PB_UE_FW_MASK = 15461; // 1 +static const uint64_t SH_FLD_PB_UNEXPCRESP = 15462; // 1 +static const uint64_t SH_FLD_PB_UNEXPCRESP_MASK = 15463; // 1 +static const uint64_t SH_FLD_PB_UNEXPDATA = 15464; // 1 +static const uint64_t SH_FLD_PB_UNEXPDATA_MASK = 15465; // 1 +static const uint64_t SH_FLD_PB_WEST_FW_SCRATCH0 = 15466; // 1 +static const uint64_t SH_FLD_PB_WEST_FW_SCRATCH0_LEN = 15467; // 1 +static const uint64_t SH_FLD_PB_WEST_FW_SCRATCH1 = 15468; // 1 +static const uint64_t SH_FLD_PB_WEST_FW_SCRATCH1_LEN = 15469; // 1 +static const uint64_t SH_FLD_PB_WEST_PBIXXX_INIT = 15470; // 1 +static const uint64_t SH_FLD_PB_WEST_SPARE = 15471; // 1 +static const uint64_t SH_FLD_PB_WEST_SPARE_LEN = 15472; // 1 +static const uint64_t SH_FLD_PB_WRADRERR_FW = 15473; // 1 +static const uint64_t SH_FLD_PB_WRADRERR_FW_MASK = 15474; // 1 +static const uint64_t SH_FLD_PB_X0_FIR_ERR = 15475; // 2 +static const uint64_t SH_FLD_PB_X1_FIR_ERR = 15476; // 2 +static const uint64_t SH_FLD_PB_X2_FIR_ERR = 15477; // 2 +static const uint64_t SH_FLD_PB_X3_FIR_ERR = 15478; // 2 +static const uint64_t SH_FLD_PB_X4_FIR_ERR = 15479; // 2 +static const uint64_t SH_FLD_PB_X5_FIR_ERR = 15480; // 2 +static const uint64_t SH_FLD_PB_X6_FIR_ERR = 15481; // 2 +static const uint64_t SH_FLD_PB_XLAT_DATA_SUE = 15482; // 1 +static const uint64_t SH_FLD_PB_XLAT_DATA_UE = 15483; // 1 +static const uint64_t SH_FLD_PCB = 15484; // 3 +static const uint64_t SH_FLD_PCBMUX_GRANT_C0 = 15485; // 12 +static const uint64_t SH_FLD_PCBMUX_GRANT_C1 = 15486; // 12 +static const uint64_t SH_FLD_PCBMUX_REQ_C0 = 15487; // 12 +static const uint64_t SH_FLD_PCBMUX_REQ_C1 = 15488; // 12 +static const uint64_t SH_FLD_PCBM_DATA = 15489; // 24 +static const uint64_t SH_FLD_PCBM_DATA_LEN = 15490; // 24 +static const uint64_t SH_FLD_PCBM_INFO = 15491; // 24 +static const uint64_t SH_FLD_PCBM_INFO_LEN = 15492; // 24 +static const uint64_t SH_FLD_PCBQ_N_INFO = 15493; // 24 +static const uint64_t SH_FLD_PCBQ_N_INFO_LEN = 15494; // 24 +static const uint64_t SH_FLD_PCB_ACCESS = 15495; // 86 +static const uint64_t SH_FLD_PCB_ACCESS_LEN = 15496; // 43 +static const uint64_t SH_FLD_PCB_ADDRESS_NOT_VALID_ERR = 15497; // 43 +static const uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 15498; // 43 +static const uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 15499; // 43 +static const uint64_t SH_FLD_PCB_ADDRESS_PARITY = 15500; // 43 +static const uint64_t SH_FLD_PCB_COMMAND_PARITY = 15501; // 43 +static const uint64_t SH_FLD_PCB_EP_RESET = 15502; // 43 +static const uint64_t SH_FLD_PCB_ERROR = 15503; // 43 +static const uint64_t SH_FLD_PCB_ERR_HOLD_OUT = 15504; // 43 +static const uint64_t SH_FLD_PCB_FSM = 15505; // 43 +static const uint64_t SH_FLD_PCB_IDLE = 15506; // 43 +static const uint64_t SH_FLD_PCB_INTERFACE = 15507; // 43 +static const uint64_t SH_FLD_PCB_INTERRUPT_PROTOCOL = 15508; // 30 +static const uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N = 15509; // 144 +static const uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN = 15510; // 144 +static const uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N = 15511; // 12 +static const uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN = 15512; // 12 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_0 = 15513; // 8 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_1 = 15514; // 8 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_10 = 15515; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_11 = 15516; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_12 = 15517; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_13 = 15518; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_14 = 15519; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_15 = 15520; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_16 = 15521; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_17 = 15522; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_18 = 15523; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_19 = 15524; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_2 = 15525; // 8 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_20 = 15526; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_21 = 15527; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_22 = 15528; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_23 = 15529; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_3 = 15530; // 8 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_4 = 15531; // 8 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_5 = 15532; // 8 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_6 = 15533; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_7 = 15534; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_8 = 15535; // 6 +static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_9 = 15536; // 6 +static const uint64_t SH_FLD_PCB_LEN = 15537; // 2 +static const uint64_t SH_FLD_PCB_MASK = 15538; // 43 +static const uint64_t SH_FLD_PCB_PARITY_ON_ADDR_ERR = 15539; // 43 +static const uint64_t SH_FLD_PCB_PARITY_ON_CMD_ERR = 15540; // 43 +static const uint64_t SH_FLD_PCB_PARITY_ON_DATA_ERR = 15541; // 43 +static const uint64_t SH_FLD_PCB_PARITY_ON_SPCIF_ERR = 15542; // 43 +static const uint64_t SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR = 15543; // 43 +static const uint64_t SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 15544; // 43 +static const uint64_t SH_FLD_PCB_READ_NOT_ALLOWED_ERR = 15545; // 43 +static const uint64_t SH_FLD_PCB_REQUEST_SINCE_RESET = 15546; // 43 +static const uint64_t SH_FLD_PCB_RESET_DC = 15547; // 3 +static const uint64_t SH_FLD_PCB_TMP = 15548; // 1 +static const uint64_t SH_FLD_PCB_TMP_LEN = 15549; // 1 +static const uint64_t SH_FLD_PCB_WDATA_PARITY = 15550; // 43 +static const uint64_t SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR = 15551; // 43 +static const uint64_t SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR = 15552; // 43 +static const uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C0 = 15553; // 12 +static const uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C1 = 15554; // 12 +static const uint64_t SH_FLD_PCHKEN = 15555; // 48 +static const uint64_t SH_FLD_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE = 15556; // 24 +static const uint64_t SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS = 15557; // 30 +static const uint64_t SH_FLD_PCIE_REQUEST_ACCESS_ERROR = 15558; // 6 +static const uint64_t SH_FLD_PCLKDIFSEL = 15559; // 10 +static const uint64_t SH_FLD_PCLKSEL = 15560; // 14 +static const uint64_t SH_FLD_PCLKSEL_LEN = 15561; // 14 +static const uint64_t SH_FLD_PC_CAL_PCFSM_1HOT = 15562; // 8 +static const uint64_t SH_FLD_PC_CORE_HANG_DETECT_ERROR = 15563; // 24 +static const uint64_t SH_FLD_PC_CRD_AVAIL_PERR = 15564; // 1 +static const uint64_t SH_FLD_PC_CRD_PERR = 15565; // 1 +static const uint64_t SH_FLD_PC_DISABLE_DROOP = 15566; // 12 +static const uint64_t SH_FLD_PC_ERR_STATUS0 = 15567; // 8 +static const uint64_t SH_FLD_PC_ERR_STATUS0_LEN = 15568; // 8 +static const uint64_t SH_FLD_PC_FATAL_ERROR_0_2 = 15569; // 1 +static const uint64_t SH_FLD_PC_FATAL_ERROR_0_2_LEN = 15570; // 1 +static const uint64_t SH_FLD_PC_FUSED_CORE_MODE = 15571; // 12 +static const uint64_t SH_FLD_PC_FWD_PROGRESS_ERROR = 15572; // 24 +static const uint64_t SH_FLD_PC_FW_INJ_REC_ERROR = 15573; // 24 +static const uint64_t SH_FLD_PC_FW_INJ_XSTOP_ERROR = 15574; // 24 +static const uint64_t SH_FLD_PC_HANG_RECOVERY_FAILED = 15575; // 24 +static const uint64_t SH_FLD_PC_HYP_RES_ERROR = 15576; // 24 +static const uint64_t SH_FLD_PC_INFO_ERROR_0_2 = 15577; // 1 +static const uint64_t SH_FLD_PC_INFO_ERROR_0_2_LEN = 15578; // 1 +static const uint64_t SH_FLD_PC_INIT_CAL_ERR = 15579; // 8 +static const uint64_t SH_FLD_PC_INIT_CAL_ERR_LEN = 15580; // 8 +static const uint64_t SH_FLD_PC_INSTR_RUNNING_C0 = 15581; // 12 +static const uint64_t SH_FLD_PC_INSTR_RUNNING_C1 = 15582; // 12 +static const uint64_t SH_FLD_PC_INTR_PENDING_C0 = 15583; // 24 +static const uint64_t SH_FLD_PC_INTR_PENDING_C1 = 15584; // 24 +static const uint64_t SH_FLD_PC_LOG_XSTOP_ERROR = 15585; // 24 +static const uint64_t SH_FLD_PC_NEST_HANG_DETECT_ERROR = 15586; // 24 +static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C0 = 15587; // 12 +static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C0_LEN = 15588; // 12 +static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C1 = 15589; // 12 +static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C1_LEN = 15590; // 12 +static const uint64_t SH_FLD_PC_OTHER_CORE_CHIPLET_REC_ERROR = 15591; // 24 +static const uint64_t SH_FLD_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR = 15592; // 24 +static const uint64_t SH_FLD_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR = 15593; // 24 +static const uint64_t SH_FLD_PC_PE = 15594; // 8 +static const uint64_t SH_FLD_PC_PHYP_XSTOP_ERROR = 15595; // 24 +static const uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C0 = 15596; // 24 +static const uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C1 = 15597; // 24 +static const uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3 = 15598; // 1 +static const uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN = 15599; // 1 +static const uint64_t SH_FLD_PC_RECOV_ERROR_0_2 = 15600; // 1 +static const uint64_t SH_FLD_PC_RECOV_ERROR_0_2_LEN = 15601; // 1 +static const uint64_t SH_FLD_PC_RECOV_IN_MAINT_ERROR = 15602; // 24 +static const uint64_t SH_FLD_PC_RECOV_XSTOP_ERROR = 15603; // 24 +static const uint64_t SH_FLD_PC_SCOM_ERROR = 15604; // 24 +static const uint64_t SH_FLD_PC_SLICE_EN_ENC = 15605; // 1 +static const uint64_t SH_FLD_PC_SLICE_EN_ENC_LEN = 15606; // 1 +static const uint64_t SH_FLD_PC_SYS_XSTOP_ERROR = 15607; // 24 +static const uint64_t SH_FLD_PC_TC_AVP_OUT = 15608; // 24 +static const uint64_t SH_FLD_PC_TC_VALID_NOT_HV_MODE = 15609; // 24 +static const uint64_t SH_FLD_PC_TEST = 15610; // 1 +static const uint64_t SH_FLD_PC_TFAC_XSTOP_ERROR = 15611; // 24 +static const uint64_t SH_FLD_PC_THREAD_HANG_REC_ERROR = 15612; // 24 +static const uint64_t SH_FLD_PC_THROTTLE_REQ = 15613; // 12 +static const uint64_t SH_FLD_PC_TP_TRIG_SEL = 15614; // 43 +static const uint64_t SH_FLD_PC_TP_TRIG_SEL_LEN = 15615; // 43 +static const uint64_t SH_FLD_PC_UNMASKED_ATTN_C0 = 15616; // 12 +static const uint64_t SH_FLD_PC_UNMASKED_ATTN_C1 = 15617; // 12 +static const uint64_t SH_FLD_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 15618; // 24 +static const uint64_t SH_FLD_PDA_ENABLE_OVERRIDE = 15619; // 8 +static const uint64_t SH_FLD_PDA_ENABLE_OVERRIDE_LEN = 15620; // 8 +static const uint64_t SH_FLD_PDA_RANKDELAY_ENABLE = 15621; // 8 +static const uint64_t SH_FLD_PDWN = 15622; // 5 +static const uint64_t SH_FLD_PDWN_LITE = 15623; // 140 +static const uint64_t SH_FLD_PDWN_LITE_CONTROLS = 15624; // 72 +static const uint64_t SH_FLD_PDWN_LITE_CONTROLS_LEN = 15625; // 72 +static const uint64_t SH_FLD_PDWN_LITE_DISABLE = 15626; // 8 +static const uint64_t SH_FLD_PE = 15627; // 45 +static const uint64_t SH_FLD_PE0_CXA_LINKDOWN_ERRHOLD = 15628; // 2 +static const uint64_t SH_FLD_PE1_CXA_LINKDOWN_ERRHOLD = 15629; // 2 +static const uint64_t SH_FLD_PEAIB_CMD_CRD_AVAIL_PE = 15630; // 9 +static const uint64_t SH_FLD_PEAIB_CMD_CRD_PE = 15631; // 9 +static const uint64_t SH_FLD_PEAIB_CMD_PE = 15632; // 9 +static const uint64_t SH_FLD_PEAIB_DAT_CRD_AVAIL_PE = 15633; // 9 +static const uint64_t SH_FLD_PEAIB_DAT_CRD_PE = 15634; // 9 +static const uint64_t SH_FLD_PEAIB_DAT_PE = 15635; // 9 +static const uint64_t SH_FLD_PEAIB_OVERRUN = 15636; // 9 +static const uint64_t SH_FLD_PEAIB_QCNT_ERR = 15637; // 9 +static const uint64_t SH_FLD_PEAIB_TX_DAT_ERR = 15638; // 9 +static const uint64_t SH_FLD_PEAK_ENABLE_DAC_CFG = 15639; // 4 +static const uint64_t SH_FLD_PEAK_INIT_CFG = 15640; // 6 +static const uint64_t SH_FLD_PEAK_INIT_CFG_LEN = 15641; // 6 +static const uint64_t SH_FLD_PEAK_INIT_TIMEOUT = 15642; // 6 +static const uint64_t SH_FLD_PEAK_INIT_TIMEOUT_LEN = 15643; // 6 +static const uint64_t SH_FLD_PEAK_RECAL_CFG = 15644; // 6 +static const uint64_t SH_FLD_PEAK_RECAL_CFG_LEN = 15645; // 6 +static const uint64_t SH_FLD_PEAK_RECAL_TIMEOUT = 15646; // 6 +static const uint64_t SH_FLD_PEAK_RECAL_TIMEOUT_LEN = 15647; // 6 +static const uint64_t SH_FLD_PEAK_TUNE = 15648; // 4 +static const uint64_t SH_FLD_PECE = 15649; // 96 +static const uint64_t SH_FLD_PECE2 = 15650; // 96 +static const uint64_t SH_FLD_PECE2_LEN = 15651; // 96 +static const uint64_t SH_FLD_PECE_C_N_T0 = 15652; // 24 +static const uint64_t SH_FLD_PECE_C_N_T0_LEN = 15653; // 24 +static const uint64_t SH_FLD_PECE_C_N_T1 = 15654; // 24 +static const uint64_t SH_FLD_PECE_C_N_T1_LEN = 15655; // 24 +static const uint64_t SH_FLD_PECE_C_N_T2 = 15656; // 24 +static const uint64_t SH_FLD_PECE_C_N_T2_LEN = 15657; // 24 +static const uint64_t SH_FLD_PECE_C_N_T3 = 15658; // 24 +static const uint64_t SH_FLD_PECE_C_N_T3_LEN = 15659; // 24 +static const uint64_t SH_FLD_PECE_DECR = 15660; // 96 +static const uint64_t SH_FLD_PECE_DHDES = 15661; // 96 +static const uint64_t SH_FLD_PECE_DPDES = 15662; // 96 +static const uint64_t SH_FLD_PECE_HMAINT = 15663; // 96 +static const uint64_t SH_FLD_PECE_HYPV = 15664; // 96 +static const uint64_t SH_FLD_PECE_INTR_DISABLED = 15665; // 24 +static const uint64_t SH_FLD_PECE_LEN = 15666; // 96 +static const uint64_t SH_FLD_PECE_OS_EXT = 15667; // 96 +static const uint64_t SH_FLD_PECE_T0 = 15668; // 24 +static const uint64_t SH_FLD_PECE_T0_LEN = 15669; // 24 +static const uint64_t SH_FLD_PECE_T1 = 15670; // 24 +static const uint64_t SH_FLD_PECE_T1_LEN = 15671; // 24 +static const uint64_t SH_FLD_PECE_T2 = 15672; // 24 +static const uint64_t SH_FLD_PECE_T2_LEN = 15673; // 24 +static const uint64_t SH_FLD_PECE_T3 = 15674; // 24 +static const uint64_t SH_FLD_PECE_T3_LEN = 15675; // 24 +static const uint64_t SH_FLD_PEEK_DATA1_0 = 15676; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_0_LEN = 15677; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_1 = 15678; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_1_LEN = 15679; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_2 = 15680; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_2_LEN = 15681; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_3 = 15682; // 12 +static const uint64_t SH_FLD_PEEK_DATA1_3_LEN = 15683; // 12 +static const uint64_t SH_FLD_PEND = 15684; // 8 +static const uint64_t SH_FLD_PENDING_SOURCE = 15685; // 30 +static const uint64_t SH_FLD_PENDING_SOURCE_LEN = 15686; // 30 +static const uint64_t SH_FLD_PERFMON_COUNTER = 15687; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_1 = 15688; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_1_LEN = 15689; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_2 = 15690; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_2_LEN = 15691; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_3 = 15692; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_3_LEN = 15693; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_4 = 15694; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_4_LEN = 15695; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_5 = 15696; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_5_LEN = 15697; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_6 = 15698; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_6_LEN = 15699; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_7 = 15700; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_7_LEN = 15701; // 5 +static const uint64_t SH_FLD_PERFMON_COUNTER_LEN = 15702; // 5 +static const uint64_t SH_FLD_PERFORM_RDCLK_ALIGN = 15703; // 8 +static const uint64_t SH_FLD_PERFTRACE_ENABLE = 15704; // 5 +static const uint64_t SH_FLD_PERFTRACE_FIXED_WINDOW = 15705; // 5 +static const uint64_t SH_FLD_PERFTRACE_MODE = 15706; // 5 +static const uint64_t SH_FLD_PERFTRACE_MODE_LEN = 15707; // 5 +static const uint64_t SH_FLD_PERFTRACE_PRESCALE = 15708; // 5 +static const uint64_t SH_FLD_PERF_CASCADE = 15709; // 1 +static const uint64_t SH_FLD_PERF_CASCADE_LEN = 15710; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_CASCADE = 15711; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_CASCADE_LEN = 15712; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_DISABLE_PMISC = 15713; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_ENABLE = 15714; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_EVENTS = 15715; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_EVENTS_LEN = 15716; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_FREEZEMODE = 15717; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0 = 15718; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0_LEN = 15719; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1 = 15720; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1_LEN = 15721; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2 = 15722; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2_LEN = 15723; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3 = 15724; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3_LEN = 15725; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PMISC_MODE = 15726; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0 = 15727; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN = 15728; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1 = 15729; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN = 15730; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2 = 15731; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN = 15732; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3 = 15733; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN = 15734; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_RESETMODE = 15735; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_SPARE = 15736; // 1 +static const uint64_t SH_FLD_PERF_CONFIG_SPARE_LEN = 15737; // 1 +static const uint64_t SH_FLD_PERF_DISABLE_PMISC = 15738; // 1 +static const uint64_t SH_FLD_PERF_ENABLE = 15739; // 2 +static const uint64_t SH_FLD_PERF_EVENT0 = 15740; // 1 +static const uint64_t SH_FLD_PERF_EVENT0_LEN = 15741; // 1 +static const uint64_t SH_FLD_PERF_EVENT1 = 15742; // 1 +static const uint64_t SH_FLD_PERF_EVENT1_LEN = 15743; // 1 +static const uint64_t SH_FLD_PERF_EVENT2 = 15744; // 1 +static const uint64_t SH_FLD_PERF_EVENT2_LEN = 15745; // 1 +static const uint64_t SH_FLD_PERF_EVENT3 = 15746; // 1 +static const uint64_t SH_FLD_PERF_EVENT3_LEN = 15747; // 1 +static const uint64_t SH_FLD_PERF_FREEZEMODE = 15748; // 1 +static const uint64_t SH_FLD_PERF_PE_MASK = 15749; // 1 +static const uint64_t SH_FLD_PERF_PE_MATCH = 15750; // 1 +static const uint64_t SH_FLD_PERF_PE_MATCH_LEN = 15751; // 1 +static const uint64_t SH_FLD_PERF_PMISC_MODE = 15752; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C0 = 15753; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C0_LEN = 15754; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C1 = 15755; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C1_LEN = 15756; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C2 = 15757; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C2_LEN = 15758; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C3 = 15759; // 1 +static const uint64_t SH_FLD_PERF_PRESCALE_C3_LEN = 15760; // 1 +static const uint64_t SH_FLD_PERF_RESETMODE = 15761; // 1 +static const uint64_t SH_FLD_PERF_THRESH = 15762; // 8 +static const uint64_t SH_FLD_PERF_THRESH_LEN = 15763; // 8 +static const uint64_t SH_FLD_PERIODIC = 15764; // 56 +static const uint64_t SH_FLD_PERIODIC_CAL_REQ_EN = 15765; // 8 +static const uint64_t SH_FLD_PERIODIC_LEN = 15766; // 56 +static const uint64_t SH_FLD_PERR_BAR_REG = 15767; // 2 +static const uint64_t SH_FLD_PERR_NONBAR_REG = 15768; // 2 +static const uint64_t SH_FLD_PERSIST = 15769; // 8 +static const uint64_t SH_FLD_PERSIST_LEN = 15770; // 8 +static const uint64_t SH_FLD_PERV = 15771; // 215 +static const uint64_t SH_FLD_PERVASIVE_CAPT = 15772; // 6 +static const uint64_t SH_FLD_PERV_CTRL0_COPY_REG = 15773; // 1 +static const uint64_t SH_FLD_PERV_CTRL0_COPY_REG_LEN = 15774; // 1 +static const uint64_t SH_FLD_PERV_CTRL1_COPY_REG = 15775; // 1 +static const uint64_t SH_FLD_PERV_CTRL1_COPY_REG_LEN = 15776; // 1 +static const uint64_t SH_FLD_PER_ABORT = 15777; // 8 +static const uint64_t SH_FLD_PER_DUTY_CYCLE_SW = 15778; // 8 +static const uint64_t SH_FLD_PER_REPEAT_COUNT = 15779; // 8 +static const uint64_t SH_FLD_PER_REPEAT_COUNT_LEN = 15780; // 8 +static const uint64_t SH_FLD_PE_ADR_BAR_MODE = 15781; // 3 +static const uint64_t SH_FLD_PE_BLOCK_CQPB_PB_INIT = 15782; // 3 +static const uint64_t SH_FLD_PE_CAPP = 15783; // 3 +static const uint64_t SH_FLD_PE_CAPP_APC_ENG = 15784; // 3 +static const uint64_t SH_FLD_PE_CAPP_APC_ENG_LEN = 15785; // 3 +static const uint64_t SH_FLD_PE_CAPP_EN = 15786; // 3 +static const uint64_t SH_FLD_PE_CAPP_LEN = 15787; // 3 +static const uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG = 15788; // 3 +static const uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN = 15789; // 3 +static const uint64_t SH_FLD_PE_CAPP_P8_MODE = 15790; // 3 +static const uint64_t SH_FLD_PE_CHANNEL_STREAMING_EN = 15791; // 3 +static const uint64_t SH_FLD_PE_CONSTANT_EINJ = 15792; // 3 +static const uint64_t SH_FLD_PE_CQ_ECC_INJECT_ENABLE = 15793; // 3 +static const uint64_t SH_FLD_PE_CQ_PAR_INJECT_ENABLE = 15794; // 3 +static const uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY = 15795; // 3 +static const uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY_LEN = 15796; // 3 +static const uint64_t SH_FLD_PE_CQ_SRAM_ARRAY = 15797; // 3 +static const uint64_t SH_FLD_PE_CQ_SRAM_ARRAY_LEN = 15798; // 3 +static const uint64_t SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION = 15799; // 3 +static const uint64_t SH_FLD_PE_DISABLE_INJ_ON_RESEND = 15800; // 3 +static const uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP = 15801; // 3 +static const uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE = 15802; // 3 +static const uint64_t SH_FLD_PE_DISABLE_INTWR_VG = 15803; // 3 +static const uint64_t SH_FLD_PE_DISABLE_MC_PREFETCH = 15804; // 3 +static const uint64_t SH_FLD_PE_DISABLE_OOO_MODE = 15805; // 3 +static const uint64_t SH_FLD_PE_DISABLE_PCI_CLK_CHECK = 15806; // 3 +static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_GROUP = 15807; // 3 +static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_NODAL = 15808; // 3 +static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_RNNN = 15809; // 3 +static const uint64_t SH_FLD_PE_DISABLE_RD_VG = 15810; // 3 +static const uint64_t SH_FLD_PE_DISABLE_TCE_ARBITRATION = 15811; // 3 +static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP = 15812; // 3 +static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL = 15813; // 3 +static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN = 15814; // 3 +static const uint64_t SH_FLD_PE_DISABLE_TCE_VG = 15815; // 3 +static const uint64_t SH_FLD_PE_DISABLE_WR_SCOPE_GROUP = 15816; // 3 +static const uint64_t SH_FLD_PE_DISABLE_WR_VG = 15817; // 3 +static const uint64_t SH_FLD_PE_DROPPACECOUNT = 15818; // 3 +static const uint64_t SH_FLD_PE_DROPPACECOUNT_LEN = 15819; // 3 +static const uint64_t SH_FLD_PE_DROPPACEINC = 15820; // 3 +static const uint64_t SH_FLD_PE_DROPPACEINC_LEN = 15821; // 3 +static const uint64_t SH_FLD_PE_DROPPRIORITYMASK = 15822; // 3 +static const uint64_t SH_FLD_PE_DROPPRIORITYMASK_LEN = 15823; // 3 +static const uint64_t SH_FLD_PE_ECC_INJECT_TYPE = 15824; // 3 +static const uint64_t SH_FLD_PE_ECC_INJECT_TYPE_LEN = 15825; // 3 +static const uint64_t SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY = 15826; // 3 +static const uint64_t SH_FLD_PE_ENABLE_DMAR_IOPACING = 15827; // 3 +static const uint64_t SH_FLD_PE_ENABLE_DMAW_IOPACING = 15828; // 3 +static const uint64_t SH_FLD_PE_ENABLE_ENH_FLOW = 15829; // 3 +static const uint64_t SH_FLD_PE_ENABLE_IO_CMD_PACING = 15830; // 3 +static const uint64_t SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 15831; // 3 +static const uint64_t SH_FLD_PE_ENABLE_RD_SKIP_GROUP = 15832; // 3 +static const uint64_t SH_FLD_PE_ENABLE_TCE_SKIP_GROUP = 15833; // 3 +static const uint64_t SH_FLD_PE_ENHANCED_PEER2PEER_MODDE = 15834; // 9 +static const uint64_t SH_FLD_PE_ETU_RESET = 15835; // 9 +static const uint64_t SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 15836; // 3 +static const uint64_t SH_FLD_PE_HANG_SM_ON_ARE = 15837; // 3 +static const uint64_t SH_FLD_PE_IGNORE_SFSTAT = 15838; // 3 +static const uint64_t SH_FLD_PE_INBOUND_ACTIVE = 15839; // 9 +static const uint64_t SH_FLD_PE_INT_BAR = 15840; // 9 +static const uint64_t SH_FLD_PE_INT_BAR_EN = 15841; // 9 +static const uint64_t SH_FLD_PE_INT_BAR_LEN = 15842; // 9 +static const uint64_t SH_FLD_PE_ISMB_ERROR_INJECT = 15843; // 3 +static const uint64_t SH_FLD_PE_ISMB_ERROR_INJECT_LEN = 15844; // 3 +static const uint64_t SH_FLD_PE_LEN = 15845; // 45 +static const uint64_t SH_FLD_PE_MMIO_BAR0 = 15846; // 9 +static const uint64_t SH_FLD_PE_MMIO_BAR0_EN = 15847; // 9 +static const uint64_t SH_FLD_PE_MMIO_BAR0_LEN = 15848; // 9 +static const uint64_t SH_FLD_PE_MMIO_BAR1 = 15849; // 9 +static const uint64_t SH_FLD_PE_MMIO_BAR1_EN = 15850; // 9 +static const uint64_t SH_FLD_PE_MMIO_BAR1_LEN = 15851; // 9 +static const uint64_t SH_FLD_PE_MMIO_MASK0 = 15852; // 9 +static const uint64_t SH_FLD_PE_MMIO_MASK0_LEN = 15853; // 9 +static const uint64_t SH_FLD_PE_MMIO_MASK1 = 15854; // 9 +static const uint64_t SH_FLD_PE_MMIO_MASK1_LEN = 15855; // 9 +static const uint64_t SH_FLD_PE_OSMB_DATASTART_MODE = 15856; // 3 +static const uint64_t SH_FLD_PE_OSMB_DATASTART_MODE_LEN = 15857; // 3 +static const uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE = 15858; // 3 +static const uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN = 15859; // 3 +static const uint64_t SH_FLD_PE_OSMB_EARLY_START = 15860; // 3 +static const uint64_t SH_FLD_PE_OSMB_EARLY_START_LEN = 15861; // 3 +static const uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT = 15862; // 3 +static const uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN = 15863; // 3 +static const uint64_t SH_FLD_PE_OUTBOUND_ACTIVE = 15864; // 9 +static const uint64_t SH_FLD_PE_PCIE_CLK_TRACE_EN = 15865; // 3 +static const uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL = 15866; // 3 +static const uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN = 15867; // 3 +static const uint64_t SH_FLD_PE_PEER2PEER_MODDE = 15868; // 9 +static const uint64_t SH_FLD_PE_PERFMON_EN = 15869; // 3 +static const uint64_t SH_FLD_PE_PERFMON_EN_LEN = 15870; // 3 +static const uint64_t SH_FLD_PE_PERFMON_READ_TYPE = 15871; // 3 +static const uint64_t SH_FLD_PE_PERFMON_READ_TYPE_LEN = 15872; // 3 +static const uint64_t SH_FLD_PE_PHB_BAR = 15873; // 9 +static const uint64_t SH_FLD_PE_PHB_BAR_EN = 15874; // 9 +static const uint64_t SH_FLD_PE_PHB_BAR_LEN = 15875; // 9 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE0 = 15876; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE0_LEN = 15877; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE1 = 15878; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE1_LEN = 15879; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE2 = 15880; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE2_LEN = 15881; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE3 = 15882; // 3 +static const uint64_t SH_FLD_PE_PMON_MUX_BYTE3_LEN = 15883; // 3 +static const uint64_t SH_FLD_PE_QFIFO_HOLD_MODE = 15884; // 3 +static const uint64_t SH_FLD_PE_QFIFO_HOLD_MODE_LEN = 15885; // 3 +static const uint64_t SH_FLD_PE_RD_TIMEOUT_MASK = 15886; // 3 +static const uint64_t SH_FLD_PE_RD_TIMEOUT_MASK_LEN = 15887; // 3 +static const uint64_t SH_FLD_PE_RD_WRITE_ORDERING = 15888; // 3 +static const uint64_t SH_FLD_PE_RD_WRITE_ORDERING_LEN = 15889; // 3 +static const uint64_t SH_FLD_PE_RTYDROPDIVIDER = 15890; // 3 +static const uint64_t SH_FLD_PE_RTYDROPDIVIDER_LEN = 15891; // 3 +static const uint64_t SH_FLD_PE_SELECT_ETU_TRACE = 15892; // 3 +static const uint64_t SH_FLD_PE_STOP_STATE_ERROR = 15893; // 24 +static const uint64_t SH_FLD_PE_STOP_STATE_SIGNALED = 15894; // 6 +static const uint64_t SH_FLD_PE_STQ_ALLOCATION = 15895; // 3 +static const uint64_t SH_FLD_PE_TX_RESP_HWM = 15896; // 3 +static const uint64_t SH_FLD_PE_TX_RESP_HWM_LEN = 15897; // 3 +static const uint64_t SH_FLD_PE_TX_RESP_LWM = 15898; // 3 +static const uint64_t SH_FLD_PE_TX_RESP_LWM_LEN = 15899; // 3 +static const uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE = 15900; // 3 +static const uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN = 15901; // 3 +static const uint64_t SH_FLD_PE_WR_STRICT_ORDER_MODE = 15902; // 3 +static const uint64_t SH_FLD_PE_WR_TIMEOUT_MASK = 15903; // 3 +static const uint64_t SH_FLD_PE_WR_TIMEOUT_MASK_LEN = 15904; // 3 +static const uint64_t SH_FLD_PFD360SEL = 15905; // 4 +static const uint64_t SH_FLD_PFET_SEQ_PROGRAM = 15906; // 30 +static const uint64_t SH_FLD_PFIRACTION0 = 15907; // 9 +static const uint64_t SH_FLD_PFIRACTION0_LEN = 15908; // 9 +static const uint64_t SH_FLD_PFIRACTION1 = 15909; // 9 +static const uint64_t SH_FLD_PFIRACTION1_LEN = 15910; // 9 +static const uint64_t SH_FLD_PFIRMASK = 15911; // 9 +static const uint64_t SH_FLD_PFIRMASK_LEN = 15912; // 9 +static const uint64_t SH_FLD_PFIRPFIR = 15913; // 9 +static const uint64_t SH_FLD_PFIRPFIR_LEN = 15914; // 9 +static const uint64_t SH_FLD_PFREQ0 = 15915; // 24 +static const uint64_t SH_FLD_PFREQ0_LEN = 15916; // 24 +static const uint64_t SH_FLD_PFREQ1 = 15917; // 24 +static const uint64_t SH_FLD_PFREQ1_LEN = 15918; // 24 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH0 = 15919; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH0_LEN = 15920; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH1 = 15921; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH1_LEN = 15922; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH2 = 15923; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH2_LEN = 15924; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH3 = 15925; // 8 +static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH3_LEN = 15926; // 8 +static const uint64_t SH_FLD_PF_DROP_CNT_THRESH = 15927; // 4 +static const uint64_t SH_FLD_PF_DROP_CNT_THRESH_LEN = 15928; // 4 +static const uint64_t SH_FLD_PF_DROP_VALUE0 = 15929; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE0_LEN = 15930; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE1 = 15931; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE1_LEN = 15932; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE2 = 15933; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE2_LEN = 15934; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE3 = 15935; // 8 +static const uint64_t SH_FLD_PF_DROP_VALUE3_LEN = 15936; // 8 +static const uint64_t SH_FLD_PF_MACHINE_HANG = 15937; // 12 +static const uint64_t SH_FLD_PF_MACHINE_W4DT_HANG = 15938; // 12 +static const uint64_t SH_FLD_PF_PROMOTE_ASYNC_IF = 15939; // 8 +static const uint64_t SH_FLD_PF_PROMOTE_ERR_INJ = 15940; // 8 +static const uint64_t SH_FLD_PF_UNSOLICITED_CRESP = 15941; // 12 +static const uint64_t SH_FLD_PF_UNSOLICITED_DATA = 15942; // 12 +static const uint64_t SH_FLD_PGMIGR1_BAR = 15943; // 1 +static const uint64_t SH_FLD_PGMIGR1_BAR_LEN = 15944; // 1 +static const uint64_t SH_FLD_PGMIGR1_PGSZ = 15945; // 1 +static const uint64_t SH_FLD_PGMIGR1_PGSZ_LEN = 15946; // 1 +static const uint64_t SH_FLD_PGMIGR1_VAL = 15947; // 1 +static const uint64_t SH_FLD_PGMIGR2_BAR = 15948; // 1 +static const uint64_t SH_FLD_PGMIGR2_BAR_LEN = 15949; // 1 +static const uint64_t SH_FLD_PGMIGR2_PGSZ = 15950; // 1 +static const uint64_t SH_FLD_PGMIGR2_PGSZ_LEN = 15951; // 1 +static const uint64_t SH_FLD_PGMIGR2_VAL = 15952; // 1 +static const uint64_t SH_FLD_PGMIGR3_BAR = 15953; // 1 +static const uint64_t SH_FLD_PGMIGR3_BAR_LEN = 15954; // 1 +static const uint64_t SH_FLD_PGMIGR3_PGSZ = 15955; // 1 +static const uint64_t SH_FLD_PGMIGR3_PGSZ_LEN = 15956; // 1 +static const uint64_t SH_FLD_PGMIGR3_VAL = 15957; // 1 +static const uint64_t SH_FLD_PGMIGR4_BAR = 15958; // 1 +static const uint64_t SH_FLD_PGMIGR4_BAR_LEN = 15959; // 1 +static const uint64_t SH_FLD_PGMIGR4_PGSZ = 15960; // 1 +static const uint64_t SH_FLD_PGMIGR4_PGSZ_LEN = 15961; // 1 +static const uint64_t SH_FLD_PGMIGR4_VAL = 15962; // 1 +static const uint64_t SH_FLD_PGMIGR5_BAR = 15963; // 1 +static const uint64_t SH_FLD_PGMIGR5_BAR_LEN = 15964; // 1 +static const uint64_t SH_FLD_PGMIGR5_PGSZ = 15965; // 1 +static const uint64_t SH_FLD_PGMIGR5_PGSZ_LEN = 15966; // 1 +static const uint64_t SH_FLD_PGMIGR5_VAL = 15967; // 1 +static const uint64_t SH_FLD_PGMIGR6_BAR = 15968; // 1 +static const uint64_t SH_FLD_PGMIGR6_BAR_LEN = 15969; // 1 +static const uint64_t SH_FLD_PGMIGR6_PGSZ = 15970; // 1 +static const uint64_t SH_FLD_PGMIGR6_PGSZ_LEN = 15971; // 1 +static const uint64_t SH_FLD_PGMIGR6_VAL = 15972; // 1 +static const uint64_t SH_FLD_PGMIGR7_BAR = 15973; // 1 +static const uint64_t SH_FLD_PGMIGR7_BAR_LEN = 15974; // 1 +static const uint64_t SH_FLD_PGMIGR7_PGSZ = 15975; // 1 +static const uint64_t SH_FLD_PGMIGR7_PGSZ_LEN = 15976; // 1 +static const uint64_t SH_FLD_PGMIGR7_VAL = 15977; // 1 +static const uint64_t SH_FLD_PGM_DBG_ACCESS = 15978; // 1 +static const uint64_t SH_FLD_PGOFFIRSTLS = 15979; // 1 +static const uint64_t SH_FLD_PGOFFIRSTLS_LEN = 15980; // 1 +static const uint64_t SH_FLD_PGOFNEXTLS = 15981; // 1 +static const uint64_t SH_FLD_PGOFNEXTLS_LEN = 15982; // 1 +static const uint64_t SH_FLD_PGOOD_TIMEOUT_SEL = 15983; // 4 +static const uint64_t SH_FLD_PGOOD_TIMEOUT_SEL_LEN = 15984; // 4 +static const uint64_t SH_FLD_PG_MIG_DISABLED_ERR = 15985; // 2 +static const uint64_t SH_FLD_PG_MIG_SIZE_MISMATCH_ERR = 15986; // 2 +static const uint64_t SH_FLD_PHASEFB = 15987; // 4 +static const uint64_t SH_FLD_PHASEFB_LEN = 15988; // 4 +static const uint64_t SH_FLD_PHASE_CNT_CORRUPTION_ERR = 15989; // 43 +static const uint64_t SH_FLD_PHBCSR_SPARE = 15990; // 1 +static const uint64_t SH_FLD_PHBRESET_PE = 15991; // 9 +static const uint64_t SH_FLD_PHBRESET_SCOM_ERR = 15992; // 9 +static const uint64_t SH_FLD_PHB_FILTER_CNTL = 15993; // 2 +static const uint64_t SH_FLD_PHB_FILTER_CNTL_LEN = 15994; // 2 +static const uint64_t SH_FLD_PHB_LINK_DOWN = 15995; // 4 +static const uint64_t SH_FLD_PHY = 15996; // 6 +static const uint64_t SH_FLD_PHYP_SCOPE = 15997; // 1 +static const uint64_t SH_FLD_PHY_LEN = 15998; // 6 +static const uint64_t SH_FLD_PHY_RPTR_PARITY_ERROR = 15999; // 8 +static const uint64_t SH_FLD_PIB2PCB_DC = 16000; // 3 +static const uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID = 16001; // 1 +static const uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN = 16002; // 1 +static const uint64_t SH_FLD_PIB_0 = 16003; // 2 +static const uint64_t SH_FLD_PIB_0_LEN = 16004; // 2 +static const uint64_t SH_FLD_PIB_1 = 16005; // 2 +static const uint64_t SH_FLD_PIB_1_LEN = 16006; // 2 +static const uint64_t SH_FLD_PIB_2 = 16007; // 2 +static const uint64_t SH_FLD_PIB_2_LEN = 16008; // 2 +static const uint64_t SH_FLD_PIB_3 = 16009; // 2 +static const uint64_t SH_FLD_PIB_3_LEN = 16010; // 2 +static const uint64_t SH_FLD_PIB_ABORT = 16011; // 2 +static const uint64_t SH_FLD_PIB_ADDR = 16012; // 14 +static const uint64_t SH_FLD_PIB_ADDR_LEN = 16013; // 14 +static const uint64_t SH_FLD_PIB_ADDR_P = 16014; // 1 +static const uint64_t SH_FLD_PIB_ADDR_P_ERR = 16015; // 1 +static const uint64_t SH_FLD_PIB_BUSY = 16016; // 13 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0 = 16017; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0_LEN = 16018; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1 = 16019; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1_LEN = 16020; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2 = 16021; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2_LEN = 16022; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3 = 16023; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3_LEN = 16024; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 = 16025; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 = 16026; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 = 16027; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 = 16028; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_0 = 16029; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_1 = 16030; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_2 = 16031; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_3 = 16032; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 = 16033; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 = 16034; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 = 16035; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 = 16036; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 = 16037; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 = 16038; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 = 16039; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 = 16040; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 = 16041; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 = 16042; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 = 16043; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 = 16044; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0 = 16045; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN = 16046; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1 = 16047; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN = 16048; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2 = 16049; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN = 16050; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3 = 16051; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN = 16052; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0 = 16053; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN = 16054; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1 = 16055; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN = 16056; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2 = 16057; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN = 16058; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3 = 16059; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN = 16060; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0 = 16061; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN = 16062; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1 = 16063; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN = 16064; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2 = 16065; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN = 16066; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3 = 16067; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN = 16068; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0 = 16069; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN = 16070; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1 = 16071; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN = 16072; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2 = 16073; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN = 16074; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3 = 16075; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN = 16076; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0 = 16077; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN = 16078; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1 = 16079; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN = 16080; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2 = 16081; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN = 16082; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3 = 16083; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN = 16084; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 = 16085; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 16086; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 = 16087; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 16088; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 = 16089; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 16090; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 = 16091; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 16092; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0 = 16093; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0_LEN = 16094; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1 = 16095; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1_LEN = 16096; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2 = 16097; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2_LEN = 16098; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3 = 16099; // 1 +static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3_LEN = 16100; // 1 +static const uint64_t SH_FLD_PIB_COMPONENT_BUSY = 16101; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_0 = 16102; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_0_LEN = 16103; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_1 = 16104; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_1_LEN = 16105; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_2 = 16106; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_2_LEN = 16107; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_3 = 16108; // 1 +static const uint64_t SH_FLD_PIB_DATA0TO7_3_LEN = 16109; // 1 +static const uint64_t SH_FLD_PIB_DATAOP_PENDING = 16110; // 13 +static const uint64_t SH_FLD_PIB_DATA_P = 16111; // 1 +static const uint64_t SH_FLD_PIB_DATA_P_ERR = 16112; // 1 +static const uint64_t SH_FLD_PIB_ERROR_CODE = 16113; // 1 +static const uint64_t SH_FLD_PIB_ERROR_CODE_LEN = 16114; // 1 +static const uint64_t SH_FLD_PIB_FSM_STATE = 16115; // 1 +static const uint64_t SH_FLD_PIB_FSM_STATE_LEN = 16116; // 1 +static const uint64_t SH_FLD_PIB_HANG = 16117; // 1 +static const uint64_t SH_FLD_PIB_IFETCH_PENDING = 16118; // 21 +static const uint64_t SH_FLD_PIB_IMPRECISE_ERROR_PENDING = 16119; // 13 +static const uint64_t SH_FLD_PIB_MASTER_REQUEST = 16120; // 4 +static const uint64_t SH_FLD_PIB_MASTER_RSP_INFO = 16121; // 4 +static const uint64_t SH_FLD_PIB_MASTER_RSP_INFO_LEN = 16122; // 4 +static const uint64_t SH_FLD_PIB_RESET_DURING_PIB_ACCESS = 16123; // 4 +static const uint64_t SH_FLD_PIB_RESPONSE_INFO = 16124; // 1 +static const uint64_t SH_FLD_PIB_RESPONSE_INFO_LEN = 16125; // 1 +static const uint64_t SH_FLD_PIB_RSP_INFO = 16126; // 13 +static const uint64_t SH_FLD_PIB_RSP_INFO_LEN = 16127; // 13 +static const uint64_t SH_FLD_PIB_R_NW = 16128; // 13 +static const uint64_t SH_FLD_PIB_SLAVE_ADDR_INVALID = 16129; // 4 +static const uint64_t SH_FLD_PIB_SLAVE_ADDR_PARITY = 16130; // 4 +static const uint64_t SH_FLD_PIB_SLAVE_DATA_PARITY = 16131; // 4 +static const uint64_t SH_FLD_PIB_SLAVE_READ_INVALID = 16132; // 4 +static const uint64_t SH_FLD_PIB_SLAVE_WRITE_INVALID = 16133; // 4 +static const uint64_t SH_FLD_PID = 16134; // 305 +static const uint64_t SH_FLD_PID_LEN = 16135; // 305 +static const uint64_t SH_FLD_PID_MASK = 16136; // 1 +static const uint64_t SH_FLD_PID_MASK_LEN = 16137; // 1 +static const uint64_t SH_FLD_PIPELINE_ENABLE = 16138; // 1 +static const uint64_t SH_FLD_PIPE_COUNTER = 16139; // 1 +static const uint64_t SH_FLD_PIPE_COUNTER_LEN = 16140; // 1 +static const uint64_t SH_FLD_PIPE_MARGIN = 16141; // 48 +static const uint64_t SH_FLD_PIPE_SEL = 16142; // 120 +static const uint64_t SH_FLD_PIPE_SEL_LEN = 16143; // 48 +static const uint64_t SH_FLD_PI_ECC_CE = 16144; // 1 +static const uint64_t SH_FLD_PI_ECC_SUE = 16145; // 1 +static const uint64_t SH_FLD_PI_ECC_UE = 16146; // 1 +static const uint64_t SH_FLD_PLBARB_LOCKERR = 16147; // 1 +static const uint64_t SH_FLD_PLLCVHOLD = 16148; // 6 +static const uint64_t SH_FLD_PLLFMAX = 16149; // 6 +static const uint64_t SH_FLD_PLLFMIN = 16150; // 6 +static const uint64_t SH_FLD_PLLFORCE_OUT_EN = 16151; // 43 +static const uint64_t SH_FLD_PLLLOCK = 16152; // 4 +static const uint64_t SH_FLD_PLLLOCK_0_FILTER_PLL_NEST = 16153; // 1 +static const uint64_t SH_FLD_PLLLOCK_1_FILTER_PLL_MC = 16154; // 1 +static const uint64_t SH_FLD_PLLLOCK_2_XBUS = 16155; // 1 +static const uint64_t SH_FLD_PLLLOCK_3_NEST = 16156; // 1 +static const uint64_t SH_FLD_PLLREFSEL = 16157; // 3 +static const uint64_t SH_FLD_PLLREFSEL_LEN = 16158; // 3 +static const uint64_t SH_FLD_PLLRESET = 16159; // 6 +static const uint64_t SH_FLD_PLL_BNDY_BYPASS_EN = 16160; // 43 +static const uint64_t SH_FLD_PLL_BYPASS = 16161; // 43 +static const uint64_t SH_FLD_PLL_CLKIN_SEL = 16162; // 43 +static const uint64_t SH_FLD_PLL_DESTOUT = 16163; // 43 +static const uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL = 16164; // 4 +static const uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN = 16165; // 4 +static const uint64_t SH_FLD_PLL_REFCLKSEL_SCOM_EN = 16166; // 4 +static const uint64_t SH_FLD_PLL_RESET = 16167; // 43 +static const uint64_t SH_FLD_PLL_TEST_EN = 16168; // 43 +static const uint64_t SH_FLD_PLL_UNLOCK = 16169; // 43 +static const uint64_t SH_FLD_PLL_UNLOCK_LEN = 16170; // 43 +static const uint64_t SH_FLD_PLS = 16171; // 96 +static const uint64_t SH_FLD_PLS_LEN = 16172; // 96 +static const uint64_t SH_FLD_PL_ERR = 16173; // 6 +static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_EN = 16174; // 12 +static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM = 16175; // 12 +static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN = 16176; // 12 +static const uint64_t SH_FLD_PM03_SMT_ROTATION_DIS = 16177; // 12 +static const uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE = 16178; // 12 +static const uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN = 16179; // 12 +static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_EN = 16180; // 12 +static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM = 16181; // 12 +static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN = 16182; // 12 +static const uint64_t SH_FLD_PM47_SMT_ROTATION_DIS = 16183; // 12 +static const uint64_t SH_FLD_PMAE = 16184; // 96 +static const uint64_t SH_FLD_PMAO = 16185; // 96 +static const uint64_t SH_FLD_PMAOQ = 16186; // 96 +static const uint64_t SH_FLD_PMAOQ_HOT = 16187; // 96 +static const uint64_t SH_FLD_PMAOQ_TRC = 16188; // 96 +static const uint64_t SH_FLD_PMC1 = 16189; // 24 +static const uint64_t SH_FLD_PMC1CE = 16190; // 96 +static const uint64_t SH_FLD_PMC1COMB = 16191; // 96 +static const uint64_t SH_FLD_PMC1SEL = 16192; // 96 +static const uint64_t SH_FLD_PMC1SEL_LEN = 16193; // 96 +static const uint64_t SH_FLD_PMC1UNIT = 16194; // 96 +static const uint64_t SH_FLD_PMC1UNIT_LEN = 16195; // 96 +static const uint64_t SH_FLD_PMC1_EVENTS_UNIT_SELECTOR = 16196; // 96 +static const uint64_t SH_FLD_PMC1_EVENTS_UNIT_SELECTOR_LEN = 16197; // 96 +static const uint64_t SH_FLD_PMC1_EVENT_SELECTOR = 16198; // 96 +static const uint64_t SH_FLD_PMC1_EVENT_SELECTOR_LEN = 16199; // 96 +static const uint64_t SH_FLD_PMC2 = 16200; // 24 +static const uint64_t SH_FLD_PMC2COMB = 16201; // 96 +static const uint64_t SH_FLD_PMC2SEL = 16202; // 96 +static const uint64_t SH_FLD_PMC2SEL_LEN = 16203; // 96 +static const uint64_t SH_FLD_PMC2UNIT = 16204; // 96 +static const uint64_t SH_FLD_PMC2UNIT_LEN = 16205; // 96 +static const uint64_t SH_FLD_PMC2_EVENTS_UNIT_SELECTOR = 16206; // 96 +static const uint64_t SH_FLD_PMC2_EVENTS_UNIT_SELECTOR_LEN = 16207; // 96 +static const uint64_t SH_FLD_PMC2_EVENT_SELECTOR = 16208; // 96 +static const uint64_t SH_FLD_PMC2_EVENT_SELECTOR_LEN = 16209; // 96 +static const uint64_t SH_FLD_PMC3 = 16210; // 24 +static const uint64_t SH_FLD_PMC3COMB = 16211; // 96 +static const uint64_t SH_FLD_PMC3SEL = 16212; // 96 +static const uint64_t SH_FLD_PMC3SEL_LEN = 16213; // 96 +static const uint64_t SH_FLD_PMC3UNIT = 16214; // 96 +static const uint64_t SH_FLD_PMC3UNIT_LEN = 16215; // 96 +static const uint64_t SH_FLD_PMC3_EVENTS_UNIT_SELECTOR = 16216; // 96 +static const uint64_t SH_FLD_PMC3_EVENTS_UNIT_SELECTOR_LEN = 16217; // 96 +static const uint64_t SH_FLD_PMC3_EVENT_SELECTOR = 16218; // 96 +static const uint64_t SH_FLD_PMC3_EVENT_SELECTOR_LEN = 16219; // 96 +static const uint64_t SH_FLD_PMC4 = 16220; // 24 +static const uint64_t SH_FLD_PMC4COMB = 16221; // 96 +static const uint64_t SH_FLD_PMC4SEL = 16222; // 96 +static const uint64_t SH_FLD_PMC4SEL_LEN = 16223; // 96 +static const uint64_t SH_FLD_PMC4UNIT = 16224; // 96 +static const uint64_t SH_FLD_PMC4UNIT_LEN = 16225; // 96 +static const uint64_t SH_FLD_PMC4_EVENTS_UNIT_SELECTOR = 16226; // 96 +static const uint64_t SH_FLD_PMC4_EVENTS_UNIT_SELECTOR_LEN = 16227; // 96 +static const uint64_t SH_FLD_PMC4_EVENT_SELECTOR = 16228; // 96 +static const uint64_t SH_FLD_PMC4_EVENT_SELECTOR_LEN = 16229; // 96 +static const uint64_t SH_FLD_PMC5 = 16230; // 24 +static const uint64_t SH_FLD_PMC6 = 16231; // 24 +static const uint64_t SH_FLD_PMCC = 16232; // 96 +static const uint64_t SH_FLD_PMCC_LEN = 16233; // 96 +static const uint64_t SH_FLD_PMCJCE = 16234; // 96 +static const uint64_t SH_FLD_PMCM_THRESHOLD = 16235; // 24 +static const uint64_t SH_FLD_PMCM_THRESHOLD_LEN = 16236; // 24 +static const uint64_t SH_FLD_PMCR = 16237; // 24 +static const uint64_t SH_FLD_PMCR_LEN = 16238; // 24 +static const uint64_t SH_FLD_PMCR_OVERRIDE_EN = 16239; // 12 +static const uint64_t SH_FLD_PMCR_UPDATE_C0 = 16240; // 12 +static const uint64_t SH_FLD_PMCR_UPDATE_C1 = 16241; // 12 +static const uint64_t SH_FLD_PMC_ENABLE = 16242; // 1 +static const uint64_t SH_FLD_PMC_O2S_0A_ONGOING = 16243; // 1 +static const uint64_t SH_FLD_PMC_O2S_0B_ONGOING = 16244; // 1 +static const uint64_t SH_FLD_PMC_O2S_1A_ONGOING = 16245; // 1 +static const uint64_t SH_FLD_PMC_O2S_1B_ONGOING = 16246; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE0_PENDING = 16247; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE1_PENDING = 16248; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE2_PENDING = 16249; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE3_PENDING = 16250; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE4_PENDING = 16251; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE5_PENDING = 16252; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE6_PENDING = 16253; // 1 +static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE7_PENDING = 16254; // 1 +static const uint64_t SH_FLD_PMISC_CRESP_ADDR_ERR = 16255; // 12 +static const uint64_t SH_FLD_PMISC_MODE = 16256; // 9 +static const uint64_t SH_FLD_PMM = 16257; // 96 +static const uint64_t SH_FLD_PMON_GROUP_SELECT = 16258; // 2 +static const uint64_t SH_FLD_PMON_GROUP_SELECT_LEN = 16259; // 2 +static const uint64_t SH_FLD_PMON_MUX_BYTE0_0_2 = 16260; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE0_0_2_LEN = 16261; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE1_0_2 = 16262; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE1_0_2_LEN = 16263; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE2_0_2 = 16264; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE2_0_2_LEN = 16265; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE3_0_2 = 16266; // 1 +static const uint64_t SH_FLD_PMON_MUX_BYTE3_0_2_LEN = 16267; // 1 +static const uint64_t SH_FLD_PMSR = 16268; // 24 +static const uint64_t SH_FLD_PMSR_LEN = 16269; // 24 +static const uint64_t SH_FLD_PMSR_OVERRIDE_EN = 16270; // 12 +static const uint64_t SH_FLD_PMU0145_EVENT0_MODE = 16271; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT0_MODE_LEN = 16272; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT1_MODE = 16273; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT1_MODE_LEN = 16274; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT2_MODE = 16275; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT2_MODE_LEN = 16276; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT3_MODE = 16277; // 2 +static const uint64_t SH_FLD_PMU0145_EVENT3_MODE_LEN = 16278; // 2 +static const uint64_t SH_FLD_PMU01_LINK_SELECT = 16279; // 2 +static const uint64_t SH_FLD_PMU0_ENABLE = 16280; // 2 +static const uint64_t SH_FLD_PMU0_SIZE = 16281; // 2 +static const uint64_t SH_FLD_PMU0_SIZE_LEN = 16282; // 2 +static const uint64_t SH_FLD_PMU1_ENABLE = 16283; // 2 +static const uint64_t SH_FLD_PMU1_SIZE = 16284; // 2 +static const uint64_t SH_FLD_PMU1_SIZE_LEN = 16285; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT0_MODE = 16286; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT0_MODE_LEN = 16287; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT1_MODE = 16288; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT1_MODE_LEN = 16289; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT2_MODE = 16290; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT2_MODE_LEN = 16291; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT3_MODE = 16292; // 2 +static const uint64_t SH_FLD_PMU2367_EVENT3_MODE_LEN = 16293; // 2 +static const uint64_t SH_FLD_PMU23_LINK_SELECT = 16294; // 2 +static const uint64_t SH_FLD_PMU2_ENABLE = 16295; // 2 +static const uint64_t SH_FLD_PMU2_SIZE = 16296; // 2 +static const uint64_t SH_FLD_PMU2_SIZE_LEN = 16297; // 2 +static const uint64_t SH_FLD_PMU3_ENABLE = 16298; // 2 +static const uint64_t SH_FLD_PMU3_SIZE = 16299; // 2 +static const uint64_t SH_FLD_PMU3_SIZE_LEN = 16300; // 2 +static const uint64_t SH_FLD_PMU45_LINK_SELECT = 16301; // 2 +static const uint64_t SH_FLD_PMU4_ENABLE = 16302; // 2 +static const uint64_t SH_FLD_PMU5_ENABLE = 16303; // 2 +static const uint64_t SH_FLD_PMU67_LINK_SELECT = 16304; // 2 +static const uint64_t SH_FLD_PMU6_ENABLE = 16305; // 2 +static const uint64_t SH_FLD_PMU7_ENABLE = 16306; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT = 16307; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 16308; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER0_ENABLE = 16309; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT = 16310; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN = 16311; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT = 16312; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT = 16313; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 16314; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER1_ENABLE = 16315; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT = 16316; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN = 16317; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT = 16318; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT = 16319; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 16320; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER2_ENABLE = 16321; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT = 16322; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN = 16323; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT = 16324; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT = 16325; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 16326; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER3_ENABLE = 16327; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT = 16328; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN = 16329; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT = 16330; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER_FREEZE_MODE = 16331; // 2 +static const uint64_t SH_FLD_PMUA_COUNTER_RESET_MODE = 16332; // 2 +static const uint64_t SH_FLD_PMUA_PORT_SELECT = 16333; // 2 +static const uint64_t SH_FLD_PMUA_PORT_SELECT_LEN = 16334; // 2 +static const uint64_t SH_FLD_PMUA_PRESCALER_SELECT = 16335; // 2 +static const uint64_t SH_FLD_PMUA_PRESCALER_SELECT_LEN = 16336; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT = 16337; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 16338; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER0_ENABLE = 16339; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT = 16340; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN = 16341; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT = 16342; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT = 16343; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 16344; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER1_ENABLE = 16345; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT = 16346; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN = 16347; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT = 16348; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT = 16349; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 16350; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER2_ENABLE = 16351; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT = 16352; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN = 16353; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT = 16354; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT = 16355; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 16356; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER3_ENABLE = 16357; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT = 16358; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN = 16359; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT = 16360; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER_FREEZE_MODE = 16361; // 2 +static const uint64_t SH_FLD_PMUB_COUNTER_RESET_MODE = 16362; // 2 +static const uint64_t SH_FLD_PMUB_PORT_SELECT = 16363; // 2 +static const uint64_t SH_FLD_PMUB_PORT_SELECT_LEN = 16364; // 2 +static const uint64_t SH_FLD_PMUB_PRESCALER_SELECT = 16365; // 2 +static const uint64_t SH_FLD_PMUB_PRESCALER_SELECT_LEN = 16366; // 2 +static const uint64_t SH_FLD_PMULET_FREEZE_MODE = 16367; // 7 +static const uint64_t SH_FLD_PMULET_RESET_MODE = 16368; // 2 +static const uint64_t SH_FLD_PMUT0_SPR_HOLD_OUT = 16369; // 24 +static const uint64_t SH_FLD_PMUT0_SPR_HOLD_OUT_LEN = 16370; // 24 +static const uint64_t SH_FLD_PMUT1_SPR_HOLD_OUT = 16371; // 24 +static const uint64_t SH_FLD_PMUT1_SPR_HOLD_OUT_LEN = 16372; // 24 +static const uint64_t SH_FLD_PMUT2_SPR_HOLD_OUT = 16373; // 24 +static const uint64_t SH_FLD_PMUT2_SPR_HOLD_OUT_LEN = 16374; // 24 +static const uint64_t SH_FLD_PMUT3_SPR_HOLD_OUT = 16375; // 24 +static const uint64_t SH_FLD_PMUT3_SPR_HOLD_OUT_LEN = 16376; // 24 +static const uint64_t SH_FLD_PMU_BUS_ENABLE = 16377; // 2 +static const uint64_t SH_FLD_PMU_BUS_ENABLE_LEN = 16378; // 2 +static const uint64_t SH_FLD_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD = 16379; // 2 +static const uint64_t SH_FLD_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD = 16380; // 2 +static const uint64_t SH_FLD_PMU_ENABLE = 16381; // 2 +static const uint64_t SH_FLD_PMU_EVENT_SEL_REG_PARITY_ERRHOLD = 16382; // 2 +static const uint64_t SH_FLD_PMU_SELECT_HIGH = 16383; // 2 +static const uint64_t SH_FLD_PMU_SELECT_HIGH_LEN = 16384; // 2 +static const uint64_t SH_FLD_PMU_SELECT_LOW = 16385; // 2 +static const uint64_t SH_FLD_PMU_SELECT_LOW_LEN = 16386; // 2 +static const uint64_t SH_FLD_PM_ACCESS = 16387; // 129 +static const uint64_t SH_FLD_PM_ACCESS_LEN = 16388; // 43 +static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0 = 16389; // 12 +static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 16390; // 12 +static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1 = 16391; // 12 +static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 16392; // 12 +static const uint64_t SH_FLD_PM_ENTRY_ACK_C0 = 16393; // 12 +static const uint64_t SH_FLD_PM_ENTRY_ACK_C0_ACTUAL = 16394; // 12 +static const uint64_t SH_FLD_PM_ENTRY_ACK_C1 = 16395; // 12 +static const uint64_t SH_FLD_PM_ENTRY_ACK_C1_ACTUAL = 16396; // 12 +static const uint64_t SH_FLD_PM_ERROR = 16397; // 6 +static const uint64_t SH_FLD_PM_EXIT_C0 = 16398; // 12 +static const uint64_t SH_FLD_PM_EXIT_C0_ACTUAL = 16399; // 12 +static const uint64_t SH_FLD_PM_EXIT_C1 = 16400; // 12 +static const uint64_t SH_FLD_PM_EXIT_C1_ACTUAL = 16401; // 12 +static const uint64_t SH_FLD_PM_STATE_ACTIVE_C0 = 16402; // 12 +static const uint64_t SH_FLD_PM_STATE_ACTIVE_C1 = 16403; // 12 +static const uint64_t SH_FLD_PM_STATE_ALL_HV_C0 = 16404; // 12 +static const uint64_t SH_FLD_PM_STATE_ALL_HV_C1 = 16405; // 12 +static const uint64_t SH_FLD_PM_STATE_C0 = 16406; // 12 +static const uint64_t SH_FLD_PM_STATE_C0_LEN = 16407; // 12 +static const uint64_t SH_FLD_PM_STATE_C1 = 16408; // 12 +static const uint64_t SH_FLD_PM_STATE_C1_LEN = 16409; // 12 +static const uint64_t SH_FLD_POCKET_ND_RATE1 = 16410; // 12 +static const uint64_t SH_FLD_POCKET_ND_RATE1_LEN = 16411; // 12 +static const uint64_t SH_FLD_POCKET_RATE1 = 16412; // 12 +static const uint64_t SH_FLD_POCKET_RATE1_LEN = 16413; // 12 +static const uint64_t SH_FLD_POCKET_RATE2 = 16414; // 12 +static const uint64_t SH_FLD_POCKET_RATE2_LEN = 16415; // 12 +static const uint64_t SH_FLD_POCKET_RATE3 = 16416; // 12 +static const uint64_t SH_FLD_POCKET_RATE3_LEN = 16417; // 12 +static const uint64_t SH_FLD_POD0 = 16418; // 50 +static const uint64_t SH_FLD_POD0_LEN = 16419; // 50 +static const uint64_t SH_FLD_POD1 = 16420; // 50 +static const uint64_t SH_FLD_POD10 = 16421; // 50 +static const uint64_t SH_FLD_POD10_LEN = 16422; // 50 +static const uint64_t SH_FLD_POD1_LEN = 16423; // 50 +static const uint64_t SH_FLD_POD2 = 16424; // 50 +static const uint64_t SH_FLD_POD2_LEN = 16425; // 50 +static const uint64_t SH_FLD_POD3 = 16426; // 50 +static const uint64_t SH_FLD_POD3_LEN = 16427; // 50 +static const uint64_t SH_FLD_POD4 = 16428; // 50 +static const uint64_t SH_FLD_POD4_LEN = 16429; // 50 +static const uint64_t SH_FLD_POD5 = 16430; // 50 +static const uint64_t SH_FLD_POD5_LEN = 16431; // 50 +static const uint64_t SH_FLD_POD6 = 16432; // 50 +static const uint64_t SH_FLD_POD6_LEN = 16433; // 50 +static const uint64_t SH_FLD_POD7 = 16434; // 50 +static const uint64_t SH_FLD_POD7_LEN = 16435; // 50 +static const uint64_t SH_FLD_POD8 = 16436; // 50 +static const uint64_t SH_FLD_POD8_LEN = 16437; // 50 +static const uint64_t SH_FLD_POD9 = 16438; // 50 +static const uint64_t SH_FLD_POD9_LEN = 16439; // 50 +static const uint64_t SH_FLD_POINTER = 16440; // 2 +static const uint64_t SH_FLD_POINTER_LEN = 16441; // 2 +static const uint64_t SH_FLD_POLLING_TIMEOUT_SEL = 16442; // 6 +static const uint64_t SH_FLD_POLLING_TIMEOUT_SEL_LEN = 16443; // 6 +static const uint64_t SH_FLD_POLL_BCST_RTY_MON = 16444; // 1 +static const uint64_t SH_FLD_POLL_DONE = 16445; // 1 +static const uint64_t SH_FLD_POOL = 16446; // 1 +static const uint64_t SH_FLD_POOL_LEN = 16447; // 1 +static const uint64_t SH_FLD_PORT0_ERROR_CODE = 16448; // 3 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_0 = 16449; // 1 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_0_LEN = 16450; // 1 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_1 = 16451; // 2 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_1_LEN = 16452; // 2 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_2 = 16453; // 3 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_2_LEN = 16454; // 3 +static const uint64_t SH_FLD_PORT0_ERROR_CODE_LEN = 16455; // 3 +static const uint64_t SH_FLD_PORT1_ERROR_CODE = 16456; // 3 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_0 = 16457; // 1 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_0_LEN = 16458; // 1 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_1 = 16459; // 2 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_1_LEN = 16460; // 2 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_2 = 16461; // 3 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_2_LEN = 16462; // 3 +static const uint64_t SH_FLD_PORT1_ERROR_CODE_LEN = 16463; // 3 +static const uint64_t SH_FLD_PORT2_ERROR_CODE = 16464; // 3 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_0 = 16465; // 1 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_0_LEN = 16466; // 1 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_1 = 16467; // 2 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_1_LEN = 16468; // 2 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_2 = 16469; // 3 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_2_LEN = 16470; // 3 +static const uint64_t SH_FLD_PORT2_ERROR_CODE_LEN = 16471; // 3 +static const uint64_t SH_FLD_PORT3_ERROR_CODE = 16472; // 3 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_0 = 16473; // 1 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_0_LEN = 16474; // 1 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_1 = 16475; // 2 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_1_LEN = 16476; // 2 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_2 = 16477; // 3 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_2_LEN = 16478; // 3 +static const uint64_t SH_FLD_PORT3_ERROR_CODE_LEN = 16479; // 3 +static const uint64_t SH_FLD_PORT4_ERROR_CODE = 16480; // 3 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_0 = 16481; // 1 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_0_LEN = 16482; // 1 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_1 = 16483; // 2 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_1_LEN = 16484; // 2 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_2 = 16485; // 3 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_2_LEN = 16486; // 3 +static const uint64_t SH_FLD_PORT4_ERROR_CODE_LEN = 16487; // 3 +static const uint64_t SH_FLD_PORT5_ERROR_CODE = 16488; // 3 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_0 = 16489; // 1 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_0_LEN = 16490; // 1 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_1 = 16491; // 2 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_1_LEN = 16492; // 2 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_2 = 16493; // 3 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_2_LEN = 16494; // 3 +static const uint64_t SH_FLD_PORT5_ERROR_CODE_LEN = 16495; // 3 +static const uint64_t SH_FLD_PORT6_ERROR_CODE = 16496; // 3 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_0 = 16497; // 1 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_0_LEN = 16498; // 1 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_1 = 16499; // 2 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_1_LEN = 16500; // 2 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_2 = 16501; // 3 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_2_LEN = 16502; // 3 +static const uint64_t SH_FLD_PORT6_ERROR_CODE_LEN = 16503; // 3 +static const uint64_t SH_FLD_PORT7_ERROR_CODE = 16504; // 3 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_0 = 16505; // 1 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_0_LEN = 16506; // 1 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_1 = 16507; // 2 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_1_LEN = 16508; // 2 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_2 = 16509; // 3 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_2_LEN = 16510; // 3 +static const uint64_t SH_FLD_PORT7_ERROR_CODE_LEN = 16511; // 3 +static const uint64_t SH_FLD_PORTPOWERDOWN = 16512; // 8 +static const uint64_t SH_FLD_PORTSEL = 16513; // 2 +static const uint64_t SH_FLD_PORTSEL_LEN = 16514; // 2 +static const uint64_t SH_FLD_PORT_0_ENABLE = 16515; // 1 +static const uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP = 16516; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 16517; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP = 16518; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 16519; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE = 16520; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP = 16521; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 16522; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 16523; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 16524; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE = 16525; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 16526; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 16527; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE = 16528; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP = 16529; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 16530; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 16531; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 16532; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 16533; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 16534; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP = 16535; // 2 +static const uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 16536; // 2 +static const uint64_t SH_FLD_PORT_1_ENABLE = 16537; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP = 16538; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 16539; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP = 16540; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 16541; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE = 16542; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP = 16543; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 16544; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 16545; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 16546; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE = 16547; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 16548; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 16549; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE = 16550; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP = 16551; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 16552; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 16553; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 16554; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 16555; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 16556; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP = 16557; // 2 +static const uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 16558; // 2 +static const uint64_t SH_FLD_PORT_2_ENABLE = 16559; // 3 +static const uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP = 16560; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 16561; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP = 16562; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 16563; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE = 16564; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP = 16565; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 16566; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 16567; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 16568; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE = 16569; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 16570; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 16571; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE = 16572; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP = 16573; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 16574; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 16575; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 16576; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 16577; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 16578; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP = 16579; // 2 +static const uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 16580; // 2 +static const uint64_t SH_FLD_PORT_3_ENABLE = 16581; // 3 +static const uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP = 16582; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 16583; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP = 16584; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 16585; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE = 16586; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP = 16587; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 16588; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 16589; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 16590; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE = 16591; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 16592; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 16593; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE = 16594; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP = 16595; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 16596; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 16597; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 16598; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 16599; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 16600; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP = 16601; // 2 +static const uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 16602; // 2 +static const uint64_t SH_FLD_PORT_4_ENABLE = 16603; // 3 +static const uint64_t SH_FLD_PORT_5_ENABLE = 16604; // 3 +static const uint64_t SH_FLD_PORT_6_ENABLE = 16605; // 3 +static const uint64_t SH_FLD_PORT_7_ENABLE = 16606; // 3 +static const uint64_t SH_FLD_PORT_ENABLE = 16607; // 3 +static const uint64_t SH_FLD_PORT_ERROR_RESET = 16608; // 4 +static const uint64_t SH_FLD_PORT_ERROR_RESET_1 = 16609; // 2 +static const uint64_t SH_FLD_PORT_ERROR_RESET_2 = 16610; // 3 +static const uint64_t SH_FLD_PORT_ERROR_RESET_3 = 16611; // 3 +static const uint64_t SH_FLD_PORT_ERROR_RESET_4 = 16612; // 3 +static const uint64_t SH_FLD_PORT_ERROR_RESET_5 = 16613; // 3 +static const uint64_t SH_FLD_PORT_ERROR_RESET_6 = 16614; // 3 +static const uint64_t SH_FLD_PORT_ERROR_RESET_7 = 16615; // 3 +static const uint64_t SH_FLD_PORT_FAIL = 16616; // 8 +static const uint64_t SH_FLD_PORT_GENERAL_RESET = 16617; // 4 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_1 = 16618; // 2 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_2 = 16619; // 3 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_3 = 16620; // 3 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_4 = 16621; // 3 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_5 = 16622; // 3 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_6 = 16623; // 3 +static const uint64_t SH_FLD_PORT_GENERAL_RESET_7 = 16624; // 3 +static const uint64_t SH_FLD_PORT_HOT_PLUG = 16625; // 6 +static const uint64_t SH_FLD_PORT_HOT_PLUG_0 = 16626; // 2 +static const uint64_t SH_FLD_PORT_HOT_PLUG_1 = 16627; // 4 +static const uint64_t SH_FLD_PORT_HOT_PLUG_2 = 16628; // 6 +static const uint64_t SH_FLD_PORT_HOT_PLUG_3 = 16629; // 6 +static const uint64_t SH_FLD_PORT_HOT_PLUG_4 = 16630; // 6 +static const uint64_t SH_FLD_PORT_HOT_PLUG_5 = 16631; // 6 +static const uint64_t SH_FLD_PORT_HOT_PLUG_6 = 16632; // 6 +static const uint64_t SH_FLD_PORT_HOT_PLUG_7 = 16633; // 6 +static const uint64_t SH_FLD_PORT_IS_FENCED = 16634; // 3 +static const uint64_t SH_FLD_PORT_LEVEL = 16635; // 6 +static const uint64_t SH_FLD_PORT_LEVEL_0 = 16636; // 2 +static const uint64_t SH_FLD_PORT_LEVEL_1 = 16637; // 4 +static const uint64_t SH_FLD_PORT_LEVEL_2 = 16638; // 6 +static const uint64_t SH_FLD_PORT_LEVEL_3 = 16639; // 6 +static const uint64_t SH_FLD_PORT_LEVEL_4 = 16640; // 6 +static const uint64_t SH_FLD_PORT_LEVEL_5 = 16641; // 6 +static const uint64_t SH_FLD_PORT_LEVEL_6 = 16642; // 6 +static const uint64_t SH_FLD_PORT_LEVEL_7 = 16643; // 6 +static const uint64_t SH_FLD_PORT_NUMBER_0 = 16644; // 2 +static const uint64_t SH_FLD_PORT_NUMBER_0_LEN = 16645; // 2 +static const uint64_t SH_FLD_PORT_NUMBER_1 = 16646; // 1 +static const uint64_t SH_FLD_PORT_NUMBER_1_LEN = 16647; // 1 +static const uint64_t SH_FLD_PORT_NUMBER_2 = 16648; // 1 +static const uint64_t SH_FLD_PORT_NUMBER_2_LEN = 16649; // 1 +static const uint64_t SH_FLD_PORT_NUMBER_3 = 16650; // 1 +static const uint64_t SH_FLD_PORT_NUMBER_3_LEN = 16651; // 1 +static const uint64_t SH_FLD_PORT_SEL = 16652; // 1 +static const uint64_t SH_FLD_PORT_SEL_LEN = 16653; // 1 +static const uint64_t SH_FLD_POST_LDBAR = 16654; // 96 +static const uint64_t SH_FLD_POWDN_DLY = 16655; // 30 +static const uint64_t SH_FLD_POWDN_DLY_LEN = 16656; // 30 +static const uint64_t SH_FLD_POWERBUS_DATA_HANG_ERROR = 16657; // 4 +static const uint64_t SH_FLD_POWERBUS_HANG_ERROR = 16658; // 4 +static const uint64_t SH_FLD_POWERBUS_INTERFACE_PE = 16659; // 4 +static const uint64_t SH_FLD_POWERBUS_MISC_ERROR = 16660; // 4 +static const uint64_t SH_FLD_POWERBUS_PROTOCOL_ERROR = 16661; // 4 +static const uint64_t SH_FLD_POWER_MANAGEMENT_INTERRUPT = 16662; // 1 +static const uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N = 16663; // 96 +static const uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N_LEN = 16664; // 96 +static const uint64_t SH_FLD_POWER_UP_CNTR_REF = 16665; // 1 +static const uint64_t SH_FLD_POWER_UP_CNTR_REF_LEN = 16666; // 1 +static const uint64_t SH_FLD_POWUP_DLY = 16667; // 30 +static const uint64_t SH_FLD_POWUP_DLY_LEN = 16668; // 30 +static const uint64_t SH_FLD_PPC405_CHIP_RESET = 16669; // 1 +static const uint64_t SH_FLD_PPC405_CHIP_RESET_MASK = 16670; // 1 +static const uint64_t SH_FLD_PPC405_CORE_RESET = 16671; // 1 +static const uint64_t SH_FLD_PPC405_CORE_RESET_MASK = 16672; // 1 +static const uint64_t SH_FLD_PPC405_DBGMSRWE = 16673; // 1 +static const uint64_t SH_FLD_PPC405_DBGMSRWE_MASK = 16674; // 1 +static const uint64_t SH_FLD_PPC405_DBGSTOPACK = 16675; // 1 +static const uint64_t SH_FLD_PPC405_DBGSTOPACK_MASK = 16676; // 1 +static const uint64_t SH_FLD_PPC405_HALT = 16677; // 1 +static const uint64_t SH_FLD_PPC405_SYSTEM_RESET = 16678; // 1 +static const uint64_t SH_FLD_PPC405_SYSTEM_RESET_MASK = 16679; // 1 +static const uint64_t SH_FLD_PPC_INSTR = 16680; // 24 +static const uint64_t SH_FLD_PPC_INSTR_LEN = 16681; // 24 +static const uint64_t SH_FLD_PPC_PREDCD = 16682; // 24 +static const uint64_t SH_FLD_PPC_PREDCD_LEN = 16683; // 24 +static const uint64_t SH_FLD_PPE_BREAKPOINT_ERROR = 16684; // 12 +static const uint64_t SH_FLD_PPE_DEBUG_TRIGGER = 16685; // 12 +static const uint64_t SH_FLD_PPE_EXTERNAL_ERROR = 16686; // 12 +static const uint64_t SH_FLD_PPE_GCR = 16687; // 4 +static const uint64_t SH_FLD_PPE_HALTED = 16688; // 12 +static const uint64_t SH_FLD_PPE_INTERNAL_ERROR = 16689; // 12 +static const uint64_t SH_FLD_PPE_PROGRESS_ERROR = 16690; // 12 +static const uint64_t SH_FLD_PPE_RD_ACK_DEAD = 16691; // 12 +static const uint64_t SH_FLD_PPE_RD_CRESP_ADDR_ERR = 16692; // 12 +static const uint64_t SH_FLD_PPE_WATCHDOG = 16693; // 12 +static const uint64_t SH_FLD_PPE_WR_ACK_DEAD = 16694; // 12 +static const uint64_t SH_FLD_PPE_WR_CRESP_ADDR_ERR = 16695; // 12 +static const uint64_t SH_FLD_PPE_XIRAMEDR_EDR = 16696; // 4 +static const uint64_t SH_FLD_PPE_XIRAMEDR_EDR_LEN = 16697; // 4 +static const uint64_t SH_FLD_PPE_XIRAMGA_IR = 16698; // 4 +static const uint64_t SH_FLD_PPE_XIRAMGA_IR_LEN = 16699; // 4 +static const uint64_t SH_FLD_PPE_XIRAMRA_SPRG0 = 16700; // 4 +static const uint64_t SH_FLD_PPE_XIRAMRA_SPRG0_LEN = 16701; // 4 +static const uint64_t SH_FLD_PPE_XIXCR_XCR = 16702; // 8 +static const uint64_t SH_FLD_PPE_XIXCR_XCR_LEN = 16703; // 8 +static const uint64_t SH_FLD_PPM_SPARE_OUT_C0 = 16704; // 12 +static const uint64_t SH_FLD_PPM_SPARE_OUT_C1 = 16705; // 12 +static const uint64_t SH_FLD_PPM_WRITE_DISABLE = 16706; // 24 +static const uint64_t SH_FLD_PPM_WRITE_OVERRIDE = 16707; // 24 +static const uint64_t SH_FLD_PQ_STATE = 16708; // 1 +static const uint64_t SH_FLD_PQ_STATE_LEN = 16709; // 1 +static const uint64_t SH_FLD_PR = 16710; // 96 +static const uint64_t SH_FLD_PRB0 = 16711; // 12 +static const uint64_t SH_FLD_PRB1 = 16712; // 12 +static const uint64_t SH_FLD_PRBS = 16713; // 2 +static const uint64_t SH_FLD_PRBS_CHECK_SYNC = 16714; // 72 +static const uint64_t SH_FLD_PRBS_INVERT = 16715; // 2 +static const uint64_t SH_FLD_PRBS_LEN = 16716; // 2 +static const uint64_t SH_FLD_PRBS_PHASE_SELECT = 16717; // 2 +static const uint64_t SH_FLD_PRBS_PHASE_SELECT_LEN = 16718; // 2 +static const uint64_t SH_FLD_PRBS_RXBIST_MODE = 16719; // 72 +static const uint64_t SH_FLD_PRBS_SCRAMBLE_MODE = 16720; // 144 +static const uint64_t SH_FLD_PRBS_SCRAMBLE_MODE_LEN = 16721; // 144 +static const uint64_t SH_FLD_PRBS_SEED_DDC = 16722; // 72 +static const uint64_t SH_FLD_PRBS_SEED_DFE = 16723; // 72 +static const uint64_t SH_FLD_PRBS_SEED_MODE = 16724; // 4 +static const uint64_t SH_FLD_PRBS_SEED_VALUE_0_15 = 16725; // 140 +static const uint64_t SH_FLD_PRBS_SEED_VALUE_0_15_LEN = 16726; // 140 +static const uint64_t SH_FLD_PRBS_SEED_VALUE_16_22 = 16727; // 140 +static const uint64_t SH_FLD_PRBS_SEED_VALUE_16_22_LEN = 16728; // 140 +static const uint64_t SH_FLD_PRBS_SLS_EXPECT = 16729; // 4 +static const uint64_t SH_FLD_PRBS_SLS_EXPECT_LEN = 16730; // 4 +static const uint64_t SH_FLD_PRBS_SYNC_MODE = 16731; // 72 +static const uint64_t SH_FLD_PRBS_TEST_DATA = 16732; // 120 +static const uint64_t SH_FLD_PRBS_TEST_DATA_LEN = 16733; // 120 +static const uint64_t SH_FLD_PRECISE_DIR_FLUSH_FAILED = 16734; // 2 +static const uint64_t SH_FLD_PRECISE_DIR_SIZE = 16735; // 2 +static const uint64_t SH_FLD_PRECISE_DIR_SIZE_LEN = 16736; // 2 +static const uint64_t SH_FLD_PRECLUDE = 16737; // 1 +static const uint64_t SH_FLD_PREF2DMD = 16738; // 1 +static const uint64_t SH_FLD_PREFETCH = 16739; // 6 +static const uint64_t SH_FLD_PREFETCH_CHANNEL_CNT = 16740; // 1 +static const uint64_t SH_FLD_PREFETCH_CHANNEL_CNT_LEN = 16741; // 1 +static const uint64_t SH_FLD_PREFETCH_DISABLE = 16742; // 6 +static const uint64_t SH_FLD_PREFETCH_DISTANCE = 16743; // 6 +static const uint64_t SH_FLD_PREFETCH_DISTANCE_LEN = 16744; // 6 +static const uint64_t SH_FLD_PREFETCH_LIMIT = 16745; // 8 +static const uint64_t SH_FLD_PREFETCH_LIMIT_LEN = 16746; // 8 +static const uint64_t SH_FLD_PREFETCH_RESET = 16747; // 24 +static const uint64_t SH_FLD_PREFEVOD = 16748; // 1 +static const uint64_t SH_FLD_PREF_DEPTH = 16749; // 1 +static const uint64_t SH_FLD_PREF_DEPTH_LEN = 16750; // 1 +static const uint64_t SH_FLD_PREF_SRC = 16751; // 96 +static const uint64_t SH_FLD_PREF_THRSH0 = 16752; // 1 +static const uint64_t SH_FLD_PREF_THRSH0_LEN = 16753; // 1 +static const uint64_t SH_FLD_PREF_THRSH1 = 16754; // 1 +static const uint64_t SH_FLD_PREF_THRSH1_LEN = 16755; // 1 +static const uint64_t SH_FLD_PREF_THRSH2 = 16756; // 1 +static const uint64_t SH_FLD_PREF_THRSH2_LEN = 16757; // 1 +static const uint64_t SH_FLD_PREF_THRSH3 = 16758; // 1 +static const uint64_t SH_FLD_PREF_THRSH3_LEN = 16759; // 1 +static const uint64_t SH_FLD_PREF_TIMEOUT = 16760; // 1 +static const uint64_t SH_FLD_PREF_TIMEOUT_LEN = 16761; // 1 +static const uint64_t SH_FLD_PREF_TRK_MODE = 16762; // 96 +static const uint64_t SH_FLD_PREF_TRK_MODE_LEN = 16763; // 96 +static const uint64_t SH_FLD_PRESCALAR_SEL0 = 16764; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL0_LEN = 16765; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL1 = 16766; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL1_LEN = 16767; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL2 = 16768; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL2_LEN = 16769; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL3 = 16770; // 2 +static const uint64_t SH_FLD_PRESCALAR_SEL3_LEN = 16771; // 2 +static const uint64_t SH_FLD_PRESCALER_SEL = 16772; // 1 +static const uint64_t SH_FLD_PRESCALER_SEL_LEN = 16773; // 1 +static const uint64_t SH_FLD_PRESCALE_C0 = 16774; // 9 +static const uint64_t SH_FLD_PRESCALE_C0_LEN = 16775; // 9 +static const uint64_t SH_FLD_PRESCALE_C1 = 16776; // 9 +static const uint64_t SH_FLD_PRESCALE_C1_LEN = 16777; // 9 +static const uint64_t SH_FLD_PRESCALE_C2 = 16778; // 9 +static const uint64_t SH_FLD_PRESCALE_C2_LEN = 16779; // 9 +static const uint64_t SH_FLD_PRESCALE_C3 = 16780; // 9 +static const uint64_t SH_FLD_PRESCALE_C3_LEN = 16781; // 9 +static const uint64_t SH_FLD_PRESP_RTY_OTHER = 16782; // 2 +static const uint64_t SH_FLD_PREVENTED_SCAN_COLLISION_ERR = 16783; // 43 +static const uint64_t SH_FLD_PREVENT_MTP_AT_DEM_IN_PIPE = 16784; // 1 +static const uint64_t SH_FLD_PRGM_ADDR = 16785; // 1 +static const uint64_t SH_FLD_PRGM_ADDR_LEN = 16786; // 1 +static const uint64_t SH_FLD_PRGSM_BUSY = 16787; // 24 +static const uint64_t SH_FLD_PRGSM_BUSY_ON_THIS = 16788; // 24 +static const uint64_t SH_FLD_PRG_BIT_LOCATION = 16789; // 1 +static const uint64_t SH_FLD_PRG_BIT_LOCATION_LEN = 16790; // 1 +static const uint64_t SH_FLD_PRI = 16791; // 8 +static const uint64_t SH_FLD_PRIMARY_ADDRESS = 16792; // 43 +static const uint64_t SH_FLD_PRIMARY_ADDRESS_LEN = 16793; // 43 +static const uint64_t SH_FLD_PRIORITY = 16794; // 18 +static const uint64_t SH_FLD_PRIORITY_ENABLE = 16795; // 6 +static const uint64_t SH_FLD_PRIORITY_LEN = 16796; // 6 +static const uint64_t SH_FLD_PRIORITY_LIMIT_0_3 = 16797; // 1 +static const uint64_t SH_FLD_PRIORITY_LIMIT_0_3_LEN = 16798; // 1 +static const uint64_t SH_FLD_PRIORITY_LPID = 16799; // 6 +static const uint64_t SH_FLD_PRIORITY_LPID_LEN = 16800; // 6 +static const uint64_t SH_FLD_PRIORITY_PID = 16801; // 6 +static const uint64_t SH_FLD_PRIORITY_PID_LEN = 16802; // 6 +static const uint64_t SH_FLD_PRIORITY_PRIMAX = 16803; // 3 +static const uint64_t SH_FLD_PRIORITY_PRIMAX_LEN = 16804; // 3 +static const uint64_t SH_FLD_PRIORITY_QUEUED = 16805; // 6 +static const uint64_t SH_FLD_PRIORITY_QUEUED_LEN = 16806; // 6 +static const uint64_t SH_FLD_PRIORITY_READ_OFFSET = 16807; // 6 +static const uint64_t SH_FLD_PRIORITY_READ_OFFSET_LEN = 16808; // 6 +static const uint64_t SH_FLD_PRIORITY_SIZE = 16809; // 6 +static const uint64_t SH_FLD_PRIORITY_SIZE_LEN = 16810; // 6 +static const uint64_t SH_FLD_PRIORITY_TID = 16811; // 6 +static const uint64_t SH_FLD_PRIORITY_TID_LEN = 16812; // 6 +static const uint64_t SH_FLD_PRIV = 16813; // 192 +static const uint64_t SH_FLD_PRIV_LEN = 16814; // 192 +static const uint64_t SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE = 16815; // 1 +static const uint64_t SH_FLD_PRI_LEN = 16816; // 8 +static const uint64_t SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE = 16817; // 1 +static const uint64_t SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE = 16818; // 1 +static const uint64_t SH_FLD_PRI_M_PATH_SELECT = 16819; // 2 +static const uint64_t SH_FLD_PRI_M_S_DRAWER_SELECT = 16820; // 2 +static const uint64_t SH_FLD_PRI_M_S_SELECT = 16821; // 2 +static const uint64_t SH_FLD_PRI_SEC_SELECT = 16822; // 1 +static const uint64_t SH_FLD_PRI_SEC_SELECT_LEN = 16823; // 1 +static const uint64_t SH_FLD_PRI_SELECT = 16824; // 1 +static const uint64_t SH_FLD_PRI_STATE_MACHINE_RESET = 16825; // 6 +static const uint64_t SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE = 16826; // 1 +static const uint64_t SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE = 16827; // 1 +static const uint64_t SH_FLD_PRI_S_PATH_SELECT = 16828; // 1 +static const uint64_t SH_FLD_PRI_V = 16829; // 8 +static const uint64_t SH_FLD_PROBE_0_TOGGLE_ENABLE = 16830; // 1 +static const uint64_t SH_FLD_PROBE_1_TOGGLE_ENABLE = 16831; // 1 +static const uint64_t SH_FLD_PROBE_2_TOGGLE_ENABLE = 16832; // 1 +static const uint64_t SH_FLD_PROBE_3_TOGGLE_ENABLE = 16833; // 1 +static const uint64_t SH_FLD_PROC_RCVY_AGAIN = 16834; // 96 +static const uint64_t SH_FLD_PROC_RCVY_DONE = 16835; // 96 +static const uint64_t SH_FLD_PROGRAM_ENABLE = 16836; // 1 +static const uint64_t SH_FLD_PROGRESS_ERROR = 16837; // 1 +static const uint64_t SH_FLD_PROG_REQ_DELAY = 16838; // 1 +static const uint64_t SH_FLD_PROG_REQ_DELAY_LEN = 16839; // 1 +static const uint64_t SH_FLD_PROTECTION_CHECK = 16840; // 1 +static const uint64_t SH_FLD_PROTOCOL_CHECKSTOP = 16841; // 2 +static const uint64_t SH_FLD_PROTOCOL_ERROR = 16842; // 45 +static const uint64_t SH_FLD_PROT_EX_SPARE0 = 16843; // 1 +static const uint64_t SH_FLD_PROT_EX_SPARE1 = 16844; // 1 +static const uint64_t SH_FLD_PROT_TP_SPARE0 = 16845; // 1 +static const uint64_t SH_FLD_PROT_TP_SPARE1 = 16846; // 1 +static const uint64_t SH_FLD_PROT_TP_SPARE2 = 16847; // 1 +static const uint64_t SH_FLD_PRPG_A_VAL = 16848; // 43 +static const uint64_t SH_FLD_PRPG_A_VAL_LEN = 16849; // 43 +static const uint64_t SH_FLD_PRPG_B_VAL = 16850; // 43 +static const uint64_t SH_FLD_PRPG_B_VAL_LEN = 16851; // 43 +static const uint64_t SH_FLD_PRPG_MODE = 16852; // 43 +static const uint64_t SH_FLD_PRPG_VALUE = 16853; // 43 +static const uint64_t SH_FLD_PRPG_VALUE_LEN = 16854; // 43 +static const uint64_t SH_FLD_PRPG_WEIGHTING = 16855; // 43 +static const uint64_t SH_FLD_PRPG_WEIGHTING_LEN = 16856; // 43 +static const uint64_t SH_FLD_PRS = 16857; // 8 +static const uint64_t SH_FLD_PRS0_ADDRESS_PTY = 16858; // 2 +static const uint64_t SH_FLD_PRS0_ATAG_PTY = 16859; // 2 +static const uint64_t SH_FLD_PRS0_CC0_CREDITERR = 16860; // 2 +static const uint64_t SH_FLD_PRS0_CC1_CREDITERR = 16861; // 2 +static const uint64_t SH_FLD_PRS0_CC2_CREDITERR = 16862; // 2 +static const uint64_t SH_FLD_PRS0_CC3_CREDITERR = 16863; // 2 +static const uint64_t SH_FLD_PRS0_CONTROL_ERROR = 16864; // 2 +static const uint64_t SH_FLD_PRS0_PR0_CREDITERR = 16865; // 2 +static const uint64_t SH_FLD_PRS0_PR1_CREDITERR = 16866; // 2 +static const uint64_t SH_FLD_PRS0_RTAG_PTY = 16867; // 2 +static const uint64_t SH_FLD_PRS0_TTAG_PTY = 16868; // 2 +static const uint64_t SH_FLD_PRS0_VC0_CREDITERR = 16869; // 2 +static const uint64_t SH_FLD_PRS0_VC1_CREDITERR = 16870; // 2 +static const uint64_t SH_FLD_PRS1_ADDRESS_PTY = 16871; // 2 +static const uint64_t SH_FLD_PRS1_ATAG_PTY = 16872; // 2 +static const uint64_t SH_FLD_PRS1_CC0_CREDITERR = 16873; // 2 +static const uint64_t SH_FLD_PRS1_CC1_CREDITERR = 16874; // 2 +static const uint64_t SH_FLD_PRS1_CC2_CREDITERR = 16875; // 2 +static const uint64_t SH_FLD_PRS1_CC3_CREDITERR = 16876; // 2 +static const uint64_t SH_FLD_PRS1_CONTROL_ERROR = 16877; // 2 +static const uint64_t SH_FLD_PRS1_PR0_CREDITERR = 16878; // 2 +static const uint64_t SH_FLD_PRS1_PR1_CREDITERR = 16879; // 2 +static const uint64_t SH_FLD_PRS1_RTAG_PTY = 16880; // 2 +static const uint64_t SH_FLD_PRS1_TTAG_PTY = 16881; // 2 +static const uint64_t SH_FLD_PRS1_VC0_CREDITERR = 16882; // 2 +static const uint64_t SH_FLD_PRS1_VC1_CREDITERR = 16883; // 2 +static const uint64_t SH_FLD_PRS2_ADDRESS_PTY = 16884; // 2 +static const uint64_t SH_FLD_PRS2_ATAG_PTY = 16885; // 2 +static const uint64_t SH_FLD_PRS2_CC0_CREDITERR = 16886; // 2 +static const uint64_t SH_FLD_PRS2_CC1_CREDITERR = 16887; // 2 +static const uint64_t SH_FLD_PRS2_CC2_CREDITERR = 16888; // 2 +static const uint64_t SH_FLD_PRS2_CC3_CREDITERR = 16889; // 2 +static const uint64_t SH_FLD_PRS2_CONTROL_ERROR = 16890; // 2 +static const uint64_t SH_FLD_PRS2_PR0_CREDITERR = 16891; // 2 +static const uint64_t SH_FLD_PRS2_PR1_CREDITERR = 16892; // 2 +static const uint64_t SH_FLD_PRS2_RTAG_PTY = 16893; // 2 +static const uint64_t SH_FLD_PRS2_TTAG_PTY = 16894; // 2 +static const uint64_t SH_FLD_PRS2_VC0_CREDITERR = 16895; // 2 +static const uint64_t SH_FLD_PRS2_VC1_CREDITERR = 16896; // 2 +static const uint64_t SH_FLD_PRS3_ADDRESS_PTY = 16897; // 2 +static const uint64_t SH_FLD_PRS3_ATAG_PTY = 16898; // 2 +static const uint64_t SH_FLD_PRS3_CC0_CREDITERR = 16899; // 2 +static const uint64_t SH_FLD_PRS3_CC1_CREDITERR = 16900; // 2 +static const uint64_t SH_FLD_PRS3_CC2_CREDITERR = 16901; // 2 +static const uint64_t SH_FLD_PRS3_CC3_CREDITERR = 16902; // 2 +static const uint64_t SH_FLD_PRS3_CONTROL_ERROR = 16903; // 2 +static const uint64_t SH_FLD_PRS3_PR0_CREDITERR = 16904; // 2 +static const uint64_t SH_FLD_PRS3_PR1_CREDITERR = 16905; // 2 +static const uint64_t SH_FLD_PRS3_RTAG_PTY = 16906; // 2 +static const uint64_t SH_FLD_PRS3_TTAG_PTY = 16907; // 2 +static const uint64_t SH_FLD_PRS3_VC0_CREDITERR = 16908; // 2 +static const uint64_t SH_FLD_PRS3_VC1_CREDITERR = 16909; // 2 +static const uint64_t SH_FLD_PRS4_ADDRESS_PTY = 16910; // 2 +static const uint64_t SH_FLD_PRS4_ATAG_PTY = 16911; // 2 +static const uint64_t SH_FLD_PRS4_CC0_CREDITERR = 16912; // 2 +static const uint64_t SH_FLD_PRS4_CC1_CREDITERR = 16913; // 2 +static const uint64_t SH_FLD_PRS4_CC2_CREDITERR = 16914; // 2 +static const uint64_t SH_FLD_PRS4_CC3_CREDITERR = 16915; // 2 +static const uint64_t SH_FLD_PRS4_CONTROL_ERROR = 16916; // 2 +static const uint64_t SH_FLD_PRS4_PR0_CREDITERR = 16917; // 2 +static const uint64_t SH_FLD_PRS4_PR1_CREDITERR = 16918; // 2 +static const uint64_t SH_FLD_PRS4_RTAG_PTY = 16919; // 2 +static const uint64_t SH_FLD_PRS4_TTAG_PTY = 16920; // 2 +static const uint64_t SH_FLD_PRS4_VC0_CREDITERR = 16921; // 2 +static const uint64_t SH_FLD_PRS4_VC1_CREDITERR = 16922; // 2 +static const uint64_t SH_FLD_PRS5_ADDRESS_PTY = 16923; // 2 +static const uint64_t SH_FLD_PRS5_ATAG_PTY = 16924; // 2 +static const uint64_t SH_FLD_PRS5_CC0_CREDITERR = 16925; // 2 +static const uint64_t SH_FLD_PRS5_CC1_CREDITERR = 16926; // 2 +static const uint64_t SH_FLD_PRS5_CC2_CREDITERR = 16927; // 2 +static const uint64_t SH_FLD_PRS5_CC3_CREDITERR = 16928; // 2 +static const uint64_t SH_FLD_PRS5_CONTROL_ERROR = 16929; // 2 +static const uint64_t SH_FLD_PRS5_PR0_CREDITERR = 16930; // 2 +static const uint64_t SH_FLD_PRS5_PR1_CREDITERR = 16931; // 2 +static const uint64_t SH_FLD_PRS5_RTAG_PTY = 16932; // 2 +static const uint64_t SH_FLD_PRS5_TTAG_PTY = 16933; // 2 +static const uint64_t SH_FLD_PRS5_VC0_CREDITERR = 16934; // 2 +static const uint64_t SH_FLD_PRS5_VC1_CREDITERR = 16935; // 2 +static const uint64_t SH_FLD_PRS6_ADDRESS_PTY = 16936; // 1 +static const uint64_t SH_FLD_PRS6_ATAG_PTY = 16937; // 1 +static const uint64_t SH_FLD_PRS6_CC0_CREDITERR = 16938; // 1 +static const uint64_t SH_FLD_PRS6_CC1_CREDITERR = 16939; // 1 +static const uint64_t SH_FLD_PRS6_CC2_CREDITERR = 16940; // 1 +static const uint64_t SH_FLD_PRS6_CC3_CREDITERR = 16941; // 1 +static const uint64_t SH_FLD_PRS6_CONTROL_ERROR = 16942; // 1 +static const uint64_t SH_FLD_PRS6_PR0_CREDITERR = 16943; // 1 +static const uint64_t SH_FLD_PRS6_PR1_CREDITERR = 16944; // 1 +static const uint64_t SH_FLD_PRS6_RTAG_PTY = 16945; // 1 +static const uint64_t SH_FLD_PRS6_TTAG_PTY = 16946; // 1 +static const uint64_t SH_FLD_PRS6_VC0_CREDITERR = 16947; // 1 +static const uint64_t SH_FLD_PRS6_VC1_CREDITERR = 16948; // 1 +static const uint64_t SH_FLD_PRS7_ADDRESS_PTY = 16949; // 1 +static const uint64_t SH_FLD_PRS7_ATAG_PTY = 16950; // 1 +static const uint64_t SH_FLD_PRS7_CC0_CREDITERR = 16951; // 1 +static const uint64_t SH_FLD_PRS7_CC1_CREDITERR = 16952; // 1 +static const uint64_t SH_FLD_PRS7_CC2_CREDITERR = 16953; // 1 +static const uint64_t SH_FLD_PRS7_CC3_CREDITERR = 16954; // 1 +static const uint64_t SH_FLD_PRS7_CONTROL_ERROR = 16955; // 1 +static const uint64_t SH_FLD_PRS7_PR0_CREDITERR = 16956; // 1 +static const uint64_t SH_FLD_PRS7_PR1_CREDITERR = 16957; // 1 +static const uint64_t SH_FLD_PRS7_RTAG_PTY = 16958; // 1 +static const uint64_t SH_FLD_PRS7_TTAG_PTY = 16959; // 1 +static const uint64_t SH_FLD_PRS7_VC0_CREDITERR = 16960; // 1 +static const uint64_t SH_FLD_PRS7_VC1_CREDITERR = 16961; // 1 +static const uint64_t SH_FLD_PRST = 16962; // 48 +static const uint64_t SH_FLD_PRV_BUS0_STG2_SEL = 16963; // 1 +static const uint64_t SH_FLD_PRV_BUS1_STG2_SEL = 16964; // 1 +static const uint64_t SH_FLD_PR_BUMP_SL_1UI = 16965; // 120 +static const uint64_t SH_FLD_PR_BUMP_SR_1UI = 16966; // 120 +static const uint64_t SH_FLD_PR_BUMP_TO_CENTER = 16967; // 72 +static const uint64_t SH_FLD_PR_BUMP_TO_EDGE_A = 16968; // 120 +static const uint64_t SH_FLD_PR_BUMP_TO_EDGE_B = 16969; // 48 +static const uint64_t SH_FLD_PR_COARSE_MODE_EN = 16970; // 48 +static const uint64_t SH_FLD_PR_COARSE_MODE_TIMER_SEL = 16971; // 48 +static const uint64_t SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN = 16972; // 48 +static const uint64_t SH_FLD_PR_DATA_A_OFFSET = 16973; // 120 +static const uint64_t SH_FLD_PR_DATA_A_OFFSET_LEN = 16974; // 120 +static const uint64_t SH_FLD_PR_DATA_B_OFFSET = 16975; // 48 +static const uint64_t SH_FLD_PR_DATA_B_OFFSET_LEN = 16976; // 48 +static const uint64_t SH_FLD_PR_DDC_A = 16977; // 120 +static const uint64_t SH_FLD_PR_DDC_B = 16978; // 48 +static const uint64_t SH_FLD_PR_EDGE_TRACK_CNTL = 16979; // 120 +static const uint64_t SH_FLD_PR_EDGE_TRACK_CNTL_LEN = 16980; // 120 +static const uint64_t SH_FLD_PR_FW_INERTIA_AMT = 16981; // 48 +static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_COARSE = 16982; // 48 +static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN = 16983; // 48 +static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_LEN = 16984; // 48 +static const uint64_t SH_FLD_PR_FW_OFF = 16985; // 48 +static const uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE = 16986; // 120 +static const uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN = 16987; // 120 +static const uint64_t SH_FLD_PR_INVALID_LOCK_COARSE_EN = 16988; // 48 +static const uint64_t SH_FLD_PR_INVALID_LOCK_FILTER_EN = 16989; // 120 +static const uint64_t SH_FLD_PR_LOCK_DONE = 16990; // 120 +static const uint64_t SH_FLD_PR_PHASE_STEP = 16991; // 120 +static const uint64_t SH_FLD_PR_PHASE_STEP_COARSE = 16992; // 48 +static const uint64_t SH_FLD_PR_PHASE_STEP_COARSE_LEN = 16993; // 48 +static const uint64_t SH_FLD_PR_PHASE_STEP_LEN = 16994; // 120 +static const uint64_t SH_FLD_PR_RESET = 16995; // 48 +static const uint64_t SH_FLD_PR_TRACE_DDC_SM = 16996; // 120 +static const uint64_t SH_FLD_PR_TRACE_DDC_SM_LEN = 16997; // 120 +static const uint64_t SH_FLD_PR_TRACE_DDC_STOP = 16998; // 120 +static const uint64_t SH_FLD_PR_TRACE_WOBBLE_SM = 16999; // 120 +static const uint64_t SH_FLD_PR_TRACE_WOBBLE_SM_LEN = 17000; // 120 +static const uint64_t SH_FLD_PR_TRACE_WOBBLE_STOP = 17001; // 120 +static const uint64_t SH_FLD_PR_USE_DFE_CLOCK_A = 17002; // 120 +static const uint64_t SH_FLD_PR_USE_DFE_CLOCK_B = 17003; // 48 +static const uint64_t SH_FLD_PR_WOBBLE_A = 17004; // 120 +static const uint64_t SH_FLD_PR_WOBBLE_B = 17005; // 48 +static const uint64_t SH_FLD_PR_WOBBLE_EDGE = 17006; // 48 +static const uint64_t SH_FLD_PSAVE_ANA_REQ_DIS = 17007; // 48 +static const uint64_t SH_FLD_PSAVE_DIG_REQ_DIS = 17008; // 48 +static const uint64_t SH_FLD_PSAVE_FENCE_ENABLE = 17009; // 4 +static const uint64_t SH_FLD_PSAVE_INVALID_STATE = 17010; // 6 +static const uint64_t SH_FLD_PSAVE_MODE_DISABLE = 17011; // 140 +static const uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL = 17012; // 4 +static const uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL_LEN = 17013; // 4 +static const uint64_t SH_FLD_PSAVE_REQ_DIS = 17014; // 48 +static const uint64_t SH_FLD_PSAVE_RESYNC_DISABLE = 17015; // 72 +static const uint64_t SH_FLD_PSAVE_TIMER_WAKEUP_MODE = 17016; // 4 +static const uint64_t SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE = 17017; // 8 +static const uint64_t SH_FLD_PSCOM_PURGE = 17018; // 24 +static const uint64_t SH_FLD_PSCR_OVERRIDE_EN = 17019; // 12 +static const uint64_t SH_FLD_PSEG_MAIN_EN = 17020; // 6 +static const uint64_t SH_FLD_PSEG_MAIN_EN_LEN = 17021; // 6 +static const uint64_t SH_FLD_PSEG_MARGINPD_EN = 17022; // 6 +static const uint64_t SH_FLD_PSEG_MARGINPD_EN_LEN = 17023; // 6 +static const uint64_t SH_FLD_PSEG_MARGINPU_EN = 17024; // 6 +static const uint64_t SH_FLD_PSEG_MARGINPU_EN_LEN = 17025; // 6 +static const uint64_t SH_FLD_PSEG_POST_EN = 17026; // 2 +static const uint64_t SH_FLD_PSEG_POST_EN_LEN = 17027; // 2 +static const uint64_t SH_FLD_PSEG_POST_SEL = 17028; // 2 +static const uint64_t SH_FLD_PSEG_POST_SEL_LEN = 17029; // 2 +static const uint64_t SH_FLD_PSEG_PRE_EN = 17030; // 6 +static const uint64_t SH_FLD_PSEG_PRE_EN_LEN = 17031; // 6 +static const uint64_t SH_FLD_PSEG_PRE_SEL = 17032; // 6 +static const uint64_t SH_FLD_PSEG_PRE_SEL_LEN = 17033; // 6 +static const uint64_t SH_FLD_PSIFSP_ACK_TIMEOUT = 17034; // 1 +static const uint64_t SH_FLD_PSIFSP_DMAR_OUTSTANDING = 17035; // 1 +static const uint64_t SH_FLD_PSIFSP_DMA_ADDR_ERR = 17036; // 1 +static const uint64_t SH_FLD_PSIFSP_DMA_ERR = 17037; // 1 +static const uint64_t SH_FLD_PSIFSP_INT_BUSY = 17038; // 1 +static const uint64_t SH_FLD_PSIFSP_INV_OP = 17039; // 1 +static const uint64_t SH_FLD_PSIFSP_LOAD_OUTSTANDING = 17040; // 1 +static const uint64_t SH_FLD_PSIFSP_MMIO_ADDR_ERR = 17041; // 1 +static const uint64_t SH_FLD_PSIFSP_MMIO_LENGTH_ERR = 17042; // 1 +static const uint64_t SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT = 17043; // 1 +static const uint64_t SH_FLD_PSIFSP_MMIO_TYPE_ERR = 17044; // 1 +static const uint64_t SH_FLD_PSIFSP_PAGE_FAULT = 17045; // 1 +static const uint64_t SH_FLD_PSIFSP_PERR = 17046; // 1 +static const uint64_t SH_FLD_PSIFSP_TCE_EXTENT_ERR = 17047; // 1 +static const uint64_t SH_FLD_PSIHB2FSP_INJ_CONST = 17048; // 1 +static const uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS = 17049; // 1 +static const uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN = 17050; // 1 +static const uint64_t SH_FLD_PSIHB2FSP_INJ_ONCE = 17051; // 1 +static const uint64_t SH_FLD_PSIHB2PB_INJ_CONST = 17052; // 1 +static const uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS = 17053; // 1 +static const uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN = 17054; // 1 +static const uint64_t SH_FLD_PSIHB2PB_INJ_ONCE = 17055; // 1 +static const uint64_t SH_FLD_PSIHBC_RESET = 17056; // 1 +static const uint64_t SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR = 17057; // 1 +static const uint64_t SH_FLD_PSIRFACC_RADDR_PCK = 17058; // 1 +static const uint64_t SH_FLD_PSIRFACC_RCTRL_PCK = 17059; // 1 +static const uint64_t SH_FLD_PSIRFACC_RDL_FSM_PCK = 17060; // 1 +static const uint64_t SH_FLD_PSIRFACC_RFSM_PCK = 17061; // 1 +static const uint64_t SH_FLD_PSIRFACC_RLINK_STATE_LT_02 = 17062; // 1 +static const uint64_t SH_FLD_PSIRFACC_RXSC_PCK = 17063; // 1 +static const uint64_t SH_FLD_PSIRFACC_TADDR_PCK = 17064; // 1 +static const uint64_t SH_FLD_PSIRFACC_TCTRL_PCK = 17065; // 1 +static const uint64_t SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK = 17066; // 1 +static const uint64_t SH_FLD_PSIRFACC_TDL_FSM_PCK = 17067; // 1 +static const uint64_t SH_FLD_PSIRFACC_TDL_RETRY_ERR = 17068; // 1 +static const uint64_t SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK = 17069; // 1 +static const uint64_t SH_FLD_PSIRFACC_TFSM_PCK = 17070; // 1 +static const uint64_t SH_FLD_PSIRFACC_TXSC_PCK = 17071; // 1 +static const uint64_t SH_FLD_PSIRXBFF_DATAO_PCK = 17072; // 1 +static const uint64_t SH_FLD_PSIRXBFF_DATA_PCK = 17073; // 1 +static const uint64_t SH_FLD_PSIRXBFF_RFC_PCK = 17074; // 1 +static const uint64_t SH_FLD_PSIRXEI_SHIFT_PCK = 17075; // 1 +static const uint64_t SH_FLD_PSIRXEI_TRANSMIT_PCK = 17076; // 1 +static const uint64_t SH_FLD_PSIRXINS_DATA_PCK = 17077; // 1 +static const uint64_t SH_FLD_PSIRXINS_OVERRUN = 17078; // 1 +static const uint64_t SH_FLD_PSIRXINS_RFGSHIFT_PCK = 17079; // 1 +static const uint64_t SH_FLD_PSIRXINS_RZRTMP_PCK = 17080; // 1 +static const uint64_t SH_FLD_PSIRXLC_CE_RF = 17081; // 1 +static const uint64_t SH_FLD_PSIRXLC_DATA_BUFF_PCK = 17082; // 1 +static const uint64_t SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N = 17083; // 1 +static const uint64_t SH_FLD_PSIRXLC_DATA_PCK = 17084; // 1 +static const uint64_t SH_FLD_PSIRXLC_FSM_PCK = 17085; // 1 +static const uint64_t SH_FLD_PSIRXLC_RADDR_PCK = 17086; // 1 +static const uint64_t SH_FLD_PSIRXLC_RCTRL_PCK = 17087; // 1 +static const uint64_t SH_FLD_PSIRXLC_UE_RF = 17088; // 1 +static const uint64_t SH_FLD_PSITXBFF_DATA_PCK = 17089; // 1 +static const uint64_t SH_FLD_PSITXBFF_TDO_PCK = 17090; // 1 +static const uint64_t SH_FLD_PSITXBFF_TFC_PCK = 17091; // 1 +static const uint64_t SH_FLD_PSITXEI_SHIFT_PCK = 17092; // 1 +static const uint64_t SH_FLD_PSITXEI_TRANSMIT_PCK = 17093; // 1 +static const uint64_t SH_FLD_PSITXINS_DATA_PCK = 17094; // 1 +static const uint64_t SH_FLD_PSITXINS_PARITY = 17095; // 1 +static const uint64_t SH_FLD_PSITXINS_TZRTMP_PCK = 17096; // 1 +static const uint64_t SH_FLD_PSITXINS_UNDERRUN = 17097; // 1 +static const uint64_t SH_FLD_PSITXLC_CE_GX_2N = 17098; // 1 +static const uint64_t SH_FLD_PSITXLC_CE_RF = 17099; // 1 +static const uint64_t SH_FLD_PSITXLC_DATA_BUFF_PCK = 17100; // 1 +static const uint64_t SH_FLD_PSITXLC_DATA_GXST2_PCK_2N = 17101; // 1 +static const uint64_t SH_FLD_PSITXLC_DATA_GXST3_PCK_2N = 17102; // 1 +static const uint64_t SH_FLD_PSITXLC_FSM_PCK = 17103; // 1 +static const uint64_t SH_FLD_PSITXLC_TADDR_PCK = 17104; // 1 +static const uint64_t SH_FLD_PSITXLC_TCTRL_PCK = 17105; // 1 +static const uint64_t SH_FLD_PSITXLC_TDO_PCK = 17106; // 1 +static const uint64_t SH_FLD_PSITXLC_UE_GX_2N = 17107; // 1 +static const uint64_t SH_FLD_PSITXLC_UE_RF = 17108; // 1 +static const uint64_t SH_FLD_PSI_ALERT1 = 17109; // 1 +static const uint64_t SH_FLD_PSI_ALERT2 = 17110; // 1 +static const uint64_t SH_FLD_PSI_INTERRUPT_HIGH = 17111; // 1 +static const uint64_t SH_FLD_PSI_INTERRUPT_PENDING = 17112; // 1 +static const uint64_t SH_FLD_PSI_LINK_ENABLE = 17113; // 1 +static const uint64_t SH_FLD_PSI_LINK_INACTIVE_TRANS = 17114; // 1 +static const uint64_t SH_FLD_PSI_RESERVED0 = 17115; // 2 +static const uint64_t SH_FLD_PSI_RESERVED1 = 17116; // 2 +static const uint64_t SH_FLD_PSI_RESERVED2 = 17117; // 2 +static const uint64_t SH_FLD_PSI_RESERVED3 = 17118; // 2 +static const uint64_t SH_FLD_PSI_RESERVED4 = 17119; // 2 +static const uint64_t SH_FLD_PSI_UE = 17120; // 1 +static const uint64_t SH_FLD_PSI_XMIT_ERROR = 17121; // 1 +static const uint64_t SH_FLD_PSLL = 17122; // 96 +static const uint64_t SH_FLD_PSLL_LEN = 17123; // 96 +static const uint64_t SH_FLD_PSL_CMD_SUE = 17124; // 4 +static const uint64_t SH_FLD_PSL_CMD_SUE_ERRHOLD = 17125; // 2 +static const uint64_t SH_FLD_PSL_CMD_UE = 17126; // 4 +static const uint64_t SH_FLD_PSL_CMD_UE_ERRHOLD = 17127; // 2 +static const uint64_t SH_FLD_PSL_CREDIT_TIMEOUT_ERR = 17128; // 4 +static const uint64_t SH_FLD_PSPB_CURRENT_VALUE = 17129; // 96 +static const uint64_t SH_FLD_PSPB_CURRENT_VALUE_LEN = 17130; // 96 +static const uint64_t SH_FLD_PSSBRIDGE_ONGOING = 17131; // 1 +static const uint64_t SH_FLD_PSSCR_T0_PLS = 17132; // 24 +static const uint64_t SH_FLD_PSSCR_T0_PLS_LEN = 17133; // 24 +static const uint64_t SH_FLD_PSSCR_T0_SRR1 = 17134; // 24 +static const uint64_t SH_FLD_PSSCR_T0_SRR1_LEN = 17135; // 24 +static const uint64_t SH_FLD_PSSCR_T1_PLS = 17136; // 24 +static const uint64_t SH_FLD_PSSCR_T1_PLS_LEN = 17137; // 24 +static const uint64_t SH_FLD_PSSCR_T1_SRR1 = 17138; // 24 +static const uint64_t SH_FLD_PSSCR_T1_SRR1_LEN = 17139; // 24 +static const uint64_t SH_FLD_PSSCR_T2_PLS = 17140; // 24 +static const uint64_t SH_FLD_PSSCR_T2_PLS_LEN = 17141; // 24 +static const uint64_t SH_FLD_PSSCR_T2_SRR1 = 17142; // 24 +static const uint64_t SH_FLD_PSSCR_T2_SRR1_LEN = 17143; // 24 +static const uint64_t SH_FLD_PSSCR_T3_PLS = 17144; // 24 +static const uint64_t SH_FLD_PSSCR_T3_PLS_LEN = 17145; // 24 +static const uint64_t SH_FLD_PSSCR_T3_SRR1 = 17146; // 24 +static const uint64_t SH_FLD_PSSCR_T3_SRR1_LEN = 17147; // 24 +static const uint64_t SH_FLD_PSS_HAM = 17148; // 3 +static const uint64_t SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK = 17149; // 1 +static const uint64_t SH_FLD_PSTATE_A_THRESHOLD = 17150; // 24 +static const uint64_t SH_FLD_PSTATE_A_THRESHOLD_LEN = 17151; // 24 +static const uint64_t SH_FLD_PSTATE_B_THRESHOLD = 17152; // 24 +static const uint64_t SH_FLD_PSTATE_B_THRESHOLD_LEN = 17153; // 24 +static const uint64_t SH_FLD_PSU_INTERRUPT_HIGH = 17154; // 1 +static const uint64_t SH_FLD_PSU_INTERRUPT_PENDING = 17155; // 1 +static const uint64_t SH_FLD_PS_SPARE1 = 17156; // 1 +static const uint64_t SH_FLD_PTAG_MAX_IN_USE = 17157; // 1 +static const uint64_t SH_FLD_PTAG_MAX_IN_USE_LEN = 17158; // 1 +static const uint64_t SH_FLD_PTCR = 17159; // 1 +static const uint64_t SH_FLD_PTCR_LEN = 17160; // 1 +static const uint64_t SH_FLD_PTID0_V = 17161; // 24 +static const uint64_t SH_FLD_PTID1_V = 17162; // 24 +static const uint64_t SH_FLD_PTID2_V = 17163; // 24 +static const uint64_t SH_FLD_PTID3_V = 17164; // 24 +static const uint64_t SH_FLD_PTID_RECONFIG_SM_HOLD_OUT = 17165; // 24 +static const uint64_t SH_FLD_PTSPARE6 = 17166; // 2 +static const uint64_t SH_FLD_PTSPARE7 = 17167; // 2 +static const uint64_t SH_FLD_PULL_EMPTY = 17168; // 4 +static const uint64_t SH_FLD_PULL_ENABLE = 17169; // 4 +static const uint64_t SH_FLD_PULL_FULL = 17170; // 4 +static const uint64_t SH_FLD_PULL_INTR_ACTION_0_1 = 17171; // 4 +static const uint64_t SH_FLD_PULL_INTR_ACTION_0_1_LEN = 17172; // 4 +static const uint64_t SH_FLD_PULL_LENGTH = 17173; // 4 +static const uint64_t SH_FLD_PULL_LENGTH_LEN = 17174; // 4 +static const uint64_t SH_FLD_PULL_READ_PTR = 17175; // 4 +static const uint64_t SH_FLD_PULL_READ_PTR_LEN = 17176; // 4 +static const uint64_t SH_FLD_PULL_READ_UNDERFLOW = 17177; // 4 +static const uint64_t SH_FLD_PULL_READ_UNDERFLOW_EN = 17178; // 4 +static const uint64_t SH_FLD_PULL_REGION = 17179; // 4 +static const uint64_t SH_FLD_PULL_REGION_LEN = 17180; // 4 +static const uint64_t SH_FLD_PULL_START = 17181; // 4 +static const uint64_t SH_FLD_PULL_START_LEN = 17182; // 4 +static const uint64_t SH_FLD_PULL_WRITE_OVERFLOW = 17183; // 4 +static const uint64_t SH_FLD_PULL_WRITE_PTR = 17184; // 4 +static const uint64_t SH_FLD_PULL_WRITE_PTR_LEN = 17185; // 4 +static const uint64_t SH_FLD_PULSE1_CNTR = 17186; // 1 +static const uint64_t SH_FLD_PULSE1_CNTR_LEN = 17187; // 1 +static const uint64_t SH_FLD_PULSE2_CNTR = 17188; // 1 +static const uint64_t SH_FLD_PULSE2_CNTR_LEN = 17189; // 1 +static const uint64_t SH_FLD_PULSE_DELAY = 17190; // 43 +static const uint64_t SH_FLD_PULSE_DELAY_LEN = 17191; // 43 +static const uint64_t SH_FLD_PULSE_DROOP_DATA = 17192; // 6 +static const uint64_t SH_FLD_PULSE_DROOP_DATA_LEN = 17193; // 6 +static const uint64_t SH_FLD_PULSE_DROOP_ENABLE = 17194; // 6 +static const uint64_t SH_FLD_PULSE_INPUT_SEL = 17195; // 43 +static const uint64_t SH_FLD_PULSE_OUT_DIS = 17196; // 43 +static const uint64_t SH_FLD_PUMP_MODE = 17197; // 1 +static const uint64_t SH_FLD_PUP_LITE_WAIT_SEL = 17198; // 4 +static const uint64_t SH_FLD_PUP_LITE_WAIT_SEL_LEN = 17199; // 4 +static const uint64_t SH_FLD_PURE_SBE_INTERRUPT_HIGH = 17200; // 1 +static const uint64_t SH_FLD_PURR_OVERFLOW_ERROR = 17201; // 96 +static const uint64_t SH_FLD_PURR_PARITY_ERROR = 17202; // 96 +static const uint64_t SH_FLD_PUSH_EMPTY = 17203; // 6 +static const uint64_t SH_FLD_PUSH_ENABLE = 17204; // 6 +static const uint64_t SH_FLD_PUSH_FULL = 17205; // 6 +static const uint64_t SH_FLD_PUSH_INTR_ACTION_0_1 = 17206; // 6 +static const uint64_t SH_FLD_PUSH_INTR_ACTION_0_1_LEN = 17207; // 6 +static const uint64_t SH_FLD_PUSH_LENGTH = 17208; // 6 +static const uint64_t SH_FLD_PUSH_LENGTH_LEN = 17209; // 6 +static const uint64_t SH_FLD_PUSH_READ_PTR = 17210; // 6 +static const uint64_t SH_FLD_PUSH_READ_PTR_LEN = 17211; // 6 +static const uint64_t SH_FLD_PUSH_READ_UNDERFLOW = 17212; // 4 +static const uint64_t SH_FLD_PUSH_REGION = 17213; // 4 +static const uint64_t SH_FLD_PUSH_REGION_LEN = 17214; // 4 +static const uint64_t SH_FLD_PUSH_START = 17215; // 6 +static const uint64_t SH_FLD_PUSH_START_LEN = 17216; // 6 +static const uint64_t SH_FLD_PUSH_WRITE_OVERFLOW = 17217; // 4 +static const uint64_t SH_FLD_PUSH_WRITE_OVERFLOW_EN = 17218; // 4 +static const uint64_t SH_FLD_PUSH_WRITE_PTR = 17219; // 6 +static const uint64_t SH_FLD_PUSH_WRITE_PTR_LEN = 17220; // 6 +static const uint64_t SH_FLD_PU_BIT_ENABLES = 17221; // 1 +static const uint64_t SH_FLD_PU_BIT_ENABLES_LEN = 17222; // 1 +static const uint64_t SH_FLD_PU_CNTL_UNUSED = 17223; // 1 +static const uint64_t SH_FLD_PU_CNTL_UNUSED_LEN = 17224; // 1 +static const uint64_t SH_FLD_PU_COUNTS = 17225; // 8 +static const uint64_t SH_FLD_PU_COUNTS_LEN = 17226; // 8 +static const uint64_t SH_FLD_PVALID = 17227; // 32 +static const uint64_t SH_FLD_PVREF_ERROR_EN = 17228; // 1 +static const uint64_t SH_FLD_PVREF_ERROR_EN_LEN = 17229; // 1 +static const uint64_t SH_FLD_PVREF_ERROR_FINE = 17230; // 1 +static const uint64_t SH_FLD_PVREF_ERROR_GROSS = 17231; // 1 +static const uint64_t SH_FLD_PVREF_FAIL = 17232; // 12 +static const uint64_t SH_FLD_PVTN = 17233; // 8 +static const uint64_t SH_FLD_PVTNB = 17234; // 16 +static const uint64_t SH_FLD_PVTNL = 17235; // 8 +static const uint64_t SH_FLD_PVTNL_ENC = 17236; // 1 +static const uint64_t SH_FLD_PVTNL_ENC_LEN = 17237; // 1 +static const uint64_t SH_FLD_PVTNL_LEN = 17238; // 8 +static const uint64_t SH_FLD_PVTN_LEN = 17239; // 8 +static const uint64_t SH_FLD_PVTPB = 17240; // 16 +static const uint64_t SH_FLD_PVTPL = 17241; // 16 +static const uint64_t SH_FLD_PVTPL_ENC = 17242; // 1 +static const uint64_t SH_FLD_PVTPL_ENC_LEN = 17243; // 1 +static const uint64_t SH_FLD_PVTPL_LEN = 17244; // 16 +static const uint64_t SH_FLD_PVT_OVERRIDE = 17245; // 8 +static const uint64_t SH_FLD_PWR0 = 17246; // 12 +static const uint64_t SH_FLD_PWR1 = 17247; // 12 +static const uint64_t SH_FLD_QPPM_ONGOING = 17248; // 24 +static const uint64_t SH_FLD_QPPM_RDATA = 17249; // 24 +static const uint64_t SH_FLD_QPPM_RDATA_LEN = 17250; // 24 +static const uint64_t SH_FLD_QPPM_REG = 17251; // 24 +static const uint64_t SH_FLD_QPPM_REG_LEN = 17252; // 24 +static const uint64_t SH_FLD_QPPM_RNW = 17253; // 24 +static const uint64_t SH_FLD_QPPM_STATUS = 17254; // 24 +static const uint64_t SH_FLD_QPPM_STATUS_LEN = 17255; // 24 +static const uint64_t SH_FLD_QPPM_WDATA = 17256; // 24 +static const uint64_t SH_FLD_QPPM_WDATA_LEN = 17257; // 24 +static const uint64_t SH_FLD_QUA = 17258; // 8 +static const uint64_t SH_FLD_QUAD_CHECKSTOP = 17259; // 12 +static const uint64_t SH_FLD_QUAD_CLK_SB_OVERRIDE = 17260; // 24 +static const uint64_t SH_FLD_QUAD_CLK_SW_OVERRIDE = 17261; // 24 +static const uint64_t SH_FLD_QUAD_ID = 17262; // 24 +static const uint64_t SH_FLD_QUAD_ID_LEN = 17263; // 24 +static const uint64_t SH_FLD_QUAD_SEL = 17264; // 4 +static const uint64_t SH_FLD_QUAD_SEL_LEN = 17265; // 4 +static const uint64_t SH_FLD_QUAD_STOPPED = 17266; // 1 +static const uint64_t SH_FLD_QUAD_STOPPED_LEN = 17267; // 1 +static const uint64_t SH_FLD_QUA_LEN = 17268; // 8 +static const uint64_t SH_FLD_QUA_V = 17269; // 8 +static const uint64_t SH_FLD_QUEUED_RD_EN = 17270; // 12 +static const uint64_t SH_FLD_QUEUED_WR_EN = 17271; // 12 +static const uint64_t SH_FLD_QUEUE_DISABLE = 17272; // 6 +static const uint64_t SH_FLD_QUEUE_NOT_EMPTY = 17273; // 6 +static const uint64_t SH_FLD_QUIESCE = 17274; // 1 +static const uint64_t SH_FLD_QUIESCED = 17275; // 1 +static const uint64_t SH_FLD_QUIESCE_ACHEIVED = 17276; // 1 +static const uint64_t SH_FLD_QUIESCE_AUTO_RESET = 17277; // 1 +static const uint64_t SH_FLD_QUIESCE_DONE = 17278; // 2 +static const uint64_t SH_FLD_QUIESCE_FAILED = 17279; // 1 +static const uint64_t SH_FLD_QUIESCE_PB = 17280; // 1 +static const uint64_t SH_FLD_QUIESCE_REQUEST = 17281; // 1 +static const uint64_t SH_FLD_R = 17282; // 8 +static const uint64_t SH_FLD_R0_COUNT = 17283; // 12 +static const uint64_t SH_FLD_R0_COUNT_LEN = 17284; // 12 +static const uint64_t SH_FLD_R15_BIT_MAP = 17285; // 8 +static const uint64_t SH_FLD_R15_BIT_MAP_LEN = 17286; // 8 +static const uint64_t SH_FLD_R16_BIT_MAP = 17287; // 8 +static const uint64_t SH_FLD_R16_BIT_MAP_LEN = 17288; // 8 +static const uint64_t SH_FLD_R17_BIT_MAP = 17289; // 8 +static const uint64_t SH_FLD_R17_BIT_MAP_LEN = 17290; // 8 +static const uint64_t SH_FLD_R1_COUNT = 17291; // 12 +static const uint64_t SH_FLD_R1_COUNT_LEN = 17292; // 12 +static const uint64_t SH_FLD_R2_COUNT = 17293; // 12 +static const uint64_t SH_FLD_R2_COUNT_LEN = 17294; // 12 +static const uint64_t SH_FLD_RADX = 17295; // 96 +static const uint64_t SH_FLD_RAM_COMPLETION = 17296; // 24 +static const uint64_t SH_FLD_RAM_CONTROL_ACCESS_DURING_RECOV = 17297; // 24 +static const uint64_t SH_FLD_RAM_EXCEPTION = 17298; // 24 +static const uint64_t SH_FLD_RAM_THREAD_ACTIVE = 17299; // 24 +static const uint64_t SH_FLD_RAM_THREAD_ACTIVE_LEN = 17300; // 24 +static const uint64_t SH_FLD_RAM_VTID = 17301; // 24 +static const uint64_t SH_FLD_RAM_VTID_LEN = 17302; // 24 +static const uint64_t SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN = 17303; // 2 +static const uint64_t SH_FLD_RAND_ERROR_RATE = 17304; // 5 +static const uint64_t SH_FLD_RAND_ERROR_RATE_LEN = 17305; // 5 +static const uint64_t SH_FLD_RAND_EVENT = 17306; // 1 +static const uint64_t SH_FLD_RAND_EVENT_LEN = 17307; // 1 +static const uint64_t SH_FLD_RAND_SAMP_ELIG = 17308; // 192 +static const uint64_t SH_FLD_RAND_SAMP_ELIG_LEN = 17309; // 192 +static const uint64_t SH_FLD_RAND_SAMP_MODE = 17310; // 192 +static const uint64_t SH_FLD_RAND_SAMP_MODE_LEN = 17311; // 192 +static const uint64_t SH_FLD_RANGE = 17312; // 2 +static const uint64_t SH_FLD_RANGE_LEN = 17313; // 2 +static const uint64_t SH_FLD_RANK = 17314; // 8 +static const uint64_t SH_FLD_RANK_LEN = 17315; // 8 +static const uint64_t SH_FLD_RANK_OVERRIDE = 17316; // 8 +static const uint64_t SH_FLD_RANK_OVERRIDE_VALUE = 17317; // 8 +static const uint64_t SH_FLD_RANK_OVERRIDE_VALUE_LEN = 17318; // 8 +static const uint64_t SH_FLD_RANK_PAIR = 17319; // 8 +static const uint64_t SH_FLD_RANK_PAIR_LEN = 17320; // 8 +static const uint64_t SH_FLD_RANK_SM_1HOT = 17321; // 8 +static const uint64_t SH_FLD_RATE = 17322; // 14 +static const uint64_t SH_FLD_RATE_LEN = 17323; // 14 +static const uint64_t SH_FLD_RATIO = 17324; // 2 +static const uint64_t SH_FLD_RATIO_LEN = 17325; // 2 +static const uint64_t SH_FLD_RAW_CYC_CNT = 17326; // 24 +static const uint64_t SH_FLD_RAW_CYC_CNT_LEN = 17327; // 24 +static const uint64_t SH_FLD_RBUFSM_ERROR = 17328; // 2 +static const uint64_t SH_FLD_RC = 17329; // 8 +static const uint64_t SH_FLD_RCDAT_RD_PARITY_ERR = 17330; // 12 +static const uint64_t SH_FLD_RCD_CAL_PARITY_ERROR = 17331; // 8 +static const uint64_t SH_FLD_RCD_PARITY_ERROR = 17332; // 16 +static const uint64_t SH_FLD_RCE_COUNT = 17333; // 2 +static const uint64_t SH_FLD_RCE_COUNT_LEN = 17334; // 2 +static const uint64_t SH_FLD_RCE_ETE_ATTN = 17335; // 2 +static const uint64_t SH_FLD_RCMD0_ADDR_PARITY_ERROR = 17336; // 2 +static const uint64_t SH_FLD_RCMD0_ADDR_PERR = 17337; // 1 +static const uint64_t SH_FLD_RCMD0_TTAG_PERR = 17338; // 1 +static const uint64_t SH_FLD_RCMD1_ADDR_PARITY_ERROR = 17339; // 2 +static const uint64_t SH_FLD_RCMD1_ADDR_PERR = 17340; // 1 +static const uint64_t SH_FLD_RCMD1_TTAG_PERR = 17341; // 1 +static const uint64_t SH_FLD_RCMD2_ADDR_PARITY_ERROR = 17342; // 2 +static const uint64_t SH_FLD_RCMD2_ADDR_PERR = 17343; // 1 +static const uint64_t SH_FLD_RCMD2_TTAG_PERR = 17344; // 1 +static const uint64_t SH_FLD_RCMD3_ADDR_PARITY_ERROR = 17345; // 2 +static const uint64_t SH_FLD_RCMD3_ADDR_PERR = 17346; // 1 +static const uint64_t SH_FLD_RCMD3_TTAG_PERR = 17347; // 1 +static const uint64_t SH_FLD_RCMD_ASYNC_IF = 17348; // 8 +static const uint64_t SH_FLD_RCMD_ERR_INJ = 17349; // 8 +static const uint64_t SH_FLD_RCS_RECOVERY_FAILED_ERRHOLD = 17350; // 2 +static const uint64_t SH_FLD_RCS_RECOVERY_TIMEOUT_ERRHOLD = 17351; // 2 +static const uint64_t SH_FLD_RCS_STATE_MACHINE_ERRHOLD = 17352; // 2 +static const uint64_t SH_FLD_RCTRL_CONFIG = 17353; // 8 +static const uint64_t SH_FLD_RCTRL_CONFIG_LEN = 17354; // 8 +static const uint64_t SH_FLD_RCTRL_DEBUG_SEL = 17355; // 4 +static const uint64_t SH_FLD_RCTRL_DEBUG_SEL_LEN = 17356; // 4 +static const uint64_t SH_FLD_RCTRL_WAT_ACTION_SEL = 17357; // 4 +static const uint64_t SH_FLD_RCTRL_WAT_ACTION_SEL_LEN = 17358; // 4 +static const uint64_t SH_FLD_RCVD_POISONED_CIST_DATA = 17359; // 1 +static const uint64_t SH_FLD_RCV_BRDCST_GROUP = 17360; // 1 +static const uint64_t SH_FLD_RCV_BRDCST_GROUP_LEN = 17361; // 1 +static const uint64_t SH_FLD_RCV_CAPTURE = 17362; // 1 +static const uint64_t SH_FLD_RCV_CAPTURE_LEN = 17363; // 1 +static const uint64_t SH_FLD_RCV_CHIPID = 17364; // 1 +static const uint64_t SH_FLD_RCV_CHIPID_LEN = 17365; // 1 +static const uint64_t SH_FLD_RCV_CREDIT_OVERFLOW_ENA = 17366; // 6 +static const uint64_t SH_FLD_RCV_DATATO_DIV = 17367; // 1 +static const uint64_t SH_FLD_RCV_DATATO_DIV_LEN = 17368; // 1 +static const uint64_t SH_FLD_RCV_ERROR = 17369; // 1 +static const uint64_t SH_FLD_RCV_GROUPID = 17370; // 1 +static const uint64_t SH_FLD_RCV_GROUPID_LEN = 17371; // 1 +static const uint64_t SH_FLD_RCV_IN_PROGRESS = 17372; // 1 +static const uint64_t SH_FLD_RCV_PB_OP_HANG_ERR = 17373; // 1 +static const uint64_t SH_FLD_RCV_RESERVATION_SET = 17374; // 1 +static const uint64_t SH_FLD_RCV_RESET = 17375; // 1 +static const uint64_t SH_FLD_RCV_TOD_STATE = 17376; // 1 +static const uint64_t SH_FLD_RCV_TOD_STATE_LEN = 17377; // 1 +static const uint64_t SH_FLD_RCV_TTAG_PARITY_ERR = 17378; // 1 +static const uint64_t SH_FLD_RCV_WRITE_IN_PROGRESS = 17379; // 1 +static const uint64_t SH_FLD_RC_ADDR_PAR = 17380; // 1 +static const uint64_t SH_FLD_RC_ENABLE_AUTO_RECAL = 17381; // 2 +static const uint64_t SH_FLD_RC_ENABLE_BER_TEST = 17382; // 4 +static const uint64_t SH_FLD_RC_ENABLE_CM_COARSE_CAL = 17383; // 6 +static const uint64_t SH_FLD_RC_ENABLE_CM_FINE_CAL = 17384; // 6 +static const uint64_t SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 17385; // 6 +static const uint64_t SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 17386; // 6 +static const uint64_t SH_FLD_RC_ENABLE_CTLE_COARSE_CAL = 17387; // 6 +static const uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 17388; // 2 +static const uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 17389; // 4 +static const uint64_t SH_FLD_RC_ENABLE_DAC_H1_CAL = 17390; // 6 +static const uint64_t SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL = 17391; // 4 +static const uint64_t SH_FLD_RC_ENABLE_DDC = 17392; // 6 +static const uint64_t SH_FLD_RC_ENABLE_DFE_H1_CAL = 17393; // 6 +static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_CAL = 17394; // 4 +static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP = 17395; // 4 +static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 17396; // 4 +static const uint64_t SH_FLD_RC_ENABLE_DFE_H6_H12_FAST_MODE = 17397; // 4 +static const uint64_t SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE = 17398; // 4 +static const uint64_t SH_FLD_RC_ENABLE_H1AP_TWEAK = 17399; // 6 +static const uint64_t SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 17400; // 6 +static const uint64_t SH_FLD_RC_ENABLE_RESULT_CHECK = 17401; // 4 +static const uint64_t SH_FLD_RC_ENABLE_VGA_AMAX_MODE = 17402; // 6 +static const uint64_t SH_FLD_RC_ENABLE_VGA_CAL = 17403; // 6 +static const uint64_t SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 17404; // 2 +static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 17405; // 12 +static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR = 17406; // 12 +static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP = 17407; // 12 +static const uint64_t SH_FLD_RC_MASK = 17408; // 8 +static const uint64_t SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 17409; // 12 +static const uint64_t SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 17410; // 12 +static const uint64_t SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 17411; // 12 +static const uint64_t SH_FLD_RC_POWERBUS_DATA_TIMEOUT = 17412; // 12 +static const uint64_t SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 17413; // 12 +static const uint64_t SH_FLD_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR = 17414; // 12 +static const uint64_t SH_FLD_RC_TTAG_PAR = 17415; // 1 +static const uint64_t SH_FLD_RDADDR_ARB_BAD_HAND = 17416; // 2 +static const uint64_t SH_FLD_RDATA = 17417; // 1 +static const uint64_t SH_FLD_RDATA_LEN = 17418; // 1 +static const uint64_t SH_FLD_RDCLK_ALIGN = 17419; // 8 +static const uint64_t SH_FLD_RDCMP = 17420; // 2 +static const uint64_t SH_FLD_RDCMP_LEN = 17421; // 2 +static const uint64_t SH_FLD_RDIV = 17422; // 14 +static const uint64_t SH_FLD_RDIV_LEN = 17423; // 10 +static const uint64_t SH_FLD_RDQ_ABORT_OP = 17424; // 1 +static const uint64_t SH_FLD_RDQ_ABORT_TRM = 17425; // 1 +static const uint64_t SH_FLD_RDQ_BAD_CRESP = 17426; // 1 +static const uint64_t SH_FLD_RDQ_DATA_HANG = 17427; // 1 +static const uint64_t SH_FLD_RDQ_FSM_PERR = 17428; // 1 +static const uint64_t SH_FLD_RDQ_OP_HANG = 17429; // 1 +static const uint64_t SH_FLD_RDQ_OVERFLOW = 17430; // 1 +static const uint64_t SH_FLD_RDWR_ACCESS_EN = 17431; // 2 +static const uint64_t SH_FLD_RDWR_ADDR = 17432; // 2 +static const uint64_t SH_FLD_RDWR_ADDR_LEN = 17433; // 2 +static const uint64_t SH_FLD_RDWR_OP_BUSY = 17434; // 1 +static const uint64_t SH_FLD_RDWR_RDWR_DATA = 17435; // 2 +static const uint64_t SH_FLD_RDWR_RDWR_DATA_LEN = 17436; // 2 +static const uint64_t SH_FLD_RDWR_READ_STATUS = 17437; // 2 +static const uint64_t SH_FLD_RDWR_REQ_PEND = 17438; // 2 +static const uint64_t SH_FLD_RDWR_UPDATE_ERROR = 17439; // 2 +static const uint64_t SH_FLD_RDWR_WRITE_MODE = 17440; // 2 +static const uint64_t SH_FLD_RDWR_WRITE_STATUS = 17441; // 2 +static const uint64_t SH_FLD_RDWR_WR_ENABLE = 17442; // 2 +static const uint64_t SH_FLD_RDX_BUS0_STG0_SEL = 17443; // 1 +static const uint64_t SH_FLD_RDX_BUS0_STG0_SEL_LEN = 17444; // 1 +static const uint64_t SH_FLD_RDX_BUS0_STG1_SEL = 17445; // 1 +static const uint64_t SH_FLD_RDX_BUS0_STG2_SEL = 17446; // 1 +static const uint64_t SH_FLD_RDX_BUS1_STG0_SEL = 17447; // 1 +static const uint64_t SH_FLD_RDX_BUS1_STG0_SEL_LEN = 17448; // 1 +static const uint64_t SH_FLD_RDX_BUS1_STG1_SEL = 17449; // 1 +static const uint64_t SH_FLD_RDX_BUS1_STG2_SEL = 17450; // 1 +static const uint64_t SH_FLD_RD_ADDR_0_7 = 17451; // 1 +static const uint64_t SH_FLD_RD_ADDR_0_7_LEN = 17452; // 1 +static const uint64_t SH_FLD_RD_CNTL = 17453; // 8 +static const uint64_t SH_FLD_RD_CNTL_MASK = 17454; // 8 +static const uint64_t SH_FLD_RD_DATA_COUNT = 17455; // 1 +static const uint64_t SH_FLD_RD_DATA_COUNT_LEN = 17456; // 1 +static const uint64_t SH_FLD_RD_DATA_PARITY_ERROR = 17457; // 3 +static const uint64_t SH_FLD_RD_ECC_CE = 17458; // 1 +static const uint64_t SH_FLD_RD_ECC_UE = 17459; // 1 +static const uint64_t SH_FLD_RD_GO_M_QOS = 17460; // 2 +static const uint64_t SH_FLD_RD_MACHINE_HANG = 17461; // 12 +static const uint64_t SH_FLD_RD_RST_INTRPT_FACES = 17462; // 1 +static const uint64_t SH_FLD_RD_RST_INTRPT_PIB = 17463; // 1 +static const uint64_t SH_FLD_RD_SCOPE = 17464; // 24 +static const uint64_t SH_FLD_RD_SCOPE_LEN = 17465; // 24 +static const uint64_t SH_FLD_RD_SLVNUM = 17466; // 6 +static const uint64_t SH_FLD_RD_SLVNUM_LEN = 17467; // 6 +static const uint64_t SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR = 17468; // 8 +static const uint64_t SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR = 17469; // 8 +static const uint64_t SH_FLD_READ_BUFFER_OVERFLOW_ERROR = 17470; // 8 +static const uint64_t SH_FLD_READ_COMPARE_REQUIRED = 17471; // 64 +static const uint64_t SH_FLD_READ_COMPLETE = 17472; // 1 +static const uint64_t SH_FLD_READ_CONTINUE_0 = 17473; // 2 +static const uint64_t SH_FLD_READ_CONTINUE_1 = 17474; // 1 +static const uint64_t SH_FLD_READ_CONTINUE_2 = 17475; // 1 +static const uint64_t SH_FLD_READ_CONTINUE_3 = 17476; // 1 +static const uint64_t SH_FLD_READ_CONTROL_OVERFLOW_ERROR = 17477; // 8 +static const uint64_t SH_FLD_READ_COUNT = 17478; // 8 +static const uint64_t SH_FLD_READ_COUNT_LEN = 17479; // 8 +static const uint64_t SH_FLD_READ_CPM_LT = 17480; // 43 +static const uint64_t SH_FLD_READ_CRD_POOL = 17481; // 1 +static const uint64_t SH_FLD_READ_CRD_POOL_LEN = 17482; // 1 +static const uint64_t SH_FLD_READ_CTR = 17483; // 8 +static const uint64_t SH_FLD_READ_DATA = 17484; // 3 +static const uint64_t SH_FLD_READ_DATA_LEN = 17485; // 3 +static const uint64_t SH_FLD_READ_DATA_VALID = 17486; // 3 +static const uint64_t SH_FLD_READ_DEBUG_SELECT = 17487; // 8 +static const uint64_t SH_FLD_READ_DEBUG_SELECT_LEN = 17488; // 8 +static const uint64_t SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR = 17489; // 8 +static const uint64_t SH_FLD_READ_ENABLE = 17490; // 129 +static const uint64_t SH_FLD_READ_EPSILON_MODE = 17491; // 2 +static const uint64_t SH_FLD_READ_EPSILON_TIER0 = 17492; // 2 +static const uint64_t SH_FLD_READ_EPSILON_TIER0_LEN = 17493; // 2 +static const uint64_t SH_FLD_READ_EPSILON_TIER1 = 17494; // 2 +static const uint64_t SH_FLD_READ_EPSILON_TIER1_LEN = 17495; // 2 +static const uint64_t SH_FLD_READ_EPSILON_TIER2 = 17496; // 2 +static const uint64_t SH_FLD_READ_EPSILON_TIER2_LEN = 17497; // 2 +static const uint64_t SH_FLD_READ_ERR_INJECT0 = 17498; // 8 +static const uint64_t SH_FLD_READ_ERR_INJECT0_LEN = 17499; // 8 +static const uint64_t SH_FLD_READ_INVALID_FACES = 17500; // 1 +static const uint64_t SH_FLD_READ_INVALID_PIB = 17501; // 1 +static const uint64_t SH_FLD_READ_LATENCY_OFFSET = 17502; // 8 +static const uint64_t SH_FLD_READ_LATENCY_OFFSET_LEN = 17503; // 8 +static const uint64_t SH_FLD_READ_NOT_WRITE_0 = 17504; // 2 +static const uint64_t SH_FLD_READ_NOT_WRITE_1 = 17505; // 1 +static const uint64_t SH_FLD_READ_NOT_WRITE_2 = 17506; // 1 +static const uint64_t SH_FLD_READ_NOT_WRITE_3 = 17507; // 1 +static const uint64_t SH_FLD_READ_NVLD = 17508; // 1 +static const uint64_t SH_FLD_READ_OR_WRITE_DATA = 17509; // 64 +static const uint64_t SH_FLD_READ_OR_WRITE_DATA_LEN = 17510; // 64 +static const uint64_t SH_FLD_READ_PAR_NOT_SEQ = 17511; // 8 +static const uint64_t SH_FLD_READ_POOL = 17512; // 1 +static const uint64_t SH_FLD_READ_POOL_LEN = 17513; // 1 +static const uint64_t SH_FLD_READ_PREFETCH_CTL = 17514; // 4 +static const uint64_t SH_FLD_READ_PREFETCH_CTL_LEN = 17515; // 4 +static const uint64_t SH_FLD_READ_RESPONSE_DELAY_ENABLE = 17516; // 2 +static const uint64_t SH_FLD_READ_RST_INTERRUPT_FACES = 17517; // 1 +static const uint64_t SH_FLD_READ_RST_INTERRUPT_PIB = 17518; // 1 +static const uint64_t SH_FLD_READ_STATE_LT = 17519; // 43 +static const uint64_t SH_FLD_READ_STATE_LT_LEN = 17520; // 43 +static const uint64_t SH_FLD_READ_TTYPE = 17521; // 4 +static const uint64_t SH_FLD_RECAL_ABORT = 17522; // 48 +static const uint64_t SH_FLD_RECAL_ABORT_DL_MASK = 17523; // 2 +static const uint64_t SH_FLD_RECAL_DONE_DL_MASK = 17524; // 2 +static const uint64_t SH_FLD_RECAL_ERROR = 17525; // 8 +static const uint64_t SH_FLD_RECAL_LANE_TO_MONITOR = 17526; // 6 +static const uint64_t SH_FLD_RECAL_LANE_TO_MONITOR_LEN = 17527; // 6 +static const uint64_t SH_FLD_RECAL_MAX_SPARES_EXCEEDED = 17528; // 8 +static const uint64_t SH_FLD_RECAL_REQ = 17529; // 48 +static const uint64_t SH_FLD_RECAL_REQ_DL_MASK = 17530; // 2 +static const uint64_t SH_FLD_RECAL_SPARE_DEPLOYED = 17531; // 8 +static const uint64_t SH_FLD_RECEIVED = 17532; // 1 +static const uint64_t SH_FLD_RECEIVED_ERROR = 17533; // 1 +static const uint64_t SH_FLD_RECEIVER_MODE = 17534; // 3 +static const uint64_t SH_FLD_RECEIVER_MODE_LEN = 17535; // 3 +static const uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER = 17536; // 1 +static const uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 17537; // 1 +static const uint64_t SH_FLD_RECOV = 17538; // 86 +static const uint64_t SH_FLD_RECOVERABLE_ERROR = 17539; // 2 +static const uint64_t SH_FLD_RECOVERY_BLK = 17540; // 24 +static const uint64_t SH_FLD_RECOVERY_BLK_EXTEND = 17541; // 24 +static const uint64_t SH_FLD_RECOVERY_FAILED = 17542; // 6 +static const uint64_t SH_FLD_RECOVERY_HANG_DETECTED = 17543; // 2 +static const uint64_t SH_FLD_RECR_PE = 17544; // 8 +static const uint64_t SH_FLD_REC_ACK_DEAD_ERROR = 17545; // 2 +static const uint64_t SH_FLD_REC_LIMIT = 17546; // 24 +static const uint64_t SH_FLD_REC_LIMIT_LEN = 17547; // 24 +static const uint64_t SH_FLD_REC_PB_SM_ERROR_ERR = 17548; // 2 +static const uint64_t SH_FLD_REC_SM_ERROR_ERR = 17549; // 2 +static const uint64_t SH_FLD_REC_UPDATE_ERROR = 17550; // 2 +static const uint64_t SH_FLD_REDIS_PRIORITY = 17551; // 1 +static const uint64_t SH_FLD_REDIS_PRIORITY_LEN = 17552; // 1 +static const uint64_t SH_FLD_REDIS_RSD = 17553; // 1 +static const uint64_t SH_FLD_REDIS_RSD_LEN = 17554; // 1 +static const uint64_t SH_FLD_REFCLKSEL = 17555; // 4 +static const uint64_t SH_FLD_REFCLK_0_TERM_DIS_DC = 17556; // 3 +static const uint64_t SH_FLD_REFCLK_1_TERM_DIS_DC = 17557; // 3 +static const uint64_t SH_FLD_REFCLK_CLKMUX0_SEL = 17558; // 43 +static const uint64_t SH_FLD_REFCLK_CLKMUX1_SEL = 17559; // 43 +static const uint64_t SH_FLD_REFCLOCK_STATUS = 17560; // 2 +static const uint64_t SH_FLD_REFCLOCK_STATUS_LEN = 17561; // 2 +static const uint64_t SH_FLD_REFISINK = 17562; // 3 +static const uint64_t SH_FLD_REFISINK_LEN = 17563; // 3 +static const uint64_t SH_FLD_REFISRC = 17564; // 3 +static const uint64_t SH_FLD_REFISRC_LEN = 17565; // 3 +static const uint64_t SH_FLD_REFRESH_ALL_RANKS = 17566; // 8 +static const uint64_t SH_FLD_REFRESH_BLOCK_CONFIG = 17567; // 8 +static const uint64_t SH_FLD_REFRESH_BLOCK_CONFIG_LEN = 17568; // 8 +static const uint64_t SH_FLD_REFRESH_CONTROL = 17569; // 8 +static const uint64_t SH_FLD_REFRESH_CONTROL_LEN = 17570; // 8 +static const uint64_t SH_FLD_REFRESH_COUNT = 17571; // 8 +static const uint64_t SH_FLD_REFRESH_COUNT_LEN = 17572; // 8 +static const uint64_t SH_FLD_REFRESH_INTERVAL = 17573; // 8 +static const uint64_t SH_FLD_REFRESH_INTERVAL_LEN = 17574; // 8 +static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_EN = 17575; // 2 +static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 17576; // 2 +static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 17577; // 2 +static const uint64_t SH_FLD_REFRESH_OVERRUN = 17578; // 16 +static const uint64_t SH_FLD_REFVREG = 17579; // 3 +static const uint64_t SH_FLD_REFVREG_LEN = 17580; // 3 +static const uint64_t SH_FLD_REG = 17581; // 19 +static const uint64_t SH_FLD_REGF = 17582; // 43 +static const uint64_t SH_FLD_REGION = 17583; // 72 +static const uint64_t SH_FLD_REGION_LEN = 17584; // 72 +static const uint64_t SH_FLD_REGISTER = 17585; // 3 +static const uint64_t SH_FLD_REGISTER_ACCESS_ERROR = 17586; // 3 +static const uint64_t SH_FLD_REGISTER_ACCESS_FSM_CHECK = 17587; // 3 +static const uint64_t SH_FLD_REGISTER_LEN = 17588; // 3 +static const uint64_t SH_FLD_REGISTER_PE = 17589; // 4 +static const uint64_t SH_FLD_REGISTER_VALID = 17590; // 4 +static const uint64_t SH_FLD_REGS = 17591; // 1 +static const uint64_t SH_FLD_REGSEL = 17592; // 4 +static const uint64_t SH_FLD_REGSEL_LEN = 17593; // 4 +static const uint64_t SH_FLD_REGS_CMD_CRD_ERROR = 17594; // 1 +static const uint64_t SH_FLD_REGS_DATA_CRD_ERROR = 17595; // 1 +static const uint64_t SH_FLD_REGS_IORESET = 17596; // 48 +static const uint64_t SH_FLD_REGS_LEN = 17597; // 1 +static const uint64_t SH_FLD_REGS_ORDERING_TAG = 17598; // 1 +static const uint64_t SH_FLD_REGS_ORDERING_TAG_LEN = 17599; // 1 +static const uint64_t SH_FLD_REGS_PARITY_ERROR = 17600; // 1 +static const uint64_t SH_FLD_REGS_SCOM_INTERNAL_ERROR = 17601; // 1 +static const uint64_t SH_FLD_REGULAR_WKUP_ACTIVE = 17602; // 30 +static const uint64_t SH_FLD_REGULAR_WKUP_PRESENT = 17603; // 30 +static const uint64_t SH_FLD_REGULAR_WKUP_REQUESTED = 17604; // 30 +static const uint64_t SH_FLD_REG_ADDR_LENGTH = 17605; // 1 +static const uint64_t SH_FLD_REG_ADDR_LENGTH_LEN = 17606; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_0 = 17607; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_0_LEN = 17608; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_1 = 17609; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_1_LEN = 17610; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_2 = 17611; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_2_LEN = 17612; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_3 = 17613; // 1 +static const uint64_t SH_FLD_REG_ADDR_LEN_3_LEN = 17614; // 1 +static const uint64_t SH_FLD_REG_DP16 = 17615; // 16 +static const uint64_t SH_FLD_REG_DP16_LEN = 17616; // 16 +static const uint64_t SH_FLD_REG_ENABLE = 17617; // 1 +static const uint64_t SH_FLD_REG_FIFO_SIZE_EQ_1 = 17618; // 1 +static const uint64_t SH_FLD_REG_LEN = 17619; // 19 +static const uint64_t SH_FLD_REG_UNUSED = 17620; // 1 +static const uint64_t SH_FLD_REG_UNUSED_LEN = 17621; // 1 +static const uint64_t SH_FLD_REG_WAKEUP_C0 = 17622; // 24 +static const uint64_t SH_FLD_REG_WAKEUP_C1 = 17623; // 24 +static const uint64_t SH_FLD_REG_WKUP_OVERRIDE = 17624; // 30 +static const uint64_t SH_FLD_REINIT_CREDITS = 17625; // 1 +static const uint64_t SH_FLD_REJECTED_PASTE_CMD = 17626; // 2 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_ADD = 17627; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_AND = 17628; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_E = 17629; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S = 17630; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U = 17631; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17632; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U = 17633; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_U = 17634; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_OR = 17635; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_XOR = 17636; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_ADD = 17637; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_AND = 17638; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S = 17639; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U = 17640; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S = 17641; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U = 17642; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_OR = 17643; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_ARMW_XOR = 17644; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_INJ = 17645; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W = 17646; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W_HP = 17647; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_CL_RD_NC_F0 = 17648; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_DMA_PR_W = 17649; // 12 +static const uint64_t SH_FLD_RELAXED_CMD_PR_DMA_INJ = 17650; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED0 = 17651; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED0_LEN = 17652; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED1 = 17653; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED1_LEN = 17654; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED2 = 17655; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED2_LEN = 17656; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED3 = 17657; // 12 +static const uint64_t SH_FLD_RELAXED_RESERVED3_LEN = 17658; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE0_MASK = 17659; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE0_MASK_LEN = 17660; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE0_MATCH = 17661; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE0_MATCH_LEN = 17662; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE0_RDENA = 17663; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE0_WRENA = 17664; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE1_MASK = 17665; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE1_MASK_LEN = 17666; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE1_MATCH = 17667; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE1_MATCH_LEN = 17668; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE1_RDENA = 17669; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE1_WRENA = 17670; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE2_MASK = 17671; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE2_MASK_LEN = 17672; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE2_MATCH = 17673; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE2_MATCH_LEN = 17674; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE2_RDENA = 17675; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE2_WRENA = 17676; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE3_MASK = 17677; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE3_MASK_LEN = 17678; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE3_MATCH = 17679; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE3_MATCH_LEN = 17680; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE3_RDENA = 17681; // 12 +static const uint64_t SH_FLD_RELAXED_SOURCE3_WRENA = 17682; // 12 +static const uint64_t SH_FLD_RELAXED_WR_DMA = 17683; // 1 +static const uint64_t SH_FLD_RELAXED_WR_EQP = 17684; // 1 +static const uint64_t SH_FLD_RELAXED_WR_ORDERING = 17685; // 1 +static const uint64_t SH_FLD_RELEASE_LBUS_OWNERSHIP = 17686; // 2 +static const uint64_t SH_FLD_RELEASE_LBUS_OWNERSHIP_LEN = 17687; // 2 +static const uint64_t SH_FLD_REL_ASYNC_PARITY_ERROR = 17688; // 8 +static const uint64_t SH_FLD_REL_ASYNC_SEQUENCE_ERROR = 17689; // 8 +static const uint64_t SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR = 17690; // 8 +static const uint64_t SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR = 17691; // 8 +static const uint64_t SH_FLD_REMAINING_WORDS = 17692; // 1 +static const uint64_t SH_FLD_REMAINING_WORDS_LEN = 17693; // 1 +static const uint64_t SH_FLD_REMAP_DEST = 17694; // 1 +static const uint64_t SH_FLD_REMAP_DEST_LEN = 17695; // 1 +static const uint64_t SH_FLD_REMAP_SOURCE = 17696; // 1 +static const uint64_t SH_FLD_REMAP_SOURCE_LEN = 17697; // 1 +static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE = 17698; // 5 +static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN = 17699; // 5 +static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID = 17700; // 5 +static const uint64_t SH_FLD_REMOTE_LATENCY_LONGER_LINK = 17701; // 5 +static const uint64_t SH_FLD_REMOTE_NODAL_EPSILON = 17702; // 8 +static const uint64_t SH_FLD_REMOTE_NODAL_EPSILON_LEN = 17703; // 8 +static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION = 17704; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR = 17705; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN = 17706; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 17707; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 17708; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_DISABLE = 17709; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_ERROR_DISABLE = 17710; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX = 17711; // 1 +static const uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 17712; // 1 +static const uint64_t SH_FLD_REM_0 = 17713; // 6 +static const uint64_t SH_FLD_REM_0_LEN = 17714; // 6 +static const uint64_t SH_FLD_REM_1 = 17715; // 6 +static const uint64_t SH_FLD_REM_1_LEN = 17716; // 6 +static const uint64_t SH_FLD_REM_2 = 17717; // 6 +static const uint64_t SH_FLD_REM_2_LEN = 17718; // 6 +static const uint64_t SH_FLD_REM_3 = 17719; // 6 +static const uint64_t SH_FLD_REM_3_LEN = 17720; // 6 +static const uint64_t SH_FLD_REPAIR_DONE = 17721; // 4 +static const uint64_t SH_FLD_REPAIR_FAILED = 17722; // 4 +static const uint64_t SH_FLD_REPEAT_CMD_CNT = 17723; // 64 +static const uint64_t SH_FLD_REPEAT_CMD_CNT_LEN = 17724; // 64 +static const uint64_t SH_FLD_REPLAY_BUFFER_SIZE = 17725; // 2 +static const uint64_t SH_FLD_REPLAY_BUFFER_SIZE_LEN = 17726; // 2 +static const uint64_t SH_FLD_REPLAY_CAP_ADDR = 17727; // 10 +static const uint64_t SH_FLD_REPLAY_CAP_ADDR_LEN = 17728; // 10 +static const uint64_t SH_FLD_REPLAY_CAP_INST = 17729; // 10 +static const uint64_t SH_FLD_REPLAY_CAP_INST_LEN = 17730; // 4 +static const uint64_t SH_FLD_REPLAY_CAP_SYN = 17731; // 10 +static const uint64_t SH_FLD_REPLAY_CAP_SYN_LEN = 17732; // 10 +static const uint64_t SH_FLD_REPLAY_CAP_VALID = 17733; // 10 +static const uint64_t SH_FLD_REPORT_SL_CHKBIT_ERR = 17734; // 5 +static const uint64_t SH_FLD_REPR = 17735; // 43 +static const uint64_t SH_FLD_REPTEST_ENABLE = 17736; // 1 +static const uint64_t SH_FLD_REPTEST_MATCH_TH = 17737; // 1 +static const uint64_t SH_FLD_REPTEST_MATCH_TH_LEN = 17738; // 1 +static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 = 17739; // 1 +static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 17740; // 1 +static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 = 17741; // 1 +static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 17742; // 1 +static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH = 17743; // 1 +static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH_LEN = 17744; // 1 +static const uint64_t SH_FLD_REQ = 17745; // 43 +static const uint64_t SH_FLD_REQUEST = 17746; // 1 +static const uint64_t SH_FLD_REQUEST_LBUS_OWNERSHIP = 17747; // 2 +static const uint64_t SH_FLD_REQUEST_LEN = 17748; // 1 +static const uint64_t SH_FLD_REQ_INTR_PAYLOAD = 17749; // 30 +static const uint64_t SH_FLD_REQ_INTR_PAYLOAD_LEN = 17750; // 30 +static const uint64_t SH_FLD_REQ_INTR_TYPE = 17751; // 30 +static const uint64_t SH_FLD_REQ_INTR_TYPE_LEN = 17752; // 30 +static const uint64_t SH_FLD_REQ_RESET_FR_SBE = 17753; // 1 +static const uint64_t SH_FLD_REQ_RESET_FR_SP = 17754; // 1 +static const uint64_t SH_FLD_REQ_STOP_LEVEL = 17755; // 150 +static const uint64_t SH_FLD_REQ_STOP_LEVEL_LEN = 17756; // 150 +static const uint64_t SH_FLD_REQ_WRITE_ENABLE = 17757; // 30 +static const uint64_t SH_FLD_RESERVATION_EN = 17758; // 1 +static const uint64_t SH_FLD_RESERVED = 17759; // 192 +static const uint64_t SH_FLD_RESERVED0 = 17760; // 44 +static const uint64_t SH_FLD_RESERVED0_3 = 17761; // 4 +static const uint64_t SH_FLD_RESERVED0_3_LEN = 17762; // 4 +static const uint64_t SH_FLD_RESERVED0_LEN = 17763; // 12 +static const uint64_t SH_FLD_RESERVED1 = 17764; // 393 +static const uint64_t SH_FLD_RESERVED12_15 = 17765; // 16 +static const uint64_t SH_FLD_RESERVED12_15_LEN = 17766; // 16 +static const uint64_t SH_FLD_RESERVED13_15 = 17767; // 4 +static const uint64_t SH_FLD_RESERVED13_15_LEN = 17768; // 4 +static const uint64_t SH_FLD_RESERVED14 = 17769; // 4 +static const uint64_t SH_FLD_RESERVED15 = 17770; // 4 +static const uint64_t SH_FLD_RESERVED18 = 17771; // 4 +static const uint64_t SH_FLD_RESERVED19 = 17772; // 4 +static const uint64_t SH_FLD_RESERVED19_22 = 17773; // 4 +static const uint64_t SH_FLD_RESERVED19_22_LEN = 17774; // 4 +static const uint64_t SH_FLD_RESERVED19_31 = 17775; // 4 +static const uint64_t SH_FLD_RESERVED19_31_LEN = 17776; // 4 +static const uint64_t SH_FLD_RESERVED1_2 = 17777; // 4 +static const uint64_t SH_FLD_RESERVED1_2_LEN = 17778; // 4 +static const uint64_t SH_FLD_RESERVED1_LEN = 17779; // 251 +static const uint64_t SH_FLD_RESERVED2 = 17780; // 240 +static const uint64_t SH_FLD_RESERVED20 = 17781; // 4 +static const uint64_t SH_FLD_RESERVED21 = 17782; // 4 +static const uint64_t SH_FLD_RESERVED21_23 = 17783; // 4 +static const uint64_t SH_FLD_RESERVED21_23_LEN = 17784; // 4 +static const uint64_t SH_FLD_RESERVED22 = 17785; // 4 +static const uint64_t SH_FLD_RESERVED22_31 = 17786; // 8 +static const uint64_t SH_FLD_RESERVED22_31_LEN = 17787; // 8 +static const uint64_t SH_FLD_RESERVED23 = 17788; // 4 +static const uint64_t SH_FLD_RESERVED25 = 17789; // 4 +static const uint64_t SH_FLD_RESERVED26 = 17790; // 4 +static const uint64_t SH_FLD_RESERVED27 = 17791; // 4 +static const uint64_t SH_FLD_RESERVED28 = 17792; // 4 +static const uint64_t SH_FLD_RESERVED28_31 = 17793; // 10 +static const uint64_t SH_FLD_RESERVED28_31_LEN = 17794; // 10 +static const uint64_t SH_FLD_RESERVED29_31 = 17795; // 4 +static const uint64_t SH_FLD_RESERVED29_31_LEN = 17796; // 4 +static const uint64_t SH_FLD_RESERVED2_15 = 17797; // 4 +static const uint64_t SH_FLD_RESERVED2_15_LEN = 17798; // 4 +static const uint64_t SH_FLD_RESERVED2_LEN = 17799; // 54 +static const uint64_t SH_FLD_RESERVED3 = 17800; // 68 +static const uint64_t SH_FLD_RESERVED36_47 = 17801; // 4 +static const uint64_t SH_FLD_RESERVED36_47_LEN = 17802; // 4 +static const uint64_t SH_FLD_RESERVED37_39 = 17803; // 4 +static const uint64_t SH_FLD_RESERVED37_39_LEN = 17804; // 4 +static const uint64_t SH_FLD_RESERVED3_7 = 17805; // 4 +static const uint64_t SH_FLD_RESERVED3_7_LEN = 17806; // 4 +static const uint64_t SH_FLD_RESERVED3_LEN = 17807; // 27 +static const uint64_t SH_FLD_RESERVED4 = 17808; // 18 +static const uint64_t SH_FLD_RESERVED45_47 = 17809; // 4 +static const uint64_t SH_FLD_RESERVED45_47_LEN = 17810; // 4 +static const uint64_t SH_FLD_RESERVED4_LEN = 17811; // 6 +static const uint64_t SH_FLD_RESERVED52_55 = 17812; // 4 +static const uint64_t SH_FLD_RESERVED52_55_LEN = 17813; // 4 +static const uint64_t SH_FLD_RESERVED57_63 = 17814; // 4 +static const uint64_t SH_FLD_RESERVED57_63_LEN = 17815; // 4 +static const uint64_t SH_FLD_RESERVED6 = 17816; // 1 +static const uint64_t SH_FLD_RESERVED63 = 17817; // 4 +static const uint64_t SH_FLD_RESERVED8_9 = 17818; // 8 +static const uint64_t SH_FLD_RESERVED8_9_LEN = 17819; // 8 +static const uint64_t SH_FLD_RESERVED9 = 17820; // 17 +static const uint64_t SH_FLD_RESERVED_0 = 17821; // 9 +static const uint64_t SH_FLD_RESERVED_00 = 17822; // 1 +static const uint64_t SH_FLD_RESERVED_02 = 17823; // 1 +static const uint64_t SH_FLD_RESERVED_03 = 17824; // 1 +static const uint64_t SH_FLD_RESERVED_0_1 = 17825; // 17 +static const uint64_t SH_FLD_RESERVED_0_11 = 17826; // 24 +static const uint64_t SH_FLD_RESERVED_0_11_LEN = 17827; // 24 +static const uint64_t SH_FLD_RESERVED_0_17 = 17828; // 2 +static const uint64_t SH_FLD_RESERVED_0_17_LEN = 17829; // 2 +static const uint64_t SH_FLD_RESERVED_0_1_LEN = 17830; // 17 +static const uint64_t SH_FLD_RESERVED_0_20 = 17831; // 5 +static const uint64_t SH_FLD_RESERVED_0_20_LEN = 17832; // 5 +static const uint64_t SH_FLD_RESERVED_0_23 = 17833; // 6 +static const uint64_t SH_FLD_RESERVED_0_23_LEN = 17834; // 6 +static const uint64_t SH_FLD_RESERVED_0_25 = 17835; // 1 +static const uint64_t SH_FLD_RESERVED_0_25_LEN = 17836; // 1 +static const uint64_t SH_FLD_RESERVED_0_29 = 17837; // 1 +static const uint64_t SH_FLD_RESERVED_0_29_LEN = 17838; // 1 +static const uint64_t SH_FLD_RESERVED_0_3 = 17839; // 1 +static const uint64_t SH_FLD_RESERVED_0_31 = 17840; // 2 +static const uint64_t SH_FLD_RESERVED_0_31_LEN = 17841; // 2 +static const uint64_t SH_FLD_RESERVED_0_32 = 17842; // 1 +static const uint64_t SH_FLD_RESERVED_0_32_LEN = 17843; // 1 +static const uint64_t SH_FLD_RESERVED_0_3_LEN = 17844; // 1 +static const uint64_t SH_FLD_RESERVED_0_LEN = 17845; // 2 +static const uint64_t SH_FLD_RESERVED_1 = 17846; // 13 +static const uint64_t SH_FLD_RESERVED_10 = 17847; // 1 +static const uint64_t SH_FLD_RESERVED_10_11 = 17848; // 32 +static const uint64_t SH_FLD_RESERVED_10_11_LEN = 17849; // 31 +static const uint64_t SH_FLD_RESERVED_10_LEN = 17850; // 1 +static const uint64_t SH_FLD_RESERVED_11 = 17851; // 2 +static const uint64_t SH_FLD_RESERVED_11A = 17852; // 43 +static const uint64_t SH_FLD_RESERVED_11_12 = 17853; // 4 +static const uint64_t SH_FLD_RESERVED_11_12_LEN = 17854; // 4 +static const uint64_t SH_FLD_RESERVED_11_14 = 17855; // 4 +static const uint64_t SH_FLD_RESERVED_11_14_LEN = 17856; // 4 +static const uint64_t SH_FLD_RESERVED_11_15 = 17857; // 1 +static const uint64_t SH_FLD_RESERVED_11_15_LEN = 17858; // 1 +static const uint64_t SH_FLD_RESERVED_11_LEN = 17859; // 1 +static const uint64_t SH_FLD_RESERVED_12 = 17860; // 3 +static const uint64_t SH_FLD_RESERVED_12_13 = 17861; // 9 +static const uint64_t SH_FLD_RESERVED_12_13_LEN = 17862; // 9 +static const uint64_t SH_FLD_RESERVED_12_14 = 17863; // 30 +static const uint64_t SH_FLD_RESERVED_12_14_LEN = 17864; // 30 +static const uint64_t SH_FLD_RESERVED_12_15 = 17865; // 24 +static const uint64_t SH_FLD_RESERVED_12_15_LEN = 17866; // 24 +static const uint64_t SH_FLD_RESERVED_12_16 = 17867; // 1 +static const uint64_t SH_FLD_RESERVED_12_16_LEN = 17868; // 1 +static const uint64_t SH_FLD_RESERVED_12_23 = 17869; // 1 +static const uint64_t SH_FLD_RESERVED_12_23_LEN = 17870; // 1 +static const uint64_t SH_FLD_RESERVED_13 = 17871; // 2 +static const uint64_t SH_FLD_RESERVED_13_15 = 17872; // 12 +static const uint64_t SH_FLD_RESERVED_13_15_LEN = 17873; // 12 +static const uint64_t SH_FLD_RESERVED_13_31 = 17874; // 2 +static const uint64_t SH_FLD_RESERVED_13_31_LEN = 17875; // 2 +static const uint64_t SH_FLD_RESERVED_13_33 = 17876; // 2 +static const uint64_t SH_FLD_RESERVED_13_33_LEN = 17877; // 2 +static const uint64_t SH_FLD_RESERVED_13_LEN = 17878; // 1 +static const uint64_t SH_FLD_RESERVED_14 = 17879; // 1 +static const uint64_t SH_FLD_RESERVED_14C = 17880; // 43 +static const uint64_t SH_FLD_RESERVED_14_15 = 17881; // 1 +static const uint64_t SH_FLD_RESERVED_14_15_LEN = 17882; // 1 +static const uint64_t SH_FLD_RESERVED_14_LEN = 17883; // 1 +static const uint64_t SH_FLD_RESERVED_15 = 17884; // 10 +static const uint64_t SH_FLD_RESERVED_15C = 17885; // 43 +static const uint64_t SH_FLD_RESERVED_16 = 17886; // 9 +static const uint64_t SH_FLD_RESERVED_16_17 = 17887; // 4 +static const uint64_t SH_FLD_RESERVED_16_17_LEN = 17888; // 4 +static const uint64_t SH_FLD_RESERVED_16_18 = 17889; // 30 +static const uint64_t SH_FLD_RESERVED_16_18_LEN = 17890; // 30 +static const uint64_t SH_FLD_RESERVED_16_26 = 17891; // 1 +static const uint64_t SH_FLD_RESERVED_16_26_LEN = 17892; // 1 +static const uint64_t SH_FLD_RESERVED_16_27 = 17893; // 1 +static const uint64_t SH_FLD_RESERVED_16_27_LEN = 17894; // 1 +static const uint64_t SH_FLD_RESERVED_16_LEN = 17895; // 1 +static const uint64_t SH_FLD_RESERVED_17 = 17896; // 3 +static const uint64_t SH_FLD_RESERVED_17_19 = 17897; // 6 +static const uint64_t SH_FLD_RESERVED_17_19_LEN = 17898; // 6 +static const uint64_t SH_FLD_RESERVED_17_LEN = 17899; // 1 +static const uint64_t SH_FLD_RESERVED_18 = 17900; // 1 +static const uint64_t SH_FLD_RESERVED_18A = 17901; // 43 +static const uint64_t SH_FLD_RESERVED_18_19 = 17902; // 9 +static const uint64_t SH_FLD_RESERVED_18_19_LEN = 17903; // 9 +static const uint64_t SH_FLD_RESERVED_18_23 = 17904; // 10 +static const uint64_t SH_FLD_RESERVED_18_23_LEN = 17905; // 10 +static const uint64_t SH_FLD_RESERVED_18_29 = 17906; // 12 +static const uint64_t SH_FLD_RESERVED_18_29_LEN = 17907; // 12 +static const uint64_t SH_FLD_RESERVED_18_31 = 17908; // 2 +static const uint64_t SH_FLD_RESERVED_18_31_LEN = 17909; // 2 +static const uint64_t SH_FLD_RESERVED_18_LEN = 17910; // 1 +static const uint64_t SH_FLD_RESERVED_19 = 17911; // 2 +static const uint64_t SH_FLD_RESERVED_19A = 17912; // 43 +static const uint64_t SH_FLD_RESERVED_1_12 = 17913; // 4 +static const uint64_t SH_FLD_RESERVED_1_12_LEN = 17914; // 4 +static const uint64_t SH_FLD_RESERVED_1_2 = 17915; // 55 +static const uint64_t SH_FLD_RESERVED_1_2_LEN = 17916; // 55 +static const uint64_t SH_FLD_RESERVED_1_3 = 17917; // 3 +static const uint64_t SH_FLD_RESERVED_1_3_LEN = 17918; // 3 +static const uint64_t SH_FLD_RESERVED_1_5 = 17919; // 1 +static const uint64_t SH_FLD_RESERVED_1_5_LEN = 17920; // 1 +static const uint64_t SH_FLD_RESERVED_1_7 = 17921; // 3 +static const uint64_t SH_FLD_RESERVED_1_7_LEN = 17922; // 3 +static const uint64_t SH_FLD_RESERVED_2 = 17923; // 6 +static const uint64_t SH_FLD_RESERVED_20 = 17924; // 6 +static const uint64_t SH_FLD_RESERVED_20_31 = 17925; // 1 +static const uint64_t SH_FLD_RESERVED_20_31_LEN = 17926; // 1 +static const uint64_t SH_FLD_RESERVED_20_LEN = 17927; // 1 +static const uint64_t SH_FLD_RESERVED_21 = 17928; // 8 +static const uint64_t SH_FLD_RESERVED_21_31 = 17929; // 1 +static const uint64_t SH_FLD_RESERVED_21_31_LEN = 17930; // 1 +static const uint64_t SH_FLD_RESERVED_22C = 17931; // 43 +static const uint64_t SH_FLD_RESERVED_22_23 = 17932; // 1 +static const uint64_t SH_FLD_RESERVED_22_23_LEN = 17933; // 1 +static const uint64_t SH_FLD_RESERVED_22_31 = 17934; // 1 +static const uint64_t SH_FLD_RESERVED_22_31_LEN = 17935; // 1 +static const uint64_t SH_FLD_RESERVED_23 = 17936; // 4 +static const uint64_t SH_FLD_RESERVED_23C = 17937; // 43 +static const uint64_t SH_FLD_RESERVED_23_26 = 17938; // 8 +static const uint64_t SH_FLD_RESERVED_23_26_LEN = 17939; // 8 +static const uint64_t SH_FLD_RESERVED_23_63 = 17940; // 2 +static const uint64_t SH_FLD_RESERVED_23_63_LEN = 17941; // 2 +static const uint64_t SH_FLD_RESERVED_24 = 17942; // 5 +static const uint64_t SH_FLD_RESERVED_24_25 = 17943; // 7 +static const uint64_t SH_FLD_RESERVED_24_25_LEN = 17944; // 7 +static const uint64_t SH_FLD_RESERVED_24_26 = 17945; // 3 +static const uint64_t SH_FLD_RESERVED_24_26_LEN = 17946; // 3 +static const uint64_t SH_FLD_RESERVED_24_29 = 17947; // 1 +static const uint64_t SH_FLD_RESERVED_24_29_LEN = 17948; // 1 +static const uint64_t SH_FLD_RESERVED_24_31 = 17949; // 1 +static const uint64_t SH_FLD_RESERVED_24_31_LEN = 17950; // 1 +static const uint64_t SH_FLD_RESERVED_24_LEN = 17951; // 1 +static const uint64_t SH_FLD_RESERVED_25 = 17952; // 13 +static const uint64_t SH_FLD_RESERVED_25_26 = 17953; // 3 +static const uint64_t SH_FLD_RESERVED_25_26_LEN = 17954; // 3 +static const uint64_t SH_FLD_RESERVED_25_33 = 17955; // 8 +static const uint64_t SH_FLD_RESERVED_25_33_LEN = 17956; // 8 +static const uint64_t SH_FLD_RESERVED_26_49 = 17957; // 2 +static const uint64_t SH_FLD_RESERVED_26_49_LEN = 17958; // 2 +static const uint64_t SH_FLD_RESERVED_27 = 17959; // 1 +static const uint64_t SH_FLD_RESERVED_27_29 = 17960; // 1 +static const uint64_t SH_FLD_RESERVED_27_29_LEN = 17961; // 1 +static const uint64_t SH_FLD_RESERVED_27_31 = 17962; // 1 +static const uint64_t SH_FLD_RESERVED_27_31_LEN = 17963; // 1 +static const uint64_t SH_FLD_RESERVED_28 = 17964; // 5 +static const uint64_t SH_FLD_RESERVED_28_31 = 17965; // 65 +static const uint64_t SH_FLD_RESERVED_28_31_LEN = 17966; // 65 +static const uint64_t SH_FLD_RESERVED_28_LEN = 17967; // 2 +static const uint64_t SH_FLD_RESERVED_29_30 = 17968; // 8 +static const uint64_t SH_FLD_RESERVED_29_30_LEN = 17969; // 8 +static const uint64_t SH_FLD_RESERVED_29_31 = 17970; // 6 +static const uint64_t SH_FLD_RESERVED_29_31_LEN = 17971; // 6 +static const uint64_t SH_FLD_RESERVED_2E = 17972; // 43 +static const uint64_t SH_FLD_RESERVED_2_3 = 17973; // 3 +static const uint64_t SH_FLD_RESERVED_2_3_LEN = 17974; // 3 +static const uint64_t SH_FLD_RESERVED_2_9 = 17975; // 25 +static const uint64_t SH_FLD_RESERVED_2_9_LEN = 17976; // 25 +static const uint64_t SH_FLD_RESERVED_2_LEN = 17977; // 2 +static const uint64_t SH_FLD_RESERVED_3 = 17978; // 11 +static const uint64_t SH_FLD_RESERVED_30 = 17979; // 1 +static const uint64_t SH_FLD_RESERVED_30C = 17980; // 43 +static const uint64_t SH_FLD_RESERVED_30_31 = 17981; // 13 +static const uint64_t SH_FLD_RESERVED_30_31_LEN = 17982; // 13 +static const uint64_t SH_FLD_RESERVED_31 = 17983; // 3 +static const uint64_t SH_FLD_RESERVED_31C = 17984; // 43 +static const uint64_t SH_FLD_RESERVED_31_LEN = 17985; // 2 +static const uint64_t SH_FLD_RESERVED_32 = 17986; // 28 +static const uint64_t SH_FLD_RESERVED_32_33 = 17987; // 6 +static const uint64_t SH_FLD_RESERVED_32_33_LEN = 17988; // 6 +static const uint64_t SH_FLD_RESERVED_32_34 = 17989; // 8 +static const uint64_t SH_FLD_RESERVED_32_34_LEN = 17990; // 8 +static const uint64_t SH_FLD_RESERVED_32_35 = 17991; // 3 +static const uint64_t SH_FLD_RESERVED_32_35_LEN = 17992; // 3 +static const uint64_t SH_FLD_RESERVED_32_39 = 17993; // 3 +static const uint64_t SH_FLD_RESERVED_32_39_LEN = 17994; // 3 +static const uint64_t SH_FLD_RESERVED_32_40 = 17995; // 10 +static const uint64_t SH_FLD_RESERVED_32_40_LEN = 17996; // 10 +static const uint64_t SH_FLD_RESERVED_32_44 = 17997; // 3 +static const uint64_t SH_FLD_RESERVED_32_44_LEN = 17998; // 3 +static const uint64_t SH_FLD_RESERVED_32_63 = 17999; // 8 +static const uint64_t SH_FLD_RESERVED_32_63_LEN = 18000; // 8 +static const uint64_t SH_FLD_RESERVED_33 = 18001; // 2 +static const uint64_t SH_FLD_RESERVED_33A = 18002; // 43 +static const uint64_t SH_FLD_RESERVED_33_39 = 18003; // 1 +static const uint64_t SH_FLD_RESERVED_33_39_LEN = 18004; // 1 +static const uint64_t SH_FLD_RESERVED_33_43 = 18005; // 1 +static const uint64_t SH_FLD_RESERVED_33_43_LEN = 18006; // 1 +static const uint64_t SH_FLD_RESERVED_33_63 = 18007; // 1 +static const uint64_t SH_FLD_RESERVED_33_63_LEN = 18008; // 1 +static const uint64_t SH_FLD_RESERVED_34 = 18009; // 1 +static const uint64_t SH_FLD_RESERVED_34A = 18010; // 43 +static const uint64_t SH_FLD_RESERVED_35 = 18011; // 1 +static const uint64_t SH_FLD_RESERVED_35A = 18012; // 43 +static const uint64_t SH_FLD_RESERVED_36_37 = 18013; // 8 +static const uint64_t SH_FLD_RESERVED_36_37_LEN = 18014; // 8 +static const uint64_t SH_FLD_RESERVED_36_39 = 18015; // 1 +static const uint64_t SH_FLD_RESERVED_36_39_LEN = 18016; // 1 +static const uint64_t SH_FLD_RESERVED_37 = 18017; // 1 +static const uint64_t SH_FLD_RESERVED_37_45 = 18018; // 1 +static const uint64_t SH_FLD_RESERVED_37_45_LEN = 18019; // 1 +static const uint64_t SH_FLD_RESERVED_37_56 = 18020; // 8 +static const uint64_t SH_FLD_RESERVED_37_56_LEN = 18021; // 8 +static const uint64_t SH_FLD_RESERVED_38 = 18022; // 1 +static const uint64_t SH_FLD_RESERVED_38A = 18023; // 43 +static const uint64_t SH_FLD_RESERVED_38_39 = 18024; // 24 +static const uint64_t SH_FLD_RESERVED_38_39_LEN = 18025; // 24 +static const uint64_t SH_FLD_RESERVED_38_41 = 18026; // 1 +static const uint64_t SH_FLD_RESERVED_38_41_LEN = 18027; // 1 +static const uint64_t SH_FLD_RESERVED_38_63 = 18028; // 2 +static const uint64_t SH_FLD_RESERVED_38_63_LEN = 18029; // 2 +static const uint64_t SH_FLD_RESERVED_39 = 18030; // 12 +static const uint64_t SH_FLD_RESERVED_39A = 18031; // 43 +static const uint64_t SH_FLD_RESERVED_39_47 = 18032; // 64 +static const uint64_t SH_FLD_RESERVED_39_47_LEN = 18033; // 64 +static const uint64_t SH_FLD_RESERVED_3E = 18034; // 43 +static const uint64_t SH_FLD_RESERVED_4 = 18035; // 12 +static const uint64_t SH_FLD_RESERVED_40 = 18036; // 35 +static const uint64_t SH_FLD_RESERVED_40_41 = 18037; // 9 +static const uint64_t SH_FLD_RESERVED_40_41_LEN = 18038; // 9 +static const uint64_t SH_FLD_RESERVED_40_42 = 18039; // 1 +static const uint64_t SH_FLD_RESERVED_40_42_LEN = 18040; // 1 +static const uint64_t SH_FLD_RESERVED_40_47 = 18041; // 2 +static const uint64_t SH_FLD_RESERVED_40_47_LEN = 18042; // 2 +static const uint64_t SH_FLD_RESERVED_40_51 = 18043; // 1 +static const uint64_t SH_FLD_RESERVED_40_51_LEN = 18044; // 1 +static const uint64_t SH_FLD_RESERVED_41 = 18045; // 2 +static const uint64_t SH_FLD_RESERVED_41_42 = 18046; // 2 +static const uint64_t SH_FLD_RESERVED_41_42_LEN = 18047; // 2 +static const uint64_t SH_FLD_RESERVED_41_43 = 18048; // 2 +static const uint64_t SH_FLD_RESERVED_41_43_LEN = 18049; // 2 +static const uint64_t SH_FLD_RESERVED_41_63 = 18050; // 8 +static const uint64_t SH_FLD_RESERVED_41_63_LEN = 18051; // 8 +static const uint64_t SH_FLD_RESERVED_42 = 18052; // 2 +static const uint64_t SH_FLD_RESERVED_42A = 18053; // 43 +static const uint64_t SH_FLD_RESERVED_42C = 18054; // 43 +static const uint64_t SH_FLD_RESERVED_42_43 = 18055; // 12 +static const uint64_t SH_FLD_RESERVED_42_43_LEN = 18056; // 12 +static const uint64_t SH_FLD_RESERVED_42_47 = 18057; // 8 +static const uint64_t SH_FLD_RESERVED_42_47_LEN = 18058; // 8 +static const uint64_t SH_FLD_RESERVED_43 = 18059; // 2 +static const uint64_t SH_FLD_RESERVED_43A = 18060; // 43 +static const uint64_t SH_FLD_RESERVED_43C = 18061; // 43 +static const uint64_t SH_FLD_RESERVED_43_44 = 18062; // 2 +static const uint64_t SH_FLD_RESERVED_43_44_LEN = 18063; // 2 +static const uint64_t SH_FLD_RESERVED_44 = 18064; // 1 +static const uint64_t SH_FLD_RESERVED_44_46 = 18065; // 1 +static const uint64_t SH_FLD_RESERVED_44_46_LEN = 18066; // 1 +static const uint64_t SH_FLD_RESERVED_44_47 = 18067; // 1 +static const uint64_t SH_FLD_RESERVED_44_47_LEN = 18068; // 1 +static const uint64_t SH_FLD_RESERVED_45 = 18069; // 1 +static const uint64_t SH_FLD_RESERVED_46 = 18070; // 1 +static const uint64_t SH_FLD_RESERVED_47 = 18071; // 1 +static const uint64_t SH_FLD_RESERVED_47_48 = 18072; // 2 +static const uint64_t SH_FLD_RESERVED_47_48_LEN = 18073; // 2 +static const uint64_t SH_FLD_RESERVED_47_51 = 18074; // 1 +static const uint64_t SH_FLD_RESERVED_47_51_LEN = 18075; // 1 +static const uint64_t SH_FLD_RESERVED_48 = 18076; // 27 +static const uint64_t SH_FLD_RESERVED_48_49 = 18077; // 3 +static const uint64_t SH_FLD_RESERVED_48_49_LEN = 18078; // 3 +static const uint64_t SH_FLD_RESERVED_48_50 = 18079; // 2 +static const uint64_t SH_FLD_RESERVED_48_50_LEN = 18080; // 2 +static const uint64_t SH_FLD_RESERVED_48_63 = 18081; // 10 +static const uint64_t SH_FLD_RESERVED_48_63_LEN = 18082; // 10 +static const uint64_t SH_FLD_RESERVED_49_63 = 18083; // 8 +static const uint64_t SH_FLD_RESERVED_49_63_LEN = 18084; // 8 +static const uint64_t SH_FLD_RESERVED_4_15 = 18085; // 30 +static const uint64_t SH_FLD_RESERVED_4_15_LEN = 18086; // 30 +static const uint64_t SH_FLD_RESERVED_4_5 = 18087; // 1 +static const uint64_t SH_FLD_RESERVED_4_5_LEN = 18088; // 1 +static const uint64_t SH_FLD_RESERVED_4_7 = 18089; // 32 +static const uint64_t SH_FLD_RESERVED_4_7_LEN = 18090; // 32 +static const uint64_t SH_FLD_RESERVED_4_LEN = 18091; // 3 +static const uint64_t SH_FLD_RESERVED_5 = 18092; // 4 +static const uint64_t SH_FLD_RESERVED_50 = 18093; // 4 +static const uint64_t SH_FLD_RESERVED_50_51 = 18094; // 3 +static const uint64_t SH_FLD_RESERVED_50_51_LEN = 18095; // 3 +static const uint64_t SH_FLD_RESERVED_50_63 = 18096; // 1 +static const uint64_t SH_FLD_RESERVED_50_63_LEN = 18097; // 1 +static const uint64_t SH_FLD_RESERVED_51 = 18098; // 17 +static const uint64_t SH_FLD_RESERVED_51_63 = 18099; // 9 +static const uint64_t SH_FLD_RESERVED_51_63_LEN = 18100; // 9 +static const uint64_t SH_FLD_RESERVED_52 = 18101; // 38 +static const uint64_t SH_FLD_RESERVED_52_55 = 18102; // 64 +static const uint64_t SH_FLD_RESERVED_52_55_LEN = 18103; // 64 +static const uint64_t SH_FLD_RESERVED_52_56 = 18104; // 8 +static const uint64_t SH_FLD_RESERVED_52_56_LEN = 18105; // 8 +static const uint64_t SH_FLD_RESERVED_53_54 = 18106; // 8 +static const uint64_t SH_FLD_RESERVED_53_54_LEN = 18107; // 8 +static const uint64_t SH_FLD_RESERVED_53_58 = 18108; // 2 +static const uint64_t SH_FLD_RESERVED_53_58_LEN = 18109; // 2 +static const uint64_t SH_FLD_RESERVED_53_63 = 18110; // 1 +static const uint64_t SH_FLD_RESERVED_53_63_LEN = 18111; // 1 +static const uint64_t SH_FLD_RESERVED_54_63 = 18112; // 8 +static const uint64_t SH_FLD_RESERVED_54_63_LEN = 18113; // 8 +static const uint64_t SH_FLD_RESERVED_55_63 = 18114; // 8 +static const uint64_t SH_FLD_RESERVED_55_63_LEN = 18115; // 8 +static const uint64_t SH_FLD_RESERVED_56 = 18116; // 32 +static const uint64_t SH_FLD_RESERVED_56_57 = 18117; // 2 +static const uint64_t SH_FLD_RESERVED_56_57_LEN = 18118; // 2 +static const uint64_t SH_FLD_RESERVED_56_58 = 18119; // 5 +static const uint64_t SH_FLD_RESERVED_56_58_LEN = 18120; // 5 +static const uint64_t SH_FLD_RESERVED_56_59 = 18121; // 5 +static const uint64_t SH_FLD_RESERVED_56_59_LEN = 18122; // 5 +static const uint64_t SH_FLD_RESERVED_56_63 = 18123; // 18 +static const uint64_t SH_FLD_RESERVED_56_63_LEN = 18124; // 18 +static const uint64_t SH_FLD_RESERVED_57 = 18125; // 25 +static const uint64_t SH_FLD_RESERVED_57_58 = 18126; // 2 +static const uint64_t SH_FLD_RESERVED_57_58_LEN = 18127; // 2 +static const uint64_t SH_FLD_RESERVED_57_59 = 18128; // 7 +static const uint64_t SH_FLD_RESERVED_57_59_LEN = 18129; // 7 +static const uint64_t SH_FLD_RESERVED_58 = 18130; // 1 +static const uint64_t SH_FLD_RESERVED_58_59 = 18131; // 1 +static const uint64_t SH_FLD_RESERVED_58_59_LEN = 18132; // 1 +static const uint64_t SH_FLD_RESERVED_58_63 = 18133; // 8 +static const uint64_t SH_FLD_RESERVED_58_63_LEN = 18134; // 8 +static const uint64_t SH_FLD_RESERVED_59 = 18135; // 1 +static const uint64_t SH_FLD_RESERVED_59_63 = 18136; // 8 +static const uint64_t SH_FLD_RESERVED_59_63_LEN = 18137; // 8 +static const uint64_t SH_FLD_RESERVED_5_15 = 18138; // 1 +static const uint64_t SH_FLD_RESERVED_5_15_LEN = 18139; // 1 +static const uint64_t SH_FLD_RESERVED_5_7 = 18140; // 1 +static const uint64_t SH_FLD_RESERVED_5_7_LEN = 18141; // 1 +static const uint64_t SH_FLD_RESERVED_5_LEN = 18142; // 3 +static const uint64_t SH_FLD_RESERVED_6 = 18143; // 2 +static const uint64_t SH_FLD_RESERVED_60 = 18144; // 24 +static const uint64_t SH_FLD_RESERVED_60_63 = 18145; // 9 +static const uint64_t SH_FLD_RESERVED_60_63_LEN = 18146; // 9 +static const uint64_t SH_FLD_RESERVED_61 = 18147; // 24 +static const uint64_t SH_FLD_RESERVED_61_63 = 18148; // 18 +static const uint64_t SH_FLD_RESERVED_61_63_LEN = 18149; // 18 +static const uint64_t SH_FLD_RESERVED_62 = 18150; // 1 +static const uint64_t SH_FLD_RESERVED_62_63 = 18151; // 20 +static const uint64_t SH_FLD_RESERVED_62_63_LEN = 18152; // 20 +static const uint64_t SH_FLD_RESERVED_63 = 18153; // 20 +static const uint64_t SH_FLD_RESERVED_6C = 18154; // 43 +static const uint64_t SH_FLD_RESERVED_6E = 18155; // 43 +static const uint64_t SH_FLD_RESERVED_6_14 = 18156; // 2 +static const uint64_t SH_FLD_RESERVED_6_14_LEN = 18157; // 2 +static const uint64_t SH_FLD_RESERVED_6_7 = 18158; // 3 +static const uint64_t SH_FLD_RESERVED_6_7_LEN = 18159; // 3 +static const uint64_t SH_FLD_RESERVED_6_8 = 18160; // 12 +static const uint64_t SH_FLD_RESERVED_6_8_LEN = 18161; // 12 +static const uint64_t SH_FLD_RESERVED_6_9 = 18162; // 1 +static const uint64_t SH_FLD_RESERVED_6_9_LEN = 18163; // 1 +static const uint64_t SH_FLD_RESERVED_7 = 18164; // 25 +static const uint64_t SH_FLD_RESERVED_7C = 18165; // 43 +static const uint64_t SH_FLD_RESERVED_7_8 = 18166; // 1 +static const uint64_t SH_FLD_RESERVED_7_8_LEN = 18167; // 1 +static const uint64_t SH_FLD_RESERVED_7_9 = 18168; // 8 +static const uint64_t SH_FLD_RESERVED_7_9_LEN = 18169; // 8 +static const uint64_t SH_FLD_RESERVED_7_LEN = 18170; // 1 +static const uint64_t SH_FLD_RESERVED_8 = 18171; // 6 +static const uint64_t SH_FLD_RESERVED_8_10 = 18172; // 39 +static const uint64_t SH_FLD_RESERVED_8_10_LEN = 18173; // 39 +static const uint64_t SH_FLD_RESERVED_8_11 = 18174; // 25 +static const uint64_t SH_FLD_RESERVED_8_11_LEN = 18175; // 25 +static const uint64_t SH_FLD_RESERVED_8_9 = 18176; // 6 +static const uint64_t SH_FLD_RESERVED_8_9_LEN = 18177; // 6 +static const uint64_t SH_FLD_RESERVED_8_LEN = 18178; // 1 +static const uint64_t SH_FLD_RESERVED_9 = 18179; // 27 +static const uint64_t SH_FLD_RESERVED_9_15 = 18180; // 2 +static const uint64_t SH_FLD_RESERVED_9_15_LEN = 18181; // 2 +static const uint64_t SH_FLD_RESERVED_9_26 = 18182; // 1 +static const uint64_t SH_FLD_RESERVED_9_26_LEN = 18183; // 1 +static const uint64_t SH_FLD_RESERVED_9_27 = 18184; // 1 +static const uint64_t SH_FLD_RESERVED_9_27_LEN = 18185; // 1 +static const uint64_t SH_FLD_RESERVED_BIT10 = 18186; // 2 +static const uint64_t SH_FLD_RESERVED_BIT15 = 18187; // 98 +static const uint64_t SH_FLD_RESERVED_BIT17 = 18188; // 98 +static const uint64_t SH_FLD_RESERVED_BIT19 = 18189; // 98 +static const uint64_t SH_FLD_RESERVED_BIT20 = 18190; // 98 +static const uint64_t SH_FLD_RESERVED_BIT21 = 18191; // 98 +static const uint64_t SH_FLD_RESERVED_BIT22 = 18192; // 98 +static const uint64_t SH_FLD_RESERVED_BIT23 = 18193; // 98 +static const uint64_t SH_FLD_RESERVED_BIT25 = 18194; // 96 +static const uint64_t SH_FLD_RESERVED_BIT36 = 18195; // 96 +static const uint64_t SH_FLD_RESERVED_BIT37 = 18196; // 96 +static const uint64_t SH_FLD_RESERVED_BIT38 = 18197; // 96 +static const uint64_t SH_FLD_RESERVED_BIT39 = 18198; // 96 +static const uint64_t SH_FLD_RESERVED_BIT52 = 18199; // 96 +static const uint64_t SH_FLD_RESERVED_BIT53 = 18200; // 96 +static const uint64_t SH_FLD_RESERVED_BIT54 = 18201; // 96 +static const uint64_t SH_FLD_RESERVED_BIT55 = 18202; // 96 +static const uint64_t SH_FLD_RESERVED_BIT63 = 18203; // 96 +static const uint64_t SH_FLD_RESERVED_FOR_ADDRESS = 18204; // 1 +static const uint64_t SH_FLD_RESERVED_FOR_ADDRESS_LEN = 18205; // 1 +static const uint64_t SH_FLD_RESERVED_FOR_CONFIGS = 18206; // 1 +static const uint64_t SH_FLD_RESERVED_FOR_CONFIGS_LEN = 18207; // 1 +static const uint64_t SH_FLD_RESERVED_FOR_ERRS = 18208; // 1 +static const uint64_t SH_FLD_RESERVED_FOR_ERRS_LEN = 18209; // 1 +static const uint64_t SH_FLD_RESERVED_ID_55C = 18210; // 43 +static const uint64_t SH_FLD_RESERVED_ID_61C = 18211; // 43 +static const uint64_t SH_FLD_RESERVED_ID_62C = 18212; // 43 +static const uint64_t SH_FLD_RESERVED_ID_63C = 18213; // 43 +static const uint64_t SH_FLD_RESERVED_LAST_LT = 18214; // 43 +static const uint64_t SH_FLD_RESERVED_LEN = 18215; // 104 +static const uint64_t SH_FLD_RESERVED_LT = 18216; // 43 +static const uint64_t SH_FLD_RESERVED_LT_LEN = 18217; // 43 +static const uint64_t SH_FLD_RESERVED_RING_LOCKING = 18218; // 43 +static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_35C = 18219; // 43 +static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_36C = 18220; // 43 +static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_37C = 18221; // 43 +static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_38C = 18222; // 43 +static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_39C = 18223; // 43 +static const uint64_t SH_FLD_RESERVE_11 = 18224; // 2 +static const uint64_t SH_FLD_RESERVE_39_52 = 18225; // 2 +static const uint64_t SH_FLD_RESERVE_39_52_LEN = 18226; // 2 +static const uint64_t SH_FLD_RESERVE_5_15 = 18227; // 2 +static const uint64_t SH_FLD_RESERVE_5_15_LEN = 18228; // 2 +static const uint64_t SH_FLD_RESET = 18229; // 27 +static const uint64_t SH_FLD_RESETMODE = 18230; // 9 +static const uint64_t SH_FLD_RESET_0 = 18231; // 8 +static const uint64_t SH_FLD_RESET_0_7 = 18232; // 1 +static const uint64_t SH_FLD_RESET_0_7_LEN = 18233; // 1 +static const uint64_t SH_FLD_RESET_1 = 18234; // 8 +static const uint64_t SH_FLD_RESET_C2TIMER_ON_C1 = 18235; // 86 +static const uint64_t SH_FLD_RESET_C3_ON_C0 = 18236; // 86 +static const uint64_t SH_FLD_RESET_C3_SELECT = 18237; // 86 +static const uint64_t SH_FLD_RESET_C3_SELECT_LEN = 18238; // 86 +static const uint64_t SH_FLD_RESET_EP = 18239; // 43 +static const uint64_t SH_FLD_RESET_ERROR_LOGS = 18240; // 2 +static const uint64_t SH_FLD_RESET_ERR_RPT = 18241; // 8 +static const uint64_t SH_FLD_RESET_FWD_PROG = 18242; // 24 +static const uint64_t SH_FLD_RESET_IMPRECISE_QERR = 18243; // 12 +static const uint64_t SH_FLD_RESET_KEEPER = 18244; // 62 +static const uint64_t SH_FLD_RESET_LBUS_REQUEST = 18245; // 2 +static const uint64_t SH_FLD_RESET_LEN = 18246; // 2 +static const uint64_t SH_FLD_RESET_MODE = 18247; // 5 +static const uint64_t SH_FLD_RESET_ON_PARITY = 18248; // 1 +static const uint64_t SH_FLD_RESET_PIB = 18249; // 1 +static const uint64_t SH_FLD_RESET_RECOVER = 18250; // 8 +static const uint64_t SH_FLD_RESET_SAMPLE_DTS = 18251; // 43 +static const uint64_t SH_FLD_RESET_SAMPLE_PULSE_CNT = 18252; // 43 +static const uint64_t SH_FLD_RESET_STATE_INDICATOR = 18253; // 30 +static const uint64_t SH_FLD_RESET_TOD_STATE = 18254; // 1 +static const uint64_t SH_FLD_RESET_TRAP_CNFG = 18255; // 2 +static const uint64_t SH_FLD_RESET_TRIG_SEL = 18256; // 43 +static const uint64_t SH_FLD_RESET_TRIG_SEL_LEN = 18257; // 43 +static const uint64_t SH_FLD_RESET_TRIP_HISTORY = 18258; // 43 +static const uint64_t SH_FLD_RESID_FE_LEN_0 = 18259; // 2 +static const uint64_t SH_FLD_RESID_FE_LEN_0_LEN = 18260; // 2 +static const uint64_t SH_FLD_RESID_FE_LEN_1 = 18261; // 1 +static const uint64_t SH_FLD_RESID_FE_LEN_1_LEN = 18262; // 1 +static const uint64_t SH_FLD_RESID_FE_LEN_2 = 18263; // 1 +static const uint64_t SH_FLD_RESID_FE_LEN_2_LEN = 18264; // 1 +static const uint64_t SH_FLD_RESID_FE_LEN_3 = 18265; // 1 +static const uint64_t SH_FLD_RESID_FE_LEN_3_LEN = 18266; // 1 +static const uint64_t SH_FLD_RESPONSE = 18267; // 1 +static const uint64_t SH_FLD_RESP_PKT_RCV = 18268; // 2 +static const uint64_t SH_FLD_RESSEL = 18269; // 4 +static const uint64_t SH_FLD_RESULT = 18270; // 2 +static const uint64_t SH_FLD_RESULT_AVAILABLE = 18271; // 2 +static const uint64_t SH_FLD_RESULT_LEN = 18272; // 2 +static const uint64_t SH_FLD_RESULT_VALID = 18273; // 1 +static const uint64_t SH_FLD_RESUME_FROM_PAUSE = 18274; // 2 +static const uint64_t SH_FLD_RETIRE = 18275; // 1 +static const uint64_t SH_FLD_RETRAIN_PERCAL_SW = 18276; // 8 +static const uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT = 18277; // 4 +static const uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT_LEN = 18278; // 4 +static const uint64_t SH_FLD_RETRY_VALUE = 18279; // 1 +static const uint64_t SH_FLD_RETRY_VALUE_LEN = 18280; // 1 +static const uint64_t SH_FLD_RETURNQ_ERR = 18281; // 4 +static const uint64_t SH_FLD_RETURN_GOOD_ON_COMP = 18282; // 24 +static const uint64_t SH_FLD_RG_CERR_BIT10 = 18283; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT11 = 18284; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT12 = 18285; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT13 = 18286; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT4 = 18287; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT5 = 18288; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT6 = 18289; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT7 = 18290; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT8 = 18291; // 1 +static const uint64_t SH_FLD_RG_CERR_BIT9 = 18292; // 1 +static const uint64_t SH_FLD_RG_CERR_RESET = 18293; // 1 +static const uint64_t SH_FLD_RG_CERR_UNUSED_BITS = 18294; // 1 +static const uint64_t SH_FLD_RG_CERR_UNUSED_BITS_LEN = 18295; // 1 +static const uint64_t SH_FLD_RG_ECC_CE_ERROR = 18296; // 2 +static const uint64_t SH_FLD_RG_ECC_SUE_ERROR = 18297; // 2 +static const uint64_t SH_FLD_RG_ECC_UE_ERROR = 18298; // 2 +static const uint64_t SH_FLD_RG_LOGIC_HW_ERROR = 18299; // 2 +static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI = 18300; // 1 +static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN = 18301; // 1 +static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO = 18302; // 1 +static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN = 18303; // 1 +static const uint64_t SH_FLD_RG_TRACE_INT_DATA_HI = 18304; // 1 +static const uint64_t SH_FLD_RG_TRACE_INT_DATA_LO = 18305; // 1 +static const uint64_t SH_FLD_RG_TRACE_INT_TRIG_01 = 18306; // 1 +static const uint64_t SH_FLD_RG_TRACE_INT_TRIG_23 = 18307; // 1 +static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01 = 18308; // 1 +static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN = 18309; // 1 +static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23 = 18310; // 1 +static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN = 18311; // 1 +static const uint64_t SH_FLD_RI = 18312; // 96 +static const uint64_t SH_FLD_RIC = 18313; // 8 +static const uint64_t SH_FLD_RIC_LEN = 18314; // 8 +static const uint64_t SH_FLD_RINGS = 18315; // 43 +static const uint64_t SH_FLD_RINGS_LEN = 18316; // 43 +static const uint64_t SH_FLD_RING_LOCKING = 18317; // 43 +static const uint64_t SH_FLD_RL = 18318; // 96 +static const uint64_t SH_FLD_RL_LEN = 18319; // 96 +static const uint64_t SH_FLD_RMA_BAR = 18320; // 1 +static const uint64_t SH_FLD_RMA_BAR_LEN = 18321; // 1 +static const uint64_t SH_FLD_RMA_BAR_MASK = 18322; // 1 +static const uint64_t SH_FLD_RMA_BAR_MASK_LEN = 18323; // 1 +static const uint64_t SH_FLD_RMT_FIRST_GRPSCAN_ENA = 18324; // 1 +static const uint64_t SH_FLD_RMW_BUF_THRESH = 18325; // 8 +static const uint64_t SH_FLD_RMW_BUF_THRESH_LEN = 18326; // 8 +static const uint64_t SH_FLD_RND_BACKOFF_ENABLE = 18327; // 2 +static const uint64_t SH_FLD_RNG0_BIST_FAIL = 18328; // 1 +static const uint64_t SH_FLD_RNG0_FAIL = 18329; // 1 +static const uint64_t SH_FLD_RNG0_INJ_CONTINOUS_ERROR = 18330; // 1 +static const uint64_t SH_FLD_RNG1_BIST_FAIL = 18331; // 1 +static const uint64_t SH_FLD_RNG1_FAIL = 18332; // 1 +static const uint64_t SH_FLD_RNG1_INJ_CONTINOUS_ERROR = 18333; // 1 +static const uint64_t SH_FLD_RNG_CNTRL_LOGIC_ERR = 18334; // 1 +static const uint64_t SH_FLD_RNG_FIRST_FAIL = 18335; // 1 +static const uint64_t SH_FLD_RNG_SECOND_FAIL = 18336; // 1 +static const uint64_t SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD = 18337; // 2 +static const uint64_t SH_FLD_RNW = 18338; // 15 +static const uint64_t SH_FLD_ROOT_CTRL0_COPY_REG = 18339; // 1 +static const uint64_t SH_FLD_ROOT_CTRL0_COPY_REG_LEN = 18340; // 1 +static const uint64_t SH_FLD_ROOT_CTRL1_COPY_REG = 18341; // 1 +static const uint64_t SH_FLD_ROOT_CTRL1_COPY_REG_LEN = 18342; // 1 +static const uint64_t SH_FLD_ROOT_CTRL2_COPY_REG = 18343; // 1 +static const uint64_t SH_FLD_ROOT_CTRL2_COPY_REG_LEN = 18344; // 1 +static const uint64_t SH_FLD_ROOT_CTRL3_COPY_REG = 18345; // 1 +static const uint64_t SH_FLD_ROOT_CTRL3_COPY_REG_LEN = 18346; // 1 +static const uint64_t SH_FLD_ROOT_CTRL4_COPY_REG = 18347; // 1 +static const uint64_t SH_FLD_ROOT_CTRL4_COPY_REG_LEN = 18348; // 1 +static const uint64_t SH_FLD_ROOT_CTRL5_COPY_REG = 18349; // 1 +static const uint64_t SH_FLD_ROOT_CTRL5_COPY_REG_LEN = 18350; // 1 +static const uint64_t SH_FLD_ROOT_CTRL6_COPY_REG = 18351; // 1 +static const uint64_t SH_FLD_ROOT_CTRL6_COPY_REG_LEN = 18352; // 1 +static const uint64_t SH_FLD_ROOT_CTRL7_COPY_REG = 18353; // 1 +static const uint64_t SH_FLD_ROOT_CTRL7_COPY_REG_LEN = 18354; // 1 +static const uint64_t SH_FLD_ROOT_CTRL8_COPY_REG = 18355; // 1 +static const uint64_t SH_FLD_ROOT_CTRL8_COPY_REG_LEN = 18356; // 1 +static const uint64_t SH_FLD_ROT90 = 18357; // 48 +static const uint64_t SH_FLD_ROT90_LEN = 18358; // 48 +static const uint64_t SH_FLD_ROTA = 18359; // 48 +static const uint64_t SH_FLD_ROTA_LEN = 18360; // 48 +static const uint64_t SH_FLD_ROTB = 18361; // 48 +static const uint64_t SH_FLD_ROTB_LEN = 18362; // 48 +static const uint64_t SH_FLD_ROUTE_CHECKSTOP = 18363; // 2 +static const uint64_t SH_FLD_RP1 = 18364; // 24 +static const uint64_t SH_FLD_RP1_LEN = 18365; // 24 +static const uint64_t SH_FLD_RP2 = 18366; // 24 +static const uint64_t SH_FLD_RP2_LEN = 18367; // 24 +static const uint64_t SH_FLD_RP3 = 18368; // 24 +static const uint64_t SH_FLD_RP3_LEN = 18369; // 24 +static const uint64_t SH_FLD_RP4 = 18370; // 24 +static const uint64_t SH_FLD_RP4_LEN = 18371; // 24 +static const uint64_t SH_FLD_RP5 = 18372; // 24 +static const uint64_t SH_FLD_RP5_LEN = 18373; // 24 +static const uint64_t SH_FLD_RP6 = 18374; // 24 +static const uint64_t SH_FLD_RP6_LEN = 18375; // 24 +static const uint64_t SH_FLD_RP7 = 18376; // 24 +static const uint64_t SH_FLD_RP7_LEN = 18377; // 24 +static const uint64_t SH_FLD_RPR_TX_LD_CNTLS_TIMEOUT_SEL = 18378; // 4 +static const uint64_t SH_FLD_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN = 18379; // 4 +static const uint64_t SH_FLD_RPT = 18380; // 2 +static const uint64_t SH_FLD_RPT1 = 18381; // 1 +static const uint64_t SH_FLD_RPT1_LEN = 18382; // 1 +static const uint64_t SH_FLD_RPTHANG_SELECT = 18383; // 4 +static const uint64_t SH_FLD_RPTHANG_SELECT_LEN = 18384; // 4 +static const uint64_t SH_FLD_RPT_LEN = 18385; // 2 +static const uint64_t SH_FLD_RRDM_DLY = 18386; // 8 +static const uint64_t SH_FLD_RRDM_DLY_LEN = 18387; // 8 +static const uint64_t SH_FLD_RRN_BYPASS_ENABLE = 18388; // 1 +static const uint64_t SH_FLD_RRN_DATA = 18389; // 1 +static const uint64_t SH_FLD_RRN_DATA_LEN = 18390; // 1 +static const uint64_t SH_FLD_RROP_DLY = 18391; // 8 +static const uint64_t SH_FLD_RROP_DLY_LEN = 18392; // 8 +static const uint64_t SH_FLD_RRQ_CAPACITY_LIMIT = 18393; // 4 +static const uint64_t SH_FLD_RRQ_CAPACITY_LIMIT_LEN = 18394; // 4 +static const uint64_t SH_FLD_RRQ_HANG = 18395; // 8 +static const uint64_t SH_FLD_RRQ_PE = 18396; // 8 +static const uint64_t SH_FLD_RRSBG_DLY = 18397; // 8 +static const uint64_t SH_FLD_RRSBG_DLY_LEN = 18398; // 8 +static const uint64_t SH_FLD_RRSMDR_DLY = 18399; // 8 +static const uint64_t SH_FLD_RRSMDR_DLY_LEN = 18400; // 8 +static const uint64_t SH_FLD_RRSMSR_DLY = 18401; // 8 +static const uint64_t SH_FLD_RRSMSR_DLY_LEN = 18402; // 8 +static const uint64_t SH_FLD_RSB_BUS_LOGIC_ERROR = 18403; // 30 +static const uint64_t SH_FLD_RSB_DBG_FATAL_ERROR = 18404; // 30 +static const uint64_t SH_FLD_RSB_DBG_INF_ERROR = 18405; // 30 +static const uint64_t SH_FLD_RSB_ERR_FATAL_ERROR = 18406; // 30 +static const uint64_t SH_FLD_RSB_ERR_INF_ERROR = 18407; // 30 +static const uint64_t SH_FLD_RSB_FDA_FATAL_ERROR = 18408; // 30 +static const uint64_t SH_FLD_RSB_FDA_INF_ERROR = 18409; // 30 +static const uint64_t SH_FLD_RSB_FDB_FATAL_ERROR = 18410; // 30 +static const uint64_t SH_FLD_RSB_FDB_INF_ERROR = 18411; // 30 +static const uint64_t SH_FLD_RSB_PCIE_REQUEST_ACCESS_ERROR = 18412; // 24 +static const uint64_t SH_FLD_RSB_REG_REQUEST_ADDRESS_ERROR = 18413; // 24 +static const uint64_t SH_FLD_RSB_REQUEST_ADDRESS_ERROR = 18414; // 6 +static const uint64_t SH_FLD_RSB_UVI_FATAL_ERROR = 18415; // 30 +static const uint64_t SH_FLD_RSB_UVI_INF_ERROR = 18416; // 30 +static const uint64_t SH_FLD_RSD_AT_MACRO = 18417; // 1 +static const uint64_t SH_FLD_RSD_AT_MACRO_LEN = 18418; // 1 +static const uint64_t SH_FLD_RSD_CRD_AT_MACRO = 18419; // 1 +static const uint64_t SH_FLD_RSD_CRD_AT_MACRO_LEN = 18420; // 1 +static const uint64_t SH_FLD_RSD_CRD_DMA_READ = 18421; // 1 +static const uint64_t SH_FLD_RSD_CRD_DMA_READ_LEN = 18422; // 1 +static const uint64_t SH_FLD_RSD_CRD_DMA_WRITE = 18423; // 1 +static const uint64_t SH_FLD_RSD_CRD_DMA_WRITE_LEN = 18424; // 1 +static const uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD = 18425; // 1 +static const uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 18426; // 1 +static const uint64_t SH_FLD_RSD_CRD_EQ_POST = 18427; // 1 +static const uint64_t SH_FLD_RSD_CRD_EQ_POST_LEN = 18428; // 1 +static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1 = 18429; // 1 +static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1_LEN = 18430; // 1 +static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2 = 18431; // 1 +static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2_LEN = 18432; // 1 +static const uint64_t SH_FLD_RSD_DMA_READ = 18433; // 1 +static const uint64_t SH_FLD_RSD_DMA_READ_LEN = 18434; // 1 +static const uint64_t SH_FLD_RSD_DMA_WRITE = 18435; // 1 +static const uint64_t SH_FLD_RSD_DMA_WRITE_LEN = 18436; // 1 +static const uint64_t SH_FLD_RSD_TCTXT_WRITE = 18437; // 1 +static const uint64_t SH_FLD_RSD_TCTXT_WRITE_LEN = 18438; // 1 +static const uint64_t SH_FLD_RSD_VPC_LD_RMT = 18439; // 1 +static const uint64_t SH_FLD_RSD_VPC_LD_RMT_LEN = 18440; // 1 +static const uint64_t SH_FLD_RSD_VPC_ST_RMT = 18441; // 1 +static const uint64_t SH_FLD_RSD_VPC_ST_RMT_LEN = 18442; // 1 +static const uint64_t SH_FLD_RSD_VPC_ST_RMT_VC = 18443; // 1 +static const uint64_t SH_FLD_RSD_VPC_ST_RMT_VC_LEN = 18444; // 1 +static const uint64_t SH_FLD_RSEL = 18445; // 10 +static const uint64_t SH_FLD_RSEL_LEN = 18446; // 10 +static const uint64_t SH_FLD_RSPOUT_CE_ESR = 18447; // 1 +static const uint64_t SH_FLD_RSPOUT_UE_ESR = 18448; // 1 +static const uint64_t SH_FLD_RSP_AE_ALWAYS = 18449; // 6 +static const uint64_t SH_FLD_RSP_CTL_CRED_SINGLE_ENA = 18450; // 6 +static const uint64_t SH_FLD_RSV = 18451; // 12 +static const uint64_t SH_FLD_RSV17 = 18452; // 2 +static const uint64_t SH_FLD_RSV18 = 18453; // 2 +static const uint64_t SH_FLD_RSV19 = 18454; // 2 +static const uint64_t SH_FLD_RSV26 = 18455; // 2 +static const uint64_t SH_FLD_RSV27 = 18456; // 2 +static const uint64_t SH_FLD_RSV34 = 18457; // 2 +static const uint64_t SH_FLD_RSV35 = 18458; // 2 +static const uint64_t SH_FLD_RSV6 = 18459; // 2 +static const uint64_t SH_FLD_RSV7 = 18460; // 2 +static const uint64_t SH_FLD_RSVD = 18461; // 98 +static const uint64_t SH_FLD_RSVD0 = 18462; // 1 +static const uint64_t SH_FLD_RSVD0_LEN = 18463; // 1 +static const uint64_t SH_FLD_RSVD1 = 18464; // 1 +static const uint64_t SH_FLD_RSVD1_LEN = 18465; // 1 +static const uint64_t SH_FLD_RSVD_35_43 = 18466; // 8 +static const uint64_t SH_FLD_RSVD_35_43_LEN = 18467; // 8 +static const uint64_t SH_FLD_RSVD_LEN = 18468; // 97 +static const uint64_t SH_FLD_RTAGFLUSH_FAILED = 18469; // 2 +static const uint64_t SH_FLD_RTAG_HANG_EPOCH = 18470; // 2 +static const uint64_t SH_FLD_RTAG_PARITY = 18471; // 1 +static const uint64_t SH_FLD_RTAG_PERR = 18472; // 1 +static const uint64_t SH_FLD_RTIM_THOLD_FORCE = 18473; // 43 +static const uint64_t SH_FLD_RTT_WR0_NOM_VALUE = 18474; // 8 +static const uint64_t SH_FLD_RTT_WR0_NOM_VALUE_LEN = 18475; // 8 +static const uint64_t SH_FLD_RTT_WR1_NOM_VALUE = 18476; // 8 +static const uint64_t SH_FLD_RTT_WR1_NOM_VALUE_LEN = 18477; // 8 +static const uint64_t SH_FLD_RTT_WR2_NOM_VALUE = 18478; // 8 +static const uint64_t SH_FLD_RTT_WR2_NOM_VALUE_LEN = 18479; // 8 +static const uint64_t SH_FLD_RTT_WR3_NOM_VALUE = 18480; // 8 +static const uint64_t SH_FLD_RTT_WR3_NOM_VALUE_LEN = 18481; // 8 +static const uint64_t SH_FLD_RTT_WR4_NOM_VALUE = 18482; // 8 +static const uint64_t SH_FLD_RTT_WR4_NOM_VALUE_LEN = 18483; // 8 +static const uint64_t SH_FLD_RTT_WR5_NOM_VALUE = 18484; // 8 +static const uint64_t SH_FLD_RTT_WR5_NOM_VALUE_LEN = 18485; // 8 +static const uint64_t SH_FLD_RTT_WR6_NOM_VALUE = 18486; // 8 +static const uint64_t SH_FLD_RTT_WR6_NOM_VALUE_LEN = 18487; // 8 +static const uint64_t SH_FLD_RTT_WR7_NOM_VALUE = 18488; // 8 +static const uint64_t SH_FLD_RTT_WR7_NOM_VALUE_LEN = 18489; // 8 +static const uint64_t SH_FLD_RTY_COUNT = 18490; // 2 +static const uint64_t SH_FLD_RTY_COUNT_LEN = 18491; // 2 +static const uint64_t SH_FLD_RT_SPARE0 = 18492; // 1 +static const uint64_t SH_FLD_RT_SPARE0_LEN = 18493; // 1 +static const uint64_t SH_FLD_RUNNING = 18494; // 164 +static const uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE = 18495; // 43 +static const uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN = 18496; // 43 +static const uint64_t SH_FLD_RUNN_MODE = 18497; // 43 +static const uint64_t SH_FLD_RUN_CHIPLET_SCAN0 = 18498; // 43 +static const uint64_t SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL = 18499; // 43 +static const uint64_t SH_FLD_RUN_CYC = 18500; // 24 +static const uint64_t SH_FLD_RUN_CYC_LEN = 18501; // 24 +static const uint64_t SH_FLD_RUN_DCCAL = 18502; // 48 +static const uint64_t SH_FLD_RUN_DYN_RECAL_TIMER = 18503; // 4 +static const uint64_t SH_FLD_RUN_LANE = 18504; // 48 +static const uint64_t SH_FLD_RUN_LANE_DL_MASK = 18505; // 2 +static const uint64_t SH_FLD_RUN_LATCH = 18506; // 24 +static const uint64_t SH_FLD_RUN_ON_CAPTURE_DR = 18507; // 43 +static const uint64_t SH_FLD_RUN_ON_UPDATE_DR = 18508; // 43 +static const uint64_t SH_FLD_RUN_SCAN0 = 18509; // 43 +static const uint64_t SH_FLD_RUN_STATE_ERR_HOLD = 18510; // 43 +static const uint64_t SH_FLD_RUN_STATE_LT = 18511; // 43 +static const uint64_t SH_FLD_RUN_STATE_LT_LEN = 18512; // 43 +static const uint64_t SH_FLD_RUN_STATE_MASK = 18513; // 43 +static const uint64_t SH_FLD_RUN_TCK = 18514; // 1 +static const uint64_t SH_FLD_RUN_TCK_EQ0_ERR = 18515; // 1 +static const uint64_t SH_FLD_RWDM_DLY = 18516; // 8 +static const uint64_t SH_FLD_RWDM_DLY_LEN = 18517; // 8 +static const uint64_t SH_FLD_RWSMDR_DLY = 18518; // 8 +static const uint64_t SH_FLD_RWSMDR_DLY_LEN = 18519; // 8 +static const uint64_t SH_FLD_RWSMSR_DLY = 18520; // 8 +static const uint64_t SH_FLD_RWSMSR_DLY_LEN = 18521; // 8 +static const uint64_t SH_FLD_RX = 18522; // 8 +static const uint64_t SH_FLD_RXAERR = 18523; // 6 +static const uint64_t SH_FLD_RXBERR = 18524; // 6 +static const uint64_t SH_FLD_RXCAL = 18525; // 48 +static const uint64_t SH_FLD_RXCERR = 18526; // 6 +static const uint64_t SH_FLD_RXDERR = 18527; // 6 +static const uint64_t SH_FLD_RXEERR = 18528; // 6 +static const uint64_t SH_FLD_RXFERR = 18529; // 6 +static const uint64_t SH_FLD_RXGERR = 18530; // 6 +static const uint64_t SH_FLD_RXHERR = 18531; // 6 +static const uint64_t SH_FLD_RXIERR = 18532; // 6 +static const uint64_t SH_FLD_RXJERR = 18533; // 6 +static const uint64_t SH_FLD_RXKERR = 18534; // 6 +static const uint64_t SH_FLD_RXLERR = 18535; // 6 +static const uint64_t SH_FLD_RXMERR = 18536; // 6 +static const uint64_t SH_FLD_RXNERR = 18537; // 6 +static const uint64_t SH_FLD_RXOERR = 18538; // 6 +static const uint64_t SH_FLD_RXPERR = 18539; // 6 +static const uint64_t SH_FLD_RXSC = 18540; // 1 +static const uint64_t SH_FLD_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL = 18541; // 4 +static const uint64_t SH_FLD_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN = 18542; // 4 +static const uint64_t SH_FLD_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL = 18543; // 6 +static const uint64_t SH_FLD_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL = 18544; // 6 +static const uint64_t SH_FLD_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL = 18545; // 6 +static const uint64_t SH_FLD_RX_BER_COUNT_RO_SIGNAL = 18546; // 6 +static const uint64_t SH_FLD_RX_BER_COUNT_RO_SIGNAL_LEN = 18547; // 6 +static const uint64_t SH_FLD_RX_BER_COUNT_SATURATED_RO_SIGNAL = 18548; // 6 +static const uint64_t SH_FLD_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL = 18549; // 6 +static const uint64_t SH_FLD_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL = 18550; // 6 +static const uint64_t SH_FLD_RX_BER_TIMER_SATURATED_RO_SIGNAL = 18551; // 6 +static const uint64_t SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL = 18552; // 6 +static const uint64_t SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN = 18553; // 6 +static const uint64_t SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL = 18554; // 6 +static const uint64_t SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN = 18555; // 6 +static const uint64_t SH_FLD_RX_BUS0_MAX_SPARES_EXCEEDED = 18556; // 4 +static const uint64_t SH_FLD_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 18557; // 4 +static const uint64_t SH_FLD_RX_BUS0_SPARE_DEPLOYED = 18558; // 4 +static const uint64_t SH_FLD_RX_BUS0_TOO_MANY_BUS_ERRORS = 18559; // 4 +static const uint64_t SH_FLD_RX_BUS0_TRAINING_ERROR = 18560; // 4 +static const uint64_t SH_FLD_RX_BUS1_MAX_SPARES_EXCEEDED = 18561; // 4 +static const uint64_t SH_FLD_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 18562; // 4 +static const uint64_t SH_FLD_RX_BUS1_SPARE_DEPLOYED = 18563; // 4 +static const uint64_t SH_FLD_RX_BUS1_TOO_MANY_BUS_ERRORS = 18564; // 4 +static const uint64_t SH_FLD_RX_BUS1_TRAINING_ERROR = 18565; // 4 +static const uint64_t SH_FLD_RX_BUS2_MAX_SPARES_EXCEEDED = 18566; // 4 +static const uint64_t SH_FLD_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 18567; // 4 +static const uint64_t SH_FLD_RX_BUS2_SPARE_DEPLOYED = 18568; // 4 +static const uint64_t SH_FLD_RX_BUS2_TOO_MANY_BUS_ERRORS = 18569; // 4 +static const uint64_t SH_FLD_RX_BUS2_TRAINING_ERROR = 18570; // 4 +static const uint64_t SH_FLD_RX_BUS3_MAX_SPARES_EXCEEDED = 18571; // 4 +static const uint64_t SH_FLD_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 18572; // 4 +static const uint64_t SH_FLD_RX_BUS3_SPARE_DEPLOYED = 18573; // 4 +static const uint64_t SH_FLD_RX_BUS3_TOO_MANY_BUS_ERRORS = 18574; // 4 +static const uint64_t SH_FLD_RX_BUS3_TRAINING_ERROR = 18575; // 4 +static const uint64_t SH_FLD_RX_BUS4_MAX_SPARES_EXCEEDED = 18576; // 4 +static const uint64_t SH_FLD_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 18577; // 4 +static const uint64_t SH_FLD_RX_BUS4_SPARE_DEPLOYED = 18578; // 4 +static const uint64_t SH_FLD_RX_BUS4_TOO_MANY_BUS_ERRORS = 18579; // 4 +static const uint64_t SH_FLD_RX_BUS4_TRAINING_ERROR = 18580; // 4 +static const uint64_t SH_FLD_RX_BUS_WIDTH = 18581; // 4 +static const uint64_t SH_FLD_RX_BUS_WIDTH_LEN = 18582; // 4 +static const uint64_t SH_FLD_RX_BW = 18583; // 10 +static const uint64_t SH_FLD_RX_BW_LEN = 18584; // 10 +static const uint64_t SH_FLD_RX_CH_FSM = 18585; // 1 +static const uint64_t SH_FLD_RX_CH_FSM_LEN = 18586; // 1 +static const uint64_t SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 18587; // 72 +static const uint64_t SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 18588; // 72 +static const uint64_t SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 18589; // 72 +static const uint64_t SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 18590; // 72 +static const uint64_t SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 18591; // 72 +static const uint64_t SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 18592; // 72 +static const uint64_t SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 18593; // 72 +static const uint64_t SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 18594; // 72 +static const uint64_t SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 18595; // 72 +static const uint64_t SH_FLD_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL = 18596; // 6 +static const uint64_t SH_FLD_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 18597; // 48 +static const uint64_t SH_FLD_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL = 18598; // 48 +static const uint64_t SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL = 18599; // 6 +static const uint64_t SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN = 18600; // 6 +static const uint64_t SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL = 18601; // 6 +static const uint64_t SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL_LEN = 18602; // 6 +static const uint64_t SH_FLD_RX_DACTEST_ISEQ_RO_SIGNAL = 18603; // 6 +static const uint64_t SH_FLD_RX_DACTEST_ISGT_RO_SIGNAL = 18604; // 6 +static const uint64_t SH_FLD_RX_DACTEST_ISLT_RO_SIGNAL = 18605; // 6 +static const uint64_t SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL = 18606; // 6 +static const uint64_t SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN = 18607; // 6 +static const uint64_t SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL = 18608; // 6 +static const uint64_t SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN = 18609; // 6 +static const uint64_t SH_FLD_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 18610; // 6 +static const uint64_t SH_FLD_RX_DCCAL_DONE_RO_SIGNAL = 18611; // 48 +static const uint64_t SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 18612; // 72 +static const uint64_t SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL = 18613; // 72 +static const uint64_t SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL = 18614; // 72 +static const uint64_t SH_FLD_RX_DF_FSM = 18615; // 1 +static const uint64_t SH_FLD_RX_DF_FSM_LEN = 18616; // 1 +static const uint64_t SH_FLD_RX_DSM_STATE_RO_SIGNAL = 18617; // 4 +static const uint64_t SH_FLD_RX_DSM_STATE_RO_SIGNAL_LEN = 18618; // 4 +static const uint64_t SH_FLD_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL = 18619; // 4 +static const uint64_t SH_FLD_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN = 18620; // 4 +static const uint64_t SH_FLD_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL = 18621; // 4 +static const uint64_t SH_FLD_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN = 18622; // 4 +static const uint64_t SH_FLD_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL = 18623; // 4 +static const uint64_t SH_FLD_RX_DYN_RPR_STATE_RO_SIGNAL = 18624; // 4 +static const uint64_t SH_FLD_RX_DYN_RPR_STATE_RO_SIGNAL_LEN = 18625; // 4 +static const uint64_t SH_FLD_RX_ENC_BUS_LANE2RPR_RO_SIGNAL = 18626; // 4 +static const uint64_t SH_FLD_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN = 18627; // 4 +static const uint64_t SH_FLD_RX_ERR_MODE_0 = 18628; // 1 +static const uint64_t SH_FLD_RX_ERR_MODE_1 = 18629; // 1 +static const uint64_t SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL = 18630; // 6 +static const uint64_t SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL_LEN = 18631; // 6 +static const uint64_t SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 18632; // 72 +static const uint64_t SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 18633; // 72 +static const uint64_t SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 18634; // 72 +static const uint64_t SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 18635; // 72 +static const uint64_t SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 18636; // 72 +static const uint64_t SH_FLD_RX_INIT_DONE_RO_SIGNAL = 18637; // 48 +static const uint64_t SH_FLD_RX_INT_REQ_RO_SIGNAL = 18638; // 6 +static const uint64_t SH_FLD_RX_INT_REQ_RO_SIGNAL_LEN = 18639; // 6 +static const uint64_t SH_FLD_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL = 18640; // 6 +static const uint64_t SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR = 18641; // 8 +static const uint64_t SH_FLD_RX_IREF_PARITY_CHK_RO_SIGNAL = 18642; // 2 +static const uint64_t SH_FLD_RX_IREF_PARITY_CHK_RO_SIGNAL_LEN = 18643; // 2 +static const uint64_t SH_FLD_RX_LANE_BUSY_RO_SIGNAL = 18644; // 48 +static const uint64_t SH_FLD_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL = 18645; // 6 +static const uint64_t SH_FLD_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL = 18646; // 6 +static const uint64_t SH_FLD_RX_LAST_BAD_BUS_LANE_RO_SIGNAL = 18647; // 4 +static const uint64_t SH_FLD_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN = 18648; // 4 +static const uint64_t SH_FLD_RX_MAIN_INIT_STATE_RO_SIGNAL = 18649; // 4 +static const uint64_t SH_FLD_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN = 18650; // 4 +static const uint64_t SH_FLD_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL = 18651; // 6 +static const uint64_t SH_FLD_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL = 18652; // 6 +static const uint64_t SH_FLD_RX_MANUAL_RECAL_DONE_RO_SIGNAL = 18653; // 6 +static const uint64_t SH_FLD_RX_NONSLS_CMD_RO_SIGNAL = 18654; // 4 +static const uint64_t SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL = 18655; // 4 +static const uint64_t SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL_LEN = 18656; // 4 +static const uint64_t SH_FLD_RX_PCB_DATA_P = 18657; // 1 +static const uint64_t SH_FLD_RX_PCB_DATA_P_ERR = 18658; // 1 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL = 18659; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL = 18660; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL = 18661; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL = 18662; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL = 18663; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL = 18664; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL = 18665; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL = 18666; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL = 18667; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 18668; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 18669; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 18670; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL = 18671; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL = 18672; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL = 18673; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL = 18674; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL = 18675; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL = 18676; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL = 18677; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL = 18678; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL = 18679; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL = 18680; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL = 18681; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL = 18682; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL = 18683; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL = 18684; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL = 18685; // 6 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL = 18686; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL = 18687; // 4 +static const uint64_t SH_FLD_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL = 18688; // 4 +static const uint64_t SH_FLD_RX_PG_PRBS_SEED_DONE_RO_SIGNAL = 18689; // 4 +static const uint64_t SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL = 18690; // 120 +static const uint64_t SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 18691; // 120 +static const uint64_t SH_FLD_RX_PL_FIR_ERR_RO_SIGNAL = 18692; // 6 +static const uint64_t SH_FLD_RX_PRBS_DATA_RCV_RO_SIGNAL = 18693; // 4 +static const uint64_t SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL = 18694; // 72 +static const uint64_t SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL = 18695; // 72 +static const uint64_t SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 18696; // 72 +static const uint64_t SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL = 18697; // 72 +static const uint64_t SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL = 18698; // 72 +static const uint64_t SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL = 18699; // 72 +static const uint64_t SH_FLD_RX_PRVCPT_CHANGE_DET_RO_SIGNAL = 18700; // 6 +static const uint64_t SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 18701; // 120 +static const uint64_t SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 18702; // 120 +static const uint64_t SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 18703; // 120 +static const uint64_t SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 18704; // 120 +static const uint64_t SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 18705; // 72 +static const uint64_t SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL = 18706; // 120 +static const uint64_t SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL = 18707; // 120 +static const uint64_t SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL = 18708; // 48 +static const uint64_t SH_FLD_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN = 18709; // 48 +static const uint64_t SH_FLD_RX_PR_IN_COARSE_MODE_RO_SIGNAL = 18710; // 48 +static const uint64_t SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL = 18711; // 48 +static const uint64_t SH_FLD_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 18712; // 48 +static const uint64_t SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 18713; // 120 +static const uint64_t SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN = 18714; // 120 +static const uint64_t SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 18715; // 48 +static const uint64_t SH_FLD_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN = 18716; // 48 +static const uint64_t SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL = 18717; // 72 +static const uint64_t SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 18718; // 120 +static const uint64_t SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 18719; // 120 +static const uint64_t SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 18720; // 48 +static const uint64_t SH_FLD_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN = 18721; // 48 +static const uint64_t SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL = 18722; // 120 +static const uint64_t SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 18723; // 120 +static const uint64_t SH_FLD_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 18724; // 48 +static const uint64_t SH_FLD_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL = 18725; // 48 +static const uint64_t SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL = 18726; // 120 +static const uint64_t SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL = 18727; // 72 +static const uint64_t SH_FLD_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL = 18728; // 1 +static const uint64_t SH_FLD_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL = 18729; // 1 +static const uint64_t SH_FLD_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL = 18730; // 1 +static const uint64_t SH_FLD_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL = 18731; // 1 +static const uint64_t SH_FLD_RX_RECAL_CNT_RO_SIGNAL = 18732; // 6 +static const uint64_t SH_FLD_RX_RECAL_CNT_RO_SIGNAL_LEN = 18733; // 6 +static const uint64_t SH_FLD_RX_RECAL_DONE_RO_SIGNAL = 18734; // 48 +static const uint64_t SH_FLD_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL = 18735; // 4 +static const uint64_t SH_FLD_RX_REPAIR_REQ_RO_SIGNAL = 18736; // 4 +static const uint64_t SH_FLD_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL = 18737; // 6 +static const uint64_t SH_FLD_RX_RPR_STATE_RO_SIGNAL = 18738; // 4 +static const uint64_t SH_FLD_RX_RPR_STATE_RO_SIGNAL_LEN = 18739; // 4 +static const uint64_t SH_FLD_RX_RXDSM_STATE_RO_SIGNAL = 18740; // 4 +static const uint64_t SH_FLD_RX_RXDSM_STATE_RO_SIGNAL_LEN = 18741; // 4 +static const uint64_t SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL = 18742; // 6 +static const uint64_t SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL_LEN = 18743; // 6 +static const uint64_t SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL = 18744; // 6 +static const uint64_t SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL_LEN = 18745; // 6 +static const uint64_t SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL = 18746; // 6 +static const uint64_t SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL_LEN = 18747; // 6 +static const uint64_t SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL = 18748; // 6 +static const uint64_t SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL_LEN = 18749; // 6 +static const uint64_t SH_FLD_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 18750; // 6 +static const uint64_t SH_FLD_RX_SELECT = 18751; // 4 +static const uint64_t SH_FLD_RX_SELECT_LEN = 18752; // 4 +static const uint64_t SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL = 18753; // 6 +static const uint64_t SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN = 18754; // 6 +static const uint64_t SH_FLD_RX_SERVO_STATUS2_RO_SIGNAL = 18755; // 4 +static const uint64_t SH_FLD_RX_SERVO_STATUS2_RO_SIGNAL_LEN = 18756; // 4 +static const uint64_t SH_FLD_RX_SERVO_STATUS_RO_SIGNAL = 18757; // 6 +static const uint64_t SH_FLD_RX_SERVO_STATUS_RO_SIGNAL_LEN = 18758; // 6 +static const uint64_t SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 18759; // 72 +static const uint64_t SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 18760; // 72 +static const uint64_t SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 18761; // 72 +static const uint64_t SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 18762; // 72 +static const uint64_t SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 18763; // 72 +static const uint64_t SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 18764; // 72 +static const uint64_t SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 18765; // 72 +static const uint64_t SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 18766; // 72 +static const uint64_t SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 18767; // 72 +static const uint64_t SH_FLD_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 18768; // 48 +static const uint64_t SH_FLD_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL = 18769; // 48 +static const uint64_t SH_FLD_RX_SLS_CMD_ENCODE_RO_SIGNAL = 18770; // 4 +static const uint64_t SH_FLD_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN = 18771; // 4 +static const uint64_t SH_FLD_RX_SLS_CMD_VAL_RO_SIGNAL = 18772; // 4 +static const uint64_t SH_FLD_RX_SLS_HNDSHK_STATE_RO_SIGNAL = 18773; // 4 +static const uint64_t SH_FLD_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 18774; // 4 +static const uint64_t SH_FLD_RX_SLS_RCVY_STATE_RO_SIGNAL = 18775; // 4 +static const uint64_t SH_FLD_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN = 18776; // 4 +static const uint64_t SH_FLD_RX_SLS_USED_AS_SPR_RO_SIGNAL = 18777; // 4 +static const uint64_t SH_FLD_RX_TTYPE_0 = 18778; // 4 +static const uint64_t SH_FLD_RX_TTYPE_1 = 18779; // 4 +static const uint64_t SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE = 18780; // 1 +static const uint64_t SH_FLD_RX_TTYPE_2 = 18781; // 4 +static const uint64_t SH_FLD_RX_TTYPE_3 = 18782; // 4 +static const uint64_t SH_FLD_RX_TTYPE_4 = 18783; // 4 +static const uint64_t SH_FLD_RX_TTYPE_4_DATA_PARITY = 18784; // 4 +static const uint64_t SH_FLD_RX_TTYPE_5 = 18785; // 4 +static const uint64_t SH_FLD_RX_TTYPE_INVALID = 18786; // 4 +static const uint64_t SH_FLD_RX_WTM_STATE_RO_SIGNAL = 18787; // 4 +static const uint64_t SH_FLD_RX_WTM_STATE_RO_SIGNAL_LEN = 18788; // 4 +static const uint64_t SH_FLD_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL = 18789; // 4 +static const uint64_t SH_FLD_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN = 18790; // 4 +static const uint64_t SH_FLD_RX_WTR_CUR_LANE_RO_SIGNAL = 18791; // 4 +static const uint64_t SH_FLD_RX_WTR_CUR_LANE_RO_SIGNAL_LEN = 18792; // 4 +static const uint64_t SH_FLD_RX_WTR_STATE_RO_SIGNAL = 18793; // 4 +static const uint64_t SH_FLD_RX_WTR_STATE_RO_SIGNAL_LEN = 18794; // 4 +static const uint64_t SH_FLD_RX_WT_CU_PLL_LOCK_RO_SIGNAL = 18795; // 4 +static const uint64_t SH_FLD_S0_BIT_MAP = 18796; // 8 +static const uint64_t SH_FLD_S0_BIT_MAP_LEN = 18797; // 8 +static const uint64_t SH_FLD_S1_BIT_MAP = 18798; // 8 +static const uint64_t SH_FLD_S1_BIT_MAP_LEN = 18799; // 8 +static const uint64_t SH_FLD_S2_BIT_MAP = 18800; // 8 +static const uint64_t SH_FLD_S2_BIT_MAP_LEN = 18801; // 8 +static const uint64_t SH_FLD_SACOLL = 18802; // 12 +static const uint64_t SH_FLD_SAFE_REFRESH_MODE = 18803; // 8 +static const uint64_t SH_FLD_SAMPLED_SMD_PIN = 18804; // 1 +static const uint64_t SH_FLD_SAMPLE_DTS_LT = 18805; // 43 +static const uint64_t SH_FLD_SAMPLE_ENABLE = 18806; // 192 +static const uint64_t SH_FLD_SAMPLE_GUTS = 18807; // 43 +static const uint64_t SH_FLD_SAMPLE_GUTS_LEN = 18808; // 43 +static const uint64_t SH_FLD_SAMPLE_OVERRIDE = 18809; // 96 +static const uint64_t SH_FLD_SAMPLE_PULSE_CNT = 18810; // 43 +static const uint64_t SH_FLD_SAMPLE_PULSE_CNT_LEN = 18811; // 43 +static const uint64_t SH_FLD_SAMPLE_RESET = 18812; // 96 +static const uint64_t SH_FLD_SAMPLE_VALID = 18813; // 12 +static const uint64_t SH_FLD_SAMPSEL = 18814; // 24 +static const uint64_t SH_FLD_SAMPSEL_LEN = 18815; // 24 +static const uint64_t SH_FLD_SAMPTEST_ENABLE = 18816; // 1 +static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX = 18817; // 1 +static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN = 18818; // 1 +static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN = 18819; // 1 +static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN = 18820; // 1 +static const uint64_t SH_FLD_SAMPTEST_RRN_ENABLE = 18821; // 1 +static const uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE = 18822; // 1 +static const uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE_LEN = 18823; // 1 +static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 18824; // 43 +static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 18825; // 43 +static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 18826; // 43 +static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 18827; // 43 +static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 18828; // 43 +static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 18829; // 43 +static const uint64_t SH_FLD_SBASE = 18830; // 12 +static const uint64_t SH_FLD_SBASE_LEN = 18831; // 12 +static const uint64_t SH_FLD_SBC_CL_INDEX_ERROR = 18832; // 1 +static const uint64_t SH_FLD_SBC_CRD_OR_RESP_ERROR = 18833; // 1 +static const uint64_t SH_FLD_SBC_DATA_SRAM_ECC_UE = 18834; // 1 +static const uint64_t SH_FLD_SBC_DMA = 18835; // 1 +static const uint64_t SH_FLD_SBC_DMA_LEN = 18836; // 1 +static const uint64_t SH_FLD_SBC_EOI = 18837; // 1 +static const uint64_t SH_FLD_SBC_EOI_LEN = 18838; // 1 +static const uint64_t SH_FLD_SBC_EOI_OVERFLOW = 18839; // 1 +static const uint64_t SH_FLD_SBC_EOI_TAG_ERROR = 18840; // 1 +static const uint64_t SH_FLD_SBC_LOOKUP = 18841; // 1 +static const uint64_t SH_FLD_SBC_LOOKUP_LEN = 18842; // 1 +static const uint64_t SH_FLD_SBC_PARITY_ERROR = 18843; // 1 +static const uint64_t SH_FLD_SBC_PROCESSING_ERROR = 18844; // 1 +static const uint64_t SH_FLD_SBC_PTAG_ASSIGN_ERROR = 18845; // 1 +static const uint64_t SH_FLD_SBC_PTAG_RELEASE_ERROR = 18846; // 1 +static const uint64_t SH_FLD_SBC_REPLAY_ERROR = 18847; // 1 +static const uint64_t SH_FLD_SBC_SRAM_ECC_CE = 18848; // 1 +static const uint64_t SH_FLD_SBC_STATE_SRAM_ECC_UE = 18849; // 1 +static const uint64_t SH_FLD_SBC_TAG_SRAM_ECC_UE = 18850; // 1 +static const uint64_t SH_FLD_SBC_UNLOCK_FIFO_OVERFLOW = 18851; // 1 +static const uint64_t SH_FLD_SBEFIFO_DATA = 18852; // 5 +static const uint64_t SH_FLD_SBEFIFO_RESET = 18853; // 5 +static const uint64_t SH_FLD_SBE_ERROR_RATE = 18854; // 5 +static const uint64_t SH_FLD_SBE_ERROR_RATE_LEN = 18855; // 5 +static const uint64_t SH_FLD_SBE_EXTERNAL_FIRS = 18856; // 1 +static const uint64_t SH_FLD_SBE_EXTERNAL_FIRS_LEN = 18857; // 1 +static const uint64_t SH_FLD_SBE_INTERRUPT_PENDING = 18858; // 1 +static const uint64_t SH_FLD_SBE_OR_I2C_INTERRUPT_HIGH = 18859; // 1 +static const uint64_t SH_FLD_SB_SCOM_ERRHOLD = 18860; // 2 +static const uint64_t SH_FLD_SB_STRENGTH = 18861; // 43 +static const uint64_t SH_FLD_SB_STRENGTH_LEN = 18862; // 43 +static const uint64_t SH_FLD_SCAN0_MODE = 18863; // 43 +static const uint64_t SH_FLD_SCAN_CLK_USE_EVEN = 18864; // 43 +static const uint64_t SH_FLD_SCAN_COLLISION_ERR = 18865; // 43 +static const uint64_t SH_FLD_SCAN_COUNT = 18866; // 43 +static const uint64_t SH_FLD_SCAN_COUNT_LEN = 18867; // 43 +static const uint64_t SH_FLD_SCAN_INIT_VERSION_PARITY_MASK = 18868; // 43 +static const uint64_t SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 18869; // 43 +static const uint64_t SH_FLD_SCAN_RATIO = 18870; // 43 +static const uint64_t SH_FLD_SCAN_RATIO_LEN = 18871; // 43 +static const uint64_t SH_FLD_SCAN_READ_AND_OPCG_IP_ERR = 18872; // 43 +static const uint64_t SH_FLD_SCOM1_SAT_ERR = 18873; // 2 +static const uint64_t SH_FLD_SCOM20A_SEL = 18874; // 8 +static const uint64_t SH_FLD_SCOMFIR_ERROR = 18875; // 7 +static const uint64_t SH_FLD_SCOMFIR_ERROR_CLONE = 18876; // 7 +static const uint64_t SH_FLD_SCOMFIR_INT_ERR_0 = 18877; // 2 +static const uint64_t SH_FLD_SCOMFIR_INT_ERR_1 = 18878; // 2 +static const uint64_t SH_FLD_SCOMSAT00_ERR = 18879; // 1 +static const uint64_t SH_FLD_SCOMSAT01_ERR = 18880; // 1 +static const uint64_t SH_FLD_SCOM_CMD_REG_INJ = 18881; // 2 +static const uint64_t SH_FLD_SCOM_CMD_REG_INJ_MODE = 18882; // 2 +static const uint64_t SH_FLD_SCOM_CORE_SLOWDOWN = 18883; // 24 +static const uint64_t SH_FLD_SCOM_DIDT_THROTTLE = 18884; // 24 +static const uint64_t SH_FLD_SCOM_DIDT_THROTTLE_LEN = 18885; // 24 +static const uint64_t SH_FLD_SCOM_DIDT_TRIGGER_ENABLE = 18886; // 24 +static const uint64_t SH_FLD_SCOM_DISABLE_DROOP = 18887; // 24 +static const uint64_t SH_FLD_SCOM_DISABLE_DROOP_LEN = 18888; // 24 +static const uint64_t SH_FLD_SCOM_DROOP_MODE_DISABLE = 18889; // 24 +static const uint64_t SH_FLD_SCOM_DROOP_MODE_DISABLE_LEN = 18890; // 24 +static const uint64_t SH_FLD_SCOM_DYN_SUPPRESS_ON_THROTTLE = 18891; // 24 +static const uint64_t SH_FLD_SCOM_ERR = 18892; // 26 +static const uint64_t SH_FLD_SCOM_ERR1 = 18893; // 36 +static const uint64_t SH_FLD_SCOM_ERR2 = 18894; // 40 +static const uint64_t SH_FLD_SCOM_ERROR = 18895; // 14 +static const uint64_t SH_FLD_SCOM_ERR_DUP = 18896; // 22 +static const uint64_t SH_FLD_SCOM_ERR_MASK1 = 18897; // 12 +static const uint64_t SH_FLD_SCOM_ERR_MASK2 = 18898; // 12 +static const uint64_t SH_FLD_SCOM_FATAL_ERROR = 18899; // 30 +static const uint64_t SH_FLD_SCOM_FATAL_REG_PE = 18900; // 2 +static const uint64_t SH_FLD_SCOM_FIR_HMI = 18901; // 96 +static const uint64_t SH_FLD_SCOM_FORCE_DYN_SUPPRESS = 18902; // 24 +static const uint64_t SH_FLD_SCOM_HANG_LIMIT = 18903; // 43 +static const uint64_t SH_FLD_SCOM_HANG_LIMIT_LEN = 18904; // 43 +static const uint64_t SH_FLD_SCOM_HV_REQ_READ_DATA = 18905; // 6 +static const uint64_t SH_FLD_SCOM_HV_REQ_READ_DATA_LEN = 18906; // 6 +static const uint64_t SH_FLD_SCOM_HV_REQ_WRITE_DATA = 18907; // 6 +static const uint64_t SH_FLD_SCOM_HV_REQ_WRITE_DATA_LEN = 18908; // 6 +static const uint64_t SH_FLD_SCOM_INF_ERROR = 18909; // 30 +static const uint64_t SH_FLD_SCOM_LINK01_RESET_KEEPER = 18910; // 2 +static const uint64_t SH_FLD_SCOM_LINK23_RESET_KEEPER = 18911; // 2 +static const uint64_t SH_FLD_SCOM_LINK45_RESET_KEEPER = 18912; // 2 +static const uint64_t SH_FLD_SCOM_LINK67_RESET_KEEPER = 18913; // 1 +static const uint64_t SH_FLD_SCOM_MMIO_ADDR_ERR = 18914; // 2 +static const uint64_t SH_FLD_SCOM_MODE_0 = 18915; // 2 +static const uint64_t SH_FLD_SCOM_MODE_1 = 18916; // 2 +static const uint64_t SH_FLD_SCOM_MODE_2 = 18917; // 2 +static const uint64_t SH_FLD_SCOM_MODE_3 = 18918; // 2 +static const uint64_t SH_FLD_SCOM_MODE_4 = 18919; // 2 +static const uint64_t SH_FLD_SCOM_MODE_5 = 18920; // 2 +static const uint64_t SH_FLD_SCOM_MODE_6 = 18921; // 2 +static const uint64_t SH_FLD_SCOM_MODE_7 = 18922; // 2 +static const uint64_t SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE = 18923; // 8 +static const uint64_t SH_FLD_SCOM_PARITY_CLASS_STATUS = 18924; // 8 +static const uint64_t SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE = 18925; // 8 +static const uint64_t SH_FLD_SCOM_PARITY_ERR = 18926; // 3 +static const uint64_t SH_FLD_SCOM_PARITY_ERR2 = 18927; // 3 +static const uint64_t SH_FLD_SCOM_PARITY_HOLD_OUT = 18928; // 24 +static const uint64_t SH_FLD_SCOM_PE = 18929; // 3 +static const uint64_t SH_FLD_SCOM_PERFMON_START_COMMAND = 18930; // 4 +static const uint64_t SH_FLD_SCOM_PERFMON_STOP_COMMAND = 18931; // 4 +static const uint64_t SH_FLD_SCOM_PERR0 = 18932; // 6 +static const uint64_t SH_FLD_SCOM_PERR1 = 18933; // 6 +static const uint64_t SH_FLD_SCOM_PE_DUP = 18934; // 3 +static const uint64_t SH_FLD_SCOM_PE_DUP_FIR = 18935; // 1 +static const uint64_t SH_FLD_SCOM_PE_FIR = 18936; // 1 +static const uint64_t SH_FLD_SCOM_RECOVERABLE_REG_PE = 18937; // 2 +static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_ARM = 18938; // 2 +static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_RESET = 18939; // 2 +static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_TRIGGER = 18940; // 2 +static const uint64_t SH_FLD_SCOM_S_ERR = 18941; // 1 +static const uint64_t SH_FLD_SCOM_TRACE_RESET = 18942; // 43 +static const uint64_t SH_FLD_SCOM_TRACE_START = 18943; // 43 +static const uint64_t SH_FLD_SCOM_TRACE_STOP = 18944; // 43 +static const uint64_t SH_FLD_SCOM_UV_REQ_READ_DATA = 18945; // 6 +static const uint64_t SH_FLD_SCOM_UV_REQ_READ_DATA_LEN = 18946; // 6 +static const uint64_t SH_FLD_SCOM_UV_REQ_WRITE_DATA = 18947; // 6 +static const uint64_t SH_FLD_SCOM_UV_REQ_WRITE_DATA_LEN = 18948; // 6 +static const uint64_t SH_FLD_SCOM_WRITE = 18949; // 24 +static const uint64_t SH_FLD_SCOPE = 18950; // 24 +static const uint64_t SH_FLD_SCOPE_ATTN_BAR = 18951; // 1 +static const uint64_t SH_FLD_SCOPE_ATTN_BAR_LEN = 18952; // 1 +static const uint64_t SH_FLD_SCOPE_CONTROL = 18953; // 6 +static const uint64_t SH_FLD_SCOPE_CONTROL_LEN = 18954; // 6 +static const uint64_t SH_FLD_SCOPE_LEN = 18955; // 24 +static const uint64_t SH_FLD_SCOPE_MODE = 18956; // 48 +static const uint64_t SH_FLD_SCOPE_MODE_LEN = 18957; // 48 +static const uint64_t SH_FLD_SCPTGT_LFSR_MODE = 18958; // 2 +static const uint64_t SH_FLD_SCPTGT_LFSR_MODE_LEN = 18959; // 2 +static const uint64_t SH_FLD_SCRATCH_ATOMIC_DATA = 18960; // 24 +static const uint64_t SH_FLD_SCRATCH_ATOMIC_DATA_LEN = 18961; // 24 +static const uint64_t SH_FLD_SCRATCH_N = 18962; // 4 +static const uint64_t SH_FLD_SCRATCH_N_LEN = 18963; // 4 +static const uint64_t SH_FLD_SC_RDATA_PARITY_ERRHOLD = 18964; // 2 +static const uint64_t SH_FLD_SD = 18965; // 96 +static const uint64_t SH_FLD_SDAR_MODE = 18966; // 192 +static const uint64_t SH_FLD_SDAR_MODE_LEN = 18967; // 192 +static const uint64_t SH_FLD_SDCA_RCOV = 18968; // 24 +static const uint64_t SH_FLD_SDCCC_T0_COMP_RCOV = 18969; // 24 +static const uint64_t SH_FLD_SDCCC_T1_COMP_RCOV = 18970; // 24 +static const uint64_t SH_FLD_SDCCC_T2_COMP_RCOV = 18971; // 24 +static const uint64_t SH_FLD_SDCCC_T3_COMP_RCOV = 18972; // 24 +static const uint64_t SH_FLD_SDCC_T0_CRITICAL_IS_XSTOP = 18973; // 24 +static const uint64_t SH_FLD_SDCC_T0_HEAD_TAIL_XSTOP = 18974; // 24 +static const uint64_t SH_FLD_SDCC_T1_CRITICAL_IS_XSTOP = 18975; // 24 +static const uint64_t SH_FLD_SDCC_T1_HEAD_TAIL_XSTOP = 18976; // 24 +static const uint64_t SH_FLD_SDCC_T2_CRITICAL_IS_XSTOP = 18977; // 24 +static const uint64_t SH_FLD_SDCC_T2_HEAD_TAIL_XSTOP = 18978; // 24 +static const uint64_t SH_FLD_SDCC_T3_CRITICAL_IS_XSTOP = 18979; // 24 +static const uint64_t SH_FLD_SDCC_T3_HEAD_TAIL_XSTOP = 18980; // 24 +static const uint64_t SH_FLD_SDCR_ERR_INJ = 18981; // 24 +static const uint64_t SH_FLD_SDCU_RAM_XSTOP = 18982; // 24 +static const uint64_t SH_FLD_SDCU_XSTOP = 18983; // 24 +static const uint64_t SH_FLD_SDCV_T0_FLUSH_XSTOP = 18984; // 24 +static const uint64_t SH_FLD_SDCV_T1_FLUSH_XSTOP = 18985; // 24 +static const uint64_t SH_FLD_SDCV_T2_FLUSH_XSTOP = 18986; // 24 +static const uint64_t SH_FLD_SDCV_T3_FLUSH_XSTOP = 18987; // 24 +static const uint64_t SH_FLD_SDCXC_ERR_RPT = 18988; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT = 18989; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT = 18990; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT = 18991; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT = 18992; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT = 18993; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT = 18994; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT = 18995; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT = 18996; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 18997; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT = 18998; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT = 18999; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT = 19000; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT = 19001; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT = 19002; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT = 19003; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT = 19004; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT = 19005; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT = 19006; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 19007; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT = 19008; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT = 19009; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT = 19010; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT = 19011; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT = 19012; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT = 19013; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT = 19014; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT = 19015; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT = 19016; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 19017; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT = 19018; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT = 19019; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT = 19020; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT = 19021; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT = 19022; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT = 19023; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT = 19024; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT = 19025; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT = 19026; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 19027; // 24 +static const uint64_t SH_FLD_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT = 19028; // 24 +static const uint64_t SH_FLD_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT = 19029; // 24 +static const uint64_t SH_FLD_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT = 19030; // 24 +static const uint64_t SH_FLD_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT = 19031; // 24 +static const uint64_t SH_FLD_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT = 19032; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_EVEN_S0_1B = 19033; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_EVEN_S0_2B_XSTOP = 19034; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_EVEN_S1_1B = 19035; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_EVEN_S1_2B_XSTOP = 19036; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_EVEN_S2_1B = 19037; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_EVEN_S2_2B_XSTOP = 19038; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_ODD_S0_1B = 19039; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_ODD_S0_2B_XSTOP = 19040; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_ODD_S1_1B = 19041; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_ODD_S1_2B_XSTOP = 19042; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_ODD_S2_1B = 19043; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS0_ODD_S2_2B_XSTOP = 19044; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_EVEN_S0_1B = 19045; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_EVEN_S0_2B_XSTOP = 19046; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_EVEN_S1_1B = 19047; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_EVEN_S1_2B_XSTOP = 19048; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_EVEN_S2_1B = 19049; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_EVEN_S2_2B_XSTOP = 19050; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_ODD_S0_1B = 19051; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_ODD_S0_2B_XSTOP = 19052; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_ODD_S1_1B = 19053; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_ODD_S1_2B_XSTOP = 19054; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_ODD_S2_1B = 19055; // 24 +static const uint64_t SH_FLD_SDKSMRF_SS1_ODD_S2_2B_XSTOP = 19056; // 24 +static const uint64_t SH_FLD_SDOCTL = 19057; // 48 +static const uint64_t SH_FLD_SDOVAL = 19058; // 48 +static const uint64_t SH_FLD_SD_CI_UE_ERROR = 19059; // 24 +static const uint64_t SH_FLD_SD_L2_UE_ERROR = 19060; // 24 +static const uint64_t SH_FLD_SD_L2_UE_OVER_THRES_ERROR = 19061; // 24 +static const uint64_t SH_FLD_SD_LOG_REC_ERROR = 19062; // 24 +static const uint64_t SH_FLD_SD_LOG_XSTOP_ERROR = 19063; // 24 +static const uint64_t SH_FLD_SD_MCHK_AND_ME_EQ_0_ERROR = 19064; // 24 +static const uint64_t SH_FLD_SD_NOT_MT_CI_REC_ERROR = 19065; // 24 +static const uint64_t SH_FLD_SD_RFILE_REC_ERROR = 19066; // 24 +static const uint64_t SH_FLD_SD_RFILE_XSTOP_ERROR = 19067; // 24 +static const uint64_t SH_FLD_SD_SYS_XSTOP_ERROR = 19068; // 24 +static const uint64_t SH_FLD_SE = 19069; // 96 +static const uint64_t SH_FLD_SEC = 19070; // 8 +static const uint64_t SH_FLD_SECOND = 19071; // 1 +static const uint64_t SH_FLD_SECURE = 19072; // 1 +static const uint64_t SH_FLD_SECURE_ACCESS = 19073; // 1 +static const uint64_t SH_FLD_SECURE_ACCESS_BIT = 19074; // 1 +static const uint64_t SH_FLD_SECURE_BOOTH = 19075; // 1 +static const uint64_t SH_FLD_SECURE_DEBUG = 19076; // 1 +static const uint64_t SH_FLD_SECURE_DEBUG_MODE = 19077; // 1 +static const uint64_t SH_FLD_SECURE_ERR = 19078; // 2 +static const uint64_t SH_FLD_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD = 19079; // 2 +static const uint64_t SH_FLD_SECURE_LNK_SCOM_CONFLICT_ERRHOLD = 19080; // 2 +static const uint64_t SH_FLD_SECURE_SCOM_ERROR = 19081; // 4 +static const uint64_t SH_FLD_SECURITY_DEBUG_MODE = 19082; // 43 +static const uint64_t SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE = 19083; // 1 +static const uint64_t SH_FLD_SEC_LEN = 19084; // 8 +static const uint64_t SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE = 19085; // 1 +static const uint64_t SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE = 19086; // 1 +static const uint64_t SH_FLD_SEC_M_PATH_SELECT = 19087; // 2 +static const uint64_t SH_FLD_SEC_M_S_DRAWER_SELECT = 19088; // 2 +static const uint64_t SH_FLD_SEC_M_S_SELECT = 19089; // 2 +static const uint64_t SH_FLD_SEC_SELECT = 19090; // 1 +static const uint64_t SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE = 19091; // 1 +static const uint64_t SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE = 19092; // 1 +static const uint64_t SH_FLD_SEC_S_PATH_SELECT = 19093; // 1 +static const uint64_t SH_FLD_SEC_V = 19094; // 8 +static const uint64_t SH_FLD_SEC_WBRD_DEBUG_0_SELECT = 19095; // 8 +static const uint64_t SH_FLD_SEC_WBRD_DEBUG_1_SELECT = 19096; // 8 +static const uint64_t SH_FLD_SEEPROM_UPDATE_LOCK = 19097; // 1 +static const uint64_t SH_FLD_SEG_TEST_CLK_STATUS = 19098; // 4 +static const uint64_t SH_FLD_SEG_TEST_CLK_STATUS_LEN = 19099; // 4 +static const uint64_t SH_FLD_SEG_TEST_LEAKAGE_CTRL = 19100; // 6 +static const uint64_t SH_FLD_SEG_TEST_MODE = 19101; // 6 +static const uint64_t SH_FLD_SEG_TEST_MODE_LEN = 19102; // 6 +static const uint64_t SH_FLD_SEG_TEST_STATUS = 19103; // 116 +static const uint64_t SH_FLD_SEG_TEST_STATUS_LEN = 19104; // 116 +static const uint64_t SH_FLD_SEIDBAR = 19105; // 1 +static const uint64_t SH_FLD_SEIDBAR_LEN = 19106; // 1 +static const uint64_t SH_FLD_SEIDR = 19107; // 256 +static const uint64_t SH_FLD_SEIDR_LEN = 19108; // 256 +static const uint64_t SH_FLD_SEL = 19109; // 10 +static const uint64_t SH_FLD_SEL0 = 19110; // 1 +static const uint64_t SH_FLD_SEL0_LEN = 19111; // 1 +static const uint64_t SH_FLD_SEL1 = 19112; // 1 +static const uint64_t SH_FLD_SEL1_LEN = 19113; // 1 +static const uint64_t SH_FLD_SELCT_CONTROL = 19114; // 90 +static const uint64_t SH_FLD_SELCT_CONTROL_LEN = 19115; // 90 +static const uint64_t SH_FLD_SELD2SPR = 19116; // 10 +static const uint64_t SH_FLD_SELECT = 19117; // 2 +static const uint64_t SH_FLD_SELECTED_ERROR = 19118; // 3 +static const uint64_t SH_FLD_SELECTED_ERROR_LEN = 19119; // 3 +static const uint64_t SH_FLD_SELECT_0 = 19120; // 5 +static const uint64_t SH_FLD_SELECT_0_LEN = 19121; // 5 +static const uint64_t SH_FLD_SELECT_1 = 19122; // 5 +static const uint64_t SH_FLD_SELECT_1_LEN = 19123; // 5 +static const uint64_t SH_FLD_SELECT_2 = 19124; // 5 +static const uint64_t SH_FLD_SELECT_2_LEN = 19125; // 5 +static const uint64_t SH_FLD_SELECT_3 = 19126; // 5 +static const uint64_t SH_FLD_SELECT_3_LEN = 19127; // 5 +static const uint64_t SH_FLD_SELECT_4 = 19128; // 5 +static const uint64_t SH_FLD_SELECT_4_LEN = 19129; // 5 +static const uint64_t SH_FLD_SELECT_5 = 19130; // 5 +static const uint64_t SH_FLD_SELECT_5_LEN = 19131; // 5 +static const uint64_t SH_FLD_SELECT_6 = 19132; // 5 +static const uint64_t SH_FLD_SELECT_6_LEN = 19133; // 5 +static const uint64_t SH_FLD_SELECT_7 = 19134; // 5 +static const uint64_t SH_FLD_SELECT_7_LEN = 19135; // 5 +static const uint64_t SH_FLD_SELECT_LEN = 19136; // 2 +static const uint64_t SH_FLD_SELECT_LOCAL_HANG_PULSE = 19137; // 4 +static const uint64_t SH_FLD_SELECT_PB_HANG_PULSE = 19138; // 4 +static const uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB = 19139; // 1 +static const uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB_LEN = 19140; // 1 +static const uint64_t SH_FLD_SELECT_SECONDARY_SEEPROM = 19141; // 1 +static const uint64_t SH_FLD_SELFBOOT_DONE = 19142; // 1 +static const uint64_t SH_FLD_SELFBOOT_ENGINE_ATTENTION = 19143; // 1 +static const uint64_t SH_FLD_SELF_BUSY_0 = 19144; // 4 +static const uint64_t SH_FLD_SELF_BUSY_1 = 19145; // 2 +static const uint64_t SH_FLD_SELF_BUSY_2 = 19146; // 2 +static const uint64_t SH_FLD_SELF_BUSY_3 = 19147; // 2 +static const uint64_t SH_FLD_SELPFDPW = 19148; // 10 +static const uint64_t SH_FLD_SELPREFB = 19149; // 10 +static const uint64_t SH_FLD_SELPRESPE = 19150; // 10 +static const uint64_t SH_FLD_SEL_03_NPU_NOT = 19151; // 1 +static const uint64_t SH_FLD_SEL_04_NPU_NOT = 19152; // 1 +static const uint64_t SH_FLD_SEL_05_NPU_NOT = 19153; // 1 +static const uint64_t SH_FLD_SEL_0_2 = 19154; // 16 +static const uint64_t SH_FLD_SEL_0_2_LEN = 19155; // 16 +static const uint64_t SH_FLD_SEL_1_3 = 19156; // 16 +static const uint64_t SH_FLD_SEL_1_3_LEN = 19157; // 16 +static const uint64_t SH_FLD_SEL_LEN = 19158; // 10 +static const uint64_t SH_FLD_SEL_RG_PMU_DATA = 19159; // 1 +static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI = 19160; // 1 +static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI_LEN = 19161; // 1 +static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO = 19162; // 1 +static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO_LEN = 19163; // 1 +static const uint64_t SH_FLD_SEL_RG_TRIGGERS_01 = 19164; // 1 +static const uint64_t SH_FLD_SEL_RG_TRIGGERS_01_LEN = 19165; // 1 +static const uint64_t SH_FLD_SEL_RG_TRIGGERS_23 = 19166; // 1 +static const uint64_t SH_FLD_SEL_RG_TRIGGERS_23_LEN = 19167; // 1 +static const uint64_t SH_FLD_SEL_THOLD_ARY = 19168; // 43 +static const uint64_t SH_FLD_SEL_THOLD_NSL = 19169; // 43 +static const uint64_t SH_FLD_SEL_THOLD_SL = 19170; // 43 +static const uint64_t SH_FLD_SEL_TYPE_0_2 = 19171; // 16 +static const uint64_t SH_FLD_SEL_TYPE_1_3 = 19172; // 16 +static const uint64_t SH_FLD_SEND_DELAY_CYCLES = 19173; // 2 +static const uint64_t SH_FLD_SEND_DELAY_CYCLES_LEN = 19174; // 2 +static const uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE = 19175; // 2 +static const uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE_LEN = 19176; // 2 +static const uint64_t SH_FLD_SENSEADJ_RESET0 = 19177; // 43 +static const uint64_t SH_FLD_SENSEADJ_RESET1 = 19178; // 43 +static const uint64_t SH_FLD_SEQ = 19179; // 8 +static const uint64_t SH_FLD_SEQ_01 = 19180; // 43 +static const uint64_t SH_FLD_SEQ_01_LEN = 19181; // 43 +static const uint64_t SH_FLD_SEQ_02 = 19182; // 43 +static const uint64_t SH_FLD_SEQ_02_LEN = 19183; // 43 +static const uint64_t SH_FLD_SEQ_03 = 19184; // 43 +static const uint64_t SH_FLD_SEQ_03_LEN = 19185; // 43 +static const uint64_t SH_FLD_SEQ_04 = 19186; // 43 +static const uint64_t SH_FLD_SEQ_04_LEN = 19187; // 43 +static const uint64_t SH_FLD_SEQ_05 = 19188; // 43 +static const uint64_t SH_FLD_SEQ_05_LEN = 19189; // 43 +static const uint64_t SH_FLD_SEQ_06 = 19190; // 43 +static const uint64_t SH_FLD_SEQ_06_LEN = 19191; // 43 +static const uint64_t SH_FLD_SEQ_07 = 19192; // 43 +static const uint64_t SH_FLD_SEQ_07EVEN = 19193; // 43 +static const uint64_t SH_FLD_SEQ_07EVEN_LEN = 19194; // 43 +static const uint64_t SH_FLD_SEQ_07ODD = 19195; // 43 +static const uint64_t SH_FLD_SEQ_07ODD_LEN = 19196; // 43 +static const uint64_t SH_FLD_SEQ_07_LEN = 19197; // 43 +static const uint64_t SH_FLD_SEQ_08 = 19198; // 43 +static const uint64_t SH_FLD_SEQ_08EVEN = 19199; // 43 +static const uint64_t SH_FLD_SEQ_08EVEN_LEN = 19200; // 43 +static const uint64_t SH_FLD_SEQ_08ODD = 19201; // 43 +static const uint64_t SH_FLD_SEQ_08ODD_LEN = 19202; // 43 +static const uint64_t SH_FLD_SEQ_08_LEN = 19203; // 43 +static const uint64_t SH_FLD_SEQ_09 = 19204; // 43 +static const uint64_t SH_FLD_SEQ_09EVEN = 19205; // 43 +static const uint64_t SH_FLD_SEQ_09EVEN_LEN = 19206; // 43 +static const uint64_t SH_FLD_SEQ_09ODD = 19207; // 43 +static const uint64_t SH_FLD_SEQ_09ODD_LEN = 19208; // 43 +static const uint64_t SH_FLD_SEQ_09_LEN = 19209; // 43 +static const uint64_t SH_FLD_SEQ_10 = 19210; // 43 +static const uint64_t SH_FLD_SEQ_10EVEN = 19211; // 43 +static const uint64_t SH_FLD_SEQ_10EVEN_LEN = 19212; // 43 +static const uint64_t SH_FLD_SEQ_10ODD = 19213; // 43 +static const uint64_t SH_FLD_SEQ_10ODD_LEN = 19214; // 43 +static const uint64_t SH_FLD_SEQ_10_LEN = 19215; // 43 +static const uint64_t SH_FLD_SEQ_11 = 19216; // 43 +static const uint64_t SH_FLD_SEQ_11EVEN = 19217; // 43 +static const uint64_t SH_FLD_SEQ_11EVEN_LEN = 19218; // 43 +static const uint64_t SH_FLD_SEQ_11ODD = 19219; // 43 +static const uint64_t SH_FLD_SEQ_11ODD_LEN = 19220; // 43 +static const uint64_t SH_FLD_SEQ_11_LEN = 19221; // 43 +static const uint64_t SH_FLD_SEQ_12 = 19222; // 43 +static const uint64_t SH_FLD_SEQ_12EVEN = 19223; // 43 +static const uint64_t SH_FLD_SEQ_12EVEN_LEN = 19224; // 43 +static const uint64_t SH_FLD_SEQ_12ODD = 19225; // 43 +static const uint64_t SH_FLD_SEQ_12ODD_LEN = 19226; // 43 +static const uint64_t SH_FLD_SEQ_12_LEN = 19227; // 43 +static const uint64_t SH_FLD_SEQ_13_01EVEN = 19228; // 43 +static const uint64_t SH_FLD_SEQ_13_01EVEN_LEN = 19229; // 43 +static const uint64_t SH_FLD_SEQ_14_01ODD = 19230; // 43 +static const uint64_t SH_FLD_SEQ_14_01ODD_LEN = 19231; // 43 +static const uint64_t SH_FLD_SEQ_15_02EVEN = 19232; // 43 +static const uint64_t SH_FLD_SEQ_15_02EVEN_LEN = 19233; // 43 +static const uint64_t SH_FLD_SEQ_16_02ODD = 19234; // 43 +static const uint64_t SH_FLD_SEQ_16_02ODD_LEN = 19235; // 43 +static const uint64_t SH_FLD_SEQ_17_03EVEN = 19236; // 43 +static const uint64_t SH_FLD_SEQ_17_03EVEN_LEN = 19237; // 43 +static const uint64_t SH_FLD_SEQ_18_03ODD = 19238; // 43 +static const uint64_t SH_FLD_SEQ_18_03ODD_LEN = 19239; // 43 +static const uint64_t SH_FLD_SEQ_19_04EVEN = 19240; // 43 +static const uint64_t SH_FLD_SEQ_19_04EVEN_LEN = 19241; // 43 +static const uint64_t SH_FLD_SEQ_20_04ODD = 19242; // 43 +static const uint64_t SH_FLD_SEQ_20_04ODD_LEN = 19243; // 43 +static const uint64_t SH_FLD_SEQ_21_05EVEN = 19244; // 43 +static const uint64_t SH_FLD_SEQ_21_05EVEN_LEN = 19245; // 43 +static const uint64_t SH_FLD_SEQ_22_05ODD = 19246; // 43 +static const uint64_t SH_FLD_SEQ_22_05ODD_LEN = 19247; // 43 +static const uint64_t SH_FLD_SEQ_23_06EVEN = 19248; // 43 +static const uint64_t SH_FLD_SEQ_23_06EVEN_LEN = 19249; // 43 +static const uint64_t SH_FLD_SEQ_24_06ODD = 19250; // 43 +static const uint64_t SH_FLD_SEQ_24_06ODD_LEN = 19251; // 43 +static const uint64_t SH_FLD_SEQ_MASK = 19252; // 8 +static const uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 19253; // 43 +static const uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 19254; // 43 +static const uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 19255; // 43 +static const uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 19256; // 43 +static const uint64_t SH_FLD_SERVO_CHG_CFG = 19257; // 6 +static const uint64_t SH_FLD_SERVO_CHG_CFG_LEN = 19258; // 6 +static const uint64_t SH_FLD_SERVO_CONFIG = 19259; // 6 +static const uint64_t SH_FLD_SERVO_CONFIG_LEN = 19260; // 6 +static const uint64_t SH_FLD_SERVO_DONE = 19261; // 6 +static const uint64_t SH_FLD_SERVO_OP = 19262; // 6 +static const uint64_t SH_FLD_SERVO_OP_LEN = 19263; // 6 +static const uint64_t SH_FLD_SERVO_RECAL_IP = 19264; // 4 +static const uint64_t SH_FLD_SERVO_RESULT = 19265; // 6 +static const uint64_t SH_FLD_SERVO_RESULT_LEN = 19266; // 6 +static const uint64_t SH_FLD_SERVO_THRESH1 = 19267; // 6 +static const uint64_t SH_FLD_SERVO_THRESH1_LEN = 19268; // 6 +static const uint64_t SH_FLD_SERVO_THRESH2 = 19269; // 6 +static const uint64_t SH_FLD_SERVO_THRESH2_LEN = 19270; // 6 +static const uint64_t SH_FLD_SERVO_THRESH3 = 19271; // 4 +static const uint64_t SH_FLD_SERVO_THRESH3_LEN = 19272; // 4 +static const uint64_t SH_FLD_SET = 19273; // 6 +static const uint64_t SH_FLD_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT = 19274; // 24 +static const uint64_t SH_FLD_SET_CMDS = 19275; // 2 +static const uint64_t SH_FLD_SET_CMDS_EN = 19276; // 2 +static const uint64_t SH_FLD_SET_CMDS_LEN = 19277; // 2 +static const uint64_t SH_FLD_SET_DLY_MEASUREMENT = 19278; // 3 +static const uint64_t SH_FLD_SET_DMA_IRQ_SUSPEND_MODE = 19279; // 3 +static const uint64_t SH_FLD_SET_ECC_INJECT_ERR = 19280; // 12 +static const uint64_t SH_FLD_SET_EXT_ARM = 19281; // 4 +static const uint64_t SH_FLD_SET_EXT_RESET = 19282; // 4 +static const uint64_t SH_FLD_SET_EXT_TRIGGER = 19283; // 4 +static const uint64_t SH_FLD_SET_INDEX = 19284; // 2 +static const uint64_t SH_FLD_SET_INDEX_LEN = 19285; // 2 +static const uint64_t SH_FLD_SET_LEN = 19286; // 6 +static const uint64_t SH_FLD_SET_PORT_ENABLE = 19287; // 3 +static const uint64_t SH_FLD_SET_PORT_ENABLE_LEN = 19288; // 3 +static const uint64_t SH_FLD_SF = 19289; // 96 +static const uint64_t SH_FLD_SGB_BYTE_VALID = 19290; // 21 +static const uint64_t SH_FLD_SGB_BYTE_VALID_LEN = 19291; // 21 +static const uint64_t SH_FLD_SGB_FLUSH_PENDING = 19292; // 21 +static const uint64_t SH_FLD_SG_HIGH_DURING_FILL = 19293; // 43 +static const uint64_t SH_FLD_SHADOW_ANALOGTUNE = 19294; // 14 +static const uint64_t SH_FLD_SHADOW_ANALOGTUNE_LEN = 19295; // 14 +static const uint64_t SH_FLD_SHADOW_ATSTSEL = 19296; // 14 +static const uint64_t SH_FLD_SHADOW_ATSTSEL_LEN = 19297; // 14 +static const uint64_t SH_FLD_SHADOW_BANDSEL = 19298; // 14 +static const uint64_t SH_FLD_SHADOW_BANDSEL_LEN = 19299; // 14 +static const uint64_t SH_FLD_SHADOW_BGOFFSET = 19300; // 14 +static const uint64_t SH_FLD_SHADOW_BGOFFSET_LEN = 19301; // 14 +static const uint64_t SH_FLD_SHADOW_BYPASSN = 19302; // 10 +static const uint64_t SH_FLD_SHADOW_CALRECAL = 19303; // 10 +static const uint64_t SH_FLD_SHADOW_CALREQ = 19304; // 10 +static const uint64_t SH_FLD_SHADOW_CAPSEL = 19305; // 4 +static const uint64_t SH_FLD_SHADOW_CCALBANDSEL = 19306; // 10 +static const uint64_t SH_FLD_SHADOW_CCALBANDSEL_LEN = 19307; // 10 +static const uint64_t SH_FLD_SHADOW_CCALCOMP = 19308; // 10 +static const uint64_t SH_FLD_SHADOW_CCALCVHOLD = 19309; // 10 +static const uint64_t SH_FLD_SHADOW_CCALERR = 19310; // 10 +static const uint64_t SH_FLD_SHADOW_CCALFMAX = 19311; // 10 +static const uint64_t SH_FLD_SHADOW_CCALFMIN = 19312; // 10 +static const uint64_t SH_FLD_SHADOW_CCALLOAD = 19313; // 10 +static const uint64_t SH_FLD_SHADOW_CCALMETH = 19314; // 10 +static const uint64_t SH_FLD_SHADOW_CMLEN = 19315; // 7 +static const uint64_t SH_FLD_SHADOW_CMLEN100 = 19316; // 3 +static const uint64_t SH_FLD_SHADOW_CMLEN133 = 19317; // 3 +static const uint64_t SH_FLD_SHADOW_CMLEN156 = 19318; // 3 +static const uint64_t SH_FLD_SHADOW_CPISEL = 19319; // 14 +static const uint64_t SH_FLD_SHADOW_CPISEL_LEN = 19320; // 14 +static const uint64_t SH_FLD_SHADOW_CSEL = 19321; // 10 +static const uint64_t SH_FLD_SHADOW_CSEL_LEN = 19322; // 10 +static const uint64_t SH_FLD_SHADOW_DIVSELB = 19323; // 10 +static const uint64_t SH_FLD_SHADOW_DIVSELB_LEN = 19324; // 10 +static const uint64_t SH_FLD_SHADOW_DIVSELFB = 19325; // 4 +static const uint64_t SH_FLD_SHADOW_DIVSELFB_LEN = 19326; // 4 +static const uint64_t SH_FLD_SHADOW_EN = 19327; // 10 +static const uint64_t SH_FLD_SHADOW_ENABLE = 19328; // 10 +static const uint64_t SH_FLD_SHADOW_FILTDIVSEL = 19329; // 3 +static const uint64_t SH_FLD_SHADOW_FILTDIVSEL_LEN = 19330; // 3 +static const uint64_t SH_FLD_SHADOW_FRAC1 = 19331; // 3 +static const uint64_t SH_FLD_SHADOW_FRAC1_LEN = 19332; // 3 +static const uint64_t SH_FLD_SHADOW_FRAC2 = 19333; // 3 +static const uint64_t SH_FLD_SHADOW_FRAC2_LEN = 19334; // 3 +static const uint64_t SH_FLD_SHADOW_ITUNE = 19335; // 4 +static const uint64_t SH_FLD_SHADOW_ITUNE_LEN = 19336; // 4 +static const uint64_t SH_FLD_SHADOW_LOCK = 19337; // 10 +static const uint64_t SH_FLD_SHADOW_MUXEN = 19338; // 4 +static const uint64_t SH_FLD_SHADOW_MUXSEL = 19339; // 4 +static const uint64_t SH_FLD_SHADOW_MUXSEL_LEN = 19340; // 4 +static const uint64_t SH_FLD_SHADOW_PCLKDIFSEL = 19341; // 10 +static const uint64_t SH_FLD_SHADOW_PCLKSEL = 19342; // 14 +static const uint64_t SH_FLD_SHADOW_PCLKSEL_LEN = 19343; // 14 +static const uint64_t SH_FLD_SHADOW_PFD360SEL = 19344; // 4 +static const uint64_t SH_FLD_SHADOW_PHASEFB = 19345; // 4 +static const uint64_t SH_FLD_SHADOW_PHASEFB_LEN = 19346; // 4 +static const uint64_t SH_FLD_SHADOW_PLLLOCK = 19347; // 4 +static const uint64_t SH_FLD_SHADOW_RDIV = 19348; // 14 +static const uint64_t SH_FLD_SHADOW_RDIV_LEN = 19349; // 10 +static const uint64_t SH_FLD_SHADOW_REFCLKSEL = 19350; // 4 +static const uint64_t SH_FLD_SHADOW_RESET = 19351; // 10 +static const uint64_t SH_FLD_SHADOW_RESSEL = 19352; // 4 +static const uint64_t SH_FLD_SHADOW_RSEL = 19353; // 10 +static const uint64_t SH_FLD_SHADOW_RSEL_LEN = 19354; // 10 +static const uint64_t SH_FLD_SHADOW_SEL = 19355; // 10 +static const uint64_t SH_FLD_SHADOW_SELD2SPR = 19356; // 10 +static const uint64_t SH_FLD_SHADOW_SELPFDPW = 19357; // 10 +static const uint64_t SH_FLD_SHADOW_SELPREFB = 19358; // 10 +static const uint64_t SH_FLD_SHADOW_SELPRESPE = 19359; // 10 +static const uint64_t SH_FLD_SHADOW_SEL_LEN = 19360; // 10 +static const uint64_t SH_FLD_SHADOW_SPARE = 19361; // 7 +static const uint64_t SH_FLD_SHADOW_SPARE_LEN = 19362; // 3 +static const uint64_t SH_FLD_SHADOW_SPEDIV = 19363; // 10 +static const uint64_t SH_FLD_SHADOW_SPEDIV_LEN = 19364; // 10 +static const uint64_t SH_FLD_SHADOW_SSCGEN = 19365; // 3 +static const uint64_t SH_FLD_SHADOW_SYNCEN = 19366; // 7 +static const uint64_t SH_FLD_SHADOW_UNUSED23_31 = 19367; // 7 +static const uint64_t SH_FLD_SHADOW_UNUSED23_31_LEN = 19368; // 7 +static const uint64_t SH_FLD_SHADOW_UNUSED4 = 19369; // 7 +static const uint64_t SH_FLD_SHADOW_UNUSED5 = 19370; // 7 +static const uint64_t SH_FLD_SHADOW_UNUSED63 = 19371; // 3 +static const uint64_t SH_FLD_SHADOW_UNUSED88 = 19372; // 3 +static const uint64_t SH_FLD_SHADOW_UNUSED88_LEN = 19373; // 3 +static const uint64_t SH_FLD_SHADOW_VCORANGE = 19374; // 10 +static const uint64_t SH_FLD_SHADOW_VCORANGE_LEN = 19375; // 10 +static const uint64_t SH_FLD_SHADOW_VCOSEL = 19376; // 10 +static const uint64_t SH_FLD_SHADOW_VREGBYPASS = 19377; // 4 +static const uint64_t SH_FLD_SHADOW_VREGENABLE_N = 19378; // 4 +static const uint64_t SH_FLD_SHADOW_VSEL = 19379; // 10 +static const uint64_t SH_FLD_SHADOW_VSEL_LEN = 19380; // 10 +static const uint64_t SH_FLD_SHA_LATENCY_CFG = 19381; // 1 +static const uint64_t SH_FLD_SHIFTER_PARITY_ERR_HOLD = 19382; // 43 +static const uint64_t SH_FLD_SHIFTER_PARITY_MASK = 19383; // 43 +static const uint64_t SH_FLD_SHIFTER_VALID_ERR_HOLD = 19384; // 43 +static const uint64_t SH_FLD_SHIFTER_VALID_MASK = 19385; // 43 +static const uint64_t SH_FLD_SHIFT_DTS_LT = 19386; // 43 +static const uint64_t SH_FLD_SHIFT_VOLT_LT = 19387; // 43 +static const uint64_t SH_FLD_SIAR = 19388; // 96 +static const uint64_t SH_FLD_SIAR_LEN = 19389; // 96 +static const uint64_t SH_FLD_SIBLING_CORE_DROPOUT_ENABLE = 19390; // 12 +static const uint64_t SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN = 19391; // 12 +static const uint64_t SH_FLD_SIER = 19392; // 24 +static const uint64_t SH_FLD_SIER_A_XLATE_SRC = 19393; // 96 +static const uint64_t SH_FLD_SIER_A_XLATE_SRC_LEN = 19394; // 96 +static const uint64_t SH_FLD_SIER_CMPL = 19395; // 96 +static const uint64_t SH_FLD_SIER_CMPL_STALL = 19396; // 96 +static const uint64_t SH_FLD_SIER_DATA_SRC = 19397; // 96 +static const uint64_t SH_FLD_SIER_DATA_SRC_LEN = 19398; // 96 +static const uint64_t SH_FLD_SIER_DERAT_MISS = 19399; // 96 +static const uint64_t SH_FLD_SIER_DISP_HELD = 19400; // 96 +static const uint64_t SH_FLD_SIER_DISP_HELD_LEN = 19401; // 96 +static const uint64_t SH_FLD_SIER_EXPOSED = 19402; // 96 +static const uint64_t SH_FLD_SIER_EXT = 19403; // 96 +static const uint64_t SH_FLD_SIER_EXT_LEN = 19404; // 96 +static const uint64_t SH_FLD_SIER_FIN_STALL = 19405; // 96 +static const uint64_t SH_FLD_SIER_ICACHE = 19406; // 96 +static const uint64_t SH_FLD_SIER_ICACHE_LEN = 19407; // 96 +static const uint64_t SH_FLD_SIER_INST_TYPE = 19408; // 96 +static const uint64_t SH_FLD_SIER_INST_TYPE_LEN = 19409; // 96 +static const uint64_t SH_FLD_SIER_LDST = 19410; // 96 +static const uint64_t SH_FLD_SIER_LDST_LEN = 19411; // 96 +static const uint64_t SH_FLD_SIER_MASK_TBD = 19412; // 24 +static const uint64_t SH_FLD_SIER_MASK_TBD_LEN = 19413; // 24 +static const uint64_t SH_FLD_SIER_MPRED = 19414; // 96 +static const uint64_t SH_FLD_SIER_MPRED_BR_CCACHE = 19415; // 96 +static const uint64_t SH_FLD_SIER_MPRED_TYPE = 19416; // 96 +static const uint64_t SH_FLD_SIER_MPRED_TYPE_LEN = 19417; // 96 +static const uint64_t SH_FLD_SIER_MSR_HV = 19418; // 96 +static const uint64_t SH_FLD_SIER_MSR_PR = 19419; // 96 +static const uint64_t SH_FLD_SIER_MSR_TA = 19420; // 96 +static const uint64_t SH_FLD_SIER_PAGE_SIZE = 19421; // 96 +static const uint64_t SH_FLD_SIER_PAGE_SIZE_LEN = 19422; // 96 +static const uint64_t SH_FLD_SIER_PEMPTY = 19423; // 96 +static const uint64_t SH_FLD_SIER_REJ_ISU_COL = 19424; // 96 +static const uint64_t SH_FLD_SIER_REJ_ISU_SRC = 19425; // 96 +static const uint64_t SH_FLD_SIER_REJ_LSU = 19426; // 96 +static const uint64_t SH_FLD_SIER_REJ_LSU_REASON = 19427; // 96 +static const uint64_t SH_FLD_SIER_REJ_LSU_REASON_LEN = 19428; // 96 +static const uint64_t SH_FLD_SIER_REP_BR = 19429; // 96 +static const uint64_t SH_FLD_SIER_RESERVED1 = 19430; // 96 +static const uint64_t SH_FLD_SIER_RESERVED2 = 19431; // 96 +static const uint64_t SH_FLD_SIER_RESERVED2_LEN = 19432; // 96 +static const uint64_t SH_FLD_SIER_SDAR_VALID = 19433; // 96 +static const uint64_t SH_FLD_SIER_SIAR_VALID = 19434; // 96 +static const uint64_t SH_FLD_SIER_SLEW_DN = 19435; // 96 +static const uint64_t SH_FLD_SIER_SLEW_UP = 19436; // 96 +static const uint64_t SH_FLD_SIER_STALL_REASON = 19437; // 96 +static const uint64_t SH_FLD_SIER_STALL_REASON_LEN = 19438; // 96 +static const uint64_t SH_FLD_SIER_STCX_FAIL = 19439; // 96 +static const uint64_t SH_FLD_SIER_ST_BKILL = 19440; // 96 +static const uint64_t SH_FLD_SIER_TAK_BR = 19441; // 96 +static const uint64_t SH_FLD_SIER_TE = 19442; // 96 +static const uint64_t SH_FLD_SIER_THERMAL = 19443; // 96 +static const uint64_t SH_FLD_SIER_XLATE_SRC = 19444; // 96 +static const uint64_t SH_FLD_SIER_XLATE_SRC_LEN = 19445; // 96 +static const uint64_t SH_FLD_SIGNATURE = 19446; // 1 +static const uint64_t SH_FLD_SIGNATURE_LEN = 19447; // 1 +static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP0 = 19448; // 8 +static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP1 = 19449; // 8 +static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP2 = 19450; // 8 +static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP3 = 19451; // 8 +static const uint64_t SH_FLD_SINGLE_OUTSTANDING_CMD = 19452; // 1 +static const uint64_t SH_FLD_SIZE = 19453; // 45 +static const uint64_t SH_FLD_SIZE_0 = 19454; // 5 +static const uint64_t SH_FLD_SIZE_0_LEN = 19455; // 5 +static const uint64_t SH_FLD_SIZE_1 = 19456; // 5 +static const uint64_t SH_FLD_SIZE_1_LEN = 19457; // 5 +static const uint64_t SH_FLD_SIZE_2 = 19458; // 5 +static const uint64_t SH_FLD_SIZE_2_LEN = 19459; // 5 +static const uint64_t SH_FLD_SIZE_3 = 19460; // 5 +static const uint64_t SH_FLD_SIZE_3_LEN = 19461; // 5 +static const uint64_t SH_FLD_SIZE_4 = 19462; // 5 +static const uint64_t SH_FLD_SIZE_4_LEN = 19463; // 5 +static const uint64_t SH_FLD_SIZE_5 = 19464; // 5 +static const uint64_t SH_FLD_SIZE_5_LEN = 19465; // 5 +static const uint64_t SH_FLD_SIZE_6 = 19466; // 5 +static const uint64_t SH_FLD_SIZE_6_LEN = 19467; // 5 +static const uint64_t SH_FLD_SIZE_7 = 19468; // 5 +static const uint64_t SH_FLD_SIZE_7_LEN = 19469; // 5 +static const uint64_t SH_FLD_SIZE_LEN = 19470; // 45 +static const uint64_t SH_FLD_SKIP_G = 19471; // 4 +static const uint64_t SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS = 19472; // 2 +static const uint64_t SH_FLD_SKIP_RDCENTERING = 19473; // 8 +static const uint64_t SH_FLD_SKITTER0 = 19474; // 43 +static const uint64_t SH_FLD_SKITTER0_DELAY_SELECT = 19475; // 43 +static const uint64_t SH_FLD_SKITTER0_DELAY_SELECT_LEN = 19476; // 43 +static const uint64_t SH_FLD_SKITTER0_LEN = 19477; // 43 +static const uint64_t SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD = 19478; // 43 +static const uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD = 19479; // 43 +static const uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_MASK = 19480; // 43 +static const uint64_t SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD = 19481; // 43 +static const uint64_t SH_FLD_SKITTER_MODEREG_PARITY_MASK = 19482; // 43 +static const uint64_t SH_FLD_SLAVE10_ERROR_CODE = 19483; // 1 +static const uint64_t SH_FLD_SLAVE10_ERROR_CODE_LEN = 19484; // 1 +static const uint64_t SH_FLD_SLAVE10_RESPONSE_BIT = 19485; // 1 +static const uint64_t SH_FLD_SLAVE11_ERROR_CODE = 19486; // 1 +static const uint64_t SH_FLD_SLAVE11_ERROR_CODE_LEN = 19487; // 1 +static const uint64_t SH_FLD_SLAVE11_RESPONSE_BIT = 19488; // 1 +static const uint64_t SH_FLD_SLAVE12_ERROR_CODE = 19489; // 1 +static const uint64_t SH_FLD_SLAVE12_ERROR_CODE_LEN = 19490; // 1 +static const uint64_t SH_FLD_SLAVE12_RESPONSE_BIT = 19491; // 1 +static const uint64_t SH_FLD_SLAVE13_ERROR_CODE = 19492; // 1 +static const uint64_t SH_FLD_SLAVE13_ERROR_CODE_LEN = 19493; // 1 +static const uint64_t SH_FLD_SLAVE13_RESPONSE_BIT = 19494; // 1 +static const uint64_t SH_FLD_SLAVE14_ERROR_CODE = 19495; // 1 +static const uint64_t SH_FLD_SLAVE14_ERROR_CODE_LEN = 19496; // 1 +static const uint64_t SH_FLD_SLAVE14_RESPONSE_BIT = 19497; // 1 +static const uint64_t SH_FLD_SLAVE15_ERROR_CODE = 19498; // 1 +static const uint64_t SH_FLD_SLAVE15_ERROR_CODE_LEN = 19499; // 1 +static const uint64_t SH_FLD_SLAVE15_RESPONSE_BIT = 19500; // 1 +static const uint64_t SH_FLD_SLAVE16_ERROR_CODE = 19501; // 1 +static const uint64_t SH_FLD_SLAVE16_ERROR_CODE_LEN = 19502; // 1 +static const uint64_t SH_FLD_SLAVE16_RESPONSE_BIT = 19503; // 1 +static const uint64_t SH_FLD_SLAVE17_ERROR_CODE = 19504; // 1 +static const uint64_t SH_FLD_SLAVE17_ERROR_CODE_LEN = 19505; // 1 +static const uint64_t SH_FLD_SLAVE17_RESPONSE_BIT = 19506; // 1 +static const uint64_t SH_FLD_SLAVE18_ERROR_CODE = 19507; // 1 +static const uint64_t SH_FLD_SLAVE18_ERROR_CODE_LEN = 19508; // 1 +static const uint64_t SH_FLD_SLAVE18_RESPONSE_BIT = 19509; // 1 +static const uint64_t SH_FLD_SLAVE19_ERROR_CODE = 19510; // 1 +static const uint64_t SH_FLD_SLAVE19_ERROR_CODE_LEN = 19511; // 1 +static const uint64_t SH_FLD_SLAVE19_RESPONSE_BIT = 19512; // 1 +static const uint64_t SH_FLD_SLAVE1_ERROR_CODE = 19513; // 1 +static const uint64_t SH_FLD_SLAVE1_ERROR_CODE_LEN = 19514; // 1 +static const uint64_t SH_FLD_SLAVE1_RESPONSE_BIT = 19515; // 1 +static const uint64_t SH_FLD_SLAVE20_ERROR_CODE = 19516; // 1 +static const uint64_t SH_FLD_SLAVE20_ERROR_CODE_LEN = 19517; // 1 +static const uint64_t SH_FLD_SLAVE20_RESPONSE_BIT = 19518; // 1 +static const uint64_t SH_FLD_SLAVE21_ERROR_CODE = 19519; // 1 +static const uint64_t SH_FLD_SLAVE21_ERROR_CODE_LEN = 19520; // 1 +static const uint64_t SH_FLD_SLAVE21_RESPONSE_BIT = 19521; // 1 +static const uint64_t SH_FLD_SLAVE22_ERROR_CODE = 19522; // 1 +static const uint64_t SH_FLD_SLAVE22_ERROR_CODE_LEN = 19523; // 1 +static const uint64_t SH_FLD_SLAVE22_RESPONSE_BIT = 19524; // 1 +static const uint64_t SH_FLD_SLAVE23_ERROR_CODE = 19525; // 1 +static const uint64_t SH_FLD_SLAVE23_ERROR_CODE_LEN = 19526; // 1 +static const uint64_t SH_FLD_SLAVE23_RESPONSE_BIT = 19527; // 1 +static const uint64_t SH_FLD_SLAVE24_ERROR_CODE = 19528; // 1 +static const uint64_t SH_FLD_SLAVE24_ERROR_CODE_LEN = 19529; // 1 +static const uint64_t SH_FLD_SLAVE24_RESPONSE_BIT = 19530; // 1 +static const uint64_t SH_FLD_SLAVE25_ERROR_CODE = 19531; // 1 +static const uint64_t SH_FLD_SLAVE25_ERROR_CODE_LEN = 19532; // 1 +static const uint64_t SH_FLD_SLAVE25_RESPONSE_BIT = 19533; // 1 +static const uint64_t SH_FLD_SLAVE26_ERROR_CODE = 19534; // 1 +static const uint64_t SH_FLD_SLAVE26_ERROR_CODE_LEN = 19535; // 1 +static const uint64_t SH_FLD_SLAVE26_RESPONSE_BIT = 19536; // 1 +static const uint64_t SH_FLD_SLAVE27_ERROR_CODE = 19537; // 1 +static const uint64_t SH_FLD_SLAVE27_ERROR_CODE_LEN = 19538; // 1 +static const uint64_t SH_FLD_SLAVE27_RESPONSE_BIT = 19539; // 1 +static const uint64_t SH_FLD_SLAVE28_ERROR_CODE = 19540; // 1 +static const uint64_t SH_FLD_SLAVE28_ERROR_CODE_LEN = 19541; // 1 +static const uint64_t SH_FLD_SLAVE28_RESPONSE_BIT = 19542; // 1 +static const uint64_t SH_FLD_SLAVE29_ERROR_CODE = 19543; // 1 +static const uint64_t SH_FLD_SLAVE29_ERROR_CODE_LEN = 19544; // 1 +static const uint64_t SH_FLD_SLAVE29_RESPONSE_BIT = 19545; // 1 +static const uint64_t SH_FLD_SLAVE2_ERROR_CODE = 19546; // 1 +static const uint64_t SH_FLD_SLAVE2_ERROR_CODE_LEN = 19547; // 1 +static const uint64_t SH_FLD_SLAVE2_RESPONSE_BIT = 19548; // 1 +static const uint64_t SH_FLD_SLAVE30_ERROR_CODE = 19549; // 1 +static const uint64_t SH_FLD_SLAVE30_ERROR_CODE_LEN = 19550; // 1 +static const uint64_t SH_FLD_SLAVE30_RESPONSE_BIT = 19551; // 1 +static const uint64_t SH_FLD_SLAVE31_ERROR_CODE = 19552; // 1 +static const uint64_t SH_FLD_SLAVE31_ERROR_CODE_LEN = 19553; // 1 +static const uint64_t SH_FLD_SLAVE31_RESPONSE_BIT = 19554; // 1 +static const uint64_t SH_FLD_SLAVE32_ERROR_CODE = 19555; // 1 +static const uint64_t SH_FLD_SLAVE32_ERROR_CODE_LEN = 19556; // 1 +static const uint64_t SH_FLD_SLAVE32_RESPONSE_BIT = 19557; // 1 +static const uint64_t SH_FLD_SLAVE33_ERROR_CODE = 19558; // 1 +static const uint64_t SH_FLD_SLAVE33_ERROR_CODE_LEN = 19559; // 1 +static const uint64_t SH_FLD_SLAVE33_RESPONSE_BIT = 19560; // 1 +static const uint64_t SH_FLD_SLAVE34_ERROR_CODE = 19561; // 1 +static const uint64_t SH_FLD_SLAVE34_ERROR_CODE_LEN = 19562; // 1 +static const uint64_t SH_FLD_SLAVE34_RESPONSE_BIT = 19563; // 1 +static const uint64_t SH_FLD_SLAVE35_ERROR_CODE = 19564; // 1 +static const uint64_t SH_FLD_SLAVE35_ERROR_CODE_LEN = 19565; // 1 +static const uint64_t SH_FLD_SLAVE35_RESPONSE_BIT = 19566; // 1 +static const uint64_t SH_FLD_SLAVE36_ERROR_CODE = 19567; // 1 +static const uint64_t SH_FLD_SLAVE36_ERROR_CODE_LEN = 19568; // 1 +static const uint64_t SH_FLD_SLAVE36_RESPONSE_BIT = 19569; // 1 +static const uint64_t SH_FLD_SLAVE37_ERROR_CODE = 19570; // 1 +static const uint64_t SH_FLD_SLAVE37_ERROR_CODE_LEN = 19571; // 1 +static const uint64_t SH_FLD_SLAVE37_RESPONSE_BIT = 19572; // 1 +static const uint64_t SH_FLD_SLAVE38_ERROR_CODE = 19573; // 1 +static const uint64_t SH_FLD_SLAVE38_ERROR_CODE_LEN = 19574; // 1 +static const uint64_t SH_FLD_SLAVE38_RESPONSE_BIT = 19575; // 1 +static const uint64_t SH_FLD_SLAVE39_ERROR_CODE = 19576; // 1 +static const uint64_t SH_FLD_SLAVE39_ERROR_CODE_LEN = 19577; // 1 +static const uint64_t SH_FLD_SLAVE39_RESPONSE_BIT = 19578; // 1 +static const uint64_t SH_FLD_SLAVE3_ERROR_CODE = 19579; // 1 +static const uint64_t SH_FLD_SLAVE3_ERROR_CODE_LEN = 19580; // 1 +static const uint64_t SH_FLD_SLAVE3_RESPONSE_BIT = 19581; // 1 +static const uint64_t SH_FLD_SLAVE40_ERROR_CODE = 19582; // 1 +static const uint64_t SH_FLD_SLAVE40_ERROR_CODE_LEN = 19583; // 1 +static const uint64_t SH_FLD_SLAVE40_RESPONSE_BIT = 19584; // 1 +static const uint64_t SH_FLD_SLAVE41_ERROR_CODE = 19585; // 1 +static const uint64_t SH_FLD_SLAVE41_ERROR_CODE_LEN = 19586; // 1 +static const uint64_t SH_FLD_SLAVE41_RESPONSE_BIT = 19587; // 1 +static const uint64_t SH_FLD_SLAVE42_ERROR_CODE = 19588; // 1 +static const uint64_t SH_FLD_SLAVE42_ERROR_CODE_LEN = 19589; // 1 +static const uint64_t SH_FLD_SLAVE42_RESPONSE_BIT = 19590; // 1 +static const uint64_t SH_FLD_SLAVE43_ERROR_CODE = 19591; // 1 +static const uint64_t SH_FLD_SLAVE43_ERROR_CODE_LEN = 19592; // 1 +static const uint64_t SH_FLD_SLAVE43_RESPONSE_BIT = 19593; // 1 +static const uint64_t SH_FLD_SLAVE44_ERROR_CODE = 19594; // 1 +static const uint64_t SH_FLD_SLAVE44_ERROR_CODE_LEN = 19595; // 1 +static const uint64_t SH_FLD_SLAVE44_RESPONSE_BIT = 19596; // 1 +static const uint64_t SH_FLD_SLAVE45_ERROR_CODE = 19597; // 1 +static const uint64_t SH_FLD_SLAVE45_ERROR_CODE_LEN = 19598; // 1 +static const uint64_t SH_FLD_SLAVE45_RESPONSE_BIT = 19599; // 1 +static const uint64_t SH_FLD_SLAVE46_ERROR_CODE = 19600; // 1 +static const uint64_t SH_FLD_SLAVE46_ERROR_CODE_LEN = 19601; // 1 +static const uint64_t SH_FLD_SLAVE46_RESPONSE_BIT = 19602; // 1 +static const uint64_t SH_FLD_SLAVE47_ERROR_CODE = 19603; // 1 +static const uint64_t SH_FLD_SLAVE47_ERROR_CODE_LEN = 19604; // 1 +static const uint64_t SH_FLD_SLAVE47_RESPONSE_BIT = 19605; // 1 +static const uint64_t SH_FLD_SLAVE48_ERROR_CODE = 19606; // 1 +static const uint64_t SH_FLD_SLAVE48_ERROR_CODE_LEN = 19607; // 1 +static const uint64_t SH_FLD_SLAVE48_RESPONSE_BIT = 19608; // 1 +static const uint64_t SH_FLD_SLAVE49_ERROR_CODE = 19609; // 1 +static const uint64_t SH_FLD_SLAVE49_ERROR_CODE_LEN = 19610; // 1 +static const uint64_t SH_FLD_SLAVE49_RESPONSE_BIT = 19611; // 1 +static const uint64_t SH_FLD_SLAVE4_ERROR_CODE = 19612; // 1 +static const uint64_t SH_FLD_SLAVE4_ERROR_CODE_LEN = 19613; // 1 +static const uint64_t SH_FLD_SLAVE4_RESPONSE_BIT = 19614; // 1 +static const uint64_t SH_FLD_SLAVE50_ERROR_CODE = 19615; // 1 +static const uint64_t SH_FLD_SLAVE50_ERROR_CODE_LEN = 19616; // 1 +static const uint64_t SH_FLD_SLAVE50_RESPONSE_BIT = 19617; // 1 +static const uint64_t SH_FLD_SLAVE51_ERROR_CODE = 19618; // 1 +static const uint64_t SH_FLD_SLAVE51_ERROR_CODE_LEN = 19619; // 1 +static const uint64_t SH_FLD_SLAVE51_RESPONSE_BIT = 19620; // 1 +static const uint64_t SH_FLD_SLAVE52_ERROR_CODE = 19621; // 1 +static const uint64_t SH_FLD_SLAVE52_ERROR_CODE_LEN = 19622; // 1 +static const uint64_t SH_FLD_SLAVE52_RESPONSE_BIT = 19623; // 1 +static const uint64_t SH_FLD_SLAVE53_ERROR_CODE = 19624; // 1 +static const uint64_t SH_FLD_SLAVE53_ERROR_CODE_LEN = 19625; // 1 +static const uint64_t SH_FLD_SLAVE53_RESPONSE_BIT = 19626; // 1 +static const uint64_t SH_FLD_SLAVE54_ERROR_CODE = 19627; // 1 +static const uint64_t SH_FLD_SLAVE54_ERROR_CODE_LEN = 19628; // 1 +static const uint64_t SH_FLD_SLAVE54_RESPONSE_BIT = 19629; // 1 +static const uint64_t SH_FLD_SLAVE55_ERROR_CODE = 19630; // 1 +static const uint64_t SH_FLD_SLAVE55_ERROR_CODE_LEN = 19631; // 1 +static const uint64_t SH_FLD_SLAVE55_RESPONSE_BIT = 19632; // 1 +static const uint64_t SH_FLD_SLAVE56_ERROR_CODE = 19633; // 1 +static const uint64_t SH_FLD_SLAVE56_ERROR_CODE_LEN = 19634; // 1 +static const uint64_t SH_FLD_SLAVE56_RESPONSE_BIT = 19635; // 1 +static const uint64_t SH_FLD_SLAVE57_ERROR_CODE = 19636; // 1 +static const uint64_t SH_FLD_SLAVE57_ERROR_CODE_LEN = 19637; // 1 +static const uint64_t SH_FLD_SLAVE57_RESPONSE_BIT = 19638; // 1 +static const uint64_t SH_FLD_SLAVE58_ERROR_CODE = 19639; // 1 +static const uint64_t SH_FLD_SLAVE58_ERROR_CODE_LEN = 19640; // 1 +static const uint64_t SH_FLD_SLAVE58_RESPONSE_BIT = 19641; // 1 +static const uint64_t SH_FLD_SLAVE59_ERROR_CODE = 19642; // 1 +static const uint64_t SH_FLD_SLAVE59_ERROR_CODE_LEN = 19643; // 1 +static const uint64_t SH_FLD_SLAVE59_RESPONSE_BIT = 19644; // 1 +static const uint64_t SH_FLD_SLAVE5_ERROR_CODE = 19645; // 1 +static const uint64_t SH_FLD_SLAVE5_ERROR_CODE_LEN = 19646; // 1 +static const uint64_t SH_FLD_SLAVE5_RESPONSE_BIT = 19647; // 1 +static const uint64_t SH_FLD_SLAVE60_ERROR_CODE = 19648; // 1 +static const uint64_t SH_FLD_SLAVE60_ERROR_CODE_LEN = 19649; // 1 +static const uint64_t SH_FLD_SLAVE60_RESPONSE_BIT = 19650; // 1 +static const uint64_t SH_FLD_SLAVE61_ERROR_CODE = 19651; // 1 +static const uint64_t SH_FLD_SLAVE61_ERROR_CODE_LEN = 19652; // 1 +static const uint64_t SH_FLD_SLAVE61_RESPONSE_BIT = 19653; // 1 +static const uint64_t SH_FLD_SLAVE62_ERROR_CODE = 19654; // 1 +static const uint64_t SH_FLD_SLAVE62_ERROR_CODE_LEN = 19655; // 1 +static const uint64_t SH_FLD_SLAVE62_RESPONSE_BIT = 19656; // 1 +static const uint64_t SH_FLD_SLAVE63_ERROR_CODE = 19657; // 1 +static const uint64_t SH_FLD_SLAVE63_ERROR_CODE_LEN = 19658; // 1 +static const uint64_t SH_FLD_SLAVE63_RESPONSE_BIT = 19659; // 1 +static const uint64_t SH_FLD_SLAVE6_ERROR_CODE = 19660; // 1 +static const uint64_t SH_FLD_SLAVE6_ERROR_CODE_LEN = 19661; // 1 +static const uint64_t SH_FLD_SLAVE6_RESPONSE_BIT = 19662; // 1 +static const uint64_t SH_FLD_SLAVE7_ERROR_CODE = 19663; // 1 +static const uint64_t SH_FLD_SLAVE7_ERROR_CODE_LEN = 19664; // 1 +static const uint64_t SH_FLD_SLAVE7_RESPONSE_BIT = 19665; // 1 +static const uint64_t SH_FLD_SLAVE8_ERROR_CODE = 19666; // 1 +static const uint64_t SH_FLD_SLAVE8_ERROR_CODE_LEN = 19667; // 1 +static const uint64_t SH_FLD_SLAVE8_RESPONSE_BIT = 19668; // 1 +static const uint64_t SH_FLD_SLAVE9_ERROR_CODE = 19669; // 1 +static const uint64_t SH_FLD_SLAVE9_ERROR_CODE_LEN = 19670; // 1 +static const uint64_t SH_FLD_SLAVE9_RESPONSE_BIT = 19671; // 1 +static const uint64_t SH_FLD_SLAVE_IDLE = 19672; // 1 +static const uint64_t SH_FLD_SLAVE_MODE = 19673; // 43 +static const uint64_t SH_FLD_SLAVE_RESET_TO_405_ENABLE = 19674; // 1 +static const uint64_t SH_FLD_SLBI_GROUP_PUMP_EN = 19675; // 12 +static const uint64_t SH_FLD_SLB_BUS0_STG1_SEL = 19676; // 1 +static const uint64_t SH_FLD_SLB_BUS0_STG2_SEL = 19677; // 1 +static const uint64_t SH_FLD_SLB_BUS1_STG1_SEL = 19678; // 1 +static const uint64_t SH_FLD_SLB_BUS1_STG2_SEL = 19679; // 1 +static const uint64_t SH_FLD_SLB_CAC_PERR_DET = 19680; // 1 +static const uint64_t SH_FLD_SLB_DIR_PERR_DET = 19681; // 1 +static const uint64_t SH_FLD_SLB_LRU_PERR_DET = 19682; // 1 +static const uint64_t SH_FLD_SLB_MULTIHIT_DET = 19683; // 1 +static const uint64_t SH_FLD_SLE = 19684; // 96 +static const uint64_t SH_FLD_SLEWCTL = 19685; // 1 +static const uint64_t SH_FLD_SLEWCTL_LEN = 19686; // 1 +static const uint64_t SH_FLD_SLEW_DN_SEL = 19687; // 6 +static const uint64_t SH_FLD_SLICE = 19688; // 3 +static const uint64_t SH_FLD_SLICE0_CFG_ECC_CE_ERR = 19689; // 2 +static const uint64_t SH_FLD_SLICE0_CFG_ECC_UE_ERR = 19690; // 2 +static const uint64_t SH_FLD_SLICE1_CFG_ECC_CE_ERR = 19691; // 2 +static const uint64_t SH_FLD_SLICE1_CFG_ECC_UE_ERR = 19692; // 2 +static const uint64_t SH_FLD_SLICE2_CFG_ECC_CE_ERR = 19693; // 2 +static const uint64_t SH_FLD_SLICE2_CFG_ECC_UE_ERR = 19694; // 2 +static const uint64_t SH_FLD_SLICE3_CFG_ECC_CE_ERR = 19695; // 2 +static const uint64_t SH_FLD_SLICE3_CFG_ECC_UE_ERR = 19696; // 2 +static const uint64_t SH_FLD_SLICE_LEN = 19697; // 3 +static const uint64_t SH_FLD_SLOT0_B2_VALID = 19698; // 8 +static const uint64_t SH_FLD_SLOT0_D_VALUE = 19699; // 8 +static const uint64_t SH_FLD_SLOT0_M0_VALID = 19700; // 8 +static const uint64_t SH_FLD_SLOT0_M1_VALID = 19701; // 8 +static const uint64_t SH_FLD_SLOT0_ROW15_VALID = 19702; // 8 +static const uint64_t SH_FLD_SLOT0_ROW16_VALID = 19703; // 8 +static const uint64_t SH_FLD_SLOT0_ROW17_VALID = 19704; // 8 +static const uint64_t SH_FLD_SLOT0_S0_VALID = 19705; // 8 +static const uint64_t SH_FLD_SLOT0_S1_VALID = 19706; // 8 +static const uint64_t SH_FLD_SLOT0_S2_VALID = 19707; // 8 +static const uint64_t SH_FLD_SLOT0_VALID = 19708; // 8 +static const uint64_t SH_FLD_SLOT1_B2_VALID = 19709; // 8 +static const uint64_t SH_FLD_SLOT1_D_VALUE = 19710; // 8 +static const uint64_t SH_FLD_SLOT1_M0_VALID = 19711; // 8 +static const uint64_t SH_FLD_SLOT1_M1_VALID = 19712; // 8 +static const uint64_t SH_FLD_SLOT1_ROW15_VALID = 19713; // 8 +static const uint64_t SH_FLD_SLOT1_ROW16_VALID = 19714; // 8 +static const uint64_t SH_FLD_SLOT1_ROW17_VALID = 19715; // 8 +static const uint64_t SH_FLD_SLOT1_S0_VALID = 19716; // 8 +static const uint64_t SH_FLD_SLOT1_S1_VALID = 19717; // 8 +static const uint64_t SH_FLD_SLOT1_S2_VALID = 19718; // 8 +static const uint64_t SH_FLD_SLOT1_VALID = 19719; // 8 +static const uint64_t SH_FLD_SLOW_CMD_RATE = 19720; // 1 +static const uint64_t SH_FLD_SLOW_TO_MODE = 19721; // 86 +static const uint64_t SH_FLD_SLS_CMD_GCRMSG = 19722; // 4 +static const uint64_t SH_FLD_SLS_CMD_GCRMSG_LEN = 19723; // 4 +static const uint64_t SH_FLD_SLS_CNTR_TAP_PTS = 19724; // 4 +static const uint64_t SH_FLD_SLS_CNTR_TAP_PTS_LEN = 19725; // 4 +static const uint64_t SH_FLD_SLS_DISABLE = 19726; // 4 +static const uint64_t SH_FLD_SLS_EXCEPTION2_CS = 19727; // 4 +static const uint64_t SH_FLD_SLS_EXTEND_SEL = 19728; // 4 +static const uint64_t SH_FLD_SLS_EXTEND_SEL_LEN = 19729; // 4 +static const uint64_t SH_FLD_SLS_LANE_ENC_SPR1_GCRMSG = 19730; // 4 +static const uint64_t SH_FLD_SLS_LANE_GCRMSG = 19731; // 4 +static const uint64_t SH_FLD_SLS_LANE_GCRMSG_LEN = 19732; // 4 +static const uint64_t SH_FLD_SLS_LANE_MUX_SPR1_GCRMSG = 19733; // 4 +static const uint64_t SH_FLD_SLS_LANE_MUX_SPR2_GCRMSG = 19734; // 4 +static const uint64_t SH_FLD_SLS_LANE_SEL_LG_GCRMSG = 19735; // 4 +static const uint64_t SH_FLD_SLS_LANE_SHDW_GCRMSG = 19736; // 4 +static const uint64_t SH_FLD_SLS_LANE_SHDW_RPR_GCRMSG = 19737; // 4 +static const uint64_t SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG = 19738; // 4 +static const uint64_t SH_FLD_SLS_LANE_VAL_GCRMSG = 19739; // 4 +static const uint64_t SH_FLD_SLS_RCVY_DISABLE = 19740; // 4 +static const uint64_t SH_FLD_SLS_SCRAMBLE_MODE = 19741; // 4 +static const uint64_t SH_FLD_SLS_SCRAMBLE_MODE_LEN = 19742; // 4 +static const uint64_t SH_FLD_SLS_TIMEOUT_EXT_SEL = 19743; // 4 +static const uint64_t SH_FLD_SLS_TIMEOUT_EXT_SEL_LEN = 19744; // 4 +static const uint64_t SH_FLD_SLS_TIMEOUT_SEL = 19745; // 4 +static const uint64_t SH_FLD_SLS_TIMEOUT_SEL_LEN = 19746; // 4 +static const uint64_t SH_FLD_SLV_DIS_ABUSPAR = 19747; // 1 +static const uint64_t SH_FLD_SLV_DIS_BE = 19748; // 1 +static const uint64_t SH_FLD_SLV_DIS_BEPAR = 19749; // 1 +static const uint64_t SH_FLD_SLV_DIS_RDDBUSPAREN = 19750; // 1 +static const uint64_t SH_FLD_SLV_DIS_SACK = 19751; // 1 +static const uint64_t SH_FLD_SLV_DIS_WRDBUSPAR = 19752; // 1 +static const uint64_t SH_FLD_SLV_EVENT_MUX = 19753; // 1 +static const uint64_t SH_FLD_SLV_EVENT_MUX_LEN = 19754; // 1 +static const uint64_t SH_FLD_SLV_LGL_RPR_REQ_GCRMSG = 19755; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG = 19756; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG = 19757; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 19758; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_SPR1_GCRMSG = 19759; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_SPR2_GCRMSG = 19760; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 19761; // 4 +static const uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 19762; // 4 +static const uint64_t SH_FLD_SLV_SPARE = 19763; // 1 +static const uint64_t SH_FLD_SL_UE_CRC_ERR = 19764; // 5 +static const uint64_t SH_FLD_SMALL_DROOP_ERR = 19765; // 12 +static const uint64_t SH_FLD_SMALL_EVENT_PROFILE_CTR = 19766; // 12 +static const uint64_t SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN = 19767; // 12 +static const uint64_t SH_FLD_SMALL_EVENT_THRESHOLD = 19768; // 12 +static const uint64_t SH_FLD_SMALL_EVENT_THRESHOLD_LEN = 19769; // 12 +static const uint64_t SH_FLD_SMALL_STEP = 19770; // 8 +static const uint64_t SH_FLD_SMALL_STEP_LEN = 19771; // 8 +static const uint64_t SH_FLD_SMASK_IN0 = 19772; // 43 +static const uint64_t SH_FLD_SMASK_IN1 = 19773; // 43 +static const uint64_t SH_FLD_SMASK_IN2 = 19774; // 43 +static const uint64_t SH_FLD_SMASK_IN3 = 19775; // 43 +static const uint64_t SH_FLD_SMASK_IN4 = 19776; // 43 +static const uint64_t SH_FLD_SMQ = 19777; // 48 +static const uint64_t SH_FLD_SMQM = 19778; // 48 +static const uint64_t SH_FLD_SMQM_LEN = 19779; // 48 +static const uint64_t SH_FLD_SMQ_LEN = 19780; // 48 +static const uint64_t SH_FLD_SMT_MODE = 19781; // 24 +static const uint64_t SH_FLD_SMT_MODE_LEN = 19782; // 24 +static const uint64_t SH_FLD_SM_1HOT_ERR = 19783; // 16 +static const uint64_t SH_FLD_SM_MMIO0 = 19784; // 3 +static const uint64_t SH_FLD_SM_MMIO1 = 19785; // 3 +static const uint64_t SH_FLD_SM_MMIO2 = 19786; // 3 +static const uint64_t SH_FLD_SM_MMIO3 = 19787; // 3 +static const uint64_t SH_FLD_SM_OR_CASE = 19788; // 2 +static const uint64_t SH_FLD_SM_RESET = 19789; // 1 +static const uint64_t SH_FLD_SN0_CRESP_ATAG_P = 19790; // 12 +static const uint64_t SH_FLD_SN0_CRESP_TTAG_P = 19791; // 12 +static const uint64_t SH_FLD_SN0_RCMD_ADDR_P = 19792; // 12 +static const uint64_t SH_FLD_SN0_RCMD_TTAG_P = 19793; // 12 +static const uint64_t SH_FLD_SN1_CRESP_ATAG_P = 19794; // 12 +static const uint64_t SH_FLD_SN1_CRESP_TTAG_P = 19795; // 12 +static const uint64_t SH_FLD_SN1_RCMD_ADDR_P = 19796; // 12 +static const uint64_t SH_FLD_SN1_RCMD_TTAG_P = 19797; // 12 +static const uint64_t SH_FLD_SN2_CRESP_ATAG_P = 19798; // 12 +static const uint64_t SH_FLD_SN2_CRESP_TTAG_P = 19799; // 12 +static const uint64_t SH_FLD_SN2_RCMD_ADDR_P = 19800; // 12 +static const uint64_t SH_FLD_SN2_RCMD_TTAG_P = 19801; // 12 +static const uint64_t SH_FLD_SN3_CRESP_ATAG_P = 19802; // 12 +static const uint64_t SH_FLD_SN3_CRESP_TTAG_P = 19803; // 12 +static const uint64_t SH_FLD_SN3_RCMD_ADDR_P = 19804; // 12 +static const uint64_t SH_FLD_SN3_RCMD_TTAG_P = 19805; // 12 +static const uint64_t SH_FLD_SND_CHIPID = 19806; // 1 +static const uint64_t SH_FLD_SND_CHIPID_LEN = 19807; // 1 +static const uint64_t SH_FLD_SND_CNT = 19808; // 1 +static const uint64_t SH_FLD_SND_CNT_LEN = 19809; // 1 +static const uint64_t SH_FLD_SND_CNT_STATUS = 19810; // 1 +static const uint64_t SH_FLD_SND_CNT_STATUS_LEN = 19811; // 1 +static const uint64_t SH_FLD_SND_ERROR = 19812; // 1 +static const uint64_t SH_FLD_SND_GROUPID = 19813; // 1 +static const uint64_t SH_FLD_SND_GROUPID_LEN = 19814; // 1 +static const uint64_t SH_FLD_SND_IN_PROGRESS = 19815; // 1 +static const uint64_t SH_FLD_SND_PHASE_STATUS = 19816; // 1 +static const uint64_t SH_FLD_SND_PHASE_STATUS_LEN = 19817; // 1 +static const uint64_t SH_FLD_SND_QID = 19818; // 1 +static const uint64_t SH_FLD_SND_RESERVATION = 19819; // 1 +static const uint64_t SH_FLD_SND_RESET = 19820; // 1 +static const uint64_t SH_FLD_SND_RETRY_COUNT = 19821; // 1 +static const uint64_t SH_FLD_SND_RETRY_COUNT_LEN = 19822; // 1 +static const uint64_t SH_FLD_SND_RETRY_COUNT_OVERCOM = 19823; // 1 +static const uint64_t SH_FLD_SND_RETRY_THRESH = 19824; // 1 +static const uint64_t SH_FLD_SND_RETRY_THRESH_LEN = 19825; // 1 +static const uint64_t SH_FLD_SND_RSVTO_DIV = 19826; // 1 +static const uint64_t SH_FLD_SND_RSVTO_DIV_LEN = 19827; // 1 +static const uint64_t SH_FLD_SND_SCOPE = 19828; // 1 +static const uint64_t SH_FLD_SND_SCOPE_LEN = 19829; // 1 +static const uint64_t SH_FLD_SND_SLS_CMD_GCRMSG = 19830; // 4 +static const uint64_t SH_FLD_SND_SLS_CMD_PREV_GCRMSG = 19831; // 4 +static const uint64_t SH_FLD_SND_SLS_USING_REG_SCRAMBLE = 19832; // 4 +static const uint64_t SH_FLD_SND_STOP = 19833; // 1 +static const uint64_t SH_FLD_SND_TYPE = 19834; // 1 +static const uint64_t SH_FLD_SNFSM_ADDR = 19835; // 12 +static const uint64_t SH_FLD_SNGL_THD_EN = 19836; // 2 +static const uint64_t SH_FLD_SNOOPER_RECOVERABLE_ERROR = 19837; // 4 +static const uint64_t SH_FLD_SNOOPER_SYS_XSTOP_ERROR = 19838; // 4 +static const uint64_t SH_FLD_SNOOP_ARRAY_CE = 19839; // 4 +static const uint64_t SH_FLD_SNOOP_ARRAY_UE = 19840; // 4 +static const uint64_t SH_FLD_SNOOP_DIS = 19841; // 8 +static const uint64_t SH_FLD_SNOP = 19842; // 43 +static const uint64_t SH_FLD_SNOP_FORCE_SG = 19843; // 43 +static const uint64_t SH_FLD_SNOP_LEN = 19844; // 43 +static const uint64_t SH_FLD_SNOP_WAIT = 19845; // 43 +static const uint64_t SH_FLD_SNOP_WAIT_LEN = 19846; // 43 +static const uint64_t SH_FLD_SNPBE_TRIGGER_ENABLE = 19847; // 2 +static const uint64_t SH_FLD_SNPBE_UOP_TRIGGER_ENABLE = 19848; // 2 +static const uint64_t SH_FLD_SNPFE_DIR_TRIGGER_ENABLE = 19849; // 2 +static const uint64_t SH_FLD_SNPFE_TRIGGER_ENABLE = 19850; // 2 +static const uint64_t SH_FLD_SNPRTAG_REGS_CE_ERR0 = 19851; // 2 +static const uint64_t SH_FLD_SNPRTAG_REGS_CE_ERR1 = 19852; // 2 +static const uint64_t SH_FLD_SNPRTAG_REGS_CE_ERR2 = 19853; // 2 +static const uint64_t SH_FLD_SNPRTAG_REGS_UE_ERR0 = 19854; // 2 +static const uint64_t SH_FLD_SNPRTAG_REGS_UE_ERR1 = 19855; // 2 +static const uint64_t SH_FLD_SNPRTAG_REGS_UE_ERR2 = 19856; // 2 +static const uint64_t SH_FLD_SNP_ERROR_INJECT_ENABLE = 19857; // 2 +static const uint64_t SH_FLD_SNP_ERROR_INJECT_TARGET = 19858; // 2 +static const uint64_t SH_FLD_SNP_ERROR_INJECT_TARGET_LEN = 19859; // 2 +static const uint64_t SH_FLD_SNP_INJECT_CONTINOUS_ERROR = 19860; // 2 +static const uint64_t SH_FLD_SNP_INJECT_DBL_ECC_ERROR = 19861; // 2 +static const uint64_t SH_FLD_SNP_MUX_PORT_SEL = 19862; // 2 +static const uint64_t SH_FLD_SNP_MUX_PORT_SEL_LEN = 19863; // 2 +static const uint64_t SH_FLD_SNP_REG_ERR0 = 19864; // 1 +static const uint64_t SH_FLD_SNP_REG_ERR1 = 19865; // 1 +static const uint64_t SH_FLD_SNP_REG_ERR2 = 19866; // 1 +static const uint64_t SH_FLD_SNP_REG_ERR3 = 19867; // 1 +static const uint64_t SH_FLD_SNP_REG_ERR4 = 19868; // 1 +static const uint64_t SH_FLD_SNP_REG_ERR5 = 19869; // 1 +static const uint64_t SH_FLD_SNP_REG_ERR6 = 19870; // 1 +static const uint64_t SH_FLD_SNS1_0_31 = 19871; // 1 +static const uint64_t SH_FLD_SNS1_0_31_LEN = 19872; // 1 +static const uint64_t SH_FLD_SNS2_UNUSED_0_31 = 19873; // 1 +static const uint64_t SH_FLD_SNS2_UNUSED_0_31_LEN = 19874; // 1 +static const uint64_t SH_FLD_SN_CRESP_ACK_DEAD = 19875; // 12 +static const uint64_t SH_FLD_SN_MACHINE_HANG = 19876; // 12 +static const uint64_t SH_FLD_SN_MSG_MAX_CREDIT = 19877; // 2 +static const uint64_t SH_FLD_SN_MSG_MAX_CREDIT_LEN = 19878; // 2 +static const uint64_t SH_FLD_SN_SC_RDATA_PARITY_ERRHOLD = 19879; // 2 +static const uint64_t SH_FLD_SN_UNSOLICITED_CRESP = 19880; // 12 +static const uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT = 19881; // 2 +static const uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN = 19882; // 2 +static const uint64_t SH_FLD_SOCKET = 19883; // 1 +static const uint64_t SH_FLD_SOCKET_LEN = 19884; // 1 +static const uint64_t SH_FLD_SOFT_CE_COUNT = 19885; // 2 +static const uint64_t SH_FLD_SOFT_CE_COUNT_LEN = 19886; // 2 +static const uint64_t SH_FLD_SOFT_MCE_COUNT = 19887; // 2 +static const uint64_t SH_FLD_SOFT_MCE_COUNT_LEN = 19888; // 2 +static const uint64_t SH_FLD_SOFT_NCE_ETE_ATTN = 19889; // 2 +static const uint64_t SH_FLD_SOURCE_SELECT = 19890; // 43 +static const uint64_t SH_FLD_SOURCE_SELECT_LEN = 19891; // 43 +static const uint64_t SH_FLD_SOURCE_SUBUNIT_0_1 = 19892; // 1 +static const uint64_t SH_FLD_SOURCE_SUBUNIT_0_1_LEN = 19893; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_CQ_IDLE_BIT = 19894; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_ECC = 19895; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB = 19896; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR = 19897; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_EG_IDLE_BIT = 19898; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD = 19899; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG = 19900; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 19901; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER = 19902; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_EN_FAST_SCRUB = 19903; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_UNUSED = 19904; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_UNUSED_LEN = 19905; // 1 +static const uint64_t SH_FLD_SOUTH_CTL_WC_IDLE_BIT = 19906; // 1 +static const uint64_t SH_FLD_SPARE = 19907; // 205 +static const uint64_t SH_FLD_SPARE0 = 19908; // 105 +static const uint64_t SH_FLD_SPARE0_LEN = 19909; // 8 +static const uint64_t SH_FLD_SPARE1 = 19910; // 9 +static const uint64_t SH_FLD_SPARE10 = 19911; // 1 +static const uint64_t SH_FLD_SPARE11 = 19912; // 14 +static const uint64_t SH_FLD_SPARE12 = 19913; // 12 +static const uint64_t SH_FLD_SPARE13 = 19914; // 1 +static const uint64_t SH_FLD_SPARE14 = 19915; // 1 +static const uint64_t SH_FLD_SPARE15 = 19916; // 1 +static const uint64_t SH_FLD_SPARE1TO1 = 19917; // 12 +static const uint64_t SH_FLD_SPARE1TO1_LEN = 19918; // 12 +static const uint64_t SH_FLD_SPARE2 = 19919; // 6 +static const uint64_t SH_FLD_SPARE2TO1 = 19920; // 12 +static const uint64_t SH_FLD_SPARE2TO1_LEN = 19921; // 12 +static const uint64_t SH_FLD_SPARE3 = 19922; // 1 +static const uint64_t SH_FLD_SPARE41_43 = 19923; // 24 +static const uint64_t SH_FLD_SPARE41_43_LEN = 19924; // 24 +static const uint64_t SH_FLD_SPARE4_TIMEOUT = 19925; // 6 +static const uint64_t SH_FLD_SPARE4_TIMEOUT_LEN = 19926; // 6 +static const uint64_t SH_FLD_SPARE7 = 19927; // 1 +static const uint64_t SH_FLD_SPARE8 = 19928; // 1 +static const uint64_t SH_FLD_SPARE9 = 19929; // 1 +static const uint64_t SH_FLD_SPARED = 19930; // 4 +static const uint64_t SH_FLD_SPARED_LEN = 19931; // 4 +static const uint64_t SH_FLD_SPARES = 19932; // 4 +static const uint64_t SH_FLD_SPARES1 = 19933; // 4 +static const uint64_t SH_FLD_SPARES1_LEN = 19934; // 4 +static const uint64_t SH_FLD_SPARES2 = 19935; // 4 +static const uint64_t SH_FLD_SPARES2_LEN = 19936; // 4 +static const uint64_t SH_FLD_SPARES_LEN = 19937; // 4 +static const uint64_t SH_FLD_SPARE_0 = 19938; // 4 +static const uint64_t SH_FLD_SPARE_0_LEN = 19939; // 4 +static const uint64_t SH_FLD_SPARE_10 = 19940; // 98 +static const uint64_t SH_FLD_SPARE_11 = 19941; // 17 +static const uint64_t SH_FLD_SPARE_12 = 19942; // 100 +static const uint64_t SH_FLD_SPARE_13 = 19943; // 100 +static const uint64_t SH_FLD_SPARE_14 = 19944; // 100 +static const uint64_t SH_FLD_SPARE_15 = 19945; // 112 +static const uint64_t SH_FLD_SPARE_16 = 19946; // 14 +static const uint64_t SH_FLD_SPARE_17 = 19947; // 14 +static const uint64_t SH_FLD_SPARE_18 = 19948; // 98 +static const uint64_t SH_FLD_SPARE_19 = 19949; // 106 +static const uint64_t SH_FLD_SPARE_1_3 = 19950; // 1 +static const uint64_t SH_FLD_SPARE_1_3_LEN = 19951; // 1 +static const uint64_t SH_FLD_SPARE_2 = 19952; // 4 +static const uint64_t SH_FLD_SPARE_20 = 19953; // 4 +static const uint64_t SH_FLD_SPARE_20_23 = 19954; // 6 +static const uint64_t SH_FLD_SPARE_20_23_LEN = 19955; // 6 +static const uint64_t SH_FLD_SPARE_21 = 19956; // 4 +static const uint64_t SH_FLD_SPARE_22 = 19957; // 4 +static const uint64_t SH_FLD_SPARE_22_23 = 19958; // 12 +static const uint64_t SH_FLD_SPARE_22_23_LEN = 19959; // 12 +static const uint64_t SH_FLD_SPARE_23 = 19960; // 4 +static const uint64_t SH_FLD_SPARE_24 = 19961; // 4 +static const uint64_t SH_FLD_SPARE_24_31 = 19962; // 1 +static const uint64_t SH_FLD_SPARE_24_31_LEN = 19963; // 1 +static const uint64_t SH_FLD_SPARE_25 = 19964; // 4 +static const uint64_t SH_FLD_SPARE_26 = 19965; // 4 +static const uint64_t SH_FLD_SPARE_27 = 19966; // 4 +static const uint64_t SH_FLD_SPARE_28 = 19967; // 4 +static const uint64_t SH_FLD_SPARE_28_31 = 19968; // 12 +static const uint64_t SH_FLD_SPARE_28_31_LEN = 19969; // 12 +static const uint64_t SH_FLD_SPARE_29 = 19970; // 4 +static const uint64_t SH_FLD_SPARE_2_MASK = 19971; // 1 +static const uint64_t SH_FLD_SPARE_3 = 19972; // 102 +static const uint64_t SH_FLD_SPARE_30 = 19973; // 4 +static const uint64_t SH_FLD_SPARE_31 = 19974; // 5 +static const uint64_t SH_FLD_SPARE_32_33 = 19975; // 12 +static const uint64_t SH_FLD_SPARE_32_33_LEN = 19976; // 12 +static const uint64_t SH_FLD_SPARE_3_MASK = 19977; // 1 +static const uint64_t SH_FLD_SPARE_58 = 19978; // 4 +static const uint64_t SH_FLD_SPARE_59 = 19979; // 4 +static const uint64_t SH_FLD_SPARE_59_61 = 19980; // 2 +static const uint64_t SH_FLD_SPARE_59_61_LEN = 19981; // 2 +static const uint64_t SH_FLD_SPARE_6 = 19982; // 96 +static const uint64_t SH_FLD_SPARE_60 = 19983; // 4 +static const uint64_t SH_FLD_SPARE_61 = 19984; // 4 +static const uint64_t SH_FLD_SPARE_63 = 19985; // 3 +static const uint64_t SH_FLD_SPARE_6_7 = 19986; // 16 +static const uint64_t SH_FLD_SPARE_6_7_LEN = 19987; // 16 +static const uint64_t SH_FLD_SPARE_7 = 19988; // 96 +static const uint64_t SH_FLD_SPARE_8 = 19989; // 2 +static const uint64_t SH_FLD_SPARE_8_11 = 19990; // 6 +static const uint64_t SH_FLD_SPARE_8_11_LEN = 19991; // 6 +static const uint64_t SH_FLD_SPARE_9 = 19992; // 2 +static const uint64_t SH_FLD_SPARE_CONTROL = 19993; // 90 +static const uint64_t SH_FLD_SPARE_CONTROL_LEN = 19994; // 90 +static const uint64_t SH_FLD_SPARE_CTRL = 19995; // 96 +static const uint64_t SH_FLD_SPARE_CTRL_LEN = 19996; // 96 +static const uint64_t SH_FLD_SPARE_DI_CONTROL = 19997; // 3 +static const uint64_t SH_FLD_SPARE_ERROR = 19998; // 1 +static const uint64_t SH_FLD_SPARE_ERROR_MASK = 19999; // 1 +static const uint64_t SH_FLD_SPARE_ERR_38 = 20000; // 1 +static const uint64_t SH_FLD_SPARE_ERR_38_MASK = 20001; // 1 +static const uint64_t SH_FLD_SPARE_FENCE_CONTROL = 20002; // 3 +static const uint64_t SH_FLD_SPARE_FILT0_PLL = 20003; // 3 +static const uint64_t SH_FLD_SPARE_FILT1_PLL = 20004; // 3 +static const uint64_t SH_FLD_SPARE_LEN = 20005; // 178 +static const uint64_t SH_FLD_SPARE_LT = 20006; // 162 +static const uint64_t SH_FLD_SPARE_LT_LEN = 20007; // 72 +static const uint64_t SH_FLD_SPARE_MODE_0 = 20008; // 116 +static const uint64_t SH_FLD_SPARE_MODE_1 = 20009; // 116 +static const uint64_t SH_FLD_SPARE_MODE_2 = 20010; // 116 +static const uint64_t SH_FLD_SPARE_MODE_3 = 20011; // 116 +static const uint64_t SH_FLD_SPARE_N = 20012; // 2 +static const uint64_t SH_FLD_SPARE_N_LEN = 20013; // 2 +static const uint64_t SH_FLD_SPARE_PIB_CONTROL = 20014; // 3 +static const uint64_t SH_FLD_SPARE_RI_CONTROL = 20015; // 3 +static const uint64_t SH_FLD_SPC_WKUP_OVERRIDE = 20016; // 30 +static const uint64_t SH_FLD_SPECIAL_ATTENTION = 20017; // 1 +static const uint64_t SH_FLD_SPECIAL_WAKEUP_C0 = 20018; // 24 +static const uint64_t SH_FLD_SPECIAL_WAKEUP_C1 = 20019; // 24 +static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 20020; // 12 +static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 20021; // 12 +static const uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE = 20022; // 30 +static const uint64_t SH_FLD_SPECIAL_WKUP_DONE = 20023; // 180 +static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_C0 = 20024; // 12 +static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_C1 = 20025; // 12 +static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL = 20026; // 30 +static const uint64_t SH_FLD_SPECIAL_WKUP_PROTOCOL = 20027; // 30 +static const uint64_t SH_FLD_SPECIAL_WKUP_REQUESTED = 20028; // 30 +static const uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT = 20029; // 1 +static const uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN = 20030; // 1 +static const uint64_t SH_FLD_SPEC_CILD_G = 20031; // 1 +static const uint64_t SH_FLD_SPEC_HPC_DIR_STATE = 20032; // 2 +static const uint64_t SH_FLD_SPEC_HPC_DIR_STATE_LEN = 20033; // 2 +static const uint64_t SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE = 20034; // 4 +static const uint64_t SH_FLD_SPEDIV = 20035; // 20 +static const uint64_t SH_FLD_SPEDIV_LEN = 20036; // 20 +static const uint64_t SH_FLD_SPEED_SELECT = 20037; // 2 +static const uint64_t SH_FLD_SPEED_SELECT_LEN = 20038; // 2 +static const uint64_t SH_FLD_SPLURGE = 20039; // 1 +static const uint64_t SH_FLD_SPL_ONLY = 20040; // 1 +static const uint64_t SH_FLD_SPRG0 = 20041; // 21 +static const uint64_t SH_FLD_SPRG0_LEN = 20042; // 21 +static const uint64_t SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG = 20043; // 4 +static const uint64_t SH_FLD_SPURR_OVERFLOW_ERROR = 20044; // 96 +static const uint64_t SH_FLD_SPURR_PARITY_ERROR = 20045; // 96 +static const uint64_t SH_FLD_SP_COUNT_LT = 20046; // 86 +static const uint64_t SH_FLD_SP_COUNT_LT_LEN = 20047; // 86 +static const uint64_t SH_FLD_SQ_LFSR_CNTL = 20048; // 8 +static const uint64_t SH_FLD_SQ_LFSR_CNTL_LEN = 20049; // 8 +static const uint64_t SH_FLD_SR = 20050; // 8 +static const uint64_t SH_FLD_SRAM_ABIST_DONE_DC = 20051; // 43 +static const uint64_t SH_FLD_SRAM_ACCESS_MODE = 20052; // 16 +static const uint64_t SH_FLD_SRAM_ADDRESS = 20053; // 16 +static const uint64_t SH_FLD_SRAM_ADDRESS_LEN = 20054; // 16 +static const uint64_t SH_FLD_SRAM_CE = 20055; // 13 +static const uint64_t SH_FLD_SRAM_CERRRPT = 20056; // 1 +static const uint64_t SH_FLD_SRAM_CERRRPT_LEN = 20057; // 1 +static const uint64_t SH_FLD_SRAM_DATA = 20058; // 16 +static const uint64_t SH_FLD_SRAM_DATA_LEN = 20059; // 16 +static const uint64_t SH_FLD_SRAM_HIGH_PRIORITY = 20060; // 4 +static const uint64_t SH_FLD_SRAM_HIGH_PRIORITY_LEN = 20061; // 4 +static const uint64_t SH_FLD_SRAM_LOW_PRIORITY = 20062; // 4 +static const uint64_t SH_FLD_SRAM_LOW_PRIORITY_LEN = 20063; // 4 +static const uint64_t SH_FLD_SRAM_SCRUB_ENABLE = 20064; // 16 +static const uint64_t SH_FLD_SRAM_SCRUB_ERR = 20065; // 13 +static const uint64_t SH_FLD_SRAM_SCRUB_INDEX = 20066; // 16 +static const uint64_t SH_FLD_SRAM_SCRUB_INDEX_LEN = 20067; // 16 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0 = 20068; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0_MASK = 20069; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1 = 20070; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1_MASK = 20071; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2 = 20072; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2_MASK = 20073; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3 = 20074; // 1 +static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3_MASK = 20075; // 1 +static const uint64_t SH_FLD_SRAM_UE = 20076; // 13 +static const uint64_t SH_FLD_SRC_BUS = 20077; // 24 +static const uint64_t SH_FLD_SRC_BUS_LEN = 20078; // 24 +static const uint64_t SH_FLD_SRC_DDE = 20079; // 3 +static const uint64_t SH_FLD_SRC_DDE_LEN = 20080; // 3 +static const uint64_t SH_FLD_SRC_MASK_TBD = 20081; // 24 +static const uint64_t SH_FLD_SRC_MASK_TBD_LEN = 20082; // 24 +static const uint64_t SH_FLD_SRC_SEL_EQ1_ERR = 20083; // 1 +static const uint64_t SH_FLD_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT = 20084; // 2 +static const uint64_t SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 20085; // 2 +static const uint64_t SH_FLD_SRR0 = 20086; // 96 +static const uint64_t SH_FLD_SRR0_LEN = 20087; // 96 +static const uint64_t SH_FLD_SRT_CE = 20088; // 1 +static const uint64_t SH_FLD_SRT_CE_MASK = 20089; // 1 +static const uint64_t SH_FLD_SRT_DATAOUT_PERR = 20090; // 1 +static const uint64_t SH_FLD_SRT_DATAOUT_PERR_MASK = 20091; // 1 +static const uint64_t SH_FLD_SRT_ERROR = 20092; // 1 +static const uint64_t SH_FLD_SRT_FSM_ERR = 20093; // 1 +static const uint64_t SH_FLD_SRT_FSM_ERR_MASK = 20094; // 1 +static const uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR = 20095; // 1 +static const uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR_MASK = 20096; // 1 +static const uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR = 20097; // 1 +static const uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR_MASK = 20098; // 1 +static const uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY = 20099; // 1 +static const uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY_MASK = 20100; // 1 +static const uint64_t SH_FLD_SRT_READ_ERROR = 20101; // 1 +static const uint64_t SH_FLD_SRT_READ_ERROR_MASK = 20102; // 1 +static const uint64_t SH_FLD_SRT_UE = 20103; // 1 +static const uint64_t SH_FLD_SRT_UE_MASK = 20104; // 1 +static const uint64_t SH_FLD_SRT_WRITE_ERROR = 20105; // 1 +static const uint64_t SH_FLD_SRT_WRITE_ERROR_MASK = 20106; // 1 +static const uint64_t SH_FLD_SR_LEN = 20107; // 8 +static const uint64_t SH_FLD_SSA_ECC_HI_CE_ERRHOLD = 20108; // 2 +static const uint64_t SH_FLD_SSA_ECC_HI_SUE_ERRHOLD = 20109; // 2 +static const uint64_t SH_FLD_SSA_ECC_HI_UE_ERRHOLD = 20110; // 2 +static const uint64_t SH_FLD_SSA_ECC_LO_CE_ERRHOLD = 20111; // 2 +static const uint64_t SH_FLD_SSA_ECC_LO_SUE_ERRHOLD = 20112; // 2 +static const uint64_t SH_FLD_SSA_ECC_LO_UE_ERRHOLD = 20113; // 2 +static const uint64_t SH_FLD_SSCGEN = 20114; // 3 +static const uint64_t SH_FLD_SS_ENABLE = 20115; // 6 +static const uint64_t SH_FLD_ST2_RESET_PERIOD = 20116; // 1 +static const uint64_t SH_FLD_ST2_RESET_PERIOD_LEN = 20117; // 1 +static const uint64_t SH_FLD_STACK = 20118; // 16 +static const uint64_t SH_FLD_STACK_LEN = 20119; // 16 +static const uint64_t SH_FLD_STAGGERED_PATTERN = 20120; // 8 +static const uint64_t SH_FLD_START = 20121; // 59 +static const uint64_t SH_FLD_START0 = 20122; // 5 +static const uint64_t SH_FLD_START1 = 20123; // 5 +static const uint64_t SH_FLD_STARTING_ADDRESS = 20124; // 4 +static const uint64_t SH_FLD_STARTING_ADDRESS_LEN = 20125; // 4 +static const uint64_t SH_FLD_STARTS_BIST = 20126; // 43 +static const uint64_t SH_FLD_START_BOOT_SEQUENCER = 20127; // 1 +static const uint64_t SH_FLD_START_CAL = 20128; // 1 +static const uint64_t SH_FLD_START_DC_CALIBRATE = 20129; // 4 +static const uint64_t SH_FLD_START_DESKEW = 20130; // 4 +static const uint64_t SH_FLD_START_EYE_OPT = 20131; // 4 +static const uint64_t SH_FLD_START_FUNC_MODE = 20132; // 4 +static const uint64_t SH_FLD_START_INIT = 20133; // 8 +static const uint64_t SH_FLD_START_JTAG_CMD = 20134; // 1 +static const uint64_t SH_FLD_START_LANE_ID = 20135; // 8 +static const uint64_t SH_FLD_START_LANE_ID_LEN = 20136; // 8 +static const uint64_t SH_FLD_START_LEN = 20137; // 36 +static const uint64_t SH_FLD_START_PPE_ADDR = 20138; // 4 +static const uint64_t SH_FLD_START_PPE_ADDR_LEN = 20139; // 4 +static const uint64_t SH_FLD_START_READ = 20140; // 1 +static const uint64_t SH_FLD_START_REPAIR = 20141; // 4 +static const uint64_t SH_FLD_START_RESTART_VECTOR0 = 20142; // 1 +static const uint64_t SH_FLD_START_RESTART_VECTOR1 = 20143; // 1 +static const uint64_t SH_FLD_START_SEEPROM_ADDRESS = 20144; // 4 +static const uint64_t SH_FLD_START_SEEPROM_ADDRESS_LEN = 20145; // 4 +static const uint64_t SH_FLD_START_TRANS = 20146; // 1 +static const uint64_t SH_FLD_START_WIRETEST = 20147; // 4 +static const uint64_t SH_FLD_START_WRITE = 20148; // 1 +static const uint64_t SH_FLD_START_WR_ADDR = 20149; // 2 +static const uint64_t SH_FLD_START_WR_ADDR_LEN = 20150; // 2 +static const uint64_t SH_FLD_STAT = 20151; // 45 +static const uint64_t SH_FLD_STATE = 20152; // 80 +static const uint64_t SH_FLD_STATE_LEN = 20153; // 79 +static const uint64_t SH_FLD_STATE_LOSS_ENABLE_A_N = 20154; // 96 +static const uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY = 20155; // 1 +static const uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN = 20156; // 1 +static const uint64_t SH_FLD_STATIC_MAX_SPARES_EXCEEDED = 20157; // 8 +static const uint64_t SH_FLD_STATIC_SPARE_DEPLOYED = 20158; // 8 +static const uint64_t SH_FLD_STATUS = 20159; // 5 +static const uint64_t SH_FLD_STATUS_INVALID_CRESP = 20160; // 2 +static const uint64_t SH_FLD_STATUS_LEN = 20161; // 2 +static const uint64_t SH_FLD_STATUS_PARITY_ERROR = 20162; // 2 +static const uint64_t SH_FLD_STATUS_PERV = 20163; // 129 +static const uint64_t SH_FLD_STATUS_REC_DROPPED_Q = 20164; // 26 +static const uint64_t SH_FLD_STATUS_REG = 20165; // 1 +static const uint64_t SH_FLD_STATUS_REG_LEN = 20166; // 1 +static const uint64_t SH_FLD_STATUS_SCOM_ERROR = 20167; // 26 +static const uint64_t SH_FLD_STATUS_TRIG_DROPPED_Q = 20168; // 26 +static const uint64_t SH_FLD_STATUS_UNIT1 = 20169; // 129 +static const uint64_t SH_FLD_STATUS_UNIT10 = 20170; // 129 +static const uint64_t SH_FLD_STATUS_UNIT2 = 20171; // 129 +static const uint64_t SH_FLD_STATUS_UNIT3 = 20172; // 129 +static const uint64_t SH_FLD_STATUS_UNIT4 = 20173; // 129 +static const uint64_t SH_FLD_STATUS_UNIT5 = 20174; // 129 +static const uint64_t SH_FLD_STATUS_UNIT6 = 20175; // 129 +static const uint64_t SH_FLD_STATUS_UNIT7 = 20176; // 129 +static const uint64_t SH_FLD_STATUS_UNIT8 = 20177; // 129 +static const uint64_t SH_FLD_STATUS_UNIT9 = 20178; // 129 +static const uint64_t SH_FLD_STATUS_UNUSED = 20179; // 24 +static const uint64_t SH_FLD_STATUS_UNUSED_LEN = 20180; // 24 +static const uint64_t SH_FLD_STAT_LEN = 20181; // 45 +static const uint64_t SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE = 20182; // 1 +static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION = 20183; // 1 +static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR = 20184; // 3 +static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 20185; // 3 +static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN = 20186; // 1 +static const uint64_t SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 20187; // 1 +static const uint64_t SH_FLD_STEP_CHECK_STEP_SELECT = 20188; // 1 +static const uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT = 20189; // 1 +static const uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN = 20190; // 1 +static const uint64_t SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE = 20191; // 1 +static const uint64_t SH_FLD_STICKY_CACHE_VDM_DATA = 20192; // 12 +static const uint64_t SH_FLD_STICKY_CACHE_VDM_DATA_LEN = 20193; // 12 +static const uint64_t SH_FLD_STICKY_CORE0_VDM_DATA = 20194; // 12 +static const uint64_t SH_FLD_STICKY_CORE0_VDM_DATA_LEN = 20195; // 12 +static const uint64_t SH_FLD_STICKY_CORE1_VDM_DATA = 20196; // 12 +static const uint64_t SH_FLD_STICKY_CORE1_VDM_DATA_LEN = 20197; // 12 +static const uint64_t SH_FLD_STICKY_CORE2_VDM_DATA = 20198; // 12 +static const uint64_t SH_FLD_STICKY_CORE2_VDM_DATA_LEN = 20199; // 12 +static const uint64_t SH_FLD_STICKY_CORE3_VDM_DATA = 20200; // 12 +static const uint64_t SH_FLD_STICKY_CORE3_VDM_DATA_LEN = 20201; // 12 +static const uint64_t SH_FLD_STICKY_ERROR_INJECT_ENABLE = 20202; // 1 +static const uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY = 20203; // 12 +static const uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN = 20204; // 12 +static const uint64_t SH_FLD_STOP = 20205; // 6 +static const uint64_t SH_FLD_STOP1_ACTIVE_ENABLE = 20206; // 12 +static const uint64_t SH_FLD_STOPPED = 20207; // 2 +static const uint64_t SH_FLD_STOP_ACTIVE_MASK = 20208; // 12 +static const uint64_t SH_FLD_STOP_CORR_EN = 20209; // 6 +static const uint64_t SH_FLD_STOP_ERROR_0 = 20210; // 4 +static const uint64_t SH_FLD_STOP_ERROR_1 = 20211; // 2 +static const uint64_t SH_FLD_STOP_ERROR_2 = 20212; // 2 +static const uint64_t SH_FLD_STOP_ERROR_3 = 20213; // 2 +static const uint64_t SH_FLD_STOP_EXIT_TYPE_SEL = 20214; // 24 +static const uint64_t SH_FLD_STOP_GATED = 20215; // 150 +static const uint64_t SH_FLD_STOP_ON_ERR = 20216; // 45 +static const uint64_t SH_FLD_STOP_ON_RECOV_ERR_SELECTION = 20217; // 43 +static const uint64_t SH_FLD_STOP_ON_SPATTN_SELECTION = 20218; // 43 +static const uint64_t SH_FLD_STOP_ON_XSTOP_SELECTION = 20219; // 43 +static const uint64_t SH_FLD_STOP_OVERRIDE_MODE = 20220; // 12 +static const uint64_t SH_FLD_STOP_RECOVERY_NOTIFY_PRD = 20221; // 1 +static const uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N = 20222; // 96 +static const uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN = 20223; // 96 +static const uint64_t SH_FLD_STOP_RUNN_ON_XSTOP = 20224; // 43 +static const uint64_t SH_FLD_STOP_TRANSITION = 20225; // 150 +static const uint64_t SH_FLD_STOP_TRANSITION_LEN = 20226; // 150 +static const uint64_t SH_FLD_STORE_ADDRESS = 20227; // 21 +static const uint64_t SH_FLD_STORE_ADDRESS_LEN = 20228; // 21 +static const uint64_t SH_FLD_STORE_ON_TRIG_MODE = 20229; // 90 +static const uint64_t SH_FLD_STORE_TIMEOUT = 20230; // 12 +static const uint64_t SH_FLD_STPM0_RP2_SETP_PERR_HOLD_OUT = 20231; // 24 +static const uint64_t SH_FLD_STPM1_RP2_SETP_PERR_HOLD_OUT = 20232; // 24 +static const uint64_t SH_FLD_STPM2_RP1_SETP_PERR_HOLD_OUT = 20233; // 24 +static const uint64_t SH_FLD_STPM3_RP1_SETP_PERR_HOLD_OUT = 20234; // 24 +static const uint64_t SH_FLD_STQ_DATA_HANG = 20235; // 1 +static const uint64_t SH_FLD_STQ_DATA_PARITY_ERR = 20236; // 12 +static const uint64_t SH_FLD_STQ_ERR = 20237; // 12 +static const uint64_t SH_FLD_STQ_ERR_LEN = 20238; // 12 +static const uint64_t SH_FLD_STQ_FSM_PERR = 20239; // 1 +static const uint64_t SH_FLD_STQ_HW_MAX_0_4 = 20240; // 1 +static const uint64_t SH_FLD_STQ_HW_MAX_0_4_LEN = 20241; // 1 +static const uint64_t SH_FLD_STQ_HW_MIN_0_4 = 20242; // 1 +static const uint64_t SH_FLD_STQ_HW_MIN_0_4_LEN = 20243; // 1 +static const uint64_t SH_FLD_STQ_HYP_MAX_0_4 = 20244; // 1 +static const uint64_t SH_FLD_STQ_HYP_MAX_0_4_LEN = 20245; // 1 +static const uint64_t SH_FLD_STQ_HYP_MIN_0_4 = 20246; // 1 +static const uint64_t SH_FLD_STQ_HYP_MIN_0_4_LEN = 20247; // 1 +static const uint64_t SH_FLD_STQ_IPI_MAX_0_4 = 20248; // 1 +static const uint64_t SH_FLD_STQ_IPI_MAX_0_4_LEN = 20249; // 1 +static const uint64_t SH_FLD_STQ_IPI_MIN_0_4 = 20250; // 1 +static const uint64_t SH_FLD_STQ_IPI_MIN_0_4_LEN = 20251; // 1 +static const uint64_t SH_FLD_STQ_OS_MAX_0_4 = 20252; // 1 +static const uint64_t SH_FLD_STQ_OS_MAX_0_4_LEN = 20253; // 1 +static const uint64_t SH_FLD_STQ_OS_MIN_0_4 = 20254; // 1 +static const uint64_t SH_FLD_STQ_OS_MIN_0_4_LEN = 20255; // 1 +static const uint64_t SH_FLD_STQ_RDI_MAX_0_4 = 20256; // 1 +static const uint64_t SH_FLD_STQ_RDI_MAX_0_4_LEN = 20257; // 1 +static const uint64_t SH_FLD_STQ_RDI_MIN_0_4 = 20258; // 1 +static const uint64_t SH_FLD_STQ_RDI_MIN_0_4_LEN = 20259; // 1 +static const uint64_t SH_FLD_STQ_REG_MAX_0_4 = 20260; // 1 +static const uint64_t SH_FLD_STQ_REG_MAX_0_4_LEN = 20261; // 1 +static const uint64_t SH_FLD_STQ_REG_MIN_0_4 = 20262; // 1 +static const uint64_t SH_FLD_STQ_REG_MIN_0_4_LEN = 20263; // 1 +static const uint64_t SH_FLD_STQ_THR_MAX_0_4 = 20264; // 1 +static const uint64_t SH_FLD_STQ_THR_MAX_0_4_LEN = 20265; // 1 +static const uint64_t SH_FLD_STQ_THR_MIN_0_4 = 20266; // 1 +static const uint64_t SH_FLD_STQ_THR_MIN_0_4_LEN = 20267; // 1 +static const uint64_t SH_FLD_STQ_TYPE = 20268; // 12 +static const uint64_t SH_FLD_STQ_TYPE_LEN = 20269; // 12 +static const uint64_t SH_FLD_STQ_VPC_MAX_0_4 = 20270; // 1 +static const uint64_t SH_FLD_STQ_VPC_MAX_0_4_LEN = 20271; // 1 +static const uint64_t SH_FLD_STQ_VPC_MIN_0_4 = 20272; // 1 +static const uint64_t SH_FLD_STQ_VPC_MIN_0_4_LEN = 20273; // 1 +static const uint64_t SH_FLD_STREAM_MODE = 20274; // 4 +static const uint64_t SH_FLD_STREAM_TYPE = 20275; // 4 +static const uint64_t SH_FLD_STRICT_IPI_RULES = 20276; // 1 +static const uint64_t SH_FLD_STRICT_ORDER = 20277; // 1 +static const uint64_t SH_FLD_STROBE_WINDOW_EN = 20278; // 43 +static const uint64_t SH_FLD_STTRTOGX = 20279; // 1 +static const uint64_t SH_FLD_ST_ACK_DEAD = 20280; // 12 +static const uint64_t SH_FLD_ST_ADDR_ERR = 20281; // 12 +static const uint64_t SH_FLD_ST_CLASS_ACK_DEAD = 20282; // 2 +static const uint64_t SH_FLD_ST_CLASS_ARE_ERROR = 20283; // 2 +static const uint64_t SH_FLD_ST_CLASS_CMD_ADDR_ERR = 20284; // 4 +static const uint64_t SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 20285; // 4 +static const uint64_t SH_FLD_ST_ECC_CE = 20286; // 1 +static const uint64_t SH_FLD_ST_ECC_UE = 20287; // 1 +static const uint64_t SH_FLD_SUE_0 = 20288; // 8 +static const uint64_t SH_FLD_SUE_1 = 20289; // 8 +static const uint64_t SH_FLD_SUE_DIS_BR = 20290; // 3 +static const uint64_t SH_FLD_SUE_DIS_BR_PERR = 20291; // 3 +static const uint64_t SH_FLD_SUE_DIS_IR = 20292; // 3 +static const uint64_t SH_FLD_SUE_DIS_IR_PERR = 20293; // 3 +static const uint64_t SH_FLD_SUE_DIS_OR = 20294; // 3 +static const uint64_t SH_FLD_SUE_DIS_OR_PERR = 20295; // 3 +static const uint64_t SH_FLD_SUE_DIS_PR = 20296; // 3 +static const uint64_t SH_FLD_SUE_DIS_PT = 20297; // 3 +static const uint64_t SH_FLD_SUMMARY = 20298; // 1 +static const uint64_t SH_FLD_SUOP_ERROR_1 = 20299; // 4 +static const uint64_t SH_FLD_SUOP_ERROR_2 = 20300; // 4 +static const uint64_t SH_FLD_SUOP_ERROR_3 = 20301; // 4 +static const uint64_t SH_FLD_SUPPRESS = 20302; // 301 +static const uint64_t SH_FLD_SUPPRESS_LAST_RUNN_CLK = 20303; // 43 +static const uint64_t SH_FLD_SWC_VALUE = 20304; // 1 +static const uint64_t SH_FLD_SWC_VALUE_LEN = 20305; // 1 +static const uint64_t SH_FLD_SWITCH_SYNC_ERROR_DISABLE = 20306; // 1 +static const uint64_t SH_FLD_SYM_CPB_CHECK_DISABLE = 20307; // 1 +static const uint64_t SH_FLD_SYM_MAX_INRD = 20308; // 1 +static const uint64_t SH_FLD_SYM_MAX_INRD_LEN = 20309; // 1 +static const uint64_t SH_FLD_SYNC = 20310; // 84 +static const uint64_t SH_FLD_SYNCEN = 20311; // 7 +static const uint64_t SH_FLD_SYNC_BIT_SEL = 20312; // 194 +static const uint64_t SH_FLD_SYNC_BIT_SEL_LEN = 20313; // 194 +static const uint64_t SH_FLD_SYNC_BRCST = 20314; // 43 +static const uint64_t SH_FLD_SYNC_BRCST_LEN = 20315; // 43 +static const uint64_t SH_FLD_SYNC_BRK = 20316; // 1 +static const uint64_t SH_FLD_SYNC_BRK_LEN = 20317; // 1 +static const uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT = 20318; // 1 +static const uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT_LEN = 20319; // 1 +static const uint64_t SH_FLD_SYNC_DONE = 20320; // 2 +static const uint64_t SH_FLD_SYNC_DONE_LEN = 20321; // 2 +static const uint64_t SH_FLD_SYNC_FENCE = 20322; // 4 +static const uint64_t SH_FLD_SYNC_GO_CH0 = 20323; // 4 +static const uint64_t SH_FLD_SYNC_GO_CH1 = 20324; // 4 +static const uint64_t SH_FLD_SYNC_HEADER_ERROR_RATE = 20325; // 2 +static const uint64_t SH_FLD_SYNC_HEADER_ERROR_RATE_LEN = 20326; // 2 +static const uint64_t SH_FLD_SYNC_MODE = 20327; // 4 +static const uint64_t SH_FLD_SYNC_REPLAY_COUNT = 20328; // 4 +static const uint64_t SH_FLD_SYNC_REPLAY_COUNT_LEN = 20329; // 4 +static const uint64_t SH_FLD_SYNC_RESERVED = 20330; // 4 +static const uint64_t SH_FLD_SYNC_RESERVED_LEN = 20331; // 4 +static const uint64_t SH_FLD_SYNC_RESET = 20332; // 1 +static const uint64_t SH_FLD_SYNC_TYPE = 20333; // 4 +static const uint64_t SH_FLD_SYNC_TYPE_LEN = 20334; // 4 +static const uint64_t SH_FLD_SYNC_WAIT = 20335; // 1 +static const uint64_t SH_FLD_SYNC_WAIT_LEN = 20336; // 1 +static const uint64_t SH_FLD_SYNDROME = 20337; // 8 +static const uint64_t SH_FLD_SYNDROME_LEN = 20338; // 8 +static const uint64_t SH_FLD_SYN_HI_0_7 = 20339; // 1 +static const uint64_t SH_FLD_SYN_HI_0_7_LEN = 20340; // 1 +static const uint64_t SH_FLD_SYN_LO_0_7 = 20341; // 1 +static const uint64_t SH_FLD_SYN_LO_0_7_LEN = 20342; // 1 +static const uint64_t SH_FLD_SYSCLK_2X_MEMINTCLKO = 20343; // 8 +static const uint64_t SH_FLD_SYSCLK_RESET = 20344; // 8 +static const uint64_t SH_FLD_SYSMAP_SM_NOT_LG_SEL = 20345; // 12 +static const uint64_t SH_FLD_SYSTEM = 20346; // 2 +static const uint64_t SH_FLD_SYSTEM_ATTENTION = 20347; // 1 +static const uint64_t SH_FLD_SYSTEM_ATTENTION_HIGH = 20348; // 1 +static const uint64_t SH_FLD_SYSTEM_CHECKSTOP = 20349; // 1 +static const uint64_t SH_FLD_SYSTEM_FAST_INIT = 20350; // 43 +static const uint64_t SH_FLD_SYSTEM_LEN = 20351; // 2 +static const uint64_t SH_FLD_SYSTEM_RESET = 20352; // 1 +static const uint64_t SH_FLD_S_PATH_0_PARITY = 20353; // 4 +static const uint64_t SH_FLD_S_PATH_0_STEP_CHECK = 20354; // 4 +static const uint64_t SH_FLD_S_PATH_0_STEP_CHECK_VALID = 20355; // 1 +static const uint64_t SH_FLD_S_PATH_1_PARITY = 20356; // 4 +static const uint64_t SH_FLD_S_PATH_1_STEP_CHECK = 20357; // 4 +static const uint64_t SH_FLD_S_PATH_1_STEP_CHECK_VALID = 20358; // 1 +static const uint64_t SH_FLD_S_PATH_SELECT = 20359; // 1 +static const uint64_t SH_FLD_T0 = 20360; // 24 +static const uint64_t SH_FLD_T0_0_TO_63 = 20361; // 24 +static const uint64_t SH_FLD_T0_0_TO_63_LEN = 20362; // 24 +static const uint64_t SH_FLD_T0_CORE_MAINT = 20363; // 24 +static const uint64_t SH_FLD_T0_HSPRG0 = 20364; // 24 +static const uint64_t SH_FLD_T0_HSPRG0_LEN = 20365; // 24 +static const uint64_t SH_FLD_T0_HSPRG1 = 20366; // 24 +static const uint64_t SH_FLD_T0_HSPRG1_LEN = 20367; // 24 +static const uint64_t SH_FLD_T0_IC = 20368; // 24 +static const uint64_t SH_FLD_T0_ICT_EMPTY = 20369; // 24 +static const uint64_t SH_FLD_T0_IC_LEN = 20370; // 24 +static const uint64_t SH_FLD_T0_LEN = 20371; // 24 +static const uint64_t SH_FLD_T0_LSU_QUIESCED = 20372; // 24 +static const uint64_t SH_FLD_T0_RUN_Q = 20373; // 24 +static const uint64_t SH_FLD_T0_SPRG0 = 20374; // 24 +static const uint64_t SH_FLD_T0_SPRG0_LEN = 20375; // 24 +static const uint64_t SH_FLD_T0_SPRG1 = 20376; // 24 +static const uint64_t SH_FLD_T0_SPRG1_LEN = 20377; // 24 +static const uint64_t SH_FLD_T0_SPRG2 = 20378; // 24 +static const uint64_t SH_FLD_T0_SPRG2_LEN = 20379; // 24 +static const uint64_t SH_FLD_T0_SPRG3 = 20380; // 24 +static const uint64_t SH_FLD_T0_SPRG3_LEN = 20381; // 24 +static const uint64_t SH_FLD_T0_STEP_SUCCESS = 20382; // 24 +static const uint64_t SH_FLD_T0_THREAD_QUIESCED = 20383; // 24 +static const uint64_t SH_FLD_T1 = 20384; // 24 +static const uint64_t SH_FLD_T1_0_TO_63 = 20385; // 24 +static const uint64_t SH_FLD_T1_0_TO_63_LEN = 20386; // 24 +static const uint64_t SH_FLD_T1_CORE_MAINT = 20387; // 24 +static const uint64_t SH_FLD_T1_HSPRG0 = 20388; // 24 +static const uint64_t SH_FLD_T1_HSPRG0_LEN = 20389; // 24 +static const uint64_t SH_FLD_T1_HSPRG1 = 20390; // 24 +static const uint64_t SH_FLD_T1_HSPRG1_LEN = 20391; // 24 +static const uint64_t SH_FLD_T1_IC = 20392; // 24 +static const uint64_t SH_FLD_T1_ICT_EMPTY = 20393; // 24 +static const uint64_t SH_FLD_T1_IC_LEN = 20394; // 24 +static const uint64_t SH_FLD_T1_LEN = 20395; // 24 +static const uint64_t SH_FLD_T1_LSU_QUIESCED = 20396; // 24 +static const uint64_t SH_FLD_T1_RUN_Q = 20397; // 24 +static const uint64_t SH_FLD_T1_SPRG0 = 20398; // 24 +static const uint64_t SH_FLD_T1_SPRG0_LEN = 20399; // 24 +static const uint64_t SH_FLD_T1_SPRG1 = 20400; // 24 +static const uint64_t SH_FLD_T1_SPRG1_LEN = 20401; // 24 +static const uint64_t SH_FLD_T1_SPRG2 = 20402; // 24 +static const uint64_t SH_FLD_T1_SPRG2_LEN = 20403; // 24 +static const uint64_t SH_FLD_T1_SPRG3 = 20404; // 24 +static const uint64_t SH_FLD_T1_SPRG3_LEN = 20405; // 24 +static const uint64_t SH_FLD_T1_STEP_SUCCESS = 20406; // 24 +static const uint64_t SH_FLD_T1_THREAD_QUIESCED = 20407; // 24 +static const uint64_t SH_FLD_T2 = 20408; // 24 +static const uint64_t SH_FLD_T2_0_TO_63 = 20409; // 24 +static const uint64_t SH_FLD_T2_0_TO_63_LEN = 20410; // 24 +static const uint64_t SH_FLD_T2_CORE_MAINT = 20411; // 24 +static const uint64_t SH_FLD_T2_HSPRG0 = 20412; // 24 +static const uint64_t SH_FLD_T2_HSPRG0_LEN = 20413; // 24 +static const uint64_t SH_FLD_T2_HSPRG1 = 20414; // 24 +static const uint64_t SH_FLD_T2_HSPRG1_LEN = 20415; // 24 +static const uint64_t SH_FLD_T2_IC = 20416; // 24 +static const uint64_t SH_FLD_T2_ICT_EMPTY = 20417; // 24 +static const uint64_t SH_FLD_T2_IC_LEN = 20418; // 24 +static const uint64_t SH_FLD_T2_LEN = 20419; // 24 +static const uint64_t SH_FLD_T2_LSU_QUIESCED = 20420; // 24 +static const uint64_t SH_FLD_T2_RUN_Q = 20421; // 24 +static const uint64_t SH_FLD_T2_SPRG0 = 20422; // 24 +static const uint64_t SH_FLD_T2_SPRG0_LEN = 20423; // 24 +static const uint64_t SH_FLD_T2_SPRG1 = 20424; // 24 +static const uint64_t SH_FLD_T2_SPRG1_LEN = 20425; // 24 +static const uint64_t SH_FLD_T2_SPRG2 = 20426; // 24 +static const uint64_t SH_FLD_T2_SPRG2_LEN = 20427; // 24 +static const uint64_t SH_FLD_T2_SPRG3 = 20428; // 24 +static const uint64_t SH_FLD_T2_SPRG3_LEN = 20429; // 24 +static const uint64_t SH_FLD_T2_STEP_SUCCESS = 20430; // 24 +static const uint64_t SH_FLD_T2_THREAD_QUIESCED = 20431; // 24 +static const uint64_t SH_FLD_T3 = 20432; // 24 +static const uint64_t SH_FLD_T3_0_TO_63 = 20433; // 24 +static const uint64_t SH_FLD_T3_0_TO_63_LEN = 20434; // 24 +static const uint64_t SH_FLD_T3_CORE_MAINT = 20435; // 24 +static const uint64_t SH_FLD_T3_HSPRG0 = 20436; // 24 +static const uint64_t SH_FLD_T3_HSPRG0_LEN = 20437; // 24 +static const uint64_t SH_FLD_T3_HSPRG1 = 20438; // 24 +static const uint64_t SH_FLD_T3_HSPRG1_LEN = 20439; // 24 +static const uint64_t SH_FLD_T3_IC = 20440; // 24 +static const uint64_t SH_FLD_T3_ICT_EMPTY = 20441; // 24 +static const uint64_t SH_FLD_T3_IC_LEN = 20442; // 24 +static const uint64_t SH_FLD_T3_LEN = 20443; // 24 +static const uint64_t SH_FLD_T3_LSU_QUIESCED = 20444; // 24 +static const uint64_t SH_FLD_T3_RUN_Q = 20445; // 24 +static const uint64_t SH_FLD_T3_SPRG0 = 20446; // 24 +static const uint64_t SH_FLD_T3_SPRG0_LEN = 20447; // 24 +static const uint64_t SH_FLD_T3_SPRG1 = 20448; // 24 +static const uint64_t SH_FLD_T3_SPRG1_LEN = 20449; // 24 +static const uint64_t SH_FLD_T3_SPRG2 = 20450; // 24 +static const uint64_t SH_FLD_T3_SPRG2_LEN = 20451; // 24 +static const uint64_t SH_FLD_T3_SPRG3 = 20452; // 24 +static const uint64_t SH_FLD_T3_SPRG3_LEN = 20453; // 24 +static const uint64_t SH_FLD_T3_STEP_SUCCESS = 20454; // 24 +static const uint64_t SH_FLD_T3_THREAD_QUIESCED = 20455; // 24 +static const uint64_t SH_FLD_T4_RUN_Q = 20456; // 24 +static const uint64_t SH_FLD_T5_RUN_Q = 20457; // 24 +static const uint64_t SH_FLD_T6_RUN_Q = 20458; // 24 +static const uint64_t SH_FLD_T7_RUN_Q = 20459; // 24 +static const uint64_t SH_FLD_TA = 20460; // 96 +static const uint64_t SH_FLD_TABLE_ADDRESS = 20461; // 1 +static const uint64_t SH_FLD_TABLE_ADDRESS_LEN = 20462; // 1 +static const uint64_t SH_FLD_TABLE_DATA = 20463; // 1 +static const uint64_t SH_FLD_TABLE_DATA_LEN = 20464; // 1 +static const uint64_t SH_FLD_TABLE_SELECT = 20465; // 1 +static const uint64_t SH_FLD_TABLE_SELECT_LEN = 20466; // 1 +static const uint64_t SH_FLD_TABLE_SEL_0_3 = 20467; // 1 +static const uint64_t SH_FLD_TABLE_SEL_0_3_LEN = 20468; // 1 +static const uint64_t SH_FLD_TAG_ECC = 20469; // 12 +static const uint64_t SH_FLD_TAG_ECC_LEN = 20470; // 12 +static const uint64_t SH_FLD_TAP_SEL = 20471; // 24 +static const uint64_t SH_FLD_TAP_SEL_LEN = 20472; // 24 +static const uint64_t SH_FLD_TAR = 20473; // 96 +static const uint64_t SH_FLD_TARGET = 20474; // 2 +static const uint64_t SH_FLD_TARGET_DDE = 20475; // 3 +static const uint64_t SH_FLD_TARGET_DDE_LEN = 20476; // 3 +static const uint64_t SH_FLD_TARGET_ID0 = 20477; // 2 +static const uint64_t SH_FLD_TARGET_LEN = 20478; // 2 +static const uint64_t SH_FLD_TARGET_MIN = 20479; // 2 +static const uint64_t SH_FLD_TARGET_MIN_LEN = 20480; // 2 +static const uint64_t SH_FLD_TARGET_VALID = 20481; // 2 +static const uint64_t SH_FLD_TARGET_VALID_LEN = 20482; // 2 +static const uint64_t SH_FLD_TAR_LEN = 20483; // 96 +static const uint64_t SH_FLD_TB = 20484; // 72 +static const uint64_t SH_FLD_TB40U = 20485; // 72 +static const uint64_t SH_FLD_TB40U_LEN = 20486; // 72 +static const uint64_t SH_FLD_TBEE = 20487; // 96 +static const uint64_t SH_FLD_TBL = 20488; // 72 +static const uint64_t SH_FLD_TBL_LEN = 20489; // 72 +static const uint64_t SH_FLD_TBSEL = 20490; // 96 +static const uint64_t SH_FLD_TBSEL_LEN = 20491; // 96 +static const uint64_t SH_FLD_TBST0_BADIN_ERRHOLD = 20492; // 2 +static const uint64_t SH_FLD_TBST6_BADIN_ERRHOLD = 20493; // 2 +static const uint64_t SH_FLD_TBST7_BADIN_ERRHOLD = 20494; // 2 +static const uint64_t SH_FLD_TBST9_BADIN_ERRHOLD = 20495; // 2 +static const uint64_t SH_FLD_TBST_CORRUPT = 20496; // 98 +static const uint64_t SH_FLD_TBST_CORRUPT_ERRHOLD = 20497; // 2 +static const uint64_t SH_FLD_TBST_ENCODED = 20498; // 98 +static const uint64_t SH_FLD_TBST_ENCODED_LEN = 20499; // 98 +static const uint64_t SH_FLD_TBST_LAST = 20500; // 74 +static const uint64_t SH_FLD_TBST_LAST_LEN = 20501; // 74 +static const uint64_t SH_FLD_TBU = 20502; // 72 +static const uint64_t SH_FLD_TBU_LEN = 20503; // 72 +static const uint64_t SH_FLD_TB_CMD_DISCARDED_ERRHOLD = 20504; // 2 +static const uint64_t SH_FLD_TB_ECLIPZ = 20505; // 98 +static const uint64_t SH_FLD_TB_ENABLED = 20506; // 98 +static const uint64_t SH_FLD_TB_FIR_ERR_ERRHOLD = 20507; // 2 +static const uint64_t SH_FLD_TB_LEN = 20508; // 72 +static const uint64_t SH_FLD_TB_MISSING_STEP = 20509; // 98 +static const uint64_t SH_FLD_TB_MISSING_STEP_ERRHOLD = 20510; // 2 +static const uint64_t SH_FLD_TB_MISSING_SYNC = 20511; // 98 +static const uint64_t SH_FLD_TB_MISSING_SYNC_ERRHOLD = 20512; // 2 +static const uint64_t SH_FLD_TB_REG_RDATA_PERR_ERRHOLD = 20513; // 2 +static const uint64_t SH_FLD_TB_RESIDUE_ERR = 20514; // 98 +static const uint64_t SH_FLD_TB_RESIDUE_ERR_ERRHOLD = 20515; // 2 +static const uint64_t SH_FLD_TB_SYNC_OCCURRED = 20516; // 98 +static const uint64_t SH_FLD_TB_VALID = 20517; // 98 +static const uint64_t SH_FLD_TC = 20518; // 96 +static const uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_0 = 20519; // 4 +static const uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_1 = 20520; // 4 +static const uint64_t SH_FLD_TCC_TC_FIR_SCOM_HOLD_OUT = 20521; // 24 +static const uint64_t SH_FLD_TCD_PERR_ESR = 20522; // 1 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ = 20523; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN = 20524; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN = 20525; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN = 20526; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP = 20527; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN = 20528; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN = 20529; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN = 20530; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP = 20531; // 6 +static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN = 20532; // 6 +static const uint64_t SH_FLD_TCE_CACHE_1W = 20533; // 1 +static const uint64_t SH_FLD_TCE_CACHE_DISABLE = 20534; // 1 +static const uint64_t SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR = 20535; // 1 +static const uint64_t SH_FLD_TCE_COMMON_FATAL_ERROR = 20536; // 6 +static const uint64_t SH_FLD_TCE_COMMON_FATAL_ERRORS = 20537; // 24 +static const uint64_t SH_FLD_TCE_ECC_CORRECTABLE_ERROR = 20538; // 30 +static const uint64_t SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR = 20539; // 30 +static const uint64_t SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR = 20540; // 30 +static const uint64_t SH_FLD_TCE_PAGE_ACCESS_ERR_ESR = 20541; // 1 +static const uint64_t SH_FLD_TCE_REQUEST_TIMEOUT_ERROR = 20542; // 30 +static const uint64_t SH_FLD_TCE_REQ_TO_ERR_ESR = 20543; // 1 +static const uint64_t SH_FLD_TCE_RESERVED01 = 20544; // 30 +static const uint64_t SH_FLD_TCE_RESPONSE = 20545; // 1 +static const uint64_t SH_FLD_TCE_TIMEOUT = 20546; // 1 +static const uint64_t SH_FLD_TCE_TIMEOUT_LEN = 20547; // 1 +static const uint64_t SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR = 20548; // 30 +static const uint64_t SH_FLD_TCK_WIDTH = 20549; // 1 +static const uint64_t SH_FLD_TCK_WIDTH_LEN = 20550; // 1 +static const uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP = 20551; // 1 +static const uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN = 20552; // 1 +static const uint64_t SH_FLD_TCTXT_PRESP_ERROR = 20553; // 1 +static const uint64_t SH_FLD_TC_BIT6_CHIPLET_ID_DC = 20554; // 6 +static const uint64_t SH_FLD_TC_BSC_EXTMODE_DC = 20555; // 43 +static const uint64_t SH_FLD_TC_BSC_INTMODE_DC = 20556; // 43 +static const uint64_t SH_FLD_TC_BSC_INV_DC = 20557; // 43 +static const uint64_t SH_FLD_TC_BSC_WRAPSEL_DC = 20558; // 43 +static const uint64_t SH_FLD_TC_DIAG_PORT0_OUT = 20559; // 43 +static const uint64_t SH_FLD_TC_DIAG_PORT1_OUT = 20560; // 43 +static const uint64_t SH_FLD_TC_EDRAM_ABIST_MODE_DC = 20561; // 43 +static const uint64_t SH_FLD_TC_FIR_XSTOP_ERROR = 20562; // 24 +static const uint64_t SH_FLD_TC_IOBIST_MODE_DC = 20563; // 43 +static const uint64_t SH_FLD_TC_IOM01_DDR0_DFI_RESET_ALL = 20564; // 2 +static const uint64_t SH_FLD_TC_IOM01_DDR1_DFI_RESET_ALL = 20565; // 2 +static const uint64_t SH_FLD_TC_IOM01_DDR2_DFI_RESET_ALL = 20566; // 2 +static const uint64_t SH_FLD_TC_IOM01_DDR3_DFI_RESET_ALL = 20567; // 2 +static const uint64_t SH_FLD_TC_IOM01_FORCETOKNOWN_DC = 20568; // 2 +static const uint64_t SH_FLD_TC_IOP_HSSPORWREN = 20569; // 3 +static const uint64_t SH_FLD_TC_IOP_SYS_RESET_PCS = 20570; // 3 +static const uint64_t SH_FLD_TC_IOP_SYS_RESET_PMA = 20571; // 3 +static const uint64_t SH_FLD_TC_IOX_MUX_VSEL = 20572; // 1 +static const uint64_t SH_FLD_TC_IOX_MUX_VSEL_LEN = 20573; // 1 +static const uint64_t SH_FLD_TC_LP_RESET = 20574; // 1 +static const uint64_t SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC = 20575; // 43 +static const uint64_t SH_FLD_TC_NBTI_PROBE_GATE_DC = 20576; // 43 +static const uint64_t SH_FLD_TC_OB_RATIO_DC = 20577; // 2 +static const uint64_t SH_FLD_TC_OB_RATIO_DC_LEN = 20578; // 2 +static const uint64_t SH_FLD_TC_OELCC_ALIGN_FLUSH_DC = 20579; // 43 +static const uint64_t SH_FLD_TC_OELCC_EDGE_DELAYED_DC = 20580; // 43 +static const uint64_t SH_FLD_TC_PBE0_IOVALID_DC = 20581; // 1 +static const uint64_t SH_FLD_TC_PBE1_IOVALID_DC = 20582; // 1 +static const uint64_t SH_FLD_TC_PBE2_IOVALID_DC = 20583; // 1 +static const uint64_t SH_FLD_TC_PBE3_IOVALID_DC = 20584; // 1 +static const uint64_t SH_FLD_TC_PBE4_IOVALID_DC = 20585; // 1 +static const uint64_t SH_FLD_TC_PBE5_IOVALID_DC = 20586; // 1 +static const uint64_t SH_FLD_TC_PBIOO0_IOVALID = 20587; // 2 +static const uint64_t SH_FLD_TC_PBIOO1_IOVALID = 20588; // 2 +static const uint64_t SH_FLD_TC_PCI0_IOVALID = 20589; // 1 +static const uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC = 20590; // 1 +static const uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC_LEN = 20591; // 1 +static const uint64_t SH_FLD_TC_PCI0_RATIO_DC = 20592; // 1 +static const uint64_t SH_FLD_TC_PCI0_RATIO_DC_LEN = 20593; // 1 +static const uint64_t SH_FLD_TC_PCI0_RATIO_OVERRIDE = 20594; // 1 +static const uint64_t SH_FLD_TC_PCI0_SWAP_DC = 20595; // 1 +static const uint64_t SH_FLD_TC_PCI1X_IOVALID = 20596; // 1 +static const uint64_t SH_FLD_TC_PCI1X_IOVALID_LEN = 20597; // 1 +static const uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC = 20598; // 1 +static const uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC_LEN = 20599; // 1 +static const uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC = 20600; // 1 +static const uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC_LEN = 20601; // 1 +static const uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC = 20602; // 1 +static const uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC_LEN = 20603; // 1 +static const uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE = 20604; // 1 +static const uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE_LEN = 20605; // 1 +static const uint64_t SH_FLD_TC_PCI1_SWAP_DC = 20606; // 1 +static const uint64_t SH_FLD_TC_PCI1_SWAP_DC_LEN = 20607; // 1 +static const uint64_t SH_FLD_TC_PCI2_IOVALID = 20608; // 1 +static const uint64_t SH_FLD_TC_PCI2_IOVALID_LEN = 20609; // 1 +static const uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC = 20610; // 1 +static const uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC_LEN = 20611; // 1 +static const uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC = 20612; // 1 +static const uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC_LEN = 20613; // 1 +static const uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC = 20614; // 1 +static const uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC_LEN = 20615; // 1 +static const uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC = 20616; // 1 +static const uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC_LEN = 20617; // 1 +static const uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE = 20618; // 1 +static const uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE_LEN = 20619; // 1 +static const uint64_t SH_FLD_TC_PCI2_SWAP_DC = 20620; // 1 +static const uint64_t SH_FLD_TC_PCI2_SWAP_DC_LEN = 20621; // 1 +static const uint64_t SH_FLD_TC_PERV_EXPORT_FREEZE = 20622; // 1 +static const uint64_t SH_FLD_TC_PERV_MESH_CTRL = 20623; // 2 +static const uint64_t SH_FLD_TC_PERV_REGION_FENCE = 20624; // 43 +static const uint64_t SH_FLD_TC_PSI_IOVALID_DC = 20625; // 1 +static const uint64_t SH_FLD_TC_PSRO_SEL_DC = 20626; // 43 +static const uint64_t SH_FLD_TC_PSRO_SEL_DC_LEN = 20627; // 43 +static const uint64_t SH_FLD_TC_REFCLK_DRVR_EN_DC = 20628; // 43 +static const uint64_t SH_FLD_TC_REGION1_FENCE = 20629; // 42 +static const uint64_t SH_FLD_TC_REGION2_FENCE = 20630; // 42 +static const uint64_t SH_FLD_TC_REGION3_FENCE = 20631; // 16 +static const uint64_t SH_FLD_TC_REGION4_FENCE = 20632; // 12 +static const uint64_t SH_FLD_TC_REGION5_FENCE = 20633; // 10 +static const uint64_t SH_FLD_TC_REGION6_FENCE = 20634; // 8 +static const uint64_t SH_FLD_TC_REGION7_FENCE = 20635; // 7 +static const uint64_t SH_FLD_TC_REGION8_FENCE = 20636; // 6 +static const uint64_t SH_FLD_TC_REGION9_FENCE = 20637; // 6 +static const uint64_t SH_FLD_TC_SKIT_MODE_BIST_DC = 20638; // 43 +static const uint64_t SH_FLD_TC_SRAM_ABIST_MODE_DC = 20639; // 43 +static const uint64_t SH_FLD_TC_START_TEST_DC = 20640; // 43 +static const uint64_t SH_FLD_TC_UNIT_ARY_WRT_THRU_DC = 20641; // 43 +static const uint64_t SH_FLD_TC_UNIT_AVP_MODE = 20642; // 43 +static const uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC = 20643; // 43 +static const uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC_LEN = 20644; // 43 +static const uint64_t SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 20645; // 43 +static const uint64_t SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 20646; // 43 +static const uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC = 20647; // 43 +static const uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC_LEN = 20648; // 43 +static const uint64_t SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC = 20649; // 43 +static const uint64_t SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE = 20650; // 43 +static const uint64_t SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC = 20651; // 43 +static const uint64_t SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC = 20652; // 43 +static const uint64_t SH_FLD_TC_UNIT_SYS_ID_DC = 20653; // 43 +static const uint64_t SH_FLD_TC_UNIT_SYS_ID_DC_LEN = 20654; // 43 +static const uint64_t SH_FLD_TC_VITL_REGION_FENCE = 20655; // 43 +static const uint64_t SH_FLD_TDM_DELAY = 20656; // 5 +static const uint64_t SH_FLD_TDM_DELAY_LEN = 20657; // 5 +static const uint64_t SH_FLD_TDM_HUT_LUT_00 = 20658; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_00_LEN = 20659; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_01 = 20660; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_01_LEN = 20661; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_02 = 20662; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_02_LEN = 20663; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_03 = 20664; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_03_LEN = 20665; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_04 = 20666; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_04_LEN = 20667; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_05 = 20668; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_05_LEN = 20669; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_06 = 20670; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_06_LEN = 20671; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_07 = 20672; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_07_LEN = 20673; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_08 = 20674; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_08_LEN = 20675; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_09 = 20676; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_09_LEN = 20677; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_10 = 20678; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_10_LEN = 20679; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_11 = 20680; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_11_LEN = 20681; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_12 = 20682; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_12_LEN = 20683; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_13 = 20684; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_13_LEN = 20685; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_14 = 20686; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_14_LEN = 20687; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_15 = 20688; // 6 +static const uint64_t SH_FLD_TDM_HUT_LUT_15_LEN = 20689; // 6 +static const uint64_t SH_FLD_TDR_DAC_CNTL = 20690; // 6 +static const uint64_t SH_FLD_TDR_DAC_CNTL_LEN = 20691; // 6 +static const uint64_t SH_FLD_TDR_ENABLE = 20692; // 116 +static const uint64_t SH_FLD_TDR_PERR_ESR = 20693; // 1 +static const uint64_t SH_FLD_TDR_PHASE_SEL = 20694; // 6 +static const uint64_t SH_FLD_TDR_PULSE_OFFSET = 20695; // 6 +static const uint64_t SH_FLD_TDR_PULSE_OFFSET_LEN = 20696; // 6 +static const uint64_t SH_FLD_TDR_PULSE_WIDTH = 20697; // 6 +static const uint64_t SH_FLD_TDR_PULSE_WIDTH_LEN = 20698; // 6 +static const uint64_t SH_FLD_TECHNOLOGY = 20699; // 24 +static const uint64_t SH_FLD_TECHNOLOGY_LEN = 20700; // 24 +static const uint64_t SH_FLD_TER = 20701; // 8 +static const uint64_t SH_FLD_TERM_ENC = 20702; // 1 +static const uint64_t SH_FLD_TERM_ENC_LEN = 20703; // 1 +static const uint64_t SH_FLD_TERM_TEST = 20704; // 1 +static const uint64_t SH_FLD_TER_LEN = 20705; // 8 +static const uint64_t SH_FLD_TER_V = 20706; // 8 +static const uint64_t SH_FLD_TEST_ENABLE = 20707; // 43 +static const uint64_t SH_FLD_TFAC_ERR = 20708; // 96 +static const uint64_t SH_FLD_TFHAR = 20709; // 96 +static const uint64_t SH_FLD_TFHAR_LEN = 20710; // 96 +static const uint64_t SH_FLD_TFIAR = 20711; // 96 +static const uint64_t SH_FLD_TFIAR_LEN = 20712; // 96 +static const uint64_t SH_FLD_TFMR_CORRUPT = 20713; // 98 +static const uint64_t SH_FLD_TFMR_PARITY_ERR = 20714; // 96 +static const uint64_t SH_FLD_TFRAMESIZE = 20715; // 2 +static const uint64_t SH_FLD_TFRAMESIZE_LEN = 20716; // 2 +static const uint64_t SH_FLD_TFREQ0 = 20717; // 9 +static const uint64_t SH_FLD_TFREQ0_LEN = 20718; // 9 +static const uint64_t SH_FLD_TFREQ1 = 20719; // 9 +static const uint64_t SH_FLD_TFREQ1_LEN = 20720; // 9 +static const uint64_t SH_FLD_TGT_NODAL_DINC_ERR = 20721; // 12 +static const uint64_t SH_FLD_TGT_NODAL_REQ_DINC_ERR = 20722; // 12 +static const uint64_t SH_FLD_THERM_CPM_ENABLE_L1 = 20723; // 43 +static const uint64_t SH_FLD_THERM_CPM_ENABLE_L1_LEN = 20724; // 43 +static const uint64_t SH_FLD_THERM_MODE = 20725; // 43 +static const uint64_t SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD = 20726; // 43 +static const uint64_t SH_FLD_THERM_MODEREG_PARITY_MASK = 20727; // 43 +static const uint64_t SH_FLD_THERM_MODE_LEN = 20728; // 43 +static const uint64_t SH_FLD_THERM_TRIP = 20729; // 43 +static const uint64_t SH_FLD_THERM_TRIP_LEN = 20730; // 43 +static const uint64_t SH_FLD_THIS_LBUS_REQ = 20731; // 2 +static const uint64_t SH_FLD_THIS_SIDE = 20732; // 2 +static const uint64_t SH_FLD_THIS_SIDE_LEN = 20733; // 2 +static const uint64_t SH_FLD_THREAD_CONTEXT = 20734; // 24 +static const uint64_t SH_FLD_THREAD_CONTEXT_LEN = 20735; // 24 +static const uint64_t SH_FLD_THREAD_ID = 20736; // 48 +static const uint64_t SH_FLD_THREAD_ID_LEN = 20737; // 48 +static const uint64_t SH_FLD_THRESHOLD = 20738; // 1 +static const uint64_t SH_FLD_THRESHOLD_LIMIT = 20739; // 24 +static const uint64_t SH_FLD_THRESHOLD_LIMIT_LEN = 20740; // 24 +static const uint64_t SH_FLD_THRESHOLD_RESET = 20741; // 24 +static const uint64_t SH_FLD_THRESHOLD_RESET_LEN = 20742; // 24 +static const uint64_t SH_FLD_THRESH_0 = 20743; // 3 +static const uint64_t SH_FLD_THRESH_0_LEN = 20744; // 3 +static const uint64_t SH_FLD_THRESH_1 = 20745; // 3 +static const uint64_t SH_FLD_THRESH_1_LEN = 20746; // 3 +static const uint64_t SH_FLD_THRESH_2 = 20747; // 3 +static const uint64_t SH_FLD_THRESH_2_LEN = 20748; // 3 +static const uint64_t SH_FLD_THRESH_CMP_EXP = 20749; // 96 +static const uint64_t SH_FLD_THRESH_CMP_EXP_LEN = 20750; // 96 +static const uint64_t SH_FLD_THRESH_CMP_MANTISSA = 20751; // 96 +static const uint64_t SH_FLD_THRESH_CMP_MANTISSA_LEN = 20752; // 96 +static const uint64_t SH_FLD_THRESH_CTR_EXP = 20753; // 96 +static const uint64_t SH_FLD_THRESH_CTR_EXP_LEN = 20754; // 96 +static const uint64_t SH_FLD_THRESH_CTR_MANTISSA = 20755; // 96 +static const uint64_t SH_FLD_THRESH_CTR_MANTISSA_LEN = 20756; // 96 +static const uint64_t SH_FLD_THRESH_DIS_TAP_CLEAR = 20757; // 12 +static const uint64_t SH_FLD_THRESH_DIS_TAP_STOP = 20758; // 12 +static const uint64_t SH_FLD_THRESH_DIS_TB_CLEAR = 20759; // 12 +static const uint64_t SH_FLD_THRESH_ENABLE = 20760; // 12 +static const uint64_t SH_FLD_THRESH_ENABLE_LEN = 20761; // 12 +static const uint64_t SH_FLD_THRESH_END = 20762; // 96 +static const uint64_t SH_FLD_THRESH_END_LEN = 20763; // 96 +static const uint64_t SH_FLD_THRESH_EVENT_SEL = 20764; // 96 +static const uint64_t SH_FLD_THRESH_EVENT_SEL_LEN = 20765; // 96 +static const uint64_t SH_FLD_THRESH_LINK0_CLEAR = 20766; // 12 +static const uint64_t SH_FLD_THRESH_LINK0_COUNT = 20767; // 12 +static const uint64_t SH_FLD_THRESH_LINK0_COUNT_LEN = 20768; // 12 +static const uint64_t SH_FLD_THRESH_LINK1_CLEAR = 20769; // 12 +static const uint64_t SH_FLD_THRESH_LINK1_COUNT = 20770; // 12 +static const uint64_t SH_FLD_THRESH_LINK1_COUNT_LEN = 20771; // 12 +static const uint64_t SH_FLD_THRESH_START = 20772; // 96 +static const uint64_t SH_FLD_THRESH_START_LEN = 20773; // 96 +static const uint64_t SH_FLD_THRESH_TAP_SEL = 20774; // 12 +static const uint64_t SH_FLD_THRESH_TAP_SEL_LEN = 20775; // 12 +static const uint64_t SH_FLD_THRESH_TB_SEL = 20776; // 12 +static const uint64_t SH_FLD_THRESH_TB_SEL_LEN = 20777; // 12 +static const uint64_t SH_FLD_THRESH_UNUSED1 = 20778; // 12 +static const uint64_t SH_FLD_THRESH_UNUSED1_LEN = 20779; // 12 +static const uint64_t SH_FLD_THRESH_UNUSED2 = 20780; // 12 +static const uint64_t SH_FLD_THRES_ENA = 20781; // 43 +static const uint64_t SH_FLD_THRES_ENA_LEN = 20782; // 43 +static const uint64_t SH_FLD_THRES_OVERFLOW_MASK = 20783; // 43 +static const uint64_t SH_FLD_THRES_STATE_MASK = 20784; // 43 +static const uint64_t SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD = 20785; // 43 +static const uint64_t SH_FLD_THRES_THERM_STATE_ERR_HOLD = 20786; // 43 +static const uint64_t SH_FLD_THRES_TRIP_ENA = 20787; // 43 +static const uint64_t SH_FLD_THRES_TRIP_ENA_LEN = 20788; // 43 +static const uint64_t SH_FLD_THRID = 20789; // 1 +static const uint64_t SH_FLD_THRID_LEN = 20790; // 1 +static const uint64_t SH_FLD_THR_ID = 20791; // 1 +static const uint64_t SH_FLD_THR_ID_LEN = 20792; // 1 +static const uint64_t SH_FLD_TID = 20793; // 8 +static const uint64_t SH_FLD_TID_LEN = 20794; // 8 +static const uint64_t SH_FLD_TIER0_VALUE = 20795; // 12 +static const uint64_t SH_FLD_TIER0_VALUE_LEN = 20796; // 12 +static const uint64_t SH_FLD_TIER1_VALUE = 20797; // 24 +static const uint64_t SH_FLD_TIER1_VALUE_LEN = 20798; // 24 +static const uint64_t SH_FLD_TIER2_VALUE = 20799; // 24 +static const uint64_t SH_FLD_TIER2_VALUE_LEN = 20800; // 24 +static const uint64_t SH_FLD_TIME = 20801; // 43 +static const uint64_t SH_FLD_TIMEBASE = 20802; // 330 +static const uint64_t SH_FLD_TIMEBASE_ENABLE = 20803; // 1 +static const uint64_t SH_FLD_TIMEBASE_LEN = 20804; // 330 +static const uint64_t SH_FLD_TIMEOUT = 20805; // 9 +static const uint64_t SH_FLD_TIMEOUT_ACTIVE = 20806; // 2 +static const uint64_t SH_FLD_TIMEOUT_EN = 20807; // 1 +static const uint64_t SH_FLD_TIMEOUT_ERR_HOLD = 20808; // 43 +static const uint64_t SH_FLD_TIMEOUT_LEN = 20809; // 5 +static const uint64_t SH_FLD_TIMEOUT_MASK = 20810; // 43 +static const uint64_t SH_FLD_TIMEOUT_N = 20811; // 2 +static const uint64_t SH_FLD_TIMEOUT_ON_I2C_STATUS_RD = 20812; // 1 +static const uint64_t SH_FLD_TIMEOUT_PARITY = 20813; // 43 +static const uint64_t SH_FLD_TIMEOUT_SEL = 20814; // 3 +static const uint64_t SH_FLD_TIMEOUT_SEL_LEN = 20815; // 3 +static const uint64_t SH_FLD_TIMEOUT_VALUE = 20816; // 5 +static const uint64_t SH_FLD_TIMEOUT_VALUE_LEN = 20817; // 5 +static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 20818; // 43 +static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 20819; // 43 +static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 20820; // 43 +static const uint64_t SH_FLD_TIMER = 20821; // 3 +static const uint64_t SH_FLD_TIMER_1US = 20822; // 5 +static const uint64_t SH_FLD_TIMER_1US_LEN = 20823; // 5 +static const uint64_t SH_FLD_TIMER_ENABLE = 20824; // 4 +static const uint64_t SH_FLD_TIMER_EXPIRED_RECOV_ERROR = 20825; // 4 +static const uint64_t SH_FLD_TIMER_EXPIRED_XSTOP_ERROR = 20826; // 4 +static const uint64_t SH_FLD_TIMER_LEN = 20827; // 3 +static const uint64_t SH_FLD_TIMER_N = 20828; // 2 +static const uint64_t SH_FLD_TIMER_N_LEN = 20829; // 2 +static const uint64_t SH_FLD_TIMER_PERIOD_MASK = 20830; // 4 +static const uint64_t SH_FLD_TIMER_PERIOD_MASK_LEN = 20831; // 4 +static const uint64_t SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR = 20832; // 43 +static const uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE = 20833; // 43 +static const uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN = 20834; // 43 +static const uint64_t SH_FLD_TIME_BASE_ERR = 20835; // 4 +static const uint64_t SH_FLD_TLBIE_CNT_THRESH = 20836; // 13 +static const uint64_t SH_FLD_TLBIE_CNT_THRESH_LEN = 20837; // 13 +static const uint64_t SH_FLD_TLBIE_CNT_WT4TX_CORE_EN = 20838; // 12 +static const uint64_t SH_FLD_TLBIE_CONTROL_ERR = 20839; // 12 +static const uint64_t SH_FLD_TLBIE_DEC_RATE = 20840; // 13 +static const uint64_t SH_FLD_TLBIE_DEC_RATE_LEN = 20841; // 13 +static const uint64_t SH_FLD_TLBIE_INC_RATE = 20842; // 13 +static const uint64_t SH_FLD_TLBIE_INC_RATE_LEN = 20843; // 13 +static const uint64_t SH_FLD_TLBIE_MASTER_TIMEOUT = 20844; // 12 +static const uint64_t SH_FLD_TLBIE_PACING_CNT_EN = 20845; // 12 +static const uint64_t SH_FLD_TLBIE_SLBIEG_SW_ERR = 20846; // 12 +static const uint64_t SH_FLD_TLBIE_SNOOP_TIMEOUT = 20847; // 12 +static const uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT = 20848; // 14 +static const uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN = 20849; // 14 +static const uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT = 20850; // 14 +static const uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT_LEN = 20851; // 14 +static const uint64_t SH_FLD_TLBIE_STALL_EN = 20852; // 14 +static const uint64_t SH_FLD_TLBIE_STALL_LIMIT = 20853; // 24 +static const uint64_t SH_FLD_TLBIE_STALL_LIMIT_LEN = 20854; // 24 +static const uint64_t SH_FLD_TLBIE_STALL_THRESHOLD = 20855; // 14 +static const uint64_t SH_FLD_TLBIE_STALL_THRESHOLD_LEN = 20856; // 14 +static const uint64_t SH_FLD_TLBI_BAD_OP_ERR = 20857; // 4 +static const uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV = 20858; // 2 +static const uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN = 20859; // 2 +static const uint64_t SH_FLD_TLBI_FENCE = 20860; // 2 +static const uint64_t SH_FLD_TLBI_GROUP_PUMP_EN = 20861; // 12 +static const uint64_t SH_FLD_TLBI_PSL_DEAD = 20862; // 2 +static const uint64_t SH_FLD_TLBI_REGS_PARITY_ERRHOLD = 20863; // 2 +static const uint64_t SH_FLD_TLBI_SC_RDATA_PARITY_ERRHOLD = 20864; // 2 +static const uint64_t SH_FLD_TLBI_SEQ_NUM_PARITY_ERR = 20865; // 4 +static const uint64_t SH_FLD_TLBI_SOT_ERR = 20866; // 4 +static const uint64_t SH_FLD_TLBI_TIMEOUT = 20867; // 4 +static const uint64_t SH_FLD_TLBI_TRIGGER_SEL = 20868; // 2 +static const uint64_t SH_FLD_TLB_BUS0_STG1_SEL = 20869; // 1 +static const uint64_t SH_FLD_TLB_BUS0_STG2_SEL = 20870; // 1 +static const uint64_t SH_FLD_TLB_BUS1_STG1_SEL = 20871; // 1 +static const uint64_t SH_FLD_TLB_BUS1_STG2_SEL = 20872; // 1 +static const uint64_t SH_FLD_TLB_CAC_PERR_DET = 20873; // 1 +static const uint64_t SH_FLD_TLB_CHK_WAIT_DEC = 20874; // 12 +static const uint64_t SH_FLD_TLB_CHK_WAIT_DEC_LEN = 20875; // 12 +static const uint64_t SH_FLD_TLB_DIR_PERR_DET = 20876; // 1 +static const uint64_t SH_FLD_TLB_LRU_PERR_DET = 20877; // 1 +static const uint64_t SH_FLD_TLB_MULTIHIT_DET = 20878; // 1 +static const uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV = 20879; // 12 +static const uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 20880; // 12 +static const uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV = 20881; // 12 +static const uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 20882; // 12 +static const uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV = 20883; // 12 +static const uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 20884; // 12 +static const uint64_t SH_FLD_TM = 20885; // 96 +static const uint64_t SH_FLD_TMOD_CYCLES = 20886; // 8 +static const uint64_t SH_FLD_TMOD_CYCLES_LEN = 20887; // 8 +static const uint64_t SH_FLD_TMRSC_CYCLES = 20888; // 8 +static const uint64_t SH_FLD_TMRSC_CYCLES_LEN = 20889; // 8 +static const uint64_t SH_FLD_TMR_PE = 20890; // 8 +static const uint64_t SH_FLD_TM_CAM = 20891; // 12 +static const uint64_t SH_FLD_TM_CAM_LEN = 20892; // 12 +static const uint64_t SH_FLD_TODTLON_OFF_CYCLES = 20893; // 8 +static const uint64_t SH_FLD_TODTLON_OFF_CYCLES_LEN = 20894; // 8 +static const uint64_t SH_FLD_TOD_CMD_LAST = 20895; // 24 +static const uint64_t SH_FLD_TOD_CMD_LAST_LEN = 20896; // 24 +static const uint64_t SH_FLD_TOD_CMD_OVERRUN = 20897; // 1 +static const uint64_t SH_FLD_TOD_CNTR_REF = 20898; // 2 +static const uint64_t SH_FLD_TOD_CNTR_REF_LEN = 20899; // 2 +static const uint64_t SH_FLD_TOD_HANG_ERR = 20900; // 1 +static const uint64_t SH_FLD_TOD_TAP = 20901; // 24 +static const uint64_t SH_FLD_TOO_MANY_BUS_ERRORS = 20902; // 8 +static const uint64_t SH_FLD_TOR_PERR_ESR = 20903; // 1 +static const uint64_t SH_FLD_TOTAL_DROOP_EVENT_CTR = 20904; // 12 +static const uint64_t SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN = 20905; // 12 +static const uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT = 20906; // 1 +static const uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT_LEN = 20907; // 1 +static const uint64_t SH_FLD_TO_CMP_LT = 20908; // 86 +static const uint64_t SH_FLD_TO_CMP_LT_LEN = 20909; // 86 +static const uint64_t SH_FLD_TO_IFU = 20910; // 24 +static const uint64_t SH_FLD_TO_ISU = 20911; // 24 +static const uint64_t SH_FLD_TO_LSU = 20912; // 24 +static const uint64_t SH_FLD_TO_PC = 20913; // 24 +static const uint64_t SH_FLD_TO_VSU = 20914; // 24 +static const uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC = 20915; // 3 +static const uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN = 20916; // 3 +static const uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC = 20917; // 3 +static const uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN = 20918; // 3 +static const uint64_t SH_FLD_TPCFSI_OPB_SW_RESET_DC = 20919; // 3 +static const uint64_t SH_FLD_TPFSI_ALTREFCLK_SE1 = 20920; // 3 +static const uint64_t SH_FLD_TPFSI_ALTREFCLK_SEL = 20921; // 3 +static const uint64_t SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 20922; // 2 +static const uint64_t SH_FLD_TPFSI_ARRAY_VBL_TO_VDD_DC = 20923; // 1 +static const uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC = 20924; // 3 +static const uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 20925; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW0_PGOOD_N = 20926; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW1_PGOOD = 20927; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC = 20928; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN = 20929; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC = 20930; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN = 20931; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC = 20932; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 20933; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 20934; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 20935; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC = 20936; // 3 +static const uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN = 20937; // 3 +static const uint64_t SH_FLD_TPFSI_TC_HSSPORWREN_ALLOW = 20938; // 3 +static const uint64_t SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC = 20939; // 3 +static const uint64_t SH_FLD_TPFSI_TP_EDRAM_CTRL_GATE = 20940; // 3 +static const uint64_t SH_FLD_TPFSI_TP_FENCE_VTLIO_DC = 20941; // 3 +static const uint64_t SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 20942; // 3 +static const uint64_t SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC = 20943; // 3 +static const uint64_t SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 20944; // 3 +static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 20945; // 3 +static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 20946; // 3 +static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 20947; // 3 +static const uint64_t SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 20948; // 3 +static const uint64_t SH_FLD_TPM_INTERRUPT_HIGH = 20949; // 1 +static const uint64_t SH_FLD_TPM_INTERRUPT_PENDING = 20950; // 1 +static const uint64_t SH_FLD_TPSBE_TPBR_SBE_INTR = 20951; // 1 +static const uint64_t SH_FLD_TPSBE_TPIO_TPM_RESET = 20952; // 1 +static const uint64_t SH_FLD_TPSBE_TPOCC_HALT_COMPLEX = 20953; // 1 +static const uint64_t SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC = 20954; // 3 +static const uint64_t SH_FLD_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC = 20955; // 3 +static const uint64_t SH_FLD_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC = 20956; // 3 +static const uint64_t SH_FLD_TP_CHIPLET_EN_DC = 20957; // 3 +static const uint64_t SH_FLD_TP_CHIPLET_PLL_CLKIN_SEL_DC = 20958; // 3 +static const uint64_t SH_FLD_TP_CLK_ASYNC_RESET_DC = 20959; // 3 +static const uint64_t SH_FLD_TP_CLK_DIV_BYPASS_EN_DC = 20960; // 3 +static const uint64_t SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC = 20961; // 3 +static const uint64_t SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC = 20962; // 3 +static const uint64_t SH_FLD_TP_CLK_PULSE_ENABLE_DC = 20963; // 3 +static const uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC = 20964; // 3 +static const uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC_LEN = 20965; // 3 +static const uint64_t SH_FLD_TP_CPM_CAL = 20966; // 1 +static const uint64_t SH_FLD_TP_CPM_CAL_SET = 20967; // 2 +static const uint64_t SH_FLD_TP_DI1_DC_B = 20968; // 3 +static const uint64_t SH_FLD_TP_DI1_DC_N = 20969; // 3 +static const uint64_t SH_FLD_TP_DI2_DC_B = 20970; // 3 +static const uint64_t SH_FLD_TP_DI2_DC_N = 20971; // 3 +static const uint64_t SH_FLD_TP_EDRAM_ENABLE_DC = 20972; // 3 +static const uint64_t SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC = 20973; // 1 +static const uint64_t SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 20974; // 1 +static const uint64_t SH_FLD_TP_FENCE_EN_DC = 20975; // 3 +static const uint64_t SH_FLD_TP_FENCE_PCB = 20976; // 43 +static const uint64_t SH_FLD_TP_FENCE_PCB_DC = 20977; // 3 +static const uint64_t SH_FLD_TP_FILT0_PLL_BYPASS = 20978; // 3 +static const uint64_t SH_FLD_TP_FILT0_PLL_RESET = 20979; // 3 +static const uint64_t SH_FLD_TP_FILT0_PLL_TEST_EN = 20980; // 3 +static const uint64_t SH_FLD_TP_FILT1_PLL_BYPASS = 20981; // 3 +static const uint64_t SH_FLD_TP_FILT1_PLL_RESET = 20982; // 3 +static const uint64_t SH_FLD_TP_FILT1_PLL_TEST_EN = 20983; // 3 +static const uint64_t SH_FLD_TP_FLUSH_ALIGN_OVERWRITE = 20984; // 3 +static const uint64_t SH_FLD_TP_FLUSH_SCAN_DC_N = 20985; // 3 +static const uint64_t SH_FLD_TP_FSI_CLKIN_SEL_DC = 20986; // 3 +static const uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC = 20987; // 3 +static const uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC_LEN = 20988; // 3 +static const uint64_t SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC = 20989; // 3 +static const uint64_t SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 20990; // 3 +static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 20991; // 3 +static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 20992; // 3 +static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 20993; // 3 +static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 20994; // 3 +static const uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT = 20995; // 3 +static const uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN = 20996; // 3 +static const uint64_t SH_FLD_TP_IDDQ_DC = 20997; // 3 +static const uint64_t SH_FLD_TP_IO_SPARE2_MCPRECOMP = 20998; // 1 +static const uint64_t SH_FLD_TP_IO_SPARE2_MCPRECOMP_LEN = 20999; // 1 +static const uint64_t SH_FLD_TP_IO_SPARE3_MCPRECOMP = 21000; // 1 +static const uint64_t SH_FLD_TP_IO_SPARE3_MCPRECOMP_LEN = 21001; // 1 +static const uint64_t SH_FLD_TP_IO_SPI_APSS_MCPRECOMP = 21002; // 1 +static const uint64_t SH_FLD_TP_IO_SPI_APSS_MCPRECOMP_LEN = 21003; // 1 +static const uint64_t SH_FLD_TP_IO_VSB_OP0A_V1P8_EN = 21004; // 3 +static const uint64_t SH_FLD_TP_IO_VSB_OP0B_V1P8_EN = 21005; // 3 +static const uint64_t SH_FLD_TP_IO_VSB_OP3A_V1P8_EN = 21006; // 3 +static const uint64_t SH_FLD_TP_IO_VSB_OP3B_V1P8_EN = 21007; // 3 +static const uint64_t SH_FLD_TP_LVLTRANS_FENCE_DC = 21008; // 3 +static const uint64_t SH_FLD_TP_NP_NVLINK_DISABLE = 21009; // 1 +static const uint64_t SH_FLD_TP_NX_ALLOW_CRYPTO_DC = 21010; // 1 +static const uint64_t SH_FLD_TP_OSCSWITCH_VSB = 21011; // 3 +static const uint64_t SH_FLD_TP_OSCSWITCH_VSB_LEN = 21012; // 3 +static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_2CHIP = 21013; // 1 +static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP = 21014; // 1 +static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN = 21015; // 1 +static const uint64_t SH_FLD_TP_PCB_EP_RESET_DC = 21016; // 3 +static const uint64_t SH_FLD_TP_PCB_PM_MUX_SEL_DC = 21017; // 3 +static const uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC = 21018; // 3 +static const uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 21019; // 3 +static const uint64_t SH_FLD_TP_PIB_TRACE_MODE_DATA_DC = 21020; // 3 +static const uint64_t SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC = 21021; // 3 +static const uint64_t SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE = 21022; // 3 +static const uint64_t SH_FLD_TP_PLLBYP_DC = 21023; // 3 +static const uint64_t SH_FLD_TP_PLLCHIPLET_FORCE_OUT_EN_DC = 21024; // 3 +static const uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC = 21025; // 3 +static const uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 21026; // 3 +static const uint64_t SH_FLD_TP_PLLRST_DC = 21027; // 3 +static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL1_DC = 21028; // 3 +static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL2_DC = 21029; // 3 +static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL3_DC = 21030; // 3 +static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL4_DC = 21031; // 3 +static const uint64_t SH_FLD_TP_PLL_FORCE_OUT_EN_DC = 21032; // 3 +static const uint64_t SH_FLD_TP_PLL_TEST_EN = 21033; // 3 +static const uint64_t SH_FLD_TP_PLL_TEST_EN_DC = 21034; // 3 +static const uint64_t SH_FLD_TP_PROBE0_SEL_DC = 21035; // 3 +static const uint64_t SH_FLD_TP_PROBE0_SEL_DC_LEN = 21036; // 3 +static const uint64_t SH_FLD_TP_PROBE1_SEL_DC = 21037; // 3 +static const uint64_t SH_FLD_TP_PROBE1_SEL_DC_LEN = 21038; // 3 +static const uint64_t SH_FLD_TP_PROBE_DRV_EN_DC = 21039; // 3 +static const uint64_t SH_FLD_TP_PROBE_HIGHDRIVE_DC = 21040; // 3 +static const uint64_t SH_FLD_TP_PROBE_MESH_SEL_DC = 21041; // 3 +static const uint64_t SH_FLD_TP_RESCLK_DIS_DC = 21042; // 3 +static const uint64_t SH_FLD_TP_RI_DC_B = 21043; // 3 +static const uint64_t SH_FLD_TP_RI_DC_N = 21044; // 3 +static const uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC = 21045; // 3 +static const uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 21046; // 3 +static const uint64_t SH_FLD_TP_SS0_PLL_BYPASS = 21047; // 3 +static const uint64_t SH_FLD_TP_SS0_PLL_RESET = 21048; // 3 +static const uint64_t SH_FLD_TP_SS0_PLL_TEST_EN = 21049; // 3 +static const uint64_t SH_FLD_TP_TEST_BURNIN_MODE_DC = 21050; // 3 +static const uint64_t SH_FLD_TP_TPCPERV_VSB_TRACE_STOP = 21051; // 3 +static const uint64_t SH_FLD_TP_TPFSI_ACK = 21052; // 43 +static const uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL = 21053; // 30 +static const uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 21054; // 30 +static const uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL = 21055; // 30 +static const uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 21056; // 30 +static const uint64_t SH_FLD_TP_VITL_ACT_DIS_DC = 21057; // 3 +static const uint64_t SH_FLD_TP_VITL_CLKOFF_DC = 21058; // 3 +static const uint64_t SH_FLD_TP_VITL_DELAY_LCLKR_DC = 21059; // 3 +static const uint64_t SH_FLD_TP_VITL_MPW1_DC_N = 21060; // 3 +static const uint64_t SH_FLD_TP_VITL_MPW2_DC_N = 21061; // 3 +static const uint64_t SH_FLD_TP_VITL_MPW3_DC_N = 21062; // 3 +static const uint64_t SH_FLD_TP_VITL_SCAN_CLK_DC = 21063; // 3 +static const uint64_t SH_FLD_TP_VITL_SCIN_DC = 21064; // 3 +static const uint64_t SH_FLD_TR = 21065; // 96 +static const uint64_t SH_FLD_TRACE_BUS_BITS_0_63 = 21066; // 1 +static const uint64_t SH_FLD_TRACE_BUS_BITS_0_63_LEN = 21067; // 1 +static const uint64_t SH_FLD_TRACE_BUS_BITS_64_87 = 21068; // 1 +static const uint64_t SH_FLD_TRACE_BUS_BITS_64_87_LEN = 21069; // 1 +static const uint64_t SH_FLD_TRACE_BUS_EN = 21070; // 1 +static const uint64_t SH_FLD_TRACE_BUS_SEL_0_1 = 21071; // 1 +static const uint64_t SH_FLD_TRACE_BUS_SEL_0_1_LEN = 21072; // 1 +static const uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS = 21073; // 1 +static const uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN = 21074; // 1 +static const uint64_t SH_FLD_TRACE_DATA_SEL = 21075; // 17 +static const uint64_t SH_FLD_TRACE_DATA_SELECT = 21076; // 1 +static const uint64_t SH_FLD_TRACE_DATA_SELECT_LEN = 21077; // 1 +static const uint64_t SH_FLD_TRACE_DATA_SEL_LEN = 21078; // 17 +static const uint64_t SH_FLD_TRACE_DISABLE = 21079; // 1 +static const uint64_t SH_FLD_TRACE_ENABLE = 21080; // 10 +static const uint64_t SH_FLD_TRACE_EVENT = 21081; // 1 +static const uint64_t SH_FLD_TRACE_MODE = 21082; // 96 +static const uint64_t SH_FLD_TRACE_MODE_SEL = 21083; // 17 +static const uint64_t SH_FLD_TRACE_MODE_SEL_LEN = 21084; // 17 +static const uint64_t SH_FLD_TRACE_MUX_SEL = 21085; // 1 +static const uint64_t SH_FLD_TRACE_MUX_SEL_A = 21086; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_A_LEN = 21087; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_B = 21088; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_B_LEN = 21089; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_C = 21090; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_C_LEN = 21091; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_D = 21092; // 3 +static const uint64_t SH_FLD_TRACE_MUX_SEL_D_LEN = 21093; // 3 +static const uint64_t SH_FLD_TRACE_SEL = 21094; // 44 +static const uint64_t SH_FLD_TRACE_SELECT = 21095; // 3 +static const uint64_t SH_FLD_TRACE_SELECT_LEN = 21096; // 3 +static const uint64_t SH_FLD_TRACE_SEL_0_1 = 21097; // 1 +static const uint64_t SH_FLD_TRACE_SEL_0_1_LEN = 21098; // 1 +static const uint64_t SH_FLD_TRACE_SEL_LEN = 21099; // 44 +static const uint64_t SH_FLD_TRACE_TRIGGER = 21100; // 1 +static const uint64_t SH_FLD_TRACKING_TIMEOUT_SEL = 21101; // 6 +static const uint64_t SH_FLD_TRACKING_TIMEOUT_SEL_LEN = 21102; // 6 +static const uint64_t SH_FLD_TRAIN = 21103; // 10 +static const uint64_t SH_FLD_TRAIN_A_ADJ = 21104; // 2 +static const uint64_t SH_FLD_TRAIN_A_ADJ_LEN = 21105; // 2 +static const uint64_t SH_FLD_TRAIN_A_HYST = 21106; // 2 +static const uint64_t SH_FLD_TRAIN_A_HYST_LEN = 21107; // 2 +static const uint64_t SH_FLD_TRAIN_B_ADJ = 21108; // 2 +static const uint64_t SH_FLD_TRAIN_B_ADJ_LEN = 21109; // 2 +static const uint64_t SH_FLD_TRAIN_B_HYST = 21110; // 2 +static const uint64_t SH_FLD_TRAIN_B_HYST_LEN = 21111; // 2 +static const uint64_t SH_FLD_TRAIN_LEN = 21112; // 10 +static const uint64_t SH_FLD_TRAIN_TIME = 21113; // 2 +static const uint64_t SH_FLD_TRAIN_TIME_LEN = 21114; // 2 +static const uint64_t SH_FLD_TRANSPORT_INFORMATIONAL_ERR = 21115; // 4 +static const uint64_t SH_FLD_TRANS_DELAY = 21116; // 1 +static const uint64_t SH_FLD_TRANS_DELAY_LEN = 21117; // 1 +static const uint64_t SH_FLD_TRAPPED_DL_RETURN_P0 = 21118; // 43 +static const uint64_t SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY = 21119; // 43 +static const uint64_t SH_FLD_TRAPPED_GENERAL_TIMEOUT = 21120; // 43 +static const uint64_t SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID = 21121; // 43 +static const uint64_t SH_FLD_TRAPPED_PARALLEL_READ_NVLD = 21122; // 43 +static const uint64_t SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD = 21123; // 43 +static const uint64_t SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 21124; // 43 +static const uint64_t SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE = 21125; // 43 +static const uint64_t SH_FLD_TRAPPED_PCB_ADDRESS_PARITY = 21126; // 43 +static const uint64_t SH_FLD_TRAPPED_PCB_COMMAND_PARITY = 21127; // 43 +static const uint64_t SH_FLD_TRAPPED_PCB_WDATA_PARITY = 21128; // 43 +static const uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 21129; // 43 +static const uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 21130; // 43 +static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 21131; // 43 +static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 21132; // 43 +static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 21133; // 43 +static const uint64_t SH_FLD_TRAPPED_UL_P0 = 21134; // 43 +static const uint64_t SH_FLD_TRAPPED_UL_RDATA_PARITY = 21135; // 43 +static const uint64_t SH_FLD_TRASH_EN = 21136; // 12 +static const uint64_t SH_FLD_TRCD_CYCLES = 21137; // 8 +static const uint64_t SH_FLD_TRCD_CYCLES_LEN = 21138; // 8 +static const uint64_t SH_FLD_TRCTRL_CONFIG_D = 21139; // 144 +static const uint64_t SH_FLD_TRCTRL_CONFIG_D_LEN = 21140; // 72 +static const uint64_t SH_FLD_TRC_CMD_OVERRUN = 21141; // 1 +static const uint64_t SH_FLD_TRC_CYCLES = 21142; // 8 +static const uint64_t SH_FLD_TRC_CYCLES_LEN = 21143; // 8 +static const uint64_t SH_FLD_TRC_MODE = 21144; // 6 +static const uint64_t SH_FLD_TRC_MODE_LEN = 21145; // 6 +static const uint64_t SH_FLD_TRFC_CYCLES = 21146; // 8 +static const uint64_t SH_FLD_TRFC_CYCLES_LEN = 21147; // 8 +static const uint64_t SH_FLD_TRIG = 21148; // 17 +static const uint64_t SH_FLD_TRIG0_AND_MASK = 21149; // 162 +static const uint64_t SH_FLD_TRIG0_AND_MASK_LEN = 21150; // 162 +static const uint64_t SH_FLD_TRIG0_LEVEL_SEL = 21151; // 43 +static const uint64_t SH_FLD_TRIG0_LEVEL_SEL_LEN = 21152; // 43 +static const uint64_t SH_FLD_TRIG0_NOT_MODE = 21153; // 162 +static const uint64_t SH_FLD_TRIG0_OR_MASK = 21154; // 162 +static const uint64_t SH_FLD_TRIG0_OR_MASK_LEN = 21155; // 162 +static const uint64_t SH_FLD_TRIG1_AND_MASK = 21156; // 162 +static const uint64_t SH_FLD_TRIG1_AND_MASK_LEN = 21157; // 162 +static const uint64_t SH_FLD_TRIG1_LEVEL_SEL = 21158; // 43 +static const uint64_t SH_FLD_TRIG1_LEVEL_SEL_LEN = 21159; // 43 +static const uint64_t SH_FLD_TRIG1_NOT_MODE = 21160; // 162 +static const uint64_t SH_FLD_TRIG1_OR_MASK = 21161; // 162 +static const uint64_t SH_FLD_TRIG1_OR_MASK_LEN = 21162; // 162 +static const uint64_t SH_FLD_TRIG2_TRACE_EN = 21163; // 24 +static const uint64_t SH_FLD_TRIGGER = 21164; // 151 +static const uint64_t SH_FLD_TRIGGER1 = 21165; // 24 +static const uint64_t SH_FLD_TRIGGERED = 21166; // 1 +static const uint64_t SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL = 21167; // 43 +static const uint64_t SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL = 21168; // 43 +static const uint64_t SH_FLD_TRIGGER_OPCG_ON = 21169; // 129 +static const uint64_t SH_FLD_TRIG_FIR_HMI = 21170; // 96 +static const uint64_t SH_FLD_TRIG_SEL = 21171; // 43 +static const uint64_t SH_FLD_TRIG_SEL_LEN = 21172; // 43 +static const uint64_t SH_FLD_TRP_CYCLES = 21173; // 8 +static const uint64_t SH_FLD_TRP_CYCLES_LEN = 21174; // 8 +static const uint64_t SH_FLD_TRRD = 21175; // 8 +static const uint64_t SH_FLD_TRRD_LEN = 21176; // 8 +static const uint64_t SH_FLD_TRRD_SBG = 21177; // 8 +static const uint64_t SH_FLD_TRRD_SBG_LEN = 21178; // 8 +static const uint64_t SH_FLD_TRST_B_EQ0_ERR = 21179; // 1 +static const uint64_t SH_FLD_TRY_ATR_RO = 21180; // 1 +static const uint64_t SH_FLD_TR_LEN = 21181; // 96 +static const uint64_t SH_FLD_TS0 = 21182; // 96 +static const uint64_t SH_FLD_TS1 = 21183; // 96 +static const uint64_t SH_FLD_TSIZE = 21184; // 25 +static const uint64_t SH_FLD_TSIZE_4_6 = 21185; // 1 +static const uint64_t SH_FLD_TSIZE_4_6_LEN = 21186; // 1 +static const uint64_t SH_FLD_TSIZE_LEN = 21187; // 24 +static const uint64_t SH_FLD_TSIZE_MASK = 21188; // 8 +static const uint64_t SH_FLD_TSIZE_MASK_LEN = 21189; // 8 +static const uint64_t SH_FLD_TSIZE_MATCH = 21190; // 8 +static const uint64_t SH_FLD_TSIZE_MATCH_LEN = 21191; // 8 +static const uint64_t SH_FLD_TTAG_0_16 = 21192; // 1 +static const uint64_t SH_FLD_TTAG_0_16_LEN = 21193; // 1 +static const uint64_t SH_FLD_TTAG_PARITY = 21194; // 2 +static const uint64_t SH_FLD_TTAG_PARITY_ERROR = 21195; // 2 +static const uint64_t SH_FLD_TTYPE = 21196; // 24 +static const uint64_t SH_FLD_TTYPE_LEN = 21197; // 24 +static const uint64_t SH_FLD_TTYPE_MATCH = 21198; // 8 +static const uint64_t SH_FLD_TTYPE_MATCH_LEN = 21199; // 8 +static const uint64_t SH_FLD_TTYPE_REPLACE = 21200; // 8 +static const uint64_t SH_FLD_TTYPE_REPLACE_LEN = 21201; // 8 +static const uint64_t SH_FLD_TVT0_PAGE_SIZE = 21202; // 1 +static const uint64_t SH_FLD_TVT0_PAGE_SIZE_LEN = 21203; // 1 +static const uint64_t SH_FLD_TVT0_SPARE = 21204; // 1 +static const uint64_t SH_FLD_TVT0_SPARE_LEN = 21205; // 1 +static const uint64_t SH_FLD_TVT0_TABLE_LEVEL = 21206; // 1 +static const uint64_t SH_FLD_TVT0_TABLE_LEVEL_LEN = 21207; // 1 +static const uint64_t SH_FLD_TVT0_TABLE_SIZE = 21208; // 1 +static const uint64_t SH_FLD_TVT0_TABLE_SIZE_LEN = 21209; // 1 +static const uint64_t SH_FLD_TVT0_XLAT_ADDR = 21210; // 1 +static const uint64_t SH_FLD_TVT0_XLAT_ADDR_LEN = 21211; // 1 +static const uint64_t SH_FLD_TVT_ADDR_RANGE_ERR_ESR = 21212; // 1 +static const uint64_t SH_FLD_TVT_ENTRY_INVALID_ESR = 21213; // 1 +static const uint64_t SH_FLD_TVT_PERR_ESR = 21214; // 1 +static const uint64_t SH_FLD_TWLDQSEN_CYCLES = 21215; // 8 +static const uint64_t SH_FLD_TWLDQSEN_CYCLES_LEN = 21216; // 8 +static const uint64_t SH_FLD_TWLO_TWLOE = 21217; // 8 +static const uint64_t SH_FLD_TWLO_TWLOE_LEN = 21218; // 8 +static const uint64_t SH_FLD_TWO_CYCLE_ADDR_EN = 21219; // 8 +static const uint64_t SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD = 21220; // 2 +static const uint64_t SH_FLD_TWRMRD_CYCLES = 21221; // 8 +static const uint64_t SH_FLD_TWRMRD_CYCLES_LEN = 21222; // 8 +static const uint64_t SH_FLD_TWSM_DIS = 21223; // 1 +static const uint64_t SH_FLD_TWSM_DIS_LEN = 21224; // 1 +static const uint64_t SH_FLD_TW_ADD_ERR_CR_RD_DET = 21225; // 1 +static const uint64_t SH_FLD_TW_ADD_ERR_CR_WR_DET = 21226; // 1 +static const uint64_t SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS = 21227; // 1 +static const uint64_t SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS = 21228; // 1 +static const uint64_t SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS = 21229; // 1 +static const uint64_t SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS = 21230; // 1 +static const uint64_t SH_FLD_TW_BUS0_STG0_SEL = 21231; // 1 +static const uint64_t SH_FLD_TW_BUS0_STG0_SEL_LEN = 21232; // 1 +static const uint64_t SH_FLD_TW_BUS0_STG1_SEL = 21233; // 1 +static const uint64_t SH_FLD_TW_BUS0_STG2_SEL = 21234; // 1 +static const uint64_t SH_FLD_TW_BUS1_STG0_SEL = 21235; // 1 +static const uint64_t SH_FLD_TW_BUS1_STG0_SEL_LEN = 21236; // 1 +static const uint64_t SH_FLD_TW_BUS1_STG1_SEL = 21237; // 1 +static const uint64_t SH_FLD_TW_BUS1_STG2_SEL = 21238; // 1 +static const uint64_t SH_FLD_TW_CXT_CAC_DIS = 21239; // 1 +static const uint64_t SH_FLD_TW_CXT_CAC_PERR_DET = 21240; // 1 +static const uint64_t SH_FLD_TW_FOREIGN_ADDR_DET = 21241; // 1 +static const uint64_t SH_FLD_TW_INVALID_WIMG_DET = 21242; // 1 +static const uint64_t SH_FLD_TW_INV_RDX_QUAD_DET = 21243; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_C_DIS = 21244; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_EN = 21245; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_PDE_EN = 21246; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L2_DIS = 21247; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L3_DIS = 21248; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L4_DIS = 21249; // 1 +static const uint64_t SH_FLD_TW_LCO_RDX_P_DIS = 21250; // 1 +static const uint64_t SH_FLD_TW_MPSS_DIS = 21251; // 1 +static const uint64_t SH_FLD_TW_PG_FAULT_BPCHK_DET = 21252; // 1 +static const uint64_t SH_FLD_TW_PG_FAULT_NOPTE_DET = 21253; // 1 +static const uint64_t SH_FLD_TW_PG_FAULT_SEID_DET = 21254; // 1 +static const uint64_t SH_FLD_TW_PG_FAULT_VPCHK_DET = 21255; // 1 +static const uint64_t SH_FLD_TW_PREFETCH_ABT_DET = 21256; // 1 +static const uint64_t SH_FLD_TW_PROT_ERR_CHK_DIS = 21257; // 1 +static const uint64_t SH_FLD_TW_PTE_UPD_FAIL_DET = 21258; // 1 +static const uint64_t SH_FLD_TW_PTE_UPD_INTR_EN = 21259; // 1 +static const uint64_t SH_FLD_TW_RDX_CFG_GUEST_DET = 21260; // 1 +static const uint64_t SH_FLD_TW_RDX_CFG_HOST_DET = 21261; // 1 +static const uint64_t SH_FLD_TW_RDX_INT_PWC_DIS = 21262; // 1 +static const uint64_t SH_FLD_TW_RDX_INT_TLB_DIS = 21263; // 1 +static const uint64_t SH_FLD_TW_RDX_PWC_DIS = 21264; // 1 +static const uint64_t SH_FLD_TW_RDX_PWC_PERR_DET = 21265; // 1 +static const uint64_t SH_FLD_TW_RDX_PWC_SPLIT_EN = 21266; // 1 +static const uint64_t SH_FLD_TW_RDX_PWC_VA_HASH = 21267; // 1 +static const uint64_t SH_FLD_TW_SEG_FAULT_DET = 21268; // 1 +static const uint64_t SH_FLD_TW_SM_CTL_ERR_DET = 21269; // 1 +static const uint64_t SH_FLD_TW_TIMEOUT_CHK_DIS = 21270; // 1 +static const uint64_t SH_FLD_TW_TIMEOUT_ERR_DET = 21271; // 1 +static const uint64_t SH_FLD_TXAERR = 21272; // 6 +static const uint64_t SH_FLD_TXBERR = 21273; // 6 +static const uint64_t SH_FLD_TXCERR = 21274; // 6 +static const uint64_t SH_FLD_TXDERR = 21275; // 6 +static const uint64_t SH_FLD_TXEERR = 21276; // 6 +static const uint64_t SH_FLD_TXFERR = 21277; // 6 +static const uint64_t SH_FLD_TXGERR = 21278; // 6 +static const uint64_t SH_FLD_TXHERR = 21279; // 6 +static const uint64_t SH_FLD_TXIERR = 21280; // 6 +static const uint64_t SH_FLD_TXJERR = 21281; // 6 +static const uint64_t SH_FLD_TXKERR = 21282; // 6 +static const uint64_t SH_FLD_TXLERR = 21283; // 6 +static const uint64_t SH_FLD_TXMERR = 21284; // 6 +static const uint64_t SH_FLD_TXNERR = 21285; // 6 +static const uint64_t SH_FLD_TXOERR = 21286; // 6 +static const uint64_t SH_FLD_TXPERR = 21287; // 6 +static const uint64_t SH_FLD_TXSC = 21288; // 1 +static const uint64_t SH_FLD_TX_BIST_DONE_RO_SIGNAL = 21289; // 6 +static const uint64_t SH_FLD_TX_BUS_WIDTH = 21290; // 4 +static const uint64_t SH_FLD_TX_BUS_WIDTH_LEN = 21291; // 4 +static const uint64_t SH_FLD_TX_BW = 21292; // 10 +static const uint64_t SH_FLD_TX_BW_LEN = 21293; // 10 +static const uint64_t SH_FLD_TX_CH_FSM = 21294; // 1 +static const uint64_t SH_FLD_TX_CH_FSM_LEN = 21295; // 1 +static const uint64_t SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 21296; // 68 +static const uint64_t SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 21297; // 68 +static const uint64_t SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 21298; // 68 +static const uint64_t SH_FLD_TX_DATA_ECC_CORR_ENA = 21299; // 6 +static const uint64_t SH_FLD_TX_DF_FSM = 21300; // 1 +static const uint64_t SH_FLD_TX_DF_FSM_LEN = 21301; // 1 +static const uint64_t SH_FLD_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL = 21302; // 4 +static const uint64_t SH_FLD_TX_ECC_DATA_POISON_ENA = 21303; // 6 +static const uint64_t SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 21304; // 116 +static const uint64_t SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 21305; // 116 +static const uint64_t SH_FLD_TX_ERR_MODE_0 = 21306; // 1 +static const uint64_t SH_FLD_TX_ERR_MODE_1 = 21307; // 1 +static const uint64_t SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 21308; // 116 +static const uint64_t SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR = 21309; // 8 +static const uint64_t SH_FLD_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL = 21310; // 6 +static const uint64_t SH_FLD_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 21311; // 6 +static const uint64_t SH_FLD_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 21312; // 6 +static const uint64_t SH_FLD_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 21313; // 6 +static const uint64_t SH_FLD_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL = 21314; // 6 +static const uint64_t SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL = 21315; // 116 +static const uint64_t SH_FLD_TX_PL_FIR_ERR_RO_SIGNAL = 21316; // 6 +static const uint64_t SH_FLD_TX_PSI_BIST_DONE_RO_SIGNAL = 21317; // 1 +static const uint64_t SH_FLD_TX_PSI_BIST_DONE_RO_SIGNAL_LEN = 21318; // 1 +static const uint64_t SH_FLD_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL = 21319; // 1 +static const uint64_t SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 21320; // 68 +static const uint64_t SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 21321; // 68 +static const uint64_t SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 21322; // 68 +static const uint64_t SH_FLD_TX_SLS_DISABLE = 21323; // 4 +static const uint64_t SH_FLD_TX_SLS_HNDSHK_STATE_RO_SIGNAL = 21324; // 4 +static const uint64_t SH_FLD_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 21325; // 4 +static const uint64_t SH_FLD_TX_SLS_LN_MV_TIMEOUT_SEL = 21326; // 4 +static const uint64_t SH_FLD_TX_SLS_LN_MV_TIMEOUT_SEL_LEN = 21327; // 4 +static const uint64_t SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL = 21328; // 116 +static const uint64_t SH_FLD_TX_TFMR_CORRUPT_ERRHOLD = 21329; // 2 +static const uint64_t SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 21330; // 1 +static const uint64_t SH_FLD_TX_TTYPE_PIB_MST_IF_RESET = 21331; // 1 +static const uint64_t SH_FLD_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL = 21332; // 4 +static const uint64_t SH_FLD_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL = 21333; // 4 +static const uint64_t SH_FLD_TX_ZCAL_BUSY_RO_SIGNAL = 21334; // 4 +static const uint64_t SH_FLD_TX_ZCAL_CMP_OUT_RO_SIGNAL = 21335; // 4 +static const uint64_t SH_FLD_TX_ZCAL_DONE_RO_SIGNAL = 21336; // 4 +static const uint64_t SH_FLD_TX_ZCAL_ERROR_RO_SIGNAL = 21337; // 4 +static const uint64_t SH_FLD_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL = 21338; // 4 +static const uint64_t SH_FLD_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL = 21339; // 4 +static const uint64_t SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL = 21340; // 4 +static const uint64_t SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN = 21341; // 4 +static const uint64_t SH_FLD_TX_ZCAL_TEST_DONE_RO_SIGNAL = 21342; // 4 +static const uint64_t SH_FLD_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL = 21343; // 4 +static const uint64_t SH_FLD_TX_ZCAL_TEST_STATUS_RO_SIGNAL = 21344; // 4 +static const uint64_t SH_FLD_TYPE = 21345; // 108 +static const uint64_t SH_FLD_TYPE_LEN = 21346; // 44 +static const uint64_t SH_FLD_TZQCS_CYCLES = 21347; // 8 +static const uint64_t SH_FLD_TZQCS_CYCLES_LEN = 21348; // 8 +static const uint64_t SH_FLD_TZQINIT_CYCLES = 21349; // 8 +static const uint64_t SH_FLD_TZQINIT_CYCLES_LEN = 21350; // 8 +static const uint64_t SH_FLD_UE = 21351; // 10 +static const uint64_t SH_FLD_UE1_0_OUT = 21352; // 4 +static const uint64_t SH_FLD_UE1_1_OUT = 21353; // 4 +static const uint64_t SH_FLD_UE1_2_OUT = 21354; // 4 +static const uint64_t SH_FLD_UE1_3_OUT = 21355; // 4 +static const uint64_t SH_FLD_UE1_4_OUT = 21356; // 4 +static const uint64_t SH_FLD_UE1_5_OUT = 21357; // 4 +static const uint64_t SH_FLD_UE1_6_OUT = 21358; // 4 +static const uint64_t SH_FLD_UE1_7_OUT = 21359; // 4 +static const uint64_t SH_FLD_UE2_0_OUT = 21360; // 4 +static const uint64_t SH_FLD_UE2_1_OUT = 21361; // 4 +static const uint64_t SH_FLD_UE2_2_OUT = 21362; // 4 +static const uint64_t SH_FLD_UE2_3_OUT = 21363; // 4 +static const uint64_t SH_FLD_UE2_4_OUT = 21364; // 4 +static const uint64_t SH_FLD_UE2_5_OUT = 21365; // 4 +static const uint64_t SH_FLD_UE2_6_OUT = 21366; // 4 +static const uint64_t SH_FLD_UE2_7_OUT = 21367; // 4 +static const uint64_t SH_FLD_UE_COUNT = 21368; // 2 +static const uint64_t SH_FLD_UE_COUNT_LEN = 21369; // 2 +static const uint64_t SH_FLD_UE_DISABLE = 21370; // 2 +static const uint64_t SH_FLD_UE_LEN = 21371; // 10 +static const uint64_t SH_FLD_UL_P0 = 21372; // 43 +static const uint64_t SH_FLD_UL_RDATA_PARITY = 21373; // 43 +static const uint64_t SH_FLD_UMAC_CRB_SUE = 21374; // 1 +static const uint64_t SH_FLD_UMAC_CRB_UE = 21375; // 1 +static const uint64_t SH_FLD_UMAC_LD_LINK_ERR = 21376; // 1 +static const uint64_t SH_FLD_UMAC_LINK_ABORT = 21377; // 1 +static const uint64_t SH_FLD_UMAC_MUX_SELECT = 21378; // 1 +static const uint64_t SH_FLD_UMAC_MUX_SELECT_LEN = 21379; // 1 +static const uint64_t SH_FLD_UMAC_RD_DISABLE_GROUP = 21380; // 1 +static const uint64_t SH_FLD_UMAC_RD_DISABLE_LN = 21381; // 1 +static const uint64_t SH_FLD_UMAC_RD_DISABLE_NN_RN = 21382; // 1 +static const uint64_t SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS = 21383; // 1 +static const uint64_t SH_FLD_UMAC_SCOM_SAT_ERR = 21384; // 1 +static const uint64_t SH_FLD_UMAC_WC_INT_ADDR_UE = 21385; // 1 +static const uint64_t SH_FLD_UMAC_WR_DISABLE_GROUP = 21386; // 1 +static const uint64_t SH_FLD_UMAC_WR_DISABLE_LN = 21387; // 1 +static const uint64_t SH_FLD_UMAC_WR_DISABLE_NN_RN = 21388; // 1 +static const uint64_t SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS = 21389; // 1 +static const uint64_t SH_FLD_UNCORR_ERROR = 21390; // 1 +static const uint64_t SH_FLD_UNEXPECTED_CRESP = 21391; // 2 +static const uint64_t SH_FLD_UNEXPECTED_DATA_OR_CRESP = 21392; // 4 +static const uint64_t SH_FLD_UNEXPECTED_DROOP_ENCODE = 21393; // 12 +static const uint64_t SH_FLD_UNEXPECTED_PB = 21394; // 4 +static const uint64_t SH_FLD_UNEXPECT_DATA = 21395; // 1 +static const uint64_t SH_FLD_UNIT1 = 21396; // 215 +static const uint64_t SH_FLD_UNIT10 = 21397; // 215 +static const uint64_t SH_FLD_UNIT2 = 21398; // 215 +static const uint64_t SH_FLD_UNIT3 = 21399; // 215 +static const uint64_t SH_FLD_UNIT4 = 21400; // 215 +static const uint64_t SH_FLD_UNIT5 = 21401; // 215 +static const uint64_t SH_FLD_UNIT6 = 21402; // 215 +static const uint64_t SH_FLD_UNIT7 = 21403; // 215 +static const uint64_t SH_FLD_UNIT8 = 21404; // 215 +static const uint64_t SH_FLD_UNIT9 = 21405; // 215 +static const uint64_t SH_FLD_UNIT_REGION_CLKCMD_ENABLE = 21406; // 43 +static const uint64_t SH_FLD_UNIT_SYNC_LVL_ERR = 21407; // 43 +static const uint64_t SH_FLD_UNLOAD_CLK_DISABLE = 21408; // 116 +static const uint64_t SH_FLD_UNLOAD_SEL = 21409; // 116 +static const uint64_t SH_FLD_UNLOAD_SEL_LEN = 21410; // 116 +static const uint64_t SH_FLD_UNRECOV = 21411; // 10 +static const uint64_t SH_FLD_UNRECOV_LEN = 21412; // 10 +static const uint64_t SH_FLD_UNSOLICITED_CRESP = 21413; // 3 +static const uint64_t SH_FLD_UNSOLICITED_DATA_RCV_ERRHOLD = 21414; // 2 +static const uint64_t SH_FLD_UNSOLICITED_PBDATA = 21415; // 1 +static const uint64_t SH_FLD_UNTRUSTED = 21416; // 4 +static const uint64_t SH_FLD_UNTRUSTED_LEN = 21417; // 4 +static const uint64_t SH_FLD_UNUSED = 21418; // 530 +static const uint64_t SH_FLD_UNUSED0 = 21419; // 3 +static const uint64_t SH_FLD_UNUSED0A = 21420; // 3 +static const uint64_t SH_FLD_UNUSED0B = 21421; // 3 +static const uint64_t SH_FLD_UNUSED0B_LEN = 21422; // 3 +static const uint64_t SH_FLD_UNUSED0_LEN = 21423; // 2 +static const uint64_t SH_FLD_UNUSED1 = 21424; // 89 +static const uint64_t SH_FLD_UNUSED1219 = 21425; // 43 +static const uint64_t SH_FLD_UNUSED1219_LEN = 21426; // 43 +static const uint64_t SH_FLD_UNUSED1520 = 21427; // 43 +static const uint64_t SH_FLD_UNUSED1520_LEN = 21428; // 43 +static const uint64_t SH_FLD_UNUSED1A = 21429; // 3 +static const uint64_t SH_FLD_UNUSED1B = 21430; // 3 +static const uint64_t SH_FLD_UNUSED1B_LEN = 21431; // 3 +static const uint64_t SH_FLD_UNUSED1_LEN = 21432; // 88 +static const uint64_t SH_FLD_UNUSED2 = 21433; // 89 +static const uint64_t SH_FLD_UNUSED23 = 21434; // 2 +static const uint64_t SH_FLD_UNUSED23_31 = 21435; // 7 +static const uint64_t SH_FLD_UNUSED23_31_LEN = 21436; // 7 +static const uint64_t SH_FLD_UNUSED2_LEN = 21437; // 81 +static const uint64_t SH_FLD_UNUSED3 = 21438; // 9 +static const uint64_t SH_FLD_UNUSED3_LEN = 21439; // 6 +static const uint64_t SH_FLD_UNUSED4 = 21440; // 14 +static const uint64_t SH_FLD_UNUSED41_63 = 21441; // 43 +static const uint64_t SH_FLD_UNUSED41_63_LEN = 21442; // 43 +static const uint64_t SH_FLD_UNUSED46 = 21443; // 43 +static const uint64_t SH_FLD_UNUSED4_LEN = 21444; // 6 +static const uint64_t SH_FLD_UNUSED5 = 21445; // 12 +static const uint64_t SH_FLD_UNUSED50 = 21446; // 2 +static const uint64_t SH_FLD_UNUSED51 = 21447; // 2 +static const uint64_t SH_FLD_UNUSED5_LEN = 21448; // 5 +static const uint64_t SH_FLD_UNUSED63 = 21449; // 3 +static const uint64_t SH_FLD_UNUSED88 = 21450; // 3 +static const uint64_t SH_FLD_UNUSED88_LEN = 21451; // 3 +static const uint64_t SH_FLD_UNUSED_0 = 21452; // 44 +static const uint64_t SH_FLD_UNUSED_0B = 21453; // 43 +static const uint64_t SH_FLD_UNUSED_0D = 21454; // 35 +static const uint64_t SH_FLD_UNUSED_1 = 21455; // 68 +static const uint64_t SH_FLD_UNUSED_10B = 21456; // 35 +static const uint64_t SH_FLD_UNUSED_11B = 21457; // 36 +static const uint64_t SH_FLD_UNUSED_12B = 21458; // 37 +static const uint64_t SH_FLD_UNUSED_13B = 21459; // 37 +static const uint64_t SH_FLD_UNUSED_14B = 21460; // 43 +static const uint64_t SH_FLD_UNUSED_16_22 = 21461; // 1 +static const uint64_t SH_FLD_UNUSED_16_22_LEN = 21462; // 1 +static const uint64_t SH_FLD_UNUSED_17B = 21463; // 43 +static const uint64_t SH_FLD_UNUSED_18 = 21464; // 24 +static const uint64_t SH_FLD_UNUSED_18B = 21465; // 43 +static const uint64_t SH_FLD_UNUSED_19 = 21466; // 24 +static const uint64_t SH_FLD_UNUSED_19B = 21467; // 43 +static const uint64_t SH_FLD_UNUSED_1B = 21468; // 43 +static const uint64_t SH_FLD_UNUSED_1D = 21469; // 35 +static const uint64_t SH_FLD_UNUSED_2 = 21470; // 111 +static const uint64_t SH_FLD_UNUSED_20B = 21471; // 42 +static const uint64_t SH_FLD_UNUSED_21 = 21472; // 24 +static const uint64_t SH_FLD_UNUSED_21B = 21473; // 41 +static const uint64_t SH_FLD_UNUSED_22 = 21474; // 24 +static const uint64_t SH_FLD_UNUSED_22B = 21475; // 43 +static const uint64_t SH_FLD_UNUSED_23 = 21476; // 24 +static const uint64_t SH_FLD_UNUSED_23B = 21477; // 43 +static const uint64_t SH_FLD_UNUSED_24B = 21478; // 43 +static const uint64_t SH_FLD_UNUSED_25B = 21479; // 43 +static const uint64_t SH_FLD_UNUSED_26B = 21480; // 43 +static const uint64_t SH_FLD_UNUSED_26_31 = 21481; // 1 +static const uint64_t SH_FLD_UNUSED_26_31_LEN = 21482; // 1 +static const uint64_t SH_FLD_UNUSED_27B = 21483; // 43 +static const uint64_t SH_FLD_UNUSED_28B = 21484; // 43 +static const uint64_t SH_FLD_UNUSED_29B = 21485; // 43 +static const uint64_t SH_FLD_UNUSED_2B = 21486; // 43 +static const uint64_t SH_FLD_UNUSED_2D = 21487; // 35 +static const uint64_t SH_FLD_UNUSED_2_LEN = 21488; // 86 +static const uint64_t SH_FLD_UNUSED_3 = 21489; // 1 +static const uint64_t SH_FLD_UNUSED_30B = 21490; // 43 +static const uint64_t SH_FLD_UNUSED_31B = 21491; // 43 +static const uint64_t SH_FLD_UNUSED_39_43 = 21492; // 1 +static const uint64_t SH_FLD_UNUSED_39_43_LEN = 21493; // 1 +static const uint64_t SH_FLD_UNUSED_3D = 21494; // 35 +static const uint64_t SH_FLD_UNUSED_40 = 21495; // 24 +static const uint64_t SH_FLD_UNUSED_42 = 21496; // 24 +static const uint64_t SH_FLD_UNUSED_44 = 21497; // 24 +static const uint64_t SH_FLD_UNUSED_46 = 21498; // 24 +static const uint64_t SH_FLD_UNUSED_47_51 = 21499; // 1 +static const uint64_t SH_FLD_UNUSED_47_51_LEN = 21500; // 1 +static const uint64_t SH_FLD_UNUSED_49 = 21501; // 24 +static const uint64_t SH_FLD_UNUSED_4_15 = 21502; // 1 +static const uint64_t SH_FLD_UNUSED_4_15_LEN = 21503; // 1 +static const uint64_t SH_FLD_UNUSED_50 = 21504; // 24 +static const uint64_t SH_FLD_UNUSED_51 = 21505; // 24 +static const uint64_t SH_FLD_UNUSED_53 = 21506; // 1 +static const uint64_t SH_FLD_UNUSED_54 = 21507; // 24 +static const uint64_t SH_FLD_UNUSED_5B = 21508; // 1 +static const uint64_t SH_FLD_UNUSED_6 = 21509; // 24 +static const uint64_t SH_FLD_UNUSED_6B = 21510; // 1 +static const uint64_t SH_FLD_UNUSED_7 = 21511; // 24 +static const uint64_t SH_FLD_UNUSED_7B = 21512; // 27 +static const uint64_t SH_FLD_UNUSED_8B = 21513; // 31 +static const uint64_t SH_FLD_UNUSED_8_14 = 21514; // 1 +static const uint64_t SH_FLD_UNUSED_8_14_LEN = 21515; // 1 +static const uint64_t SH_FLD_UNUSED_9B = 21516; // 33 +static const uint64_t SH_FLD_UNUSED_ERROR27 = 21517; // 43 +static const uint64_t SH_FLD_UNUSED_ERROR28 = 21518; // 43 +static const uint64_t SH_FLD_UNUSED_ERROR29 = 21519; // 43 +static const uint64_t SH_FLD_UNUSED_ERROR30 = 21520; // 43 +static const uint64_t SH_FLD_UNUSED_ERROR31 = 21521; // 43 +static const uint64_t SH_FLD_UNUSED_LEN = 21522; // 278 +static const uint64_t SH_FLD_UOP_REGS_CE_ERR = 21523; // 2 +static const uint64_t SH_FLD_UOP_REGS_UE_ERR = 21524; // 2 +static const uint64_t SH_FLD_UPDATE_COMPLETE = 21525; // 6 +static const uint64_t SH_FLD_UPDATE_ERR = 21526; // 2 +static const uint64_t SH_FLD_UPFIFO_ACK = 21527; // 1 +static const uint64_t SH_FLD_UPFIFO_DATA_IN_PORT = 21528; // 1 +static const uint64_t SH_FLD_UPFIFO_DATA_IN_PORT_LEN = 21529; // 1 +static const uint64_t SH_FLD_UPFIFO_DATA_OUT_PORT = 21530; // 1 +static const uint64_t SH_FLD_UPFIFO_DATA_OUT_PORT_LEN = 21531; // 1 +static const uint64_t SH_FLD_UPFIFO_REQ_RESET = 21532; // 1 +static const uint64_t SH_FLD_UPFIFO_RESET = 21533; // 1 +static const uint64_t SH_FLD_UPFIFO_SIGNAL = 21534; // 1 +static const uint64_t SH_FLD_UPRT = 21535; // 96 +static const uint64_t SH_FLD_UPSTREAM = 21536; // 4 +static const uint64_t SH_FLD_US = 21537; // 96 +static const uint64_t SH_FLD_USERDEF_CFG = 21538; // 6 +static const uint64_t SH_FLD_USERDEF_CFG_LEN = 21539; // 6 +static const uint64_t SH_FLD_USERDEF_TIMEOUT = 21540; // 6 +static const uint64_t SH_FLD_USERDEF_TIMEOUT_LEN = 21541; // 6 +static const uint64_t SH_FLD_USER_FILTER_MASK = 21542; // 6 +static const uint64_t SH_FLD_USER_FILTER_MASK_LEN = 21543; // 6 +static const uint64_t SH_FLD_USE_FOR_SCAN = 21544; // 43 +static const uint64_t SH_FLD_USE_OSC_OBSERVATION = 21545; // 1 +static const uint64_t SH_FLD_USE_OSC_OBSERVATION_LEN = 21546; // 1 +static const uint64_t SH_FLD_USE_PECE = 21547; // 48 +static const uint64_t SH_FLD_USE_PECE_LEN = 21548; // 48 +static const uint64_t SH_FLD_USE_PREV_COARSE_VAL = 21549; // 4 +static const uint64_t SH_FLD_USE_REC_LIMIT = 21550; // 24 +static const uint64_t SH_FLD_USE_SLS_AS_SPR = 21551; // 4 +static const uint64_t SH_FLD_USE_TB_STEP_SYNC = 21552; // 1 +static const uint64_t SH_FLD_USE_TB_SYNC_MECHANISM = 21553; // 1 +static const uint64_t SH_FLD_USE_WATCH_TO_READ_CTRL_ARY = 21554; // 2 +static const uint64_t SH_FLD_USRR0 = 21555; // 48 +static const uint64_t SH_FLD_USRR0_LEN = 21556; // 48 +static const uint64_t SH_FLD_UT = 21557; // 24 +static const uint64_t SH_FLD_UV_AUTO_INC = 21558; // 6 +static const uint64_t SH_FLD_UV_REQ_ADDR_VALUE = 21559; // 6 +static const uint64_t SH_FLD_UV_REQ_ADDR_VALUE_LEN = 21560; // 6 +static const uint64_t SH_FLD_UV_REQ_ADDR_VLD = 21561; // 6 +static const uint64_t SH_FLD_V205 = 21562; // 96 +static const uint64_t SH_FLD_V206 = 21563; // 96 +static const uint64_t SH_FLD_V207 = 21564; // 96 +static const uint64_t SH_FLD_VALID = 21565; // 72 +static const uint64_t SH_FLD_VALID_ATRGPA0 = 21566; // 256 +static const uint64_t SH_FLD_VALID_ATRGPA1 = 21567; // 256 +static const uint64_t SH_FLD_VALID_ATSD = 21568; // 256 +static const uint64_t SH_FLD_VALID_ENTRY = 21569; // 1 +static const uint64_t SH_FLD_VALUE = 21570; // 48 +static const uint64_t SH_FLD_VALUES0 = 21571; // 16 +static const uint64_t SH_FLD_VALUES0_LEN = 21572; // 16 +static const uint64_t SH_FLD_VALUES1 = 21573; // 16 +static const uint64_t SH_FLD_VALUES1_LEN = 21574; // 16 +static const uint64_t SH_FLD_VALUES2 = 21575; // 16 +static const uint64_t SH_FLD_VALUES2_LEN = 21576; // 16 +static const uint64_t SH_FLD_VALUES3 = 21577; // 16 +static const uint64_t SH_FLD_VALUES3_LEN = 21578; // 16 +static const uint64_t SH_FLD_VALUES4 = 21579; // 16 +static const uint64_t SH_FLD_VALUES4_LEN = 21580; // 16 +static const uint64_t SH_FLD_VALUES5 = 21581; // 16 +static const uint64_t SH_FLD_VALUES5_LEN = 21582; // 16 +static const uint64_t SH_FLD_VALUES6 = 21583; // 16 +static const uint64_t SH_FLD_VALUES6_LEN = 21584; // 16 +static const uint64_t SH_FLD_VALUES7 = 21585; // 16 +static const uint64_t SH_FLD_VALUES7_LEN = 21586; // 16 +static const uint64_t SH_FLD_VALUE_LEN = 21587; // 48 +static const uint64_t SH_FLD_VAS_LOCAL_XSTOP = 21588; // 1 +static const uint64_t SH_FLD_VBGENDOC = 21589; // 3 +static const uint64_t SH_FLD_VBGENDOC_LEN = 21590; // 3 +static const uint64_t SH_FLD_VC = 21591; // 96 +static const uint64_t SH_FLD_VCORANGE = 21592; // 10 +static const uint64_t SH_FLD_VCORANGE_LEN = 21593; // 10 +static const uint64_t SH_FLD_VCOSEL = 21594; // 10 +static const uint64_t SH_FLD_VCS_PFETS_DISABLED_SENSE = 21595; // 30 +static const uint64_t SH_FLD_VCS_PFETS_ENABLED_SENSE = 21596; // 30 +static const uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE = 21597; // 30 +static const uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE_LEN = 21598; // 30 +static const uint64_t SH_FLD_VCS_PFET_FORCE_STATE = 21599; // 30 +static const uint64_t SH_FLD_VCS_PFET_FORCE_STATE_LEN = 21600; // 30 +static const uint64_t SH_FLD_VCS_PFET_SEL_OVERRIDE = 21601; // 30 +static const uint64_t SH_FLD_VCS_PFET_SEL_VALUE = 21602; // 30 +static const uint64_t SH_FLD_VCS_PFET_SEL_VALUE_LEN = 21603; // 30 +static const uint64_t SH_FLD_VCS_PFET_VAL_OVERRIDE = 21604; // 30 +static const uint64_t SH_FLD_VCS_PG_SEL = 21605; // 60 +static const uint64_t SH_FLD_VCS_PG_SEL_LEN = 21606; // 60 +static const uint64_t SH_FLD_VCS_PG_STATE = 21607; // 60 +static const uint64_t SH_FLD_VCS_PG_STATE_LEN = 21608; // 60 +static const uint64_t SH_FLD_VCS_VOFF_SEL = 21609; // 30 +static const uint64_t SH_FLD_VCS_VOFF_SEL_LEN = 21610; // 30 +static const uint64_t SH_FLD_VC_CRD_AVAIL_PERR = 21611; // 1 +static const uint64_t SH_FLD_VC_CRD_PERR = 21612; // 1 +static const uint64_t SH_FLD_VC_FATAL_ERROR_0_1 = 21613; // 1 +static const uint64_t SH_FLD_VC_FATAL_ERROR_0_1_LEN = 21614; // 1 +static const uint64_t SH_FLD_VC_INFO_ERROR_0_1 = 21615; // 1 +static const uint64_t SH_FLD_VC_INFO_ERROR_0_1_LEN = 21616; // 1 +static const uint64_t SH_FLD_VC_LEN = 21617; // 96 +static const uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3 = 21618; // 1 +static const uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN = 21619; // 1 +static const uint64_t SH_FLD_VC_RECOV_ERROR_0_1 = 21620; // 1 +static const uint64_t SH_FLD_VC_RECOV_ERROR_0_1_LEN = 21621; // 1 +static const uint64_t SH_FLD_VDD2VIO_LVL_FENCE_DC = 21622; // 3 +static const uint64_t SH_FLD_VDD_NEST_OBSERVE = 21623; // 1 +static const uint64_t SH_FLD_VDD_PFETS_DISABLED_SENSE = 21624; // 30 +static const uint64_t SH_FLD_VDD_PFETS_ENABLED_SENSE = 21625; // 30 +static const uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE = 21626; // 30 +static const uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE_LEN = 21627; // 30 +static const uint64_t SH_FLD_VDD_PFET_FORCE_STATE = 21628; // 30 +static const uint64_t SH_FLD_VDD_PFET_FORCE_STATE_LEN = 21629; // 30 +static const uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_EN = 21630; // 30 +static const uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE = 21631; // 30 +static const uint64_t SH_FLD_VDD_PFET_SEL_OVERRIDE = 21632; // 30 +static const uint64_t SH_FLD_VDD_PFET_SEL_VALUE = 21633; // 30 +static const uint64_t SH_FLD_VDD_PFET_SEL_VALUE_LEN = 21634; // 30 +static const uint64_t SH_FLD_VDD_PFET_VAL_OVERRIDE = 21635; // 30 +static const uint64_t SH_FLD_VDD_PG_SEL = 21636; // 60 +static const uint64_t SH_FLD_VDD_PG_SEL_LEN = 21637; // 60 +static const uint64_t SH_FLD_VDD_PG_STATE = 21638; // 60 +static const uint64_t SH_FLD_VDD_PG_STATE_LEN = 21639; // 60 +static const uint64_t SH_FLD_VDD_VOFF_SEL = 21640; // 30 +static const uint64_t SH_FLD_VDD_VOFF_SEL_LEN = 21641; // 30 +static const uint64_t SH_FLD_VDM_DISABLE = 21642; // 30 +static const uint64_t SH_FLD_VDM_DROOP_LARGE = 21643; // 6 +static const uint64_t SH_FLD_VDM_DROOP_LARGE_LEN = 21644; // 6 +static const uint64_t SH_FLD_VDM_DROOP_SMALL = 21645; // 6 +static const uint64_t SH_FLD_VDM_DROOP_SMALL_LEN = 21646; // 6 +static const uint64_t SH_FLD_VDM_DROOP_XTREME = 21647; // 6 +static const uint64_t SH_FLD_VDM_DROOP_XTREME_LEN = 21648; // 6 +static const uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR = 21649; // 12 +static const uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR_LEN = 21650; // 12 +static const uint64_t SH_FLD_VDM_EXTREME_DROOP_THRESHOLD = 21651; // 12 +static const uint64_t SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN = 21652; // 12 +static const uint64_t SH_FLD_VDM_LARGE_DROOP_CTR = 21653; // 12 +static const uint64_t SH_FLD_VDM_LARGE_DROOP_CTR_LEN = 21654; // 12 +static const uint64_t SH_FLD_VDM_LARGE_DROOP_THRESHOLD = 21655; // 12 +static const uint64_t SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN = 21656; // 12 +static const uint64_t SH_FLD_VDM_LCL_SAMPLE_EN = 21657; // 12 +static const uint64_t SH_FLD_VDM_NO_DROOP_CTR = 21658; // 12 +static const uint64_t SH_FLD_VDM_NO_DROOP_CTR_LEN = 21659; // 12 +static const uint64_t SH_FLD_VDM_OVERVOLT = 21660; // 6 +static const uint64_t SH_FLD_VDM_OVERVOLT_CTR = 21661; // 12 +static const uint64_t SH_FLD_VDM_OVERVOLT_CTR_LEN = 21662; // 12 +static const uint64_t SH_FLD_VDM_OVERVOLT_LEN = 21663; // 6 +static const uint64_t SH_FLD_VDM_POWERON = 21664; // 30 +static const uint64_t SH_FLD_VDM_SMALL_DROOP_CTR = 21665; // 12 +static const uint64_t SH_FLD_VDM_SMALL_DROOP_CTR_LEN = 21666; // 12 +static const uint64_t SH_FLD_VDM_SMALL_DROOP_THRESHOLD = 21667; // 12 +static const uint64_t SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN = 21668; // 12 +static const uint64_t SH_FLD_VDM_VID_COMPARE = 21669; // 6 +static const uint64_t SH_FLD_VDM_VID_COMPARE_LEN = 21670; // 6 +static const uint64_t SH_FLD_VEC = 21671; // 96 +static const uint64_t SH_FLD_VECTOR_GROUP_EPSILON = 21672; // 8 +static const uint64_t SH_FLD_VECTOR_GROUP_EPSILON_LEN = 21673; // 8 +static const uint64_t SH_FLD_VERSION = 21674; // 24 +static const uint64_t SH_FLD_VERSION_LEN = 21675; // 24 +static const uint64_t SH_FLD_VG = 21676; // 1 +static const uint64_t SH_FLD_VG_COUNT = 21677; // 2 +static const uint64_t SH_FLD_VG_COUNT_LEN = 21678; // 2 +static const uint64_t SH_FLD_VG_TARGE = 21679; // 1 +static const uint64_t SH_FLD_VG_TARGET_SEL = 21680; // 24 +static const uint64_t SH_FLD_VG_TARGE_LEN = 21681; // 1 +static const uint64_t SH_FLD_VID_COMPARE_MAX = 21682; // 6 +static const uint64_t SH_FLD_VID_COMPARE_MAX_LEN = 21683; // 6 +static const uint64_t SH_FLD_VID_COMPARE_MIN = 21684; // 6 +static const uint64_t SH_FLD_VID_COMPARE_MIN_LEN = 21685; // 6 +static const uint64_t SH_FLD_VITAL_AL = 21686; // 43 +static const uint64_t SH_FLD_VITAL_PHASE = 21687; // 43 +static const uint64_t SH_FLD_VITAL_SCAN = 21688; // 43 +static const uint64_t SH_FLD_VITAL_SCAN_IN = 21689; // 43 +static const uint64_t SH_FLD_VITAL_THOLD = 21690; // 43 +static const uint64_t SH_FLD_VITL = 21691; // 43 +static const uint64_t SH_FLD_VITL_ALIGN_ERR = 21692; // 43 +static const uint64_t SH_FLD_VITL_CLKOFF = 21693; // 43 +static const uint64_t SH_FLD_VMEAS_MAX_RESULT = 21694; // 1 +static const uint64_t SH_FLD_VMEAS_MAX_RESULT_LEN = 21695; // 1 +static const uint64_t SH_FLD_VMEAS_MIN_RESULT = 21696; // 1 +static const uint64_t SH_FLD_VMEAS_MIN_RESULT_LEN = 21697; // 1 +static const uint64_t SH_FLD_VMX_CRYPTO_DIS = 21698; // 24 +static const uint64_t SH_FLD_VOFF_CFG = 21699; // 6 +static const uint64_t SH_FLD_VOFF_CFG_LEN = 21700; // 6 +static const uint64_t SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD = 21701; // 43 +static const uint64_t SH_FLD_VOLT_MODEREG_PARITY_MASK = 21702; // 43 +static const uint64_t SH_FLD_VP = 21703; // 1 +static const uint64_t SH_FLD_VPC_DMA_ORDERING_TAG = 21704; // 1 +static const uint64_t SH_FLD_VPC_DMA_ORDERING_TAG_LEN = 21705; // 1 +static const uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG = 21706; // 1 +static const uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN = 21707; // 1 +static const uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG = 21708; // 1 +static const uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN = 21709; // 1 +static const uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG = 21710; // 1 +static const uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN = 21711; // 1 +static const uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG = 21712; // 1 +static const uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN = 21713; // 1 +static const uint64_t SH_FLD_VPD_DMA_READ = 21714; // 1 +static const uint64_t SH_FLD_VPD_DMA_READ_LEN = 21715; // 1 +static const uint64_t SH_FLD_VPD_DMA_WRITE = 21716; // 1 +static const uint64_t SH_FLD_VPD_DMA_WRITE_LEN = 21717; // 1 +static const uint64_t SH_FLD_VPROTH = 21718; // 8 +static const uint64_t SH_FLD_VPROTH_PSEL_MODE = 21719; // 8 +static const uint64_t SH_FLD_VREF = 21720; // 9 +static const uint64_t SH_FLD_VREFDQ0D = 21721; // 8 +static const uint64_t SH_FLD_VREFDQ0DSGN = 21722; // 8 +static const uint64_t SH_FLD_VREFDQ0D_LEN = 21723; // 8 +static const uint64_t SH_FLD_VREFDQ1D = 21724; // 8 +static const uint64_t SH_FLD_VREFDQ1DSGN = 21725; // 8 +static const uint64_t SH_FLD_VREFDQ1D_LEN = 21726; // 8 +static const uint64_t SH_FLD_VREFTUNE = 21727; // 3 +static const uint64_t SH_FLD_VREFTUNE_LEN = 21728; // 3 +static const uint64_t SH_FLD_VREF_LEN = 21729; // 1 +static const uint64_t SH_FLD_VREGBYP = 21730; // 6 +static const uint64_t SH_FLD_VREGBYPASS = 21731; // 4 +static const uint64_t SH_FLD_VREGENABLE_N = 21732; // 4 +static const uint64_t SH_FLD_VREG_S = 21733; // 8 +static const uint64_t SH_FLD_VRMASD = 21734; // 96 +static const uint64_t SH_FLD_VRMASD_LEN = 21735; // 96 +static const uint64_t SH_FLD_VSEL = 21736; // 10 +static const uint64_t SH_FLD_VSEL_LEN = 21737; // 10 +static const uint64_t SH_FLD_VST_TYPE = 21738; // 1 +static const uint64_t SH_FLD_VST_TYPE_LEN = 21739; // 1 +static const uint64_t SH_FLD_VSX = 21740; // 96 +static const uint64_t SH_FLD_VS_DU_LOG_REC_ERROR = 21741; // 24 +static const uint64_t SH_FLD_VS_ERR_HOLD_OUT = 21742; // 24 +static const uint64_t SH_FLD_VS_ERR_HOLD_OUT_LEN = 21743; // 24 +static const uint64_t SH_FLD_VS_LOG_REC_ERROR = 21744; // 24 +static const uint64_t SH_FLD_VS_LOG_XSTOP_ERROR = 21745; // 24 +static const uint64_t SH_FLD_VT0_INSTR_CMPLT = 21746; // 24 +static const uint64_t SH_FLD_VT0_INSTR_CMPLT_LEN = 21747; // 24 +static const uint64_t SH_FLD_VT0_INSTR_DISPATCH = 21748; // 24 +static const uint64_t SH_FLD_VT0_INSTR_DISPATCH_LEN = 21749; // 24 +static const uint64_t SH_FLD_VT0_LPCR_ONL_PAR_HOLD_OUT = 21750; // 24 +static const uint64_t SH_FLD_VT0_MEM_HIER_C = 21751; // 24 +static const uint64_t SH_FLD_VT0_MEM_HIER_C_LEN = 21752; // 24 +static const uint64_t SH_FLD_VT0_MSR_HV = 21753; // 24 +static const uint64_t SH_FLD_VT0_MSR_PR = 21754; // 24 +static const uint64_t SH_FLD_VT0_PSSCR_RL = 21755; // 24 +static const uint64_t SH_FLD_VT0_PSSCR_RL_LEN = 21756; // 24 +static const uint64_t SH_FLD_VT0_RUN_CYC_CNT = 21757; // 24 +static const uint64_t SH_FLD_VT0_RUN_CYC_CNT_LEN = 21758; // 24 +static const uint64_t SH_FLD_VT0_STOP_STATE = 21759; // 24 +static const uint64_t SH_FLD_VT1_INSTR_CMPLT = 21760; // 24 +static const uint64_t SH_FLD_VT1_INSTR_CMPLT_LEN = 21761; // 24 +static const uint64_t SH_FLD_VT1_INSTR_DISPATCH = 21762; // 24 +static const uint64_t SH_FLD_VT1_INSTR_DISPATCH_LEN = 21763; // 24 +static const uint64_t SH_FLD_VT1_LPCR_ONL_PAR_HOLD_OUT = 21764; // 24 +static const uint64_t SH_FLD_VT1_MEM_HIER_C = 21765; // 24 +static const uint64_t SH_FLD_VT1_MEM_HIER_C_LEN = 21766; // 24 +static const uint64_t SH_FLD_VT1_MSR_HV = 21767; // 24 +static const uint64_t SH_FLD_VT1_MSR_PR = 21768; // 24 +static const uint64_t SH_FLD_VT1_PSSCR_RL = 21769; // 24 +static const uint64_t SH_FLD_VT1_PSSCR_RL_LEN = 21770; // 24 +static const uint64_t SH_FLD_VT1_RUN_CYC_CNT = 21771; // 24 +static const uint64_t SH_FLD_VT1_RUN_CYC_CNT_LEN = 21772; // 24 +static const uint64_t SH_FLD_VT1_STOP_STATE = 21773; // 24 +static const uint64_t SH_FLD_VT2_INSTR_CMPLT = 21774; // 24 +static const uint64_t SH_FLD_VT2_INSTR_CMPLT_LEN = 21775; // 24 +static const uint64_t SH_FLD_VT2_INSTR_DISPATCH = 21776; // 24 +static const uint64_t SH_FLD_VT2_INSTR_DISPATCH_LEN = 21777; // 24 +static const uint64_t SH_FLD_VT2_LPCR_ONL_PAR_HOLD_OUT = 21778; // 24 +static const uint64_t SH_FLD_VT2_MEM_HIER_C = 21779; // 24 +static const uint64_t SH_FLD_VT2_MEM_HIER_C_LEN = 21780; // 24 +static const uint64_t SH_FLD_VT2_MSR_HV = 21781; // 24 +static const uint64_t SH_FLD_VT2_MSR_PR = 21782; // 24 +static const uint64_t SH_FLD_VT2_PSSCR_RL = 21783; // 24 +static const uint64_t SH_FLD_VT2_PSSCR_RL_LEN = 21784; // 24 +static const uint64_t SH_FLD_VT2_RUN_CYC_CNT = 21785; // 24 +static const uint64_t SH_FLD_VT2_RUN_CYC_CNT_LEN = 21786; // 24 +static const uint64_t SH_FLD_VT2_STOP_STATE = 21787; // 24 +static const uint64_t SH_FLD_VT3_INSTR_CMPLT = 21788; // 24 +static const uint64_t SH_FLD_VT3_INSTR_CMPLT_LEN = 21789; // 24 +static const uint64_t SH_FLD_VT3_INSTR_DISPATCH = 21790; // 24 +static const uint64_t SH_FLD_VT3_INSTR_DISPATCH_LEN = 21791; // 24 +static const uint64_t SH_FLD_VT3_LPCR_ONL_PAR_HOLD_OUT = 21792; // 24 +static const uint64_t SH_FLD_VT3_MEM_HIER_C = 21793; // 24 +static const uint64_t SH_FLD_VT3_MEM_HIER_C_LEN = 21794; // 24 +static const uint64_t SH_FLD_VT3_MSR_HV = 21795; // 24 +static const uint64_t SH_FLD_VT3_MSR_PR = 21796; // 24 +static const uint64_t SH_FLD_VT3_PSSCR_RL = 21797; // 24 +static const uint64_t SH_FLD_VT3_PSSCR_RL_LEN = 21798; // 24 +static const uint64_t SH_FLD_VT3_RUN_CYC_CNT = 21799; // 24 +static const uint64_t SH_FLD_VT3_RUN_CYC_CNT_LEN = 21800; // 24 +static const uint64_t SH_FLD_VT3_STOP_STATE = 21801; // 24 +static const uint64_t SH_FLD_VTARGET = 21802; // 4 +static const uint64_t SH_FLD_VTARGET_LEN = 21803; // 4 +static const uint64_t SH_FLD_VTB = 21804; // 96 +static const uint64_t SH_FLD_VTB_LEN = 21805; // 96 +static const uint64_t SH_FLD_VTID0_TO_PTID_MAP = 21806; // 24 +static const uint64_t SH_FLD_VTID0_TO_PTID_MAP_LEN = 21807; // 24 +static const uint64_t SH_FLD_VTID0_V = 21808; // 24 +static const uint64_t SH_FLD_VTID1_TO_PTID_MAP = 21809; // 24 +static const uint64_t SH_FLD_VTID1_TO_PTID_MAP_LEN = 21810; // 24 +static const uint64_t SH_FLD_VTID1_V = 21811; // 24 +static const uint64_t SH_FLD_VTID2_TO_PTID_MAP = 21812; // 24 +static const uint64_t SH_FLD_VTID2_TO_PTID_MAP_LEN = 21813; // 24 +static const uint64_t SH_FLD_VTID2_V = 21814; // 24 +static const uint64_t SH_FLD_VTID3_TO_PTID_MAP = 21815; // 24 +static const uint64_t SH_FLD_VTID3_TO_PTID_MAP_LEN = 21816; // 24 +static const uint64_t SH_FLD_VTID3_V = 21817; // 24 +static const uint64_t SH_FLD_V_TARG = 21818; // 1 +static const uint64_t SH_FLD_V_TARG_LEN = 21819; // 1 +static const uint64_t SH_FLD_W0_COUNT = 21820; // 12 +static const uint64_t SH_FLD_W0_COUNT_LEN = 21821; // 12 +static const uint64_t SH_FLD_W1_COUNT = 21822; // 12 +static const uint64_t SH_FLD_W1_COUNT_LEN = 21823; // 12 +static const uint64_t SH_FLD_WAITING = 21824; // 2 +static const uint64_t SH_FLD_WAIT_ALLWAYS = 21825; // 129 +static const uint64_t SH_FLD_WAIT_COUNT_EN = 21826; // 36 +static const uint64_t SH_FLD_WAIT_COUNT_PRELOAD1 = 21827; // 36 +static const uint64_t SH_FLD_WAIT_COUNT_PRELOAD2 = 21828; // 36 +static const uint64_t SH_FLD_WAIT_COUNT_PRELOAD3 = 21829; // 36 +static const uint64_t SH_FLD_WAIT_CYCLES = 21830; // 172 +static const uint64_t SH_FLD_WAIT_CYCLES_LEN = 21831; // 172 +static const uint64_t SH_FLD_WANT_CACHE_DISABLE = 21832; // 4 +static const uint64_t SH_FLD_WANT_INVALIDATE = 21833; // 3 +static const uint64_t SH_FLD_WARB_INVALID_CASE_ERROR = 21834; // 2 +static const uint64_t SH_FLD_WARM_START_COMPLETED = 21835; // 2 +static const uint64_t SH_FLD_WARM_START_SYNC_FR_LEFT = 21836; // 2 +static const uint64_t SH_FLD_WARM_START_SYNC_FR_RIGHT = 21837; // 2 +static const uint64_t SH_FLD_WAT0_EVENT_SELECT = 21838; // 8 +static const uint64_t SH_FLD_WAT0_EVENT_SELECT_LEN = 21839; // 8 +static const uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA = 21840; // 8 +static const uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA_LEN = 21841; // 8 +static const uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST = 21842; // 8 +static const uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST_LEN = 21843; // 8 +static const uint64_t SH_FLD_WAT1_EVENT_SELECT = 21844; // 8 +static const uint64_t SH_FLD_WAT1_EVENT_SELECT_LEN = 21845; // 8 +static const uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA = 21846; // 8 +static const uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA_LEN = 21847; // 8 +static const uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST = 21848; // 8 +static const uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST_LEN = 21849; // 8 +static const uint64_t SH_FLD_WATCHDOG = 21850; // 1 +static const uint64_t SH_FLD_WATCHDOG_ENABLE = 21851; // 43 +static const uint64_t SH_FLD_WATCHDOG_SEL = 21852; // 17 +static const uint64_t SH_FLD_WATCHDOG_SEL_LEN = 21853; // 17 +static const uint64_t SH_FLD_WATCHDOG_TIMEOUT = 21854; // 6 +static const uint64_t SH_FLD_WATERMARK_REG_0 = 21855; // 2 +static const uint64_t SH_FLD_WATERMARK_REG_0_LEN = 21856; // 2 +static const uint64_t SH_FLD_WATERMARK_REG_1 = 21857; // 1 +static const uint64_t SH_FLD_WATERMARK_REG_1_LEN = 21858; // 1 +static const uint64_t SH_FLD_WATERMARK_REG_2 = 21859; // 1 +static const uint64_t SH_FLD_WATERMARK_REG_2_LEN = 21860; // 1 +static const uint64_t SH_FLD_WATERMARK_REG_3 = 21861; // 1 +static const uint64_t SH_FLD_WATERMARK_REG_3_LEN = 21862; // 1 +static const uint64_t SH_FLD_WAT_ACTION_DIS_ALL_SPEC = 21863; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_ALL_SPEC_LEN = 21864; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_FASTPATH = 21865; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_FASTPATH_LEN = 21866; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_PREFETCH = 21867; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_PREFETCH_LEN = 21868; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_READ_BYP = 21869; // 4 +static const uint64_t SH_FLD_WAT_ACTION_DIS_READ_BYP_LEN = 21870; // 4 +static const uint64_t SH_FLD_WAT_ACTION_FORCE_MDI = 21871; // 4 +static const uint64_t SH_FLD_WAT_ACTION_FORCE_MDI_LEN = 21872; // 4 +static const uint64_t SH_FLD_WAT_ACTION_FORCE_SFSTAT = 21873; // 4 +static const uint64_t SH_FLD_WAT_ACTION_FORCE_SFSTAT_LEN = 21874; // 4 +static const uint64_t SH_FLD_WAT_ACTION_SEL = 21875; // 8 +static const uint64_t SH_FLD_WAT_ACTION_SEL_LEN = 21876; // 8 +static const uint64_t SH_FLD_WAT_CNTL_REG_SEL = 21877; // 4 +static const uint64_t SH_FLD_WAT_CNTL_REG_SEL_LEN = 21878; // 4 +static const uint64_t SH_FLD_WAT_DEBUG_ATTN = 21879; // 2 +static const uint64_t SH_FLD_WAT_DEBUG_REG_PE = 21880; // 2 +static const uint64_t SH_FLD_WAT_ERROR = 21881; // 16 +static const uint64_t SH_FLD_WAT_EVENT_ENABLE = 21882; // 8 +static const uint64_t SH_FLD_WAT_EVENT_ENABLE_MCA = 21883; // 8 +static const uint64_t SH_FLD_WAT_EVENT_ENABLE_NEST = 21884; // 8 +static const uint64_t SH_FLD_WAT_EVENT_SEL = 21885; // 4 +static const uint64_t SH_FLD_WAT_EVENT_SEL_LEN = 21886; // 4 +static const uint64_t SH_FLD_WAT_EXT_EVENT_TO_INT_SEL = 21887; // 4 +static const uint64_t SH_FLD_WAT_EXT_EVENT_TO_INT_SEL_LEN = 21888; // 4 +static const uint64_t SH_FLD_WAT_EXT_SEL = 21889; // 4 +static const uint64_t SH_FLD_WAT_EXT_SEL_LEN = 21890; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT0_SEL = 21891; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT0_SEL_LEN = 21892; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT1_SEL = 21893; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT1_SEL_LEN = 21894; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT2_SEL = 21895; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT2_SEL_LEN = 21896; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT3_SEL = 21897; // 4 +static const uint64_t SH_FLD_WAT_GLOB_EVENT3_SEL_LEN = 21898; // 4 +static const uint64_t SH_FLD_WAT_INJECT_INT = 21899; // 24 +static const uint64_t SH_FLD_WAT_INJECT_INT_RECOV = 21900; // 24 +static const uint64_t SH_FLD_WAT_LOCAL_EVENT_SEL = 21901; // 4 +static const uint64_t SH_FLD_WAT_LOCAL_EVENT_SEL_LEN = 21902; // 4 +static const uint64_t SH_FLD_WAT_SPARE1 = 21903; // 8 +static const uint64_t SH_FLD_WAT_SPARE1_LEN = 21904; // 8 +static const uint64_t SH_FLD_WAT_SPARE1_MCA = 21905; // 8 +static const uint64_t SH_FLD_WAT_SPARE1_MCA_LEN = 21906; // 8 +static const uint64_t SH_FLD_WAT_SPARE1_NEST = 21907; // 8 +static const uint64_t SH_FLD_WAT_SPARE1_NEST_LEN = 21908; // 8 +static const uint64_t SH_FLD_WAT_STALL_ACTION = 21909; // 8 +static const uint64_t SH_FLD_WAT_STALL_ACTION_LEN = 21910; // 8 +static const uint64_t SH_FLD_WBMGR_DBG_0_SELECT = 21911; // 8 +static const uint64_t SH_FLD_WBMGR_DBG_1_SELECT = 21912; // 8 +static const uint64_t SH_FLD_WBRD_DEBUG_0_SELECT = 21913; // 8 +static const uint64_t SH_FLD_WBRD_DEBUG_1_SELECT = 21914; // 8 +static const uint64_t SH_FLD_WBUF_SM_ERROR = 21915; // 2 +static const uint64_t SH_FLD_WC = 21916; // 8 +static const uint64_t SH_FLD_WC_BS_BAR = 21917; // 1 +static const uint64_t SH_FLD_WC_BS_BAR_LEN = 21918; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT10 = 21919; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT11 = 21920; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT12 = 21921; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT13 = 21922; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT14 = 21923; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT15 = 21924; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT16 = 21925; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT17 = 21926; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT18 = 21927; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT19 = 21928; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT20 = 21929; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT21 = 21930; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT22 = 21931; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT23 = 21932; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT4 = 21933; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT5 = 21934; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT6 = 21935; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT7 = 21936; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT8 = 21937; // 1 +static const uint64_t SH_FLD_WC_CERR_BIT9 = 21938; // 1 +static const uint64_t SH_FLD_WC_CERR_RESET = 21939; // 1 +static const uint64_t SH_FLD_WC_ECC_CE_ERROR = 21940; // 2 +static const uint64_t SH_FLD_WC_ECC_SUE_ERROR = 21941; // 2 +static const uint64_t SH_FLD_WC_ECC_UE_ERROR = 21942; // 2 +static const uint64_t SH_FLD_WC_LOGIC_HW_ERROR = 21943; // 2 +static const uint64_t SH_FLD_WC_MASK = 21944; // 8 +static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI = 21945; // 1 +static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN = 21946; // 1 +static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO = 21947; // 1 +static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN = 21948; // 1 +static const uint64_t SH_FLD_WC_TRACE_INT_DATA_HI = 21949; // 1 +static const uint64_t SH_FLD_WC_TRACE_INT_DATA_LO = 21950; // 1 +static const uint64_t SH_FLD_WC_TRACE_INT_TRIG_01 = 21951; // 1 +static const uint64_t SH_FLD_WC_TRACE_INT_TRIG_23 = 21952; // 1 +static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01 = 21953; // 1 +static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN = 21954; // 1 +static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23 = 21955; // 1 +static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN = 21956; // 1 +static const uint64_t SH_FLD_WDATA = 21957; // 4 +static const uint64_t SH_FLD_WDATA_LEN = 21958; // 4 +static const uint64_t SH_FLD_WDFCFG_PE = 21959; // 8 +static const uint64_t SH_FLD_WDF_ASYNC_ERROR = 21960; // 8 +static const uint64_t SH_FLD_WDF_ASYNC_INTERFACE_ERROR = 21961; // 8 +static const uint64_t SH_FLD_WDF_BUFFER_CE = 21962; // 8 +static const uint64_t SH_FLD_WDF_BUFFER_SUE = 21963; // 8 +static const uint64_t SH_FLD_WDF_BUFFER_UE = 21964; // 8 +static const uint64_t SH_FLD_WDF_ERR_INJECT0 = 21965; // 8 +static const uint64_t SH_FLD_WDF_ERR_INJECT0_LEN = 21966; // 8 +static const uint64_t SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR = 21967; // 8 +static const uint64_t SH_FLD_WDF_OVERRUN_ERROR_0 = 21968; // 8 +static const uint64_t SH_FLD_WDF_OVERRUN_ERROR_1 = 21969; // 8 +static const uint64_t SH_FLD_WDF_SCOM_SEQUENCE_ERROR = 21970; // 8 +static const uint64_t SH_FLD_WDF_STATE_MACHINE_ERROR = 21971; // 8 +static const uint64_t SH_FLD_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT = 21972; // 24 +static const uint64_t SH_FLD_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT = 21973; // 24 +static const uint64_t SH_FLD_WECR_PE = 21974; // 8 +static const uint64_t SH_FLD_WEIGHTADISPATCH = 21975; // 24 +static const uint64_t SH_FLD_WEIGHTADISPATCH_LEN = 21976; // 24 +static const uint64_t SH_FLD_WEIGHTANONDISPATCH = 21977; // 24 +static const uint64_t SH_FLD_WEIGHTANONDISPATCH_LEN = 21978; // 24 +static const uint64_t SH_FLD_WEIGHTBDISPATCH = 21979; // 24 +static const uint64_t SH_FLD_WEIGHTBDISPATCH_LEN = 21980; // 24 +static const uint64_t SH_FLD_WEIGHTBNONDISPATCH = 21981; // 24 +static const uint64_t SH_FLD_WEIGHTBNONDISPATCH_LEN = 21982; // 24 +static const uint64_t SH_FLD_WEIGHTCDISPATCH = 21983; // 24 +static const uint64_t SH_FLD_WEIGHTCDISPATCH_LEN = 21984; // 24 +static const uint64_t SH_FLD_WEIGHTCNONDISPATCH = 21985; // 24 +static const uint64_t SH_FLD_WEIGHTCNONDISPATCH_LEN = 21986; // 24 +static const uint64_t SH_FLD_WEIGHTDDISPATCH = 21987; // 24 +static const uint64_t SH_FLD_WEIGHTDDISPATCH_LEN = 21988; // 24 +static const uint64_t SH_FLD_WEIGHTDNONDISPATCH = 21989; // 24 +static const uint64_t SH_FLD_WEIGHTDNONDISPATCH_LEN = 21990; // 24 +static const uint64_t SH_FLD_WEIGHTEDISPATCH = 21991; // 24 +static const uint64_t SH_FLD_WEIGHTEDISPATCH_LEN = 21992; // 24 +static const uint64_t SH_FLD_WEIGHTENONDISPATCH = 21993; // 24 +static const uint64_t SH_FLD_WEIGHTENONDISPATCH_LEN = 21994; // 24 +static const uint64_t SH_FLD_WEIGHTFDISPATCH = 21995; // 24 +static const uint64_t SH_FLD_WEIGHTFDISPATCH_LEN = 21996; // 24 +static const uint64_t SH_FLD_WEIGHTFNONDISPATCH = 21997; // 24 +static const uint64_t SH_FLD_WEIGHTFNONDISPATCH_LEN = 21998; // 24 +static const uint64_t SH_FLD_WEN0 = 21999; // 2 +static const uint64_t SH_FLD_WEN1 = 22000; // 2 +static const uint64_t SH_FLD_WEN2 = 22001; // 2 +static const uint64_t SH_FLD_WHICH_8BECK = 22002; // 8 +static const uint64_t SH_FLD_WHICH_8BECK_LEN = 22003; // 8 +static const uint64_t SH_FLD_WILDCARD = 22004; // 6 +static const uint64_t SH_FLD_WINDOW_SELECT = 22005; // 3 +static const uint64_t SH_FLD_WINDOW_SELECT_LEN = 22006; // 3 +static const uint64_t SH_FLD_WIRETEST_DONE = 22007; // 4 +static const uint64_t SH_FLD_WIRETEST_FAILED = 22008; // 4 +static const uint64_t SH_FLD_WITH_ADDRESS_0 = 22009; // 2 +static const uint64_t SH_FLD_WITH_ADDRESS_1 = 22010; // 1 +static const uint64_t SH_FLD_WITH_ADDRESS_2 = 22011; // 1 +static const uint64_t SH_FLD_WITH_ADDRESS_3 = 22012; // 1 +static const uint64_t SH_FLD_WITH_START_0 = 22013; // 2 +static const uint64_t SH_FLD_WITH_START_1 = 22014; // 1 +static const uint64_t SH_FLD_WITH_START_2 = 22015; // 1 +static const uint64_t SH_FLD_WITH_START_3 = 22016; // 1 +static const uint64_t SH_FLD_WITH_STOP_0 = 22017; // 2 +static const uint64_t SH_FLD_WITH_STOP_1 = 22018; // 1 +static const uint64_t SH_FLD_WITH_STOP_2 = 22019; // 1 +static const uint64_t SH_FLD_WITH_STOP_3 = 22020; // 1 +static const uint64_t SH_FLD_WI_MACHINE_HANG = 22021; // 12 +static const uint64_t SH_FLD_WI_MACHINE_W4DT_HANG = 22022; // 12 +static const uint64_t SH_FLD_WI_UNSOLICITED_DATA = 22023; // 12 +static const uint64_t SH_FLD_WKUP_NOTIFY_SELECT = 22024; // 24 +static const uint64_t SH_FLD_WKUP_OVERRIDE_EN = 22025; // 30 +static const uint64_t SH_FLD_WL = 22026; // 8 +static const uint64_t SH_FLD_WL_ONE_DQS_PULSE = 22027; // 8 +static const uint64_t SH_FLD_WM_MULTIHIT_ERR = 22028; // 2 +static const uint64_t SH_FLD_WM_WIN_NOT_OPEN_ERR = 22029; // 2 +static const uint64_t SH_FLD_WOF = 22030; // 26 +static const uint64_t SH_FLD_WOF_COUNTER = 22031; // 1 +static const uint64_t SH_FLD_WOF_COUNTER_LEN = 22032; // 1 +static const uint64_t SH_FLD_WOF_IF_LOG_REC_ERROR = 22033; // 24 +static const uint64_t SH_FLD_WOF_IF_LOG_XSTOP_ERROR = 22034; // 24 +static const uint64_t SH_FLD_WOF_IF_RFILE_REC_ERROR = 22035; // 24 +static const uint64_t SH_FLD_WOF_IF_RFILE_XSTOP_ERROR = 22036; // 24 +static const uint64_t SH_FLD_WOF_IF_SRAM_REC_ERROR = 22037; // 24 +static const uint64_t SH_FLD_WOF_LEN = 22038; // 26 +static const uint64_t SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 22039; // 4 +static const uint64_t SH_FLD_WOF_LS_DERAT_MULTIHIT_ERROR = 22040; // 24 +static const uint64_t SH_FLD_WOF_LS_LOG_REC_ERROR = 22041; // 24 +static const uint64_t SH_FLD_WOF_LS_LOG_XSTOP_ERROR = 22042; // 24 +static const uint64_t SH_FLD_WOF_LS_NOT_MT_REC_ERROR = 22043; // 24 +static const uint64_t SH_FLD_WOF_LS_RFILE_REC_ERROR = 22044; // 24 +static const uint64_t SH_FLD_WOF_LS_RFILE_XSTOP_ERROR = 22045; // 24 +static const uint64_t SH_FLD_WOF_LS_SETDELETE_ERROR = 22046; // 24 +static const uint64_t SH_FLD_WOF_LS_SLB_MULTIHIT_ERROR = 22047; // 24 +static const uint64_t SH_FLD_WOF_LS_SRAM_PARITY_ERROR = 22048; // 24 +static const uint64_t SH_FLD_WOF_LS_SYS_XSTOP_ERROR = 22049; // 24 +static const uint64_t SH_FLD_WOF_LS_TLB_MULTIHIT_ERROR = 22050; // 24 +static const uint64_t SH_FLD_WOF_PC_CORE_HANG_DETECT_ERROR = 22051; // 24 +static const uint64_t SH_FLD_WOF_PC_FWD_PROGRESS_ERROR = 22052; // 24 +static const uint64_t SH_FLD_WOF_PC_FW_INJ_REC_ERROR = 22053; // 24 +static const uint64_t SH_FLD_WOF_PC_FW_INJ_XSTOP_ERROR = 22054; // 24 +static const uint64_t SH_FLD_WOF_PC_HANG_RECOVERY_FAILED = 22055; // 24 +static const uint64_t SH_FLD_WOF_PC_HYP_RES_ERROR = 22056; // 24 +static const uint64_t SH_FLD_WOF_PC_LOG_XSTOP_ERROR = 22057; // 24 +static const uint64_t SH_FLD_WOF_PC_NEST_HANG_DETECT_ERROR = 22058; // 24 +static const uint64_t SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR = 22059; // 24 +static const uint64_t SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR = 22060; // 24 +static const uint64_t SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR = 22061; // 24 +static const uint64_t SH_FLD_WOF_PC_PHYP_XSTOP_ERROR = 22062; // 24 +static const uint64_t SH_FLD_WOF_PC_RECOV_IN_MAINT_ERROR = 22063; // 24 +static const uint64_t SH_FLD_WOF_PC_RECOV_XSTOP_ERROR = 22064; // 24 +static const uint64_t SH_FLD_WOF_PC_SCOM_ERROR = 22065; // 24 +static const uint64_t SH_FLD_WOF_PC_SYS_XSTOP_ERROR = 22066; // 24 +static const uint64_t SH_FLD_WOF_PC_TFAC_XSTOP_ERROR = 22067; // 24 +static const uint64_t SH_FLD_WOF_PC_THREAD_HANG_REC_ERROR = 22068; // 24 +static const uint64_t SH_FLD_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 22069; // 24 +static const uint64_t SH_FLD_WOF_SD_CI_UE_ERROR = 22070; // 24 +static const uint64_t SH_FLD_WOF_SD_L2_UE_ERROR = 22071; // 24 +static const uint64_t SH_FLD_WOF_SD_L2_UE_OVER_THRES_ERROR = 22072; // 24 +static const uint64_t SH_FLD_WOF_SD_LOG_REC_ERROR = 22073; // 24 +static const uint64_t SH_FLD_WOF_SD_LOG_XSTOP_ERROR = 22074; // 24 +static const uint64_t SH_FLD_WOF_SD_MCHK_AND_ME_EQ_0_ERROR = 22075; // 24 +static const uint64_t SH_FLD_WOF_SD_NOT_MT_CI_REC_ERROR = 22076; // 24 +static const uint64_t SH_FLD_WOF_SD_RFILE_REC_ERROR = 22077; // 24 +static const uint64_t SH_FLD_WOF_SD_RFILE_XSTOP_ERROR = 22078; // 24 +static const uint64_t SH_FLD_WOF_SD_SYS_XSTOP_ERROR = 22079; // 24 +static const uint64_t SH_FLD_WOF_TC_FIR_XSTOP_ERROR = 22080; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_18 = 22081; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_19 = 22082; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_21 = 22083; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_22 = 22084; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_23 = 22085; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_40 = 22086; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_42 = 22087; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_44 = 22088; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_46 = 22089; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_49 = 22090; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_50 = 22091; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_51 = 22092; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_54 = 22093; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_6 = 22094; // 24 +static const uint64_t SH_FLD_WOF_UNUSED_7 = 22095; // 24 +static const uint64_t SH_FLD_WOF_VS_DU_LOG_REC_ERROR = 22096; // 24 +static const uint64_t SH_FLD_WOF_VS_LOG_REC_ERROR = 22097; // 24 +static const uint64_t SH_FLD_WOF_VS_LOG_XSTOP_ERROR = 22098; // 24 +static const uint64_t SH_FLD_WORD = 22099; // 8 +static const uint64_t SH_FLD_WORD_LEN = 22100; // 8 +static const uint64_t SH_FLD_WORK1 = 22101; // 3 +static const uint64_t SH_FLD_WORK1_LEN = 22102; // 3 +static const uint64_t SH_FLD_WORK2 = 22103; // 3 +static const uint64_t SH_FLD_WORK2_LEN = 22104; // 3 +static const uint64_t SH_FLD_WORT = 22105; // 96 +static const uint64_t SH_FLD_WORT_LEN = 22106; // 96 +static const uint64_t SH_FLD_WPLPEN = 22107; // 48 +static const uint64_t SH_FLD_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 22108; // 24 +static const uint64_t SH_FLD_WRAP_0 = 22109; // 2 +static const uint64_t SH_FLD_WRAP_1 = 22110; // 1 +static const uint64_t SH_FLD_WRAP_2 = 22111; // 1 +static const uint64_t SH_FLD_WRAP_3 = 22112; // 1 +static const uint64_t SH_FLD_WRCMP = 22113; // 2 +static const uint64_t SH_FLD_WRCMP_LEN = 22114; // 2 +static const uint64_t SH_FLD_WRCNTL_DBG_SELECT = 22115; // 8 +static const uint64_t SH_FLD_WRDM_DLY = 22116; // 8 +static const uint64_t SH_FLD_WRDM_DLY_LEN = 22117; // 8 +static const uint64_t SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 22118; // 2 +static const uint64_t SH_FLD_WRITE = 22119; // 9 +static const uint64_t SH_FLD_WRITE_CMD = 22120; // 1 +static const uint64_t SH_FLD_WRITE_COMPLETE = 22121; // 1 +static const uint64_t SH_FLD_WRITE_COUNT = 22122; // 8 +static const uint64_t SH_FLD_WRITE_COUNTER = 22123; // 1 +static const uint64_t SH_FLD_WRITE_COUNTER_LEN = 22124; // 1 +static const uint64_t SH_FLD_WRITE_COUNT_LEN = 22125; // 8 +static const uint64_t SH_FLD_WRITE_CPM_LT = 22126; // 43 +static const uint64_t SH_FLD_WRITE_CRD_POOL = 22127; // 1 +static const uint64_t SH_FLD_WRITE_CRD_POOL_LEN = 22128; // 1 +static const uint64_t SH_FLD_WRITE_CTR = 22129; // 8 +static const uint64_t SH_FLD_WRITE_ECC_DATAPATH_ERROR = 22130; // 8 +static const uint64_t SH_FLD_WRITE_ENABLE = 22131; // 129 +static const uint64_t SH_FLD_WRITE_ERR_INJECT0 = 22132; // 8 +static const uint64_t SH_FLD_WRITE_ERR_INJECT0_LEN = 22133; // 8 +static const uint64_t SH_FLD_WRITE_INVALID_FACES = 22134; // 1 +static const uint64_t SH_FLD_WRITE_INVALID_PIB = 22135; // 1 +static const uint64_t SH_FLD_WRITE_LATENCY_OFFSET = 22136; // 8 +static const uint64_t SH_FLD_WRITE_LATENCY_OFFSET_LEN = 22137; // 8 +static const uint64_t SH_FLD_WRITE_NOT_READ = 22138; // 3 +static const uint64_t SH_FLD_WRITE_NVLD = 22139; // 1 +static const uint64_t SH_FLD_WRITE_ON_RUN = 22140; // 162 +static const uint64_t SH_FLD_WRITE_ON_RUN_MODE = 22141; // 162 +static const uint64_t SH_FLD_WRITE_POOL = 22142; // 1 +static const uint64_t SH_FLD_WRITE_POOL_LEN = 22143; // 1 +static const uint64_t SH_FLD_WRITE_RMW_CE = 22144; // 8 +static const uint64_t SH_FLD_WRITE_RMW_SUE = 22145; // 8 +static const uint64_t SH_FLD_WRITE_RMW_UE = 22146; // 8 +static const uint64_t SH_FLD_WRITE_RST_INTERRUPT_FACES = 22147; // 1 +static const uint64_t SH_FLD_WRITE_RST_INTERRUPT_PIB = 22148; // 1 +static const uint64_t SH_FLD_WRITE_STATE_LT = 22149; // 43 +static const uint64_t SH_FLD_WRITE_STATE_LT_LEN = 22150; // 43 +static const uint64_t SH_FLD_WRITE_T0_PM_STATE = 22151; // 24 +static const uint64_t SH_FLD_WRITE_T1_PM_STATE = 22152; // 24 +static const uint64_t SH_FLD_WRITE_T2_PM_STATE = 22153; // 24 +static const uint64_t SH_FLD_WRITE_T3_PM_STATE = 22154; // 24 +static const uint64_t SH_FLD_WRITE_TSIZE = 22155; // 4 +static const uint64_t SH_FLD_WRITE_TSIZE_LEN = 22156; // 4 +static const uint64_t SH_FLD_WRITE_TTYPE = 22157; // 4 +static const uint64_t SH_FLD_WRITE_TTYPE_LEN = 22158; // 4 +static const uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR = 22159; // 1 +static const uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 22160; // 1 +static const uint64_t SH_FLD_WRMON_BAR0_BA = 22161; // 1 +static const uint64_t SH_FLD_WRMON_BAR0_BA_LEN = 22162; // 1 +static const uint64_t SH_FLD_WRMON_BAR0_SIZE = 22163; // 1 +static const uint64_t SH_FLD_WRMON_BAR0_SIZE_LEN = 22164; // 1 +static const uint64_t SH_FLD_WRMON_BAR1_BA = 22165; // 1 +static const uint64_t SH_FLD_WRMON_BAR1_BA_LEN = 22166; // 1 +static const uint64_t SH_FLD_WRMON_BAR1_SIZE = 22167; // 1 +static const uint64_t SH_FLD_WRMON_BAR1_SIZE_LEN = 22168; // 1 +static const uint64_t SH_FLD_WRMON_BAR2_BA = 22169; // 1 +static const uint64_t SH_FLD_WRMON_BAR2_BA_LEN = 22170; // 1 +static const uint64_t SH_FLD_WRMON_BAR2_SIZE = 22171; // 1 +static const uint64_t SH_FLD_WRMON_BAR2_SIZE_LEN = 22172; // 1 +static const uint64_t SH_FLD_WRMON_BAR3_BA = 22173; // 1 +static const uint64_t SH_FLD_WRMON_BAR3_BA_LEN = 22174; // 1 +static const uint64_t SH_FLD_WRMON_BAR3_SIZE = 22175; // 1 +static const uint64_t SH_FLD_WRMON_BAR3_SIZE_LEN = 22176; // 1 +static const uint64_t SH_FLD_WRMON_BAR4_BA = 22177; // 1 +static const uint64_t SH_FLD_WRMON_BAR4_BA_LEN = 22178; // 1 +static const uint64_t SH_FLD_WRMON_BAR4_SIZE = 22179; // 1 +static const uint64_t SH_FLD_WRMON_BAR4_SIZE_LEN = 22180; // 1 +static const uint64_t SH_FLD_WRMON_BAR5_BA = 22181; // 1 +static const uint64_t SH_FLD_WRMON_BAR5_BA_LEN = 22182; // 1 +static const uint64_t SH_FLD_WRMON_BAR5_SIZE = 22183; // 1 +static const uint64_t SH_FLD_WRMON_BAR5_SIZE_LEN = 22184; // 1 +static const uint64_t SH_FLD_WRMON_BAR6_BA = 22185; // 1 +static const uint64_t SH_FLD_WRMON_BAR6_BA_LEN = 22186; // 1 +static const uint64_t SH_FLD_WRMON_BAR6_SIZE = 22187; // 1 +static const uint64_t SH_FLD_WRMON_BAR6_SIZE_LEN = 22188; // 1 +static const uint64_t SH_FLD_WRMON_BAR7_BA = 22189; // 1 +static const uint64_t SH_FLD_WRMON_BAR7_BA_LEN = 22190; // 1 +static const uint64_t SH_FLD_WRMON_BAR7_SIZE = 22191; // 1 +static const uint64_t SH_FLD_WRMON_BAR7_SIZE_LEN = 22192; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_ENADTTYPE = 22193; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TSIZE = 22194; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK = 22195; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK_LEN = 22196; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TSIZE_LEN = 22197; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TTYPE = 22198; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS = 22199; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS_LEN = 22200; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK = 22201; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK_LEN = 22202; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_TTYPE_LEN = 22203; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_UNUSED = 22204; // 1 +static const uint64_t SH_FLD_WRMON_CMP0_VAL = 22205; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_ENADTTYPE = 22206; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TSIZE = 22207; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK = 22208; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK_LEN = 22209; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TSIZE_LEN = 22210; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TTYPE = 22211; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS = 22212; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS_LEN = 22213; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK = 22214; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK_LEN = 22215; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_TTYPE_LEN = 22216; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_UNUSED = 22217; // 1 +static const uint64_t SH_FLD_WRMON_CMP1_VAL = 22218; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_ENADTTYPE = 22219; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TSIZE = 22220; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK = 22221; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK_LEN = 22222; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TSIZE_LEN = 22223; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TTYPE = 22224; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS = 22225; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS_LEN = 22226; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK = 22227; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK_LEN = 22228; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_TTYPE_LEN = 22229; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_UNUSED = 22230; // 1 +static const uint64_t SH_FLD_WRMON_CMP2_VAL = 22231; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_ENADTTYPE = 22232; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TSIZE = 22233; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK = 22234; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK_LEN = 22235; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TSIZE_LEN = 22236; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TTYPE = 22237; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS = 22238; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS_LEN = 22239; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK = 22240; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK_LEN = 22241; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_TTYPE_LEN = 22242; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_UNUSED = 22243; // 1 +static const uint64_t SH_FLD_WRMON_CMP3_VAL = 22244; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_ENADTTYPE = 22245; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TSIZE = 22246; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK = 22247; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK_LEN = 22248; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TSIZE_LEN = 22249; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TTYPE = 22250; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS = 22251; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS_LEN = 22252; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK = 22253; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK_LEN = 22254; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_TTYPE_LEN = 22255; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_UNUSED = 22256; // 1 +static const uint64_t SH_FLD_WRMON_CMP4_VAL = 22257; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_ENADTTYPE = 22258; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TSIZE = 22259; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK = 22260; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK_LEN = 22261; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TSIZE_LEN = 22262; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TTYPE = 22263; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS = 22264; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS_LEN = 22265; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK = 22266; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK_LEN = 22267; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_TTYPE_LEN = 22268; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_UNUSED = 22269; // 1 +static const uint64_t SH_FLD_WRMON_CMP5_VAL = 22270; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_ENADTTYPE = 22271; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TSIZE = 22272; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK = 22273; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK_LEN = 22274; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TSIZE_LEN = 22275; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TTYPE = 22276; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS = 22277; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS_LEN = 22278; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK = 22279; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK_LEN = 22280; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_TTYPE_LEN = 22281; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_UNUSED = 22282; // 1 +static const uint64_t SH_FLD_WRMON_CMP6_VAL = 22283; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_ENADTTYPE = 22284; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TSIZE = 22285; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK = 22286; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK_LEN = 22287; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TSIZE_LEN = 22288; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TTYPE = 22289; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS = 22290; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS_LEN = 22291; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK = 22292; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK_LEN = 22293; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_TTYPE_LEN = 22294; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_UNUSED = 22295; // 1 +static const uint64_t SH_FLD_WRMON_CMP7_VAL = 22296; // 1 +static const uint64_t SH_FLD_WRMON_WID0 = 22297; // 1 +static const uint64_t SH_FLD_WRMON_WID0_LEN = 22298; // 1 +static const uint64_t SH_FLD_WRMON_WID1 = 22299; // 1 +static const uint64_t SH_FLD_WRMON_WID1_LEN = 22300; // 1 +static const uint64_t SH_FLD_WRMON_WID2 = 22301; // 1 +static const uint64_t SH_FLD_WRMON_WID2_LEN = 22302; // 1 +static const uint64_t SH_FLD_WRMON_WID3 = 22303; // 1 +static const uint64_t SH_FLD_WRMON_WID3_LEN = 22304; // 1 +static const uint64_t SH_FLD_WRMON_WID4 = 22305; // 1 +static const uint64_t SH_FLD_WRMON_WID4_LEN = 22306; // 1 +static const uint64_t SH_FLD_WRMON_WID5 = 22307; // 1 +static const uint64_t SH_FLD_WRMON_WID5_LEN = 22308; // 1 +static const uint64_t SH_FLD_WRMON_WID6 = 22309; // 1 +static const uint64_t SH_FLD_WRMON_WID6_LEN = 22310; // 1 +static const uint64_t SH_FLD_WRMON_WID7 = 22311; // 1 +static const uint64_t SH_FLD_WRMON_WID7_LEN = 22312; // 1 +static const uint64_t SH_FLD_WRPMD = 22313; // 48 +static const uint64_t SH_FLD_WRPSM = 22314; // 48 +static const uint64_t SH_FLD_WRQ0_EMPTY = 22315; // 4 +static const uint64_t SH_FLD_WRQ1_EMPTY = 22316; // 4 +static const uint64_t SH_FLD_WRQ_BAD_CRESP = 22317; // 1 +static const uint64_t SH_FLD_WRQ_CAPACITY_LIMIT = 22318; // 4 +static const uint64_t SH_FLD_WRQ_CAPACITY_LIMIT_LEN = 22319; // 4 +static const uint64_t SH_FLD_WRQ_FSM_PERR = 22320; // 1 +static const uint64_t SH_FLD_WRQ_HANG = 22321; // 8 +static const uint64_t SH_FLD_WRQ_OP_HANG = 22322; // 1 +static const uint64_t SH_FLD_WRQ_OVERFLOW = 22323; // 1 +static const uint64_t SH_FLD_WRQ_PE = 22324; // 8 +static const uint64_t SH_FLD_WRQ_RRQ_HANG_ERR = 22325; // 16 +static const uint64_t SH_FLD_WRSBG_DLY = 22326; // 8 +static const uint64_t SH_FLD_WRSBG_DLY_LEN = 22327; // 8 +static const uint64_t SH_FLD_WRSMDR_DLY = 22328; // 8 +static const uint64_t SH_FLD_WRSMDR_DLY_LEN = 22329; // 8 +static const uint64_t SH_FLD_WRSMSR_DLY = 22330; // 8 +static const uint64_t SH_FLD_WRSMSR_DLY_LEN = 22331; // 8 +static const uint64_t SH_FLD_WRTCFG_PE = 22332; // 8 +static const uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES = 22333; // 8 +static const uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES_LEN = 22334; // 8 +static const uint64_t SH_FLD_WRT_BUFFER_CE = 22335; // 8 +static const uint64_t SH_FLD_WRT_BUFFER_SUE = 22336; // 8 +static const uint64_t SH_FLD_WRT_BUFFER_UE = 22337; // 8 +static const uint64_t SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR = 22338; // 8 +static const uint64_t SH_FLD_WRT_RST_INTRPT_FACES = 22339; // 1 +static const uint64_t SH_FLD_WRT_RST_INTRPT_PIB = 22340; // 1 +static const uint64_t SH_FLD_WRT_SCOM_SEQUENCE_ERROR = 22341; // 8 +static const uint64_t SH_FLD_WR_BUFFER_STATUS = 22342; // 2 +static const uint64_t SH_FLD_WR_BUFFER_STATUS_LEN = 22343; // 2 +static const uint64_t SH_FLD_WR_BYTE_COUNT = 22344; // 2 +static const uint64_t SH_FLD_WR_BYTE_COUNT_LEN = 22345; // 2 +static const uint64_t SH_FLD_WR_CNTL = 22346; // 8 +static const uint64_t SH_FLD_WR_CNTL_MASK = 22347; // 8 +static const uint64_t SH_FLD_WR_DATA_PARITY_ERROR = 22348; // 3 +static const uint64_t SH_FLD_WR_ECC_CE = 22349; // 1 +static const uint64_t SH_FLD_WR_ECC_UE = 22350; // 1 +static const uint64_t SH_FLD_WR_EPSILON_VALUE = 22351; // 2 +static const uint64_t SH_FLD_WR_EPSILON_VALUE_LEN = 22352; // 2 +static const uint64_t SH_FLD_WR_FIFO_STAB = 22353; // 8 +static const uint64_t SH_FLD_WR_GATHER_TIMEOUT = 22354; // 4 +static const uint64_t SH_FLD_WR_GATHER_TIMEOUT_LEN = 22355; // 4 +static const uint64_t SH_FLD_WR_LEVEL = 22356; // 8 +static const uint64_t SH_FLD_WR_MON_NOT_DISABLED_ERR = 22357; // 2 +static const uint64_t SH_FLD_WR_PAR_ERR = 22358; // 8 +static const uint64_t SH_FLD_WR_PAR_ERR_MASK = 22359; // 8 +static const uint64_t SH_FLD_WR_PRE_DLY = 22360; // 8 +static const uint64_t SH_FLD_WR_PRE_DLY_LEN = 22361; // 8 +static const uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT = 22362; // 8 +static const uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 22363; // 8 +static const uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT = 22364; // 8 +static const uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT_LEN = 22365; // 8 +static const uint64_t SH_FLD_WR_SCOPE = 22366; // 24 +static const uint64_t SH_FLD_WR_SLVNUM = 22367; // 2 +static const uint64_t SH_FLD_WR_SLVNUM_LEN = 22368; // 2 +static const uint64_t SH_FLD_WR_SPLIT_UT0_ENA = 22369; // 6 +static const uint64_t SH_FLD_WR_SPLIT_UT1_ENA = 22370; // 6 +static const uint64_t SH_FLD_WR_TIER_1_CNT_VAL = 22371; // 1 +static const uint64_t SH_FLD_WR_TIER_1_CNT_VAL_LEN = 22372; // 1 +static const uint64_t SH_FLD_WR_TIER_1_DIV_VAL = 22373; // 1 +static const uint64_t SH_FLD_WR_TIER_1_DIV_VAL_LEN = 22374; // 1 +static const uint64_t SH_FLD_WR_TIER_2_CNT_VAL = 22375; // 1 +static const uint64_t SH_FLD_WR_TIER_2_CNT_VAL_LEN = 22376; // 1 +static const uint64_t SH_FLD_WR_TIER_2_DIV_VAL = 22377; // 1 +static const uint64_t SH_FLD_WR_TIER_2_DIV_VAL_LEN = 22378; // 1 +static const uint64_t SH_FLD_WR_VALID = 22379; // 1 +static const uint64_t SH_FLD_WSIZE = 22380; // 1 +static const uint64_t SH_FLD_WSIZE_LEN = 22381; // 1 +static const uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL = 22382; // 12 +static const uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL_LEN = 22383; // 12 +static const uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL = 22384; // 24 +static const uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL_LEN = 22385; // 24 +static const uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL = 22386; // 24 +static const uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL_LEN = 22387; // 24 +static const uint64_t SH_FLD_WTL_SM_STATUS = 22388; // 4 +static const uint64_t SH_FLD_WTL_SM_STATUS_LEN = 22389; // 4 +static const uint64_t SH_FLD_WTL_TEST_CLOCK = 22390; // 4 +static const uint64_t SH_FLD_WTL_TEST_DATA = 22391; // 4 +static const uint64_t SH_FLD_WTR_MAX_BAD_LANES = 22392; // 4 +static const uint64_t SH_FLD_WTR_MAX_BAD_LANES_LEN = 22393; // 4 +static const uint64_t SH_FLD_WT_ALL_DONE_GCRMSG = 22394; // 4 +static const uint64_t SH_FLD_WT_BS_CLOCK_EN_BYP = 22395; // 4 +static const uint64_t SH_FLD_WT_BS_DATA_EN_BYP = 22396; // 4 +static const uint64_t SH_FLD_WT_CHECK_COUNT = 22397; // 4 +static const uint64_t SH_FLD_WT_CHECK_COUNT_LEN = 22398; // 4 +static const uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE = 22399; // 4 +static const uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE_LEN = 22400; // 4 +static const uint64_t SH_FLD_WT_CLK_LANE_INVERTED = 22401; // 4 +static const uint64_t SH_FLD_WT_CU_BYP_PLL_LOCK = 22402; // 4 +static const uint64_t SH_FLD_WT_CU_PLL_PGOOD = 22403; // 4 +static const uint64_t SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG = 22404; // 4 +static const uint64_t SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG = 22405; // 4 +static const uint64_t SH_FLD_WT_LANE_BAD_CODE = 22406; // 96 +static const uint64_t SH_FLD_WT_LANE_BAD_CODE_LEN = 22407; // 96 +static const uint64_t SH_FLD_WT_LANE_DISABLED = 22408; // 96 +static const uint64_t SH_FLD_WT_PATTERN_LENGTH = 22409; // 8 +static const uint64_t SH_FLD_WT_PATTERN_LENGTH_LEN = 22410; // 8 +static const uint64_t SH_FLD_WT_PLL_REFCLKSEL = 22411; // 4 +static const uint64_t SH_FLD_WT_PREV_DONE_GCRMSG = 22412; // 4 +static const uint64_t SH_FLD_WT_TIMEOUT_SEL = 22413; // 4 +static const uint64_t SH_FLD_WT_TIMEOUT_SEL_LEN = 22414; // 4 +static const uint64_t SH_FLD_WWDM_DLY = 22415; // 8 +static const uint64_t SH_FLD_WWDM_DLY_LEN = 22416; // 8 +static const uint64_t SH_FLD_WWOP_DLY = 22417; // 8 +static const uint64_t SH_FLD_WWOP_DLY_LEN = 22418; // 8 +static const uint64_t SH_FLD_WWSMDR_DLY = 22419; // 8 +static const uint64_t SH_FLD_WWSMDR_DLY_LEN = 22420; // 8 +static const uint64_t SH_FLD_WWSMSR_DLY = 22421; // 8 +static const uint64_t SH_FLD_WWSMSR_DLY_LEN = 22422; // 8 +static const uint64_t SH_FLD_X0_ACT = 22423; // 1 +static const uint64_t SH_FLD_X0_HI = 22424; // 1 +static const uint64_t SH_FLD_X0_HI_LEN = 22425; // 1 +static const uint64_t SH_FLD_X0_LO = 22426; // 1 +static const uint64_t SH_FLD_X0_LO_LEN = 22427; // 1 +static const uint64_t SH_FLD_X0_TX_ENABLE = 22428; // 4 +static const uint64_t SH_FLD_X0_TX_SELECT = 22429; // 4 +static const uint64_t SH_FLD_X0_TX_SELECT_LEN = 22430; // 4 +static const uint64_t SH_FLD_X1_ACT = 22431; // 1 +static const uint64_t SH_FLD_X1_HI = 22432; // 1 +static const uint64_t SH_FLD_X1_HI_LEN = 22433; // 1 +static const uint64_t SH_FLD_X1_LO = 22434; // 1 +static const uint64_t SH_FLD_X1_LO_LEN = 22435; // 1 +static const uint64_t SH_FLD_X1_TX_ENABLE = 22436; // 4 +static const uint64_t SH_FLD_X1_TX_SELECT = 22437; // 4 +static const uint64_t SH_FLD_X1_TX_SELECT_LEN = 22438; // 4 +static const uint64_t SH_FLD_X2_ACT = 22439; // 1 +static const uint64_t SH_FLD_X2_HI = 22440; // 1 +static const uint64_t SH_FLD_X2_HI_LEN = 22441; // 1 +static const uint64_t SH_FLD_X2_LO = 22442; // 1 +static const uint64_t SH_FLD_X2_LO_LEN = 22443; // 1 +static const uint64_t SH_FLD_X2_TX_ENABLE = 22444; // 4 +static const uint64_t SH_FLD_X2_TX_SELECT = 22445; // 4 +static const uint64_t SH_FLD_X2_TX_SELECT_LEN = 22446; // 4 +static const uint64_t SH_FLD_X3_TX_ENABLE = 22447; // 4 +static const uint64_t SH_FLD_X3_TX_SELECT = 22448; // 4 +static const uint64_t SH_FLD_X3_TX_SELECT_LEN = 22449; // 4 +static const uint64_t SH_FLD_X4_TX_ENABLE = 22450; // 4 +static const uint64_t SH_FLD_X4_TX_SELECT = 22451; // 4 +static const uint64_t SH_FLD_X4_TX_SELECT_LEN = 22452; // 4 +static const uint64_t SH_FLD_X5_TX_ENABLE = 22453; // 4 +static const uint64_t SH_FLD_X5_TX_SELECT = 22454; // 4 +static const uint64_t SH_FLD_X5_TX_SELECT_LEN = 22455; // 4 +static const uint64_t SH_FLD_X6_TX_ENABLE = 22456; // 4 +static const uint64_t SH_FLD_X6_TX_SELECT = 22457; // 4 +static const uint64_t SH_FLD_X6_TX_SELECT_LEN = 22458; // 4 +static const uint64_t SH_FLD_X7_TX_ENABLE = 22459; // 4 +static const uint64_t SH_FLD_X7_TX_SELECT = 22460; // 4 +static const uint64_t SH_FLD_X7_TX_SELECT_LEN = 22461; // 4 +static const uint64_t SH_FLD_XARS = 22462; // 3 +static const uint64_t SH_FLD_XARSP = 22463; // 12 +static const uint64_t SH_FLD_XATS = 22464; // 12 +static const uint64_t SH_FLD_XCR = 22465; // 21 +static const uint64_t SH_FLD_XCR_LEN = 22466; // 21 +static const uint64_t SH_FLD_XIMEM_MEM_IFETCH_PENDING = 22467; // 21 +static const uint64_t SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 22468; // 21 +static const uint64_t SH_FLD_XIRAMGA_IR = 22469; // 21 +static const uint64_t SH_FLD_XIRAMGA_IR_LEN = 22470; // 21 +static const uint64_t SH_FLD_XIRAMRA_SPRG0 = 22471; // 42 +static const uint64_t SH_FLD_XIRAMRA_SPRG0_LEN = 22472; // 42 +static const uint64_t SH_FLD_XISIB_PIB_IFETCH_PENDING = 22473; // 1 +static const uint64_t SH_FLD_XIXCR_XCR = 22474; // 21 +static const uint64_t SH_FLD_XIXCR_XCR_LEN = 22475; // 21 +static const uint64_t SH_FLD_XLAT = 22476; // 16 +static const uint64_t SH_FLD_XLATE_TO_ADDR_ID_ENABLE = 22477; // 2 +static const uint64_t SH_FLD_XLAT_LEN = 22478; // 16 +static const uint64_t SH_FLD_XPT_ERROR_INJECT_ENABLE = 22479; // 2 +static const uint64_t SH_FLD_XPT_ERROR_INJECT_TARGET = 22480; // 2 +static const uint64_t SH_FLD_XPT_ERROR_INJECT_TARGET_LEN = 22481; // 2 +static const uint64_t SH_FLD_XPT_ERROR_TYPE = 22482; // 2 +static const uint64_t SH_FLD_XPT_ERROR_TYPE_LEN = 22483; // 2 +static const uint64_t SH_FLD_XPT_INJECT_CONTINUOUS_ERROR = 22484; // 2 +static const uint64_t SH_FLD_XPT_MUX_PORT_SEL = 22485; // 2 +static const uint64_t SH_FLD_XPT_MUX_PORT_SEL_LEN = 22486; // 2 +static const uint64_t SH_FLD_XPT_POWERBUS_CE = 22487; // 4 +static const uint64_t SH_FLD_XPT_POWERBUS_SUE = 22488; // 4 +static const uint64_t SH_FLD_XPT_POWERBUS_UE = 22489; // 4 +static const uint64_t SH_FLD_XPT_RECOVERABLE_ERROR = 22490; // 4 +static const uint64_t SH_FLD_XPT_SYS_XSTOP_ERROR = 22491; // 4 +static const uint64_t SH_FLD_XPT_TRIGGER_SEL = 22492; // 2 +static const uint64_t SH_FLD_XSCOM_DONE = 22493; // 96 +static const uint64_t SH_FLD_XSCOM_FAIL = 22494; // 96 +static const uint64_t SH_FLD_XSCOM_STATUS = 22495; // 96 +static const uint64_t SH_FLD_XSCOM_STATUS_LEN = 22496; // 96 +static const uint64_t SH_FLD_XSC_CMD_OVERRUN = 22497; // 1 +static const uint64_t SH_FLD_XSR_DACR = 22498; // 46 +static const uint64_t SH_FLD_XSR_DACW = 22499; // 46 +static const uint64_t SH_FLD_XSR_EP = 22500; // 46 +static const uint64_t SH_FLD_XSR_HC = 22501; // 46 +static const uint64_t SH_FLD_XSR_HCP = 22502; // 46 +static const uint64_t SH_FLD_XSR_HC_LEN = 22503; // 46 +static const uint64_t SH_FLD_XSR_HS = 22504; // 46 +static const uint64_t SH_FLD_XSR_IAC = 22505; // 46 +static const uint64_t SH_FLD_XSR_MCS = 22506; // 46 +static const uint64_t SH_FLD_XSR_MCS_LEN = 22507; // 46 +static const uint64_t SH_FLD_XSR_MFE = 22508; // 46 +static const uint64_t SH_FLD_XSR_PTR = 22509; // 46 +static const uint64_t SH_FLD_XSR_RIP = 22510; // 46 +static const uint64_t SH_FLD_XSR_SIP = 22511; // 46 +static const uint64_t SH_FLD_XSR_SMS = 22512; // 46 +static const uint64_t SH_FLD_XSR_SMS_LEN = 22513; // 46 +static const uint64_t SH_FLD_XSR_ST = 22514; // 46 +static const uint64_t SH_FLD_XSR_TRAP = 22515; // 46 +static const uint64_t SH_FLD_XSR_TRH = 22516; // 46 +static const uint64_t SH_FLD_XSTOP = 22517; // 91 +static const uint64_t SH_FLD_XSTOP_GATE = 22518; // 1 +static const uint64_t SH_FLD_XTS_CONFIG_P = 22519; // 1 +static const uint64_t SH_FLD_XTS_INT = 22520; // 1 +static const uint64_t SH_FLD_XTS_PBUS_PROTOCOL = 22521; // 1 +static const uint64_t SH_FLD_XTS_PROTOCOL_CE = 22522; // 1 +static const uint64_t SH_FLD_XTS_PROTOCOL_UE = 22523; // 1 +static const uint64_t SH_FLD_XTS_RSVD_10 = 22524; // 1 +static const uint64_t SH_FLD_XTS_RSVD_11 = 22525; // 1 +static const uint64_t SH_FLD_XTS_RSVD_12 = 22526; // 1 +static const uint64_t SH_FLD_XTS_RSVD_13 = 22527; // 1 +static const uint64_t SH_FLD_XTS_RSVD_14 = 22528; // 1 +static const uint64_t SH_FLD_XTS_RSVD_15 = 22529; // 1 +static const uint64_t SH_FLD_XTS_RSVD_16 = 22530; // 1 +static const uint64_t SH_FLD_XTS_RSVD_17 = 22531; // 1 +static const uint64_t SH_FLD_XTS_RSVD_18 = 22532; // 1 +static const uint64_t SH_FLD_XTS_RSVD_19 = 22533; // 1 +static const uint64_t SH_FLD_XTS_RSVD_6 = 22534; // 1 +static const uint64_t SH_FLD_XTS_RSVD_7 = 22535; // 1 +static const uint64_t SH_FLD_XTS_RSVD_8 = 22536; // 1 +static const uint64_t SH_FLD_XTS_RSVD_9 = 22537; // 1 +static const uint64_t SH_FLD_XTS_SRAM_CE = 22538; // 1 +static const uint64_t SH_FLD_XTS_SRAM_UE = 22539; // 1 +static const uint64_t SH_FLD_Z = 22540; // 1 +static const uint64_t SH_FLD_ZCAL = 22541; // 12 +static const uint64_t SH_FLD_ZCAL_CYA_DATA_INV = 22542; // 4 +static const uint64_t SH_FLD_ZCAL_LEN = 22543; // 4 +static const uint64_t SH_FLD_ZCAL_N = 22544; // 4 +static const uint64_t SH_FLD_ZCAL_N_LEN = 22545; // 4 +static const uint64_t SH_FLD_ZCAL_P = 22546; // 4 +static const uint64_t SH_FLD_ZCAL_P_LEN = 22547; // 4 +static const uint64_t SH_FLD_ZCAL_RANGE_CHECK = 22548; // 4 +static const uint64_t SH_FLD_ZCAL_SM_MAX_VAL = 22549; // 4 +static const uint64_t SH_FLD_ZCAL_SM_MAX_VAL_LEN = 22550; // 4 +static const uint64_t SH_FLD_ZCAL_SM_MIN_VAL = 22551; // 4 +static const uint64_t SH_FLD_ZCAL_SM_MIN_VAL_LEN = 22552; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_CAL_SEGS = 22553; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_CMP_INV = 22554; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_CMP_OFFSET = 22555; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_CMP_RESET = 22556; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_EN = 22557; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_POWERDOWN = 22558; // 4 +static const uint64_t SH_FLD_ZCAL_SWO_TCOIL = 22559; // 4 +static const uint64_t SH_FLD_ZCAL_TEST_CLK_DIV = 22560; // 4 +static const uint64_t SH_FLD_ZCAL_TEST_OVR_1R = 22561; // 4 +static const uint64_t SH_FLD_ZCAL_TEST_OVR_2R = 22562; // 4 +static const uint64_t SH_FLD_ZCAL_TEST_OVR_4X_SEG = 22563; // 4 #endif diff --git a/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H b/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H index ec9bf941..9bdaba15 100644 --- a/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H +++ b/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H @@ -239,17 +239,17 @@ #include <p9_xbus_scom_addresses_fixes.H> -REG64( XBUS_IOPPE_CSAR , RULL(0x06010858), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_CSAR , RULL(0x0601084D), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW ); -REG64( XBUS_IOPPE_CSCR , RULL(0x06010855), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_CSCR , RULL(0x0601084A), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW ); -REG64( XBUS_IOPPE_CSCR_CLEAR , RULL(0x06010801), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_CSCR_CLEAR , RULL(0x0601084B), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM1_CLEAR ); -REG64( XBUS_IOPPE_CSCR_OR , RULL(0x06010802), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_CSCR_OR , RULL(0x0601084C), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ); -REG64( XBUS_IOPPE_CSDR , RULL(0x06010859), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_CSDR , RULL(0x0601084E), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW ); REG64( XBUS_PERV_DBG_INST1_COND_REG_1 , RULL(0x060107C1), SH_UNT_XBUS_PERV, SH_ACS_SCOM ); @@ -274,6 +274,41 @@ REG64( XBUS_PERV_DBG_TRACE_REG_1 , RULL(0x060107CE REG64( XBUS_PERV_DEBUG_TRACE_CONTROL , RULL(0x060107D0), SH_UNT_XBUS_PERV, SH_ACS_SCOM ); +REG64( XBUS_FIR_ACTION0_REG , RULL(0x06010C06), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_1_FIR_ACTION0_REG , RULL(0x06011006), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); +REG64( XBUS_2_FIR_ACTION0_REG , RULL(0x06011406), SH_UNT_XBUS_2 , SH_ACS_SCOM_RW ); + +REG64( XBUS_FIR_ACTION1_REG , RULL(0x06010C07), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_1_FIR_ACTION1_REG , RULL(0x06011007), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); +REG64( XBUS_2_FIR_ACTION1_REG , RULL(0x06011407), SH_UNT_XBUS_2 , SH_ACS_SCOM_RW ); + +REG64( XBUS_FIR_MASK_REG , RULL(0x06010C03), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_1_FIR_MASK_REG , RULL(0x06011003), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); +REG64( XBUS_FIR_MASK_REG_AND , RULL(0x06010C04), SH_UNT_XBUS , SH_ACS_SCOM1_AND ); +REG64( XBUS_1_FIR_MASK_REG_AND , RULL(0x06011004), SH_UNT_XBUS_1 , SH_ACS_SCOM1_AND ); +REG64( XBUS_FIR_MASK_REG_OR , RULL(0x06010C05), SH_UNT_XBUS , SH_ACS_SCOM2_OR ); +REG64( XBUS_1_FIR_MASK_REG_OR , RULL(0x06011005), SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR ); +REG64( XBUS_2_FIR_MASK_REG , RULL(0x06011403), SH_UNT_XBUS_2 , SH_ACS_SCOM_RW ); +REG64( XBUS_2_FIR_MASK_REG_AND , RULL(0x06011404), SH_UNT_XBUS_2 , SH_ACS_SCOM1_AND ); +REG64( XBUS_2_FIR_MASK_REG_OR , RULL(0x06011405), SH_UNT_XBUS_2 , SH_ACS_SCOM2_OR ); + +REG64( XBUS_FIR_REG , RULL(0x06010C00), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_1_FIR_REG , RULL(0x06011000), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); +REG64( XBUS_FIR_REG_AND , RULL(0x06010C01), SH_UNT_XBUS , SH_ACS_SCOM1_AND ); +REG64( XBUS_1_FIR_REG_AND , RULL(0x06011001), SH_UNT_XBUS_1 , SH_ACS_SCOM1_AND ); +REG64( XBUS_FIR_REG_OR , RULL(0x06010C02), SH_UNT_XBUS , SH_ACS_SCOM2_OR ); +REG64( XBUS_1_FIR_REG_OR , RULL(0x06011002), SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR ); +REG64( XBUS_2_FIR_REG , RULL(0x06011400), SH_UNT_XBUS_2 , SH_ACS_SCOM_RW ); +REG64( XBUS_2_FIR_REG_AND , RULL(0x06011401), SH_UNT_XBUS_2 , SH_ACS_SCOM1_AND ); +REG64( XBUS_2_FIR_REG_OR , RULL(0x06011402), SH_UNT_XBUS_2 , SH_ACS_SCOM2_OR ); + +REG64( XBUS_FIR_WOF_REG , RULL(0x06010C08), SH_UNT_XBUS , + SH_ACS_SCOM_WCLRREG ); +REG64( XBUS_1_FIR_WOF_REG , RULL(0x06011008), SH_UNT_XBUS_1 , + SH_ACS_SCOM_WCLRREG ); +REG64( XBUS_2_FIR_WOF_REG , RULL(0x06011408), SH_UNT_XBUS_2 , + SH_ACS_SCOM_WCLRREG ); + REG64( XBUS_LL0_IOEL_CONFIG , RULL(0x0601180A), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_0_LL0_IOEL_CONFIG , RULL(0x0601180A), SH_UNT_XBUS_0 , SH_ACS_SCOM ); @@ -292,6 +327,11 @@ REG64( XBUS_0_LL0_IOEL_FIR_ACTION0_REG , RULL(0x06011806 REG64( XBUS_LL0_IOEL_FIR_ACTION1_REG , RULL(0x06011807), SH_UNT_XBUS , SH_ACS_SCOM_RW ); REG64( XBUS_0_LL0_IOEL_FIR_ACTION1_REG , RULL(0x06011807), SH_UNT_XBUS_0 , SH_ACS_SCOM_RW ); +REG64( XBUS_LL0_IOEL_FIR_WOF_REG , RULL(0x06011808), SH_UNT_XBUS , + SH_ACS_SCOM_WCLRREG ); +REG64( XBUS_0_LL0_IOEL_FIR_WOF_REG , RULL(0x06011808), SH_UNT_XBUS_0 , + SH_ACS_SCOM_WCLRREG ); + REG64( XBUS_LL0_IOEL_LAT_MEASURE , RULL(0x0601180E), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_0_LL0_IOEL_LAT_MEASURE , RULL(0x0601180E), SH_UNT_XBUS_0 , SH_ACS_SCOM ); @@ -382,12 +422,19 @@ REG64( XBUS_1_LL1_IOEL_DLL_STATUS , RULL(0x06011C28 REG64( XBUS_LL1_IOEL_ERR_INJ_LFSR , RULL(0x06010C1B), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_LL1_IOEL_ERR_INJ_LFSR , RULL(0x06011C1B), SH_UNT_XBUS_1 , SH_ACS_SCOM ); -REG64( XBUS_LL1_IOEL_FIR_ACTION0_REG , RULL(0x06010C06), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_LL1_IOEL_FIR_ACTION0_REG , RULL(0x06010C06), SH_UNT_XBUS , + SH_ACS_SCOM_RW ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_IOEL_FIR_ACTION0_REG , RULL(0x06011C06), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); -REG64( XBUS_LL1_IOEL_FIR_ACTION1_REG , RULL(0x06010C07), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_LL1_IOEL_FIR_ACTION1_REG , RULL(0x06010C07), SH_UNT_XBUS , + SH_ACS_SCOM_RW ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_IOEL_FIR_ACTION1_REG , RULL(0x06011C07), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); +REG64( XBUS_LL1_IOEL_FIR_WOF_REG , RULL(0x06010C08), SH_UNT_XBUS , + SH_ACS_SCOM_WCLRREG ); //WARNING - VALUE SET SAME AS ANOTHER REG +REG64( XBUS_1_LL1_IOEL_FIR_WOF_REG , RULL(0x06011C08), SH_UNT_XBUS_1 , + SH_ACS_SCOM_WCLRREG ); + REG64( XBUS_LL1_IOEL_LAT_MEASURE , RULL(0x06010C0E), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_LL1_IOEL_LAT_MEASURE , RULL(0x06011C0E), SH_UNT_XBUS_1 , SH_ACS_SCOM ); @@ -452,18 +499,24 @@ REG64( XBUS_1_LL1_IOEL_SEC_CONFIG , RULL(0x06011C0D REG64( XBUS_LL1_IOEL_SL_ECC_THRESHOLD , RULL(0x06010C19), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD , RULL(0x06011C19), SH_UNT_XBUS_1 , SH_ACS_SCOM ); -REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG , RULL(0x06010C03), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG , RULL(0x06010C03), SH_UNT_XBUS , + SH_ACS_SCOM_RW ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG , RULL(0x06011C03), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); -REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG_AND , RULL(0x06010C04), SH_UNT_XBUS , SH_ACS_SCOM1_AND ); +REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG_AND , RULL(0x06010C04), SH_UNT_XBUS , + SH_ACS_SCOM1_AND ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_AND , RULL(0x06011C04), SH_UNT_XBUS_1 , SH_ACS_SCOM1_AND ); -REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG_OR , RULL(0x06010C05), SH_UNT_XBUS , SH_ACS_SCOM2_OR ); +REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG_OR , RULL(0x06010C05), SH_UNT_XBUS , + SH_ACS_SCOM2_OR ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_OR , RULL(0x06011C05), SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR ); -REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG , RULL(0x06010C00), SH_UNT_XBUS , SH_ACS_SCOM_RW ); +REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG , RULL(0x06010C00), SH_UNT_XBUS , + SH_ACS_SCOM_RW ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG , RULL(0x06011C00), SH_UNT_XBUS_1 , SH_ACS_SCOM_RW ); -REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG_AND , RULL(0x06010C01), SH_UNT_XBUS , SH_ACS_SCOM1_AND ); +REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG_AND , RULL(0x06010C01), SH_UNT_XBUS , + SH_ACS_SCOM1_AND ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_AND , RULL(0x06011C01), SH_UNT_XBUS_1 , SH_ACS_SCOM1_AND ); -REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG_OR , RULL(0x06010C02), SH_UNT_XBUS , SH_ACS_SCOM2_OR ); +REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG_OR , RULL(0x06010C02), SH_UNT_XBUS , + SH_ACS_SCOM2_OR ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_OR , RULL(0x06011C02), SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR ); REG64( XBUS_2_LL2_IOEL_CONFIG , RULL(0x0601200A), SH_UNT_XBUS_2 , SH_ACS_SCOM ); @@ -478,6 +531,9 @@ REG64( XBUS_2_LL2_IOEL_FIR_ACTION0_REG , RULL(0x06012006 REG64( XBUS_2_LL2_IOEL_FIR_ACTION1_REG , RULL(0x06012007), SH_UNT_XBUS_2 , SH_ACS_SCOM_RW ); +REG64( XBUS_2_LL2_IOEL_FIR_WOF_REG , RULL(0x06012008), SH_UNT_XBUS_2 , + SH_ACS_SCOM_WCLRREG ); + REG64( XBUS_2_LL2_IOEL_LAT_MEASURE , RULL(0x0601200E), SH_UNT_XBUS_2 , SH_ACS_SCOM ); REG64( XBUS_2_LL2_IOEL_LINK0_EDPL_STATUS , RULL(0x06012024), SH_UNT_XBUS_2 , SH_ACS_SCOM_RO ); @@ -528,31 +584,54 @@ REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_REG , RULL(0x06012000 REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_REG_AND , RULL(0x06012001), SH_UNT_XBUS_2 , SH_ACS_SCOM1_AND ); REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_REG_OR , RULL(0x06012002), SH_UNT_XBUS_2 , SH_ACS_SCOM2_OR ); -REG64( XBUS_IOPPE_MIB_XIICAC , RULL(0x06010853), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_MIB_XIICAC , RULL(0x06010859), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO ); -REG64( XBUS_IOPPE_MIB_XIMEM , RULL(0x06010851), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_MIB_XIMEM , RULL(0x06010857), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO ); -REG64( XBUS_IOPPE_MIB_XISGB , RULL(0x06010852), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_MIB_XISGB , RULL(0x06010858), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO ); -REG64( XBUS_IOPPE_PPE_XIDBGPRO , RULL(0x0601084F), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_PPE_FIR_ACTION0_REG , RULL(0x06010846), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM_RW ); + +REG64( XBUS_IOPPE_PPE_FIR_ACTION1_REG , RULL(0x06010847), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM_RW ); + +REG64( XBUS_IOPPE_PPE_FIR_MASK_REG , RULL(0x06010843), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM_RW ); +REG64( XBUS_IOPPE_PPE_FIR_MASK_REG_AND , RULL(0x06010844), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM1_AND ); +REG64( XBUS_IOPPE_PPE_FIR_MASK_REG_OR , RULL(0x06010845), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM2_OR ); + +REG64( XBUS_IOPPE_PPE_FIR_REG , RULL(0x06010840), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM_RW ); +REG64( XBUS_IOPPE_PPE_FIR_REG_AND , RULL(0x06010841), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM1_AND ); +REG64( XBUS_IOPPE_PPE_FIR_REG_OR , RULL(0x06010842), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM2_OR ); + +REG64( XBUS_IOPPE_PPE_FIR_WOF_REG , RULL(0x06010848), SH_UNT_XBUS_IOPPE, + SH_ACS_SCOM_WCLRREG ); + +REG64( XBUS_IOPPE_PPE_XIDBGPRO , RULL(0x06010855), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM ); -REG64( XBUS_IOPPE_PPE_XIRAMDBG , RULL(0x0601084D), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_PPE_XIRAMDBG , RULL(0x06010853), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM ); -REG64( XBUS_IOPPE_PPE_XIRAMEDR , RULL(0x0601084E), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_PPE_XIRAMEDR , RULL(0x06010854), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM ); -REG64( XBUS_IOPPE_PPE_XIRAMGA , RULL(0x0601084C), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_PPE_XIRAMGA , RULL(0x06010852), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO ); -REG64( XBUS_IOPPE_PPE_XIRAMRA , RULL(0x0601084B), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_PPE_XIRAMRA , RULL(0x06010851), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO ); -REG64( XBUS_IOPPE_PPE_XIXCR , RULL(0x0601084A), SH_UNT_XBUS_IOPPE, +REG64( XBUS_IOPPE_PPE_XIXCR , RULL(0x06010850), SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO ); REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL , RULL(0x8003000D06010C3F), SH_UNT_XBUS , @@ -5455,13 +5534,6 @@ REG64( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG , RULL(0x80091800 REG64( XBUS_2_RX0_RX_CTL_CNTL9_EO_PG , RULL(0x800918000601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); -REG64( XBUS_RX0_RX_CTL_CNTLX10_E_PG , RULL(0x800A280006010C3F), SH_UNT_XBUS , - SH_ACS_SCOM ); -REG64( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG , RULL(0x800A28000601103F), SH_UNT_XBUS_1 , - SH_ACS_SCOM ); -REG64( XBUS_2_RX0_RX_CTL_CNTLX10_E_PG , RULL(0x800A28000601143F), SH_UNT_XBUS_2 , - SH_ACS_SCOM ); - REG64( XBUS_RX0_RX_CTL_CNTLX11_E_PG , RULL(0x800A300006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG , RULL(0x800A30000601103F), SH_UNT_XBUS_1 , @@ -5469,13 +5541,6 @@ REG64( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG , RULL(0x800A3000 REG64( XBUS_2_RX0_RX_CTL_CNTLX11_E_PG , RULL(0x800A30000601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); -REG64( XBUS_RX0_RX_CTL_CNTLX5_E_PG , RULL(0x800A000006010C3F), SH_UNT_XBUS , - SH_ACS_SCOM ); -REG64( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG , RULL(0x800A00000601103F), SH_UNT_XBUS_1 , - SH_ACS_SCOM ); -REG64( XBUS_2_RX0_RX_CTL_CNTLX5_E_PG , RULL(0x800A00000601143F), SH_UNT_XBUS_2 , - SH_ACS_SCOM ); - REG64( XBUS_RX0_RX_CTL_CNTLX7_EO_PG , RULL(0x8009080006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG , RULL(0x800908000601103F), SH_UNT_XBUS_1 , @@ -6008,6 +6073,13 @@ REG64( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG , RULL(0x800AE800 REG64( XBUS_2_RX0_RX_GLBSM_CNTL3_EO_PG , RULL(0x800AE8000601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); +REG64( XBUS_RX0_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF00006010C3F), SH_UNT_XBUS , + SH_ACS_SCOM ); +REG64( XBUS_1_RX0_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF0000601103F), SH_UNT_XBUS_1 , + SH_ACS_SCOM ); +REG64( XBUS_2_RX0_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF0000601143F), SH_UNT_XBUS_2 , + SH_ACS_SCOM ); + REG64( XBUS_RX0_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB00006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB0000601103F), SH_UNT_XBUS_1 , @@ -6015,6 +6087,13 @@ REG64( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB000 REG64( XBUS_2_RX0_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB0000601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); +REG64( XBUS_RX0_RX_GLBSM_MODE1_E_PG , RULL(0x800AF80006010C3F), SH_UNT_XBUS , + SH_ACS_SCOM ); +REG64( XBUS_1_RX0_RX_GLBSM_MODE1_E_PG , RULL(0x800AF8000601103F), SH_UNT_XBUS_1 , + SH_ACS_SCOM ); +REG64( XBUS_2_RX0_RX_GLBSM_MODE1_E_PG , RULL(0x800AF8000601143F), SH_UNT_XBUS_2 , + SH_ACS_SCOM ); + REG64( XBUS_RX0_RX_GLBSM_SPARE_MODE_PG , RULL(0x800A800006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG , RULL(0x800A80000601103F), SH_UNT_XBUS_1 , @@ -11706,13 +11785,6 @@ REG64( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG , RULL(0x80091820 REG64( XBUS_2_RX1_RX_CTL_CNTL9_EO_PG , RULL(0x800918200601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); -REG64( XBUS_RX1_RX_CTL_CNTLX10_E_PG , RULL(0x800A282006010C3F), SH_UNT_XBUS , - SH_ACS_SCOM ); -REG64( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG , RULL(0x800A28200601103F), SH_UNT_XBUS_1 , - SH_ACS_SCOM ); -REG64( XBUS_2_RX1_RX_CTL_CNTLX10_E_PG , RULL(0x800A28200601143F), SH_UNT_XBUS_2 , - SH_ACS_SCOM ); - REG64( XBUS_RX1_RX_CTL_CNTLX11_E_PG , RULL(0x800A302006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG , RULL(0x800A30200601103F), SH_UNT_XBUS_1 , @@ -11720,13 +11792,6 @@ REG64( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG , RULL(0x800A3020 REG64( XBUS_2_RX1_RX_CTL_CNTLX11_E_PG , RULL(0x800A30200601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); -REG64( XBUS_RX1_RX_CTL_CNTLX5_E_PG , RULL(0x800A002006010C3F), SH_UNT_XBUS , - SH_ACS_SCOM ); -REG64( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG , RULL(0x800A00200601103F), SH_UNT_XBUS_1 , - SH_ACS_SCOM ); -REG64( XBUS_2_RX1_RX_CTL_CNTLX5_E_PG , RULL(0x800A00200601143F), SH_UNT_XBUS_2 , - SH_ACS_SCOM ); - REG64( XBUS_RX1_RX_CTL_CNTLX7_EO_PG , RULL(0x8009082006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG , RULL(0x800908200601103F), SH_UNT_XBUS_1 , @@ -12259,6 +12324,13 @@ REG64( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG , RULL(0x800AE820 REG64( XBUS_2_RX1_RX_GLBSM_CNTL3_EO_PG , RULL(0x800AE8200601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); +REG64( XBUS_RX1_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF02006010C3F), SH_UNT_XBUS , + SH_ACS_SCOM ); +REG64( XBUS_1_RX1_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF0200601103F), SH_UNT_XBUS_1 , + SH_ACS_SCOM ); +REG64( XBUS_2_RX1_RX_GLBSM_CNTL4_EO_PG , RULL(0x800AF0200601143F), SH_UNT_XBUS_2 , + SH_ACS_SCOM ); + REG64( XBUS_RX1_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB02006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB0200601103F), SH_UNT_XBUS_1 , @@ -12266,6 +12338,13 @@ REG64( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB020 REG64( XBUS_2_RX1_RX_GLBSM_CNTLX1_EO_PG , RULL(0x800AB0200601143F), SH_UNT_XBUS_2 , SH_ACS_SCOM ); +REG64( XBUS_RX1_RX_GLBSM_MODE1_E_PG , RULL(0x800AF82006010C3F), SH_UNT_XBUS , + SH_ACS_SCOM ); +REG64( XBUS_1_RX1_RX_GLBSM_MODE1_E_PG , RULL(0x800AF8200601103F), SH_UNT_XBUS_1 , + SH_ACS_SCOM ); +REG64( XBUS_2_RX1_RX_GLBSM_MODE1_E_PG , RULL(0x800AF8200601143F), SH_UNT_XBUS_2 , + SH_ACS_SCOM ); + REG64( XBUS_RX1_RX_GLBSM_SPARE_MODE_PG , RULL(0x800A802006010C3F), SH_UNT_XBUS , SH_ACS_SCOM ); REG64( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG , RULL(0x800A80200601103F), SH_UNT_XBUS_1 , diff --git a/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H index 3b07d3c5..7c760664 100644 --- a/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H @@ -262,10 +262,14 @@ REG64_FLD( XBUS_PERV_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( XBUS_PERV_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , +REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , +REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_TRIG_SEL ); +REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); REG64_FLD( XBUS_PERV_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( XBUS_PERV_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , @@ -274,6 +278,10 @@ REG64_FLD( XBUS_PERV_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UN SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( XBUS_PERV_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); +REG64_FLD( XBUS_PERV_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SYNC_BRCST ); +REG64_FLD( XBUS_PERV_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); @@ -422,6 +430,198 @@ REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UN REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( XBUS_PERV_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_START ); +REG64_FLD( XBUS_PERV_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_STOP ); +REG64_FLD( XBUS_PERV_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SCOM_TRACE_RESET ); + +REG64_FLD( XBUS_1_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( XBUS_1_FIR_ACTION0_REG_ACTION0_LEN , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( XBUS_1_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( XBUS_1_FIR_ACTION1_REG_ACTION1_LEN , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR , 1 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_GCR_HANG_ERROR , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_GCR_HANG_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED3_7 , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED3_7 ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED3_7_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED3_7_LEN ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS0_TRAINING_ERROR , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS0_SPARE_DEPLOYED , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS0_MAX_SPARES_EXCEEDED , 10 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR , 11 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS0_TOO_MANY_BUS_ERRORS , 12 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED13_15 , 13 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED13_15 ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED13_15_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED13_15_LEN ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS1_TRAINING_ERROR , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS1_SPARE_DEPLOYED , 17 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS1_MAX_SPARES_EXCEEDED , 18 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR , 19 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS1_TOO_MANY_BUS_ERRORS , 20 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED21_23 , 21 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED21_23 ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED21_23_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED21_23_LEN ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS2_TRAINING_ERROR , 24 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS2_SPARE_DEPLOYED , 25 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS2_MAX_SPARES_EXCEEDED , 26 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR , 27 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS2_TOO_MANY_BUS_ERRORS , 28 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED29_31 , 29 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED29_31 ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED29_31_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED29_31_LEN ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS3_TRAINING_ERROR , 32 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS3_SPARE_DEPLOYED , 33 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS3_MAX_SPARES_EXCEEDED , 34 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR , 35 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS3_TOO_MANY_BUS_ERRORS , 36 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED37_39 , 37 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED37_39 ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED37_39_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED37_39_LEN ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS4_TRAINING_ERROR , 40 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS4_SPARE_DEPLOYED , 41 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS4_MAX_SPARES_EXCEEDED , 42 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR , 43 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RX_BUS4_TOO_MANY_BUS_ERRORS , 44 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED45_47 , 45 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED45_47 ); +REG64_FLD( XBUS_1_FIR_MASK_REG_RESERVED45_47_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED45_47_LEN ); +REG64_FLD( XBUS_1_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( XBUS_1_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( XBUS_1_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR , 1 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_TX_INVALID_STATE_OR_PARITY_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_GCR_HANG_ERROR , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_GCR_HANG_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED3_7 , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED3_7 ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED3_7_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED3_7_LEN ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS0_TRAINING_ERROR , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS0_SPARE_DEPLOYED , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS0_MAX_SPARES_EXCEEDED , 10 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR , 11 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS0_TOO_MANY_BUS_ERRORS , 12 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS0_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED13_15 , 13 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED13_15 ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED13_15_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED13_15_LEN ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS1_TRAINING_ERROR , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS1_SPARE_DEPLOYED , 17 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS1_MAX_SPARES_EXCEEDED , 18 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR , 19 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS1_TOO_MANY_BUS_ERRORS , 20 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS1_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED21_23 , 21 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED21_23 ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED21_23_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED21_23_LEN ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS2_TRAINING_ERROR , 24 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS2_SPARE_DEPLOYED , 25 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS2_MAX_SPARES_EXCEEDED , 26 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR , 27 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS2_TOO_MANY_BUS_ERRORS , 28 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS2_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED29_31 , 29 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED29_31 ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED29_31_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED29_31_LEN ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS3_TRAINING_ERROR , 32 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS3_SPARE_DEPLOYED , 33 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS3_MAX_SPARES_EXCEEDED , 34 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR , 35 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS3_TOO_MANY_BUS_ERRORS , 36 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS3_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED37_39 , 37 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED37_39 ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED37_39_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED37_39_LEN ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS4_TRAINING_ERROR , 40 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_TRAINING_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS4_SPARE_DEPLOYED , 41 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_SPARE_DEPLOYED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS4_MAX_SPARES_EXCEEDED , 42 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_MAX_SPARES_EXCEEDED ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR , 43 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_RX_BUS4_TOO_MANY_BUS_ERRORS , 44 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RX_BUS4_TOO_MANY_BUS_ERRORS ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED45_47 , 45 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED45_47 ); +REG64_FLD( XBUS_1_FIR_REG_RESERVED45_47_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_RESERVED45_47_LEN ); +REG64_FLD( XBUS_1_FIR_REG_SCOMFIR_ERROR , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR ); +REG64_FLD( XBUS_1_FIR_REG_SCOMFIR_ERROR_CLONE , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR_CLONE ); + +REG64_FLD( XBUS_1_FIR_WOF_REG_WOF , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( XBUS_1_FIR_WOF_REG_WOF_LEN , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( XBUS_LL0_IOEL_CONFIG_LINK_PAIR , 0 , SH_UNT_XBUS , SH_ACS_SCOM , SH_FLD_LINK_PAIR ); REG64_FLD( XBUS_LL0_IOEL_CONFIG_DISABLE_SL_ECC , 1 , SH_UNT_XBUS , SH_ACS_SCOM , @@ -560,6 +760,11 @@ REG64_FLD( XBUS_LL0_IOEL_FIR_ACTION1_REG_ACTION1 , 0 , SH_UN REG64_FLD( XBUS_LL0_IOEL_FIR_ACTION1_REG_ACTION1_LEN , 64 , SH_UNT_XBUS , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); +REG64_FLD( XBUS_LL0_IOEL_FIR_WOF_REG_WOF , 0 , SH_UNT_XBUS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( XBUS_LL0_IOEL_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT_XBUS , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID , 0 , SH_UNT_XBUS , SH_ACS_SCOM , SH_FLD_LINK0_ROUND_TRIP_VALID ); REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP , 2 , SH_UNT_XBUS , SH_ACS_SCOM , @@ -1432,6 +1637,11 @@ REG64_FLD( XBUS_1_LL1_IOEL_FIR_ACTION1_REG_ACTION1 , 0 , SH_UN REG64_FLD( XBUS_1_LL1_IOEL_FIR_ACTION1_REG_ACTION1_LEN , 64 , SH_UNT_XBUS_1 , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); +REG64_FLD( XBUS_1_LL1_IOEL_FIR_WOF_REG_WOF , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( XBUS_1_LL1_IOEL_FIR_WOF_REG_WOF_LEN , 64 , SH_UNT_XBUS_1 , SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID , 0 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LINK0_ROUND_TRIP_VALID ); REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2172,12 +2382,24 @@ REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); +REG64_FLD( XBUS_IOPPE_MIB_XIICAC_PIB_IFETCH_PENDING , 34 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( XBUS_IOPPE_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID ); +REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_VALID_LEN ); +REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE_PTR ); +REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , + SH_FLD_ICACHE_LINE2_ERR ); +REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , + SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -2217,23 +2439,164 @@ REG64_FLD( XBUS_IOPPE_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( XBUS_IOPPE_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_ACTION0_REG_ACTION0_LEN , 13 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( XBUS_IOPPE_PPE_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_ACTION1_REG_ACTION1_LEN , 13 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_ERROR , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ERROR ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_ERROR_LEN , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ERROR_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_HALTED , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT , 5 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG_TIMEOUT ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_MMIO_DATA_IN , 6 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_MMIO_DATA_IN ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK , 7 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ARB_MISSED_SCRUB_TICK ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_ARB_ARY_UE , 8 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_UE ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_ARB_ARY_CE , 9 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_CE ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_RESERVED , 10 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 11 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 12 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); + +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_ERROR , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ERROR ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_ERROR_LEN , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ERROR_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_HALTED , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_WATCHDOG_TIMEOUT , 5 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG_TIMEOUT ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_MMIO_DATA_IN , 6 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_MMIO_DATA_IN ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK , 7 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ARB_MISSED_SCRUB_TICK ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_ARB_ARY_UE , 8 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_UE ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_ARB_ARY_CE , 9 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_ARB_ARY_CE ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_RESERVED , 10 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_RESERVED ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_SCOMFIR_ERROR , 11 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_REG_SCOMFIR_ERROR_CLONE , 12 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_ERROR_CLONE ); + +REG64_FLD( XBUS_IOPPE_PPE_FIR_WOF_REG_WOF , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF ); +REG64_FLD( XBUS_IOPPE_PPE_FIR_WOF_REG_WOF_LEN , 13 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WCLRREG, + SH_FLD_WOF_LEN ); + +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); - +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_IAR , 32 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_IAR ); +REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_IAR_LEN ); + +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HS ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HC ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HC_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_HCP ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_RIP ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_SIP ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_TRAP ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_IAC ); REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_DACR ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_DACW ); REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_TRH ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_SMS ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_SMS_LEN ); REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_EP ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_PTR ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_ST ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_MFE ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_MCS ); +REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , + SH_FLD_XSR_MCS_LEN ); REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM , @@ -2271,6 +2634,37 @@ REG64_FLD( XBUS_IOPPE_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( XBUS_IOPPE_PPE_XIXCR_XCR_LEN , 3 , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -2308,6 +2702,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2327,6 +2742,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2402,11 +2822,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2440,10 +2900,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -2596,6 +3052,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2613,6 +3074,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -2650,6 +3142,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2669,6 +3182,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2744,11 +3262,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2782,10 +3340,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -2938,6 +3492,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -2955,6 +3514,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -2992,6 +3582,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3011,6 +3622,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3086,11 +3702,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3124,10 +3780,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -3280,6 +3932,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3297,6 +3954,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -3334,6 +4022,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3353,6 +4062,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3428,11 +4142,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3466,10 +4220,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -3622,6 +4372,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3639,6 +4394,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -3676,6 +4462,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3695,6 +4502,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3770,11 +4582,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3808,10 +4660,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -3964,6 +4812,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -3981,6 +4834,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -4018,6 +4902,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4037,6 +4942,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4112,11 +5022,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4150,10 +5100,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -4306,6 +5252,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4323,6 +5274,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -4360,6 +5342,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4379,6 +5382,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4454,11 +5462,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4492,10 +5540,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -4648,6 +5692,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4665,6 +5714,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -4702,6 +5782,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4721,6 +5822,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4796,11 +5902,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -4834,10 +5980,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -4990,6 +6132,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5007,6 +6154,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -5044,6 +6222,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5063,6 +6262,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5138,11 +6342,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5176,10 +6420,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -5332,6 +6572,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5349,6 +6594,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -5386,6 +6662,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5405,6 +6702,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5480,11 +6782,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5518,10 +6860,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -5674,6 +7012,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5691,6 +7034,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -5728,6 +7102,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5747,6 +7142,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5822,11 +7222,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -5860,10 +7300,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -6016,6 +7452,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6033,6 +7474,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -6070,6 +7542,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6089,6 +7582,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6164,11 +7662,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6202,10 +7740,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -6358,6 +7892,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6375,6 +7914,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -6412,6 +7982,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6431,6 +8022,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6506,11 +8102,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6544,10 +8180,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -6700,6 +8332,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6717,6 +8354,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -6754,6 +8422,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6773,6 +8462,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6848,11 +8542,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -6886,10 +8620,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -7042,6 +8772,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7059,6 +8794,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -7096,6 +8862,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7115,6 +8902,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7190,11 +8982,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7228,10 +9060,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -7384,6 +9212,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7401,6 +9234,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -7438,6 +9302,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7457,6 +9342,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7532,11 +9422,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7570,10 +9500,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -7726,6 +9652,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7743,6 +9674,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -7780,6 +9742,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7799,6 +9782,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7874,11 +9862,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -7912,10 +9940,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -8068,6 +10092,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8085,6 +10114,37 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -8122,6 +10182,27 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8141,6 +10222,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8216,11 +10302,51 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8254,10 +10380,6 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -8410,6 +10532,11 @@ REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8591,35 +10718,6 @@ REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN , 2 , SH REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PERVASIVE_CAPT ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_DONE_FIN_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_NOP_FIN_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_DONE_FIN_GCRMSG , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_NOP_FIN_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_DONE_FIN_GCRMSG , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_NOP_FIN_GCRMSG , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_DONE_NOP_FIN_GCRMSG , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FAIL_NOP_FIN_GCRMSG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FRESULTS_FIN_GCRMSG , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_ACK_FIN_GCRMSG , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG ); - REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DESKEW_SEQ_GCRMSG ); REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8633,17 +10731,6 @@ REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG , 56 , SH_UN REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DESKEW_SKMAX_GCRMSG_LEN ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_REQ_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_REQ_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_LANE2RPR_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_IP_GCRMSG , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_IP_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_COMPLETE_GCRMSG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_COMPLETE_GCRMSG ); - REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_GCRMSG ); REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -8841,14 +10928,6 @@ REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_MASTER_MODE , 48 , SH_UN SH_FLD_MASTER_MODE ); REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DISABLE_FENCE_RESET ); -REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_ACT_CHECK_TIMEOUT_SEL ); -REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN ); -REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BIST_JITTER_PULSE_SEL ); -REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BIST_JITTER_PULSE_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_FENCE , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_FENCE ); REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9184,10 +11263,6 @@ REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS , 52 , SH_UN SH_FLD_NONSLS_CNTR_TAP_PTS ); REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_NONSLS_CNTR_TAP_PTS_LEN ); -REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL ); -REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN ); REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLS_EXCEPTION2_CS ); REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9317,10 +11392,6 @@ REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG , 48 , SH_UN SH_FLD_WT_PREV_DONE_GCRMSG ); REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_ALL_DONE_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_CD_PREV_DONE_GCRMSG , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_CD_PREV_DONE_GCRMSG ); -REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_CD_ALL_DONE_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_CD_ALL_DONE_GCRMSG ); REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CNTLS_PREV_LDED_GCRMSG ); @@ -9342,6 +11413,23 @@ REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT , 55 , SH_UN SH_FLD_PRBS_SLS_EXPECT ); REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SLS_EXPECT_LEN ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_HALF_RATE_MODE , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_HALF_RATE_MODE ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); @@ -9366,8 +11454,92 @@ REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN , 4 , SH_UN REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CTL_CLKDIST_PDWN ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS2_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS2_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_LAST_BAD_BUS_LANE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN , 11 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_SATURATED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL , 60 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL , 61 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_TIMER_SATURATED_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG_RX_PRBS_DATA_RCV_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PRBS_DATA_RCV_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG_RX_PG_PRBS_SEED_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_PRBS_SEED_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PRVCPT_CHANGE_DET_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERR_INJ ); @@ -9379,6 +11551,37 @@ REG64_FLD( XBUS_1_RX0_RX_FIR1_MASK_PG_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RX_FIR1_MASK_PG_ERRS_LEN , 15 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERR_RO_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERR_INJ ); REG64_FLD( XBUS_1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9389,6 +11592,39 @@ REG64_FLD( XBUS_1_RX0_RX_FIR2_MASK_PG_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX0_RX_FIR2_MASK_PG_ERRS_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL ); + REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_ERROR , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9454,12 +11690,36 @@ REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE , 51 , SH_UN SH_FLD_MANUAL_RECAL_LANE ); REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_MANUAL_RECAL_LANE_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_TIMEOUT_EXT_SEL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_TIMEOUT_EXT_SEL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_HALF_RATE_MODE , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_HALF_RATE_MODE ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_FIR_RESET ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_MODE1_E_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RPR_TX_LD_CNTLS_TIMEOUT_SEL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_MODE1_E_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_MODE1_E_PG_TX_SLS_LN_MV_TIMEOUT_SEL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_LN_MV_TIMEOUT_SEL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_MODE1_E_PG_TX_SLS_LN_MV_TIMEOUT_SEL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_LN_MV_TIMEOUT_SEL_LEN ); + REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9483,6 +11743,119 @@ REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE , 57 , SH_UN REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SERVO_RECAL_IP ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN , 12 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_MAIN_INIT_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTM_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTM_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG_RX_WT_CU_PLL_LOCK_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WT_CU_PLL_LOCK_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RECAL_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RECAL_CNT_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_CUR_LANE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_CUR_LANE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISGT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISLT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISEQ_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DSM_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DSM_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RXDSM_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RXDSM_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_INT_REQ_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_INT_REQ_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RPR_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RPR_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_RCVY_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_MANUAL_RECAL_DONE_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_VAL_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_CMD_VAL_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_NONSLS_CMD_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_NONSLS_CMD_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_CMD_ENCODE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_ENC_BUS_LANE2RPR_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG_RX_REPAIR_REQ_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_REPAIR_REQ_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_USED_AS_SPR_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_USED_AS_SPR_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DYN_RPR_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DYN_RPR_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_HNDSHK_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_LANE1 ); @@ -9545,8 +11918,6 @@ REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9603,8 +11974,6 @@ REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9661,8 +12030,6 @@ REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9719,8 +12086,6 @@ REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9777,8 +12142,6 @@ REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9835,8 +12198,6 @@ REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9893,8 +12254,6 @@ REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -9951,8 +12310,6 @@ REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10009,8 +12366,6 @@ REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10067,8 +12422,6 @@ REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10125,8 +12478,6 @@ REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10183,8 +12534,6 @@ REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10241,8 +12590,6 @@ REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10299,8 +12646,6 @@ REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10357,8 +12702,6 @@ REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10415,8 +12758,6 @@ REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10473,8 +12814,6 @@ REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10531,8 +12870,6 @@ REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10589,8 +12926,6 @@ REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10647,8 +12982,6 @@ REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10705,8 +13038,6 @@ REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10763,8 +13094,6 @@ REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10821,8 +13150,6 @@ REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10879,8 +13206,6 @@ REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10914,6 +13239,37 @@ REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD , 54 , SH_UN REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PATH_OFF_ODD_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -10951,6 +13307,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -10970,6 +13347,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11045,11 +13427,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11083,10 +13505,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -11239,6 +13657,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11256,6 +13679,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -11293,6 +13747,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11312,6 +13787,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11387,11 +13867,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11425,10 +13945,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -11581,6 +14097,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11598,6 +14119,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -11635,6 +14187,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11654,6 +14227,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11729,11 +14307,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11767,10 +14385,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -11923,6 +14537,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11940,6 +14559,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -11977,6 +14627,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -11996,6 +14667,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12071,11 +14747,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12109,10 +14825,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -12265,6 +14977,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12282,6 +14999,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -12319,6 +15067,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12338,6 +15107,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12413,11 +15187,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12451,10 +15265,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -12607,6 +15417,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12624,6 +15439,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -12661,6 +15507,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12680,6 +15547,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12755,11 +15627,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12793,10 +15705,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -12949,6 +15857,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -12966,6 +15879,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -13003,6 +15947,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13022,6 +15987,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13097,11 +16067,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13135,10 +16145,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -13291,6 +16297,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13308,6 +16319,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -13345,6 +16387,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13364,6 +16427,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13439,11 +16507,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13477,10 +16585,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -13633,6 +16737,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13650,6 +16759,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -13687,6 +16827,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13706,6 +16867,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13781,11 +16947,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13819,10 +17025,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -13975,6 +17177,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -13992,6 +17199,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -14029,6 +17267,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14048,6 +17307,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14123,11 +17387,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14161,10 +17465,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -14317,6 +17617,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14334,6 +17639,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -14371,6 +17707,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14390,6 +17747,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14465,11 +17827,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14503,10 +17905,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -14659,6 +18057,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14676,6 +18079,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -14713,6 +18147,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14732,6 +18187,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14807,11 +18267,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -14845,10 +18345,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -15001,6 +18497,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15018,6 +18519,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -15055,6 +18587,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15074,6 +18627,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15149,11 +18707,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15187,10 +18785,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -15343,6 +18937,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15360,6 +18959,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -15397,6 +19027,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15416,6 +19067,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15491,11 +19147,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15529,10 +19225,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -15685,6 +19377,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15702,6 +19399,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -15739,6 +19467,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15758,6 +19507,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15833,11 +19587,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -15871,10 +19665,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -16027,6 +19817,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16044,6 +19839,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -16081,6 +19907,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16100,6 +19947,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16175,11 +20027,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16213,10 +20105,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -16369,6 +20257,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16386,6 +20279,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -16423,6 +20347,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16442,6 +20387,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16517,11 +20467,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16555,10 +20545,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -16711,6 +20697,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16728,6 +20719,37 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6 , 54 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7 , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_7 ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 54 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL , 56 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 57 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL , 60 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 61 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL , 62 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_EDGE_TRACK_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2 , SH_UNT_XBUS_1 , @@ -16765,6 +20787,27 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SI REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 50 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL , 51 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 52 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL , 53 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN , 2 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PR_TRACE_DDC_STOP ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16784,6 +20827,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_S REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL , 48 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL , 49 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_SEL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16859,11 +20907,51 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG , 53 , SH_UN SH_FLD_DDC_CFG ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DDC_CFG_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_INIT_TMR_CFG_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_NIBBLE_FOUND_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DFE_SYNC_DONE_B_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_WOBBLE_A_IP_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_DDC_FAILED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL , 55 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_TRACE_STOPPED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_PR_DFE_CLKADJ ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -16897,10 +20985,6 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL , 54 , SH_UN SH_FLD_CM_CNTL ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CM_CNTL_LEN ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL ); -REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_PR_IQ_RES_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_A_H3E_VAL ); @@ -17053,6 +21137,11 @@ REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -17234,35 +21323,6 @@ REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN , 2 , SH REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PERVASIVE_CAPT ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_DONE_FIN_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_NOP_FIN_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_DONE_FIN_GCRMSG , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_NOP_FIN_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_DONE_FIN_GCRMSG , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_NOP_FIN_GCRMSG , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_DONE_NOP_FIN_GCRMSG , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FAIL_NOP_FIN_GCRMSG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FRESULTS_FIN_GCRMSG , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_ACK_FIN_GCRMSG , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG ); - REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DESKEW_SEQ_GCRMSG ); REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -17276,17 +21336,6 @@ REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG , 56 , SH_UN REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DESKEW_SKMAX_GCRMSG_LEN ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_REQ_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_REQ_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_LANE2RPR_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_IP_GCRMSG , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_IP_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_COMPLETE_GCRMSG , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_DYN_RPR_COMPLETE_GCRMSG ); - REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CAL_LANE_GCRMSG ); REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -17484,14 +21533,6 @@ REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_MASTER_MODE , 48 , SH_UN SH_FLD_MASTER_MODE ); REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_DISABLE_FENCE_RESET ); -REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_ACT_CHECK_TIMEOUT_SEL ); -REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN ); -REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BIST_JITTER_PULSE_SEL ); -REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BIST_JITTER_PULSE_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_FENCE , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_FENCE ); REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -17827,10 +21868,6 @@ REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS , 52 , SH_UN SH_FLD_NONSLS_CNTR_TAP_PTS ); REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_NONSLS_CNTR_TAP_PTS_LEN ); -REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL ); -REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN ); REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLS_EXCEPTION2_CS ); REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -17960,10 +21997,6 @@ REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG , 48 , SH_UN SH_FLD_WT_PREV_DONE_GCRMSG ); REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_ALL_DONE_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_CD_PREV_DONE_GCRMSG , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_CD_PREV_DONE_GCRMSG ); -REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_CD_ALL_DONE_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_CD_ALL_DONE_GCRMSG ); REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CNTLS_PREV_LDED_GCRMSG ); @@ -17985,6 +22018,23 @@ REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT , 55 , SH_UN SH_FLD_PRBS_SLS_EXPECT ); REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SLS_EXPECT_LEN ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_HALF_RATE_MODE , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_HALF_RATE_MODE ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL , 52 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); @@ -18009,8 +22059,92 @@ REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN , 4 , SH_UN REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CTL_CLKDIST_PDWN ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_16_23_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_N_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS2_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS2_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_LAST_BAD_BUS_LANE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN , 11 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_COUNT_SATURATED_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL , 60 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL , 61 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_BER_TIMER_SATURATED_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_STATUS_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG_RX_PRBS_DATA_RCV_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PRBS_DATA_RCV_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG_RX_PG_PRBS_SEED_DONE_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_PRBS_SEED_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PRVCPT_CHANGE_DET_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_0_15_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SCAN_P_16_23_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERR_INJ ); @@ -18022,6 +22156,37 @@ REG64_FLD( XBUS_1_RX1_RX_FIR1_MASK_PG_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RX_FIR1_MASK_PG_ERRS_LEN , 15 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PL_FIR_ERR_RO_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERR_INJ ); REG64_FLD( XBUS_1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18032,6 +22197,39 @@ REG64_FLD( XBUS_1_RX1_RX_FIR2_MASK_PG_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX1_RX_FIR2_MASK_PG_ERRS_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL ); + REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_ERROR , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18097,12 +22295,36 @@ REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE , 51 , SH_UN SH_FLD_MANUAL_RECAL_LANE ); REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_MANUAL_RECAL_LANE_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_TIMEOUT_EXT_SEL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_TIMEOUT_EXT_SEL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_HALF_RATE_MODE , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_HALF_RATE_MODE ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL , 51 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL ); REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_FIR_RESET ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_MODE1_E_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RPR_TX_LD_CNTLS_TIMEOUT_SEL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_MODE1_E_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_MODE1_E_PG_TX_SLS_LN_MV_TIMEOUT_SEL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_LN_MV_TIMEOUT_SEL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_MODE1_E_PG_TX_SLS_LN_MV_TIMEOUT_SEL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_LN_MV_TIMEOUT_SEL_LEN ); + REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_1 , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18126,6 +22348,119 @@ REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE , 57 , SH_UN REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SERVO_RECAL_IP ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN , 12 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_EYE_OPT_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_MAIN_INIT_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN , 4 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTM_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTM_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG_RX_WT_CU_PLL_LOCK_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WT_CU_PLL_LOCK_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RECAL_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RECAL_CNT_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_CUR_LANE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_CUR_LANE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISGT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISLT_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_ISEQ_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DACTEST_DIFF_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DSM_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DSM_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RXDSM_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RXDSM_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_INT_REQ_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN , 16 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_INT_REQ_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RPR_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_RPR_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_RCVY_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_MANUAL_RECAL_DONE_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_VAL_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_CMD_VAL_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_NONSLS_CMD_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_NONSLS_CMD_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_CMD_ENCODE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_ENC_BUS_LANE2RPR_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG_RX_REPAIR_REQ_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_REPAIR_REQ_RO_SIGNAL ); + +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_USED_AS_SPR_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_USED_AS_SPR_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DYN_RPR_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL_LEN , 6 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_DYN_RPR_STATE_RO_SIGNAL_LEN ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_HNDSHK_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN , 8 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_LANE1 ); @@ -18188,8 +22523,6 @@ REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18246,8 +22579,6 @@ REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18304,8 +22635,6 @@ REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18362,8 +22691,6 @@ REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18420,8 +22747,6 @@ REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18478,8 +22803,6 @@ REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18536,8 +22859,6 @@ REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18594,8 +22915,6 @@ REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18652,8 +22971,6 @@ REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18710,8 +23027,6 @@ REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18768,8 +23083,6 @@ REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18826,8 +23139,6 @@ REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18884,8 +23195,6 @@ REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -18942,8 +23251,6 @@ REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19000,8 +23307,6 @@ REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19058,8 +23363,6 @@ REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_U SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19116,8 +23419,6 @@ REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19174,8 +23475,6 @@ REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19232,8 +23531,6 @@ REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19290,8 +23587,6 @@ REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19348,8 +23643,6 @@ REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19406,8 +23699,6 @@ REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19464,8 +23755,6 @@ REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19522,8 +23811,6 @@ REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49 , SH_UN SH_FLD_BAD_EYE_OPT_WIDTH ); REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_BAD_EYE_OPT_HEIGHT ); -REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_BAD_EYE_OPT_DDC ); REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_WT_LANE_DISABLED ); REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19567,6 +23854,11 @@ REG64_FLD( XBUS_1_RX_FIR_MASK_PB_ERRS , 48 , SH_UN REG64_FLD( XBUS_1_RX_FIR_MASK_PB_ERRS_LEN , 10 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS_LEN ); +REG64_FLD( XBUS_1_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL ); +REG64_FLD( XBUS_1_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL_LEN , 10 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_RX_PB_FIR_ERRS_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_RX_FIR_RESET_PB_CLR_PAR_ERRS , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( XBUS_1_RX_FIR_RESET_PB_RESET , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -19680,8 +23972,28 @@ REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_XBUS_PERV, - SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -19773,6 +24085,14 @@ REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -19804,8 +24124,28 @@ REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_XBUS_PERV, - SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -19897,6 +24237,14 @@ REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO , SH_FLD_DATA ); @@ -19928,8 +24276,28 @@ REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); -REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_XBUS_PERV, - SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_WRITE_ON_RUN_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_EXTEND_TRIG_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_BANK_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ENH_MODE ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SELCT_CONTROL_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); @@ -20021,6 +24389,14 @@ REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_ERROR_MODE_LT_LEN ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_XBUS_PERV, + SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); +REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_XBUS_PERV, SH_ACS_SCOM , + SH_FLD_SPARE_LT ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20032,6 +24408,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20041,6 +24436,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20078,8 +24476,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20099,6 +24495,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20110,6 +24508,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20119,6 +24536,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20156,8 +24576,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20177,6 +24595,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20188,6 +24608,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20197,6 +24636,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20234,8 +24676,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20255,6 +24695,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20266,6 +24708,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20275,6 +24736,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20312,8 +24776,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20333,6 +24795,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20344,6 +24808,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20353,6 +24836,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20390,8 +24876,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20411,6 +24895,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20422,6 +24908,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20431,6 +24936,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20468,8 +24976,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20489,6 +24995,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20500,6 +25008,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20509,6 +25036,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20546,8 +25076,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20567,6 +25095,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20578,6 +25108,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20587,6 +25136,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20624,8 +25176,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20645,6 +25195,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20656,6 +25208,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20665,6 +25236,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20702,8 +25276,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20723,6 +25295,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20734,6 +25308,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20743,6 +25336,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20780,8 +25376,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20801,6 +25395,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20812,6 +25408,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20821,6 +25436,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20858,8 +25476,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20879,6 +25495,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20890,6 +25508,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20899,6 +25536,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20936,8 +25576,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -20957,6 +25595,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -20968,6 +25608,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -20977,6 +25636,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21014,8 +25676,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21035,6 +25695,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21046,6 +25708,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21055,6 +25736,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21092,8 +25776,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21113,6 +25795,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21124,6 +25808,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21133,6 +25836,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21170,8 +25876,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21191,6 +25895,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21202,6 +25908,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21211,6 +25936,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21248,8 +25976,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21269,6 +25995,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21280,6 +26008,25 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21289,6 +26036,9 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21326,8 +26076,6 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21347,6 +26095,8 @@ REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PSEG_PRE_EN ); @@ -21403,6 +26153,9 @@ REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN , 51 , SH_UN REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN , 13 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_NSEG_MAIN_EN_LEN ); +REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTLG1_E_PG_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE ); REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21415,6 +26168,8 @@ REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN , 59 , SH_UN SH_FLD_FFE_BOOST_EN ); REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_LEAKAGE_CTRL ); +REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_HALF_RATE_MODE , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_HALF_RATE_MODE ); REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CTL_SM_0 ); @@ -21437,6 +26192,12 @@ REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR , 48 , SH_UN SH_FLD_CLK_BIST_ERR ); REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLK_BIST_ACTIVITY_DET ); +REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_BIST_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_HNDSHK_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_CLK_STATUS ); @@ -21531,9 +26292,17 @@ REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN , 7 , SH_UN SH_FLD_SLS_LANE_GCRMSG_LEN ); REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLS_LANE_VAL_GCRMSG ); +REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_ENC_SPR1_GCRMSG , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_ENC_SPR1_GCRMSG ); REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLS_LANE_SHDW_GCRMSG ); +REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_RPR_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_SHDW_RPR_GCRMSG ); +REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR1_GCRMSG , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_MUX_SPR1_GCRMSG ); +REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR2_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_MUX_SPR2_GCRMSG ); REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG ); @@ -21543,6 +26312,10 @@ REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG , 50 , SH SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG ); REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG ); +REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR1_GCRMSG , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLV_MV_SLS_SPR1_GCRMSG ); +REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR2_GCRMSG , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLV_MV_SLS_SPR2_GCRMSG ); REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG ); REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21653,6 +26426,19 @@ REG64_FLD( XBUS_1_TX0_TX_FIR_MASK_PG_ERRS_LEN , 5 , SH_UN REG64_FLD( XBUS_1_TX0_TX_FIR_MASK_PG_PL_ERR , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PL_ERR ); +REG64_FLD( XBUS_1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX0_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERR_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( XBUS_1_TX0_TX_FIR_RESET_PG_RESET , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21703,6 +26489,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21712,6 +26517,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21749,8 +26557,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21770,6 +26576,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21781,6 +26589,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21790,6 +26617,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21827,8 +26657,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21848,6 +26676,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21859,6 +26689,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21868,6 +26717,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21905,8 +26757,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21926,6 +26776,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -21937,6 +26789,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -21946,6 +26817,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -21983,8 +26857,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22004,6 +26876,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22015,6 +26889,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22024,6 +26917,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22061,8 +26957,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22082,6 +26976,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22093,6 +26989,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22102,6 +27017,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22139,8 +27057,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22160,6 +27076,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22171,6 +27089,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22180,6 +27117,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22217,8 +27157,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22238,6 +27176,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22249,6 +27189,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22258,6 +27217,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22295,8 +27257,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22316,6 +27276,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22327,6 +27289,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22336,6 +27317,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22373,8 +27357,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22394,6 +27376,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22405,6 +27389,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22414,6 +27417,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22451,8 +27457,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22472,6 +27476,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22483,6 +27489,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22492,6 +27517,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22529,8 +27557,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22550,6 +27576,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22561,6 +27589,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22570,6 +27617,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22607,8 +27657,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22628,6 +27676,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22639,6 +27689,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22648,6 +27717,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22685,8 +27757,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22706,6 +27776,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22717,6 +27789,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22726,6 +27817,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22763,8 +27857,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22784,6 +27876,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22795,6 +27889,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22804,6 +27917,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22841,8 +27957,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22862,6 +27976,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22873,6 +27989,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22882,6 +28017,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22919,8 +28057,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22940,6 +28076,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_0_15 ); @@ -22951,6 +28089,25 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PRBS_SEED_VALUE_16_22_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 54 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL , 55 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 56 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 57 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 58 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL , 59 , + SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_TDR_ENABLE ); @@ -22960,6 +28117,9 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48 , SH_ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ERRS ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERRS_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_LANE_PDWN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -22997,8 +28157,6 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2 , SH_FLD_PRBS_SCRAMBLE_MODE_LEN ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_CLK_DISABLE ); -REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_RXCAL , 57 , SH_UNT_XBUS_1 , SH_ACS_SCOM , - SH_FLD_RXCAL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL , 58 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_UNLOAD_SEL ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN , 3 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -23018,6 +28176,8 @@ REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS , 50 , SH_UN SH_FLD_SEG_TEST_STATUS ); REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_STATUS_LEN ); +REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_TDR_CAPT_VAL_RO_SIGNAL ); REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PSEG_PRE_EN ); @@ -23074,6 +28234,9 @@ REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN , 51 , SH_UN REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN , 13 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_NSEG_MAIN_EN_LEN ); +REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTLG1_E_PG_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL , 48 , SH_UNT_XBUS_1 , + SH_ACS_SCOM , SH_FLD_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE ); REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -23086,6 +28249,8 @@ REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN , 59 , SH_UN SH_FLD_FFE_BOOST_EN ); REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL , 61 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_LEAKAGE_CTRL ); +REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_HALF_RATE_MODE , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_HALF_RATE_MODE ); REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CTL_SM_0 ); @@ -23108,6 +28273,12 @@ REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR , 48 , SH_UN SH_FLD_CLK_BIST_ERR ); REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLK_BIST_ACTIVITY_DET ); +REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_BIST_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_HNDSHK_STATE_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN , 5 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN ); REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SEG_TEST_CLK_STATUS ); @@ -23202,9 +28373,17 @@ REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN , 7 , SH_UN SH_FLD_SLS_LANE_GCRMSG_LEN ); REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLS_LANE_VAL_GCRMSG ); +REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_ENC_SPR1_GCRMSG , 56 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_ENC_SPR1_GCRMSG ); REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLS_LANE_SHDW_GCRMSG ); +REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_RPR_GCRMSG , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_SHDW_RPR_GCRMSG ); +REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR1_GCRMSG , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_MUX_SPR1_GCRMSG ); +REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR2_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLS_LANE_MUX_SPR2_GCRMSG ); REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG ); @@ -23214,6 +28393,10 @@ REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG , 50 , SH SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG ); REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG ); +REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR1_GCRMSG , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLV_MV_SLS_SPR1_GCRMSG ); +REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR2_GCRMSG , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_SLV_MV_SLS_SPR2_GCRMSG ); REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG , 59 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG ); REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG , 60 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -23324,6 +28507,19 @@ REG64_FLD( XBUS_1_TX1_TX_FIR_MASK_PG_ERRS_LEN , 5 , SH_UN REG64_FLD( XBUS_1_TX1_TX_FIR_MASK_PG_PL_ERR , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_PL_ERR ); +REG64_FLD( XBUS_1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX1_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_PL_FIR_ERR_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX1_TX_FIR_RESET_PG_CLR_PAR_ERRS , 62 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_CLR_PAR_ERRS ); REG64_FLD( XBUS_1_TX1_TX_FIR_RESET_PG_RESET , 63 , SH_UNT_XBUS_1 , SH_ACS_SCOM , @@ -23364,11 +28560,39 @@ REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_8_9 , 56 , SH_UN REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_8_9_LEN , 2 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_8_9_LEN ); +REG64_FLD( XBUS_1_TX_IMPCAL2_PB_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL2_PB_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL2_PB_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL2_PB_TX_ZCAL_TEST_STATUS_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_TEST_STATUS_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL2_PB_TX_ZCAL_TEST_DONE_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_TEST_DONE_RO_SIGNAL ); + REG64_FLD( XBUS_1_TX_IMPCAL_NVAL_PB_ZCAL_N , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ZCAL_N ); REG64_FLD( XBUS_1_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ZCAL_N_LEN ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL , 49 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_DONE_RO_SIGNAL , 50 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_DONE_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_ERROR_RO_SIGNAL , 51 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_ERROR_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_BUSY_RO_SIGNAL , 52 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_BUSY_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL , 53 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_CMP_OUT_RO_SIGNAL , 54 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_CMP_OUT_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL , 55 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL ); +REG64_FLD( XBUS_1_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , + SH_FLD_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN ); + REG64_FLD( XBUS_1_TX_IMPCAL_PVAL_PB_ZCAL_P , 48 , SH_UNT_XBUS_1 , SH_ACS_SCOM , SH_FLD_ZCAL_P ); REG64_FLD( XBUS_1_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN , 9 , SH_UNT_XBUS_1 , SH_ACS_SCOM , |
