Additional risk level support - (step 2) Updating the image w/RL2

This commit changes the images' .rings section by adding the TOR
RL2 variant slot to the runtime Quad chiplets, EQ and EC.

Specifically, we have changed the definition of the ATTR_RISK_LEVEL
attribute to now have three risk levels, RL0 (prev FALSE), RL1
(prev TRUE) and RL2 (new). To accomodate RL2, a new "override"
txt file has been created, ./attribute_ovd/runtime_risk2.txt and
changes to many other files using the ATTR_RISK_LEVEL attrib have
been updated as well.

Lastly, and to allow for the inclusion of RL2 rings in the HW
image, the TOR_VERSION has been updated to version 6 which will
allow for RL2 support in the ring ID metadata files.

p9_setup_sbe_config is updated to write the RISK_LEVEL value into
scratch 3 bits 28:31, and deprecate the existing mailbox.

RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's
only function is to seed mailboxes which are empty via the
attribute state present in the SEEPROM.  Since RISK_LEVEL is zero
at image build time, and explicitly cleared as a result of every
customization, there's logically no need to process the RISK_LEVEL
here.

PPE changes to accomodate the new RISK_LEVEL mailbox
location need to be implemented in the PLAT code: src/hwpf/target.C

Key_Cronus_Test=XIP_REGRESS

HW-ImageBuild-Preqeq=52659
- 52659 must be fully merged in Cronus and HB before this commit
  (53292) can be merged. This is to avoid a Coreq situation.

CQ: SW416424
cmvc-prereq: 1046058
cmvc-prereq: 1043606
cmvc-prereq: 1045920
Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53322

1 files changed, 2 insertions, 2 deletions

diff --git a/src/hwpf/plat_ring_traverse.C b/src/hwpf/plat_ring_traverse.C
index 0056cb6b..6fc31309 100644
--- a/src/hwpf/plat_ring_traverse.C
+++ b/src/hwpf/plat_ring_traverse.C
@@ -34,7 +34,7 @@
 // SEEPROM start address
 const uint32_t g_seepromAddr = SBE_SEEPROM_BASE_ORIGIN;
 const uint32_t CACHE_CONTAINED_MODE = 4;
-const uint32_t RISK_LEVEL_MODE = 1;
+const uint32_t RISK_LEVEL_ZERO = 0;
 #define CACHE_CONTAINED_MODE_OFFSET_IN_TOR 1
 #define RISK_LEVEL_MODE_OFFSET_IN_TOR      2
 #define OVERRIDE_VARIANT_SIZE 1
@@ -468,7 +468,7 @@ fapi2::ReturnCode getRS4ImageFromTor(
                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> (),
                               l_riskLevel);
 
-                if((RISK_LEVEL_MODE == l_riskLevel) &&
+                if((RISK_LEVEL_ZERO != l_riskLevel) &&
                    *(l_ringTorAddr + l_RL_offset))
                 {
                     l_ringTorAddr += l_RL_offset;