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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-10-25 11:29:50 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-10-26 20:37:39 -0400 |
| commit | 2d59a2b4714803ba4c2c610f94a174f3f41fc6fc (patch) | |
| tree | 9cc96ae28b792f5b837946c43b5d6232ebd6dd7f /src/build | |
| parent | 0dbc6004c009d3221ac8e7ea74b0c7582d3da6ca (diff) | |
| download | talos-sbe-2d59a2b4714803ba4c2c610f94a174f3f41fc6fc.tar.gz talos-sbe-2d59a2b4714803ba4c2c610f94a174f3f41fc6fc.zip | |
p9_hcd_core_startclocks -- set CPLT_CONF0 system/group/chip ID fields
required to configure the PIR SPR correctly on multi-socket systems
Change-Id: Iadfcd5bd52e1ea1914de98c6a76e36a9f5d2e36a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31795
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31798
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/build')
0 files changed, 0 insertions, 0 deletions
