RTC: 130392

Add infrastructure for SBE-Host interface

Change-Id: I99ea38b8c8cb5e0d450e8f0011703051d4573055
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/11681
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

16 files changed, 914 insertions, 124 deletions

diff --git a/sbe/sbefw/pk_app_cfg.h b/sbe/sbefw/pk_app_cfg.h
index 970c70e3..36f8b775 100644
--- a/sbe/sbefw/pk_app_cfg.h
+++ b/sbe/sbefw/pk_app_cfg.h
@@ -23,6 +23,7 @@
     SBE_IRQ_DRTM_REQ            STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
     SBE_IRQ_SBEFIFO_RESET       STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
     SBE_IRQ_SBEFIFO_DATA        STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
+    SBE_IRQ_HOST_PSU_INTR       STD_IRQ_TYPE_LEVEL   STD_IRQ_POLARITY_RISING    STD_IRQ_MASKED \
 
 
 /*
@@ -31,7 +32,6 @@
  */
 #define APPCFG_IRQ_INVALID_MASK \
 (\
-   STD_IRQ_MASK64(SBE_IRQ_RESERVED_7) |  \
    STD_IRQ_MASK64(SBE_IRQ_RESERVED_8) |  \
    STD_IRQ_MASK64(SBE_IRQ_RESERVED_9) |  \
    STD_IRQ_MASK64(SBE_IRQ_RESERVED_10) |  \
diff --git a/sbe/sbefw/sbeFifoMsgUtils.H b/sbe/sbefw/sbeFifoMsgUtils.H
index d0e6f098..472e9cd1 100644
--- a/sbe/sbefw/sbeFifoMsgUtils.H
+++ b/sbe/sbefw/sbeFifoMsgUtils.H
@@ -86,9 +86,9 @@ extern uint32_t sbeDownFifoEnq_mult (uint32_t        &io_len,
   */
 extern inline uint32_t sbeBuildRespHeaderMagicCodeCmdClass (void)
 {
-    return ( (0xC0DE0000 ) |
-             (uint32_t)(g_sbeCmdHdr.cmdClass << 8) |
-             (uint32_t)(g_sbeCmdHdr.command ));
+    return ( (0xC0DE0000) |
+             (uint32_t)(g_sbeFifoCmdHdr.cmdClass << 8) |
+             (uint32_t)(g_sbeFifoCmdHdr.command));
 }
 
 /**
diff --git a/sbe/sbefw/sbeHostMsg.H b/sbe/sbefw/sbeHostMsg.H
new file mode 100644
index 00000000..a3632908
--- /dev/null
+++ b/sbe/sbefw/sbeHostMsg.H
@@ -0,0 +1,108 @@
+/*
+ * @file: ppe/sbe/sbefw/sbeHostMsg.H
+ *
+ * @brief This file contains the message structures for SBE Host
+ *        communication.
+ *
+ */
+
+#ifndef __SBEFW_SBEHOST_MSG_H
+#define __SBEFW_SBEHOST_MSG_H
+
+#include <stdint.h>
+#include "sbe_host_intf.H"
+
+/*****************************************************************/
+/*            SBE->PSU request structures                        */
+/*****************************************************************/
+
+/**
+  * @brief structure for Host->SBE command request format denoting
+  *        mininum header (as of now, contained in mbx 0)
+  */
+typedef struct
+{
+    // mbxReg0
+    uint64_t  res:16;
+    uint64_t  flags:16;
+    uint64_t  seqID:16;
+    uint64_t  cmdClass:8;
+    uint64_t  command:8;
+
+    /**
+      * @brief initialize the fields contained in PSU Mbx0
+      *
+      */
+    void init()
+    {
+        res       = 0;
+        flags     = 0;
+        seqID     = 0;
+        cmdClass  = SBE_PSU_CMD_CLASS_UNKNOWN;
+        command   = SBE_PSU_CMD_UNKNOWN;
+    }
+} sbePsu2SbeCmdReqHdr_t;
+
+extern sbePsu2SbeCmdReqHdr_t g_sbePsu2SbeCmdReqHdr;
+
+
+/*****************************************************************/
+/*            SBE->PSU response structures                       */
+/*****************************************************************/
+
+/**
+  * @brief SBE->Host Generic response structure
+  *
+  */
+typedef struct
+{
+    uint64_t mbxReg4;
+    uint64_t mbxReg5;
+    uint64_t mbxReg6;
+    uint64_t mbxReg7;
+} sbeSbe2PsuGenericResp_t ;
+
+/**
+  * @brief Structure for SBE->Host response header contained in
+  *        mbx4 register
+  *
+  */
+typedef struct
+{
+    // mbxReg 4
+    uint64_t  primStatus:16;
+    uint64_t  secStatus:16;
+    uint64_t  seqID:16;
+    uint64_t  cmdClass:8;
+    uint64_t  command:8;
+
+    /**
+      * @brief set the primary and secondary status
+      *
+      * @param[in] i_prim  Primary status
+      * @param[in] i_sec   Secondary status
+      *
+      */
+    void setStatus(const uint16_t i_prim, const uint16_t i_sec)
+    {
+        primStatus = i_prim;
+        secStatus  = i_sec;
+    }
+
+    /**
+      * @brief initialize the response fields contained in PSU Mbx3
+      *
+      */
+    void init()
+    {
+        primStatus   = SBE_PRI_OPERATION_SUCCESSFUL;
+        secStatus    = SBE_SEC_OPERATION_SUCCESSFUL;
+        seqID        = g_sbePsu2SbeCmdReqHdr.seqID;
+        cmdClass     = g_sbePsu2SbeCmdReqHdr.cmdClass;
+        command      = g_sbePsu2SbeCmdReqHdr.command;
+    }
+} sbeSbe2PsuRespHdr_t;
+
+extern sbeSbe2PsuRespHdr_t g_sbeSbe2PsuRespHdr;
+
+#endif // __SBEFW_SBEHOST_MSG_H
diff --git a/sbe/sbefw/sbeHostUtils.C b/sbe/sbefw/sbeHostUtils.C
new file mode 100644
index 00000000..f8622566
--- /dev/null
+++ b/sbe/sbefw/sbeHostUtils.C
@@ -0,0 +1,138 @@
+/*
+ * @file: ppe/sbe/sbefw/sbeHostUtils.C
+ *
+ * @brief This file contains the PSU Access Utility Functions
+ *
+ */
+
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+#include "sbeHostUtils.H"
+#include "sbeHostMsg.H"
+#include "sbe_host_intf.H"
+#include "sbeerrorcodes.H"
+#include "assert.h"
+
+
+
+///////////////////////////////////////////////////////////////////
+// PSU->SBE register access utilities
+///////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////
+uint32_t sbeReadPsu2SbeMbxReg (uint32_t       i_addr,
+                               uint8_t       &io_count,
+                               uint64_t       *o_pData)
+{
+    #define SBE_FUNC " sbeReadPsu2SbeMbxReg "
+    SBE_DEBUG(SBE_FUNC"io_count[0x%02X], i_addr=[0x%08X]", io_count, i_addr);
+
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+    uint8_t  l_count = 0;
+
+    assert((io_count >0 ) && (NULL != o_pData))
+    assert( (SBE_HOST_PSU_MBOX_REG0 <= i_addr) &&
+            (SBE_HOST_PSU_MBOX_REG3 >= (i_addr + io_count - 1)) )
+
+    while (l_count < io_count)
+    {
+        l_rc = getscom_abs ( i_addr,
+                    reinterpret_cast<uint64_t*>(&o_pData[l_count]) );
+
+        if (l_rc)
+        {
+            // Error while reading from PSU->SBE mbx register
+            SBE_ERROR(SBE_FUNC"getscom_abs failed,"
+                         "l_rc=[0x%08X], i_addr=[0x%08X]",
+                         l_rc, i_addr);
+            break;
+        }
+
+        SBE_DEBUG(SBE_FUNC"l_data=[0x%016X]", o_pData[l_count]);
+        ++l_count;
+        ++i_addr;
+    }
+
+    // Indicate the number of Mbx registers read off
+    io_count = l_count;
+    return l_rc;
+
+    #undef SBE_FUNC
+}
+
+///////////////////////////////////////////////////////////////////
+// SBE->PSU register access utilities
+///////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////
+uint32_t sbeIntrHostUponRespWaiting ()
+{
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    // Interrupt the host by setting bit0 in SBE->PSU DB register
+    // if the caller requested for it.
+    if (g_sbePsu2SbeCmdReqHdr.flags & SBE_PSU_FLAGS_RESP_REQUIRED)
+    {
+        l_rc = sbeSetSbe2PsuDbBitX(SBE_SBE2PSU_DOORBELL_SET_BIT0);
+    }
+    return l_rc;
+}
+
+///////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////
+uint32_t sbeAcknowledgeHost ()
+{
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    // Set the Ack bit in SBE->PSU DB register
+    // if the caller requested for it.
+    if (g_sbePsu2SbeCmdReqHdr.flags & SBE_PSU_FLAGS_ACK_REQUIRED)
+    {
+        l_rc = sbeSetSbe2PsuDbBitX(SBE_SBE2PSU_DOORBELL_SET_BIT1);
+    }
+    return l_rc;
+}
+
+///////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////
+uint32_t sbeWriteSbe2PsuMbxReg (uint32_t        i_addr,
+                                const uint64_t  *i_pData,
+                                uint8_t         &io_count)
+{
+    #define SBE_FUNC " sbeWriteSbe2PsuMbxReg "
+    SBE_DEBUG(SBE_FUNC"io_count[0x%02X], i_addr=[0x%08X]", io_count, i_addr);
+    uint32_t  l_rc   = SBE_SEC_OPERATION_SUCCESSFUL;
+    uint8_t   l_count = 0;
+
+    assert( ((io_count >0 ) && (NULL != i_pData)) || (io_count = 0) )
+    assert( (SBE_HOST_PSU_MBOX_REG4 <= i_addr) &&
+            (SBE_HOST_PSU_MBOX_REG7 >= (i_addr + io_count - 1)) )
+
+    while ( (g_sbePsu2SbeCmdReqHdr.flags & SBE_PSU_FLAGS_RESP_REQUIRED) &&
+            (l_count < io_count) )
+    {
+        SBE_DEBUG(SBE_FUNC"l_data=[0x%016X]", *(i_pData+l_count));
+
+        l_rc = putscom_abs ( i_addr, *(i_pData+l_count) );
+
+        if (l_rc)
+        {
+            // Error while reading from PSU->SBE mbx register
+            SBE_ERROR(SBE_FUNC"putscom_abs failed,"
+                         "l_rc=[0x%08X], i_addr=[0x%08X]",
+                         l_rc, i_addr);
+            break;
+        }
+
+        ++l_count;
+        ++i_addr;
+    }
+
+    // Indicate the number of Mbx registers written into
+    io_count = l_count;
+    return l_rc;
+
+    #undef SBE_FUNC
+}
diff --git a/sbe/sbefw/sbeHostUtils.H b/sbe/sbefw/sbeHostUtils.H
new file mode 100644
index 00000000..e4e6e211
--- /dev/null
+++ b/sbe/sbefw/sbeHostUtils.H
@@ -0,0 +1,202 @@
+/*
+ * @file: ppe/sbe/sbefw/sbeHostUtils.H
+ *
+ * @brief This file contains basic SBE PSU hardware specific
+ *        definitions and operations.
+ *
+ */
+
+#ifndef __SBEFW_SBEHOSTUTILS_H
+#define __SBEFW_SBEHOSTUTILS_H
+
+#include <stdint.h>
+#include "ppe42_scom.h"
+
+/**
+  * @brief SBE PSU Access register addresses
+  *
+  */
+const uint32_t SBE_HOST_PSU_BASE                 = 0x000D0050;
+
+const uint32_t SBE_HOST_PSU_MBOX_REG0            = SBE_HOST_PSU_BASE + 0x0000;
+const uint32_t SBE_HOST_PSU_MBOX_REG1            = SBE_HOST_PSU_BASE + 0x0001;
+const uint32_t SBE_HOST_PSU_MBOX_REG2            = SBE_HOST_PSU_BASE + 0x0002;
+const uint32_t SBE_HOST_PSU_MBOX_REG3            = SBE_HOST_PSU_BASE + 0x0003;
+const uint32_t SBE_HOST_PSU_MBOX_REG4            = SBE_HOST_PSU_BASE + 0x0004;
+const uint32_t SBE_HOST_PSU_MBOX_REG5            = SBE_HOST_PSU_BASE + 0x0005;
+const uint32_t SBE_HOST_PSU_MBOX_REG6            = SBE_HOST_PSU_BASE + 0x0006;
+const uint32_t SBE_HOST_PSU_MBOX_REG7            = SBE_HOST_PSU_BASE + 0x0007;
+
+
+const uint32_t SBE_PSU2SBE_DOORBELL_REG_RW       = 0x000D0060;
+const uint32_t SBE_PSU2SBE_DOORBELL_REG_AND      = 0x000D0061;
+const uint32_t SBE_PSU2SBE_DOORBELL_REG_OR       = 0x000D0062;
+const uint32_t SBE_PSU2HOST_DOORBELL_REG_RW       = 0x000D0063;
+const uint32_t SBE_PSU2HOST_DOORBELL_REG_AND      = 0x000D0064;
+const uint32_t SBE_PSU2HOST_DOORBELL_REG_OR       = 0x000D0065;
+
+
+/**
+  * @brief SBE PSU door bell register Bit definitions
+  */
+typedef enum
+{
+    // Bit 0 AND flag for PSU->SBE Doorbell Register;
+    // When this is set by the host firmware, it would trigger an
+    // interrupt to the SBE about a waiting message in the Host/SBE
+    // Mailbox Registers. SBE is responsible for clearing this
+    // bit upon being interrupted.
+    SBE_PSU2SBE_DOORBELL_CLEAR_BIT0      = 0x7FFFFFFFFFFFFFFFull,
+} sbe_psu2sbeDoorbellReg_UpdateFlags;
+
+typedef enum
+{
+    // Bit 0 OR flag for SBE->PSU Doorbell Register;
+    // When this is set by SBE, it would trigger an interrupt to host
+    // firmware about a waiting response in the Host/SBE Mailbox Registers 4-7
+    SBE_SBE2PSU_DOORBELL_SET_BIT0      = 0x8000000000000000ull,
+
+    // Bit 1 OR flag for SBE->PSU Doorbell Register;
+    // When this is set by SBE, it would trigger an interrupt to host
+    // firmware indicating that the message in Host/SBE mailbox registers 0-3
+    // has been read by SBE and is being processed
+    SBE_SBE2PSU_DOORBELL_SET_BIT1      = 0x4000000000000000ull,
+
+    // Bit 2 OR flag for SBE->PSU Doorbell Register;
+    // When this is set by SBE, it would trigger an interrupt to host
+    // firmware to trigger Stop15 exit on thread 0 on the master core.
+    // This would be used to trigger hostboot in istep 16
+    SBE_SBE2PSU_DOORBELL_SET_BIT2      = 0x2000000000000000ull,
+} sbe_sbe2psuDoorbellReg_UpdateFlags;
+
+
+/*****************************************************************/
+/** PSU->SBE register access utilities **/
+/*****************************************************************/
+
+/**
+  * @brief sbeClearPsu2SbeDbBitX : Clear given bit in PSU->SBE DB register
+  *
+  * @param[in] 64-Bit Scom Data indicating bit position to be cleared
+  *
+  * @return    RC from the underlying scom utility
+  *
+  */
+inline uint32_t sbeClearPsu2SbeDbBitX (const uint64_t i_bit)
+{
+    return putscom_abs (SBE_PSU2SBE_DOORBELL_REG_AND, i_bit) ;
+}
+
+
+/**
+  * @brief sbeReadPsu2SbeDbReg : Read PSU->SBE DB register
+  *
+  * @param[out] 64-Bit Data read from PSU->SBE DB register
+  *
+  * @return     RC from the underlying scom utility
+  *
+  */
+inline uint32_t sbeReadPsu2SbeDbReg (uint64_t *o_data)
+{
+    return getscom_abs (SBE_PSU2SBE_DOORBELL_REG_RW, o_data) ;
+}
+
+
+/**
+  * @brief sbeReadPsu2SbeMbxReg : Read from PSU->SBE MBX register(s)
+  *
+  * @param[in]     i_addr
+  *    Starting Mbx Register Address
+  * @param[in/out] io_count
+  *    On input:  Number of Mbx registers to be read.
+  *    On output: Number of Mbx registers read.
+  * @param[out]    o_pData
+  *    Contents of the Mbx registers read into the buffer
+  * @return  Return Code
+  *    SUCCESS or TBD
+  */
+uint32_t sbeReadPsu2SbeMbxReg (uint32_t       i_addr,
+                               uint8_t        &io_count,
+                               uint64_t       *o_pData);
+
+/*****************************************************************/
+/** SBE->PSU register access utilities **/
+/*****************************************************************/
+
+/**
+  * @brief sbeSetSbe2PsuDbBitX : Set Bit-X in SBE->PSU DB register
+  *
+  * @param[in] 64-Bit Scom Data indicating bit position
+  *
+  * @return    RC from the underlying scom utility
+  *
+  */
+inline uint32_t sbeSetSbe2PsuDbBitX (const uint64_t i_bit)
+{
+    return putscom_abs (SBE_PSU2HOST_DOORBELL_REG_OR, i_bit) ;
+}
+
+/**
+  * @brief sbeClearSbe2PsuDbBitX : Clear Bit-X in SBE->PSU DB register
+  *
+  * @param[in] 64-Bit Scom Data indicating bit position
+  *
+  * @return    RC from the underlying scom utility
+  *
+  */
+inline uint32_t sbeClearSbe2PsuDbBitX (const uint64_t i_bit)
+{
+    return putscom_abs (SBE_PSU2HOST_DOORBELL_REG_AND, i_bit) ;
+}
+
+/**
+  * @brief sbeReadSbe2PsuDbReg : Read SBE->PSU DB register
+  *
+  * @param[out] 64-Bit Data read from SBE->PSU DB register
+  *
+  * @return     RC from the underlying scom utility
+  *
+  */
+inline uint32_t sbeReadSbe2PsuDbReg (uint64_t *o_data)
+{
+    return getscom_abs (SBE_PSU2HOST_DOORBELL_REG_RW, o_data) ;
+}
+
+/**
+  * @brief sbeAcknowledgeHost : Acknowldge by setting bit 1 in
+  *      SBE->PSU DB register if the host had requested for an ack
+  *
+  * @return    RC from the underlying scom utility
+  *
+  */
+uint32_t sbeAcknowledgeHost();
+
+/**
+  * @brief sbeIntrHostUponRespWaiting : Interrupt Host by
+  *      setting bit 0 in SBE->PSU DB register if the host had
+  *      requested for response
+  *
+  * @return    RC from the underlying scom utility
+  *
+  */
+uint32_t sbeIntrHostUponRespWaiting();
+
+
+/**
+  * @brief sbeWriteSbe2PsuMbxReg : Write to SBE->PSU MBX register(s)
+  *
+  * @param[in]     i_addr
+  *    Starting Mbx Register Address
+  * @param[in]     i_pData
+  *    Contains the data to be written into given Mbx registers
+  * @param[in/out] io_count
+  *    On input:  Number of Mbx registers to be written.
+  *    On output: Number of Mbx registers written.
+  * @return  Return Code
+  *    SUCCESS or TBD
+  */
+uint32_t sbeWriteSbe2PsuMbxReg (uint32_t        i_addr,
+                                const uint64_t  *i_pData,
+                                uint8_t         &io_count);
+
+#endif // __SBEFW_SBEHOSTUTILS_H
diff --git a/sbe/sbefw/sbeSpMsg.H b/sbe/sbefw/sbeSpMsg.H
index 8c021184..a60ae274 100644
--- a/sbe/sbefw/sbeSpMsg.H
+++ b/sbe/sbefw/sbeSpMsg.H
@@ -31,9 +31,9 @@ typedef struct
     uint32_t reserved:16;
     uint32_t cmdClass:8;
     uint32_t command:8;
-}sbeCmdReqBuf_t;
+}sbeFifoCmdReqBuf_t;
 
-extern sbeCmdReqBuf_t g_sbeCmdHdr;
+extern sbeFifoCmdReqBuf_t g_sbeFifoCmdHdr;
 
 /**
   * @brief structure for generic header for fifo response.
@@ -65,15 +65,15 @@ typedef struct
       * @brief set initial values for response header
       *
       * @note  We did not set this in constructor as based on use case
-      *        it is possible that g_sbeCmdHdr does not have proper
+      *        it is possible that g_sbeFifoCmdHdr does not have proper
       *        values at time of object creation.
       *
       */
     void init()
     {
         magicCode = 0xC0DE;
-        cmdClass  = g_sbeCmdHdr.cmdClass;
-        command = g_sbeCmdHdr.command;
+        cmdClass  = g_sbeFifoCmdHdr.cmdClass;
+        command = g_sbeFifoCmdHdr.command;
         primaryStatus = SBE_PRI_OPERATION_SUCCESSFUL;
         secondaryStatus = SBE_SEC_OPERATION_SUCCESSFUL;
     }
diff --git a/sbe/sbefw/sbe_host_intf.H b/sbe/sbefw/sbe_host_intf.H
new file mode 100644
index 00000000..d6263645
--- /dev/null
+++ b/sbe/sbefw/sbe_host_intf.H
@@ -0,0 +1,50 @@
+/*
+ * @file: ppe/sbe/sbefw/sbe_host_intf.H
+ *
+ * @brief This file contains the Host-SBE interface protocol common details
+ */
+
+#ifndef __SBEFW_SBE_HOST_INTF_H
+#define __SBEFW_SBE_HOST_INTF_H
+
+#include <stdint.h>
+
+/**
+ * $Version: Conforms to HOST-SBE Interface Spec v0.5a
+ */
+
+/*
+ * Constants for SBE FW major and minor number
+ */
+static const uint16_t SBE_SBEFW_HOST_MAJOR_VERSION = 1;
+static const uint16_t SBE_SBEFW_HOST_MINOR_VERSION = 0;
+
+/**
+  * @brief enums for SBE-Host interface command class
+  */
+enum sbePsuCommandClass
+ {
+    SBE_PSU_CMD_CLASS_UNKNOWN      = 0,
+    SBE_PSU_CMD_CLASS_CORE_STATE   = 0xD1,
+ };
+
+/**
+  * @brief enums for SBE-Host interface core state control commands
+  */
+enum sbePsuCoreStateControlCommands
+{
+    SBE_PSU_CMD_CONTROL_DEADMAN    = 0x01,
+    SBE_PSU_CMD_UNKNOWN            = 0xFF,
+};
+
+/**
+  * @brief enums denoting control flags
+  *
+  */
+enum sbePsuControlFlags
+{
+    SBE_PSU_FLAGS_RESP_REQUIRED   = 0x0100,
+    SBE_PSU_FLAGS_ACK_REQUIRED    = 0x0200,
+};
+
+#endif // __SBEFW_SBE_HOST_INTF_H
diff --git a/sbe/sbefw/sbecmdcntrldmt.C b/sbe/sbefw/sbecmdcntrldmt.C
new file mode 100644
index 00000000..8c6178d6
--- /dev/null
+++ b/sbe/sbefw/sbecmdcntrldmt.C
@@ -0,0 +1,26 @@
+/*
+ * @file: ppe/sbe/sbefw/sbecmdcntrldmt.C
+ *
+ * @brief This file contains the Core State Control Messages
+ *
+ */
+
+#include "sbecmdcntrldmt.H"
+#include "sbefifo.H"
+#include "sbetrace.H"
+#include "sbe_sp_intf.H"
+#include "sbe_build_info.H"
+#include "sbeFifoMsgUtils.H"
+#include "sbeHostMsg.H"
+
+/////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////
+uint32_t sbeControlDeadmanTimer (uint8_t *i_pArg)
+{
+    #define SBE_FUNC "sbeControlDeadmanTimer"
+    SBE_DEBUG(SBE_FUNC);
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    return rc;
+    #undef SBE_FUNC
+}
diff --git a/sbe/sbefw/sbecmdcntrldmt.H b/sbe/sbefw/sbecmdcntrldmt.H
new file mode 100644
index 00000000..be017f13
--- /dev/null
+++ b/sbe/sbefw/sbecmdcntrldmt.H
@@ -0,0 +1,23 @@
+/*
+ * @file: ppe/sbe/sbefw/sbecmdcntrldmt.H
+ *
+ * @brief This file contains the Core State Control Messages API header
+ *
+ */
+
+#ifndef __SBEFW_SBECMDCNTRLDMT_H
+#define __SBEFW_SBECMDCNTRLDMT_H
+
+#include <stdint.h>
+
+
+/**
+  * @brief Control Deadman Timer command (0xD101)
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    RC from the PSU access utility
+  */
+uint32_t sbeControlDeadmanTimer(uint8_t *i_pArg);
+
+#endif // __SBEFW_SBECMDCNTRLDMT_H
diff --git a/sbe/sbefw/sbecmdparser.C b/sbe/sbefw/sbecmdparser.C
index 9d20d099..873d0986 100644
--- a/sbe/sbefw/sbecmdparser.C
+++ b/sbe/sbefw/sbecmdparser.C
@@ -10,9 +10,11 @@
 #include "sbecmdiplcontrol.H"
 #include "sbecmdgeneric.H"
 #include "sbecmdmemaccess.H"
+#include "sbecmdcntrldmt.H"
 #include "sbetrace.H"
 #include "sbe_sp_intf.H"
-
+#include "sbeHostMsg.H"
+#include "sbe_host_intf.H"
 
 ////////////////////////////////////////////////////////////////
 // @brief g_sbeScomCmdArray
@@ -99,6 +101,17 @@ static sbeCmdStruct_t g_sbeMemoryAccessCmdArray [] =
     },
 };
 
+//////////////////////////////////////////////////////////////
+// @brief g_sbeCoreStateControlCmdArray
+//
+//////////////////////////////////////////////////////////////
+static sbeCmdStruct_t g_sbeCoreStateControlCmdArray [] =
+{
+    {sbeControlDeadmanTimer,
+     SBE_PSU_CMD_CONTROL_DEADMAN,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+};
 
 ////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////
@@ -112,6 +125,7 @@ uint8_t sbeGetCmdStructAttr (const uint8_t  i_cmdClass,
 
     switch(i_cmdClass)
     {
+        // FIFO Commands
         case SBE_CMD_CLASS_IPL_CONTROL:
             // @TODO via RTC : 128655
             //       Use C++ style typecase
@@ -136,6 +150,13 @@ uint8_t sbeGetCmdStructAttr (const uint8_t  i_cmdClass,
             *o_ppCmd  = (sbeCmdStruct_t*)g_sbeMemoryAccessCmdArray;
             break;
 
+        // PSU Commands
+        case SBE_PSU_CMD_CLASS_CORE_STATE:
+            l_numCmds = sizeof(g_sbeCoreStateControlCmdArray) /
+                        sizeof(sbeCmdStruct_t);
+            *o_ppCmd  = (sbeCmdStruct_t*)g_sbeCoreStateControlCmdArray;
+            break;
+
         // This will grow with each class of chipOp in future
         default:
                 break;
diff --git a/sbe/sbefw/sbecmdprocessor.C b/sbe/sbefw/sbecmdprocessor.C
index d868174b..cf42865b 100644
--- a/sbe/sbefw/sbecmdprocessor.C
+++ b/sbe/sbefw/sbecmdprocessor.C
@@ -15,89 +15,98 @@
 #include "assert.h"
 #include "sbeFifoMsgUtils.H"
 #include "sbeerrorcodes.H"
+#include "sbeHostUtils.H"
+#include "sbeHostMsg.H"
 
-//////////////////////////////////////////////////////
-//////////////////////////////////////////////////////
-void sbeSyncCommandProcessor_routine(void *i_pArg)
+
+/////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////
+void sbeHandlePsuResponse (const uint32_t i_rc)
 {
-    #define SBE_FUNC " sbeSyncCommandProcessor_routine "
+    #define SBE_FUNC " sbeHandlePsuResponse "
     SBE_ENTER(SBE_FUNC);
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
 
     do
     {
-        uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
-        uint16_t l_primStatus = SBE_PRI_OPERATION_SUCCESSFUL;
-
-        // Wait for new command processing
-        int l_rcPk = pk_semaphore_pend (
-                    &g_sbeSemCmdProcess, PK_WAIT_FOREVER);
-
-        do
+        uint8_t  l_count = 0;
+        switch (i_rc)
         {
-            l_primStatus = g_sbeCmdRespHdr.prim_status;
-            l_rc         = g_sbeCmdRespHdr.sec_status;
-
-            SBE_DEBUG (SBE_FUNC"l_primStatus=[0x%04X], l_rc=[0x%04X]",
-                            l_primStatus, l_rc);
-
-            // PK API failure
-            if (l_rcPk != PK_OK)
-            {
-                SBE_ERROR(SBE_FUNC"pk_semaphore_pend failed, "
-                          "l_rcPk=%d, g_sbeSemCmdRecv.count=%d",
-                           l_rcPk, g_sbeSemCmdRecv.count);
+            case SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED:
+            case SBE_SEC_COMMAND_NOT_SUPPORTED:
+                // Caller sent an invalid Command class/opcode
 
-                // if the command receiver thread already updated
-                // the response status codes, don't override them.
-                if (l_primStatus == SBE_PRI_OPERATION_SUCCESSFUL)
+                // Set the Ack bit in SBE->PSU DB register
+                l_rc = sbeAcknowledgeHost();
+                if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc)
                 {
-                    l_primStatus = SBE_PRI_INTERNAL_ERROR;
-                    l_rc         = SBE_SEC_OS_FAILURE;
+                    break;
+                }
+                // Set primary and secondary status
+                g_sbeSbe2PsuRespHdr.setStatus(SBE_PRI_INVALID_COMMAND, i_rc);
+
+                // Now Update SBE->PSU Mbx Reg4 with response
+                l_count = sizeof(g_sbeSbe2PsuRespHdr)/
+                                       sizeof(uint64_t);
+                l_rc = sbeWriteSbe2PsuMbxReg(SBE_HOST_PSU_MBOX_REG4,
+                            reinterpret_cast<const uint64_t *>(
+                                &g_sbeSbe2PsuRespHdr), l_count);
+                if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc)
+                {
+                    break;
                 }
-            }
-
-            SBE_DEBUG(SBE_FUNC"unblocked");
 
-            if (l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
-            {
+                // Interrupt the host indicating about the response
+                // message in SBE->PSU mbx register
+                l_rc = sbeIntrHostUponRespWaiting();
+                if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc)
+                {
+                    break;
+                }
                 break;
-            }
 
-            SBE_DEBUG(SBE_FUNC"New cmd arrived, g_sbeSemCmdProcess.count=%d",
-                         g_sbeSemCmdProcess.count);
+            case SBE_SEC_OPERATION_SUCCESSFUL:
+                // Services code successfully executed the chipOp.
+                SBE_INFO(SBE_FUNC"PSU ChipOp Done");
+                break;
 
-            uint8_t  l_cmdClass  = 0;
-            uint8_t  l_cmdOpCode = 0;
+             default:
+                // The only possibility (as of now) to reach till this point
+                // is when there was a mbx register access (scom) failure
+                // happened. Going to return to the waiting loop.
+                break;
+        }
+    } while(false);
 
-            // @TODO via RTC: 128658
-            //       Review if Mutex protection is required
-            //       for all the globals used between threads
-            l_cmdClass  = g_sbeCmdHdr.cmdClass;
-            l_cmdOpCode = g_sbeCmdHdr.command;
+    SBE_DEBUG(SBE_FUNC"l_rc[0x0%08X]", l_rc);
 
-            // Get the command function
-            sbeCmdFunc_t l_pFuncP = sbeFindCmdFunc (l_cmdClass, l_cmdOpCode) ;
+    #undef SBE_FUNC
+}
 
-            assert( l_pFuncP )
 
-            // Call the ChipOp function
-            l_rc = l_pFuncP ((uint8_t *)i_pArg);
-
-        } while(false); // Inner do..while loop ends here
+/////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////
+void sbeHandleFifoResponse (const uint32_t i_rc)
+{
+    #define SBE_FUNC " sbeHandleFifoResponse "
+    SBE_ENTER(SBE_FUNC);
 
-        SBE_DEBUG(SBE_FUNC"l_rc=[0x%08X]", l_rc);
+    do
+    {
+        uint16_t l_primStatus = SBE_PRI_OPERATION_SUCCESSFUL;
+        uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
 
         // Handle FIFO reset case
-        if (l_rc == SBE_FIFO_RESET_RECEIVED)
+        if (i_rc == SBE_FIFO_RESET_RECEIVED)
         {
             // @TODO via RTC : 126147
             //       Handle FIFO reset flow
             pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
-            continue;
+            break;
         }
 
-        if ( (l_rc == SBE_SEC_UNEXPECTED_EOT_INSUFFICIENT_DATA) ||
-             (l_rc == SBE_SEC_UNEXPECTED_EOT_EXCESS_DATA) )
+        if ( (i_rc == SBE_SEC_UNEXPECTED_EOT_INSUFFICIENT_DATA) ||
+             (i_rc == SBE_SEC_UNEXPECTED_EOT_EXCESS_DATA) )
         {
             l_primStatus = SBE_PRI_INVALID_DATA;
         }
@@ -105,9 +114,9 @@ void sbeSyncCommandProcessor_routine(void *i_pArg)
         uint32_t l_len2dequeue            = 0;
         uint32_t l_dist2StatusHdr         = 0;
         uint32_t l_sbeDownFifoRespBuf[4] = {0};
-        uint32_t l_secStatus = l_rc;
+        uint32_t l_secStatus = i_rc;
 
-        switch (l_rc)
+        switch (i_rc)
         {
             case SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED:
             case SBE_SEC_COMMAND_NOT_SUPPORTED:
@@ -176,11 +185,118 @@ void sbeSyncCommandProcessor_routine(void *i_pArg)
              default:
                 break;
         }
+    } while (false);
+
+    #undef SBE_FUNC
+}
+
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+void sbeSyncCommandProcessor_routine(void *i_pArg)
+{
+    #define SBE_FUNC " sbeSyncCommandProcessor_routine "
+    SBE_ENTER(SBE_FUNC);
+
+    do
+    {
+        uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+        uint16_t l_primStatus = SBE_PRI_OPERATION_SUCCESSFUL;
+
+        // Wait for new command processing
+        int l_rcPk = pk_semaphore_pend (
+                    &g_sbeSemCmdProcess, PK_WAIT_FOREVER);
+
+        do
+        {
+            if ( g_sbeIntrSource.isSet(SBE_INTERFACE_PSU) )
+            {
+                l_primStatus = g_sbeSbe2PsuRespHdr.primStatus;
+                l_rc         = g_sbeSbe2PsuRespHdr.secStatus;
+            }
+            else if ( g_sbeIntrSource.isSet(SBE_INTERFACE_FIFO) )
+            {
+                l_primStatus = g_sbeCmdRespHdr.prim_status;
+                l_rc         = g_sbeCmdRespHdr.sec_status;
+            }
+
+            SBE_DEBUG (SBE_FUNC"l_primStatus=[0x%04X], l_rc=[0x%04X]",
+                            l_primStatus, l_rc);
+
+            // PK API failure
+            if (l_rcPk != PK_OK)
+            {
+                SBE_ERROR(SBE_FUNC"pk_semaphore_pend failed, "
+                          "l_rcPk=%d, g_sbeSemCmdRecv.count=%d",
+                           l_rcPk, g_sbeSemCmdRecv.count);
+
+                // if the command receiver thread already updated
+                // the response status codes, don't override them.
+                if (l_primStatus == SBE_PRI_OPERATION_SUCCESSFUL)
+                {
+                    l_primStatus = SBE_PRI_INTERNAL_ERROR;
+                    l_rc         = SBE_SEC_OS_FAILURE;
+                }
+            }
+
+            SBE_DEBUG(SBE_FUNC"unblocked");
+
+            if (l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
+            {
+                break;
+            }
+
+            SBE_DEBUG(SBE_FUNC"New cmd arrived, g_sbeSemCmdProcess.count=%d",
+                         g_sbeSemCmdProcess.count);
+
+            uint8_t  l_cmdClass  = 0;
+            uint8_t  l_cmdOpCode = 0;
+
+            // @TODO via RTC: 128658
+            //       Review if Mutex protection is required
+            //       for all the globals used between threads
+
+            if ( g_sbeIntrSource.isSet(SBE_INTERFACE_PSU) )
+            {
+                l_cmdClass  = g_sbePsu2SbeCmdReqHdr.cmdClass;
+                l_cmdOpCode = g_sbePsu2SbeCmdReqHdr.command;
+            }
+            else if (  g_sbeIntrSource.isSet(SBE_INTERFACE_FIFO) )
+            {
+                l_cmdClass  = g_sbeFifoCmdHdr.cmdClass;
+                l_cmdOpCode = g_sbeFifoCmdHdr.command;
+            }
+
+            // Get the command function
+            sbeCmdFunc_t l_pFuncP = sbeFindCmdFunc (l_cmdClass, l_cmdOpCode) ;
+
+            assert( l_pFuncP )
+
+            // Call the ChipOp function
+            l_rc = l_pFuncP ((uint8_t *)i_pArg);
+
+        } while(false); // Inner do..while loop ends here
+
+        SBE_DEBUG(SBE_FUNC"l_rc=[0x%08X]", l_rc);
+        if ( g_sbeIntrSource.isSet(SBE_INTERFACE_PSU) )
+        {
+            sbeHandlePsuResponse (l_rc);
+
+            // Enable Host interrupt
+            g_sbeIntrSource.clearIntrSource(SBE_INTERFACE_PSU);
+            pk_irq_enable(SBE_IRQ_HOST_PSU_INTR);
+        }
+        else if ( g_sbeIntrSource.isSet(SBE_INTERFACE_FIFO) )
+        {
+            sbeHandleFifoResponse (l_rc);
 
-        // @TODO via RTC : 126147
-        //       Review all the scenarios
-        // Enable the new data available interrupt
-        pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+            // @TODO via RTC : 126147
+            //       Review all the scenarios
+
+            // Enable the new data available interrupt
+            g_sbeIntrSource.clearIntrSource(SBE_INTERFACE_FIFO);
+            pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+        }
 
     } while(true); // Thread always exists
 }
diff --git a/sbe/sbefw/sbecmdreceiver.C b/sbe/sbefw/sbecmdreceiver.C
index 8474d8d3..93af6005 100644
--- a/sbe/sbefw/sbecmdreceiver.C
+++ b/sbe/sbefw/sbecmdreceiver.C
@@ -14,9 +14,14 @@
 #include "sbe_sp_intf.H"
 #include "sbeFifoMsgUtils.H"
 #include "sbeerrorcodes.H"
+#include "sbeHostMsg.H"
+#include "sbeHostUtils.H"
 
-sbeCmdReqBuf_t g_sbeCmdHdr;
+sbeFifoCmdReqBuf_t g_sbeFifoCmdHdr;
 sbeCmdRespHdr_t g_sbeCmdRespHdr;
+sbePsu2SbeCmdReqHdr_t g_sbePsu2SbeCmdReqHdr;
+sbeSbe2PsuRespHdr_t g_sbeSbe2PsuRespHdr;
+sbeIntrHandle_t g_sbeIntrSource ;
 
 //////////////////////////////////////////////////////
 //////////////////////////////////////////////////////
@@ -36,7 +41,7 @@ void sbeCommandReceiver_routine(void *i_pArg)
         // @TODO via RTC: 128944
         //       Read Scratchpad
 
-        // Wait for new data in FIFO or FIFO reset interrupt
+        // Wait for new data in FIFO or FIFO reset interrupt or PSU interrupt
         int l_rcPk = pk_semaphore_pend (&g_sbeSemCmdRecv, PK_WAIT_FOREVER);
 
         // @TODO via RTC: 128658
@@ -44,11 +49,15 @@ void sbeCommandReceiver_routine(void *i_pArg)
         //       for all the globals used between threads
         g_sbeCmdRespHdr.prim_status = SBE_PRI_OPERATION_SUCCESSFUL;
         g_sbeCmdRespHdr.sec_status  = SBE_SEC_OPERATION_SUCCESSFUL;
-        g_sbeCmdHdr.cmdClass = SBE_CMD_CLASS_UNKNOWN;
+        g_sbeFifoCmdHdr.cmdClass = SBE_CMD_CLASS_UNKNOWN;
+        g_sbePsu2SbeCmdReqHdr.init();
 
         // inner loop for command handling
         do
         {
+            uint8_t l_cmdClass = SBE_CMD_CLASS_UNKNOWN;
+            uint8_t l_command  = 0xFF;
+
             // pk API failure
             if (l_rcPk != PK_OK)
             {
@@ -57,14 +66,32 @@ void sbeCommandReceiver_routine(void *i_pArg)
 
             SBE_DEBUG(SBE_FUNC"unblocked");
 
-            // @TODO via RTC: 128943
-            //       Host services / OPAL handling
-
-            // @TODO via RTC: 128945
-            // Handle protocol violation if needed (a long term goal)
+            // The responsibility of this thread is limited to reading off
+            // the FIFO or PSU interfaces to be able to decode the command
+            // class and the command opcode parameters.
 
-            // The responsibility of this thread is limited to dequeueing
-            // only the first two word entries from the protocol header.
+            // Received PSU interrupt
+            if ( g_sbeIntrSource.isSet(SBE_INTERFACE_PSU) )
+            {
+                // First clear PSU->SBE DB bit 0
+                l_rc = sbeClearPsu2SbeDbBitX(SBE_PSU2SBE_DOORBELL_CLEAR_BIT0);
+                if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc)
+                {
+                    break;
+                }
+
+                // Read the request field from PSU->SBE Mbx Reg0
+                uint8_t l_count = sizeof(g_sbePsu2SbeCmdReqHdr)/
+                                  sizeof(uint64_t);
+                l_rc = sbeReadPsu2SbeMbxReg (SBE_HOST_PSU_MBOX_REG0,
+                              l_count, (uint64_t *)&g_sbePsu2SbeCmdReqHdr);
+                g_sbeSbe2PsuRespHdr.init();
+                l_cmdClass  = g_sbePsu2SbeCmdReqHdr.cmdClass;
+                l_command   = g_sbePsu2SbeCmdReqHdr.command;
+            } // end if loop for PSU interface chipOp handling
+
+            // Received FIFO interrupt
+            else if (  g_sbeIntrSource.isSet(SBE_INTERFACE_FIFO) ) {
 
             // This thread will attempt to unblock the command processor
             // thread on the following scenarios:
@@ -78,8 +105,10 @@ void sbeCommandReceiver_routine(void *i_pArg)
             // and g_sbeCmdRespHdr.sec_status for command processor thread
             // to handle them later in the sequence.
 
-            uint32_t len = sizeof( g_sbeCmdHdr)/ sizeof(uint32_t);
-            l_rc = sbeUpFifoDeq_mult ( len, (uint32_t *)&g_sbeCmdHdr, false );
+            l_cmdClass  = SBE_CMD_CLASS_UNKNOWN;
+            uint32_t len = sizeof(g_sbeFifoCmdHdr)/sizeof(uint32_t);
+            l_rc = sbeUpFifoDeq_mult ( len, (uint32_t *)&g_sbeFifoCmdHdr,
+                                       false );
 
             // If FIFO reset is requested,
             if (l_rc == SBE_FIFO_RESET_RECEIVED)
@@ -112,25 +141,34 @@ void sbeCommandReceiver_routine(void *i_pArg)
                 break;
             }
 
+            l_cmdClass  = g_sbeFifoCmdHdr.cmdClass;
+            l_command   = g_sbeFifoCmdHdr.command;
+
+            } // end else if loop for FIFO interface chipOp handling
+
             // Any other FIFO access issue
             if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
             {
-                SBE_ERROR(SBE_FUNC"sbeUpFifoDeq_mult failue, "
-                          "l_rc=[0x%08X]", l_rc);
                 break;
             }
 
             // validate the command class and sub-class opcodes
-            l_rc = sbeValidateCmdClass (
-                        g_sbeCmdHdr.cmdClass,
-                        g_sbeCmdHdr.command ) ;
+            l_rc = sbeValidateCmdClass (l_cmdClass, l_command) ;
 
             if (l_rc)
             {
                 // Command Validation failed;
                 SBE_ERROR(SBE_FUNC"Command validation failed");
-                g_sbeCmdRespHdr.prim_status = SBE_PRI_INVALID_COMMAND;
-                g_sbeCmdRespHdr.sec_status  = l_rc;
+                if (  g_sbeIntrSource.isSet(SBE_INTERFACE_PSU) )
+                {
+                    g_sbeSbe2PsuRespHdr.primStatus = SBE_PRI_INVALID_COMMAND;
+                    g_sbeSbe2PsuRespHdr.secStatus  = l_rc;
+                }
+                else if (  g_sbeIntrSource.isSet(SBE_INTERFACE_FIFO) )
+                {
+                    g_sbeCmdRespHdr.prim_status = SBE_PRI_INVALID_COMMAND;
+                    g_sbeCmdRespHdr.sec_status  = l_rc;
+                }
 
                 // Reassign l_rc to Success to Unblock command processor
                 // thread and let that take the necessary action.
@@ -153,7 +191,7 @@ void sbeCommandReceiver_routine(void *i_pArg)
         if ((l_rcPk != PK_OK) || (l_rc != SBE_SEC_OPERATION_SUCCESSFUL))
         {
             // It's likely a code bug or PK failure,
-            // or any other FIFO access failure.
+            // or any other PSU/FIFO access (scom) failure.
 
             // @TODO via RTC : 129166
             //       Review if we need to add ASSERT here
@@ -164,8 +202,16 @@ void sbeCommandReceiver_routine(void *i_pArg)
                 "l_rcPk=[%d], g_sbeSemCmdProcess.count=[%d], l_rc=[%d]",
                 l_rcPk, g_sbeSemCmdProcess.count, l_rc);
 
-            pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
-
+            if ( g_sbeIntrSource.isSet(SBE_INTERFACE_PSU) )
+            {
+                g_sbeIntrSource.clearIntrSource(SBE_INTERFACE_PSU);
+                pk_irq_enable(SBE_IRQ_HOST_PSU_INTR);
+            }
+            else if ( g_sbeIntrSource.isSet(SBE_INTERFACE_FIFO) )
+            {
+                g_sbeIntrSource.clearIntrSource(SBE_INTERFACE_FIFO);
+                pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+            }
             continue;
         }
 
diff --git a/sbe/sbefw/sbeexeintf.H b/sbe/sbefw/sbeexeintf.H
index 024cddfb..e4eef8dd 100644
--- a/sbe/sbefw/sbeexeintf.H
+++ b/sbe/sbefw/sbeexeintf.H
@@ -86,6 +86,43 @@ extern PkSemaphore g_sbeSemCmdProcess;
 extern PkSemaphore g_sbeSemFifoReset;
 
 /**
+ *  @brief SBE Interface source
+ *
+ */
+typedef enum
+{
+    SBE_INTERFACE_UNKNOWN = 0x00,
+    SBE_INTERFACE_FIFO    = 0x01,
+    SBE_INTERFACE_PSU     = 0x02,
+} sbeInterfaceSrc_t;
+
+/**
+ *  @brief structure for SBE external Interrupt handling
+ *
+ */
+typedef struct
+{
+    uint8_t l_intrSource;
+
+    void setIntrSource(const sbeInterfaceSrc_t i_val)
+    {
+        l_intrSource |= i_val;
+    }
+
+    void clearIntrSource(const sbeInterfaceSrc_t i_val)
+    {
+        l_intrSource &= ~i_val;
+    }
+
+    bool isSet (const sbeInterfaceSrc_t i_val)
+    {
+        return (l_intrSource & i_val);
+    }
+} sbeIntrHandle_t;
+extern sbeIntrHandle_t g_sbeIntrSource ;
+
+
+/**
  * @TODO via RTC : 128658
  *   Mutex protect the critical data
  *   e.g., add Mutex g_sbeMutCmdReqBuf etc.
@@ -137,14 +174,15 @@ void sbeSyncCommandProcessor_routine(void *i_pArg);
 void sbeAsyncCommandProcessor_routine(void *i_pArg);
 
 
-/* @brief  ISR for all application FIFO Interrupts
+/* @brief  ISR for all SBE External Interrupts
  *         - FIFO : New data available
  *         - FIFO : Reset Request
+ *         - PSU  : New data available
  *
  * @param[in/out]  i_pArg - Any buffer needed to be passed to the handler
  * @param[in]      i_irq  - IRQ number as defined in the SBE PPE spec
  */
-void sbe_fifo_interrupt_handler(void* i_pArg, PkIrqId i_irq);
+void sbe_interrupt_handler(void* i_pArg, PkIrqId i_irq);
 
 
 /* brief : Register SBE interrupt handlers and enable the IRQs
diff --git a/sbe/sbefw/sbefwfiles.mk b/sbe/sbefw/sbefwfiles.mk
index 4d169799..b537dff4 100644
--- a/sbe/sbefw/sbefwfiles.mk
+++ b/sbe/sbefw/sbefwfiles.mk
@@ -10,6 +10,9 @@ SBEFW-CPP-SOURCES += sbecmdgeneric.C
 SBEFW-CPP-SOURCES += sbeFifoMsgUtils.C
 SBEFW-CPP-SOURCES += attr.C
 SBEFW-CPP-SOURCES += sbecmdmemaccess.C
+SBEFW-CPP-SOURCES += sbeHostUtils.C
+SBEFW-CPP-SOURCES += sbecmdcntrldmt.C
+
 SBEFW-C-SOURCES =
 SBEFW-S-SOURCES =
 
diff --git a/sbe/sbefw/sbeirq.C b/sbe/sbefw/sbeirq.C
index c8436d1d..c2f3b616 100644
--- a/sbe/sbefw/sbeirq.C
+++ b/sbe/sbefw/sbeirq.C
@@ -10,38 +10,34 @@
 #include "sbetrace.H"
 #include "assert.h"
 
+extern sbeIntrHandle_t g_sbeIntrSource ;
+
 ////////////////////////////////////////////////////////////////
 // @brief:     SBE control loop ISR:
 //               - FIFO new data available
 //               - FIFO reset request
+//               - PSU new data available
 //
 // @param[in]  i_pArg - Unused
 // @param[in]  i_irq  - IRQ number as defined in sbeirq.h
 //
 ////////////////////////////////////////////////////////////////
-void sbe_fifo_interrupt_handler (void *i_pArg, PkIrqId i_irq)
+void sbe_interrupt_handler (void *i_pArg, PkIrqId i_irq)
 {
-    #define SBE_FUNC " sbe_fifo_interrupt_handler "
+    #define SBE_FUNC " sbe_interrupt_handler "
     SBE_ENTER(SBE_FUNC"i_irq=[0x%02X]",i_irq);
 
     int l_rc = 0;
+
     switch (i_irq)
     {
+        case SBE_IRQ_HOST_PSU_INTR:
+            g_sbeIntrSource.setIntrSource(SBE_INTERFACE_PSU);
+            break;
+
         case SBE_IRQ_SBEFIFO_DATA:
         case SBE_IRQ_SBEFIFO_RESET:
-            // Mask the interrupt
-            pk_irq_disable(i_irq);
-
-            // Unblock the command receiver thread
-            l_rc = pk_semaphore_post(&g_sbeSemCmdRecv);
-            if (l_rc)
-            {
-                // If we received an error while posting the semaphore,
-                // unmask the interrupt back and assert
-                SBE_ERROR(SBE_FUNC"pk_semaphore_post failed, rc=[%d]", l_rc);
-                pk_irq_enable(i_irq);
-                assert(!l_rc);
-            }
+            g_sbeIntrSource.setIntrSource(SBE_INTERFACE_FIFO);
             break;
 
         default:
@@ -49,6 +45,19 @@ void sbe_fifo_interrupt_handler (void *i_pArg, PkIrqId i_irq)
             assert(0);
             break;
     }
+    // Mask the interrupt
+    pk_irq_disable(i_irq);
+
+    // Unblock the command receiver thread
+    l_rc = pk_semaphore_post(&g_sbeSemCmdRecv);
+    if (l_rc)
+    {
+        // If we received an error while posting the semaphore,
+        // unmask the interrupt back and assert
+        SBE_ERROR(SBE_FUNC"pk_semaphore_post failed, rc=[%d]", l_rc);
+        pk_irq_enable(i_irq);
+        assert(!l_rc);
+    }
     #undef SBE_FUNC
 }
 
@@ -59,8 +68,10 @@ int sbeIRQSetup (void)
 {
     #define SBE_FUNC " sbeIRQSetup "
     int l_rc = 0;
+    PkIrqId l_irq;
 
     // Disable the relevant IRQs while we set them up
+    pk_irq_disable(SBE_IRQ_HOST_PSU_INTR);
     pk_irq_disable(SBE_IRQ_SBEFIFO_DATA);
     pk_irq_disable(SBE_IRQ_SBEFIFO_RESET);
 
@@ -68,35 +79,42 @@ int sbeIRQSetup (void)
     {
         // Register the IRQ handler with PK
 
-        // FIFO New data available interrupt
-        l_rc = pk_irq_handler_set(SBE_IRQ_SBEFIFO_DATA,
-                              sbe_fifo_interrupt_handler,
-                              NULL);
+        // PSU New data available interrupt
+        l_irq = SBE_IRQ_HOST_PSU_INTR;
+        l_rc = pk_irq_handler_set(l_irq, sbe_interrupt_handler, NULL);
+        if(l_rc)
+        {
+            break;
+        }
 
+        // FIFO New data available interrupt
+        l_irq = SBE_IRQ_SBEFIFO_DATA;
+        l_rc = pk_irq_handler_set(l_irq, sbe_interrupt_handler, NULL);
         if(l_rc)
         {
-            SBE_ERROR (SBE_FUNC"pk_irq_handler_set failed, IRQ=[0x%02X], "
-                   "rc=[%d]", SBE_IRQ_SBEFIFO_DATA, l_rc);
             break;
         }
 
         // FIFO Reset request
-        l_rc = pk_irq_handler_set(SBE_IRQ_SBEFIFO_RESET,
-                              sbe_fifo_interrupt_handler,
-                              NULL);
-
+        l_irq = SBE_IRQ_SBEFIFO_RESET;
+        l_rc = pk_irq_handler_set(l_irq, sbe_interrupt_handler, NULL);
         if(l_rc)
         {
-            SBE_ERROR (SBE_FUNC"pk_irq_handler_set failed, IRQ=[0x%02X], "
-                  "rc=[%d]", SBE_IRQ_SBEFIFO_RESET, l_rc);
             break;
         }
 
         // Enable the IRQ
         pk_irq_enable(SBE_IRQ_SBEFIFO_RESET);
         pk_irq_enable(SBE_IRQ_SBEFIFO_DATA);
+        pk_irq_enable(SBE_IRQ_HOST_PSU_INTR);
     } while(false);
 
+    if (l_rc)
+    {
+        SBE_ERROR (SBE_FUNC"pk_irq_handler_set failed, IRQ=[0x%02X], "
+            "rc=[%d]", l_irq, l_rc);
+    }
+
     return l_rc;
     #undef SBE_FUNC
 }
diff --git a/sbe/sbefw/sbeirq.H b/sbe/sbefw/sbeirq.H
index 2fcdd082..acf32079 100644
--- a/sbe/sbefw/sbeirq.H
+++ b/sbe/sbefw/sbeirq.H
@@ -19,8 +19,9 @@
 #define SBE_IRQ_DRTM_REQ 4       /* DRTM late launch request */
 #define SBE_IRQ_SBEFIFO_RESET 5  /* FIFO - Reset request from SE */
 #define SBE_IRQ_SBEFIFO_DATA  6  /* FIFO - Incoming Data Available */
+#define SBE_IRQ_HOST_PSU_INTR 7  /* PSU  - Incoming Data Available */
+
 
-#define SBE_IRQ_RESERVED_7  7
 #define SBE_IRQ_RESERVED_8  8
 #define SBE_IRQ_RESERVED_9  9