SBEFW istep integration with HWP

Change-Id: I3f17367d6fc6c4f421319b592762d4f10a63bde8
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17852
Tested-by: Jenkins Server
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>

4 files changed, 414 insertions, 191 deletions

diff --git a/sbe/sbefw/sbeSpMsg.H b/sbe/sbefw/sbeSpMsg.H
new file mode 100644
index 00000000..1c7a8d52
--- /dev/null
+++ b/sbe/sbefw/sbeSpMsg.H
@@ -0,0 +1,165 @@
+/*
+ * @file: ppe/sbe/sbefw/sbeSpMsg.H
+ *
+ * @brief This file contains the message structures for FIFO
+ *        communication.
+ *
+ */
+
+#ifndef __SBEFW_SBESP_MSG_H
+#define __SBEFW_SBESP_MSG_H
+
+// @NOTE Make sure all FIFO structures are 32 bit alligned ( the largest
+// member should be atleast 4 byte). It is required as in sbe fifo
+// operation we are casting these structures to uint32_t pointer. It can
+// cause alignment issue if largest member of structure is not atleast
+// 32 bit. We can use bit fields to optimize  memory requirements.
+// These are two coding guidleines we will follow for this file
+// 1. All data members less than 32 bits will be bit fields
+// 2. All data members more than 32 buts will be divided into small
+//    members of 32 bit each. This is required as compiler pads structure
+//    to largest data member and we do not want extra padding for data
+//    members gretater than 32 bits ( e.g. uint64_t )
+/**
+  * @brief Command Request Header
+  */
+typedef struct
+{
+    uint32_t len;
+    uint32_t reserved:16;
+    uint32_t cmdClass:8;
+    uint32_t command:8;
+}sbeCmdReqBuf_t;
+
+extern sbeCmdReqBuf_t g_sbeCmdHdr;
+
+/**
+  * @brief structure for generic header for fifo response.
+  *
+  */
+typedef struct
+{
+    uint32_t magicCode:16;
+    uint32_t cmdClass:8;
+    uint32_t command:8;
+    uint32_t primaryStatus:16;
+    uint32_t secondaryStatus:16;
+
+    /**
+      * @brief set the primary and secondary status
+      *
+      * @param[in] i_prim  Primary status
+      * @param[in] i_sec   Secondary status
+      *
+      * @return
+      */
+    void setStatus( const uint16_t i_prim, const uint16_t i_sec)
+    {
+        primaryStatus = i_prim;
+        secondaryStatus = i_sec;
+    }
+
+    /**
+      * @brief set initial values for response header
+      *
+      * @note  We did not set this in constructor as based on use case
+      *        it is possible that g_sbeCmdHdr does not have proper
+      *        values at time of object creation.
+      *
+      */
+    void init()
+    {
+        magicCode = 0xC0DE;
+        cmdClass  = g_sbeCmdHdr.cmdClass;
+        command = g_sbeCmdHdr.command;
+        primaryStatus = SBE_PRI_OPERATION_SUCCESSFUL;
+        secondaryStatus = SBE_SEC_OPERATION_SUCCESSFUL;
+    }
+
+}sbeResponseGenericHeader_t;
+
+/**
+  * @brief structure for ffdc header for fifo response.
+  *
+  */
+typedef struct sbeResponseFfdc
+{
+    uint32_t magicBytes:16;
+    uint32_t lenInWords:16;  // length in word( 4 byte )
+    uint32_t hiFapiRc;
+    uint32_t lowFapiRc;
+
+    /**
+      * @brief set rc
+      *
+      * @param[in] i_rc  FAPI RC
+      *
+      * @return
+      */
+    void setRc(const uint64_t i_rc)
+    {
+        lowFapiRc = uint32_t(i_rc);
+        hiFapiRc = uint32_t(i_rc>>32);
+    }
+
+    /**
+      * @brief return fapiRc
+      *
+      * @return fapiRc
+      */
+    uint64_t getRc()
+    {
+        uint64_t temp = ( (uint64_t)hiFapiRc << 32) | lowFapiRc;
+        return temp;
+    }
+
+    /**
+      * @brief constructor
+      *
+      * @param[in] i_rc  FAPI RC
+      *
+      * @return
+      */
+    sbeResponseFfdc()
+    {
+        magicBytes = 0xFFDC;
+        //TODO via 129076.
+        //Need to change value for length once FFDC design is final.
+        lenInWords  = ( sizeof(uint32_t )    // For magicBytes + lenInWords
+                        + sizeof(lowFapiRc) + sizeof(hiFapiRc) )
+                           / sizeof(uint32_t);
+        lowFapiRc = 0;
+        hiFapiRc = 0;
+    }
+}sbeResponseFfdc_t;
+
+/**
+  * @brief structure for execute istep chipop (0xA101) contents.
+  *
+  */
+typedef struct
+{
+    uint32_t reserved1:8;
+    uint32_t major:8;
+    uint32_t reserved2:8;
+    uint32_t minor:8;
+}sbeIstepReqMsg_t;
+
+//  TODO via RTC 128658
+//  We may be able to replace this structure by sbeResponseGenericHeader_t
+
+/**
+  * @brief Command response structure to hold the primary and secondary
+  *        status values. This will be utilized when a command class
+  *        validation or state machine check fails.
+  *
+  */
+typedef struct
+{
+    uint32_t          prim_status:16 ;    // Primary Response Status
+    uint32_t          sec_status:16  ;    // Secondary Response Status
+} sbeCmdRespHdr_t;
+
+extern sbeCmdRespHdr_t g_sbeCmdRespHdr;
+
+#endif // __SBEFW_SBESP_MSG_H
diff --git a/sbe/sbefw/sbecmdiplcontrol.C b/sbe/sbefw/sbecmdiplcontrol.C
index a48e32aa..7ff3208e 100644
--- a/sbe/sbefw/sbecmdiplcontrol.C
+++ b/sbe/sbefw/sbecmdiplcontrol.C
@@ -1,7 +1,7 @@
 /*
  * @file: ppe/sbe/sbefw/sbecmdiplcontrol.C
  *
- * @brief This file contains the SBE FIFO Commands
+ * @brief This file contains the SBE istep chipOps
  *
  */
 
@@ -10,67 +10,183 @@
 #include "sbetrace.H"
 #include "sbe_sp_intf.H"
 
-// Forward declaration
-
-uint32_t sbeExecuteIstep (const uint8_t i_major, const uint8_t i_minor);
-bool validateIstep (const uint8_t i_major, const uint8_t i_minor);
+#include "fapi2.H"
+// Pervasive HWP Header Files ( istep 2)
+#include <p9_sbe_attr_setup.H>
+#include <p9_sbe_tp_chiplet_init1.H>
+#include <p9_sbe_npll_initf.H>
+#include <p9_sbe_npll_setup.H>
+#include <p9_sbe_tp_switch_gears.H>
+#include <p9_sbe_tp_chiplet_reset.H>
+#include <p9_sbe_tp_gptr_time_repr_initf.H>
+#include <p9_sbe_tp_chiplet_init2.H>
+#include <p9_sbe_tp_arrayinit.H>
+#include <p9_sbe_tp_initf.H>
+#include <p9_sbe_tp_chiplet_init3.H>
+
+// Pervasive HWP Header Files ( istep 3)
+#include <p9_sbe_chiplet_reset.H>
+#include <p9_sbe_chiplet_pll_initf.H>
+#include <p9_sbe_chiplet_pll_setup.H>
+#include <p9_sbe_gptr_time_repr_initf.H>
+#include <p9_sbe_chiplet_init.H>
+#include <p9_sbe_arrayinit.H>
+#include <p9_sbe_tp_enable_ridi.H>
+#include <p9_sbe_setup_evid.H>
+#include <p9_sbe_nest_initf.H>
+#include <p9_sbe_nest_startclocks.H>
+#include <p9_sbe_nest_enable_ridi.H>
+#include <p9_sbe_startclock_chiplets.H>
+#include <p9_sbe_scominit.H>
+#include <p9_sbe_lpc_init.H>
+#include <p9_sbe_fabricinit.H>
+#include <p9_sbe_mcs_setup.H>
+#include <p9_sbe_select_ex.H>
+// Cache HWP header file
+#include "p9_hcd_cache.H"
+// Core HWP header file
+#include "p9_hcd_core.H"
 
-// @TODO via RTC 129073.
-// Just a dummy code for HWP to test the flow.
-// Remove it once complete flow is ready
-uint32_t istep1SuccessHwp(  ) { SBE_DEBUG("istep1SuccessHwp"); return 0; }
-uint32_t istep1FailHwp(  ) { SBE_DEBUG("istep1FailHwp"); return 1; }
+// Forward declaration
+using namespace fapi2;
+ReturnCode sbeExecuteIstep (uint8_t i_major, uint8_t i_minor);
+bool validateIstep (uint8_t i_major, uint8_t i_minor);
 
 
 //typedefs
-// @TODO via RTC 129073.
-// This is currently not defined as actual HWP signature as it
-// will break compilation. Once Greg FAPI codeis in master, we will
-// change it
-typedef uint32_t (*sbe_istep_hwp)();
+typedef ReturnCode (*sbeIstepHwp_t)
+                    (const Target<TARGET_TYPE_ALL> & i_target);
 
 // Wrapper function for HWP IPl functions
-typedef uint32_t (*sbe_istep)( sbe_istep_hwp );
+typedef ReturnCode (*sbeIstep_t)( sbeIstepHwp_t );
 
 // Wrapper function which will call HWP with Proc target.
-uint32_t istepWithProc( sbe_istep_hwp i_hwp );
+ReturnCode istepWithProc( sbeIstepHwp_t i_hwp );
+ReturnCode istepNoOp( sbeIstepHwp_t i_hwp );
 
+ReturnCode istepWithEx( sbeIstepHwp_t i_hwp);
+
+ReturnCode istepWithEq( sbeIstepHwp_t i_hwp);
+ReturnCode istepWithCore( sbeIstepHwp_t i_hwp);
 //structure for mapping SBE wrapper and HWP functions
+
 typedef struct
 {
-    sbe_istep istepWrapper;
-    sbe_istep_hwp istepHwp;
+    sbeIstep_t istepWrapper;
+    sbeIstepHwp_t istepHwp;
 }istepMap_t;
 
 // Major isteps which are supported
 typedef enum
 {
     SBE_ISTEP2 = 2,
+    SBE_ISTEP3 = 3,
     SBE_ISTEP4 = 4,
     SBE_ISTEP5 = 5,
 }sbe_supported_steps_t;
 
 // constants
-// @TODO via RTC 129073.
-// These are random numbers now. Will fill up
-// once IPL flow document is in better shape.
+// TODO via RTC 135345
+// Check with Dean. In IPL flow doc ( version 0.63 ),
+// after istep 2.9, next istep is 2.11. istep 2.10 is not present.
+// So in IPL flow doc, total minor isteps for step 2 are 16.
 const uint32_t ISTEP2_MAX_SUBSTEPS = 15;
-const uint32_t ISTEP4_MAX_SUBSTEPS = 2;
-const uint32_t ISTEP5_MAX_SUBSTEPS = 4;
+const uint32_t ISTEP3_MAX_SUBSTEPS = 20;
+const uint32_t ISTEP4_MAX_SUBSTEPS = 31;
+const uint32_t ISTEP5_MAX_SUBSTEPS = 2;
 
 // File static data
-// @TODO via RTC 129073.
-// Initialise pointer tables.
 
 static istepMap_t g_istep2PtrTbl[ ISTEP2_MAX_SUBSTEPS ] =
-                    {
-                        { NULL, NULL },
-                        { &istepWithProc, &istep1FailHwp },
-                        { &istepWithProc, &istep1SuccessHwp }
-
-                    };
-static istepMap_t g_istep4PtrTbl[ ISTEP4_MAX_SUBSTEPS ];
-static istepMap_t g_istep5PtrTbl[ ISTEP5_MAX_SUBSTEPS ];
+         {
+             { NULL, NULL },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_attr_setup },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_chiplet_init1 },
+             { &istepNoOp, NULL },  // DFT only
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_npll_initf },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_npll_setup },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_switch_gears },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_chiplet_reset },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_gptr_time_repr_initf },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_chiplet_init2 },
+             { &istepNoOp, NULL },  // DFT only
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_arrayinit },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_initf },
+             { &istepNoOp, NULL }, // DFT only
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_chiplet_init3},
+         };
+
+static istepMap_t g_istep3PtrTbl[ ISTEP3_MAX_SUBSTEPS ] =
+         {
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_chiplet_reset },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_chiplet_pll_initf },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_chiplet_pll_setup },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_gptr_time_repr_initf },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_chiplet_init },
+             { &istepNoOp, NULL }, // DFT only
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_arrayinit },
+             { &istepNoOp, NULL }, // DFT only
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_tp_enable_ridi },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_setup_evid },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_nest_initf },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_nest_startclocks },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_nest_enable_ridi },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_startclock_chiplets },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_scominit },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_lpc_init },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_fabricinit },
+             { &istepNoOp, NULL }, // TODO via RTC 120752
+                                   // FW proc_sbe_check_master
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_mcs_setup },
+             { &istepWithProc, (sbeIstepHwp_t)&p9_sbe_select_ex },
+         };
+static istepMap_t g_istep4PtrTbl[ ISTEP4_MAX_SUBSTEPS ] =
+         {
+             { &istepWithEq, (sbeIstepHwp_t )&p9_hcd_cache_poweron },
+             { &istepWithEq, (sbeIstepHwp_t )&p9_hcd_cache_chiplet_reset },
+             { &istepWithEq, (sbeIstepHwp_t )&p9_hcd_cache_gptr_time_initf },
+             { &istepWithEq, (sbeIstepHwp_t )&p9_hcd_cache_dpll_setup },
+             { &istepWithEq, (sbeIstepHwp_t )&p9_hcd_cache_chiplet_init },
+             { &istepWithEx, (sbeIstepHwp_t )&p9_hcd_cache_repair_initf },
+             { &istepWithEx, (sbeIstepHwp_t )&p9_hcd_cache_arrayinit },
+             { &istepNoOp, NULL },  // DFT Only
+             { &istepNoOp, NULL },  // DFT Only
+             { &istepWithEx, (sbeIstepHwp_t )&p9_hcd_cache_initf },
+             { &istepWithEx, (sbeIstepHwp_t )&p9_hcd_cache_startclocks },
+             { &istepWithEx, (sbeIstepHwp_t )&p9_hcd_cache_scominit },
+             { &istepWithEx, (sbeIstepHwp_t )&p9_hcd_cache_scomcust },
+             { &istepNoOp, NULL }, // Runtime only
+             { &istepNoOp, NULL }, // Runtime only
+             { &istepNoOp, NULL }, // stub for SBE
+             // TODO via RTC 135345
+             // As per IPL flow doc, p9_hcd_core_pcb_arb is no-op on SBE
+             // But this HWP is present in SBE code bas and is No-OP.
+             // If we do not require this HWP for future use cases, we
+             // can make it istepNoOp as it will save space in SBE.
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_pcb_arb },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_poweron },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_chiplet_reset },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_gptr_time_initf },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_chiplet_init },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_repair_initf },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_arrayinit },
+             { &istepNoOp, NULL },  // DFT Only
+             { &istepNoOp, NULL },  // DFT Only
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_initf },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_startclocks },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_scominit },
+             { &istepWithCore, (sbeIstepHwp_t )&p9_hcd_core_scomcust },
+             { &istepNoOp, NULL },
+             { &istepNoOp, NULL },
+         };
+
+// TODO via RTC 135345
+//  Add the support for istep 5 HWP
+static istepMap_t g_istep5PtrTbl[ ISTEP5_MAX_SUBSTEPS ]
+         {
+             { &istepNoOp, NULL },
+             { &istepNoOp, NULL },
+         };
 
 // Functions
 //----------------------------------------------------------------------------
@@ -79,10 +195,8 @@ uint32_t sbeHandleIstep (uint8_t *i_pArg)
     #define SBE_FUNC "sbeHandleIstep "
     SBE_DEBUG(SBE_FUNC);
     uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
-    //@TODO via RTC 129073.
-    //Use proper initialisation for fapi RC
-    uint32_t fapiRc = SBE_SEC_OPERATION_SUCCESSFUL;
     uint8_t len = 0;
+    ReturnCode fapiRc = FAPI2_RC_SUCCESS;
     sbeIstepReqMsg_t req;
     sbeResponseGenericHeader_t respHdr;
     respHdr.init();
@@ -123,14 +237,14 @@ uint32_t sbeHandleIstep (uint8_t *i_pArg)
         {
             SBE_ERROR(SBE_FUNC" Invalid Istep. major:0x%08x"
                       " minor:0x%08x", req.major, req.minor);
-            // @TODO via RTC 129073.
+            // @TODO via RTC 132295.
             // Need to change code asper better error handling.
             respHdr.setStatus( SBE_PRI_INVALID_DATA,
                                SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
             break;
         }
         fapiRc = sbeExecuteIstep( req.major, req.minor );
-        if( fapiRc )
+        if( fapiRc != FAPI2_RC_SUCCESS )
         {
             SBE_ERROR(SBE_FUNC" sbeExecuteIstep() Failed. major:0x%08x"
                                       " minor:0x%08x", req.major, req.minor);
@@ -161,7 +275,7 @@ uint32_t sbeHandleIstep (uint8_t *i_pArg)
         distance += len;
 
         // If no ffdc , exit;
-        if( ffdc.fapiRc )
+        if( ffdc.getRc() )
         {
             len = sizeof(ffdc)/sizeof(uint32_t);
             rc = sbeDownFifoEnq_mult ( len, ( uint32_t *) &ffdc);
@@ -172,7 +286,7 @@ uint32_t sbeHandleIstep (uint8_t *i_pArg)
             distance += len;
         }
         len = sizeof(distance)/sizeof(uint32_t);
-        //@TODO via 129076.
+        //@TODO via RTC 129076.
         //Need to add FFDC data as well.
         rc = sbeDownFifoEnq_mult ( len, &distance);
         if (rc)
@@ -190,20 +304,18 @@ uint32_t sbeHandleIstep (uint8_t *i_pArg)
 }
 
 //----------------------------------------------------------------------------
-// @TODO via RTC 129073.
-// Change return code as per design
 // @note This is the responsibilty of caller to verify major/minor
 //       number before calling this function
 
 // @TODO via RTC 129077.
 // This function should check for system checkstop as well.
-uint32_t sbeExecuteIstep (const uint8_t i_major, const uint8_t i_minor)
+ReturnCode sbeExecuteIstep (const uint8_t i_major, const uint8_t i_minor)
 {
     #define SBE_FUNC "sbeExecuteIstep "
     SBE_DEBUG(SBE_FUNC"Major number:0x%x minor number:0x%x",
                        i_major, i_minor );
-    uint32_t rc = 0;
 
+    ReturnCode rc = FAPI2_RC_SUCCESS;
     switch( i_major )
     {
         case SBE_ISTEP2:
@@ -211,6 +323,11 @@ uint32_t sbeExecuteIstep (const uint8_t i_major, const uint8_t i_minor)
                                 g_istep2PtrTbl[i_minor-1].istepHwp);
             break;
 
+        case SBE_ISTEP3:
+            rc = (g_istep3PtrTbl[i_minor-1].istepWrapper)(
+                                g_istep2PtrTbl[i_minor-1].istepHwp);
+            break;
+
         case SBE_ISTEP4:
             rc = (g_istep4PtrTbl[i_minor-1].istepWrapper)(
                               g_istep4PtrTbl[i_minor-1].istepHwp);
@@ -256,6 +373,10 @@ bool validateIstep (const uint8_t i_major, const uint8_t i_minor)
                 }
                 break;
 
+            case SBE_ISTEP3:
+                if( i_minor > ISTEP3_MAX_SUBSTEPS ) { valid = false; } ;
+                break;
+
             case SBE_ISTEP4:
                 if( i_minor > ISTEP4_MAX_SUBSTEPS )
                 {
@@ -281,22 +402,82 @@ bool validateIstep (const uint8_t i_major, const uint8_t i_minor)
 
 //----------------------------------------------------------------------------
 
-uint32_t istepWithProc( sbe_istep_hwp i_hwp)
+ReturnCode istepWithProc( sbeIstepHwp_t i_hwp)
 {
     SBE_DEBUG("istepWithProc");
-    uint32_t rc = 0;
+    Target<TARGET_TYPE_PROC_CHIP > proc = plat_getChipTarget();
+    ReturnCode rc = FAPI2_RC_SUCCESS;
     if( i_hwp )
     {
-        rc = i_hwp();
+        rc = i_hwp(proc);
     }
+    SBE_DEBUG("istepWithProc");
     return rc;
 }
 
 //----------------------------------------------------------------------------
 
+ReturnCode istepWithEx( sbeIstepHwp_t i_hwp)
+{
+    fapi2::Target<fapi2::TARGET_TYPE_EX > ex10_target((uint64_t)10);
+    SBE_DEBUG("istepWithEx");
+    ReturnCode rc = FAPI2_RC_SUCCESS;
+    if( i_hwp )
+    {
+        rc = i_hwp(ex10_target);
+    }
+    return rc;
+}
+
+//----------------------------------------------------------------------------
+
+ReturnCode istepWithEq( sbeIstepHwp_t i_hwp)
+{
+    // TODO via RTC 135345
+    // Curently we are passing Hard code eq target. Finally it is
+    // going to be a multicast target. Once multicast support is
+    // present, use the right target.
+    fapi2::Target<fapi2::TARGET_TYPE_EQ > eq10_target((uint64_t)10);
+    SBE_DEBUG("istepWithEq");
+    ReturnCode rc = FAPI2_RC_SUCCESS;
+    if( i_hwp )
+    {
+        rc = i_hwp( eq10_target );
+    }
+    return rc;
+}
+
+//----------------------------------------------------------------------------
+
+ReturnCode istepWithCore( sbeIstepHwp_t i_hwp)
+{
+    // TODO via RTC 135345
+    // Curently we are passing Hard code core target. Finally it is
+    // going to be a multicast target. Once multicast support is
+    // present, use the right target.
+    fapi2::Target<fapi2::TARGET_TYPE_CORE > core_target((uint64_t)10);
+    SBE_DEBUG("istepWithCore");
+    ReturnCode rc = FAPI2_RC_SUCCESS;
+    if( i_hwp )
+    {
+        rc = i_hwp( core_target );
+    }
+    return rc;
+}
+
+//----------------------------------------------------------------------------
+
+ReturnCode istepNoOp( sbeIstepHwp_t i_hwp)
+{
+    SBE_DEBUG("istepNoOp");
+    return FAPI2_RC_SUCCESS ;
+}
+
+//----------------------------------------------------------------------------
+
 uint32_t sbeWaitForSbeIplDone (uint8_t *i_pArg)
 {
-    uint32_t rc = 0;
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
     SBE_TRACE("sbeWaitForSbeIplDone");
 
 
diff --git a/sbe/sbefw/sbefifo.H b/sbe/sbefw/sbefifo.H
index bf1c3123..b0b7b41d 100644
--- a/sbe/sbefw/sbefifo.H
+++ b/sbe/sbefw/sbefifo.H
@@ -12,6 +12,7 @@
 #include "sbetrace.H"
 #include "ppe42_scom.h"
 #include "sbe_sp_intf.H"
+#include "sbeSpMsg.H"
 
 /**
   * @brief SBE FIFO Access addresses
@@ -118,147 +119,6 @@ typedef union
 } sbe_downfifo_status_t;
 
 
-// @TODO via RTC 129073.
-// Put these structures in separate file as these are not FIFO specific.
-// Also make sure all FIFO structures are 32 bit alligned ( the largest
-// member should be atleast 4 byte). It is required as in sbe fifo
-// operation we are casting these structures to uint32_t pointer. It can
-// cause allignment issue if largest member of structure is not atleast
-// 32 bit. We can use bit fields to optimize  memory requirements.
-/**
-  * @brief Command Request Header
-  */
-typedef struct
-{
-    uint32_t len;
-    uint16_t reserved;
-    uint8_t cmdClass;
-    uint8_t command;
-}sbeCmdReqBuf_t;
-
-extern sbeCmdReqBuf_t g_sbeCmdHdr;
-
-/**
-  * @brief structure for generic header for fifo response.
-  *
-  */
-typedef struct
-{
-    uint16_t magicCode;
-    uint8_t cmdClass;
-    uint8_t command;
-    uint16_t primaryStatus;
-    uint16_t secondaryStatus;
-
-    /**
-      * @brief set the primary and secondary status
-      *
-      * @param[in] i_prim  Primary status
-      * @param[in] i_sec   Secondary status
-      *
-      * @return
-      */
-    void setStatus( const uint16_t i_prim, const uint16_t i_sec)
-    {
-        primaryStatus = i_prim;
-        secondaryStatus = i_sec;
-    }
-
-    /**
-      * @brief set initial values for response header
-      *
-      * @note  We did not set this in constructor as based on use case
-      *        it is possible that g_sbeCmdHdr does not have proper
-      *        values at time of object creation.
-      *
-      */
-    void init()
-    {
-        magicCode = 0xC0DE;
-        cmdClass  = g_sbeCmdHdr.cmdClass;
-        command = g_sbeCmdHdr.command;
-        primaryStatus = SBE_PRI_OPERATION_SUCCESSFUL;
-        secondaryStatus = SBE_SEC_OPERATION_SUCCESSFUL;
-    }
-
-}sbeResponseGenericHeader_t;
-
-/**
-  * @brief structure for ffdc header for fifo response.
-  *
-  */
-typedef struct sbeResponseFfdc
-{
-    uint16_t magicBytes;
-    uint16_t lenInWords;  // length in word( 4 byte )
-    //@TODO via RTC 129073.
-    //make fapiRc 64 bit
-    uint32_t fapiRc;
-
-    /**
-      * @brief set rc
-      *
-      * @param[in] i_rc  FAPI RC
-      *
-      * @return
-      */
-    void setRc(const uint32_t i_rc)
-    {
-        fapiRc = i_rc;
-    }
-
-    /**
-      * @brief constructor
-      *
-      * @param[in] i_rc  FAPI RC
-      *
-      * @return
-      */
-    sbeResponseFfdc()
-    {
-        magicBytes = 0xFFDC;
-        //TODO via 129076.
-        //Need to change value for length once FFDC design is final.
-        lenInWords  = ( sizeof(magicBytes) + sizeof(lenInWords)
-                            + sizeof(fapiRc) )/ sizeof(uint32_t);
-        fapiRc = 0;
-    }
-}sbeResponseFfdc_t;
-
-/**
-  * @brief structure for execute istep chipop (0xA101) contents.
-  *
-  */
-typedef struct
-{
-    uint8_t reserved1;
-    uint8_t major;
-    uint8_t reserved2;
-    uint8_t minor;
-}sbeIstepReqMsg_t;
-
-
-/**
-  * @brief Command response structure to hold the primary and secondary
-  *        status values. This will be utilized when a command class
-  *        validation or state machine check fails.
-  *
-  */
-typedef struct
-{
-    uint16_t          prim_status ;    // Primary Response Status
-    uint16_t          sec_status  ;    // Secondary Response Status
-} sbeCmdRespHdr_t;
-
-extern sbeCmdRespHdr_t g_sbeCmdRespHdr;
-
-typedef struct
-{
-    uint16_t magic_bytes;
-    uint16_t len;
-} sbeCmdResp_FFDC_t;
-
-
 /*****************************************************************/
 /** Upstream FIFO access utilities **/
 /*****************************************************************/
diff --git a/sbe/sbefw/sbemain.C b/sbe/sbefw/sbemain.C
index f2403bff..65d91f4d 100644
--- a/sbe/sbefw/sbemain.C
+++ b/sbe/sbefw/sbemain.C
@@ -15,6 +15,7 @@
 
 #include "sbeexeintf.H"
 #include "sbetrace.H"
+#include "fapi2.H" // For target init
 
 
 ////////////////////////////////////////////////////////////////
@@ -211,7 +212,8 @@ int sbeInitThreads(void)
 ////////////////////////////////////////////////////////////////
 uint32_t main(int argc, char **argv)
 {
-    SBE_TRACE("Enter SBE main");
+    #define SBE_FUNC "main "
+    SBE_ENTER(SBE_FUNC);
     int l_rc = 0;
 
     // @TODO via RTC : 128818
@@ -255,6 +257,21 @@ uint32_t main(int argc, char **argv)
             break;
         }
 
+        // TODO via RTC 126146.
+        //  Check if we should call plat_TargetsInit in some other thread.
+        //  We may want to keep only PK init in main and can move
+        //  plat init to some other thread. Only if this is required by more
+        //  than one thread and there can be some race condition, we will
+        //  keep it here before starting other threads.
+        fapi2::ReturnCode fapiRc = fapi2::plat_TargetsInit();
+        if( fapiRc != fapi2::FAPI2_RC_SUCCESS )
+        {
+            SBE_ERROR(SBE_FUNC"plat_TargetsInit failed");
+            // TODO via RTC 126146.
+            //  Set the state to Failure and remove break statement. It will
+            //  enable FSP to get FFDC for this failure.
+            break;
+        }
         // Start running the highest priority thread.
         // This function never returns
         pk_start_threads();