SBE memory (PBA) Access Support

RTC:128062
RTC:128976

Rebased with master to pull in the latest fixes.

Change-Id: I7985429189403b06c8eae48125007ba6f7f9c6c4
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20836
Tested-by: Jenkins Server
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>

9 files changed, 561 insertions, 5 deletions

diff --git a/sbe/sbefw/sbeFifoMsgUtils.C b/sbe/sbefw/sbeFifoMsgUtils.C
index 317c9c3f..9771a420 100644
--- a/sbe/sbefw/sbeFifoMsgUtils.C
+++ b/sbe/sbefw/sbeFifoMsgUtils.C
@@ -113,7 +113,7 @@ uint32_t sbeUpFifoDeq_mult (uint32_t    &io_len,
         // if Upstream FIFO is empty,
         if (l_data.statusOrReserved.fifo_empty)
         {
-            SBE_DEBUG(SBE_FUNC"Downstream FIFO is empty. Sleeping for 1 ms");
+            //SBE_DEBUG(SBE_FUNC"Downstream FIFO is empty. Sleeping for 1 ms");
             pk_sleep(PK_MILLISECONDS(1));
             continue;
         }
@@ -173,7 +173,7 @@ uint32_t sbeDownFifoEnq_mult (uint32_t        &io_len,
         if (l_status.downfifo_status.fifo_full)
         {
             // Downstream FIFO is full
-            SBE_DEBUG(SBE_FUNC"Downstream FIFO is full. Sleeping for 1 ms");
+            //SBE_DEBUG(SBE_FUNC"Downstream FIFO is full. Sleeping for 1 ms");
             pk_sleep(PK_MILLISECONDS(1));
             continue;
         }
diff --git a/sbe/sbefw/sbeSpMsg.H b/sbe/sbefw/sbeSpMsg.H
index 07d8bbb8..57a00f98 100644
--- a/sbe/sbefw/sbeSpMsg.H
+++ b/sbe/sbefw/sbeSpMsg.H
@@ -9,6 +9,8 @@
 #ifndef __SBEFW_SBESP_MSG_H
 #define __SBEFW_SBESP_MSG_H
 
+#include "sbe_sp_intf.H"
+
 // @NOTE Make sure all FIFO structures are 32 bit alligned ( the largest
 // member should be atleast 4 byte). It is required as in sbe fifo
 // operation we are casting these structures to uint32_t pointer. It can
@@ -238,7 +240,7 @@ typedef struct
         uint64_t data = ((uint64_t)hiMaskData << 32) | lowMaskData;
         return data;
     }
-    
+
     /**
       * @brief Determines 64-bit Scom data
       *
@@ -250,9 +252,82 @@ typedef struct
         uint64_t l_inputData = getInputData();
         io_scomData = (io_scomData & (~l_inputMask))
                     | (l_inputData & l_inputMask);
-    }    
+    }
 }sbePutScomUnderMaskReqMsg_t;
 
+/**
+ * @brief Structure for SBE Memory Access ChipOps (0xA401/A402)
+ *
+ */
+typedef struct
+{
+    uint32_t flags;  // Operational Flags
+    uint32_t addrHi; // Higher 32-Bit Memory Address
+    uint32_t addrLo; // Lower  32-Bit Memory Address
+    uint32_t len;    // Length of Data in Bytes
+
+    /**
+      * @brief Calculates 64-bit PBA Address
+      *
+      * @return Return 64-bit PBA address
+      */
+    uint64_t getPbaAddr()
+    {
+        uint64_t addr = ((uint64_t)addrHi << 32) | addrLo;
+        return addr;
+    }
+
+    /**
+      * @brief Determines if PBA flag is set
+      *
+      * @return Returns True if PBA Flag is set
+      *                 False if PBA flag is not set
+      */
+    bool isPbaFlagSet()
+    {
+        bool tmp_flag = (flags & SBE_MEM_ACCESS_FLAGS_TARGET_PBA) ?
+                           true : false ;
+        return tmp_flag;
+    }
+
+    /**
+      * @brief Determines if Auto Increment Mode is set
+      *
+      * @return Returns True if Auto Increment mode is set
+      *                 False if Auto Increment is not set
+      */
+    bool isAutoIncrModeSet()
+    {
+        bool tmp_flag = (flags & SBE_MEM_ACCESS_FLAGS_AUTO_INCR_ON) ?
+                           true : false ;
+        return tmp_flag;
+    }
+
+    /**
+      * @brief Determines if Fast Mode is set
+      *
+      * @return Returns True if Fast mode is set
+      *                 False if Fast mode is not set
+      */
+    uint32_t isFastModeSet()
+    {
+        uint32_t tmp_flag = (flags & SBE_MEM_ACCESS_FLAGS_FAST_MODE_ON) ?
+                             (1<<31) : 0;
+        return tmp_flag;
+    }
+
+    /**
+      * @brief Calculates Data length in alignment with PBA Cacheline (128B)
+      *
+      * @return Returns Data length in alignment with PBA Cacheline
+      */
+    uint64_t getDataLenPbaCacheAlign()
+    {
+        uint64_t l_len = (len / 8) / 16;
+        return l_len;
+    }
+}sbeMemAccessReqMsgHdr_t;
+
 
 // Maximum number of capabilities
 static const uint32_t SBE_MAX_CAPABILITIES = 18;
diff --git a/sbe/sbefw/sbe_sp_intf.H b/sbe/sbefw/sbe_sp_intf.H
index 66cccfbc..b536bd9f 100644
--- a/sbe/sbefw/sbe_sp_intf.H
+++ b/sbe/sbefw/sbe_sp_intf.H
@@ -261,6 +261,22 @@ enum
     GET_SBE_STATE_SUPPPORTED            = 0xA8000008,
 };
 
+/**
+ *  * @brief enums for SBE Memory Access command flags
+ *
+ */
+enum sbeMemoryAccessFlags
+{
+    SBE_MEM_ACCESS_FLAGS_TARGET_PROC  = 0x00000001,
+    SBE_MEM_ACCESS_FLAGS_TARGET_PBA   = 0x00000002,
+    SBE_MEM_ACCESS_FLAGS_AUTO_INCR_ON = 0x00000004,
+    SBE_MEM_ACCESS_FLAGS_ECC_OVERRIDE = 0x00000008,
+    SBE_MEM_ACCESS_FLAGS_TAG          = 0x00000010,
+    SBE_MEM_ACCESS_FLAGS_FAST_MODE_ON = 0x00000020,
+};
+
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/sbe/sbefw/sbecmdgeneric.C b/sbe/sbefw/sbecmdgeneric.C
index 7a288e20..7ad0016b 100644
--- a/sbe/sbefw/sbecmdgeneric.C
+++ b/sbe/sbefw/sbecmdgeneric.C
@@ -35,6 +35,10 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg()
 
     capability[GENERIC_CHIPOP_CAPABILITY_START_IDX] =
                                 GET_SBE_CAPABILITIES_SUPPPORTED;
+
+    capability[MEMORY_CAPABILITY_START_IDX] =
+                                GET_MEMORY_SUPPPORTED |
+                                PUT_MEMORY_SUPPPORTED ;
 }
 // Functions
 //----------------------------------------------------------------------------
diff --git a/sbe/sbefw/sbecmdmemaccess.C b/sbe/sbefw/sbecmdmemaccess.C
new file mode 100644
index 00000000..b47e00e9
--- /dev/null
+++ b/sbe/sbefw/sbecmdmemaccess.C
@@ -0,0 +1,378 @@
+/*
+ * @file: ppe/sbe/sbefw/sbecmdmemaccess.C
+ *
+ * @brief This file contains the SBE Memory Access chipOps
+ *
+ */
+
+#include "sbecmdmemaccess.H"
+#include "sbefifo.H"
+#include "sbe_sp_intf.H"
+#include "sbetrace.H"
+#include "sbeFifoMsgUtils.H"
+
+#include "fapi2.H"
+
+#include "p9_pba_access.H"
+#include "p9_pba_setup.H"
+
+using namespace fapi2;
+
+///////////////////////////////////////////////////////////////////////
+// @brief sbeMemAccess_Wrap Memory Access Wrapper function
+//
+// @param [in] i_flagGetOrPut Flag to indicate the memory Access Type
+//                 true  : GetMem ChipOp
+//                 false : PutMem ChipOp
+//
+// @return  RC from the underlying FIFO utility
+///////////////////////////////////////////////////////////////////////
+uint32_t sbeMemAccess_Wrap(const bool i_flagGetOrPut)
+{
+    #define SBE_FUNC " sbeMemAccess_Wrap "
+    SBE_ENTER(SBE_FUNC);
+
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    ReturnCode l_fapiRc = FAPI2_RC_SUCCESS;
+    sbeResponseGenericHeader_t l_respHdr;
+    l_respHdr.init();
+    sbeResponseFfdc_t l_ffdc;
+
+    // Create an instance of Memory Access ChipOp structure
+    sbeMemAccessReqMsgHdr_t l_req = {0};
+
+    // @TODO via RTC: 128982
+    //       ADU support
+    //       Handle ECC data
+
+    // Offload the common header from
+    // the Upstream FIFO
+    bool l_eot = (i_flagGetOrPut)? true : false;
+    uint32_t l_len2dequeue  = sizeof(l_req) / sizeof(uint32_t);
+    l_rc = sbeUpFifoDeq_mult (l_len2dequeue, (uint32_t *)&l_req, l_eot);
+
+    SBE_DEBUG(SBE_FUNC " flags[0x%08X], addrHi[0x%08X],"
+                       " addrLo[0x%08X], len[[0x%08X]",
+                       l_req.flags, l_req.addrHi,
+                       l_req.addrLo, l_req.len);
+
+    // Calculate the PBA address from the given input
+    uint64_t l_pbaAddr = l_req.getPbaAddr();
+
+    // @TODO via RTC: 128982
+    //       Handle Invalid length (0) and Invalid Flags:
+    //       Primary status code could be SBE_PRI_INVALID_DATA,
+    //       but, what would be the secondary status code?
+
+    // @TODO via RTC: 128982
+    //       ADU support
+    //       Auto Increment Flag is applicable only for ADU operations
+    // bool l_isAutoIncr = l_req.isAutoIncrModeSet();
+
+    // Determine the access flags
+    bool l_isPBA = l_req.isPbaFlagSet();
+    uint32_t l_isFastMode = l_req.isFastModeSet();
+
+    uint32_t l_numGranules = 0;
+    uint64_t l_numCacheLineCompleted = 0;
+
+    // Input Data length in alignment with PBA Cacheline (128 Bytes)
+    uint64_t l_dataLenCacheLineAligned = l_req.getDataLenPbaCacheAlign();
+
+    Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc =
+                              plat_getChipTarget();
+    // @TODO via RTC: 128982
+    //       Accept Ex target from input data
+    Target<fapi2::TARGET_TYPE_EX > l_ex((uint64_t)7);
+
+    while (l_numCacheLineCompleted < l_dataLenCacheLineAligned)
+    {
+        // If FIFO access failure
+        if (l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            // Let command processor routine to handle the RC.
+            break;
+        }
+
+        if (l_isPBA)
+        {
+            // Call the PBA setup HWP
+            l_fapiRc = p9_pba_setup (l_proc,
+                                     l_ex,
+                                     l_pbaAddr,
+                                     i_flagGetOrPut,
+                                     l_isFastMode,
+                                     l_numGranules);
+        }
+        else
+        {
+            // @TODO via RTC: 128982
+            //       ADU support
+            //       Call p9_*_setup for ADU operations
+            l_rc = SBE_SEC_COMMAND_NOT_SUPPORTED;
+            break;
+        }
+
+        // if p9_pba_setup returns error
+        if( l_fapiRc != FAPI2_RC_SUCCESS )
+        {
+            SBE_ERROR(SBE_FUNC" p9_pba_setup Failed");
+
+             // Respond with HWP FFDC
+            l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                                 SBE_SEC_GENERIC_FAILURE_IN_EXECUTION );
+            l_ffdc.setRc(l_fapiRc);
+
+            break;
+        }
+
+        SBE_DEBUG(SBE_FUNC "l_numGranules=[0x%08X]", l_numGranules);
+        uint64_t l_numAccesses = 0;
+
+        if ((l_numGranules != 0) &&
+            (l_numGranules <
+            (l_dataLenCacheLineAligned - l_numCacheLineCompleted)))
+        {
+            l_numAccesses = l_numGranules;
+        }
+        else
+        {
+            l_numAccesses =
+                l_dataLenCacheLineAligned - l_numCacheLineCompleted;
+        }
+
+        uint64_t l_numCurrentAccess = 0;
+        while (l_numCurrentAccess < l_numAccesses)
+        {
+            bool l_lastGranule = false;
+            bool l_firstGranule = false;
+
+            // @TODO via RTC: 128982
+            //       ADU support
+            //       Need 8Byte alignment for ADU operations
+            uint32_t l_dataFifo[32] ; // 128Byte granule for PBA access
+
+            if (l_numCurrentAccess == (l_numGranules - 1))
+            {
+                l_lastGranule = true;
+            }
+
+            if (l_numCurrentAccess == 0)
+            {
+                l_firstGranule = true;
+            }
+
+            // If this is putmem request,
+            // read input data from the upstream FIFO
+            if (!i_flagGetOrPut)
+            {
+                // @TODO via RTC: 128982
+                //       Use a granule variable
+                l_len2dequeue = 32;
+
+                l_rc = sbeUpFifoDeq_mult (l_len2dequeue,
+                                         (uint32_t *)&l_dataFifo,
+                                          false);
+
+                // If there was an underlying FIFO operation failure
+                if (l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
+                {
+                    // Let command processor routine to handle the RC.
+                    break;
+                }
+            }
+
+            // Call PBA access HWP for PBA write or read request
+            l_fapiRc = p9_pba_access ( l_proc, l_pbaAddr,
+                                       i_flagGetOrPut,
+                                       l_isFastMode,
+                                       l_firstGranule,
+                                       l_lastGranule,
+                                       (uint8_t *)&l_dataFifo);
+
+            // if p9_pba_access returns error
+            if( l_fapiRc != FAPI2_RC_SUCCESS )
+            {
+                SBE_ERROR(SBE_FUNC" p9_pba_access Failed");
+
+                // Respond with HWP FFDC
+                l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
+                                 SBE_SEC_GENERIC_FAILURE_IN_EXECUTION );
+                l_ffdc.setRc(l_fapiRc);
+
+                break;
+            }
+
+            // If this is a getmem request,
+            // need to push the data into the downstream FIFO
+            if (i_flagGetOrPut)
+            {
+                // Break out on underlying FIFO operational error
+                if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+                {
+                    break;
+                }
+
+                uint32_t l_len = 32;
+                l_rc = sbeDownFifoEnq_mult (l_len, (uint32_t *)&l_dataFifo);
+
+                // If FIFO failure
+                if (l_rc != SBE_SEC_OPERATION_SUCCESSFUL)
+                {
+                    // Let command processor routine to handle the RC.
+                    break;
+                }
+            }
+            l_numCacheLineCompleted++;
+            l_numCurrentAccess++;
+
+        } // End inner while loop
+
+        if ( (l_fapiRc != FAPI2_RC_SUCCESS) ||
+             (l_rc != SBE_SEC_OPERATION_SUCCESSFUL) )
+        {
+            break;
+        }
+
+        // @TODO via RTC: 128982
+        //       Use a granule variable
+        l_pbaAddr += 128 * l_numCacheLineCompleted;
+
+    } // End..while (l_numCacheLineCompleted < l_dataLenCacheLineAligned);
+
+    // Now build and enqueue response into downstream FIFO
+    do
+    {
+        // If there was a FIFO error, will skip sending the response,
+        // instead give the control back to the command processor thread
+        if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+        {
+            break;
+        }
+
+        l_len2dequeue = 0;
+        // If there was a HWP failure for putmem request,
+        // need to Flush out upstream FIFO, until EOT arrives
+        if (!i_flagGetOrPut)
+        {
+            if ( l_fapiRc != FAPI2_RC_SUCCESS )
+            {
+                l_rc = sbeUpFifoDeq_mult(l_len2dequeue, NULL,
+                                     true, true);
+            }
+            // For other success paths, just attempt to offload
+            // the next entry, which is supposed to be the EOT entry
+            else
+            {
+                l_rc = sbeUpFifoDeq_mult(l_len2dequeue, NULL, true);
+            }
+        }
+
+        // Break out on underlying FIFO operational error
+        if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+        {
+            break;
+        }
+
+        // first enqueue the length of data actually written
+        uint32_t l_len = 1;
+        uint32_t l_respLen = l_numCacheLineCompleted*8*16;
+        l_rc = sbeDownFifoEnq_mult ( l_len, &l_respLen );
+
+        if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+        {
+            break;
+        }
+
+        // Now enqueue the minimum response header
+        uint32_t l_dist2Hdr = 1;
+        l_len = sizeof(l_respHdr) / sizeof(uint32_t);
+        l_rc = sbeDownFifoEnq_mult ( l_len, reinterpret_cast<uint32_t *>
+                                                 (&l_respHdr) );
+
+        if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+        {
+            break;
+        }
+
+        l_dist2Hdr += l_len;
+
+        // Enqueue FFDC data if there is one
+        if( l_ffdc.getRc() )
+        {
+            l_len = sizeof(l_ffdc) / sizeof(uint32_t);
+            l_rc = sbeDownFifoEnq_mult ( l_len,
+                        reinterpret_cast<uint32_t *>(&l_ffdc) );
+            if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+            {
+                break;
+            }
+
+            l_dist2Hdr += l_len;
+
+            // @TODO via 129076:
+            //       Need to add FFDC data as well.
+        }
+
+        l_len = sizeof(l_dist2Hdr) / sizeof(uint32_t);
+        l_rc = sbeDownFifoEnq_mult ( l_len, &l_dist2Hdr);
+
+        if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL )
+        {
+            break;
+        }
+
+    } while(false);
+
+    return l_rc;
+    #undef SBE_FUNC
+}
+
+//////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbePutMem (uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbePutMem "
+    SBE_ENTER(SBE_FUNC);
+
+    return sbeMemAccess_Wrap (false);
+
+    #undef SBE_FUNC
+}
+
+/////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbeGetMem (uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbeGetMem "
+    SBE_ENTER(SBE_FUNC);
+
+    return sbeMemAccess_Wrap (true);
+
+    #undef SBE_FUNC
+}
+
+/////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbeGetSram (uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbeGetSram "
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+
+    return l_rc;
+    #undef SBE_FUNC
+}
+
+/////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
+uint32_t sbePutSram (uint8_t *i_pArg)
+{
+    #define SBE_FUNC " sbePutSram "
+    uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+
+    return l_rc;
+    #undef SBE_FUNC
+}
diff --git a/sbe/sbefw/sbecmdmemaccess.H b/sbe/sbefw/sbecmdmemaccess.H
new file mode 100644
index 00000000..b8c01922
--- /dev/null
+++ b/sbe/sbefw/sbecmdmemaccess.H
@@ -0,0 +1,50 @@
+/*
+ * @file: ppe/sbe/sbefw/sbecmdmemaccess.H
+ *
+ * @brief This file contains the Interfaces for the Memory Access chip-ops
+ *
+ */
+
+#ifndef __SBEFW_SBECMDMEMACCESS_H
+#define __SBEFW_SBECMDMEMACCESS_H
+
+#include <stdint.h>
+
+/**
+  * @brief sbeGetMem : Implements SBE Get Memory ChipOp
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbeGetMem (uint8_t *i_pArg);
+
+/**
+  * @brief sbePutMem : Implements SBE Put Memory ChipOp
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbePutMem  (uint8_t *i_pArg);
+
+/**
+ * @brief sbeGetSram : Implements SBE Get SRAM ChipOp
+ *
+ * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+ *
+ * @return    Rc from the FIFO access utility
+ */
+uint32_t sbeGetSram (uint8_t *i_pArg);
+
+/**
+ * @brief sbePutSram : Implements SBE Put SRAM ChipOp
+ *
+ * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+ *
+ * @return    Rc from the FIFO access utility
+ */
+uint32_t sbePutSram (uint8_t *i_pArg);
+
+
+#endif /* __SBEFW_SBECMDMEMACCESS_H */
diff --git a/sbe/sbefw/sbecmdparser.C b/sbe/sbefw/sbecmdparser.C
index 1cfa21a7..9d20d099 100644
--- a/sbe/sbefw/sbecmdparser.C
+++ b/sbe/sbefw/sbecmdparser.C
@@ -9,6 +9,7 @@
 #include "sbecmdscomaccess.H"
 #include "sbecmdiplcontrol.H"
 #include "sbecmdgeneric.H"
+#include "sbecmdmemaccess.H"
 #include "sbetrace.H"
 #include "sbe_sp_intf.H"
 
@@ -71,6 +72,33 @@ static sbeCmdStruct_t g_sbeGenericCmdArray [] =
 
 };
 
+//////////////////////////////////////////////////////////////
+// @brief g_sbeMemoryAccessCmdArray
+//
+//////////////////////////////////////////////////////////////
+static sbeCmdStruct_t g_sbeMemoryAccessCmdArray [] =
+{
+    {sbeGetMem,
+     SBE_CMD_GETMEM,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+
+    {sbePutMem,
+     SBE_CMD_PUTMEM,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+
+    {sbeGetSram,
+     SBE_CMD_GETSRAM,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+
+    {sbePutSram,
+     SBE_CMD_PUTSRAM,
+     SBE_FENCE_AT_CONTINUOUS_IPL,
+    },
+};
+
 
 ////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////
@@ -102,6 +130,11 @@ uint8_t sbeGetCmdStructAttr (const uint8_t  i_cmdClass,
             *o_ppCmd    = (sbeCmdStruct_t*)g_sbeGenericCmdArray;
             break;
 
+        case SBE_CMD_CLASS_MEMORY_ACCESS:
+            l_numCmds = sizeof(g_sbeMemoryAccessCmdArray) /
+                        sizeof(sbeCmdStruct_t);
+            *o_ppCmd  = (sbeCmdStruct_t*)g_sbeMemoryAccessCmdArray;
+            break;
 
         // This will grow with each class of chipOp in future
         default:
diff --git a/sbe/sbefw/sbefifo.H b/sbe/sbefw/sbefifo.H
index 74386cb5..9991f57e 100644
--- a/sbe/sbefw/sbefifo.H
+++ b/sbe/sbefw/sbefifo.H
@@ -209,7 +209,6 @@ extern inline uint32_t sbeDownFifoEnq (const uint64_t i_data)
   */
 extern inline uint32_t sbeDownFifoGetStatus (uint64_t *o_data)
 {
-    SBE_DEBUG(">sbeDownFifoStatus");
     return getscom_abs(SBE_DOWNSTREAM_FIFO_STATUS, o_data);
 }
 
diff --git a/sbe/sbefw/sbefwfiles.mk b/sbe/sbefw/sbefwfiles.mk
index e8012cb7..4d169799 100644
--- a/sbe/sbefw/sbefwfiles.mk
+++ b/sbe/sbefw/sbefwfiles.mk
@@ -9,6 +9,7 @@ SBEFW-CPP-SOURCES += pool.C
 SBEFW-CPP-SOURCES += sbecmdgeneric.C
 SBEFW-CPP-SOURCES += sbeFifoMsgUtils.C
 SBEFW-CPP-SOURCES += attr.C
+SBEFW-CPP-SOURCES += sbecmdmemaccess.C
 SBEFW-C-SOURCES =
 SBEFW-S-SOURCES =