PPE FAPI2 resync changes

- Tested SCOMs (absolute and FAPI_TRY) on GPE SIMICS without RCs
  to chip target OCB registers.  GPE SIMICS model does not have
  registers in non-chip level targets.
- Testing on GPE SIMICS with RCs fails with illegal addresses in
  thread local storage initialization
- Added ./ppe/sbe/plat platform specifics
- Added missing ./ppe/hwpf/plat/include files
- Added missing fapi2AttributeService.H
- Add PPE specific (though likely temporary) versions of buffer.H
  (to deal with compile errors for "units_per_bit()" to "units_per_bit"
  and "bit_length()" to "bit_length") and return_code.H (to include
  return_code_defs.H)
- Add ppe/plat/include/plat_error_scope.H to deal with SBE return code
  tracing
- Deleted old file version
- Added local version of buffer.H
- Move current_err to global variable (vs thread local storage);
  This removes #include <thread>.
- Enable PK_TRACE under FAPI_* Trace macros
- Added plat_attributes.H to include generated platform specific files
- Added -DUSE_PK_APP_CFG to img_defs.mk

Change-Id: Ice6c24a5091d3cf8eb4e4d93a0d139086126df95
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18239
Reviewed-by: Derk Rembold <rembold@de.ibm.com>
Tested-by: Derk Rembold <rembold@de.ibm.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/sbe/image/Makefile b/sbe/image/Makefile
index 0526a1be..a895c1b8 100644
--- a/sbe/image/Makefile
+++ b/sbe/image/Makefile
@@ -220,6 +220,13 @@ run: $(OBJDIR)/$(IMAGE_SEEPROM_NAME).out
 
 
 
+# load and run the SBE image in a GPE simics environment
+run: $(OBJDIR)/$(IMAGE_NAME).out
+	$(SIMICS_WS)/simics \
+		-e '$$occ_gpe0_binary_to_load=$(OBJDIR)/$(IMAGE_NAME).out' modelsetup.simics
+
+
+
 #Add dependencies to header files
 ifneq ($(MAKECMDGOALS),clean)
 include $(OBJS:.o=.d)