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author | Santosh Puranik <santosh.puranik@in.ibm.com> | 2016-05-03 05:04:47 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-05-06 05:37:29 -0400 |
commit | 8a02e8a8ddb68329beb1be70011b42ecbf705e56 (patch) | |
tree | e6115d75f29d9f41c05a544c7832c68176608544 /sbe/build/citest/etc/patches | |
parent | 9f1b774d571fec417188b5912b01e1edd22da345 (diff) | |
download | talos-sbe-8a02e8a8ddb68329beb1be70011b42ecbf705e56.tar.gz talos-sbe-8a02e8a8ddb68329beb1be70011b42ecbf705e56.zip |
Patch for powermgmt.act
Change-Id: I14d9c208d7ec298a6499fe09890247c046496471
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23988
Tested-by: Jenkins Server
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'sbe/build/citest/etc/patches')
-rw-r--r-- | sbe/build/citest/etc/patches/powermgmt.act.patch | 1057 |
1 files changed, 1057 insertions, 0 deletions
diff --git a/sbe/build/citest/etc/patches/powermgmt.act.patch b/sbe/build/citest/etc/patches/powermgmt.act.patch new file mode 100644 index 00000000..efb03845 --- /dev/null +++ b/sbe/build/citest/etc/patches/powermgmt.act.patch @@ -0,0 +1,1057 @@ +43,112d42 +< ## Actions for Procedure - p9_pm_occ_control +< ## +< +< CAUSE_EFFECT { +< LABEL=[PPC405 HALT] +< WATCH=[REG(0x0006D006)] +< CAUSE: TARGET=[REG(0x0006D006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 02000000 00000000)] +< #suet PPC405_UNHALT:tc1- EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,OFF] BIT=[31] +< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31] +< } +< +< ## +< ## Actions for Procedure - p9_pm_occ_gpe_init +< ## +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE0 HALT] +< WATCH=[REG(0x00060010)] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE1 HALT] +< WATCH=[REG(0x00062010)] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0] +< } +< +< # Upon writing the PU_OCB_PIB_OCR[DBG_HALT} bit, set the OCCLFIR_PPC405_DBGSTOPACK_BIT. +< CAUSE_EFFECT { +< LABEL=[PPC405 SAFE_HALT] +< WATCH=[REG(00x0006D002)] +< CAUSE: TARGET=[REG(0x0006D002)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00200000 00000000)] +< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31] +< } +< +< +< ## +< ## Actions for Procedure - p9_pm_occ_gpe_init +< ## +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE0 HALT] +< WATCH=[REG(0x00060010)] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE1 HALT] +< WATCH=[REG(0x00062010)] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0] +< } +< +< +< ## +134,409c64 +< +< ## Core0 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x200F0110)] +< CAUSE: TARGET=[REG(0x200F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[REG(0x200F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core0 End +< +< ## Core1 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x210F0110)] +< CAUSE: TARGET=[REG(0x210F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)] +< EFFECT: TARGET=[REG(0x210F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x210F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x210F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x210F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core1 End +< +< ## Core2 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x220F0110)] +< CAUSE: TARGET=[REG(0x220F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x220F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[REG(0x220F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x220F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x220F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x220F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core2 End +< +< ## Core3 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x230F0110)] +< CAUSE: TARGET=[REG(0x230F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)] +< EFFECT: TARGET=[REG(0x230F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x230F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x230F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x230F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core3 End +< +< ## Core4 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x240F0110)] +< CAUSE: TARGET=[REG(0x240F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)] +< EFFECT: TARGET=[REG(0x240F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x240F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x240F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x240F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core4 End +< +< ## Core5 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x250F0110)] +< CAUSE: TARGET=[REG(0x250F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)] +< EFFECT: TARGET=[REG(0x250F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x250F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x250F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x250F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core5 End +< +< ## Core6 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x260F0110)] +< CAUSE: TARGET=[REG(0x260F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x260F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[REG(0x260F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x260F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x260F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x260F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core6 End +< +< ## Core7 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x270F0110)] +< CAUSE: TARGET=[REG(0x270F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)] +< EFFECT: TARGET=[REG(0x270F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x270F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x270F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x270F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core7 End +< +< ## Core8 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x280F0110)] +< CAUSE: TARGET=[REG(0x280F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)] +< EFFECT: TARGET=[REG(0x280F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x280F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x280F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core8 End +< +< ## Core9 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x290F0110)] +< CAUSE: TARGET=[REG(0x290F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)] +< EFFECT: TARGET=[REG(0x290F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x290F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x290F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x290F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core9 End +< +< ## Core10 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2A0F0110)] +< CAUSE: TARGET=[REG(0x2A0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)] +< EFFECT: TARGET=[REG(0x2A0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2A0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2A0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2A0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core10 End +< +< ## Core11 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2B0F0110)] +< CAUSE: TARGET=[REG(0x2B0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)] +< EFFECT: TARGET=[REG(0x2B0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2B0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2B0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2B0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core11 End +< +< ## Core12 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2C0F0110)] +< CAUSE: TARGET=[REG(0x2C0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)] +< EFFECT: TARGET=[REG(0x2C0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2C0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2C0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2C0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core12 End +< +< ## Core13 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2D0F0110)] +< CAUSE: TARGET=[REG(0x2D0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)] +< EFFECT: TARGET=[REG(0x2D0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2D0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2D0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2D0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core13 End +< +< ## Core14 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2E0F0110)] +< CAUSE: TARGET=[REG(0x2E0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)] +< EFFECT: TARGET=[REG(0x2E0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2E0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2E0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2E0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core14 End +< +< ## Core15 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2F0F0110)] +< CAUSE: TARGET=[REG(0x2F0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)] +< EFFECT: TARGET=[REG(0x2F0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2F0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2F0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2F0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core15 End +< +< ## Core16 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x300F0110)] +< CAUSE: TARGET=[REG(0x300F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)] +< EFFECT: TARGET=[REG(0x300F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x300F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x300F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x300F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core16 End +< +< ## Core17 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x310F0110)] +< CAUSE: TARGET=[REG(0x310F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)] +< EFFECT: TARGET=[REG(0x310F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x310F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x310F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x310F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core17 End +< +< ## Core18 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x320F0110)] +< CAUSE: TARGET=[REG(0x320F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)] +< EFFECT: TARGET=[REG(0x320F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x320F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x320F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x320F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core18 End +< +< ## Core19 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x330F0110)] +< CAUSE: TARGET=[REG(0x330F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)] +< EFFECT: TARGET=[REG(0x330F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x330F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x330F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x330F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core19 End +< +< ## Core20 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x340F0110)] +< CAUSE: TARGET=[REG(0x340F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)] +< EFFECT: TARGET=[REG(0x340F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x340F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x340F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x340F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core20 End +< +< ## Core21 Start +< CAUSE_EFFECT { +--- +> CAUSE_EFFECT CHIPLETS ec { +411,478c66,89 +< WATCH=[REG(0x350F0110)] +< CAUSE: TARGET=[REG(0x350F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)] +< EFFECT: TARGET=[REG(0x350F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x350F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x350F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x350F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core21 End +< +< ## Core22 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x360F0110)] +< CAUSE: TARGET=[REG(0x360F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)] +< EFFECT: TARGET=[REG(0x360F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x360F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x360F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x360F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core22 End +< +< ## Core23 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x370F0110)] +< CAUSE: TARGET=[REG(0x370F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)] +< EFFECT: TARGET=[REG(0x370F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x370F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x370F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x370F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core23 End +< +< ## +< # Actions for Procedure - p9_block_wakeup_intr +< ## +< +< # Core Power Management Mode Register +< CAUSE_EFFECT { +< LABEL=[CPMMR Write OR of PPM Write Override] +< WATCH=[REG(0x290F0108)] +< CAUSE: TARGET=[REG(0x290F0108)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,ON] BIT=[1] +< } +< +< CAUSE_EFFECT { +< LABEL=[CPMMR Write CLEAR of PPM Write Override] +< WATCH=[REG(0x290F0107)] +< CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[1] +< } +< +< # General Power Management Mode Register +< CAUSE_EFFECT { +< LABEL=[GPMMR Write OR of Block Wakeup Events] +< WATCH=[REG(0x290F0102)] +< CAUSE: TARGET=[REG(0x290F0102)] OP=[BIT,ON] BIT=[6] +< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[6] +< } +< +< CAUSE_EFFECT { +< LABEL=[GPMMR Write CLEAR of PPM Write Override] +< WATCH=[REG(0x290F0101)] +< CAUSE: TARGET=[REG(0x290F0101)] OP=[BIT,ON] BIT=[6] +< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[6] +--- +> WATCH=[REG(MYCHIPLET, 0x0F0110)] +> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F0110)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)] +> EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> } +> +> ## Action triggered when all threads are idle +> # Used for istep 16 to have hostboot properly wake up on SBE-set PSU +> # interrupt as well as to have p9_sbe_check_master_stop15.C properly +> # execute in firmware simics. +> # TODO: RTC 147787 +> CAUSE_EFFECT CHIPLETS ec { +> LABEL=[Master Winkle LPCR] +> WATCH=[IDLESTATE(MYCHIPLET,0x0)] +> # look for stop15 +> CAUSE: TARGET=[IDLESTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,0F000000)] MASK=[LITERAL(32,FF000000)] +> # Restore LPCR for wake-up options. +> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[17] +> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[49] +> # Set required C_PPM_SSHOTR register required by procedure +> EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,8BB00000 FFFFFFFF)] +514c125 +< ## Actions for p9_pm_ocb_init +--- +> # Actions for Procedure - p9_hcd_core_poweron / p9_hcd_cache_poweron +517,524c128,133 +< CAUSE_EFFECT { +< LABEL=[Channel 0 linear stream] +< WATCH=[REG(0x0006D013)] +< WATCH=[REG(0x0006D012)] +< CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D012)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,OFF] BIT=[5] +--- +> CAUSE_EFFECT CHIPLETS ec cache { +> LABEL=[Power on core/cache vdd pfet then fsm is idle and sense is enabled] +> WATCH=[REG(MYCHIPLET, 0x0F011A)] +> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[0] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[42] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[0] +527,1071c136 +< CAUSE_EFFECT { +< LABEL=[Channel 1 linear stream] +< WATCH=[REG(0x0006D033)] +< WATCH=[REG(0x0006D032)] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 1 circular push interupt enable] +< WATCH=[REG(0x0006D033)] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[3] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[3] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 1 circular push interrupt disable] +< WATCH=[REG(0x0006D033)] +< WATCH=[REG(0x0006D032)] +< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[3] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[3] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 2 linear stream] +< WATCH=[REG(0x0006D053)] +< WATCH=[REG(0x0006D052)] +< CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D052)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,OFF] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 3 linear stream] +< WATCH=[REG(0x0006D073)] +< WATCH=[REG(0x0006D072)] +< CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D072)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,OFF] BIT=[5] +< ## Actions for Procedure - p9_setup_evid +< ## +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Write data register 0B] +< WATCH=[REG(0x0006C718)] +< CAUSE: TARGET=[REG(0x0006C718)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Status register 0B] +< WATCH_READ=[REG(0x0006C716)] +< CAUSE: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,OFF] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Write data register 1B] +< WATCH=[REG(0x0006C738)] +< CAUSE: TARGET=[REG(0x0006C738)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Status register 1B] +< WATCH_READ=[REG(0x0006C736)] +< CAUSE: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,OFF] BIT=[0] +< } +< +< ## Core 0 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x200F011A)] +< CAUSE: TARGET=[REG(0x200F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x200F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x200F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 0 End +< ## Core 1 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x210F011A)] +< CAUSE: TARGET=[REG(0x210F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x210F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x210F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 1 End +< ## Core 2 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x220F011A)] +< CAUSE: TARGET=[REG(0x220F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x220F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x220F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 2 End +< ## Core 3 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x230F011A)] +< CAUSE: TARGET=[REG(0x230F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x230F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x230F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 3 End +< ## Core 4 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x240F011A)] +< CAUSE: TARGET=[REG(0x240F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x240F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x240F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 4 End +< ## Core 5 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x250F011A)] +< CAUSE: TARGET=[REG(0x250F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x250F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x250F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 5 End +< ## Core 6 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x260F011A)] +< CAUSE: TARGET=[REG(0x260F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x260F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x260F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 6 End +< ## Core 7 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x270F011A)] +< CAUSE: TARGET=[REG(0x270F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x270F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x270F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 7 End +< ## Core 8 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x280F011A)] +< CAUSE: TARGET=[REG(0x280F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x280F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x280F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 8 End +< ## Core 9 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x290F011A)] +< CAUSE: TARGET=[REG(0x290F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x290F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x290F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 9 End +< ## Core 10 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2a0F011A)] +< CAUSE: TARGET=[REG(0x2a0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2a0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2a0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 10 End +< ## Core 11 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2b0F011A)] +< CAUSE: TARGET=[REG(0x2b0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2b0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2b0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 11 End +< ## Core 12 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2c0F011A)] +< CAUSE: TARGET=[REG(0x2c0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2c0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2c0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 12 End +< ## Core 13 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2d0F011A)] +< CAUSE: TARGET=[REG(0x2d0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2d0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2d0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 13 End +< ## Core 14 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2e0F011A)] +< CAUSE: TARGET=[REG(0x2e0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2e0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2e0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 14 End +< ## Core 15 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2f0F011A)] +< CAUSE: TARGET=[REG(0x2f0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2f0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2f0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 15 End +< ## Core 16 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x300F011A)] +< CAUSE: TARGET=[REG(0x300F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x300F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x300F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 16 End +< ## Core 17 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x310F011A)] +< CAUSE: TARGET=[REG(0x310F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x310F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x310F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 17 End +< ## Core 18 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x320F011A)] +< CAUSE: TARGET=[REG(0x320F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x320F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x320F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 18 End +< ## Core 19 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x330F011A)] +< CAUSE: TARGET=[REG(0x330F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x330F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x330F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 19 End +< ## Core 20 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x340F011A)] +< CAUSE: TARGET=[REG(0x340F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x340F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x340F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 20 End +< ## Core 21 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x350F011A)] +< CAUSE: TARGET=[REG(0x350F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x350F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x350F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 21 End +< ## Core 22 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x360F011A)] +< CAUSE: TARGET=[REG(0x360F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x360F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x360F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 22 End +< ## Core 23 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x370F011A)] +< CAUSE: TARGET=[REG(0x370F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x370F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x370F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 23 End +< ## EQ 0 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x100F011A)] +< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x100F011A)] +< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 0 End +< +< ## EQ 1 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x110F011A)] +< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x110F011A)] +< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 1 End +< +< ## EQ 2 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x120F011A)] +< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x120F011A)] +< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 2 End +< +< ## EQ 3 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x130F011A)] +< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x130F011A)] +< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 3 End +< +< ## EQ 4 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +--- +> CAUSE_EFFECT CHIPLETS cache { +1073,1084c138,141 +< WATCH=[REG(0x140F011A)] +< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x140F011A)] +< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[2] +--- +> WATCH=[REG(MYCHIPLET, 0x0F011A)] +> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[2] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[50] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[2] +1087,1112d143 +< ## EQ 4 End +< +< ## EQ 5 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x150F011A)] +< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x150F011A)] +< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 5 End +< |