p9_sbe_select_ex Level 2 update

- add PFET Delay settings for booting Quads/Cores for istep 4
- Delays controled the -DPRODUCT_DEFAULT_PFET_DELAY compile switch
   - if not defined (aka simulation), delays only 1 cycle between steps
     (on or off)
   - if defined, fixed delays based on the fastest nest times to meet
      minimum times for hardware (turn on);  turn off is fast
- Backed out the vector use reduction as this presented SBE platform
problems.  Those will be addressed in RTC 151413
- Per discussion to have ALL good core/cache and EX Multicast groups
setup in p9_sbe_chiplet_reset, redid this procedure to only REMOVE
chiplets from groups 3, 4, 5, and 6 in single mode (the default) so
as to leave only one core n group 3 with the associated EQ in group 4
and the assoicated EX in either group 5 or 6 depending on even or odd
EX number.  If ALL mode (controlled by an attribute), no MC groups are
modified.
- Vector removal was addressed by removing some error checking for the
sake of SBE code space.
- Added default setting of QSSR that all L2s and Quads are stopped

Change-Id: I650ab91b72cce86d9b7f319e988cccc72a691abd
RTC: 151360
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23138
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23139
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

0 files changed, 0 insertions, 0 deletions