Procedures modified for DD1 changes

Change-Id: Iaff301338637dac67457330698fa85383012186d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27973
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27974
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

5 files changed, 60 insertions, 5 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index d63d89bb..f6272ec7 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -522,12 +522,29 @@ fapi_try_exit:
 static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
 {
+    fapi2::buffer<uint8_t> l_read_attr;
     FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup: Entering ...");
 
     //Setting NET_CTRL0 register value
-    //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE
-    FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
-                            p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE));
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target_cplt.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    FAPI_DBG("Disable local clock gating VITAL");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING,
+                           l_chip, l_read_attr));
+
+    if (l_read_attr)
+    {
+        //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
+                                p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1));
+    }
+    else
+    {
+        //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
+                                p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE));
+    }
+
     //Setting NET_CTRL1 register value
     //NET_CTRL1 = p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE
     FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL1,
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
index 0d615ed7..0d416ace 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
@@ -54,7 +54,8 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants
     MCGR_CNFG_SETTING_GROUP4 = 0xF0001C0000000000ull,
     MCGR_CNFG_SETTING_GROUP5 = 0xF4001C0000000000ull,
     MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull,
-    NET_CNTL0_HW_INIT_VALUE = 0x7C16222000000000ull,
+    NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull,
+    NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull,
     HANG_PULSE_0X10 = 0x10,
     HANG_PULSE_0X0F = 0x0F,
     HANG_PULSE_0X06 = 0x06,
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
index e97e1a8d..87103f02 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -32,7 +32,6 @@
 
 //## auto_generated
 #include "p9_sbe_tp_chiplet_init1.H"
-
 #include <p9_perv_scom_addresses.H>
 #include <p9_perv_scom_addresses_fld.H>
 #include <p9_perv_sbe_cmn.H>
@@ -50,8 +49,25 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
 {
     fapi2::buffer<uint16_t> l_regions;
     fapi2::buffer<uint64_t> l_data64;
+    fapi2::buffer<uint8_t> l_read_attr;
     FAPI_INF("p9_sbe_tp_chiplet_init1: Entering ...");
 
+    FAPI_DBG("Disable local clock gating VITAL");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING,
+                           i_target_chip, l_read_attr));
+    FAPI_DBG("l_read_attr is %d", l_read_attr);
+
+    if (l_read_attr)
+    {
+        //Getting PERV_CTRL0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64))
+        //PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC = 1
+        l_data64.setBit<PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM,
+                                l_data64));
+    }
+
     FAPI_DBG("Release PCB Reset");
     //Setting ROOT_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
diff --git a/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 72918cce..2969ead1 100644
--- a/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -158,4 +158,21 @@
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 only: disable local clock gating VITAL. This is used by the 
+      procedure for p9_sbe_tp_chiplet_init1 and p9_Sbe_chiplet_reset.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 </attributes>
diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 0797fa60..b99ffadc 100644
--- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -531,4 +531,8 @@ attribute tank
            <name>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</name>
            <virtual/>
   </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</name>
+           <virtual/>
+  </entry>
 </entries>