Adding target for lco_m, changed flags, changed INF to DBG

Change-Id: Ia390e82f22aea05e1fc24f203c0e2cfdfcc71a2d
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20576
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22233
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

6 files changed, 218 insertions, 227 deletions

diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_access.C b/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
index b498aeff..160558ba 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
@@ -53,7 +53,7 @@ extern "C" {
         fapi2::ReturnCode rc1;
 
         // mark HWP entry
-        FAPI_INF("p9_pba_access: Entering ...\n");
+        FAPI_INF("Entering ...\n");
 
         //if read
         if (i_rnw)
@@ -66,24 +66,20 @@ extern "C" {
             rc1 = p9_pba_coherent_pba_write(i_target, i_address, i_flags, io_data);
         }
 
-        //If we are not in fastmode we want to check the status after every read
-        if (!rc1 && !(i_flags >> (31 - FLAG_FASTMODE)))
+        //If we are not in fastmode or this is the last granule, we want to check the status
+        if (!rc1)
         {
-            rc1 = p9_pba_coherent_status_check(i_target);
-        }
-
-        //if it's the last Read/Write
-        if (i_lastGranule)
-        {
-            //If we are in fastmode this will be the first and only time that we check the status
-            if (!rc1 && (i_flags >> (31 - FLAG_FASTMODE)))
+            if ((i_lastGranule) || !(i_flags & FLAG_FASTMODE))
             {
                 rc1 = p9_pba_coherent_status_check(i_target);
-            }
 
-            //Clean up the PBA since it's the last read/write and it has been finished
-            FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target),
-                     "Error doing p9_pba_coherent_cleanup_pba");
+                if (i_lastGranule)
+                {
+                    //Clean up the PBA since it's the last read/write and it has been finished
+                    FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target),
+                             "Error doing p9_pba_coherent_cleanup_pba");
+                }
+            }
         }
 
         // mark HWP exit
@@ -102,7 +98,7 @@ extern "C" {
             fapi2::current_err = rc1;
         }
 
-        FAPI_INF("p9_pba_access: Exit ...\n");
+        FAPI_INF("Exit ...\n");
         return fapi2::current_err;
     }
 
diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
index d6497c75..272242ab 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
@@ -33,74 +33,137 @@
 // Includes
 //-----------------------------------------------------------------------------------
 #include <p9_pba_coherent_utils.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_fbc_utils.H>
 
 extern "C"
 {
     //---------------------------------------------------------------------------------
     // Constant definitions
     //---------------------------------------------------------------------------------
-    //These may be defined elsewhere and may change, but for now I have included them
-    //here TODO These will live in the p9_fbc_utils header - Change when this is ready
-    const uint64_t PROC_FBC_UTILS_CACHELINE_MASK = 0x7FULL;
-    const uint64_t PROC_FBC_UTILS_FBC_MAX_ADDRESS = ((1ULL << 50) - 1ULL);
-    //TODO Joe commented here that it's in p9_fbc_utils uner http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20275
-    //Right now not adding this because Basabjit just needs the changes that I had to make to get his to run, I will change
-    //this after the long weekend.
 
+    //PBA Delay Constants
+    const uint32_t PBA_SLVRST_DELAY_HW_NS = 1000;
+    const uint32_t PBA_SLVRST_DELAY_SIM_CYCLES = 200;
+    const uint32_t WRITE_DELAY_HW_NS = 100;
+    const uint32_t WRITE_DELAY_SIM_CYCLES = 20;
+    const uint32_t PBA_BAR_SCOPE_LOCAL_NODE = 0;
+
+//PBA Slave Control register field/bit definitions
+    const uint32_t PBA_SLVCTL_ENABLE_BIT = 0;
+    const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_START_BIT = 1;
+    const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_END_BIT = 3;
+    const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT = 5;
+    const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_END_BIT = 7;
+    const uint32_t PBA_SLVCTL_WRITE_TTYPE_START_BIT = 8;
+    const uint32_t PBA_SLVCTL_WRITE_TTYPE_END_BIT = 10;
+    const uint32_t PBA_SLVCTL_READ_TTYPE_BIT = 15;
+    const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT = 16;
+    const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_END_BIT = 17;
+    const uint32_t PBA_SLVCTL_READ_BUF_INVALIDATE_CTL_BIT = 18;
+    const uint32_t PBA_SLVCTL_WRITE_BUF_PAIR_ALLOCATION_BIT = 19;
+    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_A_ALLOCATION_BIT = 20;
+    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_B_ALLOCATION_BIT = 21;
+    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT = 22;
+    const uint32_t PBA_SLVCTL_DISABLE_WRITE_GATHER_BIT = 24;
+    const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT = 25;
+    const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT = 27;
+    const uint32_t PBA_SLVCTL_WRITE_TSIZE_START_BIT = 28;
+    const uint32_t PBA_SLVCTL_WRITE_TSIZE_END_BIT = 35;
+    const uint32_t PBA_SLVCTL_EXT_ADDR_START_BIT = 36;
+    const uint32_t PBA_SLVCTL_EXT_ADDR_END_BIT = 49;
+
+    const uint32_t PBA_SLVCTL_EXTADDR_SHIFT = 27;
+    const uint32_t PBA_SLVCTL_EXTADDR_MASK = 0x3fff;
+
+//PBA Slave Reset register field/bit definitions
+    const uint32_t PBA_SLVRST_SET_START_BIT = 0;
+    const uint32_t PBA_SLVRST_SET_END_BIT = 2;
+    const uint32_t PBA_SLVRST_SLVCTL0_IN_PROG = 4;
+    const uint32_t PBA_SLVRST_SLVCTL1_IN_PROG = 5;
+    const uint32_t PBA_SLVRST_SLVCTL2_IN_PROG = 6;
+    const uint32_t PBA_SLVRST_SLVCTL3_IN_PROG = 7;
+    const uint32_t PBA_SLVRST_IN_PROG_START_BIT = 4;
+    const uint32_t PBA_SLVRST_IN_PROG_END_BIT = 7;
+    const uint32_t PBA_SLVRST_BUSY_START_BIT = 8;
+    const uint32_t PBA_SLVRST_BUSY_END_BIT = 11;
+    //mask to check if there is a PBA slave rest in progress and if the PBA Slave Control is busy
+    //if it is not all these bits 4:11 should be set to 0
+    const uint64_t PBA_SLVRST_BUSY_IN_PROG_MASK = 0xFF0000000000000ull;
+
+//PBA Read Buffer Valid Status field/bit definitions
+    const uint32_t PBA_RD_BUF_VALID_START_BIT = 33;
+    const uint32_t PBA_RD_BUF_VALID_END_BIT = 39;
+    const uint64_t PBA_RD_BUF_VALID_MASK = 0x7F000000ull;
+    const uint64_t PBA_RD_BUF_EMPTY =  0x1000000ull;
+
+//PBA Write Buffer Valid Status field/bit definitions
+    const uint32_t PBA_WR_BUF_VALID_START_BIT = 35;
+    const uint32_t PBA_WR_BUF_VALID_END_BIT = 39;
+    const uint64_t PBA_WR_BUF_VALID_MASK = 0x1F000000ull;
+    const uint64_t PBA_WR_BUF_EMPTY = 0x1000000ull;
+
+//PBA BAR register field/bit definitions
+    const uint32_t PBA_BAR_SCOPE_START_BIT = 0;
+    const uint32_t PBA_BAR_SCOPE_END_BIT = 2;
+    const uint32_t PBA_BAR_BASE_ADDRESS_START_BIT = 8;
+    const uint32_t PBA_BAR_BASE_ADDRESS_END_BIT = 43;
+    const uint32_t PBA_BAR_BASE_ADDRESS_SHIFT = 21;
+    const uint64_t PBA_BAR_BASE_ADDRESS_MASK = 0xFFFFFFFFFull;
+
+//PBA BAR Mask register field/bit definitions
+    const uint32_t PBA_BAR_MASK_START_BIT = 23;
+    const uint32_t PBA_BAR_MASK_END_BIT = 43;
 
     //---------------------------------------------------------------------------------
     // Function definitions
     //---------------------------------------------------------------------------------
 
-    /// @brief check that the address is cacheline aligned and within the fabric real address range
-    /// @param[in] i_target => P9 chip target
-    /// @param[in] i_address => starting address for PBA operation
-    /// @return FAPI_RC_SUCCESS if arguments are valid
     fapi2::ReturnCode p9_pba_coherent_utils_check_args(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address)
     {
 
-        FAPI_DBG("p9_pba_coherent_utils_check_args: Start");
+        FAPI_DBG("Start");
 
         //Check the address alignment
-        FAPI_ASSERT(!(i_address & PROC_FBC_UTILS_CACHELINE_MASK),
+        FAPI_ASSERT(!(i_address & P9_FBC_UTILS_CACHELINE_MASK),
                     fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
                         i_address),
-                    "p9_pba_coherent_utils_check_args: Address is not cacheline aligned");
+                    "Address is not cacheline aligned");
 
         //Make sure the address is within the PBA bounds
-        FAPI_ASSERT(i_address <= PROC_FBC_UTILS_FBC_MAX_ADDRESS,
+        FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
                     fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
                         i_address),
-                    "p9_pba_coherent_utils_check_args: Address exceeds supported fabric real address range");
+                    "Address exceeds supported fabric real address range");
 
     fapi_try_exit:
-        FAPI_INF("p9_pba_coherent_utils_check_args: End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-    /// @brief ensure that fabric is initialized and stop control is not set
-    ///           (by checkstop/mode switch), which if set would prohibit fabric
-    ///           commands from being broadcasted
-    /// @param[in] i_target => P9 chip target
-    /// @return FAPI_RC_SUCCESS if fabric is not stopped
     fapi2::ReturnCode p9_pba_coherent_utils_check_fbc_state(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     {
-        fapi2::ReturnCode rc;
-        FAPI_DBG("p9_pba_coherent_utils_check_fbc_state: Start");
-
-        //Make sure the fabric is initialized TODO Put in the functions that Joe just made in here
+        bool fbc_initialized = false;
+        bool fbc_running = false;
+        FAPI_DBG("Start");
+
+        //Make sure the fabric is initialized and running
+        FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, fbc_initialized, fbc_running),
+                 "Error from p9_fbc_utils_get_fbc_state");
+        FAPI_ASSERT(fbc_initialized
+                    && fbc_running, fapi2::P9_PBA_FBC_NOT_INITIALIZED_ERR().set_TARGET(i_target).set_INITIALIZED(
+                        fbc_initialized).set_RUNNING(
+                        fbc_running), "Fabric is not initialized or running");
 
-        //Make sure the fabric is running TODO Put in the functions that Joe just made in here
-        return rc;
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
     }
 
-    /// @brief calculates the number of 128 byte granules that can be read/written before setup needs to be run again
-    /// @param[in] i_target => P9 chip target
-    /// @param[in] i_address => starting address for PBA operation
-    /// @return number of 128 byte granules that can be read/written before setup needs to be run again
     fapi2::ReturnCode p9_pba_coherent_utils_get_num_granules(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address,
@@ -114,7 +177,7 @@ extern "C"
         //by setting bits 23:43 to 0b1.
         uint64_t pba_bar_mask_attr = 0x1FFFFF00000ull;
 
-        FAPI_DBG("p9_pba_coherent_utils_get_num_granules: Start");
+        FAPI_DBG("Start");
 
         pba_bar_mask_data.insertFromRight<0, 63>(pba_bar_mask_attr);
 
@@ -131,54 +194,49 @@ extern "C"
         //subtract the oci part of the address from this maximum number and divide by 8 to get the number of bytes
         //then divide by 128 to get the number of 128 bye granules that can be sent
         o_numGranules = ((maximumAddress - (i_address & oci_address_mask)) / 8) / 128;
-        FAPI_INF("o_numGranules = %016x", o_numGranules);
+        FAPI_DBG("o_numGranules = %016x", o_numGranules);
 
     fapi_try_exit:
-        FAPI_INF("End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-    /// @brief does the setup for the PBA to set up the initial registers for a read/write
-    /// @param[in] i_target => P9 chip target
-    /// @param[in] i_address => starting address for PBA operation
-    /// @param[in] i_rnw => whether the operation is a read or write
-    /// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
-    /// @return FAPI_RC_SUCCESS if setting up the pba registers is a success
     fapi2::ReturnCode p9_pba_coherent_setup_pba(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
         const uint64_t i_address,
         const bool i_rnw,
         const uint32_t i_flags)
     {
         uint32_t extaddr;
         uint64_t ocb3_addr_data;
+        uint64_t chiplet_number = 0x0ull;
         fapi2::buffer<uint64_t> ocb_status_ctl_data;
         fapi2::buffer<uint64_t> ocb3_addr;
         fapi2::buffer<uint64_t> pba_slave_ctl_data;
+        fapi2::buffer<uint64_t> l3_mode_reg1;
 
-        FAPI_DBG("p9_pba_coherent_setup_pba: Start");
+        FAPI_DBG("Start");
 
         //Write the OCB3 Status Control Register
         //Configure linear stream mode (auto-increment +8 with each data register read/write)
         //set bit 4 and unset bit 5 of OCB3 Status Control Register
         ocb_status_ctl_data.flush<1>().clearBit<5>();
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE6_OCB_PIB_OCBCSR3_CLEAR,
+        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_CLEAR,
                                 ocb_status_ctl_data),
                  "Error writing to the OCB3 Status Control Register with and mask");
         ocb_status_ctl_data.flush<0>().setBit<4>();
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE6_OCB_PIB_OCBCSR3_OR,
+        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_OR,
                                 ocb_status_ctl_data),
                  "Error writing to the OCB3 Status Control Register with or mask");
 
         //Write the address to OCB3_ADDRESS Register
         ocb3_addr_data = 0xE000000000000000 | (i_address & 0x7FFFFFFull);
+        //TODO when the fix has come to us for the PBA need to change this back to B instead of E
         //uint64_t ocb3_addr_data = 0xB000000000000000 | (i_address & 0x7FFFFFFull);
-        //uint64_t ocb3_addr_data = 0xB000003800000000 | (i_address & 0x7FFFFFFull);
         ocb3_addr.insertFromRight<0, 64>(ocb3_addr_data);
 
-        FAPI_INF("setting ocb3_addr to 0x%016x", ocb3_addr);
-
-        FAPI_TRY(fapi2::putScom(i_target, PU_GPE6_OCB_PIB_OCBAR3, ocb3_addr),
+        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBAR3, ocb3_addr),
                  "Error writing the OCB3_ADDRESS Register");
 
         //Write the PBA Slave Control Register that controls the tsize, fastmode, etc
@@ -195,7 +253,7 @@ extern "C"
 
         //set the write ttype bits 8:10 to whatever is in the flags
         pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TTYPE_START_BIT,
-                                           (PBA_SLVCTL_WRITE_TTYPE_END_BIT - PBA_SLVCTL_WRITE_TTYPE_START_BIT) + 1 > (i_flags >> (31 - flags::FLAG_TTYPE_END));
+                                           (PBA_SLVCTL_WRITE_TTYPE_END_BIT - PBA_SLVCTL_WRITE_TTYPE_START_BIT) + 1 > ((i_flags & FLAG_TTYPE) >> FLAG_TTYPE_SHIFT);
 
         //it's not cache-inhibited so set bit 15 to cl_rd_nc (0)
         pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_TTYPE_BIT>();
@@ -217,56 +275,51 @@ extern "C"
         pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT,
                                            (PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT -
                                             PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT) + 1 > (0);
-        //set bits 28:35 for the tsize to 0 - TODO when this is a write need to do the chiplet ID of the L3 cache in the form of 00cc_ccc0
-        //TODO Joe commented here:
-        //For LCO, we need to think about how we're going to be instructed (in the SBE chip-op use case, this has to come across the SBE FIFO interface) which L3 to target.  In this HWP routine, this information should drive obtaining the correct target to query its LCO config, so it can be used to target the correct cache.
-        //I am planning to get to this after the long weekend, I need to send a note to Dean, Amit, and Basabjit and ask whether they would rather have us
-        //put in a chiplet number into the flags or have them pass in an extra quad target argument - either one works for me but I wasn't sure what they would rather have.
+
+        //set bits 28:35 for the tsize to 0 - TODO when this is a write need to do the chiplet ID of the L3 cache in the form of 00cc_ccc0 if it's an lco_m
+        //pass in an extra quad target argument
+        if (((i_flags & FLAG_TTYPE) >> FLAG_TTYPE_SHIFT) == 1)
+        {
+            FAPI_TRY(fapi2::getScom(i_ex_target, EX_L3_MODE_REG1, l3_mode_reg1), "Error reading from the L3 Mode Register");
+            l3_mode_reg1.extractToRight(chiplet_number, 1, 5);
+        }
+
         pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TSIZE_START_BIT,
-                                           (PBA_SLVCTL_WRITE_TSIZE_END_BIT - PBA_SLVCTL_WRITE_TSIZE_START_BIT) + 1 > (0);
+                                           (PBA_SLVCTL_WRITE_TSIZE_END_BIT - PBA_SLVCTL_WRITE_TSIZE_START_BIT) + 1 > (chiplet_number);
         //set bits 36:49 to the ext addr
         extaddr = ((uint32_t) (i_address >> PBA_SLVCTL_EXTADDR_SHIFT)) &
                   PBA_SLVCTL_EXTADDR_MASK;
 
-        FAPI_INF("the external address that will be put into the pba_slave_control register = 0x%016x", extaddr);
-
         pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_EXT_ADDR_START_BIT,
                                            (PBA_SLVCTL_EXT_ADDR_END_BIT - PBA_SLVCTL_EXT_ADDR_START_BIT) + 1 > (extaddr);
 
-
         FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL3_SCOM, pba_slave_ctl_data),
                  "Error writing the PBA Slave Control Register");
 
-        FAPI_INF("pba_slv_ctl is going to be set to 0x%016x", pba_slave_ctl_data);
-
     fapi_try_exit:
-        FAPI_INF("End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-    ///@brief sets up the PBA Bar
-    ///@param[in] i_target => P9 chip target
-    ///@param[in] i_address => address for this read/write
-    ///@return FAPI_RC_SUCCESS if writing the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_setup_pba_bar(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_baseAddress)
     {
         fapi2::buffer<uint64_t> pba_bar_data;
 
-        FAPI_DBG("p9_pba_coherent_setup_pba_bar: Start");
+        FAPI_DBG("Start");
 
         //Validate the input parameters
         //Check the address alignment
-        FAPI_ASSERT(!(i_baseAddress & PROC_FBC_UTILS_CACHELINE_MASK),
+        FAPI_ASSERT(!(i_baseAddress & P9_FBC_UTILS_CACHELINE_MASK),
                     fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
                         i_baseAddress),
-                    "p9_pba_coherent_setup_pba_bar: Base Address is not cacheline aligned");
+                    "Base Address is not cacheline aligned");
         //Make sure the address is within the PBA bounds
-        FAPI_ASSERT(i_baseAddress <= PROC_FBC_UTILS_FBC_MAX_ADDRESS,
+        FAPI_ASSERT(i_baseAddress <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
                     fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
                         i_baseAddress),
-                    "p9_pba_coherent_setup_pba_bar: Base Address exceeds supported fabric real address range");
+                    "Base Address exceeds supported fabric real address range");
 
         //set command scope to local node scope
         pba_bar_data.insertFromRight < PBA_BAR_SCOPE_START_BIT,
@@ -278,24 +331,16 @@ extern "C"
                                      (PBA_BAR_BASE_ADDRESS_END_BIT - PBA_BAR_BASE_ADDRESS_START_BIT) + 1 > ((
                                              i_baseAddress >> PBA_BAR_BASE_ADDRESS_SHIFT) & PBA_BAR_BASE_ADDRESS_MASK);
 
-        FAPI_INF("pba_bar3 is going to be set to 0x%016x", pba_bar_data);
-
         //write the register
         FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR3, pba_bar_data),
                  "Error writing the PBA Bar Register");
 
     fapi_try_exit:
-        FAPI_INF("End p9_pba_coherent_setup_pba_bar");
+        FAPI_DBG("End");
         return fapi2::current_err;
 
     }
 
-    /// @brief does the write for the PBA
-    /// @param[in] i_target => P9 chip target
-    /// @param[in] i_address => address for this write
-    /// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
-    /// @param[in] i_write_data => the data that is to be written to the PBA
-    /// @return FAPI_RC_SUCCESS if writing the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_pba_write(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address,
@@ -303,27 +348,21 @@ extern "C"
         const uint64_t i_write_data[])
     {
         fapi2::ReturnCode rc;
-        FAPI_DBG("p9_pba_coherent_pba_write: Start");
+        FAPI_DBG("Start");
 
         //Perform a 128B write -- need to do 16 8B writes since it's in linear mode which can only do 8B...
         for (int i = 0; i < 16; i++)
         {
             fapi2::buffer<uint64_t> data(i_write_data[i]);
-            FAPI_TRY(fapi2::putScom(i_target, PU_GPE6_OCB_PIB_OCBDR3, data),
+            FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBDR3, data),
                      "Error writing to the PBA via the OCB");
         }
 
     fapi_try_exit:
-        FAPI_INF("p9_pba_coherent_pba_write: End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-    /// @brief does the read for the PBA
-    /// @param[in] i_target => P9 chip target
-    /// @param[in] i_address => address for this write
-    /// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
-    /// @param[out] o_read_data => the data that is read from the PBA
-    /// @return FAPI_RC_SUCCESS if reading the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_pba_read(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address,
@@ -332,28 +371,25 @@ extern "C"
     {
         fapi2::buffer<uint64_t> data;
 
-        FAPI_DBG("p9_pba_coherent_pba_read: Start");
+        FAPI_DBG("Start");
 
         //Perform a 128B read -- need to do 16 8B reads since it's in linear mode which can only do 8B...
         for (int i = 0; i < 16; i++)
         {
-            FAPI_TRY(fapi2::getScom(i_target, PU_GPE6_OCB_PIB_OCBDR3, data),
+            FAPI_TRY(fapi2::getScom(i_target, PU_OCB_PIB_OCBDR3, data),
                      "Error reading from the PBA via the OCB");
             o_read_data[i] = data;
         }
 
     fapi_try_exit:
-        FAPI_INF("p9_pba_coherent_pba_read: End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-    /// @brief this does any cleanup for the PBA after all reads/writes have been done
-    /// @param[in] i_target => P9 chip target
-    /// @return FAPI_RC_SUCCESS if cleaning up the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_cleanup_pba(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     {
-        FAPI_DBG("p9_pba_coherent_cleanup_pba: Start");
+        FAPI_DBG("Start");
 
         fapi2::buffer<uint64_t> data;
 
@@ -376,40 +412,26 @@ extern "C"
                     "Error in resetting the PBA Slave Reset register");
 
     fapi_try_exit:
-        FAPI_INF("p9_pba_coherent_cleanup_pba: End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-    /// @brief this checks the PBA/OCB status registers - this is for use at the end of each write/read or at the end of each stream
-    /// @return FAPI_RC_SUCCESS if the status check is a success
     fapi2::ReturnCode p9_pba_coherent_status_check(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     {
-        FAPI_DBG("p9_pba_coherent_status_check: Start");
+        FAPI_DBG("Start");
 
-        fapi2::buffer<uint64_t> rd_buf0_valid;
-        fapi2::buffer<uint64_t> rd_buf1_valid;
         fapi2::buffer<uint64_t> rd_buf2_valid;
         fapi2::buffer<uint64_t> rd_buf3_valid;
-        fapi2::buffer<uint64_t> rd_buf4_valid;
-        fapi2::buffer<uint64_t> rd_buf5_valid;
         fapi2::buffer<uint64_t> wr_buf0_valid;
         fapi2::buffer<uint64_t> wr_buf1_valid;
         fapi2::buffer<uint64_t> reset_buf;
 
-        //Check the 6 PBA Read Buffer Valid Status by reading the read buffer status (bits 33:39) and making sure it's 1
-        FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL0, rd_buf0_valid),
-                 "Error reading from the PBA Read Buffer Valid 0 Status Register");
-        FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL1, rd_buf1_valid),
-                 "Error reading from the PBA Read Buffer Valid 1 Status Register");
+        //Check the 2 PBA Read Buffer Valid Status (2 and 3 since we set Buffer pair "B")by reading the read buffer status (bits 33:39) and making sure it's 1
         FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL2, rd_buf2_valid),
                  "Error reading from the PBA Read Buffer Valid 2 Status Register");
         FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL3, rd_buf3_valid),
                  "Error reading from the PBA Read Buffer Valid 3 Status Register");
-        FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL4, rd_buf4_valid),
-                 "Error reading from the PBA Read Buffer Valid 4 Status Register");
-        FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL5, rd_buf5_valid),
-                 "Error reading from the PBA Read Buffer Valid 5 Status Register");
 
         //Check the 2 PBA Write Buffer Valid Status by reading the write buffer status (bits 35:39) and making sure it's 1
         FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL0, wr_buf0_valid),
@@ -422,19 +444,19 @@ extern "C"
                  "Error reading from the PBA Slave Reset Register");
 
         //If there are any errors in the Status registers that we got above, collect all of the data and send an error
-        FAPI_ASSERT(((rd_buf0_valid & PBA_RD_BUF_VALID_MASK) == (rd_buf1_valid & PBA_RD_BUF_VALID_MASK) ==
-                     (rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == (rd_buf3_valid & PBA_RD_BUF_VALID_MASK) ==
-                     (rd_buf4_valid & PBA_RD_BUF_VALID_MASK) == (rd_buf5_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
-                    && ((wr_buf0_valid & PBA_WR_BUF_VALID_MASK) == (wr_buf1_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
-                    && ((reset_buf & PBA_SLVRST_BUSY_IN_PROG_MASK) == 0),
-                    fapi2::P9_PBA_STATUS_ERR().set_TARGET(i_target).set_RDBUF0(rd_buf0_valid).set_RDBUF1(rd_buf1_valid).set_RDBUF2(
-                        rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_RDBUF4(rd_buf4_valid).set_RDBUF5(rd_buf5_valid).set_WRBUF0(
+        FAPI_ASSERT((((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
+                     && ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
+                     && ((wr_buf0_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
+                     && ((wr_buf1_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
+                     && ((reset_buf & PBA_SLVRST_BUSY_IN_PROG_MASK) == 0)),
+                    fapi2::P9_PBA_STATUS_ERR().set_TARGET(i_target).set_RDBUF2(
+                        rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_WRBUF0(
                         wr_buf0_valid).set_WRBUF1(wr_buf1_valid).set_SLVRSTDATA(reset_buf),
                     "Error in checking the PBA Reset, PBA Read Buffer, or PBA Write Buffer Registers");
 
     fapi_try_exit:
-        FAPI_INF("p9_pba_coherent_status_check: End");
+        FAPI_DBG("End");
         return fapi2::current_err;
     }
 
-} // extern "C"
+} //extern "C"
diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H b/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
index a43364ea..abfaab1b 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
@@ -40,7 +40,6 @@
 //-----------------------------------------------------------------------------------
 
 #include <fapi2.H>
-#include <misc_scom_addresses.H>
 #include <p9_pba_constants.H>
 
 extern "C"
@@ -50,117 +49,87 @@ extern "C"
 // Constant definitions
 //-----------------------------------------------------------------------------------
 
-//PBA Delay Constants
-    const uint32_t PBA_SLVRST_DELAY_HW_NS = 1000;
-    const uint32_t PBA_SLVRST_DELAY_SIM_CYCLES = 200;
-    const uint32_t WRITE_DELAY_HW_NS = 100;
-    const uint32_t WRITE_DELAY_SIM_CYCLES = 20;
-    const uint32_t PBA_BAR_SCOPE_LOCAL_NODE = 0;
-
-//PBA Slave Control register field/bit definitions
-    const uint32_t PBA_SLVCTL_ENABLE_BIT = 0;
-    const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_START_BIT = 1;
-    const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_END_BIT = 3;
-    const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT = 5;
-    const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_END_BIT = 7;
-    const uint32_t PBA_SLVCTL_WRITE_TTYPE_START_BIT = 8;
-    const uint32_t PBA_SLVCTL_WRITE_TTYPE_END_BIT = 10;
-    const uint32_t PBA_SLVCTL_READ_TTYPE_BIT = 15;
-    const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT = 16;
-    const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_END_BIT = 17;
-    const uint32_t PBA_SLVCTL_READ_BUF_INVALIDATE_CTL_BIT = 18;
-    const uint32_t PBA_SLVCTL_WRITE_BUF_PAIR_ALLOCATION_BIT = 19;
-    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_A_ALLOCATION_BIT = 20;
-    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_B_ALLOCATION_BIT = 21;
-    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT = 22;
-    const uint32_t PBA_SLVCTL_DISABLE_WRITE_GATHER_BIT = 24;
-    const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT = 25;
-    const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT = 27;
-    const uint32_t PBA_SLVCTL_WRITE_TSIZE_START_BIT = 28;
-    const uint32_t PBA_SLVCTL_WRITE_TSIZE_END_BIT = 35;
-    const uint32_t PBA_SLVCTL_EXT_ADDR_START_BIT = 36;
-    const uint32_t PBA_SLVCTL_EXT_ADDR_END_BIT = 49;
-
-    const uint32_t PBA_SLVCTL_EXTADDR_SHIFT = 27;
-    const uint32_t PBA_SLVCTL_EXTADDR_MASK = 0x3fff;
-
-//PBA Slave Reset register field/bit definitions
-    const uint32_t PBA_SLVRST_SET_START_BIT = 0;
-    const uint32_t PBA_SLVRST_SET_END_BIT = 2;
-    const uint32_t PBA_SLVRST_SLVCTL0_IN_PROG = 4;
-    const uint32_t PBA_SLVRST_SLVCTL1_IN_PROG = 5;
-    const uint32_t PBA_SLVRST_SLVCTL2_IN_PROG = 6;
-    const uint32_t PBA_SLVRST_SLVCTL3_IN_PROG = 7;
-    const uint32_t PBA_SLVRST_IN_PROG_START_BIT = 4;
-    const uint32_t PBA_SLVRST_IN_PROG_END_BIT = 7;
-    const uint32_t PBA_SLVRST_BUSY_START_BIT = 8;
-    const uint32_t PBA_SLVRST_BUSY_END_BIT = 11;
-    //mask to check if there is a PBA slave rest in progress and if the PBA Slave Control is busy
-    //if it is not all these bits 4:11 should be set to 0
-    const uint64_t PBA_SLVRST_BUSY_IN_PROG_MASK = 0xFF0000000000000ull;
-
-//PBA Read Buffer Valid Status field/bit definitions
-    const uint32_t PBA_RD_BUF_VALID_START_BIT = 33;
-    const uint32_t PBA_RD_BUF_VALID_END_BIT = 39;
-    const uint64_t PBA_RD_BUF_VALID_MASK = 0x7F000000ull;
-    const uint64_t PBA_RD_BUF_EMPTY =  0x1000000ull;
-
-//PBA Write Buffer Valid Status field/bit definitions
-    const uint32_t PBA_WR_BUF_VALID_START_BIT = 35;
-    const uint32_t PBA_WR_BUF_VALID_END_BIT = 39;
-    const uint64_t PBA_WR_BUF_VALID_MASK = 0x1F000000ull;
-    const uint64_t PBA_WR_BUF_EMPTY = 0x1000000ull;
-
-//PBA BAR register field/bit definitions
-    const uint32_t PBA_BAR_SCOPE_START_BIT = 0;
-    const uint32_t PBA_BAR_SCOPE_END_BIT = 2;
-    const uint32_t PBA_BAR_BASE_ADDRESS_START_BIT = 8;
-    const uint32_t PBA_BAR_BASE_ADDRESS_END_BIT = 43;
-    const uint32_t PBA_BAR_BASE_ADDRESS_SHIFT = 21;
-    const uint64_t PBA_BAR_BASE_ADDRESS_MASK = 0xFFFFFFFFFull;
-
-//PBA BAR Mask register field/bit definitions
-    const uint32_t PBA_BAR_MASK_START_BIT = 23;
-    const uint32_t PBA_BAR_MASK_END_BIT = 43;
-
 //-----------------------------------------------------------------------------------
 // Function prototypes
 //-----------------------------------------------------------------------------------
+
+/// @brief does the setup for the PBA to set up the initial registers for a read/write
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_ex_target => Ex target for which L3 we are targeting
+/// @param[in] i_address => starting address for PBA operation
+/// @param[in] i_rnw => whether the operation is a read or write
+/// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
+/// @return FAPI_RC_SUCCESS if setting up the pba registers is a success
     fapi2::ReturnCode p9_pba_coherent_setup_pba(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
         const uint64_t i_address,
         const bool i_rnw,
         const uint32_t i_flags);
 
+/// @brief does the write for the PBA
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => address for this write
+/// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
+/// @param[in] i_write_data => the data that is to be written to the PBA
+/// @return FAPI_RC_SUCCESS if writing the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_pba_write(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address,
         const uint32_t i_flags,
         const uint64_t i_write_data[]);
 
+/// @brief does the read for the PBA
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => address for this write
+/// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
+/// @param[out] o_read_data => the data that is read from the PBA
+/// @return FAPI_RC_SUCCESS if reading the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_pba_read(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address,
         const uint32_t i_flags,
         uint64_t o_read_data[]);
 
+/// @brief calculates the number of 128 byte granules that can be read/written before setup needs to be run again
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => starting address for PBA operation
+/// @return number of 128 byte granules that can be read/written before setup needs to be run again
     fapi2::ReturnCode p9_pba_coherent_utils_get_num_granules(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address,
         uint32_t& o_numGranules);
 
+/// @brief ensure that fabric is initialized and stop control is not set
+///           (by checkstop/mode switch), which if set would prohibit fabric
+///           commands from being broadcasted
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if fabric is not stopped
     fapi2::ReturnCode p9_pba_coherent_utils_check_fbc_state(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
 
+/// @brief check that the address is cacheline aligned and within the fabric real address range
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => starting address for PBA operation
+/// @return FAPI_RC_SUCCESS if arguments are valid
     fapi2::ReturnCode p9_pba_coherent_utils_check_args(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_address);
-
+/// @brief this checks the PBA/OCB status registers - this is for use at the end of each write/read or at the end of each stream
+/// @return FAPI_RC_SUCCESS if the status check is a success
     fapi2::ReturnCode p9_pba_coherent_status_check(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
 
+/// @brief this does any cleanup for the PBA after all reads/writes have been done
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if cleaning up the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_cleanup_pba(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+///@brief sets up the PBA Bar
+///@param[in] i_target => P9 chip target
+///@param[in] i_address => address for this read/write
+///@return FAPI_RC_SUCCESS if writing the PBA is a success
     fapi2::ReturnCode p9_pba_coherent_setup_pba_bar(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         const uint64_t i_baseAddress);
diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H b/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H
index 9016e38b..7a660bbf 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H
@@ -39,18 +39,16 @@ extern "C"
 // Constant definitions
 //----------------------------------------------------------------------------------------------
 
-//if the flag is more than 1 bit there will be a start and end bit for the flag
-//these give the bit position that is expected for the flags
-    enum flags
+//these give the bit mask for each flag
+    enum p9_pba_flags
     {
         //fastmode flag, if this flag is set it means we will not check for errors until the very last granule for the read/write
-        FLAG_FASTMODE = 0,
+        FLAG_FASTMODE = 0x80000000ull,
         //ttype flag, this is 3 bits, will be set to 0 for dma, 1, to lco_m, 2 for atomic, 3 for cache_inj, and 4 for ci_pr_w --same as in the documentation and how they will be passed to the register
-        FLAG_TTYPE_START = 1,
-        FLAG_TTYPE_END = 3
+        FLAG_TTYPE = 0x70000000ull
     };
 
-    enum proc_pba_write_ttype
+    enum p9_pba_write_ttype
     {
         DMA = 0,
         LCO = 1,
@@ -59,6 +57,8 @@ extern "C"
         CI = 4
     };
 
+    const uint64_t FLAG_TTYPE_SHIFT = 28;
+
 } //extern "C"
 
 #endif //_P9_PBA_CONSTANTS_H_
diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C b/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
index a04c988e..fb13ba16 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
@@ -45,21 +45,22 @@ extern "C"
 //--------------------------------------------------------------------------
     fapi2::ReturnCode p9_pba_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
                                    & i_target,
+                                   const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
                                    const uint64_t i_address,
                                    const bool i_rnw,
                                    const uint32_t i_flags,
                                    uint32_t& o_numGranules)
     {
         // mark HWP entry
-        FAPI_INF("p9_pba_setup: Entering ...\n");
+        FAPI_INF("Entering ...\n");
 
         //check arguments
         FAPI_TRY(p9_pba_coherent_utils_check_args(i_target, i_address),
-                 "p9_pba_setup: Error from p9_pba_coherent_utils_check_args");
+                 "Error from p9_pba_coherent_utils_check_args");
 
         //ensure fabric is running
         FAPI_TRY(p9_pba_coherent_utils_check_fbc_state(i_target),
-                 "p9_pba_setup: Error from p9_pba_coherent_utils_check_fbc_state");
+                 "Error from p9_pba_coherent_utils_check_fbc_state");
 
         //reset the ADU - cleanup just calls reset
         //TODO Joe had made a comment on this about resetting the PBA as part of the setup process - I need to test
@@ -69,19 +70,19 @@ extern "C"
         //The PBA Bar and PBA Bar Mask need to be setup before getting the number of granules because how they get setup affects the number of granules that can be read/written
         //setup the PBA Bar
         FAPI_TRY(p9_pba_coherent_setup_pba_bar(i_target, i_address),
-                 "p9_pba_setup: Error from p9_pba_coherent_setup_pba_bar");
+                 "Error from p9_pba_coherent_setup_pba_bar");
 
         //setup the PBA for reading/writing
-        FAPI_TRY(p9_pba_coherent_setup_pba(i_target,  i_address, i_rnw, i_flags),
-                 "p9_pba_setup: Error from p9_pba_coherent_setup_pba");
+        FAPI_TRY(p9_pba_coherent_setup_pba(i_target, i_ex_target, i_address, i_rnw, i_flags),
+                 "Error from p9_pba_coherent_setup_pba");
 
         //figure out the number of 128B granules that can be read/written
         FAPI_TRY(p9_pba_coherent_utils_get_num_granules(i_target, i_address,
                  o_numGranules),
-                 "p9_pba_setup: Error from p9_pba_coherent_utils_get_num_granules");
+                 "Error from p9_pba_coherent_utils_get_num_granules");
 
     fapi_try_exit:
-        FAPI_INF("p9_pba_setup: Exiting...");
+        FAPI_INF("Exiting...");
         return fapi2::current_err;
     }
 } // extern "C"
diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H b/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H
index 45e05bd0..57177c86 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H
@@ -56,6 +56,7 @@
 //-----------------------------------------------------------------------------------
 typedef fapi2::ReturnCode
 (*p9_pba_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+                      const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
                       const uint64_t,
                       const bool,
                       const uint32_t,
@@ -72,6 +73,7 @@ extern "C" {
 
 /// @brief setup for reads/writes from the PBA
 /// @param[in]  i_target  => P9 chip target
+/// @param[in]  i_ex_target => P9 EX Target for use with lco_m operations
 /// @param[in]  i_address => base real address for read/write operation (expected to be 128B aligned)
 /// @param[in]  i_rnw     => if the operation is read not write (1 for read, 0 for write)
 /// @param[in]  i_flags   => other information that is needed - the flags are:
@@ -82,6 +84,7 @@ extern "C" {
 //
     fapi2::ReturnCode p9_pba_setup(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
         const uint64_t i_address,
         const bool i_rnw,
         const uint32_t i_flags,