Level 2 HWP for p9_sbe_tp_chiplet_init1

Added a new scom operation (drop OOB Mux)

Change-Id: I8c89dc294a5b44cdf017e6853d2b5024a24a605b
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21555
Tested-by: Jenkins Server
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Parvathi Rachakonda
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21858
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>

2 files changed, 32 insertions, 23 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
index 831d97f7..d045bb64 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -21,12 +21,12 @@
 ///
 /// @brief Initial steps of PIB AND PCB
 //------------------------------------------------------------------------------
-// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
-// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
-// *HWP Team             : Perv
-// *HWP Level            : 2
-// *HWP Consumed by      : SBE
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
 //------------------------------------------------------------------------------
 
 
@@ -34,44 +34,55 @@
 #include "p9_sbe_tp_chiplet_init1.H"
 
 #include "p9_perv_scom_addresses.H"
+#include "p9_perv_scom_addresses_fld.H"
 
 
-fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
-        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     fapi2::buffer<uint64_t> l_data64;
     FAPI_DBG("Entering ...");
 
     //Setting ROOT_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
-    l_data64.clearBit<15>();  //PIB.ROOT_CTRL0.VDD2VIO_LVL_FENCE_DC = 0
+    //PIB.ROOT_CTRL0.VDD2VIO_LVL_FENCE_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL0_VDD2VIO_LVL_FENCE_DC>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
 
     FAPI_INF("Release PCB Reset");
     //Setting ROOT_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
-    l_data64.clearBit<30>();  //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+    //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL0_PCB_RESET_DC>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
 
     FAPI_INF("Set Chiplet Enable");
     //Setting PERV_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
-    l_data64.setBit<0>();  //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+    //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+    l_data64.setBit<PERV_PERV_CTRL0_TP_CHIPLET_EN_DC>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
 
     FAPI_INF("Drop TP Chiplet Fence Enable");
     //Setting PERV_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
-    l_data64.clearBit<18>();  //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+    //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+    l_data64.clearBit<PERV_PERV_CTRL0_TP_FENCE_EN_DC>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
 
     FAPI_INF("Drop Global Endpoint reset");
     //Setting ROOT_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
-    l_data64.clearBit<31>();  //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0
+    //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL0_GLOBAL_EP_RESET_DC>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
     FAPI_INF("Switching PIB trace bus to SBE tracing");
 
+    FAPI_INF("Drop OOB Mux");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<PERV_ROOT_CTRL0_OOB_MUX>();  //PIB.ROOT_CTRL0.OOB_MUX = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
     FAPI_DBG("Exiting ...");
 
 fapi_try_exit:
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H
index 9f8bcfda..aa81ba26 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H
@@ -21,12 +21,12 @@
 ///
 /// @brief Initial steps of PIB AND PCB
 //------------------------------------------------------------------------------
-// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
-// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
-// *HWP Team             : Perv
-// *HWP Level            : 2
-// *HWP Consumed by      : SBE
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
 //------------------------------------------------------------------------------
 
 
@@ -37,8 +37,7 @@
 #include <fapi2.H>
 
 
-typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)(
-    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
 
 /// @brief Releases the Pervasive Control Bus (PCB) reset
 /// Sets TP chiplet enable
@@ -49,8 +48,7 @@ typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)(
 /// @return  FAPI2_RC_SUCCESS if success, else error code.
 extern "C"
 {
-    fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
-            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+    fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
 }
 
 #endif