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authorThi Tran <thi@us.ibm.com>2016-06-11 16:17:42 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2016-07-01 07:30:29 -0400
commit4f61b7eaca4a176e32e8162ae931b6a347796487 (patch)
treebbc8c641a489e40f82eac3f225ca7ec3d1bd113d /import
parent82f9fe9c97b0a39261eef652765facdfd74e545b (diff)
downloadtalos-sbe-4f61b7eaca4a176e32e8162ae931b6a347796487.tar.gz
talos-sbe-4f61b7eaca4a176e32e8162ae931b6a347796487.zip
p9_htm_setup (L2) - Part 2: HTM setup/reset/start
RTC:138851 Change-Id: Icedf9f1a020948c5515edaf92c9de40897b2ad69 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25689 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25690 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import')
-rw-r--r--import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml75
1 files changed, 60 insertions, 15 deletions
diff --git a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 342c1682..8520c036 100644
--- a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -898,28 +898,73 @@
</attribute>
<!-- ********************************************************************** -->
<attribute>
- <id>ATTR_PROC_HTM_BAR_BASE_ADDR</id>
+ <id>ATTR_PROC_NHTM_BAR_BASE_ADDR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
- <description> The base addresses where the HTM traces start. They are
- calculated based on the HTM trace sizes requested by users.
- There are two different HTM trace areas, thus two different
- base addresses.
+ <description> The base address where the NHTM traces start. They are
+ calculated based on the NHTM trace size requested by user.
+ This address in memory will be the location where NHTM0/1
+ traces are output.
+ Set by p9_mss_eff_grouping.
+ Used by p9_setup_bars and p9_htm_setup.
+ </description>
+ <valueType>uint64</valueType>
+ <writeable/>
+ <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+ <id>ATTR_PROC_NHTM_BAR_SIZE</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description> The amount of memory a user can reserve to store NHTM traces.
+ This amount will be used to store both NHTM0 and NHTM1 traces.
+ Used by p9_mss_eff_grouping.
+ </description>
+ <valueType>uint64</valueType>
+ <enum>
+ 256_GB = 0x0000004000000000,
+ 128_GB = 0x0000002000000000,
+ 64_GB = 0x0000001000000000,
+ 32_GB = 0x0000000800000000,
+ 16_GB = 0x0000000400000000,
+ 8_GB = 0x0000000200000000,
+ 4_GB = 0x0000000100000000,
+ 2_GB = 0x0000000080000000,
+ 1_GB = 0x0000000040000000,
+ 512_MB = 0x0000000020000000,
+ 256_MB = 0x0000000010000000,
+ 128_MB = 0x0000000008000000,
+ 64_MB = 0x0000000004000000,
+ 32_MB = 0x0000000002000000,
+ 16_MB = 0x0000000001000000,
+ ZERO = 0x0000000000000000
+ </enum>
+ <initToZero/>
+ <writeable/>
+ <persistRuntime/>
+</attribute>
+
+<!-- ********************************************************************** -->
+<attribute>
+ <id>ATTR_PROC_CHTM_BAR_BASE_ADDR</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description> The base addresses where the CHTM traces start. They are
+ calculated based on the CHTM trace sizes requested by users.
+ There are 24 different CHTM regions, thus 24 different sizes.
+ Each region is to store HTM trace for a core.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars.
</description>
<valueType>uint64</valueType>
- <array>2</array>
+ <array>24</array>
<writeable/>
<persistRuntime/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
- <id>ATTR_PROC_HTM_BAR_SIZES</id>
+ <id>ATTR_PROC_CHTM_BAR_SIZES</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
- <description> The amount of memory a user can reserve to store HTM traces.
- There are two different HTM trace areas, thus two different
- sizes (For example, one to store NHTM0 and one forNHTM1).
- Set by user via attribute override.
+ <description> The amount of memory a user can reserve to store CHTM traces.
+ There are 24 cores, thus 24 different sizes.
Used by p9_mss_eff_grouping.
</description>
<valueType>uint64</valueType>
@@ -941,10 +986,12 @@
16_MB = 0x0000000001000000,
ZERO = 0x0000000000000000
</enum>
- <array>2</array>
+ <array>24</array>
+ <initToZero/>
<writeable/>
<persistRuntime/>
</attribute>
+
<!-- ********************************************************************** -->
<attribute>
<id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id>
@@ -963,8 +1010,6 @@
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description> The amount of memory a user can reserve to store OCC sandbox
functions.
- Platform is to initialize this attribute to 0 (default).
- Set by user via attribute override.
Used by p9_mss_eff_grouping.
</description>
<valueType>uint64</valueType>
@@ -986,7 +1031,7 @@
16_MB = 0x0000000001000000,
ZERO = 0x0000000000000000
</enum>
- <platInit/>
+ <writeable/>
<persistRuntime/>
</attribute>
<!-- ********************************************************************** -->
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