Level 2 HWP for p9_sbe_npll_setup

Change-Id: I33fda7070a01cafe01beac0b69c5ebaa77e0c6ed
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26288
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26289
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

4 files changed, 185 insertions, 104 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
index b2a21013..729bd30d 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
@@ -32,6 +32,8 @@
 
 //## auto_generated
 #include "p9_sbe_npll_setup.H"
+//## auto_generated
+#include "p9_const_common.H"
 
 #include <p9_perv_scom_addresses.H>
 #include <p9_perv_scom_addresses_fld.H>
@@ -49,115 +51,151 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
     fapi2::buffer<uint64_t> l_read_reg;
     uint8_t l_read_attr = 0;
     fapi2::buffer<uint64_t> l_data64_root_ctrl8;
-    fapi2::buffer<uint64_t> l_data64;
+    fapi2::buffer<uint64_t> l_data64_perv_ctrl0;
     FAPI_INF("Entering ...");
 
-    FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL");
-    //Setting ROOT_CTRL8 register value
+    FAPI_DBG("Reading ROOT_CTRL8 register value");
+    //Getting ROOT_CTRL8 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-    //PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-
-    FAPI_DBG("Drop PLL test enable for CP Filter PLL");
-    //Setting ROOT_CTRL8 register value
-    //PIB.ROOT_CTRL8.TP_FILT1_PLL_TEST_EN = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-
-    FAPI_DBG("Drop PLL test enable for IO Filter PLL");
-    //Setting ROOT_CTRL8 register value
-    //PIB.ROOT_CTRL8.TP_FILT0_PLL_TEST_EN = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
+                            l_data64_root_ctrl8)); //l_data64_root_ctrl8 = PIB.ROOT_CTRL8
 
-    FAPI_DBG("Drop PLL test enable for Nest PLL");
-    //Setting PERV_CTRL0 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
-    //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0
-    l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
 
-    FAPI_DBG("Release SS PLL reset");
-    //Setting ROOT_CTRL8 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-    //PIB.ROOT_CTRL8.TP_SS0_PLL_RESET = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
+    FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip,
+                           l_read_attr));
 
-    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+    if ( l_read_attr == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
 
-    FAPI_DBG("check SS PLL lock");
-    //Getting PLL_LOCK_REG register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
-                            l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+        FAPI_DBG("Release SS PLL reset");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_SS0_PLL_RESET = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
 
-    FAPI_ASSERT(l_read_reg.getBit<0>(),
-                fapi2::SS_PLL_LOCK_ERR()
-                .set_SS_PLL_READ(l_read_reg),
-                "ERROR:SS PLL LOCK NOT SET");
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
 
-    FAPI_DBG("Release SS PLL Bypass");
-    //Setting ROOT_CTRL8 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-    //PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-
-    FAPI_DBG("Release CP Filter PLL reset");
-    //Setting ROOT_CTRL8 register value
-    //PIB.ROOT_CTRL8.TP_FILT1_PLL_RESET = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-
-    FAPI_DBG("Release IO Filter PLL reset");
-    //Setting ROOT_CTRL8 register value
-    //PIB.ROOT_CTRL8.TP_FILT0_PLL_RESET = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
+        FAPI_DBG("check SS PLL lock");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
 
-    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+        FAPI_ASSERT(l_read_reg.getBit<0>(),
+                    fapi2::SS_PLL_LOCK_ERR()
+                    .set_SS_PLL_READ(l_read_reg),
+                    "ERROR:SS PLL LOCK NOT SET");
 
-    FAPI_DBG("check  PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
-    //Getting PLL_LOCK_REG register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
-                            l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+        FAPI_DBG("Release SS PLL Bypass");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
 
-    FAPI_ASSERT(l_read_reg.getBit<1>() && l_read_reg.getBit<2>(),
-                fapi2::FILTER_PLL_LOCK_ERR()
-                .set_FILTER_PLL_READ(l_read_reg),
-                "ERROR:CP or IO FILTER PLL LOCK NOT SET");
+    FAPI_DBG("Reading ATTR_CP_FILTER_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip,
+                           l_read_attr));
 
-    FAPI_DBG("Release CP filetr and IO filter PLL Bypass Signals");
-    //Setting ROOT_CTRL8 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-    //PIB.ROOT_CTRL8.TP_FILT1_PLL_BYPASS = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS>();
-    //PIB.ROOT_CTRL8.TP_FILT0_PLL_BYPASS = 0
-    l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                            l_data64_root_ctrl8));
-
-    FAPI_DBG("Switch MC meshs to Nest mesh");
+    if ( l_read_attr == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for CP Filter PLL");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT1_PLL_TEST_EN = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        FAPI_DBG("Release CP Filter PLL reset");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT1_PLL_RESET = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+        FAPI_DBG("check  PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+        FAPI_ASSERT(l_read_reg.getBit<1>(),
+                    fapi2::CP_FILTER_PLL_LOCK_ERR()
+                    .set_CP_FILTER_PLL_READ(l_read_reg),
+                    "ERROR:CP FILTER PLL LOCK NOT SET");
+
+        FAPI_DBG("Release CP filter PLL Bypass Signal");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT1_PLL_BYPASS = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
+
+    FAPI_DBG("Reading ATTR_IO_FILTER_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip,
+                           l_read_attr));
+
+    if ( l_read_attr == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for IO Filter PLL");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT0_PLL_TEST_EN = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        FAPI_DBG("Release IO Filter PLL reset");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT0_PLL_RESET = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+        FAPI_DBG("check  PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+        FAPI_ASSERT(l_read_reg.getBit<2>(),
+                    fapi2::IO_FILTER_PLL_LOCK_ERR()
+                    .set_IO_FILTER_PLL_READ(l_read_reg),
+                    "ERROR:IO FILTER PLL LOCK NOT SET");
+
+        FAPI_DBG("Release IO filter PLL Bypass Signal");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT0_PLL_BYPASS = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
+
+    FAPI_DBG("Drop PLL test enable for Nest PLL");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
+    //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0
+    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
+
+    FAPI_DBG("Reading ATTR_MC_SYNC_MODE");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
 
     if ( l_read_attr == 1 )
     {
         FAPI_DBG("Set MUX to Nest Clock input");
         //Setting ROOT_CTRL8 register value
-        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
-                                l_data64_root_ctrl8));
         //PIB.ROOT_CTRL8.TP_PLL_CLKIN_SEL4_DC = 1
         l_data64_root_ctrl8.setBit<PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC>();
         FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
@@ -166,10 +204,10 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
 
     FAPI_DBG("Release Nest PLL  reset");
     //Setting PERV_CTRL0 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
     //PIB.PERV_CTRL0.TP_PLLRST_DC = 0
-    l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
 
     fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
 
@@ -185,10 +223,10 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
 
     FAPI_DBG("Release PLL bypass2");
     //Setting PERV_CTRL0 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
     //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
-    l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
 
     FAPI_INF("Exiting ...");
 
diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 8afc8236..9bdc0209 100644
--- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -620,7 +620,7 @@
            <name>ATTR_RUNN_MODE</name>
            <value>0x0</value>
   </entry>
-  <!-- See chip_attributes.xml for a description of ATTR_EC -->
+   <!-- See chip_attributes.xml for a description of ATTR_EC -->
   <entry>
            <name>ATTR_EC</name>
            <!-- The value needs to be changed as per the EC level  -->
@@ -641,4 +641,16 @@ attribute tank
            <virtual/>
   </entry>
 -->
+  <entry>
+           <name>ATTR_SS_FILTER_BYPASS</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_CP_FILTER_BYPASS</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_IO_FILTER_BYPASS</name>
+           <value>0x0</value>
+  </entry>
 </entries>
diff --git a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index db1b0713..f2e4c67d 100644
--- a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -35,7 +35,7 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>Clock Mux#0 settings</description>
   <valueType>uint8</valueType>
-  <writeable/> 
+  <platInit/> 
 </attribute>
 
 <attribute>
@@ -349,8 +349,9 @@
   <id>ATTR_ECID</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
-Created from running the mss_get_cen_ecid.C
-Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description>
+  Created from running the mss_get_cen_ecid.C
+  Firmware shares some code with the processor, 
+  so the attribute is named so they can point at a target and have common function.</description>
   <valueType>uint64</valueType>
   <writeable/>
   <odmVisable/>
@@ -656,4 +657,28 @@ Firmware shares some code with the processor, so the attribute is named so they
     <platInit/>
 </attribute>
 
+<attribute>
+    <id>ATTR_CP_FILTER_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>To skip the locking sequence and check for lock of CP PLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SS_FILTER_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>To skip the locking sequence and check for lock of SS PLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_IO_FILTER_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>To skip the locking sequence and check for lock of IO PLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
 </attributes>
diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml
index 17285f30..028675eb 100644
--- a/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml
+++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml
@@ -7,7 +7,7 @@
 <!--                                                                        -->
 <!-- EKB Project                                                            -->
 <!--                                                                        -->
-<!-- COPYRIGHT 2015                                                         -->
+<!-- COPYRIGHT 2015,2016                                                    -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -29,9 +29,9 @@
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_FILTER_PLL_LOCK_ERR</rc>
-    <description>Filter PLL not locked</description>
-    <ffdc>FILTER_PLL_READ</ffdc>
+    <rc>RC_CP_FILTER_PLL_LOCK_ERR</rc>
+    <description>CP Filter PLL not locked</description>
+    <ffdc>CP_FILTER_PLL_READ</ffdc>
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
@@ -40,4 +40,10 @@
     <ffdc>NEST_PLL_READ</ffdc>
   </hwpError>
   <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_IO_FILTER_PLL_LOCK_ERR</rc>
+    <description>IO Filter PLL not locked</description>
+    <ffdc>IO_FILTER_PLL_READ</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
 </hwpErrors>