Fixing PBARBUFVAL and PBAWBUFVAL to fix error that Raja found in simics

Change-Id: I2a95635e3b11f5b6a6cdc4e9a0c7c96116604b62
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23878
Tested-by: Jenkins Server
Tested-by: PPE CI
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23879
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 37 insertions, 35 deletions

diff --git a/import/chips/p9/sw_simulation/chip.act b/import/chips/p9/sw_simulation/chip.act
index 2ace1e90..cfeb2352 100644
--- a/import/chips/p9/sw_simulation/chip.act
+++ b/import/chips/p9/sw_simulation/chip.act
@@ -35,21 +35,17 @@ CAUSE_EFFECT{
   EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
 
 }
-#Basabjit had me separate these into the read and write because of their read/writeMainstore modules 
-#If a read is done need to set the PBARBUFVAL[0, 1, 2, 3, 4, 5] rd buffer status (bits 33:39) to 0b0000001
+
+#If a read or write is done need to set the PBARBUFVAL[0,1,2,3,4,5] bits 33:39 to 0b0000001
+#set the PBAWBUFVAL[0,1] bits 35:39 to 0b00001
 #set the PBASLVRST to appropriate value
-CAUSE_EFFECT{
-  LABEL=[PBA Read to set the PBARBUFVAL PBAWBUFVAL and PBASLVRST]
-  #If the data register is read
+CAUSE_EFFECT {
+  LABEL=[PBA Read or Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST]
+  #If the data register is read or write 
   WATCH_READ=[REG(0x0006D075)] #OCBDR3
+  WATCH=[REG(0x0006D075)] 
   CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
 
-  #Basabjit had me add these
-  # Read from the Memory
-  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of address
-  EFFECT: TARGET=[MODULE(readMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
-  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
-
   #set PBARBUFVAL0[buffer_status] to 0b0000001
   EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[33]
   EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[34]
@@ -74,6 +70,7 @@ CAUSE_EFFECT{
   EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[37]
   EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[38]
   EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,ON] BIT=[39]
+
   #set PBARBUFVAL3[buffer_status] to 0b0000001
   EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[33]
   EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[34]
@@ -99,28 +96,6 @@ CAUSE_EFFECT{
   EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[38]
   EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,ON] BIT=[39]
 
-  #unset PBASLVRST[in_prog] bit
-  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
-  #set PBASLVRST[busy_status] to 0b0000 bits 8:11
-  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[8]
-  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[9]
-  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[10]
-  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[11]  
-}
-
-#If a write is done need to set the PBAWBUFVAL[0, 1] wr buffer status (bits 35:39) to 0b00001
-#set the PBASLVRST to appropriate value
-CAUSE_EFFECT{
-  LABEL=[PBA Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST]
-  #If the data register is written
-  WATCH=[REG(0x0006D075)] #OCBDR3
-  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
-
-  # Write into from the Memory
-  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of PBA address
-  EFFECT: TARGET=[MODULE(writeMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
-  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
-
   #set PBAWBUFVAL0[buffer_status] to 0b00001
   EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[35]
   EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[36]
@@ -136,8 +111,7 @@ CAUSE_EFFECT{
   EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,ON] BIT=[39]
 
   #unset PBASLVRST[in_prog] bit
-  EFFECT: TARGET=[REG(0x0068001)] OP=[BIT,OFF] BIT=[7]
-
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
   #set PBASLVRST[busy_status] to 0b0000 bits 8:11
   EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[8]
   EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[9]
@@ -145,6 +119,34 @@ CAUSE_EFFECT{
   EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[11]
 }
 
+#Basabjit had me separate these into the read and write because of their read/writeMainstore modules 
+#If a read is done do the read from memory 
+CAUSE_EFFECT{
+  LABEL=[PBA Read to set the PBARBUFVAL PBAWBUFVAL and PBASLVRST]
+  #If the data register is read
+  WATCH_READ=[REG(0x0006D075)] #OCBDR3
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
+
+  #Basabjit had me add these
+  # Read from the Memory
+  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of address
+  EFFECT: TARGET=[MODULE(readMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
+  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
+}
+
+#If a write is done do the write into memory 
+CAUSE_EFFECT{
+  LABEL=[PBA Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST]
+  #If the data register is written
+  WATCH=[REG(0x0006D075)] #OCBDR3
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
+
+  # Write into from the Memory
+  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of PBA address
+  EFFECT: TARGET=[MODULE(writeMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
+  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
+}
+
 # PBA ADDRESS CALC
 CAUSE_EFFECT{
   LABEL=[PBA ADDR Calculation]