p9_sbe_chiplet_reset Level 2 update: set EC/core multicast reg3=group3

replace MCGR[0..3]_CNFG_SETTINGS and MCGR[234]_CACHE_CNFG_SETTINGS
with complete set MCGR_CNFG_SETTING_GROUP[0..6] for human readability

likewise comments now reflect that REGISTERs are being set to those SETTINGS

ideally the PERV_MULTICAST_GROUP_[1..4] would be changed to better clarify,
but these exist in a global header based on the vhdl/figtree descriptions

Change-Id: If89768eb8a49566762fce1fc188e1f03a10c5f53
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26466
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26471
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 35 insertions, 24 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index 19019e71..a09c709b 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -95,7 +95,8 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup(
 static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const
         fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
         const uint64_t i_mc_grp1_val,
-        const uint64_t i_mc_grp2_val = 0x0);
+        const uint64_t i_mc_grp2_val = 0x0,
+        const uint64_t i_mc_grp3_val = 0x0);
 
 static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
@@ -150,7 +151,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
         // Configuring chiplet multicasting registers.
         FAPI_DBG("Configuring multicasting registers for Nest,Xb,Obus,pcie chiplets" );
         FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt,
-                                               p9SbeChipletReset::MCGR0_CNFG_SETTINGS));
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0));
     }
 
     for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
@@ -158,8 +159,8 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
     {
         FAPI_DBG("Configuring multicast registers for MC01,MC23");
         FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt,
-                                               p9SbeChipletReset::MCGR0_CNFG_SETTINGS,
-                                               p9SbeChipletReset::MCGR2_CNFG_SETTINGS));
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP2));
     }
 
     for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
@@ -176,8 +177,9 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
         // Configuring chiplet multicasting registers..
         FAPI_DBG("Configuring core chiplet multicasting registers");
         FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt,
-                                               p9SbeChipletReset::MCGR0_CNFG_SETTINGS,
-                                               p9SbeChipletReset::MCGR1_CNFG_SETTINGS));
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP1,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP3));
     }
 
     for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
@@ -875,23 +877,32 @@ fapi_try_exit:
 static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const
         fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
         const uint64_t i_mc_grp1_val,
-        const uint64_t i_mc_grp2_val)
+        const uint64_t i_mc_grp2_val,
+        const uint64_t i_mc_grp3_val)
 {
     FAPI_INF("Entering ...");
 
     //Setting MULTICAST_GROUP_1 register value
-    //MULTICAST_GROUP_1 = i_mc_grp1_val
+    //MULTICAST_GROUP_1 (register) = i_mc_grp1_val
     FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1,
                             i_mc_grp1_val));
 
     //Setting MULTICAST_GROUP_2 register value
     if (i_mc_grp2_val != 0x0)
     {
-        //MULTICAST_GROUP_2 = (i_mc_grp2_val != 0x0) ? i_mc_grp2_val
+        //MULTICAST_GROUP_2 (register) = (i_mc_grp2_val != 0x0) ? i_mc_grp2_val
         FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2,
                                 i_mc_grp2_val));
     }
 
+    //Setting MULTICAST_GROUP_3 register value
+    if (i_mc_grp3_val != 0x0)
+    {
+        //MULTICAST_GROUP_REGISTER_3 = (i_mc_grp3_val != 0x0) ? i_mc_grp3_val
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3,
+                                i_mc_grp3_val));
+    }
+
     FAPI_INF("Exiting ...");
 
 fapi_try_exit:
@@ -914,30 +925,30 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache(
 
     FAPI_DBG("Setting Multicast register 1&2 for cache chiplet");
     //Setting MULTICAST_GROUP_1 register value
-    //MULTICAST_GROUP_1 = p9SbeChipletReset::MCGR0_CNFG_SETTINGS
+    //MULTICAST_GROUP_1 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0
     FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1,
-                            p9SbeChipletReset::MCGR0_CNFG_SETTINGS));
+                            p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0));
     //Setting MULTICAST_GROUP_2 register value
-    //MULTICAST_GROUP_2 = p9SbeChipletReset::MCGR2_CACHE_CNFG_SETTINGS
+    //MULTICAST_GROUP_2 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4
     FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2,
-                            p9SbeChipletReset::MCGR2_CACHE_CNFG_SETTINGS));
+                            p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4));
 
     if ( ( l_attr_pg & 0x1EBA ) == 0x0 ) // Check good EP chiplet clockdomains excluding l31, l21, refr1
     {
         FAPI_DBG("Setting up multicast register 3 for even cache chiplet");
         //Setting MULTICAST_GROUP_3 register value
-        //MULTICAST_GROUP_3 = p9SbeChipletReset::MCGR3_CACHE_CNFG_SETTINGS
+        //MULTICAST_GROUP_3 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5
         FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3,
-                                p9SbeChipletReset::MCGR3_CACHE_CNFG_SETTINGS));
+                                p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5));
     }
 
     if ( ( l_attr_pg & 0x1D76 ) == 0x0 ) // Check good EP chiplet clockdomains excluding l30, l20, refr0
     {
         FAPI_DBG("Setting up multicast register 4 for odd cache chiplet");
         //Setting MULTICAST_GROUP_4 register value
-        //MULTICAST_GROUP_4 = p9SbeChipletReset::MCGR4_CACHE_CNFG_SETTINGS
+        //MULTICAST_GROUP_4 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6
         FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_4,
-                                p9SbeChipletReset::MCGR4_CACHE_CNFG_SETTINGS));
+                                p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6));
     }
 
     FAPI_INF("Exiting ...");
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
index 150570b6..0d615ed7 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
@@ -47,10 +47,13 @@ namespace p9SbeChipletReset
 {
 enum P9_SBE_CHIPLET_RESET_Public_Constants
 {
-    MCGR0_CNFG_SETTINGS = 0xE0001C0000000000ull,
-    MCGR1_CNFG_SETTINGS = 0xE4001C0000000000ull,
-    MCGR2_CNFG_SETTINGS = 0xE8001C0000000000ull,
-    MCGR3_CNFG_SETTINGS = 0xEC001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP0 = 0xE0001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP1 = 0xE4001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP2 = 0xE8001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP3 = 0xEC001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP4 = 0xF0001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP5 = 0xF4001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull,
     NET_CNTL0_HW_INIT_VALUE = 0x7C16222000000000ull,
     HANG_PULSE_0X10 = 0x10,
     HANG_PULSE_0X0F = 0x0F,
@@ -71,9 +74,6 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants
     HANG_PULSE_0X04 = 0x04,
     HANG_PULSE_0X1A = 0x1A,
     NET_CNTL1_HW_INIT_VALUE = 0x7200000000000000ull,
-    MCGR2_CACHE_CNFG_SETTINGS = 0xF0001C0000000000ull,
-    MCGR3_CACHE_CNFG_SETTINGS = 0xF4001C0000000000ull,
-    MCGR4_CACHE_CNFG_SETTINGS = 0xF8001C0000000000ull,
     REGIONS_EXCEPT_VITAL = 0x7FF,
     SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE,
     SCAN_TYPES_TIME_GPTR_REPR = 0x230,