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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-04-19 07:29:11 +0200 |
|---|---|---|
| committer | Prachi Gupta <pragupta@us.ibm.com> | 2016-06-08 11:45:54 -0500 |
| commit | fef534cb390af83ba62bda8e0162bab0108a5e30 (patch) | |
| tree | 8abd948e365bc0ef8793483d4b9b5a52f488a28e /import/chips/p9 | |
| parent | d08097acee82c4cba1b182c7bdd631b0a1dca572 (diff) | |
| download | talos-sbe-fef534cb390af83ba62bda8e0162bab0108a5e30.tar.gz talos-sbe-fef534cb390af83ba62bda8e0162bab0108a5e30.zip | |
Level 1 HWP for p9_hcd_cache_chiplet_l3_dcc_setup
Change-Id: Ie1c3e381437a35a1e588165ad451137110c2ae8e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23398
Tested-by: Jenkins Server
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25112
Diffstat (limited to 'import/chips/p9')
| -rw-r--r-- | import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C | 47 | ||||
| -rw-r--r-- | import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H | 54 |
2 files changed, 101 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C new file mode 100644 index 00000000..8de85c52 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_chiplet_l3_dcc_setup.C +/// +/// @brief Setup L3 DCC, Drop L3 DCC bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_hcd_cache_chiplet_l3_dcc_setup.H" + + + +fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet) +{ + FAPI_INF("Entering ..."); + + FAPI_INF("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H new file mode 100644 index 00000000..506923c6 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H @@ -0,0 +1,54 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_chiplet_l3_dcc_setup.H +/// +/// @brief Setup L3 DCC, Drop L3 DCC bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_HCD_CACHE_CHIPLET_L3_DCC_SETUP_H_ +#define _P9_HCD_CACHE_CHIPLET_L3_DCC_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_l3_dcc_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief * Setup L3 DCC (scan with setpulse, scan region = ANEP), attribute dependency Nimbus/Cumulus +/// * Drop L3 DCC bypass +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet); +} + +#endif |
