Recommit of p9_sbe_setup_evid for Level 1

- Change 17359 was orignally closed (review) for Level 1.  However,
  that change was not formally merged to master (apparently) as a
  rebase has these files missing.
- Added copyright
- fixed unused variable

Change-Id: Ice8e69cacdcc8d13ed3cb706c2090a8e93e088fc
Original-Change-Id: Ie0c7b44fce86d4c50df11620a2f36c4e48c8452d
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18396
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-by: Bilicon Patil <bilpatil@in.ibm.com>
Reviewed-by: Derk Rembold <rembold@de.ibm.com>
Tested-by: Derk Rembold <rembold@de.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23570
Tested-by: Jenkins Server
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 135 insertions, 0 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C
new file mode 100644
index 00000000..c8706a2c
--- /dev/null
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C
@@ -0,0 +1,76 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C $            */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_setup_evid.C
+/// @brief Setup External Voltage IDs and Boot Frequency
+///
+// *HW Owner    : Greg Still <stillgs@us.ibm.com>
+// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+// *Team        : PM
+// *Consumed by : SBE
+// *Level       : 1
+///
+/// @verbatim
+/// Procedure Summary:
+///   - Use Attributes to send VDD, VCS via the AVS bus to VRMs
+///   - Use Attributes to adjust the VDN and send via I2C to VRM
+///   - Read core frequency ATTR and write to the Quad PPM
+/// @endverbatim
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include "p9_sbe_setup_evid.H"
+
+//-----------------------------------------------------------------------------
+// Procedure
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+
+    //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    // Substep indicators
+
+    // commented out in Level 1 to not have "unused variable" warnings
+    // until the SBE substep management "macro" or "call" is defined.
+
+    // const uint32_t STEP_SBE_EVID_START              = 0x1;
+    // const uint32_t STEP_SBE_EVID_CONFIG             = 0x2;
+    // const uint32_t STEP_SBE_EVID_WRITE_VDN          = 0x3;
+    // const uint32_t STEP_SBE_EVID_POLL_VDN_STATUS    = 0x4;
+    // const uint32_t STEP_SBE_EVID_WRITE_VDD          = 0x5;
+    // const uint32_t STEP_SBE_EVID_POLL_VDD_STATUS    = 0x6;
+    // const uint32_t STEP_SBE_EVID_WRITE_VCS          = 0x7;
+    // const uint32_t STEP_SBE_EVID_POLL_VCS_STATUS    = 0x8;
+    // const uint32_t STEP_SBE_EVID_TIMEOUT            = 0x9;
+    // const uint32_t STEP_SBE_EVID_BOOT_FREQ          = 0xA;
+    // const uint32_t STEP_SBE_EVID_COMPLETE           = 0xB;
+
+// The inclusion of the following will cause a "label 'fapi_try_exit' defined but not used"
+// compile error in Cronus.  This will be uncommented when FAPI_TRY functions are added
+// during the real procedure development.  However, this is NOT needed for Level 1.
+//fapi_try_exit:
+    return fapi2::current_err;
+
+} // Procedure
+
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H
new file mode 100644
index 00000000..4c17e3da
--- /dev/null
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H $            */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_setup_evid.H
+/// @brief Setup External Voltage IDs and Boot Frequency
+///
+/// *HW Owner    : Greg Still <stillgs@us.ibm.com>
+/// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+/// *Team        : PM
+/// *Consumed by : SBE
+/// *Level       : 1
+///
+
+#ifndef __P9_SBE_SETUP_EVID_H__
+#define __P9_SBE_SETUP_EVID_H__
+
+extern "C"
+{
+
+/// @typedef p9_sbe_setup_evid_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_sbe_setup_evid_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Read attributes containing this part's boot voltages (VDD, VCS and VDN)
+///        and set these voltage using the AVSBUS interface (VDD, VCS) an I2C (VDN).
+///        Also reads a differnt attribute containing the boot frequency and set that
+///        into each configured EQ chiplet.
+/// @param [in] i_target TARGET_TYPE_PROC_CHIP
+/// @attr
+/// @attritem   ATTR_BOOT_FREQ          uint16_t - 9 bit frequency multiplier of the refclk right justified
+/// @attritem   ATTR_VCS_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VCS rail
+/// @attritem   ATTR_VDD_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VDD rail
+/// @attritem   ATTR_VDN_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VDN rail
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_SBE_SETUP_EVID_H__