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authorThi Tran <thi@us.ibm.com>2015-12-11 12:49:53 -0600
committerSachin Gupta <sgupta2m@in.ibm.com>2016-05-02 04:07:08 -0400
commit1fa5766a96abf206c09dcac8ba880c76b24f1ace (patch)
tree75c0c9824f0b47db4ed309d61b30ff67a2a7423f /import/chips/p9
parent7dbe88078841fd9e2245cfa4afc8c5f4eb44395b (diff)
downloadtalos-sbe-1fa5766a96abf206c09dcac8ba880c76b24f1ace.tar.gz
talos-sbe-1fa5766a96abf206c09dcac8ba880c76b24f1ace.zip
L2 - p9_build_smp HWPs
Change-Id: I35608d7929461c3e3a7318fb318831dd584a857f Original-Change-Id: Ic3b000e1c9844499c478e29f2d370d037a8fc262 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22704 Tested-by: Jenkins Server Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Auto Mirror Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23930 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9')
-rw-r--r--import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H508
-rw-r--r--import/chips/p9/procedures/hwp/nest/p9_adu_constants.H107
2 files changed, 579 insertions, 36 deletions
diff --git a/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
index e819cfb8..3d812616 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
+++ b/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
@@ -7,7 +7,7 @@
/* */
/* EKB Project */
/* */
-/* COPYRIGHT 2015 */
+/* COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -42,6 +42,16 @@
#include <fapi2.H>
#include <p9_adu_constants.H>
+// Definitions of how to handle Busy state of the ADU when
+// checking its status.
+enum adu_status_busy_handler
+{
+ EXPECTED_BUSY_BIT_CLEAR = 0, // Expect to be clear, error if not
+ EXPECTED_BUSY_BIT_SET = 1, // Expect to be set, error if not
+ EXIT_ON_BUSY = 2 // Return Busy status without checking
+ // any other errors.
+};
+
extern"C"
{
@@ -50,6 +60,479 @@ extern"C"
//-----------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------
+// Classes
+//-----------------------------------------------------------------------------------
+///
+/// @brief Manage ADU operation flag that is used to program the
+// ADU CMD register, PU_ALTD_CMD_REG (Addr: 0x00090001)
+///
+ class p9_ADU_oper_flag
+ {
+ public:
+
+ // Type of ADU operations
+ enum OperationType_t
+ {
+ CACHE_INHIBIT = 0,
+ DMA_PARTIAL = 1,
+ PB_OPER = 2,
+ PMISC_OPER = 3,
+ };
+
+ // Transaction size
+ enum Transaction_size_t
+ {
+ TSIZE_1 = 1,
+ TSIZE_2 = 2,
+ TSIZE_4 = 4,
+ TSIZE_8 = 8,
+ };
+
+ // Constructor
+ inline p9_ADU_oper_flag()
+ : iv_operType(CACHE_INHIBIT), iv_autoInc(false), iv_lockPick(false),
+ iv_numLockAttempts(1), iv_cleanUp(true), iv_fastMode(false),
+ iv_itag(false), iv_ecc(false), iv_eccItagOverwrite(false),
+ iv_transSize(TSIZE_1)
+ {
+ }
+
+ ///
+ /// @brief Set the ADU operation type
+ ///
+ /// @param[in] i_type ADU operation type
+ ///
+ /// @return void.
+ ///
+ inline void setOperationType(const OperationType_t i_type)
+ {
+ iv_operType = i_type;
+ return;
+ }
+
+ ///
+ /// @brief Get the ADU operation type setting.
+ ///
+ /// @return iv_operType.
+ ///
+ inline const OperationType_t getOperationType(void)
+ {
+ return iv_operType;
+ }
+
+ /// @brief Set the Auto Increment option, for CI/DMA operations only.
+ ///
+ /// @param[in] i_value True: Enable auto inc; False: Disable
+ ///
+ /// @return void.
+ ///
+ inline void setAutoIncrement(bool i_value)
+ {
+ if ( (iv_operType != CACHE_INHIBIT) &&
+ (iv_operType != DMA_PARTIAL) )
+ {
+ FAPI_ERR("WARNING: Set AUTOINC for non CI/DMA operation, Operation type 0x%.8X",
+ iv_operType);
+ }
+
+ iv_autoInc = i_value;
+ return;
+ }
+
+ /// @brief Get the Auto Increment setting, for CI/DMA operations only.
+ ///
+ /// @return iv_autoInc.
+ ///
+ inline const bool getAutoIncrement(void)
+ {
+ if ( (iv_operType != CACHE_INHIBIT) &&
+ (iv_operType != DMA_PARTIAL) )
+ {
+ FAPI_ERR("WARNING: AUTOINC value is invalid for non CI/DMA operation, Operation type 0x%.8X",
+ iv_operType);
+ }
+
+ return iv_autoInc;
+ }
+
+ ///
+ /// @brief Set ADU lock control
+ ///
+ /// @param[in] i_value True: Attempt lock ADU before operation
+ /// False: No lock attempt
+ ///
+ /// @return void
+ ///
+ inline void setLockControl(bool i_value)
+ {
+ iv_lockPick = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get the ADU lock control setting.
+ ///
+ /// @return iv_lockPick.
+ ///
+ inline const bool getLockControl(void)
+ {
+ return iv_lockPick;
+ }
+
+ ///
+ /// @brief Set number of lock attempts
+ ///
+ /// @param[in] i_value Num of lock attempts to try. If still can't lock
+ /// ADU, return an error.
+ ///
+ /// @return void
+ ///
+ inline void setNumLockAttempts(uint8_t i_value)
+ {
+ if (iv_lockPick == false)
+ {
+ FAPI_ERR("WARNING: Set lock attempts value with lock pick = false");
+ }
+
+ iv_numLockAttempts = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get number of lock attempts setting.
+ ///
+ /// @return iv_numLockAttempts.
+ ///
+ inline const uint8_t getNumLockAttempts(void)
+ {
+ if (iv_lockPick == false)
+ {
+ FAPI_ERR("WARNING: Lock control is not set, num of lock attempts setting is invalid.");
+ }
+
+ return iv_numLockAttempts;
+ }
+
+ ///
+ /// @brief Clean up if operation fails
+ ///
+ /// @param[in] i_value True: Clean up and release lock if oper fails.
+ /// False: Leave ADU in fail state.
+ ///
+ /// @return void.
+ ///
+ inline void setOperFailCleanup(bool i_value)
+ {
+ iv_cleanUp = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get the clean up for failed operation setting.
+ ///
+ /// @return iv_cleanUp.
+ ///
+ inline const bool getOperFailCleanup(void)
+ {
+ return iv_cleanUp;
+ }
+
+ ///
+ /// @brief Set fast read/write mode.
+ /// For fast read/write mode, no status check. Otherwise,
+ /// do status check after every read/write.
+ ///
+ /// @param[in] i_value True: Enable fast read/write mode.
+ /// False: Disable fast read/write mode.
+ ///
+ /// @return void.
+ ///
+ inline void setFastMode(bool i_value)
+ {
+ iv_fastMode = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get the Fast mode setting.
+ ///
+ /// @return iv_fastMode.
+ ///
+ inline const bool getFastMode(void)
+ {
+ return iv_fastMode;
+ }
+
+ ///
+ /// @brief Set itag collection mode.
+ /// Collect/set itag with each 8B read/write
+ /// For a write only set if itag data should be 1
+ ///
+ /// @param[in] i_value True: Collect itag
+ /// False: Don't collect itag.
+ ///
+ /// @return void.
+ ///
+ inline void setItagMode(bool i_value)
+ {
+ iv_itag = i_value;
+ return;
+ }
+
+ ///
+ /// @brief the ITAG collection mode.
+ ///
+ /// @return iv_itag.
+ ///
+ inline const bool getItagMode(void)
+ {
+ return iv_itag;
+ }
+
+ ///
+ /// @brief Set Ecc mode.
+ /// Collect/set ecc with each 8B read/write
+ ///
+ /// @param[in] i_value True: Collect ECC
+ /// False: Don't collect ECC.
+ ///
+ /// @return void.
+ ///
+ inline void setEccMode(bool i_value)
+ {
+ iv_ecc = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get the Ecc mode setting.
+ ///
+ /// @return iv_ecc.
+ ///
+ inline const bool getEccMode(void)
+ {
+ return iv_ecc;
+ }
+
+ ///
+ /// @brief Overwrite ECC/ITAG data mode.
+ ///
+ /// @param[in] i_value Overwrite ECC
+ /// False: Don't overwrite ECC
+ ///
+ /// @return void.
+ ///
+ inline void setEccItagOverrideMode(bool i_value)
+ {
+ iv_eccItagOverwrite = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get the Overwrite ECC/ITAG data mode.
+ ///
+ /// @return iv_eccItagOverwrite.
+ ///
+ inline const bool getEccItagOverrideMode(void)
+ {
+ return iv_eccItagOverwrite;
+ }
+
+ ///
+ /// @brief Set transaction size
+ ///
+ /// @param[in] i_value Transaction size
+ ///
+ /// @return void.
+ ///
+ inline void setTransactionSize(Transaction_size_t i_value)
+ {
+ iv_transSize = i_value;
+ return;
+ }
+
+ ///
+ /// @brief Get the transaction size
+ ///
+ /// @return iv_transSize.
+ ///
+ inline const Transaction_size_t getTransactionSize(void)
+ {
+ return iv_transSize;
+ }
+
+ ///
+ /// @brief Assemble the 32-bit ADU flag based on current
+ /// info contained in this class.
+ /// This flag is to be used in ADU interface call
+ /// See flag bit definitions in p9_adu_constants.H
+ ///
+ /// @return uint32_t
+ ///
+ inline uint32_t setFlag();
+
+ ///
+ /// @brief Update the class instant variables with info
+ /// embedded in the passed in flag value.
+ ///
+ /// @return void.
+ ///
+ inline void getFlag(uint32_t i_flag);
+
+ private:
+
+ // Class variables
+ OperationType_t iv_operType; // Operation type
+ bool iv_autoInc; // Auto increment
+ bool iv_lockPick; // Lock ADU before operation
+ uint8_t iv_numLockAttempts; // Number of lock attempts
+ bool iv_cleanUp;
+ bool iv_fastMode; // Fast ADU read/write mode
+ bool iv_itag; // Itag mode
+ bool iv_ecc; // ECC mode
+ bool iv_eccItagOverwrite; // ECC/ITAG overwrite mode
+ Transaction_size_t iv_transSize; // Transaction size
+ };
+
+///
+/// See doxygen in class definition
+///
+ uint32_t p9_ADU_oper_flag::setFlag()
+ {
+ uint32_t l_aduFlag = 0;
+
+ // Operation type
+ l_aduFlag |= (iv_operType << FLAG_ADU_TTYPE_SHIFT);
+
+ // Auto Inc
+ if (iv_autoInc == true)
+ {
+ l_aduFlag |= FLAG_AUTOINC;
+ }
+
+ // Lock pick
+ if (iv_lockPick == true)
+ {
+ l_aduFlag |= FLAG_LOCK_PICK;
+ }
+
+ // Lock attempts
+ l_aduFlag |= (iv_numLockAttempts << FLAG_LOCK_TRIES_SHIFT);
+
+ // Leave dirty
+ if (iv_cleanUp == false)
+ {
+ l_aduFlag |= FLAG_LEAVE_DIRTY;
+ }
+
+ // Fast mode
+ if (iv_fastMode == true)
+ {
+ l_aduFlag |= FLAG_ADU_FASTMODE;
+ }
+
+ // Itag
+ if (iv_itag == true)
+ {
+ l_aduFlag |= FLAG_ITAG;
+ }
+
+ // ECC
+ if (iv_ecc == true)
+ {
+ l_aduFlag |= FLAG_ECC;
+ }
+
+ // Overwrite ECC
+ if (iv_eccItagOverwrite == true)
+ {
+ l_aduFlag |= FLAG_OVERWRITE_ECC;
+ }
+
+ // Transaction size
+ if (iv_transSize == TSIZE_1)
+ {
+ l_aduFlag |= FLAG_SIZE_TSIZE_1;
+ }
+ else if (iv_transSize == TSIZE_2)
+ {
+ l_aduFlag |= FLAG_SIZE_TSIZE_2;
+ }
+ else if (iv_transSize == TSIZE_4)
+ {
+ l_aduFlag |= FLAG_SIZE_TSIZE_4;
+ }
+ else if (iv_transSize == TSIZE_8)
+ {
+ l_aduFlag |= FLAG_SIZE_TSIZE_8;
+ }
+ else
+ {
+ FAPI_ERR("Invalid transaction size: iv_transSize %d", iv_transSize);
+ }
+
+ // Debug trace
+ FAPI_DBG("p9_ADU_oper_flag::setFlag()");
+ FAPI_DBG(" iv_operType 0x%.8X, iv_autoInc 0x%.8X, iv_lockPick 0x%.8X, iv_numLockAttempts 0x%.8X",
+ iv_operType, iv_autoInc, iv_lockPick, iv_numLockAttempts);
+ FAPI_DBG(" iv_cleanUp 0x%.8X, iv_fastMode 0x%.8X, iv_itag 0x%.8X, iv_ecc 0x%.8X",
+ iv_cleanUp, iv_fastMode, iv_itag, iv_ecc);
+ FAPI_DBG(" iv_eccItagOverwrite 0x%.8X, iv_transSize 0x%.8X",
+ iv_eccItagOverwrite, iv_transSize);
+ FAPI_DBG(" ADU Flag value: 0x%.8X", l_aduFlag);
+
+ return l_aduFlag;
+ }
+
+///
+/// See doxygen in class definition
+///
+ void p9_ADU_oper_flag::getFlag(const uint32_t i_flag)
+ {
+ // Decode Operation type
+ iv_operType = static_cast<OperationType_t>
+ ( (i_flag & FLAG_ADU_TTYPE) >> FLAG_ADU_TTYPE_SHIFT);
+
+ // Auto Inc
+ iv_autoInc = (i_flag & FLAG_AUTOINC);
+
+ // Lock pick
+ iv_lockPick = (i_flag & FLAG_LOCK_PICK);
+
+ // Lock attempts
+ iv_numLockAttempts = ( (i_flag & FLAG_LOCK_TRIES) >> FLAG_LOCK_TRIES_SHIFT);
+
+ // Leave dirty
+ iv_cleanUp = ~(i_flag & FLAG_LEAVE_DIRTY);
+
+ // Fast mode
+ iv_fastMode = (i_flag & FLAG_ADU_FASTMODE);
+
+ // Itag
+ iv_itag = (i_flag & FLAG_ITAG);
+
+ // ECC
+ iv_ecc = (i_flag & FLAG_ECC);
+
+ // Overwrite ECC
+ iv_eccItagOverwrite = (i_flag & FLAG_OVERWRITE_ECC);
+
+ // Transaction size
+ iv_transSize = static_cast<Transaction_size_t>
+ ( (i_flag & FLAG_SIZE) >> FLAG_ADU_SIZE_SHIFT );
+
+ // Debug trace
+ FAPI_DBG("p9_ADU_oper_flag::getFlag() - Flag value 0x%.8X", i_flag);
+ FAPI_DBG(" iv_operType 0x%.8X, iv_autoInc 0x%.8X, iv_lockPick 0x%.8X, iv_numLockAttempts 0x%.8X",
+ iv_operType, iv_autoInc, iv_lockPick, iv_numLockAttempts);
+ FAPI_DBG(" iv_cleanUp 0x%.8X, iv_fastMode 0x%.8X, iv_itag 0x%.8X, iv_ecc 0x%.8X",
+ iv_cleanUp, iv_fastMode, iv_itag, iv_ecc);
+ FAPI_DBG(" iv_eccItagOverwrite 0x%.8X, iv_transSize 0x%.8X",
+ iv_eccItagOverwrite, iv_transSize);
+ return;
+ }
+
+//-----------------------------------------------------------------------------------
// Function prototypes
//-----------------------------------------------------------------------------------
@@ -94,28 +577,28 @@ extern"C"
/// @param[in] i_target => P9 chip target
/// @param[in] i_firstGranule => the first 8B granule that we are writing
/// @param[in] i_address => address for this write
-/// @param[in] i_flags => flags that contain information that the ADU needs to know to set up registers
+/// @param[in] i_aduOper => Contains information that the ADU needs to know to set up registers
/// @param[in] i_write_data => the data that is to be written to the ADU
/// @return FAPI_RC_SUCCESS if writing the ADU is a success
fapi2::ReturnCode p9_adu_coherent_adu_write(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_firstGranule,
const uint64_t i_address,
- const uint32_t i_flags,
+ p9_ADU_oper_flag& i_aduOper,
const uint8_t i_write_data[]);
/// @brief does the read for the ADU
/// @param[in] i_target => P9 chip target
/// @param[in] i_firstGranule => the first 8B granule that we are reading
/// @param[in] i_address => address for this read
-/// @param[in] i_flags => flags that contain information that the ADU needs to know to set up registers
+/// @param[in] i_aduOper => Contains information that the ADU needs to know to set up registers
/// @param[out] o_read_data => the data that is read from the ADU
/// @return FAPI_RC_SUCCESS if reading the ADU is a success
fapi2::ReturnCode p9_adu_coherent_adu_read(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const bool i_firstGranule,
const uint64_t i_address,
- const uint32_t i_flags,
+ p9_ADU_oper_flag& i_aduOper,
uint8_t o_read_data[]);
/// @brief this does a reset for the ADU
@@ -136,12 +619,21 @@ extern"C"
fapi2::ReturnCode p9_adu_coherent_clear_autoinc(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
-/// @brief this will check the status of the pba
-/// @param[in] i_target => P9 chip target
+/// @brief This function checks the status of the adu.
+/// If ADU is busy, it will handle
+///
+/// @param[in] i_target P9 chip target
+/// @param[in] i_busyBitHandler Instruction on how to handle the ADU busy
+/// @param[in] i_addressOnlyOper Indicate the check is called after an Address
+/// only operation
+/// @param[out] o_busyStatus ADU status busy bit.
+///
/// @return FAPI_RC_SUCCESS if the status check is a success
fapi2::ReturnCode p9_adu_coherent_status_check(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
- const bool i_busy_bit_set_expected);
+ const adu_status_busy_handler i_busyBitHandler,
+ const bool i_addressOnlyOper,
+ bool& o_busyBitStatus);
/// @brief this will acquire and release a lock as well as deal with any lock picking
/// @param[in] i_target => P9 chip target
diff --git a/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H b/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
index effa2898..9c582e0b 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
+++ b/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
@@ -7,7 +7,7 @@
/* */
/* EKB Project */
/* */
-/* COPYRIGHT 2015 */
+/* COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -35,39 +35,90 @@
extern "C"
{
- //----------------------------------------------------------------------------------------------
- // Constant definitions
- //----------------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------------
+// Constant definitions
+//----------------------------------------------------------------------------------------------
- //if the flag is more than 1 bit there will be a start and end bit for the flag
- //these give the bit position that is expected for the flags
+//if the flag is more than 1 bit there will be a start and end bit for the flag
+//these give the bit position that is expected for the flags
enum adu_flags
{
- //cache-inhibited (true = ci, false = dma partial)
- FLAG_CI = 0x80000000ull,
- //utilize ADU HW auto-increment function (true = use autoinc, false = don't use autoinc)
- FLAG_AUTOINC = 0x40000000ull,
- //pick ADU lock (if required) (true = use lock pick, false = don't pick lock)
- FLAG_LOCK_PICK = 0x20000000ull,
- //in the case of a fail with lock held, reset ADU and release lock (true = , false = )
- FLAG_LEAVE_DIRTY = 0x10000000ull,
- //check status only at the end of read/write stream (true = don't do status check, false = do status check after every read/write)
- FLAG_FASTMODE_ADU = 0x8000000ull,
- //collect/set itag with each 8B read/write (true = collect itag, false = don't collect itag) for a write only set if itag data should be 1
- FLAG_ITAG = 0x4000000ull,
- //collect/set ecc with each 8B read/write (true = collect ecc, false = don't collect ecc)
- FLAG_ECC = 0x2000000ull,
- //overwrite the ecc/itag data
- FLAG_OVERWRITE_ECC = 0x1000000ull,
- //transaction size (choice is 1, 2, 4, or 8)
- FLAG_SIZE = 0xFF0000ull,
- //number of ADU lock acquisitions to attempt before giving up or attempting lock pick
- FLAG_LOCK_TRIES = 0xFFFFull
+ // Operation type
+ // 0b000: DMA partial
+ // 0b001: Cache-inhibited
+ // 0b010: PB op
+ // 0b011: PMISC op
+ FLAG_ADU_TTYPE = 0xE0000000ull, // Bits 0:2
+
+ // Utilize ADU HW auto-increment function
+ // 0: Don't use autoinc
+ // 1: Use autoinc
+ FLAG_AUTOINC = 0x10000000ull, // Bit 3
+
+ // Pick ADU lock (if required)
+ // 0: Don't use lock pick
+ // 1: Use lock pick
+ FLAG_LOCK_PICK = 0x08000000ull, // Bit 4
+
+ // In case of a fail with lock held, reset
+ // ADU and release lock
+ // 0: Reset & release
+ // 1: Leave dirty
+ FLAG_LEAVE_DIRTY = 0x04000000ull, // Bit 5
+
+ // Check status only at the end of read/write stream
+ // 0: Do status check after every read/write
+ // 1: Don't do status check
+ FLAG_ADU_FASTMODE = 0x02000000ull, // Bit 6
+
+ // Collect/set itag with each 8B read/write
+ // For a write only set if itag data should be 1
+ // 0: Don't collect itag
+ // 1: Collect itag
+ FLAG_ITAG = 0x01000000ull, // Bit 7
+
+ // Collect/set ecc with each 8B read/write
+ // 0: Don't collect ecc
+ // 1: Collect ecc
+ FLAG_ECC = 0x00800000ull, // Bit 8
+
+ // Overwrite the ecc/itag data
+ // 0: Don't overwrite ECC
+ // 1: Overwrite ECC
+ FLAG_OVERWRITE_ECC = 0x00400000ull, // Bit 9
+
+ // Transaction size (choice is 1, 2, 4, or 8)
+ // 0b00: TSIZE_1
+ // 0b01: TSIZE_2
+ // 0b10: TSIZE_4
+ // 0b11: TSIZE_8
+ FLAG_SIZE = 0x00300000ull, // Bits 10:11
+
+ // Number of ADU lock acquisitions to attempt
+ // before giving up or attempting lock pick
+ FLAG_LOCK_TRIES = 0x000F0000, // Bit 12:15
+
+ // Reserved bits
+ FLAG_NOT_USED_BITS = 0x0000FFFF, // Bit 16:31
};
- const uint64_t FLAG_SIZE_SHIFT = 17;
+// Operation type values
+ const uint32_t FLAG_ADU_TTYPE_DMA = 0x00000000ull; // DMA partial
+ const uint32_t FLAG_ADU_TTYPE_CI = 0x20000000ull; // Cache inhibit
+ const uint32_t FLAG_ADU_TTYPE_PB = 0x40000000ull; // PB operation
+ const uint32_t FLAG_ADU_TTYPE_PMISC = 0x60000000ull; // Switch operation
+
+// Flag size values
+ const uint32_t FLAG_SIZE_TSIZE_1 = 0x00000000ull;
+ const uint32_t FLAG_SIZE_TSIZE_2 = 0x00100000ull;
+ const uint32_t FLAG_SIZE_TSIZE_4 = 0x00200000ull;
+ const uint32_t FLAG_SIZE_TSIZE_8 = 0x00300000ull;
+
+// Shift positions
+ const uint64_t FLAG_ADU_TTYPE_SHIFT = 29;
+ const uint64_t FLAG_LOCK_TRIES_SHIFT = 16;
+ const uint64_t FLAG_ADU_SIZE_SHIFT = 20;
} //extern "C"
#endif //_P9_ADU_CONSTANTS_H_
-
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