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author | Yue Du <daviddu@us.ibm.com> | 2015-04-15 15:48:34 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2015-11-17 22:54:32 -0600 |
commit | cdd479f6299d3dcb016ee8911363224fa9836601 (patch) | |
tree | a2cde6feb69e6d0ef2feb5beeed346bd72e0fe09 /import/chips/p9/procedures | |
parent | 9d08b385c009089b67bf875ef97a9283df1e5aaf (diff) | |
download | talos-sbe-cdd479f6299d3dcb016ee8911363224fa9836601.tar.gz talos-sbe-cdd479f6299d3dcb016ee8911363224fa9836601.zip |
PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute defined
Patch 6 Update:
FW owner email address fix
Patch 5 Update:
target types fixed, all compiles now.
(Will rework them when multicast target is ready in Fapi2)
add @brief to function doxygen
add FW Owners to all headers
typo fixes
Note: NOT fixed with this update or this level 1 release but was commented:
1) still need a solution for document attributes in doxygen headers.
2) All traces in procedures including entry/exit are going to be
finalized in future releases as the function body development
reaches next maturity. There will be more discussion
in-term/inter-term on how to do tracing overall on these procs,
dont want to block this release because of it.
Patch 3 Update:
addressed comments from Patch 2 review.
merged p9_hcd_cache/core_sp_runtime_scom and p9_hcd_cache/core_host_runtime_scom
into p9_hcd_cache/core_ras_runtime_scom based on changes in P9_IPL_Flow.doc(v55)
Patch 2 Update:
renamed proc_* to p9_* for all procedure filenames per comment in Patch 1
Note:
1) Due to ongoing interface discussion and resolution, some of these procedures
are not yet ready for building under Cronus. Regular Fapi2 build is ready.
If you see some of Fapi2 Target Types in these procedures are not in Fapi2 yet,
that is because they are currently in discussion of addition to Fapi2.
2) There are ongoing function body development in the code, which are all
"#if 0" out in this level 1 release. The effective code in all files are
only the API prototypes. Please focus your review only to the interfaces.
3) cache/core runinit is for SGPE and CME at runtime only, not for IPL or SBE.
4) common_pro_epi_log and common_poweronoff are subroutine support(not in IPL_Flow)
Change-Id: If7d54c58fdb6f255eb9f2ee34489b3b2f517c4fb
Original-Change-Id: I46f07bb3e7cf050256c123e7f16982ccead2ceda
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17193
Reviewed-by: Reshmi Nair <reshminair@in.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Tested-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22092
Tested-by: Jenkins Server
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures')
-rw-r--r-- | import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C b/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C new file mode 100644 index 00000000..089deb79 --- /dev/null +++ b/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C @@ -0,0 +1,78 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.C +/// @brief Core Chiplet Power-on +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// 1.Command the core PFET controller to power-on, via putscom to CPPM +/// - +/// 2.Check for valid power on completion, via getscom from CPPM +/// Polled Timeout: 100us +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_poweron.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core Chiplet Power-on +//----------------------------------------------------------------------------- + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_core_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint32_t i_operation) + { + +#if 0 + + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + |