Level 2 HWP for p9_sbe_chiplet_pll_setup

Included the update on syncmode

Change-Id: I45e79a241cc86c0ca9d36572325357d2dcefbc01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23995
Tested-by: Jenkins Server
Tested-by: PPE CI
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23996
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 141 insertions, 56 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
index 65b29548..09c7b9be 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
@@ -32,6 +32,8 @@
 
 //## auto_generated
 #include "p9_sbe_chiplet_pll_setup.H"
+//## auto_generated
+#include "p9_const_common.H"
 
 #include <p9_perv_scom_addresses.H>
 #include <p9_perv_scom_addresses_fld.H>
@@ -58,7 +60,10 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock(
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
 
-static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_drop_bypass(
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
 
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset(
@@ -73,62 +78,125 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(
 fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
+    uint8_t l_read_attr = 0;
     FAPI_INF("Entering ...");
 
     for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
          (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
     {
-        FAPI_DBG("Drop PDLY, DCC bypass");
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_drop_bypass(l_chplt_trgt));
+        FAPI_DBG("Drop PDLY bypass");
+        FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_bypass(l_chplt_trgt));
     }
 
-    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-         (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
-    {
-        FAPI_DBG("call clock start stop module and drop syncclk_muxsel");
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
-    }
+    FAPI_DBG("Reading ATTR_mc_sync_mode");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
 
-    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
-          fapi2::TARGET_STATE_FUNCTIONAL))
+    if ( l_read_attr )
     {
-        FAPI_DBG("release pll test enable for except pcie");
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("call clock start stop module and drop syncclk muxsel");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("release pll test enable for except pcie");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Release PLL reset");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Check pll lock for PCIe");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Check pll lock for Xb,Ob");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+        }
     }
-
-    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
-                                           fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
-    {
-        FAPI_DBG("Release PLL reset");
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
-    }
-
-    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-         (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+    else
     {
-        FAPI_DBG("Check pll lock for pcie");
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
-    }
-
-    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
-          fapi2::TARGET_STATE_FUNCTIONAL))
-    {
-        FAPI_DBG("Check pll lock for Xb,OB,MC");
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
-    }
-
-    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
-                                           fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
-    {
-        FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Drop MCC bypass");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_dcc_bypass(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("call clock start stop module and drop syncclk_muxsel");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("release pll test enable for except pcie");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Release PLL reset");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Check pll lock for pcie");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("check pll lock for Mc,Xb,Ob");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+        }
     }
 
     FAPI_INF("Exiting ...");
@@ -227,11 +295,35 @@ fapi_try_exit:
 
 }
 
-/// @brief Drop PDLY bypass, DCC bypass
+/// @brief Drop Mc DCC bypass
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("Entering ...");
+
+    FAPI_DBG("Drop DCC bypass");
+    //Setting NET_CTRL1 register value
+    l_data64.flush<1>();
+    //NET_CTRL1.CLK_DCC_BYPASS_EN = 0
+    l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL1_WAND, l_data64));
+
+    FAPI_INF("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop Mc PDLY bypass
 ///
 /// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
 /// @return  FAPI2_RC_SUCCESS if success, else error code.
-static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_drop_bypass(
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
 {
     fapi2::buffer<uint64_t> l_data64;
@@ -244,13 +336,6 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_drop_bypass(
     l_data64.clearBit<PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN>();
     FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64));
 
-    FAPI_DBG("Drop DCC bypass");
-    //Setting NET_CTRL1 register value
-    l_data64.flush<1>();
-    //NET_CTRL1.CLK_DCC_BYPASS_EN = 0
-    l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>();
-    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64));
-
     FAPI_INF("Exiting ...");
 
 fapi_try_exit:
@@ -317,7 +402,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(
     fapi2::buffer<uint64_t> l_data64;
     FAPI_INF("Entering ...");
 
-    FAPI_DBG("Call module clock start stop to start NSL clocks for PCIE_PLL");
+    FAPI_DBG("call module clock start stop");
     FAPI_TRY(p9_sbe_common_clock_start_stop(i_target_chiplet, CLOCK_CMD,
                                             DONT_STARTSLAVE, DONT_STARTMASTER, REGIONS, CLOCK_TYPES));