L2 HWP -- p9_setup_bars

p9_setup_bars
  initial relase -- program FSP/PSI/NPU BARs & configure MCD

nest_attributes
proc_setup_bars_attributes
  adjust scope of BAR base address attributes from chip->system
  change to reflect offset from base of chip address range, rather than
  absolute address

p9_fbc_utils
  modify p9_fbc_utils_get_chip_base_address() to output base of each on
  chip region, consider policy affecting placement of mirrrored memory

p9_mss_eff_grouping
p9_sbe_load_bootloader
p9_sbe_mcs_setup
  adapt to p9_fbc_utils_get_chip_base_address() changes

p9_sbe_scominit
  adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes
  add placeholder for FIR register initialization

p9_pcie_config
  adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes
  skip programming of INT resources

Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27849
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 7 insertions, 6 deletions

diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
index cf160b39..1fe5dc4f 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
+++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
@@ -144,8 +144,7 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
     uint8_t l_is_master_sbe;
     uint8_t l_is_mpipl;
     uint8_t l_ipl_type;
-    uint64_t l_chip_base_address_nm;
-    uint64_t l_chip_base_address_m;
+    uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, l_chip_base_address_mmio;
 
     auto l_mcs_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCS>();
     auto l_mi_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MI>();
@@ -170,20 +169,22 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
 
         // determine base address
         FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
-                 l_chip_base_address_nm,
-                 l_chip_base_address_m),
+                 l_chip_base_address_nm0,
+                 l_chip_base_address_nm1,
+                 l_chip_base_address_m,
+                 l_chip_base_address_mmio),
                  "Error from p9_fbc_utils_get_chip_base_addrs");
 
         if (l_mcs_chiplets.size())
         {
             FAPI_TRY(set_hb_dcbz_config(l_mcs_chiplets.front(),
-                                        l_chip_base_address_nm),
+                                        l_chip_base_address_nm0),
                      "Error from set_hb_dcbz_config (MCS)");
         }
         else
         {
             FAPI_TRY(set_hb_dcbz_config(l_mi_chiplets.front(),
-                                        l_chip_base_address_nm),
+                                        l_chip_base_address_nm0),
                      "Error from set_hb_dcbz_config (MI)");
         }
     }