diff options
| author | Ben Gass <bgass@us.ibm.com> | 2016-01-13 15:01:40 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-01-27 23:39:41 -0600 |
| commit | 3c15b4c8e04ea9f6dcc695a8c66ed59ad83002a3 (patch) | |
| tree | 6829b08635c28f8ac1f8a39954daaea2edeefff8 /import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | |
| parent | 0b19c18e66184e0b2ad53a83402f4eb0f0106ad6 (diff) | |
| download | talos-sbe-3c15b4c8e04ea9f6dcc695a8c66ed59ad83002a3.tar.gz talos-sbe-3c15b4c8e04ea9f6dcc695a8c66ed59ad83002a3.zip | |
New scom addresses const headers for chip 9031
Fixes for mcbist
Fixes for obus
Reviewed figtree issues
Reviewed address translation
Change-Id: I07641369fffd9ac97219134ff6c6db03221d091e
Original-Change-Id: I68a21eb34c3ef5061c5d64099f108471acf96c5e
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23283
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23716
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9/common/include/p9_misc_scom_addresses_fld.H')
| -rw-r--r-- | import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | 6874 |
1 files changed, 4960 insertions, 1914 deletions
diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H index 6abee95c..e5dadd38 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -288,6 +288,39 @@ REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY , 0 , SH_UN REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_LEN ); +REG64_FLD( CAPP_APC_ERRINJ_ENABLE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( CAPP_APC_ERRINJ_DBLERR , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DBLERR ); +REG64_FLD( CAPP_APC_ERRINJ_CONTINUOUS , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CONTINUOUS ); +REG64_FLD( CAPP_APC_ERRINJ_TARGET , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET ); +REG64_FLD( CAPP_APC_ERRINJ_TARGET_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET_LEN ); +REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_ENABLE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_ERROR_INJECT_ENABLE ); +REG64_FLD( CAPP_APC_ERRINJ_SNP_INJECT_DBL_ECC_ERROR , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_INJECT_DBL_ECC_ERROR ); +REG64_FLD( CAPP_APC_ERRINJ_SNP_INJECT_CONTINOUS_ERROR , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_INJECT_CONTINOUS_ERROR ); +REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_ERROR_INJECT_TARGET ); +REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_ERROR_INJECT_TARGET_LEN ); +REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_ENABLE , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_ERROR_INJECT_ENABLE ); +REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_TYPE , 33 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_ERROR_TYPE ); +REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_TYPE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_ERROR_TYPE_LEN ); +REG64_FLD( CAPP_APC_ERRINJ_XPT_INJECT_CONTINUOUS_ERROR , 35 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_INJECT_CONTINUOUS_ERROR ); +REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET , 36 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_ERROR_INJECT_TARGET ); +REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_XPT_ERROR_INJECT_TARGET_LEN ); + REG64_FLD( CAPP_APC_PMUSEL_GRPSEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_GRPSEL ); REG64_FLD( CAPP_APC_PMUSEL_GRPSEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -397,6 +430,57 @@ REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UN REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( NV_ATR_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_ATR_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_ATR_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( NV_ATR_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( NV_ATR_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( NV_ATR_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( NV_ATR_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( NV_ATR_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END_LEN ); + REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE_LEN , 64 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , @@ -462,6 +546,11 @@ REG64_FLD( PU_NPU_SM0_ATS_HOLD_INVAL_IODA_TBL_SEL_ESR , 18 , SH_UN REG64_FLD( PU_NPU_SM0_ATS_HOLD_ESR_RSVD_19 , 19 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_ESR_RSVD_19 ); +REG64_FLD( PU_NPU_SM0_ATS_MASK_IDIAL , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , + SH_FLD_IDIAL ); +REG64_FLD( PU_NPU_SM0_ATS_MASK_IDIAL_LEN , 20 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , + SH_FLD_IDIAL_LEN ); + REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT , 10 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_TIMEOUT ); REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT_LEN , 6 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , @@ -1871,6 +1960,14 @@ REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -1976,6 +2073,14 @@ REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2081,6 +2186,14 @@ REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2186,6 +2299,14 @@ REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2291,6 +2412,14 @@ REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2396,6 +2525,14 @@ REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2501,6 +2638,14 @@ REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); @@ -2735,6 +2880,14 @@ REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2840,6 +2993,14 @@ REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -2945,6 +3106,14 @@ REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); @@ -3308,6 +3477,14 @@ REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); @@ -3413,6 +3590,14 @@ REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); @@ -7479,6 +7664,780 @@ REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UN REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( NV_CERR_FIRST_MASK1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( NV_CERR_FIRST_MASK2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_63 ); + REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -7583,6 +8542,14 @@ REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -7688,6 +8655,14 @@ REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -7793,6 +8768,14 @@ REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -7898,6 +8881,14 @@ REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -8003,6 +8994,14 @@ REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -8108,6 +9107,14 @@ REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -8213,6 +9220,14 @@ REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); @@ -8447,6 +9462,14 @@ REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -8552,6 +9575,14 @@ REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -8657,6 +9688,14 @@ REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); @@ -9020,6 +10059,14 @@ REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); @@ -9125,6 +10172,14 @@ REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); @@ -13406,6 +14461,14 @@ REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -13511,6 +14574,14 @@ REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -13616,6 +14687,14 @@ REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -13721,6 +14800,14 @@ REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -13826,6 +14913,14 @@ REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -13931,6 +15026,14 @@ REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -14036,6 +15139,14 @@ REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); @@ -14270,6 +15381,14 @@ REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -14375,6 +15494,14 @@ REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -14480,6 +15607,14 @@ REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); @@ -14843,6 +15978,14 @@ REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); @@ -14948,6 +16091,14 @@ REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UN SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); @@ -19503,6 +20654,11 @@ REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS , 37 , SH_UN REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); +REG64_FLD( PU_CLKRATIO_RATIO , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RATIO ); +REG64_FLD( PU_CLKRATIO_RATIO_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RATIO_LEN ); + REG64_FLD( PEC_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( PEC_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , @@ -29632,9 +30788,13 @@ REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -29739,9 +30899,13 @@ REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -29846,9 +31010,13 @@ REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , @@ -29953,9 +31121,13 @@ REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , @@ -30060,9 +31232,13 @@ REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , @@ -30167,9 +31343,13 @@ REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , @@ -30274,9 +31454,13 @@ REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -30438,9 +31622,13 @@ REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , @@ -30545,9 +31733,13 @@ REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , @@ -30652,9 +31844,13 @@ REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , @@ -30873,9 +32069,13 @@ REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , @@ -30980,9 +32180,13 @@ REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UN SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); -REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); +REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); +REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -31005,9 +32209,17 @@ REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , @@ -31030,9 +32242,17 @@ REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , @@ -31078,9 +32298,17 @@ REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , @@ -31103,9 +32331,17 @@ REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , @@ -31202,9 +32438,17 @@ REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -31227,9 +32471,17 @@ REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -31275,9 +32527,17 @@ REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , @@ -31300,9 +32560,17 @@ REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , @@ -31325,9 +32593,17 @@ REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , @@ -31424,9 +32700,17 @@ REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , @@ -31449,9 +32733,17 @@ REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -31571,9 +32863,17 @@ REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UN SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -33824,6 +35124,108 @@ REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UN REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( NV_CREQ_DA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_CREQ_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_CREQ_DA_PTR_START , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( NV_CREQ_DA_PTR_START_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( NV_CREQ_DA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( NV_CREQ_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( NV_CREQ_DA_PTR_END , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( NV_CREQ_DA_PTR_END_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( NV_CREQ_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_CREQ_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_CREQ_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( NV_CREQ_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( NV_CREQ_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( NV_CREQ_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( NV_CREQ_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( NV_CREQ_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END_LEN ); + REG64_FLD( PU_CSAR_SRAM_ADDRESS , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS ); REG64_FLD( PU_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , @@ -33850,25 +35252,25 @@ REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UN REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX_LEN ); -REG64_FLD( PU_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_ACCESS_MODE ); -REG64_FLD( PU_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ENABLE ); -REG64_FLD( PU_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_CORRECT_DIS ); -REG64_FLD( PU_CSCR_ECC_DETECT_DIS , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_ECC_DETECT_DIS , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_DETECT_DIS ); -REG64_FLD( PU_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_TYPE ); -REG64_FLD( PU_CSCR_ECC_INJECT_ERR , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_ECC_INJECT_ERR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_ERR ); -REG64_FLD( PU_CSCR_SPARE_6_7 , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SPARE_6_7 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CSCR_SPARE_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SPARE_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7_LEN ); -REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX ); -REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX_LEN ); REG64_FLD( PU_CSDR_SRAM_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -34290,6 +35692,27 @@ REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 22 , REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 31 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_STARTING_ADDRESS_LEN ); +REG64_FLD( CAPP_CXA_TRIGCTL_PORTSEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PORTSEL ); +REG64_FLD( CAPP_CXA_TRIGCTL_PORTSEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PORTSEL_LEN ); +REG64_FLD( CAPP_CXA_TRIGCTL_APC0_ENABLE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC0_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_APC1_ENABLE , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC1_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_SNPFE_TRIGGER_ENABLE , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPFE_TRIGGER_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_SNPFE_DIR_TRIGGER_ENABLE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPFE_DIR_TRIGGER_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPBE_TRIGGER_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNPBE_UOP_TRIGGER_ENABLE ); +REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_MUX_PORT_SEL ); +REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SNP_MUX_PORT_SEL_LEN ); + REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0 ); REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0_LEN , 64 , SH_UNT , SH_ACS_SCOM , @@ -34429,923 +35852,933 @@ REG64_FLD( PEC_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UN REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PEC_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PEC_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N3_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PU_N1_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PU_N2_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PEC_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PEC_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PU_N0_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PEC_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT1_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_X_COUPLE_SELECT2_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED_2 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PEC_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N3_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PU_N1_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PU_N2_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PEC_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PEC_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); + +REG64_FLD( PU_N0_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TO_CMP_LT_VALUE_LEN ); -REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); @@ -36289,6 +37722,57 @@ REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , @@ -36493,6 +37977,108 @@ REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_ACT ); + +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -36544,55 +38130,55 @@ REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -36646,55 +38232,55 @@ REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -36748,6 +38334,57 @@ REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -36952,6 +38589,57 @@ REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( NV_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( NV_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_DEBUG0_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , @@ -37003,6 +38691,57 @@ REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -37105,6 +38844,57 @@ REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , @@ -37309,6 +39099,108 @@ REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , + SH_FLD_ACT ); + +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -37360,55 +39252,55 @@ REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -37462,55 +39354,55 @@ REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -37564,6 +39456,57 @@ REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -37768,6 +39711,57 @@ REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( NV_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( NV_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_DEBUG1_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , @@ -37819,6 +39813,57 @@ REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD0 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD0_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD1 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD1_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD2 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD2_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD3 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD3_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD4 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD4_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD5 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD5_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD6 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD6_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD7 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD7_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD8 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD8_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD9 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD9_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD10 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_POD10_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE0 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -37923,171 +39968,6 @@ REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL , 4 , SH_UN REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_SEL_LEN ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_LOCAL_TRACE_RUN_IN ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT_LEN ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TRACE_FREEZE ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT_LEN ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT_LEN ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION0_LT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION1_LT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_3_EVENT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_TIMEOUT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_5_EVENT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_TIMEOUT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT ); -REG64_FLD( PU_N3_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT_LEN ); - -REG64_FLD( PU_N1_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_LOCAL_TRACE_RUN_IN ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT_LEN ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TRACE_FREEZE ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT_LEN ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT_LEN ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION0_LT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION1_LT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_3_EVENT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_TIMEOUT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_5_EVENT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_TIMEOUT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT ); -REG64_FLD( PU_N1_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT_LEN ); - -REG64_FLD( PU_N2_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_LOCAL_TRACE_RUN_IN ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT_LEN ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TRACE_FREEZE ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT_LEN ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT_LEN ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION0_LT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION1_LT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_3_EVENT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_TIMEOUT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_5_EVENT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_TIMEOUT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT ); -REG64_FLD( PU_N2_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT_LEN ); - -REG64_FLD( PEC_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_LOCAL_TRACE_RUN_IN ); -REG64_FLD( PEC_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT_LEN ); -REG64_FLD( PEC_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TRACE_FREEZE ); -REG64_FLD( PEC_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT_LEN ); -REG64_FLD( PEC_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT_LEN ); -REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION0_LT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION1_LT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_3_EVENT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_TIMEOUT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_5_EVENT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_TIMEOUT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT ); -REG64_FLD( PEC_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT_LEN ); - -REG64_FLD( PU_N0_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_LOCAL_TRACE_RUN_IN ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TRACE_STATE_LAT_LEN ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TRACE_FREEZE ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_COND3_STATE_LT_LEN ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_COND5_STATE_LT_LEN ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION0_LT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_HISTORY_CONDITION1_LT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_3_EVENT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND2_TIMEOUT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_5_EVENT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_HISTORY_COND4_TIMEOUT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT ); -REG64_FLD( PU_N0_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_RESERVED_TCDBG_LT_LEN ); - REG64_FLD( CAPP_DFSUOP1_WORD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WORD ); REG64_FLD( CAPP_DFSUOP1_WORD_LEN , 56 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -39844,12 +41724,18 @@ REG64_FLD( PU_ESB_NOTIFY_VALID , 63 , SH_UN REG64_FLD( PU_EXPORT_REGL_CTRL_TP_NX_ALLOW_CRYPTO_DC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_NX_ALLOW_CRYPTO_DC ); -REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EXSD_FULLSPEED_DC , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_TP_EXSD_FULLSPEED_DC ); -REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC ); -REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC ); +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_2CHIP , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TP_PB_FUSE_TOPOLOGY_2CHIP ); +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP ); +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN ); +REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_SPARE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TP_PB_FUSE_SPARE ); REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_0 ); @@ -39903,6 +41789,50 @@ REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_EXTENDED_STATUS_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , + SH_FLD_ACTION0 ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , + SH_FLD_ACTION1 ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X0_FIR_ERR , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X0_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X1_FIR_ERR , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X1_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X2_FIR_ERR , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X2_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X3_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X4_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR , 5 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X5_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR , 6 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X6_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_SCOM_ERROR , 7 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERROR ); + +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X0_FIR_ERR , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X0_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X1_FIR_ERR , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X1_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X2_FIR_ERR , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X2_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X3_FIR_ERR , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X3_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X4_FIR_ERR , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X4_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X5_FIR_ERR , 5 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X5_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X6_FIR_ERR , 6 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_PB_X6_FIR_ERR ); +REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_SCOM_ERROR , 7 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERROR ); + REG64_FLD( PU_NPU_CTL_FENCE_0_CONFIG_0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NPU_CTL_FENCE_0_CONFIG_0_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -40585,8 +42515,8 @@ REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_SUE , 36 , SH_UN SH_FLD_XPT_POWERBUS_SUE ); REG64_FLD( CAPP_FIR_REG_TLBI_TIMEOUT , 37 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_TIMEOUT ); -REG64_FLD( CAPP_FIR_REG_TLBI_SEQ_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , - SH_FLD_TLBI_SEQ_ERR ); +REG64_FLD( CAPP_FIR_REG_TLBI_SOT_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_SOT_ERR ); REG64_FLD( CAPP_FIR_REG_TLBI_BAD_OP_ERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_BAD_OP_ERR ); REG64_FLD( CAPP_FIR_REG_TLBI_SEQ_NUM_PARITY_ERR , 40 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -40629,6 +42559,127 @@ REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UN REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); +REG64_FLD( PHB_FIR_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PHB_FIR_REG_AIB_ADDRESS_INVALID , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ADDRESS_INVALID ); +REG64_FLD( PHB_FIR_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PHB_FIR_REG_PAPR_OUTBOUND_INJECT_ERROR , 3 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_OUTBOUND_INJECT_ERROR ); +REG64_FLD( PHB_FIR_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PHB_FIR_REG_AIB_INF_CLASS_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PHB_FIR_REG_PE_STOP_STATE_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PE_STOP_STATE_SIGNALED ); +REG64_FLD( PHB_FIR_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PHB_FIR_REG_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PHB_FIR_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PHB_FIR_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PHB_FIR_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PHB_FIR_REG_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PHB_FIR_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PHB_FIR_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PHB_FIR_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PHB_FIR_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PHB_FIR_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PHB_FIR_REG_PAPR_INBOUND_INJECT_ERROR , 39 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_INBOUND_INJECT_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PHB_FIR_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PHB_FIR_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_COMMON_FATAL_ERROR , 59 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_COMMON_FATAL_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PHB_FIR_REG_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_PARITY_ERROR ); + REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_CE , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_CE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_HDR_UE , 1 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , @@ -41323,18 +43374,8 @@ REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); -REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR ); -REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR_LEN ); -REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); -REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID ); -REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -41539,18 +43580,8 @@ REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); -REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR ); -REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR_LEN ); -REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); -REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID ); -REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -41755,18 +43786,8 @@ REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); -REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR ); -REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR_LEN ); -REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); -REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID ); -REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -41971,18 +43992,8 @@ REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); -REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR ); -REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR_LEN ); -REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); -REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID ); -REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -45981,11 +47992,260 @@ REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63 , 61 , SH_UN REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_0_31 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_31 ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_0_31_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_31_LEN ); + +REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_15 ); +REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_15_LEN ); + +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R0 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R0_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1R ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1R_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1W ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1W_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R2 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R2_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R3 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R3_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4R , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4R ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4R_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4W , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4W ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4W_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R5 , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R5 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R5_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R5_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R6 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R6_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R7 , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R7 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R7_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R7_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R8 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R8 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R8_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R9 , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R9 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R9_LEN ); + +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R0 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R0_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1R ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1R_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1W ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1W_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R2 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R2_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R3 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R3_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4R , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4R ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4R_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4W , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4W ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4W_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R5 , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R5 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R5_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R5_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R6 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R6_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R7 , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R7 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R7_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R7_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R8 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R8 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R8_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R9 , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R9 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R9_LEN ); + +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R0 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R0_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1R ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1R_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1W ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R1W_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R2 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R2_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R3 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R3_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4R , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4R ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4R_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4W , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4W ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R4W_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R5 , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R5 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R5_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R5_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R6 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R6_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R7 , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R7 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R7_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R7_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R8 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R8 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R8_LEN ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R9 , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R9 ); +REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_R9_LEN ); + +REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( PU_INT_PC_DBG_TMOT_ARX_TIMEOUT , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARX_TIMEOUT ); +REG64_FLD( PU_INT_PC_DBG_TMOT_ARX_TIMEOUT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARX_TIMEOUT_LEN ); +REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9 ); +REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9_LEN ); +REG64_FLD( PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MMIO_LDST_TIMEOUT ); +REG64_FLD( PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MMIO_LDST_TIMEOUT_LEN ); + +REG64_FLD( PU_INT_PC_DBG_TRACE_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0 ); +REG64_FLD( PU_INT_PC_DBG_TRACE_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1 ); + REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); +REG64_FLD( PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0 ); +REG64_FLD( PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0_LEN ); + +REG64_FLD( PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0 ); +REG64_FLD( PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0_LEN ); + +REG64_FLD( PU_INT_PC_ERR0_FATAL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR0_FATAL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR0_INFO_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR0_INFO_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR0_RECOV_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR0_RECOV_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR0_WOF_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR0_WOF_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR0_WOF_DETAIL_DETAIL , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DETAIL ); +REG64_FLD( PU_INT_PC_ERR0_WOF_DETAIL_DETAIL_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DETAIL_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0 ); +REG64_FLD( PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0 ); +REG64_FLD( PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG0_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_FATAL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR1_FATAL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_INFO_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR1_INFO_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_RECOV_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR1_RECOV_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_WOF_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_ERR1_WOF_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_ERR1_WOF_DETAIL_DETAIL , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DETAIL ); +REG64_FLD( PU_INT_PC_ERR1_WOF_DETAIL_DETAIL_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DETAIL_LEN ); + REG64_FLD( PU_INT_PC_GLOBAL_CFG_INDIRECT_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIRECT_MODE ); REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39 , 33 , SH_UNT , SH_ACS_SCOM_RW , @@ -46086,41 +48346,6 @@ REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR , 17 , SH_UN REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR_LEN ); -REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG0_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ERROR_CONFIG ); -REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG0_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ERROR_CONFIG_LEN ); - -REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG1_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ERROR_CONFIG ); -REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG1_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ERROR_CONFIG_LEN ); - -REG64_FLD( PU_INT_PC_REGS_FATAL_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_PC_REGS_FATAL_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); - -REG64_FLD( PU_INT_PC_REGS_INFO_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_PC_REGS_INFO_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); - -REG64_FLD( PU_INT_PC_REGS_RECOV_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_PC_REGS_RECOV_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); - -REG64_FLD( PU_INT_PC_REGS_WOF_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR ); -REG64_FLD( PU_INT_PC_REGS_WOF_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, - SH_FLD_ERROR_LEN ); - -REG64_FLD( PU_INT_PC_REGS_WOF_ERR_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ERROR ); -REG64_FLD( PU_INT_PC_REGS_WOF_ERR_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ERROR_LEN ); - REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P0_IS_IDLE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P0_IS_IDLE ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P1_IS_IDLE , 1 , SH_UNT , SH_ACS_SCOM_RO , @@ -46293,6 +48518,14 @@ REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET , 45 , SH_UN REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_OFFSET_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25 ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PTAG_MAX_IN_USE ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PTAG_MAX_IN_USE_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE , 33 , SH_UNT , SH_ACS_SCOM_RW , @@ -46311,10 +48544,14 @@ REG64_FLD( PU_INT_PC_VPC_CONFIG_RMT_FIRST_GRPSCAN_ENA , 42 , SH_UN SH_FLD_RMT_FIRST_GRPSCAN_ENA ); REG64_FLD( PU_INT_PC_VPC_CONFIG_LSMFB_SCAN_ALL_PRIO_ENA , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA ); -REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_44_51 , 44 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_44_51 ); -REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_44_51_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_44_51_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_P0_BACK2BACK_MODE_ENA ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_P0_BACK2BACK_MODE_ENA_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_47_51 , 47 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_47_51 ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_47_51_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_47_51_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE ); REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -46387,11 +48624,6 @@ REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG , 0 , SH_UN REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); -REG64_FLD( PU_INT_PC_VPC_ERR_CFG_REG_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ERROR_CONFIG ); -REG64_FLD( PU_INT_PC_VPC_ERR_CFG_REG_ERROR_CONFIG_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ERROR_CONFIG_LEN ); - REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, @@ -47019,10 +49251,12 @@ REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY , 58 , SH_UN REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DELAY_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_32_43 , 32 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_32_43 ); -REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_32_43_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_32_43_LEN ); +REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_PREVENT_MTP_AT_DEM_IN_PIPE , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PREVENT_MTP_AT_DEM_IN_PIPE ); +REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43 , 33 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_33_43 ); +REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_33_43_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_REGS ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , @@ -48398,10 +50632,12 @@ REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN , 5 , SH_UN SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_TRACE_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_ENABLE ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_59 , 57 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_57_59 ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_59_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_57_59_LEN ); +REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_58 , 57 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_57_58 ); +REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_58_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_57_58_LEN ); +REG64_FLD( PU_INT_VC_IVC_DEBUG_FAST_SB_LOOKUP_DISABLE , 59 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FAST_SB_LOOKUP_DISABLE ); REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT ); REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -50361,18 +52597,8 @@ REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR , 9 , SH_UN REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); -REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR ); -REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR_LEN ); -REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_ERR ); REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); -REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID ); -REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -50412,6 +52638,25 @@ REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); +REG64_FLD( PU_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_ADDR ); +REG64_FLD( PU_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_ADDR_LEN ); +REG64_FLD( PU_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_R_NW ); +REG64_FLD( PU_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_BUSY ); +REG64_FLD( PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); +REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_RSP_INFO ); +REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_RSP_INFO_LEN ); +REG64_FLD( PU_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_IFETCH_PENDING ); +REG64_FLD( PU_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PIB_DATAOP_PENDING ); + REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_WAIT ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT_LEN , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -50610,6 +52855,10 @@ REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UN REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_BKINV_INTERLOCK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DYN_ST_MODE_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_HANGP_EN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DYN_ST_MODE_HANGP_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LFSR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -50646,6 +52895,10 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS , 25 , SH_UN SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DYN_ST_MODE_THRESHOLD ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DYN_ST_MODE_THRESHOLD_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_PLS_MULT ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -50698,6 +52951,8 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN , 20 , SH_UN SH_FLD_INV_SINGLE_THREAD_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_CXT_CAC_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_MPSS_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_CNT_THRESH ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -50738,6 +52993,10 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN , 58 , SH_UN SH_FLD_TW_PTE_UPD_INTR_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN , 59 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT , 60 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DYN_ST_FREQ_MULT ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DYN_ST_FREQ_MULT_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS ); @@ -50761,6 +53020,10 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_PERR_CHK_DIS , 23 , SH_UN SH_FLD_CAC_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_LRU_PERR_CHK_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LRU_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MULTIHIT_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_EA_RANGE_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -50769,6 +53032,14 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL , 36 , SH_UN SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_GUEST_PREF_PGSZ ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_GUEST_PREF_PGSZ_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_HOST_PREF_PGSZ ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_HOST_PREF_PGSZ_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HRMOR ); @@ -50955,6 +53226,8 @@ REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0 , 16 , SH_UN SH_FLD_PORT_NUMBER_0 ); REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_0_LEN ); +REG64_FLD( PU_MODE_REGISTER_B_CHKSW_CMDQUEUEING_0 , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_CMDQUEUEING_0 ); REG64_FLD( PU_MODE_REGISTER_B_CHKSW_I2C_BUSY_0 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_0 ); REG64_FLD( PU_MODE_REGISTER_B_FGAT_0 , 28 , SH_UNT , SH_ACS_SCOM , @@ -50980,6 +53253,8 @@ REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1 , 16 , SH_UN SH_FLD_PORT_NUMBER_1 ); REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_1_LEN ); +REG64_FLD( PU_MODE_REGISTER_C_CHKSW_CMDQUEUEING_1 , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_CMDQUEUEING_1 ); REG64_FLD( PU_MODE_REGISTER_C_CHKSW_I2C_BUSY_1 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_1 ); REG64_FLD( PU_MODE_REGISTER_C_FGAT_1 , 28 , SH_UNT , SH_ACS_SCOM , @@ -51005,6 +53280,8 @@ REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2 , 16 , SH_UN SH_FLD_PORT_NUMBER_2 ); REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_2_LEN ); +REG64_FLD( PU_MODE_REGISTER_D_CHKSW_CMDQUEUEING_2 , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_CMDQUEUEING_2 ); REG64_FLD( PU_MODE_REGISTER_D_CHKSW_I2C_BUSY_2 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_2 ); REG64_FLD( PU_MODE_REGISTER_D_FGAT_2 , 28 , SH_UNT , SH_ACS_SCOM , @@ -51030,6 +53307,8 @@ REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3 , 16 , SH_UN SH_FLD_PORT_NUMBER_3 ); REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_3_LEN ); +REG64_FLD( PU_MODE_REGISTER_E_CHKSW_CMDQUEUEING_3 , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_CMDQUEUEING_3 ); REG64_FLD( PU_MODE_REGISTER_E_CHKSW_I2C_BUSY_3 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_3 ); REG64_FLD( PU_MODE_REGISTER_E_FGAT_3 , 28 , SH_UNT , SH_ACS_SCOM , @@ -51423,6 +53702,8 @@ REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_INTEST , 28 , SH_UN SH_FLD_HTB_INTEST ); REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); +REG64_FLD( PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_PLLFORCE_OUT_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); @@ -51452,6 +53733,10 @@ REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_OBS , 21 , SH_UN SH_FLD_ASYNC_OBS ); REG64_FLD( PEC_STACK0_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CPM_CAL_SET ); +REG64_FLD( PEC_STACK0_NET_CTRL1_SENSEADJ_RESET0 , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_SENSEADJ_RESET0 ); +REG64_FLD( PEC_STACK0_NET_CTRL1_SENSEADJ_RESET1 , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, + SH_FLD_SENSEADJ_RESET1 ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, @@ -51499,461 +53784,45 @@ REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UN REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - -REG64_FLD( PEC_STACK1_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - -REG64_FLD( PHB_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PHB_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - -REG64_FLD( PEC_STACK0_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - -REG64_FLD( PEC_STACK2_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PEC_STACK2_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PEC_STACK2_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PEC_STACK2_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PEC_STACK2_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PEC_STACK2_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PEC_STACK2_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PEC_STACK2_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PEC_STACK2_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); - -REG64_FLD( PEC_STACK1_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PEC_STACK1_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PEC_STACK1_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PEC_STACK1_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PEC_STACK1_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PEC_STACK1_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PEC_STACK1_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PEC_STACK1_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PEC_STACK1_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); - -REG64_FLD( PHB_NFIR_REG_BAR_PE , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PHB_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PHB_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PHB_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PHB_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PHB_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PHB_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PHB_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PHB_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PHB_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PHB_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PHB_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PHB_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PHB_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PHB_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PHB_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PHB_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PHB_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PHB_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PHB_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PHB_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PHB_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PHB_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PHB_NFIR_REG_AIB_PE , 23 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PHB_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PHB_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PHB_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PHB_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); - -REG64_FLD( PEC_STACK0_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PEC_STACK0_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PEC_STACK0_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PEC_STACK0_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PEC_STACK0_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PEC_STACK0_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PEC_STACK0_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PEC_STACK0_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PEC_STACK0_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK ); +REG64_FLD( PEC_STACK2_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK_LEN ); + +REG64_FLD( PEC_STACK1_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK ); +REG64_FLD( PEC_STACK1_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK_LEN ); + +REG64_FLD( PHB_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK ); +REG64_FLD( PHB_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK_LEN ); + +REG64_FLD( PEC_STACK0_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK ); +REG64_FLD( PEC_STACK0_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NFIRMASK_LEN ); + +REG64_FLD( PEC_STACK2_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR ); +REG64_FLD( PEC_STACK2_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR_LEN ); + +REG64_FLD( PEC_STACK1_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR ); +REG64_FLD( PEC_STACK1_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR_LEN ); + +REG64_FLD( PHB_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR ); +REG64_FLD( PHB_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR_LEN ); + +REG64_FLD( PEC_STACK0_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR ); +REG64_FLD( PEC_STACK0_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , + SH_FLD_NFIRNFIR_LEN ); REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); @@ -52684,7 +54553,7 @@ REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT , 27 , SH_UN REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN ); -REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 63 , SH_UNT_PU_NMMU , SH_ACS_SCOM , +REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); REG64_FLD( PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 63 , SH_UNT , SH_ACS_SCOM , @@ -53045,20 +54914,6 @@ REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX , 23 , SH_UN SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_RRN_ENABLE , 44 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_RRN_ENABLE ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_WINDOW_SIZE , 45 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_WINDOW_SIZE ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_WINDOW_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_WINDOW_SIZE_LEN ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MIN , 48 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_MATCH_TH_MIN ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MIN_LEN , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MAX , 56 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_MATCH_TH_MAX ); -REG64_FLD( PU_NX_RNG_ST1_SAMPTEST_MATCH_TH_MAX_LEN , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 ); @@ -53085,6 +54940,21 @@ REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1 , 38 , SH_UN REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_RRN_ENABLE ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_WINDOW_SIZE ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_WINDOW_SIZE_LEN ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_MATCH_TH_MIN ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_MATCH_TH_MAX ); +REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN ); + REG64_FLD( PU_NX_TRIGGER_CTRL_BITS , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS ); REG64_FLD( PU_NX_TRIGGER_CTRL_BITS_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , @@ -56052,8 +57922,8 @@ REG64_FLD( PEC_OPCG_REG1_UNUSED2_LEN , 2 , SH_UN SH_FLD_UNUSED2_LEN ); REG64_FLD( PEC_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RTIM_THOLD_FORCE ); -REG64_FLD( PEC_OPCG_REG1_USE_ARY_CLK_DURING_FILL , 53 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_USE_ARY_CLK_DURING_FILL ); +REG64_FLD( PEC_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL , 53 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DISABLE_ARY_CLK_DURING_FILL ); REG64_FLD( PEC_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SG_HIGH_DURING_FILL ); REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_PEC , SH_ACS_SCOM , @@ -58585,6 +60455,22 @@ REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB50_SPATTN , 46 , SH_UN SH_FLD_MB50_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB51_SPATTN , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_ERR , 52 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DOB01_ERR ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_ERR , 53 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DOB23_ERR ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_ERR , 54 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DOB45_ERR ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB01_ERR , 56 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DIB01_ERR ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB23_ERR , 57 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DIB23_ERR ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB45_ERR , 58 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DIB45_ERR ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_SCOM_ERR_DUP , 62 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_IOE_FIR_MASK_REG_SCOM_ERR , 63 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR00_TRAINED , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED ); @@ -58813,6 +60699,26 @@ REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB70_SPATTN , 50 , SH_UN SH_FLD_MB70_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB71_SPATTN , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB71_SPATTN ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_ERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DOB01_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_ERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DOB23_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_ERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DOB45_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_ERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DOB67_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB01_ERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DIB01_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB23_ERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DIB23_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB45_ERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DIB45_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB67_ERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_DIB67_ERR ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR_DUP , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR00_TRAINED , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED ); @@ -59437,6 +61343,106 @@ REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT , 12 , SH_UN REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LO_SELECT_LEN ); +REG64_FLD( PU_PB_PPE_LFIR_INTERNAL_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_ERROR ); +REG64_FLD( PU_PB_PPE_LFIR_EXTERNAL_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_EXTERNAL_ERROR ); +REG64_FLD( PU_PB_PPE_LFIR_PROGRESS_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PROGRESS_ERROR ); +REG64_FLD( PU_PB_PPE_LFIR_BREAKPOINT_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_BREAKPOINT_ERROR ); +REG64_FLD( PU_PB_PPE_LFIR_WATCHDOG , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_WATCHDOG ); +REG64_FLD( PU_PB_PPE_LFIR_HALTED , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_HALTED ); +REG64_FLD( PU_PB_PPE_LFIR_DEBUG_TRIGGER , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_DEBUG_TRIGGER ); +REG64_FLD( PU_PB_PPE_LFIR_SRAM_UE , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_UE ); +REG64_FLD( PU_PB_PPE_LFIR_SRAM_CE , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_CE ); +REG64_FLD( PU_PB_PPE_LFIR_SRAM_SCRUB_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SCRUB_ERR ); +REG64_FLD( PU_PB_PPE_LFIR_BCE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_BCE_ERROR ); +REG64_FLD( PU_PB_PPE_LFIR_SPARE11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE11 ); +REG64_FLD( PU_PB_PPE_LFIR_FIR_PARITY_ERR_DUP , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_FIR_PARITY_ERR_DUP ); +REG64_FLD( PU_PB_PPE_LFIR_FIR_PARITY_ERR , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_FIR_PARITY_ERR ); + +REG64_FLD( PU_PB_PPE_LFIRACT0_FIR_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION0 ); +REG64_FLD( PU_PB_PPE_LFIRACT0_FIR_ACTION0_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION0_LEN ); + +REG64_FLD( PU_PB_PPE_LFIRACT1_FIR_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION1 ); +REG64_FLD( PU_PB_PPE_LFIRACT1_FIR_ACTION1_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION1_LEN ); + +REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_FIR_MASK ); +REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK_LEN , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_FIR_MASK_LEN ); + +REG64_FLD( PU_PB_PSAVE_CFG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_PB_PSAVE_CFG_X0_ACT , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_X0_ACT ); +REG64_FLD( PU_PB_PSAVE_CFG_X1_ACT , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_X1_ACT ); +REG64_FLD( PU_PB_PSAVE_CFG_X2_ACT , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_X2_ACT ); +REG64_FLD( PU_PB_PSAVE_CFG_PS_SPARE1 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PS_SPARE1 ); +REG64_FLD( PU_PB_PSAVE_CFG_WSIZE , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WSIZE ); +REG64_FLD( PU_PB_PSAVE_CFG_WSIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WSIZE_LEN ); +REG64_FLD( PU_PB_PSAVE_CFG_LUC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LUC ); +REG64_FLD( PU_PB_PSAVE_CFG_LUC_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LUC_LEN ); +REG64_FLD( PU_PB_PSAVE_CFG_HUC , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HUC ); +REG64_FLD( PU_PB_PSAVE_CFG_HUC_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HUC_LEN ); +REG64_FLD( PU_PB_PSAVE_CFG_LUT , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LUT ); +REG64_FLD( PU_PB_PSAVE_CFG_LUT_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_LUT_LEN ); +REG64_FLD( PU_PB_PSAVE_CFG_HUT , 35 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HUT ); +REG64_FLD( PU_PB_PSAVE_CFG_HUT_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HUT_LEN ); + +REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_LO , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X0_LO ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_LO_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X0_LO_LEN ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_HI , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X0_HI ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X0_HI_LEN ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_LO , 19 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X1_LO ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_LO_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X1_LO_LEN ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_HI , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X1_HI ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X1_HI_LEN ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_LO , 35 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X2_LO ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_LO_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X2_LO_LEN ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI , 43 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X2_HI ); +REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_X2_HI_LEN ); + REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -59742,41 +61748,6 @@ REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP , 0 , SH_UN REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP_LEN , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_LATSTART ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_LATSTART_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_LATCANCEL ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_LATCANCEL_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT0 ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT0_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT1 ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT1_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT2 ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT2_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT3 ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_EVENT3_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_LATFINISH ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_LATFINISH_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -59812,41 +61783,6 @@ REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UN REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_LATSTART ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_LATSTART_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_LATCANCEL ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_LATCANCEL_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT0 ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT0_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT1 ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT1_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT2 ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT2_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT3 ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_EVENT3_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_LATFINISH ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_LATFINISH_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , @@ -59882,40 +61818,60 @@ REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UN REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_LATSTART ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_LATSTART_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_LATCANCEL ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_LATCANCEL_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESETMODE ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_FREEZEMODE ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_DISABLE_PMISC ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PMISC_MODE ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_CASCADE ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_CASCADE_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C0 ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C0_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C1 ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C1_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C2 ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C2_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C3 ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRESCALE_C3_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT0 ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT1 ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT2 ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT3 ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_LATFINISH ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_LATFINISH_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_ACT ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_LATENCY , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_LATENCY ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_LATENCY_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_LATENCY_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESERVED , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESERVED_LEN , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATSTART ); @@ -59952,6 +61908,297 @@ REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UN REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_ACT ); + +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESETMODE ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_FREEZEMODE ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_DISABLE_PMISC ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PMISC_MODE ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CASCADE ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CASCADE_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C0 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C0_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C1 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C1_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C2 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C2_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C3 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PRESCALE_C3_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED ); + +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_ACT ); + +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_ACT ); + +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESETMODE ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_FREEZEMODE ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_DISABLE_PMISC ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PMISC_MODE ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_CASCADE ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_CASCADE_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C0 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C0_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C1 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C1_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C2 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C2_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C3 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRESCALE_C3_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_LATENCY , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_LATENCY ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_LATENCY_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_LATENCY_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESERVED , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESERVED_LEN , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); + +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_ACT ); + +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_ACT ); + REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , @@ -60083,41 +62330,6 @@ REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UN REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_LATSTART ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_LATSTART_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_LATCANCEL ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_LATCANCEL_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT0 ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT0_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT1 ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT1_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT2 ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT2_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT3 ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_EVENT3_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_LATFINISH ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_LATFINISH_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , @@ -60153,67 +62365,6 @@ REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UN REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_ENABLE ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_RESETMODE ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_FREEZEMODE ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_DISABLE_PMISC ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PMISC_MODE ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_CASCADE ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_CASCADE_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C0 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C0_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C1 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C1_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C2 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C2_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C3 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_PRESCALE_C3_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT0 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT0_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT1 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT1_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT2 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT2_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT3 ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_EVENT3_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_LATSTART ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_LATSTART_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_LATCANCEL ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_LATCANCEL_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_LATFINISH ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_LATFINISH_LEN ); -REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_RESERVED ); - REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -60275,40 +62426,60 @@ REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UN REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_LATSTART ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_LATSTART_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_LATCANCEL ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_LATCANCEL_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_ENABLE , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( NV_PERF_CONFIG_RESETMODE , 1 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESETMODE ); +REG64_FLD( NV_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_FREEZEMODE ); +REG64_FLD( NV_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_DISABLE_PMISC ); +REG64_FLD( NV_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PMISC_MODE ); +REG64_FLD( NV_PERF_CONFIG_CASCADE , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_CASCADE ); +REG64_FLD( NV_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_CASCADE_LEN ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C0 ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C0_LEN ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C1 ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C1_LEN ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C2 ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C2_LEN ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C3 ); +REG64_FLD( NV_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRESCALE_C3_LEN ); +REG64_FLD( NV_PERF_CONFIG_EVENT0 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT0 ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT1 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT1 ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT2 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT2 ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT3 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT3 ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( NV_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_LATFINISH ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_LATFINISH_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_ACT ); +REG64_FLD( NV_PERF_CONFIG_LATENCY , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_LATENCY ); +REG64_FLD( NV_PERF_CONFIG_LATENCY_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_LATENCY_LEN ); +REG64_FLD( NV_PERF_CONFIG_RESERVED , 51 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( NV_PERF_CONFIG_RESERVED_LEN , 13 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATSTART ); @@ -60345,6 +62516,23 @@ REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UN REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT0 ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT0_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT1 ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT1_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT2 ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT2_LEN ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT3 ); +REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT3_LEN ); + REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -60396,6 +62584,40 @@ REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UN REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT0 ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT0_LEN ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT1 ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT1_LEN ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT2 ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT2_LEN ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT3 ); +REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT3_LEN ); + +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT0 ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT0_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT1 ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT1_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT2 ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT2_LEN ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT3 ); +REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_IDIAL_COUNT3_LEN ); + REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -60822,6 +63044,8 @@ REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_FACES , 3 , SH_UN SH_FLD_AUTO_PRE_INCREMENT_FACES ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_POST_DECREMENT_FACES ); +REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_CHKSW_AR012 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_AR012 ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); @@ -61126,6 +63350,57 @@ REG64_FLD( PU_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( NV_PRB_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_PRB_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_PRB_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( NV_PRB_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( NV_PRB_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( NV_PRB_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( NV_PRB_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( NV_PRB_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END_LEN ); + REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_TIMEOUT_MASK ); REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -62775,6 +65050,18 @@ REG64_FLD( PU_NPU2_REM1_ALU_TYPE_LEN , 4 , SH_UN REG64_FLD( PU_NPU2_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_SZ ); +REG64_FLD( PU_RESET_REGISTER_B_CHKSW_AR012_0 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_AR012_0 ); + +REG64_FLD( PU_RESET_REGISTER_C_CHKSW_AR012_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_AR012_1 ); + +REG64_FLD( PU_RESET_REGISTER_D_CHKSW_AR012_2 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_AR012_2 ); + +REG64_FLD( PU_RESET_REGISTER_E_CHKSW_AR012_3 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHKSW_AR012_3 ); + REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_0 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , @@ -62901,6 +65188,108 @@ REG64_FLD( PU_RNG_FAILED_INT_ADDRESS , 8 , SH_UN REG64_FLD( PU_RNG_FAILED_INT_ADDRESS_LEN , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( NV_RSP_DA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_RSP_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_RSP_DA_PTR_START , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( NV_RSP_DA_PTR_START_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( NV_RSP_DA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( NV_RSP_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( NV_RSP_DA_PTR_END , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( NV_RSP_DA_PTR_END_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( NV_RSP_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( NV_RSP_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( NV_RSP_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( NV_RSP_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( NV_RSP_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( NV_RSP_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( NV_RSP_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( NV_RSP_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_END_LEN ); + +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_START_LEN ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END ); +REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_END_LEN ); + REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_RXRF ); REG64_FLD( PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI , 2 , SH_UNT , SH_ACS_SCOM , @@ -63196,62 +65585,37 @@ REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL , 0 , SH_UN REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); -REG64_FLD( PU_N3_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_MASTERS ); -REG64_FLD( PU_N3_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_MASTERS_LEN ); - -REG64_FLD( PU_N1_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_MASTERS ); -REG64_FLD( PU_N1_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_MASTERS_LEN ); - -REG64_FLD( PU_N2_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_MASTERS ); -REG64_FLD( PU_N2_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_MASTERS_LEN ); - -REG64_FLD( PEC_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_MASTERS ); -REG64_FLD( PEC_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_MASTERS_LEN ); - -REG64_FLD( PU_N0_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_MASTERS ); -REG64_FLD( PU_N0_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_MASTERS_LEN ); - -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS , 0 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_SECURE_ACCESS ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY , 1 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LATE_LAUNCH_PRIMARY ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY , 2 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LATE_LAUNCH_SECONDARY ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED , 3 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LOCAL_QUIESCE_ACHIEVED ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK , 4 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_SEEPROM_UPDATE_LOCK ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS , 5 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LOCALITY_4_ACCESS ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG , 6 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_SECURE_DEBUG ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT , 7 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_CMFSI_ACCESS_PROTCT ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_I2C_EXTENDER , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, - SH_FLD_I2C_EXTENDER ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_MODE , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, - SH_FLD_SECURE_MODE ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_ABUS_LOCK , 8 , SH_UNT , SH_ACS_SCOM1 , + SH_FLD_ABUS_LOCK ); +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK , 9 , SH_UNT , SH_ACS_SCOM1 , + SH_FLD_NX_RAND_NUM_GEN_LOCK ); +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0 , 10 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_EX_SPARE0 ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1 , 11 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_EX_SPARE1 ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_RESERVED_0 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, - SH_FLD_RESERVED_0 ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_I2CM_TPM_DECONFIG_PROTECT , 12 , SH_UNT , SH_ACS_SCOM1 , + SH_FLD_I2CM_TPM_DECONFIG_PROTECT ); +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0 , 13 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_TP_SPARE0 ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1 , 14 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_TP_SPARE1 ); -REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, +REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_TP_SPARE2 ); REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR , 8 , SH_UNT , SH_ACS_SCOM , @@ -63339,46 +65703,44 @@ REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63406,46 +65768,44 @@ REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63473,46 +65833,44 @@ REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63540,46 +65898,44 @@ REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63607,46 +65963,44 @@ REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63674,46 +66028,44 @@ REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63741,46 +66093,44 @@ REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63808,46 +66158,44 @@ REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63875,46 +66223,44 @@ REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -63942,46 +66288,44 @@ REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -64009,46 +66353,44 @@ REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CREQ0 ); @@ -64076,46 +66418,44 @@ REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UN SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE0 ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE1 ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBLN ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBNNG ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBRNVG ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N0REQ ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N0DGD ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N1REQ ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N1DGD ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MMIO ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ATSXLATE ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBRSP ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N0RSP ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N1RSP ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_XARSP ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_SACOLL ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FREE ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); REG64_FLD( PEC_SPATTN_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_NC , SH_FLD_IN ); @@ -64825,7 +67165,7 @@ REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0_LEN , 64 , SH_UN REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1 ); -REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 17 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 22 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO , 0 , SH_UNT , SH_ACS_SCOM , @@ -64843,7 +67183,7 @@ REG64_FLD( PU_SU_ENGINE_ENABLE_CH0_EFT , 63 , SH_UN REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT ); -REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN , 47 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -65061,8 +67401,8 @@ REG64_FLD( PEC_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UN SH_FLD_USE_FOR_SCAN ); REG64_FLD( PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); -REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); +REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); REG64_FLD( PEC_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PEC , SH_ACS_SCOM , @@ -65185,6 +67525,502 @@ REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS , 15 , SH_UN REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN , 37 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ADDRESS_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , @@ -68943,8 +71779,16 @@ REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_TRACE , 32 , SH_UN SH_FLD_ENABLE_IN_TRACE ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_TRACE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_RG_TRACE ); +REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0 , 34 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_NORTH_UNUSED_BITS0 ); +REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_NORTH_UNUSED_BITS0_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_PMU_DATA ); +REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1 , 37 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_NORTH_UNUSED_BITS1 ); +REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DBG_NORTH_UNUSED_BITS1_LEN ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_IN_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING , 41 , SH_UNT , SH_ACS_SCOM_RW , @@ -68953,6 +71797,26 @@ REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_LO , 42 , SH_UN SH_FLD_IN_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_HI , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_INT_DATA_HI ); +REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_LO , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_DATA_LO ); +REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_HI , 45 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_DATA_HI ); +REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_LO , 46 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RG_TRACE_INT_DATA_LO ); +REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_HI , 47 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RG_TRACE_INT_DATA_HI ); +REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_01 , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IN_TRACE_INT_TRIG_01 ); +REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_23 , 49 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IN_TRACE_INT_TRIG_23 ); +REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_01 , 50 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_TRIG_01 ); +REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_23 , 51 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_TRIG_23 ); +REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_01 , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RG_TRACE_INT_TRIG_01 ); +REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_23 , 53 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RG_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_WC_INT_TRACE_DATA_LO ); @@ -69042,6 +71906,20 @@ REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING , 54 , SH_UN SH_FLD_ENABLE_CQ_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_LO , 55 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_INT_DATA_LO ); +REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_HI , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CQ_TRACE_INT_DATA_HI ); +REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_01 , 57 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WC_TRACE_INT_TRIG_01 ); +REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_23 , 58 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WC_TRACE_INT_TRIG_23 ); +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_01 , 59 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_TRIG_01 ); +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_23 , 60 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_TRIG_23 ); +REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_01 , 61 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CQ_TRACE_INT_TRIG_01 ); +REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_23 , 62 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CQ_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_BITS_64_87 ); @@ -69644,9 +72522,13 @@ REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT10 , 10 , SH_UN SH_FLD_RG_CERR_BIT10 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT11 ); -REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS , 12 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT12 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT13 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_UNUSED_BITS ); -REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN , 12 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_RMABAR_RMA_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -69726,10 +72608,18 @@ REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT16 , 16 , SH_UN SH_FLD_WC_CERR_BIT16 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT17 ); -REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_UNUSEDBITS , 18 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WC_CERR_UNUSEDBITS ); -REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_UNUSEDBITS_LEN , 6 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WC_CERR_UNUSEDBITS_LEN ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT18 , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT18 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT19 , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT19 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT20 , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT20 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT21 , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT21 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT22 , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT22 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT23 , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT23 ); REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR ); @@ -70267,6 +73157,103 @@ REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_AVAIL , 62 , SH_UN REG64_FLD( CAPP_XPT_CONTROL_LOAD_CI_BUFF , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LOAD_CI_BUFF ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PSL_CMD_UE_ERRHOLD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PSL_CMD_UE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PSL_CMD_SUE_ERRHOLD , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PSL_CMD_SUE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SC_RDATA_PARITY_ERRHOLD , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SC_RDATA_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_APC_SC_RDATA_PARITY_ERRHOLD , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC_SC_RDATA_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SN_SC_RDATA_PARITY_ERRHOLD , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SN_SC_RDATA_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_NX_DATA_RTAG_PARITY_ERRHOLD , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_NX_DATA_RTAG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_CE_ERRHOLD , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_NXPBXPT_PBRCV_ECC_CE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_UE_ERRHOLD , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_NXPBXPT_PBRCV_ECC_UE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_DBG_CTL_REG_PARITY_ERRHOLD , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DBG_CTL_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_CFG_REG_PARITY_ERRHOLD , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CFG_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_EVENT_SEL_REG_PARITY_ERRHOLD , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMU_EVENT_SEL_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PE0_CXA_LINKDOWN_ERRHOLD , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PE0_CXA_LINKDOWN_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PE1_CXA_LINKDOWN_ERRHOLD , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PE1_CXA_LINKDOWN_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SB_SCOM_ERRHOLD , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SB_SCOM_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PBXMIT_MSGQ_SEQ_ERRHOLD , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PBXMIT_MSGQ_SEQ_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_PBXMIT_DXMIT_SEQ_ERRHOLD , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PBXMIT_DXMIT_SEQ_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_FAILED_ERRHOLD , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RCS_RECOVERY_FAILED_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_STATE_MACHINE_ERRHOLD , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RCS_STATE_MACHINE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_LNK_RSP_PKT_DISCARDED_ERRHOLD , 25 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LNK_RSP_PKT_DISCARDED_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD , 26 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SECURE_LNK_SCOM_CONFLICT_ERRHOLD , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SECURE_LNK_SCOM_CONFLICT_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_UNSOLICITED_DATA_RCV_ERRHOLD , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_UNSOLICITED_DATA_RCV_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_RCMD0_PARITY_ERR_ERRHOLD , 29 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_AS_RCMD0_PARITY_ERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_REGS_PARITY_ERR_ERRHOLD , 30 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_AS_REGS_PARITY_ERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_SM_ERRHOLD , 31 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_AS_SM_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_REG_RDATA_PERR_ERRHOLD , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_AS_REG_RDATA_PERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_DFS_SM_ERRHOLD , 33 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DFS_SM_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_FIR_ERR_ERRHOLD , 34 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_FIR_ERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_CMD_DISCARDED_ERRHOLD , 35 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_CMD_DISCARDED_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_REG_RDATA_PERR_ERRHOLD , 36 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_REG_RDATA_PERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_RNG_WR_ENBL_REG_PERR_ERRHOLD , 37 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD , 39 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST0_BADIN_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST6_BADIN_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD , 41 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST7_BADIN_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD , 43 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_MISSING_SYNC_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_MISSING_STEP_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TB_RESIDUE_ERR_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD , 46 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TX_TFMR_CORRUPT_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD , 47 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST_CORRUPT_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TBST9_BADIN_ERRHOLD ); + REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMON_GROUP_SELECT ); REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -70274,8 +73261,8 @@ REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN , 4 , SH_UN REG64_FLD( PEC_XSTOP1_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); -REG64_FLD( PEC_XSTOP1_KEEP_EDRAM_ENABLED_ON , 1 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_KEEP_EDRAM_ENABLED_ON ); +REG64_FLD( PEC_XSTOP1_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); REG64_FLD( PEC_XSTOP1_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( PEC_XSTOP1_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , @@ -70309,8 +73296,8 @@ REG64_FLD( PEC_XSTOP1_WAIT_CYCLES_LEN , 12 , SH_UN REG64_FLD( PEC_XSTOP2_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); -REG64_FLD( PEC_XSTOP2_KEEP_EDRAM_ENABLED_ON , 1 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_KEEP_EDRAM_ENABLED_ON ); +REG64_FLD( PEC_XSTOP2_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); REG64_FLD( PEC_XSTOP2_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( PEC_XSTOP2_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , @@ -70344,8 +73331,8 @@ REG64_FLD( PEC_XSTOP2_WAIT_CYCLES_LEN , 12 , SH_UN REG64_FLD( PEC_XSTOP3_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); -REG64_FLD( PEC_XSTOP3_KEEP_EDRAM_ENABLED_ON , 1 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_KEEP_EDRAM_ENABLED_ON ); +REG64_FLD( PEC_XSTOP3_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); REG64_FLD( PEC_XSTOP3_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( PEC_XSTOP3_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , @@ -70869,6 +73856,46 @@ REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UN REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP1_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP1_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP2_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP2_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP3_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP3_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP4_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP4_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP5_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP5_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP6_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP6_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP7_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID ); +REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP7_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , + SH_FLD_LPARID_LEN ); + REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BRAZOS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BRAZOS ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_MMIOSD , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -70891,9 +73918,11 @@ REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF2DMD , 9 , SH_UN SH_FLD_PREF2DMD ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREFEVOD , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREFEVOD ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_EAINJ , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_EAINJ ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1 ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); @@ -70993,5 +74022,22 @@ REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT , 60 , SH_UN REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_TIMEOUT_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT0 ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT0_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT0_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT1 , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT1 ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT1_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT1_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT2 , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT2 ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT2_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT2_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT3 , 48 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT3 ); +REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT3_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_CNT3_LEN ); + #endif |
