diff options
| author | Ben Gass <bgass@us.ibm.com> | 2016-02-19 18:30:34 -0600 |
|---|---|---|
| committer | STEPHEN M. CPREK <smcprek@us.ibm.com> | 2016-02-23 13:05:29 -0600 |
| commit | 0c2164ca36d14d72d88ec46a8004d70a8ffbaab2 (patch) | |
| tree | f65092acf85923e98f7a5b4b4e0963c5785828e6 /import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | |
| parent | 9828c02438394e4b83d55f0c8d0c5bca05ba124f (diff) | |
| download | talos-sbe-0c2164ca36d14d72d88ec46a8004d70a8ffbaab2.tar.gz talos-sbe-0c2164ca36d14d72d88ec46a8004d70a8ffbaab2.zip | |
New scom address constants generated from e9034
Change-Id: I52e35aa1c91f215730dac2ae0b8d9f42332c49e0
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24545
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24630
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Diffstat (limited to 'import/chips/p9/common/include/p9_misc_scom_addresses_fld.H')
| -rw-r--r-- | import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | 11049 |
1 files changed, 7567 insertions, 3482 deletions
diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H index e5dadd38..40fdc373 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H @@ -132,6 +132,27 @@ REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); +REG64_FLD( PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PU_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N2 , @@ -195,6 +216,139 @@ REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); +REG64_FLD( PU_ADS_XSCOM_CMD_REG_RNW , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RNW ); +REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SIZE ); +REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SIZE_LEN ); +REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR ); +REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR_LEN , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR_LEN ); + +REG64_FLD( PU_ADU_HANG_DIV_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DATA ); +REG64_FLD( PU_ADU_HANG_DIV_REG_DATA_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_ADU_HANG_DIV_REG_OPER , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OPER ); +REG64_FLD( PU_ADU_HANG_DIV_REG_OPER_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OPER_LEN ); + +REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ADDRESS ); +REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS_LEN , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ADDRESS_LEN ); + +REG64_FLD( PU_ALTD_CMD_REG_FBC_START_OP , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_START_OP ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_CLEAR_STATUS , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_CLEAR_STATUS ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_RESET_FSM , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_RESET_FSM ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_RNW , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_RNW ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_AXTYPE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_AXTYPE ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_DATA_ONLY , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_DATA_ONLY ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCKED , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_LOCKED ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_LOCK_ID ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_LOCK_ID_LEN ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_SCOPE ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_SCOPE_LEN ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_AUTO_INC , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_AUTO_INC ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_DROP_PRIORITY ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY_MAX , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_DROP_PRIORITY_MAX ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_OVERWRITE_PBINIT ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_PIB_DIRECT , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PIB_DIRECT ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WITH_TM_QUIESCE ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_TTYPE ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_TTYPE_LEN ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_TSIZE ); +REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_TSIZE_LEN ); + +REG64_FLD( PU_ALTD_DATA_REG_FBC , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FBC ); +REG64_FLD( PU_ALTD_DATA_REG_FBC_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FBC_LEN ); + +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WITH_PRE_QUIESCE ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WITH_PBINIT_LOW_WAIT ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT , 51 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WITH_POST_INIT ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT , 54 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT ); +REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN ); + +REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WAIT_CMD_ARBIT ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDR_DONE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ADDR_DONE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_DATA_DONE , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_DATA_DONE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_RESP , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WAIT_RESP ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_OVERRUN_ERROR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_AUTOINC_ERROR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_COMMAND_ERROR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ADDRESS_ERROR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_OP_HANG_ERR , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PB_OP_HANG_ERR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_DATA_HANG_ERR , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PB_DATA_HANG_ERR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_CRESP_ERR , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_DATA_ERR , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PB_UNEXPECT_DATA_ERR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_PIB_DIRECT , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_WAIT_PIB_DIRECT ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_DIRECT_DONE , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PIB_DIRECT_DONE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PBINIT_MISSING ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR , 33 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PIB_ERROR ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_PIB_ERROR_LEN ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_CE , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ECC_CE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_UE , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ECC_UE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_SUE , 50 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_ECC_SUE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE , 59 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_CRESP_VALUE ); +REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_CRESP_VALUE_LEN ); + REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_PHB_SEL ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -404,6 +558,11 @@ REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UN REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_MASK_LEN ); +REG64_FLD( PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -884,130 +1043,130 @@ REG64_FLD( PEC_STACK0_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UN REG64_FLD( PEC_STACK0_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_INT_BAR_EN ); -REG64_FLD( PU_BCDE_CTL_STOP , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_BCDE_CTL_STOP , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_STOP ); -REG64_FLD( PU_BCDE_CTL_START , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_BCDE_CTL_START , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_START ); -REG64_FLD( PU_BCDE_OCIBAR_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_OCIBAR_ADDR , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR ); -REG64_FLD( PU_BCDE_OCIBAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_OCIBAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR_LEN ); -REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); -REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); -REG64_FLD( PU_BCDE_PBADR_PB_OFFSET , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_PB_OFFSET , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET ); -REG64_FLD( PU_BCDE_PBADR_PB_OFFSET_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_PB_OFFSET_LEN , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET_LEN ); -REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26 ); -REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26_LEN ); -REG64_FLD( PU_BCDE_PBADR_EXTADDR , 27 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_EXTADDR , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); -REG64_FLD( PU_BCDE_PBADR_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); -REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42 , 41 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42 , 41 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42 ); -REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42_LEN ); -REG64_FLD( PU_BCDE_SET_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_SET_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); -REG64_FLD( PU_BCDE_SET_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_SET_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); -REG64_FLD( PU_BCDE_SET_COPY_LENGTH , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_SET_COPY_LENGTH , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH ); -REG64_FLD( PU_BCDE_SET_COPY_LENGTH_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCDE_SET_COPY_LENGTH_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH_LEN ); -REG64_FLD( PU_BCDE_STAT_RUNNING , 0 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_RUNNING , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RUNNING ); -REG64_FLD( PU_BCDE_STAT_WAITING , 1 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_WAITING , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_WAITING ); -REG64_FLD( PU_BCDE_STAT_WRCMP , 2 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_WRCMP , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP ); -REG64_FLD( PU_BCDE_STAT_WRCMP_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_WRCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP_LEN ); -REG64_FLD( PU_BCDE_STAT_RDCMP , 14 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_RDCMP , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP ); -REG64_FLD( PU_BCDE_STAT_RDCMP_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_RDCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP_LEN ); -REG64_FLD( PU_BCDE_STAT_DEBUG , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_DEBUG , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG ); -REG64_FLD( PU_BCDE_STAT_DEBUG_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_DEBUG_LEN , 9 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_LEN ); -REG64_FLD( PU_BCDE_STAT_STOPPED , 29 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_STOPPED , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_STOPPED ); -REG64_FLD( PU_BCDE_STAT_ERROR , 30 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_ERROR , 30 , SH_UNT , SH_ACS_PIB , SH_FLD_ERROR ); -REG64_FLD( PU_BCDE_STAT_DONE , 31 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCDE_STAT_DONE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_DONE ); -REG64_FLD( PU_BCUE_CTL_STOP , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_BCUE_CTL_STOP , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_STOP ); -REG64_FLD( PU_BCUE_CTL_START , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_BCUE_CTL_START , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_START ); -REG64_FLD( PU_BCUE_OCIBAR_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_OCIBAR_ADDR , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR ); -REG64_FLD( PU_BCUE_OCIBAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_OCIBAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR_LEN ); -REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); -REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); -REG64_FLD( PU_BCUE_PBADR_PB_OFFSET , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_PB_OFFSET , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET ); -REG64_FLD( PU_BCUE_PBADR_PB_OFFSET_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_PB_OFFSET_LEN , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET_LEN ); -REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26 ); -REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26_LEN ); -REG64_FLD( PU_BCUE_PBADR_EXTADDR , 27 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_EXTADDR , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); -REG64_FLD( PU_BCUE_PBADR_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); -REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42 , 41 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42 , 41 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42 ); -REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42_LEN ); -REG64_FLD( PU_BCUE_SET_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_SET_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); -REG64_FLD( PU_BCUE_SET_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_SET_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); -REG64_FLD( PU_BCUE_SET_COPY_LENGTH , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_SET_COPY_LENGTH , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH ); -REG64_FLD( PU_BCUE_SET_COPY_LENGTH_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_BCUE_SET_COPY_LENGTH_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH_LEN ); -REG64_FLD( PU_BCUE_STAT_RUNNING , 0 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_RUNNING , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RUNNING ); -REG64_FLD( PU_BCUE_STAT_WAITING , 1 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_WAITING , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_WAITING ); -REG64_FLD( PU_BCUE_STAT_WRCMP , 2 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_WRCMP , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP ); -REG64_FLD( PU_BCUE_STAT_WRCMP_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_WRCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP_LEN ); -REG64_FLD( PU_BCUE_STAT_RDCMP , 14 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_RDCMP , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP ); -REG64_FLD( PU_BCUE_STAT_RDCMP_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_RDCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP_LEN ); -REG64_FLD( PU_BCUE_STAT_DEBUG , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_DEBUG , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG ); -REG64_FLD( PU_BCUE_STAT_DEBUG_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_DEBUG_LEN , 9 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_LEN ); -REG64_FLD( PU_BCUE_STAT_STOPPED , 29 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_STOPPED , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_STOPPED ); -REG64_FLD( PU_BCUE_STAT_ERROR , 30 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_ERROR , 30 , SH_UNT , SH_ACS_PIB , SH_FLD_ERROR ); -REG64_FLD( PU_BCUE_STAT_DONE , 31 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_BCUE_STAT_DONE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_DONE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -1592,6 +1751,8 @@ REG64_FLD( PEC_BIST_UNIT9 , 13 , SH_UN SH_FLD_UNIT9 ); REG64_FLD( PEC_BIST_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT10 ); +REG64_FLD( PEC_BIST_STROBE_WINDOW_EN , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STROBE_WINDOW_EN ); REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMER_ENABLE ); @@ -20654,11 +20815,6 @@ REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS , 37 , SH_UN REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_CLKRATIO_RATIO , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_RATIO ); -REG64_FLD( PU_CLKRATIO_RATIO_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_RATIO_LEN ); - REG64_FLD( PEC_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( PEC_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , @@ -20773,28 +20929,34 @@ REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME4_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME4_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME4_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME4_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME4_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME4_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME4_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME4_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME4_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20802,28 +20964,34 @@ REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME3_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME3_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME3_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME3_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME3_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME3_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME3_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME3_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME3_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20831,28 +20999,34 @@ REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME11_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME11_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME11_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME11_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME11_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME11_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME11_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME11_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME11_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20860,28 +21034,34 @@ REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME2_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME2_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME2_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME2_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME2_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME2_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME2_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME2_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME2_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20889,28 +21069,34 @@ REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME5_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME5_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME5_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME5_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME5_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME5_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME5_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME5_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME5_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20918,28 +21104,34 @@ REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME9_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME9_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME9_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME9_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME9_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME9_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME9_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME9_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME9_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20947,28 +21139,34 @@ REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME6_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME6_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME6_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME6_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME6_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME6_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME6_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME6_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME6_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -20976,28 +21174,34 @@ REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME10_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME10_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME10_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME10_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME10_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME10_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME10_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME10_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME10_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21005,28 +21209,34 @@ REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME8_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME8_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME8_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME8_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME8_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME8_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME8_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME8_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME8_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21034,28 +21244,34 @@ REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME1_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME1_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME1_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME1_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME1_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME1_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME1_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME1_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME1_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21063,28 +21279,34 @@ REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME0_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME0_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME0_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME0_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME0_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME0_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME0_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME0_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME0_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN ); @@ -21092,28 +21314,34 @@ REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UN SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_CME7_CME_LCL_DBG_EN_RISCTRACE , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_FULL_IVA , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_CME7_CME_LCL_DBG_DIS_TRACE_EXTRA , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_CME7_CME_LCL_DBG_DIS_TRACE_STALL , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_CME7_CME_LCL_DBG_EN_WIDE_TRACE , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_CME7_CME_LCL_DBG_SYNC_TIMER_SEL , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_CME7_CME_LCL_DBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_CME7_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_CME7_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_CME7_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); -REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_INPUT , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_HALT_INPUT ); +REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); @@ -21309,8 +21537,8 @@ REG64_FLD( PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME4_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -21371,10 +21599,10 @@ REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -21398,8 +21626,8 @@ REG64_FLD( PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME3_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -21460,10 +21688,10 @@ REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -21487,8 +21715,8 @@ REG64_FLD( PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME11_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -21549,10 +21777,10 @@ REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -21576,8 +21804,8 @@ REG64_FLD( PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME2_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -21638,10 +21866,10 @@ REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -21665,8 +21893,8 @@ REG64_FLD( PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME5_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -21727,10 +21955,10 @@ REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -21754,8 +21982,8 @@ REG64_FLD( PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME9_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -21816,10 +22044,10 @@ REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -21843,8 +22071,8 @@ REG64_FLD( PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME6_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -21905,10 +22133,10 @@ REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -21932,8 +22160,8 @@ REG64_FLD( PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME10_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -21994,10 +22222,10 @@ REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -22021,8 +22249,8 @@ REG64_FLD( PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME8_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -22083,10 +22311,10 @@ REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -22110,8 +22338,8 @@ REG64_FLD( PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME1_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -22172,10 +22400,10 @@ REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -22199,8 +22427,8 @@ REG64_FLD( PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME0_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -22261,10 +22489,10 @@ REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -22288,8 +22516,8 @@ REG64_FLD( PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UN SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME7_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_7 ); +REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -22350,10 +22578,10 @@ REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UN SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_38_39 , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39 ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_38_39_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_38_39_LEN ); +REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2 ); +REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -22427,61 +22655,157 @@ REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_ACK , 0 , SH_UN SH_FLD_COMM_ACK ); REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); +REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT ); +REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); +REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN ); +REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_COMM_RECV ); @@ -22803,8 +23127,6 @@ REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME4_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22826,8 +23148,6 @@ REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME3_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22849,8 +23169,6 @@ REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME11_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22872,8 +23190,6 @@ REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME2_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22895,8 +23211,6 @@ REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME5_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22918,8 +23232,6 @@ REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME9_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22941,8 +23253,6 @@ REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME6_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22964,8 +23274,6 @@ REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME10_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -22987,8 +23295,6 @@ REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME8_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23010,8 +23316,6 @@ REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME1_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23033,8 +23337,6 @@ REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME0_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23056,8 +23358,6 @@ REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME7_CME_LCL_PECESR0_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23079,8 +23379,6 @@ REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME4_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23102,8 +23400,6 @@ REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME3_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23125,8 +23421,6 @@ REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME11_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23148,8 +23442,6 @@ REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME2_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23171,8 +23463,6 @@ REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME5_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23194,8 +23484,6 @@ REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME9_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23217,8 +23505,6 @@ REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME6_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23240,8 +23526,6 @@ REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME10_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23263,8 +23547,6 @@ REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME8_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23286,8 +23568,6 @@ REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME1_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23309,8 +23589,6 @@ REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME0_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -23332,8 +23610,6 @@ REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE , 32 , SH_UN SH_FLD_USE_PECE ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); -REG64_FLD( PU_CME7_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); @@ -23347,10 +23623,12 @@ REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -23363,10 +23641,14 @@ REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -23416,10 +23698,12 @@ REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , @@ -23432,10 +23716,14 @@ REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , @@ -23485,10 +23773,12 @@ REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , @@ -23501,10 +23791,14 @@ REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , @@ -23554,10 +23848,12 @@ REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , @@ -23570,10 +23866,14 @@ REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , @@ -23623,10 +23923,12 @@ REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , @@ -23639,10 +23941,14 @@ REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , @@ -23692,10 +23998,12 @@ REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , @@ -23708,10 +24016,14 @@ REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , @@ -23761,10 +24073,12 @@ REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , @@ -23777,10 +24091,14 @@ REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , @@ -23830,10 +24148,12 @@ REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , @@ -23846,10 +24166,14 @@ REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , @@ -23899,10 +24223,12 @@ REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , @@ -23915,10 +24241,14 @@ REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , @@ -23968,10 +24298,12 @@ REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , @@ -23984,10 +24316,14 @@ REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , @@ -24037,10 +24373,12 @@ REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , @@ -24053,10 +24391,14 @@ REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , @@ -24106,10 +24448,12 @@ REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UN SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); -REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_RESERVED_6_9_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_6_8_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , @@ -24122,10 +24466,14 @@ REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UN SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); -REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_18_29_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , @@ -24859,6 +25207,210 @@ REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE , 42 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); + REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -24919,6 +25471,426 @@ REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA , 0 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_TIMER_MODE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_CHAR_MODE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CORE_DROPOUT_ENABLE_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPARE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_NOTIFY_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE ); +REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); + REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -28819,6 +29791,162 @@ REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES , 32 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); +REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); +REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE ); +REG64_FLD( PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROPOUT_SAMPLE_LEN ); + REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -29671,6 +30799,534 @@ REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA , 0 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_PROFILE_TYPE_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_TIMER_MODE ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_CHAR_MODE ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_NOTIFY_ENABLE ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPARE41_43 ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPARE41_43_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE ); +REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_DROOP_SAMPLE_RATE_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); + REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , @@ -30259,268 +31915,364 @@ REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR0_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); - -REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR ); +REG64_FLD( PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); + +REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME4_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME3_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME11_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME2_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME5_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME9_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME6_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME10_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME8_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME1_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME0_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); -REG64_FLD( PU_CME7_CME_SCOM_VTSR1_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART , 0 , SH_UNT , SH_ACS_SCOM , @@ -30792,9 +32544,11 @@ REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -30903,9 +32657,11 @@ REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -31014,9 +32770,11 @@ REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , @@ -31125,9 +32883,11 @@ REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , @@ -31236,9 +32996,11 @@ REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , @@ -31347,9 +33109,11 @@ REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , @@ -31458,9 +33222,11 @@ REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -31515,9 +33281,13 @@ REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UN SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); -REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 ); +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 ); +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); -REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , @@ -31626,9 +33396,11 @@ REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , @@ -31737,9 +33509,11 @@ REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , @@ -31848,9 +33622,11 @@ REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , @@ -31905,9 +33681,13 @@ REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UN SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); -REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 ); +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 ); +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); -REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -31962,9 +33742,13 @@ REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UN SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); -REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 ); +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 ); +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); -REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , @@ -32073,9 +33857,11 @@ REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , @@ -32184,9 +33970,11 @@ REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UN SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); -REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_OPT_SNOOP_CP ); +REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -34772,8 +36560,8 @@ REG64_FLD( PEC_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC , 40 , SH_UN SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC , 41 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC ); -REG64_FLD( PEC_CPLT_CONF0_ERR501 , 42 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_ERR501 ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_42C , 42 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_42C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_43C , 43 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43C ); REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_44C , 44 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -34805,42 +36593,42 @@ REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UN REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); -REG64_FLD( PEC_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_0D ); -REG64_FLD( PEC_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_1D ); -REG64_FLD( PEC_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_2D ); -REG64_FLD( PEC_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_3D ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_IOVALID , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_IOVALID ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_5D ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_6D ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_7D ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_8D ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_9D ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_10D ); -REG64_FLD( PEC_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_IOVALID_11D ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_SWAP_DC , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_SWAP_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_LANE_CFG_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_LANE_CFG_DC_LEN ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_OVERRIDE , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_RATIO_OVERRIDE ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_RATIO_DC ); -REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_PCI0_RATIO_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOX_MUX_VSEL ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOX_MUX_VSEL_LEN ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED ); +REG64_FLD( PEC_CPLT_CONF1_TC_PBE0_IOVALID_DC , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PBE0_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PBE1_IOVALID_DC , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PBE1_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PBE2_IOVALID_DC , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PBE2_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PBE3_IOVALID_DC , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PBE3_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PBE4_IOVALID_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PBE4_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PBE5_IOVALID_DC , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PBE5_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PSI_IOVALID_DC , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PSI_IOVALID_DC ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_12D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_13D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_14D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_15D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_16D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_17D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_18D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -34859,14 +36647,14 @@ REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UN SH_FLD_FREE_USAGE_26D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PCS , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOP_SYS_RESET_PCS ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PMA , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOP_SYS_RESET_PMA ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOP_HSSPORWREN , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOP_HSSPORWREN ); -REG64_FLD( PEC_CPLT_CONF1_TC_IOP_HSSPCLKOUTEN , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_TC_IOP_HSSPCLKOUTEN ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_28D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_29D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_30D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_31D ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC ); @@ -34999,16 +36787,16 @@ REG64_FLD( PEC_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UN SH_FLD_TC_REGION1_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); -REG64_FLD( PEC_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_7B ); -REG64_FLD( PEC_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_8B ); -REG64_FLD( PEC_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_9B ); -REG64_FLD( PEC_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_10B ); -REG64_FLD( PEC_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, - SH_FLD_UNUSED_11B ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION3_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION4_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION5_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION6_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION7_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_12B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, @@ -35231,27 +37019,6 @@ REG64_FLD( PU_CSAR_SRAM_ADDRESS , 16 , SH_UN REG64_FLD( PU_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS_LEN ); -REG64_FLD( PU_IOPPE_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_SRAM_ACCESS_MODE ); -REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_SRAM_SCRUB_ENABLE ); -REG64_FLD( PU_IOPPE_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_ECC_CORRECT_DIS ); -REG64_FLD( PU_IOPPE_CSCR_ECC_DETECT_DIS , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_ECC_DETECT_DIS ); -REG64_FLD( PU_IOPPE_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_ECC_INJECT_TYPE ); -REG64_FLD( PU_IOPPE_CSCR_ECC_INJECT_ERR , 5 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_ECC_INJECT_ERR ); -REG64_FLD( PU_IOPPE_CSCR_SPARE_6_7 , 6 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_IOPPE_CSCR_SPARE_6_7_LEN , 2 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_SPARE_6_7_LEN ); -REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_SRAM_SCRUB_INDEX ); -REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , - SH_FLD_SRAM_SCRUB_INDEX_LEN ); - REG64_FLD( PU_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_ACCESS_MODE ); REG64_FLD( PU_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT , SH_ACS_SCOM2_OR , @@ -36784,105 +38551,85 @@ REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST , 0 , SH_UN SH_FLD_GLB_BRCST ); REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TRACE_SEL_LEN ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); -REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , - SH_FLD_TRIG_SEL_LEN ); -REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); -REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); -REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); -REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TRACE_SEL_LEN ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); -REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , - SH_FLD_TRIG_SEL_LEN ); -REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); -REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); -REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); -REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TRACE_SEL_LEN ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); -REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , - SH_FLD_TRIG_SEL_LEN ); -REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); -REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); -REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); -REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TRACE_SEL_LEN ); -REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); -REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , - SH_FLD_TRIG_SEL_LEN ); -REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); -REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); -REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); -REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TRACE_SEL_LEN ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); -REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , - SH_FLD_TRIG_SEL_LEN ); -REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); -REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); -REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); -REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , @@ -37620,516 +39367,6 @@ REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UN REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -38181,106 +39418,55 @@ REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -38334,57 +39520,6 @@ REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -38436,106 +39571,106 @@ REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG0_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -38589,106 +39724,106 @@ REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( NV_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( NV_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( NV_DEBUG0_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , @@ -38742,516 +39877,6 @@ REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -39303,106 +39928,55 @@ REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -39456,57 +40030,6 @@ REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -39558,106 +40081,106 @@ REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( NV_DEBUG1_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -39711,106 +40234,106 @@ REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( NV_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( NV_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( NV_DEBUG1_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , @@ -41651,8 +42174,10 @@ REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR1 , 58 , SH_UN SH_FLD_MAP_REG_ERR1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4 , 59 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED4 ); -REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED4_LEN ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_MISS_IRQ , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_MISS_IRQ ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC ); @@ -42293,8 +42818,8 @@ REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_SUE , 36 , SH_UN SH_FLD_XPT_POWERBUS_SUE ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_TIMEOUT , 37 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_TIMEOUT ); -REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SEQ_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , - SH_FLD_TLBI_SEQ_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SOT_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_SOT_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_BAD_OP_ERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_BAD_OP_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SEQ_NUM_PARITY_ERR , 40 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , @@ -43038,6 +43563,15 @@ REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP , 0 , SH_UN REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FLUSH_SUE_STATE_MAP_LEN ); +REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_ITAG , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ALTD_DATA_ITAG ); +REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ALTD_DATA_TX ); +REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ALTD_DATA_TX_LEN ); +REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ALTD_DATA_TX_OVERWRITE ); + REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -43135,160 +43669,292 @@ REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UN SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); -REG64_FLD( PU_GPE0_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE0_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); -REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); -REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_GPE0_GPEDBG_EN_RISCTRACE , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_FULL_IVA , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_GPE0_GPEDBG_DIS_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_GPE0_GPEDBG_DIS_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_GPE0_GPEDBG_EN_WIDE_TRACE , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_GPE0_GPEDBG_SYNC_TIMER_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_GPE0_GPEDBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_GPE0_GPEDBG_FIR_TRIGGER , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE0_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_GPE0_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_GPE0_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_GPE0_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_GPE0_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_GPE0_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_GPE0_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_GPE0_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_GPE0_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15_LEN ); +REG64_FLD( PU_GPE0_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_GPE0_GPEDBG_SPARE , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE0_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); -REG64_FLD( PU_GPE0_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE0_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PU_GPE0_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_GPE0_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE0_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); @@ -43320,6 +43986,11 @@ REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UN REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); +REG64_FLD( PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR ); +REG64_FLD( PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR_LEN ); + REG64_FLD( PU_GPE0_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE0_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , @@ -43374,8 +44045,18 @@ REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR_LEN ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID ); +REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -43469,32 +44150,44 @@ REG64_FLD( PU_GPE0_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE0_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); -REG64_FLD( PU_GPE1_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE1_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); -REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); -REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_GPE1_GPEDBG_EN_RISCTRACE , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_FULL_IVA , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_GPE1_GPEDBG_DIS_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_GPE1_GPEDBG_DIS_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_GPE1_GPEDBG_EN_WIDE_TRACE , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_GPE1_GPEDBG_SYNC_TIMER_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_GPE1_GPEDBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_GPE1_GPEDBG_FIR_TRIGGER , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE1_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_GPE1_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_GPE1_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_GPE1_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_GPE1_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_GPE1_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_GPE1_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_GPE1_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_GPE1_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15_LEN ); +REG64_FLD( PU_GPE1_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_GPE1_GPEDBG_SPARE , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE1_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); -REG64_FLD( PU_GPE1_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE1_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PU_GPE1_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_GPE1_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE1_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); @@ -43526,6 +44219,11 @@ REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UN REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); +REG64_FLD( PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR ); +REG64_FLD( PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR_LEN ); + REG64_FLD( PU_GPE1_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE1_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , @@ -43580,8 +44278,18 @@ REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR_LEN ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID ); +REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -43675,32 +44383,44 @@ REG64_FLD( PU_GPE1_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE1_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); -REG64_FLD( PU_GPE2_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE2_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); -REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); -REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_GPE2_GPEDBG_EN_RISCTRACE , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_FULL_IVA , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_GPE2_GPEDBG_DIS_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_GPE2_GPEDBG_DIS_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_GPE2_GPEDBG_EN_WIDE_TRACE , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_GPE2_GPEDBG_SYNC_TIMER_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_GPE2_GPEDBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_GPE2_GPEDBG_FIR_TRIGGER , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE2_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_GPE2_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_GPE2_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_GPE2_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_GPE2_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_GPE2_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_GPE2_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_GPE2_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_GPE2_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15_LEN ); +REG64_FLD( PU_GPE2_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_GPE2_GPEDBG_SPARE , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE2_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); -REG64_FLD( PU_GPE2_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE2_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PU_GPE2_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_GPE2_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE2_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); @@ -43732,6 +44452,11 @@ REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UN REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); +REG64_FLD( PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR ); +REG64_FLD( PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR_LEN ); + REG64_FLD( PU_GPE2_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE2_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , @@ -43786,8 +44511,18 @@ REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR_LEN ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID ); +REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -43881,32 +44616,44 @@ REG64_FLD( PU_GPE2_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE2_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); -REG64_FLD( PU_GPE3_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE3_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); -REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); -REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); -REG64_FLD( PU_GPE3_GPEDBG_EN_RISCTRACE , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_RISCTRACE ); -REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_FULL_IVA , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_TRACE_FULL_IVA ); -REG64_FLD( PU_GPE3_GPEDBG_DIS_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_EXTRA ); -REG64_FLD( PU_GPE3_GPEDBG_DIS_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_DIS_TRACE_STALL ); -REG64_FLD( PU_GPE3_GPEDBG_EN_WIDE_TRACE , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EN_WIDE_TRACE ); -REG64_FLD( PU_GPE3_GPEDBG_SYNC_TIMER_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL ); -REG64_FLD( PU_GPE3_GPEDBG_SYNC_TIMER_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SYNC_TIMER_SEL_LEN ); -REG64_FLD( PU_GPE3_GPEDBG_FIR_TRIGGER , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE3_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_GPE3_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_INTR_ADDR ); +REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_EXTRA ); +REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_TRACE_STALL ); +REG64_FLD( PU_GPE3_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_WAIT_CYCLES ); +REG64_FLD( PU_GPE3_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_FULL_SPEED ); +REG64_FLD( PU_GPE3_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED9 ); +REG64_FLD( PU_GPE3_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL ); +REG64_FLD( PU_GPE3_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_MODE_SEL_LEN ); +REG64_FLD( PU_GPE3_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15 ); +REG64_FLD( PU_GPE3_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED12_15_LEN ); +REG64_FLD( PU_GPE3_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); -REG64_FLD( PU_GPE3_GPEDBG_SPARE , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE3_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); -REG64_FLD( PU_GPE3_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_GPE3_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PU_GPE3_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL ); +REG64_FLD( PU_GPE3_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE3_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); @@ -43938,6 +44685,11 @@ REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UN REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); +REG64_FLD( PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR ); +REG64_FLD( PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , + SH_FLD_PPE_XIXCR_XCR_LEN ); + REG64_FLD( PU_GPE3_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE3_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , @@ -43992,8 +44744,18 @@ REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UN REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR_LEN ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID ); +REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -44089,591 +44851,735 @@ REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN , 3 , SH_UN REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_GRANULE ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU0_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_GRANULE ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED ); -REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GPU1_RESERVED_LEN ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN0 ); @@ -47886,6 +48792,14 @@ REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL , 59 , SH_UN REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRITE_POOL_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_12_13 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_13 ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_12_13_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_13_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RELAXED_WR_ORDERING , 14 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RELAXED_WR_ORDERING ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_15 , 15 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_15 ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REGS_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -47911,10 +48825,12 @@ REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG , 56 , SH_UN REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN ); -REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_40_43 , 40 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_40_43 ); -REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_40_43_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_40_43_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_LIMIT_AT_DEM_IN_PIPE , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_LIMIT_AT_DEM_IN_PIPE ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43 , 41 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_41_43 ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_41_43_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_REGS ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , @@ -47931,14 +48847,14 @@ REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51 , 50 , SH_UN SH_FLD_RESERVED_50_51 ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51_LEN ); -REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_SBC_EOI_RESP , 52 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ATX_FOR_SBC_EOI_RESP ); -REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_SBC_EOI_RESP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ATX_FOR_SBC_EOI_RESP_LEN ); -REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA , 54 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_DMA ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_DMA_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD , 54 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_CI_LD ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_CI_LD_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_LD_RMT ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , @@ -47992,10 +48908,64 @@ REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63 , 61 , SH_UN REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63_LEN ); -REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_0_31 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_31 ); -REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_0_31_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_0_31_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_CRESP_CORR , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_CRESP_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_ARX_DAT_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_ARX_DAT_CORR_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_TAG_CORR , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_ARX_TAG_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_MMIO_LDST_CORR , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_MMIO_LDST_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_MMIO_RSP_CORR , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_MMIO_RSP_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_VRQ_QUEUE_CORR , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_VRQ_QUEUE_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_AVX_CORR , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_AVX_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_CMD_CORR , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_ATX_CMD_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_BAR_CORR , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_ATX_BAR_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_AT_CORR , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_ATX_AT_CORR ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_11_15 , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_11_15 ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_11_15_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_11_15_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_FORCE_SINGLE_BIT_ERR , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FORCE_SINGLE_BIT_ERR ); +REG64_FLD( PU_INT_PC_DBG_ECC_FORCE_DOUBLE_BIT_ERR , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FORCE_DOUBLE_BIT_ERR ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CRESP_SRAM , 18 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_CRESP_SRAM ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_19 , 19 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_19 ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_RSP_SRAM , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_CMD_RSP_SRAM ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_VRQ_SRAM , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_CMD_VRQ_SRAM ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_CMD_SSA ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_CMD_SSA_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_VPC_SSA ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_VPC_SSA_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_BAR_SRAM , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_BAR_SRAM ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AT_SSA , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_AT_SSA ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_AIB ); +REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ARY_SELECT_ATX_AIB_LEN ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31 , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_15 ); @@ -49720,10 +50690,14 @@ REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE , 32 , SH_UN SH_FLD_SYNC_DONE ); REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYNC_DONE_LEN ); -REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_51 , 37 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_37_51 ); -REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_51_LEN , 15 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_37_51_LEN ); +REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_45 , 37 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_37_45 ); +REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_45_LEN , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_37_45_LEN ); +REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE , 46 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_PTAG_IN_USE ); +REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE ); REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -50596,18 +51570,16 @@ REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA , 0 , SH_UN REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_32_33 ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_32_33_LEN ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION , 34 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32 ); +REG64_FLD( PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE , 33 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_PTAG_IN_USE ); +REG64_FLD( PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_PTAG_IN_USE_LEN ); +REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_38_41 , 38 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_38_41 ); -REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_38_41_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_38_41_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_STATE_ECC_CORRECTION , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44 , 43 , SH_UNT , SH_ACS_SCOM_RW , @@ -51017,6 +51989,14 @@ REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA , 0 , SH_UN REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); +REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_44_46 , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_44_46 ); +REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_44_46_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_44_46_LEN ); +REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE , 47 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_PTAG_IN_USE ); +REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE ); REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -51269,6 +52249,11 @@ REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA , 0 , SH_UN REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA_LEN , 64 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TABLE_DATA_LEN ); +REG64_FLD( PU_IO_DATA_REG_PCB_TMP , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PCB_TMP ); +REG64_FLD( PU_IO_DATA_REG_PCB_TMP_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PCB_TMP_LEN ); + REG64_FLD( PU_IVT_OFFSET_PAYLOAD , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PAYLOAD ); REG64_FLD( PU_IVT_OFFSET_PAYLOAD_LEN , 28 , SH_UNT , SH_ACS_SCOM , @@ -51471,20 +52456,22 @@ REG64_FLD( PEC_LOCAL_FIR_IN39 , 39 , SH_UN SH_FLD_IN39 ); REG64_FLD( PEC_LOCAL_FIR_IN40 , 40 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN40 ); +REG64_FLD( PEC_LOCAL_FIR_IN41 , 41 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN41 ); REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); -REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN_LEN , 41 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN_LEN , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); -REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN_LEN , 41 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN_LEN , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN ); -REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN_LEN , 41 , SH_UNT_PEC , SH_ACS_SCOM2_OR , +REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN_LEN , 42 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , @@ -51531,6 +52518,8 @@ REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UN SH_FLD_IN20 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN21 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN22 , 22 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN22 ); REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); @@ -52137,161 +53126,35 @@ REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1 , 34 , SH_UN REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_LPC_BASE_REG_BASE , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BASE ); +REG64_FLD( PU_LPC_BASE_REG_BASE_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BASE_LEN ); +REG64_FLD( PU_LPC_BASE_REG_DISABLE , 63 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE ); -REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_LPC_CMD_REG_RNW , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RNW ); +REG64_FLD( PU_LPC_CMD_REG_SIZE , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SIZE ); +REG64_FLD( PU_LPC_CMD_REG_SIZE_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SIZE_LEN ); +REG64_FLD( PU_LPC_CMD_REG_ADR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR ); +REG64_FLD( PU_LPC_CMD_REG_ADR_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR_LEN ); -REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_LPC_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_LPC_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); -REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_LPC_STATUS_REG_DONE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DONE ); +REG64_FLD( PU_LPC_STATUS_REG_VALID , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_VALID ); +REG64_FLD( PU_LPC_STATUS_REG_ACK , 11 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ACK ); REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_UE_ERR ); @@ -52311,9 +53174,11 @@ REG64_FLD( PU_MCC_FIR_REG_MCD_TTAG_PARITY_ERR , 7 , SH_UN SH_FLD_MCD_TTAG_PARITY_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_UPDATE_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_UPDATE_ERR ); -REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_ACK_DEAD_CRESP_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR ); -REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 10 , SH_UNT , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , @@ -52334,9 +53199,11 @@ REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_TTAG_PARITY_ERR , 7 , SH_UN SH_FLD_MCD_TTAG_PARITY_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UPDATE_ERR , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_UPDATE_ERR ); -REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_ACK_DEAD_CRESP_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR ); -REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD_DBG_TRACE_ENABLE , 3 , SH_UNT , SH_ACS_SCOM , @@ -52467,6 +53334,8 @@ REG64_FLD( PU_MCD_ECAP_RDWR_UPDATE_ERROR , 53 , SH_UN SH_FLD_RDWR_UPDATE_ERROR ); REG64_FLD( PU_MCD_ECAP_REC_UPDATE_ERROR , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_REC_UPDATE_ERROR ); +REG64_FLD( PU_MCD_ECAP_REC_ACK_DEAD_ERROR , 55 , SH_UNT , SH_ACS_SCOM , + SH_FLD_REC_ACK_DEAD_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CLEAR , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_CLEAR ); @@ -52530,25 +53399,27 @@ REG64_FLD( PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR , 53 , SH_UN SH_FLD_RDWR_UPDATE_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR , 54 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_REC_UPDATE_ERROR ); +REG64_FLD( PU_MCD1_MCD_ECAP_REC_ACK_DEAD_ERROR , 55 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , + SH_FLD_REC_ACK_DEAD_ERROR ); REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); -REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); -REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , +REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN , 12 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); -REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); -REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , +REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN , 12 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , @@ -52569,9 +53440,11 @@ REG64_FLD( PU_MCD_FIR_MASK_REG_TTAG_PARITY , 7 , SH_UN SH_FLD_TTAG_PARITY ); REG64_FLD( PU_MCD_FIR_MASK_REG_UPDATE_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UPDATE_ERR ); -REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCD_FIR_MASK_REG_ACK_DEAD_CRESP , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ACK_DEAD_CRESP ); +REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 10 , SH_UNT , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , @@ -52592,13 +53465,25 @@ REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_TTAG_PARITY , 7 , SH_UN SH_FLD_TTAG_PARITY ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UPDATE_ERR , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_UPDATE_ERR ); -REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ACK_DEAD_CRESP , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_ACK_DEAD_CRESP ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); -REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_TAG_ADDR_LEN ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_ERR ); REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID ); +REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); @@ -53075,6 +53960,118 @@ REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL_LEN , 4 , SH_UN REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_DISABLE , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DISABLE ); +REG64_FLD( PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0_LEN , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1_LEN , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_NMMU_MM_FIR1_MASK_REG_MASK , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_MASK ); +REG64_FLD( PU_NMMU_MM_FIR1_MASK_REG_MASK_LEN , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_MASK_LEN ); + +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_CE_DET , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_XLAT_ARY_ECC_CE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_UE_DET , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_XLAT_ARY_ECC_UE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_SUE_DET , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_XLAT_ARY_ECC_SUE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_CE_DET , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_CQRD_ARY_ECC_CE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_UE_DET , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_CQRD_ARY_ECC_UE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_SUE_DET , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_CQRD_ARY_ECC_SUE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_PROT_ERR_DET , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_XLAT_PROT_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_TIMEOUT_DET , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_XLAT_TIMEOUT_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_DIR_PERR_DET , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SLB_DIR_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_CAC_PERR_DET , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SLB_CAC_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_LRU_PERR_DET , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SLB_LRU_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_MULTIHIT_DET , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SLB_MULTIHIT_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_DIR_PERR_DET , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TLB_DIR_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_CAC_PERR_DET , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TLB_CAC_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_LRU_PERR_DET , 14 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TLB_LRU_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_MULTIHIT_DET , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TLB_MULTIHIT_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_SEG_FAULT_DET , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_SEG_FAULT_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_NOPTE_DET , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_PG_FAULT_NOPTE_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_BPCHK_DET , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_PG_FAULT_BPCHK_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_VPCHK_DET , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_PG_FAULT_VPCHK_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_SEID_DET , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_PG_FAULT_SEID_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_RD_DET , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_ADD_ERR_CR_RD_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PTE_UPD_FAIL_DET , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_PTE_UPD_FAIL_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_WR_DET , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_ADD_ERR_CR_WR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_GUEST_DET , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_RDX_CFG_GUEST_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_HOST_DET , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_RDX_CFG_HOST_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_INVALID_WIMG_DET , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_INVALID_WIMG_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_INV_RDX_QUAD_DET , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_INV_RDX_QUAD_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_FOREIGN_ADDR_DET , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_FOREIGN_ADDR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PREFETCH_ABT_DET , 29 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_PREFETCH_ABT_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_CXT_CAC_PERR_DET , 30 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_CXT_CAC_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_PWC_PERR_DET , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_RDX_PWC_PERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_SM_CTL_ERR_DET , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_SM_CTL_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_CO_SM_CTL_ERR_DET , 33 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_CO_SM_CTL_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_CI_SM_CTL_ERR_DET , 34 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_CI_SM_CTL_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_INV_SM_CTL_ERR_DET , 35 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_INV_SM_CTL_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_TIMEOUT_ERR_DET , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_TW_TIMEOUT_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_CO_TIMEOUT_ERR_DET , 37 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_CO_TIMEOUT_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_CI_TIMEOUT_ERR_DET , 38 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_CI_TIMEOUT_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_INV_TIMEOUT_ERR_DET , 39 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_INV_TIMEOUT_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_NX0_LXSTOP_ERR_DET , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_NX0_LXSTOP_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_CP0_LXSTOP_ERR_DET , 41 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_CP0_LXSTOP_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_CP1_LXSTOP_ERR_DET , 42 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_CP1_LXSTOP_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_NPU_LXSTOP_ERR_DET , 43 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_NPU_LXSTOP_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_LXSTOP_ERR_DET , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_FBC_LXSTOP_ERR_DET ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SPARE , 45 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SPARE ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SCOM_PE_FIR , 46 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_PE_FIR ); +REG64_FLD( PU_NMMU_MM_FIR1_REG_SCOM_PE_DUP_FIR , 47 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_PE_DUP_FIR ); + REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_EN , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS0_STG2_SEL , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -53346,305 +54343,509 @@ REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4 , 3 , SH_UN REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST4_LEN ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ENABLE ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT0_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2 ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_NDT0_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ENABLE ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NDT1_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2 ); -REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_NDT1_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); REG64_FLD( PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); @@ -54887,19 +56088,19 @@ REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN , 3 , SH_UN SH_FLD_ADAPTEST_WINDOW_SIZE_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH , 20 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH , 28 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH , 36 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH ); -REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH , 0 , SH_UNT , SH_ACS_SCOM , @@ -55960,8 +57161,8 @@ REG64_FLD( PU_OCB_OCI_OISR0_PPC405_HALT , 9 , SH_UN SH_FLD_PPC405_HALT ); REG64_FLD( PU_OCB_OCI_OISR0_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERROR ); -REG64_FLD( PU_OCB_OCI_OISR0_SPIPSS_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_SPIPSS_ERROR ); +REG64_FLD( PU_OCB_OCI_OISR0_SPARE_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_11 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_PPC405 , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_PPC405 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE0 , 13 , SH_UNT , SH_ACS_SCOM2_OR , @@ -58434,91 +59635,91 @@ REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT , 40 , SH_UN REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN ); -REG64_FLD( PU_PBAMODE_RESERVED_0_3 , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_RESERVED_0_3 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_3 ); -REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_3_LEN ); -REG64_FLD( PU_PBAMODE_DIS_REARB , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_REARB , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_REARB ); -REG64_FLD( PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_MSTID_MATCH_PREF_INV ); -REG64_FLD( PU_PBAMODE_DIS_SLAVE_RDPIPE , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_SLAVE_RDPIPE , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_SLAVE_RDPIPE ); -REG64_FLD( PU_PBAMODE_DIS_SLAVE_WRPIPE , 7 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_SLAVE_WRPIPE , 7 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_SLAVE_WRPIPE ); -REG64_FLD( PU_PBAMODE_EN_MARKER_ACK , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_EN_MARKER_ACK , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_MARKER_ACK ); -REG64_FLD( PU_PBAMODE_RESERVED_9 , 9 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_RESERVED_9 , 9 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_9 ); -REG64_FLD( PU_PBAMODE_EN_SECOND_WRBUF , 10 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_EN_SECOND_WRBUF , 10 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_SECOND_WRBUF ); -REG64_FLD( PU_PBAMODE_DIS_REREQUEST_TO , 11 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_REREQUEST_TO , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_REREQUEST_TO ); -REG64_FLD( PU_PBAMODE_INJECT_TYPE , 12 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_INJECT_TYPE , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_TYPE ); -REG64_FLD( PU_PBAMODE_INJECT_TYPE_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_INJECT_TYPE_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_TYPE_LEN ); -REG64_FLD( PU_PBAMODE_INJECT_MODE , 14 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_INJECT_MODE , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_MODE ); -REG64_FLD( PU_PBAMODE_INJECT_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_INJECT_MODE_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_MODE_LEN ); -REG64_FLD( PU_PBAMODE_PBA_REGION , 16 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_PBA_REGION , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_PBA_REGION ); -REG64_FLD( PU_PBAMODE_PBA_REGION_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_PBA_REGION_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PBA_REGION_LEN ); -REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE , 18 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_OCI_MARKER_SPACE ); -REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE_LEN , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_OCI_MARKER_SPACE_LEN ); -REG64_FLD( PU_PBAMODE_BCDE_OCITRANS , 21 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_BCDE_OCITRANS , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BCDE_OCITRANS ); -REG64_FLD( PU_PBAMODE_BCDE_OCITRANS_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_BCDE_OCITRANS_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_BCDE_OCITRANS_LEN ); -REG64_FLD( PU_PBAMODE_BCUE_OCITRANS , 23 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_BCUE_OCITRANS , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_BCUE_OCITRANS ); -REG64_FLD( PU_PBAMODE_BCUE_OCITRANS_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_BCUE_OCITRANS_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_BCUE_OCITRANS_LEN ); -REG64_FLD( PU_PBAMODE_DIS_MASTER_RD_PIPE , 25 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_MASTER_RD_PIPE , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_MASTER_RD_PIPE ); -REG64_FLD( PU_PBAMODE_DIS_MASTER_WR_PIPE , 26 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_MASTER_WR_PIPE , 26 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_MASTER_WR_PIPE ); -REG64_FLD( PU_PBAMODE_EN_SLV_FAIRNESS , 27 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_EN_SLV_FAIRNESS , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_SLV_FAIRNESS ); -REG64_FLD( PU_PBAMODE_EN_EVENT_COUNT , 28 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_EN_EVENT_COUNT , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_EVENT_COUNT ); -REG64_FLD( PU_PBAMODE_PB_NOCI_EVENT_SEL , 29 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_PB_NOCI_EVENT_SEL , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_NOCI_EVENT_SEL ); -REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX , 30 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX , 30 , SH_UNT , SH_ACS_PIB , SH_FLD_SLV_EVENT_MUX ); -REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SLV_EVENT_MUX_LEN ); -REG64_FLD( PU_PBAMODE_ENABLE_DEBUG_BUS , 32 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_ENABLE_DEBUG_BUS , 32 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE_DEBUG_BUS ); -REG64_FLD( PU_PBAMODE_DEBUG_PB_NOT_OCI , 33 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DEBUG_PB_NOT_OCI , 33 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_PB_NOT_OCI ); -REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE , 34 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE , 34 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_OCI_MODE ); -REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_OCI_MODE_LEN ); -REG64_FLD( PU_PBAMODE_RESERVED_39 , 39 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_RESERVED_39 , 39 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_39 ); -REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK , 40 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK , 40 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_FAIRNESS_MASK ); -REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_FAIRNESS_MASK_LEN ); -REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV , 45 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV , 45 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_REREQ_HANG_DIV ); -REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_REREQ_HANG_DIV_LEN ); -REG64_FLD( PU_PBAMODE_DIS_CHGRATE_COUNT , 50 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_DIS_CHGRATE_COUNT , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_CHGRATE_COUNT ); -REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX , 51 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX , 51 , SH_UNT , SH_ACS_PIB , SH_FLD_PBREQ_EVENT_MUX ); -REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PBREQ_EVENT_MUX_LEN ); -REG64_FLD( PU_PBAMODE_RESERVED_53_63 , 53 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_RESERVED_53_63 , 53 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_53_63 ); -REG64_FLD( PU_PBAMODE_RESERVED_53_63_LEN , 11 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAMODE_RESERVED_53_63_LEN , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_53_63_LEN ); REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -58526,58 +59727,58 @@ REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET , 0 , SH_UN REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_ACTION_SET_LEN ); -REG64_FLD( PU_PBAPBOCR0_EVENT , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR0_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); -REG64_FLD( PU_PBAPBOCR0_EVENT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR0_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); -REG64_FLD( PU_PBAPBOCR0_ACCUM , 44 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR0_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); -REG64_FLD( PU_PBAPBOCR0_ACCUM_LEN , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR0_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); -REG64_FLD( PU_PBAPBOCR1_EVENT , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR1_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); -REG64_FLD( PU_PBAPBOCR1_EVENT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR1_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); -REG64_FLD( PU_PBAPBOCR1_ACCUM , 44 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR1_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); -REG64_FLD( PU_PBAPBOCR1_ACCUM_LEN , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR1_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); -REG64_FLD( PU_PBAPBOCR2_EVENT , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR2_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); -REG64_FLD( PU_PBAPBOCR2_EVENT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR2_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); -REG64_FLD( PU_PBAPBOCR2_ACCUM , 44 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR2_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); -REG64_FLD( PU_PBAPBOCR2_ACCUM_LEN , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR2_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); -REG64_FLD( PU_PBAPBOCR3_EVENT , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR3_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); -REG64_FLD( PU_PBAPBOCR3_EVENT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR3_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); -REG64_FLD( PU_PBAPBOCR3_ACCUM , 44 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR3_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); -REG64_FLD( PU_PBAPBOCR3_ACCUM_LEN , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR3_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); -REG64_FLD( PU_PBAPBOCR4_EVENT , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR4_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); -REG64_FLD( PU_PBAPBOCR4_EVENT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR4_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); -REG64_FLD( PU_PBAPBOCR4_ACCUM , 44 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR4_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); -REG64_FLD( PU_PBAPBOCR4_ACCUM_LEN , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR4_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); -REG64_FLD( PU_PBAPBOCR5_EVENT , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR5_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); -REG64_FLD( PU_PBAPBOCR5_EVENT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR5_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); -REG64_FLD( PU_PBAPBOCR5_ACCUM , 44 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR5_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); -REG64_FLD( PU_PBAPBOCR5_ACCUM_LEN , 20 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAPBOCR5_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , @@ -58706,241 +59907,241 @@ REG64_FLD( PU_PBARBUFVAL5_MASTERID , 41 , SH_UN REG64_FLD( PU_PBARBUFVAL5_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); -REG64_FLD( PU_PBASLVCTL0_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); -REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); -REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); -REG64_FLD( PU_PBASLVCTL0_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); -REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); -REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); -REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); -REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); -REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); -REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); -REG64_FLD( PU_PBASLVCTL0_READ_TTYPE , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); -REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); -REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); -REG64_FLD( PU_PBASLVCTL0_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); -REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); -REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); -REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); -REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); -REG64_FLD( PU_PBASLVCTL0_RESERVED_23 , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); -REG64_FLD( PU_PBASLVCTL0_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); -REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); -REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); -REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); -REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); -REG64_FLD( PU_PBASLVCTL0_EXTADDR , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); -REG64_FLD( PU_PBASLVCTL0_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); -REG64_FLD( PU_PBASLVCTL0_RESERVED_50 , 50 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL0_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); -REG64_FLD( PU_PBASLVCTL1_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); -REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); -REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); -REG64_FLD( PU_PBASLVCTL1_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); -REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); -REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); -REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); -REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); -REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); -REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); -REG64_FLD( PU_PBASLVCTL1_READ_TTYPE , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); -REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); -REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); -REG64_FLD( PU_PBASLVCTL1_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); -REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); -REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); -REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); -REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); -REG64_FLD( PU_PBASLVCTL1_RESERVED_23 , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); -REG64_FLD( PU_PBASLVCTL1_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); -REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); -REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); -REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); -REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); -REG64_FLD( PU_PBASLVCTL1_EXTADDR , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); -REG64_FLD( PU_PBASLVCTL1_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); -REG64_FLD( PU_PBASLVCTL1_RESERVED_50 , 50 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL1_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); -REG64_FLD( PU_PBASLVCTL2_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); -REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); -REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); -REG64_FLD( PU_PBASLVCTL2_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); -REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); -REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); -REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); -REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); -REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); -REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); -REG64_FLD( PU_PBASLVCTL2_READ_TTYPE , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); -REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); -REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); -REG64_FLD( PU_PBASLVCTL2_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); -REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); -REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); -REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); -REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); -REG64_FLD( PU_PBASLVCTL2_RESERVED_23 , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); -REG64_FLD( PU_PBASLVCTL2_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); -REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); -REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); -REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); -REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); -REG64_FLD( PU_PBASLVCTL2_EXTADDR , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); -REG64_FLD( PU_PBASLVCTL2_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); -REG64_FLD( PU_PBASLVCTL2_RESERVED_50 , 50 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL2_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); -REG64_FLD( PU_PBASLVCTL3_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); -REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); -REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); -REG64_FLD( PU_PBASLVCTL3_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); -REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); -REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); -REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); -REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); -REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); -REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); -REG64_FLD( PU_PBASLVCTL3_READ_TTYPE , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); -REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); -REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); -REG64_FLD( PU_PBASLVCTL3_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); -REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); -REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); -REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); -REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); -REG64_FLD( PU_PBASLVCTL3_RESERVED_23 , 23 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); -REG64_FLD( PU_PBASLVCTL3_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); -REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); -REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); -REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); -REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); -REG64_FLD( PU_PBASLVCTL3_EXTADDR , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); -REG64_FLD( PU_PBASLVCTL3_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); -REG64_FLD( PU_PBASLVCTL3_RESERVED_50 , 50 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBASLVCTL3_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); -REG64_FLD( PU_PBASLVRST_SET , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_SET , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_SET ); -REG64_FLD( PU_PBASLVRST_SET_LEN , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_SET_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SET_LEN ); -REG64_FLD( PU_PBASLVRST_IN_PROG , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_IN_PROG , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_IN_PROG ); -REG64_FLD( PU_PBASLVRST_IN_PROG_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_IN_PROG_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_IN_PROG_LEN ); -REG64_FLD( PU_PBASLVRST_BUSY_STATUS , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_BUSY_STATUS , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_BUSY_STATUS ); -REG64_FLD( PU_PBASLVRST_BUSY_STATUS_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_BUSY_STATUS_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_BUSY_STATUS_LEN ); -REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR , 12 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_SCOPE_ATTN_BAR ); -REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SCOPE_ATTN_BAR_LEN ); REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , @@ -58977,174 +60178,174 @@ REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT , 41 , SH_UN REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BYTE_COUNT_LEN ); -REG64_FLD( PU_PBAXCFG_PBAX_EN , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_PBAX_EN , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PBAX_EN ); -REG64_FLD( PU_PBAXCFG_RESERVATION_EN , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RESERVATION_EN , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVATION_EN ); -REG64_FLD( PU_PBAXCFG_SND_RESET , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_SND_RESET , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RESET ); -REG64_FLD( PU_PBAXCFG_RCV_RESET , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_RESET , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_RESET ); -REG64_FLD( PU_PBAXCFG_RCV_GROUPID , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_GROUPID , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_GROUPID ); -REG64_FLD( PU_PBAXCFG_RCV_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_GROUPID_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_GROUPID_LEN ); -REG64_FLD( PU_PBAXCFG_RCV_CHIPID , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_CHIPID , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CHIPID ); -REG64_FLD( PU_PBAXCFG_RCV_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_CHIPID_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CHIPID_LEN ); -REG64_FLD( PU_PBAXCFG_RESERVED_11 , 11 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RESERVED_11 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11 ); -REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP , 12 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_BRDCST_GROUP ); -REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_BRDCST_GROUP_LEN ); -REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV , 20 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_DATATO_DIV ); -REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_DATATO_DIV_LEN ); -REG64_FLD( PU_PBAXCFG_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26 ); -REG64_FLD( PU_PBAXCFG_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26_LEN ); -REG64_FLD( PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM , 27 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_COUNT_OVERCOM ); -REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH , 28 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_THRESH ); -REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_THRESH_LEN ); -REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV , 36 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RSVTO_DIV ); -REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RSVTO_DIV_LEN ); -REG64_FLD( PU_PBAXRCVSTAT_RCV_IN_PROGRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXRCVSTAT_RCV_IN_PROGRESS , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_IN_PROGRESS ); -REG64_FLD( PU_PBAXRCVSTAT_RCV_ERROR , 1 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXRCVSTAT_RCV_ERROR , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_ERROR ); -REG64_FLD( PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS , 2 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_WRITE_IN_PROGRESS ); -REG64_FLD( PU_PBAXRCVSTAT_RCV_RESERVATION_SET , 3 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXRCVSTAT_RCV_RESERVATION_SET , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_RESERVATION_SET ); -REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE , 4 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CAPTURE ); -REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CAPTURE_LEN ); -REG64_FLD( PU_PBAXSHBR0_PUSH_START , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSHBR0_PUSH_START , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START ); -REG64_FLD( PU_PBAXSHBR0_PUSH_START_LEN , 29 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSHBR0_PUSH_START_LEN , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START_LEN ); -REG64_FLD( PU_PBAXSHBR1_PUSH_START , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSHBR1_PUSH_START , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START ); -REG64_FLD( PU_PBAXSHBR1_PUSH_START_LEN , 29 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSHBR1_PUSH_START_LEN , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START_LEN ); -REG64_FLD( PU_PBAXSHCS0_PUSH_FULL , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_FULL , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_FULL ); -REG64_FLD( PU_PBAXSHCS0_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_EMPTY ); -REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3 ); -REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3_LEN ); -REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1 ); -REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); -REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH ); -REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH_LEN ); -REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR ); -REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR_LEN ); -REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR ); -REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR_LEN ); -REG64_FLD( PU_PBAXSHCS0_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS0_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_ENABLE ); -REG64_FLD( PU_PBAXSHCS1_PUSH_FULL , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_FULL , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_FULL ); -REG64_FLD( PU_PBAXSHCS1_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_EMPTY ); -REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3 ); -REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3_LEN ); -REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1 ); -REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); -REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH ); -REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH_LEN ); -REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR ); -REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR_LEN ); -REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR ); -REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR_LEN ); -REG64_FLD( PU_PBAXSHCS1_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PBAXSHCS1_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_ENABLE ); -REG64_FLD( PU_PBAXSNDSTAT_SND_IN_PROGRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_IN_PROGRESS , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_IN_PROGRESS ); -REG64_FLD( PU_PBAXSNDSTAT_SND_ERROR , 1 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_ERROR , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_ERROR ); -REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS , 2 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_PHASE_STATUS ); -REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_PHASE_STATUS_LEN ); -REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS , 4 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT_STATUS ); -REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT_STATUS_LEN ); -REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT , 8 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_COUNT ); -REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_COUNT_LEN ); -REG64_FLD( PU_PBAXSNDTX_SND_SCOPE , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_SCOPE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_SCOPE ); -REG64_FLD( PU_PBAXSNDTX_SND_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_SCOPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_SCOPE_LEN ); -REG64_FLD( PU_PBAXSNDTX_SND_QID , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_QID , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_QID ); -REG64_FLD( PU_PBAXSNDTX_SND_TYPE , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_TYPE , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_TYPE ); -REG64_FLD( PU_PBAXSNDTX_SND_RESERVATION , 5 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_RESERVATION , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RESERVATION ); -REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7 , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7 , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_6_7 ); -REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_6_7_LEN ); -REG64_FLD( PU_PBAXSNDTX_SND_GROUPID , 8 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_GROUPID , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_GROUPID ); -REG64_FLD( PU_PBAXSNDTX_SND_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_GROUPID_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_GROUPID_LEN ); -REG64_FLD( PU_PBAXSNDTX_SND_CHIPID , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_CHIPID , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CHIPID ); -REG64_FLD( PU_PBAXSNDTX_SND_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_CHIPID_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CHIPID_LEN ); -REG64_FLD( PU_PBAXSNDTX_RESERVED_15 , 15 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_RESERVED_15 , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_15 ); -REG64_FLD( PU_PBAXSNDTX_VG_TARGE , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_VG_TARGE , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_VG_TARGE ); -REG64_FLD( PU_PBAXSNDTX_VG_TARGE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_VG_TARGE_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_VG_TARGE_LEN ); -REG64_FLD( PU_PBAXSNDTX_SND_STOP , 59 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_STOP , 59 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_STOP ); -REG64_FLD( PU_PBAXSNDTX_SND_CNT , 60 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_CNT , 60 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT ); -REG64_FLD( PU_PBAXSNDTX_SND_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PBAXSNDTX_SND_CNT_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT_LEN ); REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -59163,10 +60364,8 @@ REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY , 8 , SH_UN SH_FLD_PE_CQ_REGISTER_ARRAY ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_REGISTER_ARRAY_LEN ); -REG64_FLD( PEC_PBCQEINJ_REG_PE_EINJ_STACK , 11 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_EINJ_STACK ); -REG64_FLD( PEC_PBCQEINJ_REG_PE_EINJ_STACK_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_EINJ_STACK_LEN ); +REG64_FLD( PEC_PBCQEINJ_REG_PE_CONSTANT_EINJ , 11 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_PE_CONSTANT_EINJ ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_POLL_SCALE ); @@ -59343,6 +60542,376 @@ REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE , 12 , SH_UN REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_SPARE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_RESET_MODE , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_RESET_MODE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_COUNTER_MODE , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COUNTER_MODE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_DIS , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GLOBAL_PMISC_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_MODE , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GLOBAL_PMISC_MODE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EXTERNAL_FREEZE , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_EXTERNAL_FREEZE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_0_1_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_0_1_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_2_3_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_2_3_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_4_5_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_4_5_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_6_7_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_6_7_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_8_9_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_8_9_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_10_11_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_10_11_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_12_13_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_12_13_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_14_15_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_14_15_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_16_17_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_16_17_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_18_19_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_18_19_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_20_21_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_20_21_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_22_23_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_22_23_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_24_25_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_24_25_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_26_27_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_26_27_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_28_29_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_28_29_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_30_31_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_30_31_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1 , 41 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2 , 44 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3 , 47 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MASK , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS0_MASK , 51 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC2_MCS0_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS1_MASK , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC2_MCS1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC3_MCS0_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC3_MCS1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MCD_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PE0_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE1_MASK , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PE1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE2_MASK , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PE2_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_VAS_MASK , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_VAS_MASK ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_RESET_MODE , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_RESET_MODE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_COUNTER_MODE , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COUNTER_MODE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_DIS , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GLOBAL_PMISC_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_MODE , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GLOBAL_PMISC_MODE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EXTERNAL_FREEZE , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_EXTERNAL_FREEZE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_0_1_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_0_1_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_2_3_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_2_3_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_4_5_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_4_5_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_6_7_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_6_7_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_8_9_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_8_9_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_10_11_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_10_11_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_12_13_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_12_13_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_14_15_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_14_15_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_16_17_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_16_17_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_18_19_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_18_19_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_20_21_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_20_21_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_22_23_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_22_23_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_24_25_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_24_25_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_26_27_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_26_27_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_28_29_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_28_29_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_30_31_OP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_30_31_OP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1 , 41 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2 , 44 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3 , 47 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CASCADE_PMU3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MASK , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS0_MASK , 51 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC0_MCS0_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS1_MASK , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC0_MCS1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS0_MASK , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC1_MCS0_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS1_MASK , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MC1_MCS1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_INT_MASK , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_INT_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE0_MASK , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PE0_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PE1_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PE2_MASK ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_POLARITY , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_POLARITY ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE , 61 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SCOPE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SCOPE_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTYPE_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TSIZE_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TTAG_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_POLARITY , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CRESP_POLARITY ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE , 61 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SCOPE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SCOPE_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPA_SCOPE_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPA_SCOPE_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPA_PRESP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPA_PRESP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPA_PRESP_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPA_PRESP_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPB_SCOPE_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPB_SCOPE_MASK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP , 35 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPB_PRESP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPB_PRESP_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK , 49 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPB_PRESP_MASK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_COMPB_PRESP_MASK_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1 , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2 , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3 , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL4 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL4_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5 , 15 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL5 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL5_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6 , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL6 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL6_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7 , 21 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL7 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_SEL7_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_BITWISE_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_CFG_CNPME_BITWISE_ENABLE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_BITWISE_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, + SH_ACS_SCOM , SH_FLD_CFG_CNPMW_BITWISE_ENABLE_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PMU_PORT ); + REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , @@ -59427,6 +60996,804 @@ REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR , 16 , SH_UN REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL4 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL4_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL5 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL5_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL6 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL6_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL7 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL7_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL4 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL4_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL5 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL5_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL6 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL6_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL7 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_LVL7_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX0_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX1_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX2_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX3_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX4_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX5_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX6_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_AGGREGATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_FP_DISABLED ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_INDIRECT_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_GATHER_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX0_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX1_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX2_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX3_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX4_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX5_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX6_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_AGGREGATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_FP_DISABLED ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_INDIRECT_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_GATHER_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MASTER_CHIP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TM_MASTER ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_GP_MASTER ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_SP_MASTER ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA0_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA1_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA2_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA3_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_AGGREGATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_HOP , 29 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_HOP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SMP_OPTICS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CAPI , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CAPI ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0 , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1 , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2 , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_GATHER_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PHYP_IS_GROUP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_ADDR_BAR ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_DCACHE_CAPP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MASTER_CHIP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TM_MASTER ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_GP_MASTER ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_SP_MASTER ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA0_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA1_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA2_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA3_ADDR_DIS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_AGGREGATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_HOP , 29 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_HOP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SMP_OPTICS ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CAPI , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CAPI ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0 , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1 , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2 , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_GATHER_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PHYP_IS_GROUP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_ADDR_BAR ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PUMP , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_DCACHE_CAPP ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_DD1_MODE , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_DD1_MODE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_SEL ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_PMU_FREEZE_MODE , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_PMU_FREEZE_MODE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_LM_HI_COMP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_LM_HI_COMP_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP , 12 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_LM_LO_COMP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_LM_LO_COMP_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHIP_IS_SYSTEM ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_HNG_CHK_DISABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_DBG_CLR_MAX_HANG_STAGE , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_DBG_CLR_MAX_HANG_STAGE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SW_AB_WAIT ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SW_AB_WAIT_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SP_HW_MARK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SP_HW_MARK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK , 23 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GP_HW_MARK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GP_HW_MARK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LCL_HW_MARK ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_REQ_GATHER_ENABLE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SWITCH_CD_PULSE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SWITCH_OPTION_AB ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_RESET_ERROR_CAPTURE , 63 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_RESET_ERROR_CAPTURE ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_ENABLE , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_ENABLE ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_SAMPLE_SEL ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_SAMPLE_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_EN , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_PMUCNT_EN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_PMUCNT_SEL ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_PMUCNT_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_NM_HI_COMP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_NM_HI_COMP_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP , 12 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_NM_LO_COMP ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_APM_NM_LO_COMP_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1 , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2 , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3 , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP0_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0 , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1 , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP1_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0 , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1 , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2 , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3 , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP2_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0 , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1 , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2 , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3 , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPME_GRP3_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C0 , 33 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1 , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2 , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP0_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0 , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1 , 42 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2 , 44 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3 , 46 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP1_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0 , 48 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1 , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2 , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3 , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP2_C3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0 , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1 , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2 , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3 , 62 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CNPMW_GRP3_C3_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL4 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL4_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL5 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL5_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL6 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL6_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL7 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL7_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL4 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL4_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL5 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL5_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL6 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL6_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL7 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_RNS_LVL7_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SLOW , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SLOW ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_COUNT ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_COUNT_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELECT ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELECT_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_DATA ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_DATA_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL4 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL4_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL5 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL5_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL6 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL6_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL7 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL7_LEN ); + +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL0 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL0_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL1 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL1_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL2 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL2_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL3 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL3_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL4 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL4_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL5 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL5_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL6 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL6_LEN ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL7 ); +REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , + SH_FLD_CFG_VG_LVL7_LEN ); + +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1 , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2 , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3 , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELSN3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0 , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR0 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR0_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1 , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR1 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR1_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR2 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR2_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR3 ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELCR3_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIEN_DBG_0_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIEN_DBG_0_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIEN_DBG_1_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIEN_DBG_1_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIES_DBG_0_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIES_DBG_0_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIES_DBG_1_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIES_DBG_1_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIOT_DBG_0_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIOT_DBG_0_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIOT_DBG_1_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIOT_DBG_1_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_SEL , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PBIOT_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT , 29 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELRT ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELRT_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_EN , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_EN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_TRIG , 33 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_TRIG ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_COUNTER_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_COUNTER_SEL_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_COUNTER_MATCH ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_COUNTER_MATCH_LEN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_PRESCALE , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_ENABLE_PERFTRACE_PRESCALE ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_FIXED_WIN , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_ENABLE_PERFTRACE_FIXED_WIN ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP1_SEL , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_GRP1_SEL ); +REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP2_SEL , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PERFTRACE_GRP2_SEL ); + REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , @@ -59575,6 +61942,356 @@ REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR , 32 , SH_UN REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_EN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_EN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX0_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX1_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX2_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX3_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX4_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX5_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX6_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_AGGREGATE , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_AGGREGATE ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_FP_DISABLED , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_FP_DISABLED ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_INDIRECT_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_GATHER_ENABLE ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE ); +REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_EN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_EN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_EN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_EN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX0_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX1_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX2_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX3_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX4_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX5_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX6_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID_LEN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_AGGREGATE , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_AGGREGATE ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_FP_DISABLED , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_FP_DISABLED ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_INDIRECT_EN ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_GATHER_ENABLE ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE ); +REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_MASTER_CHIP , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_MASTER_CHIP ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_TM_MASTER , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_TM_MASTER ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_GP_MASTER ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_SP_MASTER ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_EN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA0_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA1_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA2_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA3_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_AGGREGATE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_AGGREGATE ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_HOP , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_HOP ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_SMP_OPTICS , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SMP_OPTICS ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CAPI , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CAPI ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT0 , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT0 ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT0_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT0_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT1 , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT1 ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT1_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT1_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT2 , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT2 ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT2_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT2_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT3 , 38 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT3 ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT3_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT3_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_GATHER_ENABLE ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_PHYP_IS_GROUP ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_ADDR_BAR , 53 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_ADDR_BAR ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PUMP , 54 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_DCACHE_CAPP , 55 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_DCACHE_CAPP ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE ); +REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_MASTER_CHIP , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_MASTER_CHIP ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_TM_MASTER , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_TM_MASTER ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_GP_MASTER ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_SP_MASTER ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_EN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_EN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_EN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_EN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_EN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA0_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA1_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA2_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA3_ADDR_DIS ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_AGGREGATE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_AGGREGATE ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_HOP , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_HOP ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_SMP_OPTICS , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SMP_OPTICS ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CAPI , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CAPI ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0 , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT0 ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT0_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1 , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT1 ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT1_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2 , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT2 ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT2_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3 , 38 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT3 ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_OPT3_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_GATHER_ENABLE ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_PHYP_IS_GROUP ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_ADDR_BAR , 53 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_ADDR_BAR ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PUMP , 54 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_DCACHE_CAPP , 55 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_DCACHE_CAPP ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE ); +REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_CHIP_IS_SYSTEM ); +REG64_FLD( PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_HNG_CHK_DISABLE ); +REG64_FLD( PU_PB_EAST_MODE_DBG_CLR_MAX_HANG_STAGE , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DBG_CLR_MAX_HANG_STAGE ); +REG64_FLD( PU_PB_EAST_MODE_CFG_SW_AB_WAIT , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SW_AB_WAIT ); +REG64_FLD( PU_PB_EAST_MODE_CFG_SW_AB_WAIT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SW_AB_WAIT_LEN ); +REG64_FLD( PU_PB_EAST_MODE_CFG_SP_HW_MARK , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SP_HW_MARK ); +REG64_FLD( PU_PB_EAST_MODE_CFG_SP_HW_MARK_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SP_HW_MARK_LEN ); +REG64_FLD( PU_PB_EAST_MODE_CFG_GP_HW_MARK , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_GP_HW_MARK ); +REG64_FLD( PU_PB_EAST_MODE_CFG_GP_HW_MARK_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_GP_HW_MARK_LEN ); +REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LCL_HW_MARK ); +REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_REQ_GATHER_ENABLE ); +REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SWITCH_CD_PULSE ); +REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SWITCH_OPTION_AB ); + +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SLOW , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SLOW ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_COUNT ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_COUNT_LEN ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SELECT ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SELECT_LEN ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_DATA ); +REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_DATA_LEN ); + REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , @@ -61705,6 +64422,360 @@ REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UN REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX0_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX1_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX2_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX3_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX4_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX5_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX6_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_AGGREGATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_FP_DISABLED ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_INDIRECT_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_GATHER_ENABLE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX0_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX1_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX2_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX3_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX4_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX5_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NX6_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X0_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X1_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X2_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X3_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X4_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X5_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_X6_CHIPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_AGGREGATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_FP_DISABLED ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_INDIRECT_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_GATHER_ENABLE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_X_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MASTER_CHIP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TM_MASTER ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_GP_MASTER ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_SP_MASTER ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA0_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA1_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA2_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA3_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_AGGREGATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_HOP , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_HOP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SMP_OPTICS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CAPI , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CAPI ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0 , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1 , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2 , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3 , 38 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_GATHER_ENABLE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PHYP_IS_GROUP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_ADDR_BAR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PUMP , 54 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_DCACHE_CAPP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_MASTER_CHIP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_TM_MASTER ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_GP_MASTER ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHG_RATE_SP_MASTER ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_EN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA0_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA1_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA2_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_NA3_ADDR_DIS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A0_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A1_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A2_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LINK_A3_GROUPID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_AGGREGATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_HOP , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_HOP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SMP_OPTICS ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CAPI , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CAPI ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0 , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT0_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1 , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT1_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2 , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT2_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3 , 38 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3 ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_OPT3_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_GATHER_ENABLE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PHYP_IS_GROUP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_ADDR_BAR ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PUMP , 54 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_DCACHE_CAPP ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_A_CMD_RATE_LEN ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CHIP_IS_SYSTEM ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_HNG_CHK_DISABLE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_DBG_CLR_MAX_HANG_STAGE , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_DBG_CLR_MAX_HANG_STAGE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SW_AB_WAIT ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SW_AB_WAIT_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SP_HW_MARK ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SP_HW_MARK_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK , 23 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GP_HW_MARK ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_GP_HW_MARK_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LCL_HW_MARK ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_LCL_HW_MARK_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CPU_RATIO_OVERRIDE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_REQ_GATHER_ENABLE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SWITCH_CD_PULSE ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SWITCH_OPTION_AB ); + +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SLOW , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SLOW ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_COUNT ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_COUNT_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELECT ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SELECT_LEN ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_DATA ); +REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , + SH_FLD_CFG_SHIFT_DATA_LEN ); + REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , @@ -62928,6 +65999,86 @@ REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE , 0 , SH_UN REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_DFREEZE_LEN ); +REG64_FLD( PU_PBAIB_STACK5_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0 ); +REG64_FLD( PU_PBAIB_STACK5_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0_LEN ); + +REG64_FLD( PHB_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0 ); +REG64_FLD( PHB_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0_LEN ); + +REG64_FLD( PU_PBAIB_STACK2_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0 ); +REG64_FLD( PU_PBAIB_STACK2_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0_LEN ); + +REG64_FLD( PU_PBAIB_STACK1_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0 ); +REG64_FLD( PU_PBAIB_STACK1_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION0_LEN ); + +REG64_FLD( PU_PBAIB_STACK5_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1 ); +REG64_FLD( PU_PBAIB_STACK5_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1_LEN ); + +REG64_FLD( PHB_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1 ); +REG64_FLD( PHB_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1_LEN ); + +REG64_FLD( PU_PBAIB_STACK2_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1 ); +REG64_FLD( PU_PBAIB_STACK2_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1_LEN ); + +REG64_FLD( PU_PBAIB_STACK1_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1 ); +REG64_FLD( PU_PBAIB_STACK1_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , + SH_FLD_PFIRACTION1_LEN ); + +REG64_FLD( PU_PBAIB_STACK5_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK ); +REG64_FLD( PU_PBAIB_STACK5_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK_LEN ); + +REG64_FLD( PHB_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK ); +REG64_FLD( PHB_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK_LEN ); + +REG64_FLD( PU_PBAIB_STACK2_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK ); +REG64_FLD( PU_PBAIB_STACK2_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK_LEN ); + +REG64_FLD( PU_PBAIB_STACK1_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK ); +REG64_FLD( PU_PBAIB_STACK1_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PFIRMASK_LEN ); + +REG64_FLD( PU_PBAIB_STACK5_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR ); +REG64_FLD( PU_PBAIB_STACK5_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR_LEN ); + +REG64_FLD( PHB_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR ); +REG64_FLD( PHB_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR_LEN ); + +REG64_FLD( PU_PBAIB_STACK2_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR ); +REG64_FLD( PU_PBAIB_STACK2_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR_LEN ); + +REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR ); +REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , + SH_FLD_PFIRPFIR_LEN ); + REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , @@ -62960,6 +66111,258 @@ REG64_FLD( PU_PBAIB_STACK2_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UN REG64_FLD( PU_PBAIB_STACK1_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ENABLE ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GROUP_LEN ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHIP_LEN ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); + REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ENABLE_0 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0 , 1 , SH_UNT , SH_ACS_SCOM , @@ -63115,6 +66518,25 @@ REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES , 48 , SH_UN REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_RESET_INTR_FACES_LEN ); +REG64_FLD( PU_PIB_CMD_REG_RNW , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RNW ); +REG64_FLD( PU_PIB_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR ); +REG64_FLD( PU_PIB_CMD_REG_ADR_LEN , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR_LEN ); + +REG64_FLD( PU_PIB_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_PIB_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_PIB_RESET_REG_RESET , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESET ); +REG64_FLD( PU_PIB_RESET_REG_STATE , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STATE ); +REG64_FLD( PU_PIB_RESET_REG_ABORTED_CMD , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ABORTED_CMD ); + REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_EN ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , @@ -63424,6 +66846,33 @@ REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION , 32 , SH_UN REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRG_BIT_LOCATION_LEN ); +REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NDL ); +REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NDL_LEN ); +REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_PHY , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PHY ); +REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_PHY_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PHY_LEN ); + +REG64_FLD( NV_PRI_CONFIG_NDL , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NDL ); +REG64_FLD( NV_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NDL_LEN ); +REG64_FLD( NV_PRI_CONFIG_PHY , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PHY ); +REG64_FLD( NV_PRI_CONFIG_PHY_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PHY_LEN ); + +REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_NDL , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NDL ); +REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NDL_LEN ); +REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_PHY , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PHY ); +REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_PHY_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PHY_LEN ); + REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS_LEN , 42 , SH_UNT , SH_ACS_SCOM , @@ -63434,17 +66883,21 @@ REG64_FLD( PEC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UN REG64_FLD( PEC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); -REG64_FLD( PU_PRV_MISC_RESERVED_18 , 0 , SH_UNT , SH_ACS_PPE2 , - SH_FLD_RESERVED_18 ); -REG64_FLD( PU_PRV_MISC_TPSBE_TPBR_SBE_INTR , 1 , SH_UNT , SH_ACS_PPE2 , +REG64_FLD( PU_PRV_MISC_TPSBE_TPBR_SBE_INTR , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_TPSBE_TPBR_SBE_INTR ); -REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS , 2 , SH_UNT , SH_ACS_PPE2 , +REG64_FLD( PU_PRV_MISC_CHKSW_AR012 , 1 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_CHKSW_AR012 ); +REG64_FLD( PU_PRV_MISC_RESERVED_18 , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_18 ); +REG64_FLD( PU_PRV_MISC_RESERVED_18_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_18_LEN ); +REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SBE_EXTERNAL_FIRS ); REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SBE_EXTERNAL_FIRS_LEN ); -REG64_FLD( PU_PRV_MISC_RESERVED_17 , 6 , SH_UNT , SH_ACS_PPE2 , +REG64_FLD( PU_PRV_MISC_RESERVED_17 , 8 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_17 ); -REG64_FLD( PU_PRV_MISC_RESERVED_17_LEN , 6 , SH_UNT , SH_ACS_PPE2 , +REG64_FLD( PU_PRV_MISC_RESERVED_17_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_17_LEN ); REG64_FLD( PU_PRV_MISC_TPSBE_TPIO_TPM_RESET , 12 , SH_UNT , SH_ACS_PPE2 , SH_FLD_TPSBE_TPIO_TPM_RESET ); @@ -63533,6 +66986,43 @@ REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PU_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PU_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PU_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -63690,6 +67180,29 @@ REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UN REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); +REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PU_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PU_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PU_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PU_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PU_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -63905,6 +67418,79 @@ REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIO REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -64572,6 +68158,30 @@ REG64_FLD( PU_PSU_HOST_DOORBELL_REG_2 , 2 , SH_UN SH_FLD_2 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_3 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_4 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_5 , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_5 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_6 , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_6 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_7 , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_7 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_8 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_9 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_10 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_11 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_12 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_13 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_14 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_15 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX0 ); @@ -64869,6 +68479,96 @@ REG64_FLD( PU_PSU_SBE_DOORBELL_REG_2 , 2 , SH_UN SH_FLD_2 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_3 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_4 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_5 , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_5 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_6 , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_6 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_7 , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_7 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_8 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_9 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_10 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_11 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_12 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_13 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_14 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_15 ); + +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0 , 0 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP0 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP0_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1 , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP1 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP1_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2 , 16 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP2 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP2_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3 , 24 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP3 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP3_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4 , 32 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP4 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP4_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5 , 40 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP5 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP5_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6 , 48 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP6 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP6_LEN ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7 , 56 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP7 ); +REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP7_LEN ); + +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8 , 0 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP8 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP8_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9 , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP9 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP9_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10 , 16 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP10 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP10_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11 , 24 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP11 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP11_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12 , 32 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP12 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP12_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13 , 40 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP13 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP13_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14 , 48 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP14 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP14_LEN ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15 , 56 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP15 ); +REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, + SH_FLD_MALF_ERR_FROM_GROUP15_LEN ); REG64_FLD( PU_NPU0_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC ); @@ -65050,6 +68750,9 @@ REG64_FLD( PU_NPU2_REM1_ALU_TYPE_LEN , 4 , SH_UN REG64_FLD( PU_NPU2_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_SZ ); +REG64_FLD( PU_RESET_REGISTER_CHICKEN_SWITCH , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CHICKEN_SWITCH ); + REG64_FLD( PU_RESET_REGISTER_B_CHKSW_AR012_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_AR012_0 ); @@ -65119,29 +68822,46 @@ REG64_FLD( PEC_RFIR_IN6 , 4 , SH_UN REG64_FLD( PEC_RFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6_LEN ); -REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , +REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , +REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , +REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , +REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); -REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , +REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_DISABLED ); +REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -65627,6 +69347,10 @@ REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UN SH_FLD_SKITTER0 ); REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SKITTER0_LEN ); +REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SKITTER0_DELAY_SELECT ); +REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SKITTER0_DELAY_SELECT_LEN ); REG64_FLD( PEC_SKITTER_FORCE_REG_F_READ , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_F_READ ); @@ -66457,6 +70181,90 @@ REG64_FLD( PU_NPU1_SM0_SM_STATUS_FREE , 38 , SH_UN REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_TRC_GLB_TRIG0 ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_TRC_GLB_TRIG1 ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_GLB_PULSE , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_GLB_PULSE ); +REG64_FLD( PU_SND_MODE_REG_SINGLE_OUTSTANDING_CMD , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SINGLE_OUTSTANDING_CMD ); +REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PROG_REQ_DELAY ); +REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PROG_REQ_DELAY_LEN ); +REG64_FLD( PU_SND_MODE_REG_DISABLE_ERR_CMD , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_ERR_CMD ); +REG64_FLD( PU_SND_MODE_REG_DISABLE_HTM_CMD , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_HTM_CMD ); +REG64_FLD( PU_SND_MODE_REG_DISABLE_TRACE_CMD , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_TRACE_CMD ); +REG64_FLD( PU_SND_MODE_REG_DISABLE_TOD_CMD , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_TOD_CMD ); +REG64_FLD( PU_SND_MODE_REG_DISABLE_XSCOM_CMD , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_XSCOM_CMD ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_CLR_ERR_CMD , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_CLR_ERR_CMD ); +REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_ERR_CMD , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OVERRIDE_PBINIT_ERR_CMD ); +REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_HTM_CMD , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OVERRIDE_PBINIT_HTM_CMD ); +REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TRACE_CMD , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OVERRIDE_PBINIT_TRACE_CMD ); +REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TOD_CMD , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OVERRIDE_PBINIT_TOD_CMD ); +REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_XSCOM_CMD , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD ); +REG64_FLD( PU_SND_MODE_REG_DISABLE_CHECKSTOP , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_CHECKSTOP ); +REG64_FLD( PU_SND_MODE_REG_MANUAL_SET_PB_STOP , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MANUAL_SET_PB_STOP ); +REG64_FLD( PU_SND_MODE_REG_MANUAL_CLR_PB_STOP , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MANUAL_CLR_PB_STOP ); +REG64_FLD( PU_SND_MODE_REG_PB_STOP , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_STOP ); +REG64_FLD( PU_SND_MODE_REG_MANUAL_PB_SWITCH_ABCD , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MANUAL_PB_SWITCH_ABCD ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TOD , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_RECEIVE_OWN_TOD ); +REG64_FLD( PU_SND_MODE_REG_RESET_TOD_STATE , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESET_TOD_STATE ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_AB , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_PB_SWITCH_AB ); +REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_CD , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ENABLE_PB_SWITCH_CD ); + +REG64_FLD( PU_SND_STAT_REG_ERR_CMD_OVERRUN , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERR_CMD_OVERRUN ); +REG64_FLD( PU_SND_STAT_REG_TRC_CMD_OVERRUN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRC_CMD_OVERRUN ); +REG64_FLD( PU_SND_STAT_REG_XSC_CMD_OVERRUN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_XSC_CMD_OVERRUN ); +REG64_FLD( PU_SND_STAT_REG_HTM_CMD_OVERRUN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HTM_CMD_OVERRUN ); +REG64_FLD( PU_SND_STAT_REG_TOD_CMD_OVERRUN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TOD_CMD_OVERRUN ); +REG64_FLD( PU_SND_STAT_REG_CMD_COUNT_ERR , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMD_COUNT_ERR ); +REG64_FLD( PU_SND_STAT_REG_PB_OP_HANG_ERR , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_OP_HANG_ERR ); +REG64_FLD( PU_SND_STAT_REG_INVALID_CRESP_ERR , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INVALID_CRESP_ERR ); +REG64_FLD( PU_SND_STAT_REG_RCV_TTAG_PARITY_ERR , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RCV_TTAG_PARITY_ERR ); +REG64_FLD( PU_SND_STAT_REG_RCV_PB_OP_HANG_ERR , 33 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RCV_PB_OP_HANG_ERR ); +REG64_FLD( PU_SND_STAT_REG_TOD_HANG_ERR , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TOD_HANG_ERR ); +REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE , 48 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RCV_TOD_STATE ); +REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RCV_TOD_STATE_LEN ); + REG64_FLD( PEC_SPATTN_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_NC , SH_FLD_IN ); REG64_FLD( PEC_SPATTN_IN_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM2_NC , @@ -67165,7 +70973,7 @@ REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0_LEN , 64 , SH_UN REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1 ); -REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 22 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO , 0 , SH_UNT , SH_ACS_SCOM , @@ -71442,6 +75250,21 @@ REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR , 4 , SH_UN REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SNP_TTAG_PERR ); +REG64_FLD( PU_TOD_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR ); +REG64_FLD( PU_TOD_CMD_REG_ADR_LEN , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADR_LEN ); + +REG64_FLD( PU_TOD_DATA_RCV_REG_PCB , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PCB ); +REG64_FLD( PU_TOD_DATA_RCV_REG_PCB_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_PCB_LEN ); + +REG64_FLD( PU_TOD_DATA_SND_REG_PCB , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PCB ); +REG64_FLD( PU_TOD_DATA_SND_REG_PCB_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PCB_LEN ); + REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE , 55 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMEBASE ); REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -71989,12 +75812,12 @@ REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED_LEN , 3 , SH_UN REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); -REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0_LEN , 52 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0_LEN , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); -REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1_LEN , 52 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1_LEN , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_LOGIC_HW_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , @@ -72099,6 +75922,10 @@ REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED50 , 50 , SH_UN SH_FLD_UNUSED50 ); REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED51 , 51 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNUSED51 ); +REG64_FLD( PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_0 , 52 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_INT_ERR_0 ); +REG64_FLD( PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_1 , 53 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_INT_ERR_1 ); REG64_FLD( PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_LOGIC_HW_ERROR ); @@ -72202,10 +76029,14 @@ REG64_FLD( PU_VAS_FIR_REG_UNUSED50 , 50 , SH_UN SH_FLD_UNUSED50 ); REG64_FLD( PU_VAS_FIR_REG_UNUSED51 , 51 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNUSED51 ); +REG64_FLD( PU_VAS_FIR_REG_SCOMFIR_INT_ERR_0 , 52 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_INT_ERR_0 ); +REG64_FLD( PU_VAS_FIR_REG_SCOMFIR_INT_ERR_1 , 53 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOMFIR_INT_ERR_1 ); REG64_FLD( PU_VAS_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF ); -REG64_FLD( PU_VAS_FIR_WOF_REG_WOF_LEN , 52 , SH_UNT , SH_ACS_SCOM_WCLRREG, +REG64_FLD( PU_VAS_FIR_WOF_REG_WOF_LEN , 54 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , @@ -72262,10 +76093,10 @@ REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT28 , 28 , SH_UN SH_FLD_IN_CERR_BIT28 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT29 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT29 ); -REG64_FLD( PU_VAS_INERRRPT_IN_CERR_UNUSED_BITS , 30 , SH_UNT , SH_ACS_SCOM , - SH_FLD_IN_CERR_UNUSED_BITS ); -REG64_FLD( PU_VAS_INERRRPT_IN_CERR_UNUSED_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , - SH_FLD_IN_CERR_UNUSED_BITS_LEN ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT30 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT30 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT31 , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT31 ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_4VS64 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_4VS64 ); @@ -72277,9 +76108,11 @@ REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_DISABLE_PUSH2MEM_LIMIT , 3 , SH_UN SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_QUIESCE_REQUEST , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_QUIESCE_REQUEST ); -REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_PREFETCH_DISABLE , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_PREFETCH_DISABLE ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_UNUSED_BITS ); -REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC ); @@ -73045,6 +76878,11 @@ REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UN REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); +REG64_FLD( PU_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PU_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -73070,6 +76908,11 @@ REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UN REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); +REG64_FLD( PU_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PU_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , @@ -73233,25 +77076,51 @@ REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_REG_RDATA_PERR_ERRHOLD , 36 , SH_UN SH_FLD_TB_REG_RDATA_PERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_RNG_WR_ENBL_REG_PERR_ERRHOLD , 37 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD , 39 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_UE_ERRHOLD , 38 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SSA_ECC_HI_UE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_CE_ERRHOLD , 39 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SSA_ECC_HI_CE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_SUE_ERRHOLD , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SSA_ECC_HI_SUE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_SUE_ERRHOLD , 41 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SSA_ECC_LO_SUE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_CE_ERRHOLD , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SSA_ECC_LO_CE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_UE_ERRHOLD , 43 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SSA_ECC_LO_UE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_CE_ERRHOLD , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CXACQPB_MUX_ECC_CE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_UE_ERRHOLD , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CXACQPB_MUX_ECC_UE_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_APC0_SC_RDATA_PARITY_ERRHOLD , 46 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC0_SC_RDATA_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_CREDIT_TIMEOUT_ERRHOLD , 47 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CREDIT_TIMEOUT_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TLBI_SC_RDATA_PARITY_ERRHOLD , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_SC_RDATA_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TLBI_REGS_PARITY_ERRHOLD , 49 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_REGS_PARITY_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_TIMEOUT_ERRHOLD , 50 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RCS_RECOVERY_TIMEOUT_ERRHOLD ); +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD , 51 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST0_BADIN_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD , 40 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD , 52 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST6_BADIN_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD , 41 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD , 53 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST7_BADIN_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD , 42 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD , 54 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD , 43 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD , 55 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_MISSING_SYNC_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD , 44 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD , 56 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_MISSING_STEP_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD , 45 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD , 57 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_RESIDUE_ERR_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD , 46 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD , 58 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TX_TFMR_CORRUPT_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD , 47 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD , 59 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST_CORRUPT_ERRHOLD ); -REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD , 48 , SH_UNT_CAPP , SH_ACS_SCOM , +REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD , 60 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST9_BADIN_ERRHOLD ); REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT , 0 , SH_UNT_CAPP , SH_ACS_SCOM , @@ -73259,6 +77128,151 @@ REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT , 0 , SH_UN REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMON_GROUP_SELECT_LEN ); +REG64_FLD( PU_XSCOM_BASE_REG_FBC , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC ); +REG64_FLD( PU_XSCOM_BASE_REG_FBC_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_LEN ); +REG64_FLD( PU_XSCOM_BASE_REG_FBC_RESET , 61 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_RESET ); +REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE , 62 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_DISABLE ); +REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE_LOCAL_SHORTCUT , 63 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT ); + +REG64_FLD( PU_XSCOM_DAT0_REG_DAT0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DAT0 ); +REG64_FLD( PU_XSCOM_DAT0_REG_DAT0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DAT0_LEN ); + +REG64_FLD( PU_XSCOM_DAT1_REG_DAT1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DAT1 ); +REG64_FLD( PU_XSCOM_DAT1_REG_DAT1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DAT1_LEN ); + +REG64_FLD( PU_XSCOM_ERR_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_ADDRESS ); +REG64_FLD( PU_XSCOM_ERR_REG_TSIZE , 1 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_TSIZE ); +REG64_FLD( PU_XSCOM_ERR_REG_RC_TTAG_PAR , 2 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_RC_TTAG_PAR ); +REG64_FLD( PU_XSCOM_ERR_REG_CR_TTAG_PAR , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_CR_TTAG_PAR ); +REG64_FLD( PU_XSCOM_ERR_REG_CR_ATAG_PAR , 4 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_CR_ATAG_PAR ); +REG64_FLD( PU_XSCOM_ERR_REG_RC_ADDR_PAR , 5 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_RC_ADDR_PAR ); +REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_CE , 8 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_PB_ECC_CE ); +REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_UE , 9 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_PB_ECC_UE ); +REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_SUE , 10 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_PB_ECC_SUE ); +REG64_FLD( PU_XSCOM_ERR_REG_RTAG_PARITY , 11 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_RTAG_PARITY ); +REG64_FLD( PU_XSCOM_ERR_REG_CRESP_HANG , 12 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_CRESP_HANG ); +REG64_FLD( PU_XSCOM_ERR_REG_PIB_HANG , 13 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_PIB_HANG ); +REG64_FLD( PU_XSCOM_ERR_REG_PBDATA_HANG , 14 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_PBDATA_HANG ); +REG64_FLD( PU_XSCOM_ERR_REG_ADS_HANG , 15 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_ADS_HANG ); +REG64_FLD( PU_XSCOM_ERR_REG_FSM_PERR , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_FSM_PERR ); +REG64_FLD( PU_XSCOM_ERR_REG_SPARE0 , 17 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_SPARE0 ); +REG64_FLD( PU_XSCOM_ERR_REG_SPARE1 , 18 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_SPARE1 ); +REG64_FLD( PU_XSCOM_ERR_REG_UNEXPECT_DATA , 19 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_UNEXPECT_DATA ); +REG64_FLD( PU_XSCOM_ERR_REG_ILL_CRESP , 20 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_ILL_CRESP ); + +REG64_FLD( PU_XSCOM_LOG_REG_CMD_IN_PROG , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMD_IN_PROG ); +REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMD_STATUS ); +REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMD_STATUS_LEN ); +REG64_FLD( PU_XSCOM_LOG_REG_WRITE_CMD , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WRITE_CMD ); +REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADDR_TAG ); +REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ADDR_TAG_LEN ); +REG64_FLD( PU_XSCOM_LOG_REG_THR_ID , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_THR_ID ); +REG64_FLD( PU_XSCOM_LOG_REG_THR_ID_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_THR_ID_LEN ); +REG64_FLD( PU_XSCOM_LOG_REG_PIB_COMPONENT_BUSY , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PIB_COMPONENT_BUSY ); +REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR , 33 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PIB_ADDR ); +REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR_LEN , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PIB_ADDR_LEN ); + +REG64_FLD( PU_XSCOM_MODE_REG_SPARE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE ); +REG64_FLD( PU_XSCOM_MODE_REG_SPARE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARE_LEN ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR1 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR1 ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR2 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR2 ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR3 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR3 ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR4 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR4 ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR5 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR5 ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR6 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR6 ); +REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR7 , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BAR_PIB_ON_ERROR7 ); +REG64_FLD( PU_XSCOM_MODE_REG_HANG_PIB_RESET , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HANG_PIB_RESET ); +REG64_FLD( PU_XSCOM_MODE_REG_HANG_RESET , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HANG_RESET ); +REG64_FLD( PU_XSCOM_MODE_REG_RESET_ON_PARITY , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESET_ON_PARITY ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR1 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR1 ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR2 , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR2 ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR3 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR3 ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR4 , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR4 ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR5 , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR5 ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR6 , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR6 ); +REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR7 , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FREEZE_LOG_ON_ERROR7 ); + +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DONE , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_DONE ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT , 1 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_RESULT ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_RESULT_LEN ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID , 4 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_COREID ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_COREID_LEN ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID , 10 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_THRID ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_THRID_LEN ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID , 13 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_DEST_GROUPID ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_DEST_GROUPID_LEN ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID , 17 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_DEST_CHIPID ); +REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, + SH_FLD_DEST_CHIPID_LEN ); + REG64_FLD( PEC_XSTOP1_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( PEC_XSTOP1_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , @@ -73856,6 +77870,77 @@ REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UN REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); +REG64_FLD( PEC_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DATA ); +REG64_FLD( PEC_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_XTRA_TRACE_MODE_DATA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA ); +REG64_FLD( PU_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ADDR , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ADDR ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ADDR_LEN , 37 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ADDR_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_OTHER , 54 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_FLAG_OTHER ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_PREF , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_FLAG_PREF ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_DMD , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_FLAG_DMD ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP , 57 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_FLAG_MAP ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_FENCE , 58 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_FLAG_FENCE ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_RETIRE , 59 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_RETIRE ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_IRQENA , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_IRQENA ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_SECOND , 61 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_SECOND ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_TRIGGERED , 62 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_TRIGGERED ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ENA , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ENA ); + +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_GPA , 27 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_GPA ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_BDF , 28 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_BDF ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_BDF_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_BDF_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_PASID , 44 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_PASID ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_PASID_LEN , 20 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_PASID_LEN ); + +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ADDR , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_ADDR ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ADDR_LEN , 37 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_ADDR_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_OTHER , 54 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_FLAG_OTHER ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_PREF , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_FLAG_PREF ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_DMD , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_FLAG_DMD ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_MAP , 57 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_FLAG_MAP ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_FENCE , 58 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_FLAG_FENCE ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_RETIRE , 59 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_RETIRE ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_IRQENA , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_IRQENA ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_SECOND , 61 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_SECOND ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_TRIGGERED , 62 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_TRIGGERED ); +REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ENA , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATRMISS_ENA ); + REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , |
