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| author | Abhishek Agarwal <abagarw8@in.ibm.com> | 2015-06-17 13:22:10 +0200 |
|---|---|---|
| committer | Derk Rembold <rembold@de.ibm.com> | 2015-07-08 03:55:20 -0500 |
| commit | edcf5533a70ab87a2889b46dc953dd1e95e4bea0 (patch) | |
| tree | 8ceedcea4af9f93ff95f01d2ba0b9e87005bd489 /hwp | |
| parent | cd61ac1d7850ed40028ae5db13bedfb11607c71b (diff) | |
| download | talos-sbe-edcf5533a70ab87a2889b46dc953dd1e95e4bea0.tar.gz talos-sbe-edcf5533a70ab87a2889b46dc953dd1e95e4bea0.zip | |
PERV SBE: Level 1 Procedure - p9_sbe_startclock_chiplets
Start clock procedure for Xbus, Obus, PCIe
Change-Id: Ia7ef79f162b6ec8eef398f690e8bcdf404318553
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18546
Reviewed-by: Bilicon Patil <bilpatil@in.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Derk Rembold <rembold@de.ibm.com>
Tested-by: Derk Rembold <rembold@de.ibm.com>
Diffstat (limited to 'hwp')
| -rw-r--r-- | hwp/perv/p9_sbe_startclock_chiplets.C | 29 | ||||
| -rw-r--r-- | hwp/perv/p9_sbe_startclock_chiplets.H | 36 |
2 files changed, 65 insertions, 0 deletions
diff --git a/hwp/perv/p9_sbe_startclock_chiplets.C b/hwp/perv/p9_sbe_startclock_chiplets.C new file mode 100644 index 00000000..01d65344 --- /dev/null +++ b/hwp/perv/p9_sbe_startclock_chiplets.C @@ -0,0 +1,29 @@ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.C +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_startclock_chiplets.H" + + + +fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target_chiplets) +{ + FAPI_DBG("Entering ..."); + + FAPI_DBG("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/hwp/perv/p9_sbe_startclock_chiplets.H b/hwp/perv/p9_sbe_startclock_chiplets.H new file mode 100644 index 00000000..e5749d02 --- /dev/null +++ b/hwp/perv/p9_sbe_startclock_chiplets.H @@ -0,0 +1,36 @@ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.H +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_STARTCLOCK_CHIPLETS_H_ +#define _P9_SBE_STARTCLOCK_CHIPLETS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_startclock_chiplets_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PERV> &); + +/// @brief Start Xbus, Obus, PCIe clocks +/// Start clocks on configured chiplets for all chips (master and slaves) +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV> & i_target_chiplets); +} + +#endif |
