PERV SBE: Level 2 Procedure - p9_sbe_tp_chiplet_init1

Initial steps of PIB AND PCB

Change-Id: I55969c9139af10115852988f8b4086fea312c431
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18427
Reviewed-by: Derk Rembold <rembold@de.ibm.com>
Tested-by: Derk Rembold <rembold@de.ibm.com>

2 files changed, 57 insertions, 26 deletions

diff --git a/hwp/perv/p9_sbe_tp_chiplet_init1.C b/hwp/perv/p9_sbe_tp_chiplet_init1.C
index cda80929..b8284a46 100644
--- a/hwp/perv/p9_sbe_tp_chiplet_init1.C
+++ b/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -1,28 +1,62 @@
 //------------------------------------------------------------------------------
 /// @file  p9_sbe_tp_chiplet_init1.C
 ///
-/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
+/// @brief Initial steps of PIB AND PCB
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
 //## auto_generated
 #include "p9_sbe_tp_chiplet_init1.H"
+
+#include "perv_scom_addresses.H"
+
+
 fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip)
 {
-    FAPI_DBG("p9_sbe_tp_chiplet_init1: Entering ...");
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Entering ...");
+
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<15>();  //PIB.ROOT_CTRL0.VDD2VIO_LVL_FENCE_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Release PCB Reset");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<30>();  //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Set Chiplet Enable");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    l_data64.setBit<0>();  //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Drop TP Chiplet Fence Enable");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<18>();  //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_INF("Drop Global Endpoint reset");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<31>();  //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    FAPI_INF("Switching PIB trace bus to SBE tracing");
 
-    FAPI_DBG("p9_sbe_tp_chiplet_init1: Exiting ...");
+    FAPI_DBG("Exiting ...");
 
-    return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
+    return fapi2::current_err;
 
 }
diff --git a/hwp/perv/p9_sbe_tp_chiplet_init1.H b/hwp/perv/p9_sbe_tp_chiplet_init1.H
index 74d960c6..5b0eb823 100644
--- a/hwp/perv/p9_sbe_tp_chiplet_init1.H
+++ b/hwp/perv/p9_sbe_tp_chiplet_init1.H
@@ -1,16 +1,14 @@
 //------------------------------------------------------------------------------
 /// @file  p9_sbe_tp_chiplet_init1.H
 ///
-/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
+/// @brief Initial steps of PIB AND PCB
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
@@ -24,11 +22,10 @@
 typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
 
-/// @brief DESCRIPTION  -- Drop VSS2VIO fence
-///                        -- Releases PCB reset
-///                        -- Sets PRV Chiplet Enable
-///                        -- Drops PRV Chiplet fence enable
-///                        -- Drop Global Endpoint Reset
+/// @brief Releases the Pervasive Control Bus (PCB) reset
+/// Sets TP chiplet enable
+/// Drops pervasive chiplet fences
+///
 ///
 /// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
 /// @return  FAPI2_RC_SUCCESS if success, else error code.