Adding in configurations for PNOR/LPC communication

  Adjust default LPC base address offset in image (0000030000000000)

Change-Id: I98b1ddf8fc9d515b65b20421e9e480ba4def8b9f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28570
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28571
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

2 files changed, 41 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
index 0de94fff..eb05b40e 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
@@ -41,10 +41,33 @@
 
 #include "p9_perv_scom_addresses.H"
 #include "p9_perv_scom_addresses_fld.H"
+#include "p9_misc_scom_addresses.H"
 
 fapi2::ReturnCode p9_sbe_lpc_init(const
                                   fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
+
+    const uint64_t C_OADRNB_ADDR = 0x00400000F0000C90ull;
+    // bits 0:31 are the starting byte address of flash locations directly accessible by the second interface. Must be a multiple of the size of the address rangei
+    // I have 0xF0000000 since we expect the PNOR address window to be from 0xFXXXXXXX (FW ops) and LPC IO ops from 0xDXXXXXXX
+    // This makes the "direct accessible address range" to 0xC000000  to  0xFFFFFFF because of he 64MB size
+    const uint64_t C_OADRNB_DATA = 0x0C00000000000000ull;
+    const uint64_t C_OADRNS_ADDR = 0x00400000F0000C94ull;
+    // bits 27:31 are the OPB window size this should be a multiple of the ECC granule if ECC is enbled and the large erase block size
+    // Currently I have this set to be 64 MB
+    const uint64_t C_OADRNS_DATA = 0x000000000000000Full;
+    const uint64_t C_ADRCBF_ADDR = 0x00400000F0000C80ull;
+    // bits 0:31 are the starting byte address of flash locations accessble by the first interface. Must be a multiple of the size of the address range accessible by the first interface.
+    // I have 0xF0000000 since we expect the PNOR address window to be from 0xFXXXXXXX (FW ops) and LPC IO ops from 0xDXXXXXXX
+    // This makes the "direct accessible address range" to 0xC000000  to  0xFFFFFFF because of the 64MB size
+    const uint64_t C_ADRCBF_DATA = 0x0C00000000000000ull;
+    const uint64_t C_ADRCMF_ADDR = 0x00400000F0000C84ull;
+    // bits 27:31 are the size of the first interfaces flash allocation
+    // Currently I have this set to be 64 MB
+    const uint64_t C_ADRCMF_DATA = 0x000000000000000Full;
+    const uint64_t C_CONF_ADDR = 0x00400000F0000C10ull;
+    // Set the direct access cache disable bit (bit 30)
+    const uint64_t C_CONF_DATA = 0x0000000200000000ull;
     fapi2::buffer<uint64_t> l_data64;
     FAPI_DBG("p9_sbe_lpc_init: Entering ...");
 
@@ -65,6 +88,23 @@ fapi2::ReturnCode p9_sbe_lpc_init(const
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_OR, l_data64));
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_CLEAR, l_data64));
 
+    //Sets the register OADRNB (0x90) of the nore flash master (sets a base address for direct access)
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, C_OADRNB_ADDR), "Error setting the OADRNB address");
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, C_OADRNB_DATA), "Error setting the OADRNB data");
+    //Sets the register OADRNS (0x94) of the flash master (window size setting)
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, C_OADRNS_ADDR), "Error setting the OADRNS address");
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, C_OADRNS_DATA), "Error setting the OADRNS data");
+    //Sets the ADRCBF (0x80) of the nor flash master (NOR Address offset)
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, C_ADRCBF_ADDR), "Error setting the ADRCBF address");
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, C_ADRCBF_DATA), "Error setting the ADRCBF data");
+    //Sets the register ADRCMF (0x84) of the nor flash master (size setting)
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, C_ADRCMF_ADDR), "Error setting the ADRCMF address");
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, C_ADRCMF_DATA), "Error setting the ADRCMF data");
+    //Sets the register CONF(0x10) of the nor flash master (direct access)
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, C_CONF_ADDR), "Error setting the CONF address");
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, C_CONF_DATA), "Error setting the CONF data");
+
+
     FAPI_DBG("p9_sbe_lpc_init: Exiting ...");
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 2d68f08e..23c49c20 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -526,7 +526,7 @@ attribute tank
 
   <entry>
         <name>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</name>
-        <value>0x000003FB00000000</value>
+        <value>0x0000030000000000</value>
   </entry>