p9_sbe_lpc_init: Fix timeout setup

Factor LPC register access out into its own utility function, with
added timeout for the ADU access and proper FFDC if the ADU times out.

CQ: SW418354
cmvc-prereq: 1048349
Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54641
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

5 files changed, 142 insertions, 40 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_lpc_utils.H b/src/import/chips/p9/procedures/hwp/perv/p9_lpc_utils.H
index 999dcb4f..ae0d7791 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_lpc_utils.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_lpc_utils.H
@@ -22,3 +22,91 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+/// @file  p9_lpc_utils.H
+///
+/// @brief Helper functions for indirect reads/writes to the LPC register space
+/// @author Joachim Fenkes <fenkes@de.ibm.com>
+#ifndef P9_LPC_UTILS_H_
+#define P9_LPC_UTILS_H_
+
+const uint32_t LPC_CMD_TIMEOUT_DELAY_NS = 1000000;
+const uint32_t LPC_CMD_TIMEOUT_COUNT = 4;
+
+static fapi2::ReturnCode lpc_rw(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
+    uint32_t i_addr, bool i_read_notwrite, fapi2::buffer<uint32_t>& io_data)
+{
+    const int l_bit_offset = (i_addr & 4) << 3;
+    fapi2::buffer<uint64_t> l_command;
+    l_command.writeBit<PU_LPC_CMD_REG_RNW>(i_read_notwrite)
+    .insertFromRight<PU_LPC_CMD_REG_SIZE, PU_LPC_CMD_REG_SIZE_LEN>(0x4)
+    .insertFromRight<PU_LPC_CMD_REG_ADR, PU_LPC_CMD_REG_ADR_LEN>(i_addr);
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_command), "Error writing LPC command register");
+
+    if (!i_read_notwrite)
+    {
+        fapi2::buffer<uint64_t> l_data;
+        l_data.insert(io_data, l_bit_offset, 32);
+        FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data), "Error writing LPC data");
+    }
+
+    {
+        fapi2::buffer<uint64_t> l_status;
+        int timeout = LPC_CMD_TIMEOUT_COUNT;
+
+        while (timeout--)
+        {
+            FAPI_TRY(fapi2::getScom(i_target_chip, PU_LPC_STATUS_REG, l_status), "Error reading LPC status");
+
+            if (l_status.getBit<PU_LPC_STATUS_REG_DONE>())
+            {
+                break;
+            }
+
+            fapi2::delay(LPC_CMD_TIMEOUT_DELAY_NS, LPC_CMD_TIMEOUT_DELAY_NS);
+        }
+
+        if (LPC_UTILS_TIMEOUT_FFDC)
+        {
+            FAPI_ASSERT(l_status.getBit<PU_LPC_STATUS_REG_DONE>(), fapi2::LPC_ACCESS_TIMEOUT()
+                        .set_TARGET_CHIP(i_target_chip)
+                        .set_COUNT(LPC_CMD_TIMEOUT_COUNT)
+                        .set_COMMAND(l_command)
+                        .set_DATA(io_data)
+                        .set_STATUS(l_status),
+                        "LPC access timed out");
+        }
+        else if (!l_status.getBit<PU_LPC_STATUS_REG_DONE>())
+        {
+            return fapi2::RC_LPC_ACCESS_TIMEOUT;
+        }
+    }
+
+    if (i_read_notwrite)
+    {
+        fapi2::buffer<uint64_t> l_data;
+        FAPI_TRY(fapi2::getScom(i_target_chip, PU_LPC_DATA_REG, l_data), "Error reading LPC data");
+        l_data.extract(io_data, l_bit_offset, 32);
+    }
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+static inline fapi2::ReturnCode lpc_read(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
+    uint32_t i_addr, fapi2::buffer<uint32_t>& o_data)
+{
+    return lpc_rw(i_target_chip, i_addr, true, o_data);
+}
+
+static inline fapi2::ReturnCode lpc_write(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
+    uint32_t i_addr, fapi2::buffer<uint32_t> i_data)
+{
+    return lpc_rw(i_target_chip, i_addr, false, i_data);
+}
+
+#endif /* P9_LPC_UTILS_H_ */
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
index fbaa9eec..919b9e1d 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,7 +27,7 @@
 ///
 /// @brief procedure to initialize LPC to enable communictation to PNOR
 //------------------------------------------------------------------------------
-// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Owner        : Joachim Fenkes <fenkes@de.ibm.com>
 // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
 // *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
@@ -44,6 +44,9 @@
 #include "p9_misc_scom_addresses.H"
 #include "p9_misc_scom_addresses_fld.H"
 
+const bool LPC_UTILS_TIMEOUT_FFDC = true;
+#include "p9_lpc_utils.H"
+
 static fapi2::ReturnCode reset_lpc_master(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
@@ -79,32 +82,20 @@ fapi_try_exit:
 static fapi2::ReturnCode reset_lpc_bus_via_master(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
-    fapi2::buffer<uint64_t> l_data64;
-    fapi2::buffer<uint64_t> l_lpcm_opb_master_control_register_data(0);
-
-    //Write to the LPCM OPB Master Control Register (address x'C001 0008')
-    l_lpcm_opb_master_control_register_data.setBit<PU_LPC_CMD_REG_RNW>().insertFromRight<PU_LPC_CMD_REG_ADR, PU_LPC_CMD_REG_ADR_LEN>
-    (LPCM_OPB_MASTER_CONTROL_REG).insertFromRight<PU_LPC_CMD_REG_SIZE, PU_LPC_CMD_REG_SIZE_LEN>(0x4);
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_lpcm_opb_master_control_register_data),
-             "Erro writing the LPC_CMD_REG to get the current reset value");
-    FAPI_TRY(fapi2::getScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error getting the reset value");
+    fapi2::buffer<uint32_t> l_control;
 
     //Set register bit 23 lpc_lreset_oe to b'1' and set lpc_lreset_out to b'0' to drive a low reset
-    l_data64.setBit<LPC_LRESET_OE>().clearBit<LPC_LRESET_OUT>();
-    l_lpcm_opb_master_control_register_data.clearBit<PU_LPC_CMD_REG_RNW>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_lpcm_opb_master_control_register_data),
-             "Error writing to the LPC_CMD_REG to set lpc_lreset_oe");
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error setting lpc_lreset_oe");
+    FAPI_TRY(lpc_read(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_control),
+             "Error reading the OPB master control register");
+    l_control.setBit<LPC_LRESET_OE>().clearBit<LPC_LRESET_OUT>();
+    FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_control), "Error asserting LPC reset");
 
     //Give the bus some time to reset
     fapi2::delay(LPC_LRESET_DELAY_NS, LPC_LRESET_DELAY_NS);
 
     //Clear bit 23 lpc_lreset_oe to stop driving the low reset
-    l_data64.clearBit<LPC_LRESET_OE>();
-    l_lpcm_opb_master_control_register_data.clearBit<PU_LPC_CMD_REG_RNW>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_lpcm_opb_master_control_register_data),
-             "Error writing to the LPC_CMD_REG to clear lpc_lreset_oe");
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error clearing lpc_lreset_oe");
+    l_control.clearBit<LPC_LRESET_OE>();
+    FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_control), "Error deasserting LPC reset");
 
     return fapi2::FAPI2_RC_SUCCESS;
 
@@ -140,15 +131,10 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
-
 fapi2::ReturnCode p9_sbe_lpc_init(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
-    const uint64_t C_LPC_TIMEOUT_ADDR = 0x00400000C001202C;
-    const uint64_t C_LPC_TIMEOUT_DATA = 0x00000000FE000000;
-    const uint64_t C_OPB_TIMEOUT_ADDR = 0x00400000C0010040;
-    const uint64_t C_OPB_TIMEOUT_DATA = 0x00000000FFFFFFFE;
-    fapi2::buffer<uint64_t> l_data64;
+    fapi2::buffer<uint32_t> l_data32;
     uint8_t l_use_gpio = 0;
     uint8_t l_is_fsp = 0;
     FAPI_DBG("p9_sbe_lpc_init: Entering ...");
@@ -180,16 +166,15 @@ fapi2::ReturnCode p9_sbe_lpc_init(
     //--- STEP 3: Program settings in LPC Master and FPGA
     //------------------------------------------------------------------------------------------
 
-    //Set up the LPC timeout settings
-    l_data64 = C_LPC_TIMEOUT_ADDR;
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_data64), "Error tring to set LPC timeout address");
-    l_data64 = C_LPC_TIMEOUT_DATA;
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error trying to set LPC timeout data");
-    //Set up the OPB timeout settings
-    l_data64 = C_OPB_TIMEOUT_ADDR;
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_CMD_REG, l_data64), "Error trying to set OPB timeout address");
-    l_data64 = C_OPB_TIMEOUT_DATA;
-    FAPI_TRY(fapi2::putScom(i_target_chip, PU_LPC_DATA_REG, l_data64), "Error trying to set OPB timeout data");
+    // Set up the LPC timeout settings - OPB master first, in case the LPC HC hangs
+    FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_TIMEOUT_REG, LPCM_OPB_MASTER_TIMEOUT_VALUE),
+             "Error trying to set up the OPB master timeout");
+    FAPI_TRY(lpc_read(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_data32), "Error reading OPB master control register");
+    l_data32.setBit<LPCM_OPB_MASTER_CONTROL_REG_TIMEOUT_ENABLE>();
+    FAPI_TRY(lpc_write(i_target_chip, LPCM_OPB_MASTER_CONTROL_REG, l_data32), "Error enabling OPB master timeout");
+
+    FAPI_TRY(lpc_write(i_target_chip, LPCM_LPC_MASTER_TIMEOUT_REG, LPCM_LPC_MASTER_TIMEOUT_VALUE),
+             "Error trying to set up the LPC host controller timeout");
 
     FAPI_DBG("p9_sbe_lpc_init: Exiting ...");
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
index d2d35d27..75852847 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -54,7 +54,12 @@ extern "C"
     const uint64_t LPC_LRESET_OE = 23;
     const uint64_t LPC_LRESET_OUT = 22;
     const uint32_t LPC_LRESET_DELAY_NS = 200000;
-    const uint64_t LPCM_OPB_MASTER_CONTROL_REG = 0xC0010008;
+    const uint32_t LPCM_OPB_MASTER_CONTROL_REG = 0xC0010008;
+    const uint32_t LPCM_OPB_MASTER_CONTROL_REG_TIMEOUT_ENABLE = 2;
+    const uint32_t LPCM_OPB_MASTER_TIMEOUT_REG = 0xC0010040;
+    const uint32_t LPCM_OPB_MASTER_TIMEOUT_VALUE = 0x01312D00;  // 50ms at 1600MHz Nest / 400MHz OPB
+    const uint32_t LPCM_LPC_MASTER_TIMEOUT_REG = 0xC001202C;
+    const uint32_t LPCM_LPC_MASTER_TIMEOUT_VALUE = 0xFE000000;
     const uint32_t CPLT_CONF1_TC_LP_RESET = 12;
     fapi2::ReturnCode p9_sbe_lpc_init(const
                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml
index b87e0407..1668a29e 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml
@@ -23,4 +23,26 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <hwpErrors>
+  <sbeTarget>TARGET_CHIP</sbeTarget>
+  <hwpError>
+    <sbeError/>
+    <rc>RC_LPC_ACCESS_TIMEOUT</rc>
+    <description>An attempt to read/write data in the LPC address space via the Alter/Display unit timed out.</description>
+    <ffdc>COUNT</ffdc>
+    <ffdc>COMMAND</ffdc>
+    <ffdc>DATA</ffdc>
+    <ffdc>STATUS</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <target>TARGET_CHIP</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <priority>MEDIUM</priority>
+    </callout>
+    <deconfigure>
+      <target>TARGET_CHIP</target>
+    </deconfigure>
+  </hwpError>
 </hwpErrors>
diff --git a/src/test/framework/etc/workarounds.presimsetup b/src/test/framework/etc/workarounds.presimsetup
index de849ccf..ceff4166 100755
--- a/src/test/framework/etc/workarounds.presimsetup
+++ b/src/test/framework/etc/workarounds.presimsetup
@@ -6,7 +6,7 @@
 #
 # OpenPOWER sbe Project
 #
-# Contributors Listed Below - COPYRIGHT 2015,2017
+# Contributors Listed Below - COPYRIGHT 2015,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -38,3 +38,5 @@
 #cp /esw/san5/cmolsen/sb/hw/tests/refs/ppe-ci/p9c.hw_image_magic_20170817.bin $SANDBOXBASE/src/engd/href/p9c.temp_hw_ref_image.bin
 mkdir -p $SANDBOXBASE/src/simu/data/cec-chip
 cp /esw/user/nfs/prasrang/powermgmt.act $SANDBOXBASE/src/simu/data/cec-chip/
+sbex -t 1048349
+