adjust NV mesh control setup application

  p9_sbe_attr_setup
    set ATTR_NDL_MESHCTRL_SETUP from inverse of mailbox data
  p9_sbe_startclock_chiplets
    write CPLT_CTRL1 instead of NET_CTRL1
    apply setup here instead of p9_sbe_chiplet_reset

Change-Id: Ic2cd3ef9c544278f10acfde149f42e4acc800044
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36055
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36164
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

3 files changed, 57 insertions, 66 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
index beb24596..41941df0 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -180,6 +180,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
     {
         if ( l_read_scratch8.getBit<1>() )
         {
+            uint8_t l_ndl_meshctrl_setup = 0x0;
 
             FAPI_DBG("Reading Scratch_reg2");
             //Getting SCRATCH_REGISTER_2 register value
@@ -191,10 +192,10 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
 
-            l_read_scratch_reg.extractToRight<16, 4>(l_read_1);
-
+            l_read_scratch_reg.extractToRight<16, 4>(l_ndl_meshctrl_setup);
+            l_ndl_meshctrl_setup = (~l_ndl_meshctrl_setup) & 0x0F;
             FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP");
-            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_read_1));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_ndl_meshctrl_setup));
         }
         else
         {
@@ -208,6 +209,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
 
             l_read_scratch_reg.insertFromRight< ATTR_I2C_BUS_DIV_REF_STARTBIT, ATTR_I2C_BUS_DIV_REF_LENGTH >(l_read_4);
             l_read_scratch_reg.insertFromRight< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(l_read_1);
+            l_read_scratch_reg.flipBit< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >();
 
             FAPI_DBG("Setting up value of Scratch_reg2");
             //Setting SCRATCH_REGISTER_2 register value
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index 5965b556..fac39832 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -120,8 +120,6 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0(
 static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
 
-static fapi2::ReturnCode p9_sbe_chiplet_reset_meshctrl_setup(
-    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, bool value);
 
 fapi2::ReturnCode p9_sbe_chiplet_reset(const
                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
@@ -259,32 +257,6 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
             }
         }
 
-        FAPI_DBG("Meshctrl setup");
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip,
-                               l_read_attr));
-
-        for (auto& targ : l_perv_func_WO_Core_Cache)
-        {
-            uint32_t l_chipletID = targ.getChipletNumber();
-
-            if (l_chipletID == 9)
-            {
-                FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<4>()));
-            }
-            else if (l_chipletID == 10)
-            {
-                FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<5>()));
-            }
-            else if (l_chipletID == 11)
-            {
-                FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<6>()));
-            }
-            else if (l_chipletID == 12)
-            {
-                FAPI_TRY(p9_sbe_chiplet_reset_meshctrl_setup(targ, l_read_attr.getBit<7>()));
-            }
-        }
-
         FAPI_DBG("Sector buffer strength and pulse mode setup");
 
         // MC XBUS OBUS PCI
@@ -485,41 +457,6 @@ fapi_try_exit:
 
 }
 
-/// @brief meshctrl setup
-///
-/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
-/// @param[in]     value              0 or 1 to be written into perv_net_ctrl1 reg
-/// @return  FAPI2_RC_SUCCESS if success, else error code.
-static fapi2::ReturnCode p9_sbe_chiplet_reset_meshctrl_setup(
-    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, bool value)
-{
-    fapi2::buffer<uint64_t> l_data;
-    FAPI_INF("p9_sbe_chiplet_reset_meshctrl_setup: Entering ...");
-
-    if ( value )
-    {
-        l_data.flush<0>();
-        l_data.setBit<21>();
-
-        FAPI_DBG("Meshctrl setup");
-        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WOR, l_data));
-    }
-    else
-    {
-        l_data.flush<1>();
-        l_data.clearBit<21>();
-
-        FAPI_DBG("Meshctrl setup");
-        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data));
-
-    }
-
-    FAPI_INF("p9_sbe_chiplet_reset_meshctrl_setup: Exiting ...");
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
 /// @brief Setting up hang pulse counter for all parital good chiplet except for Tp
 ///
 /// @param[in]     i_target_cplt   Reference to TARGET_TYPE_PERV target
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C
index 934dc234..62520cc1 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C
@@ -60,6 +60,10 @@ enum P9_SBE_STARTCLOCK_CHIPLETS_Private_Constants
 static fapi2::ReturnCode p9_sbe_startclock_chiplets_fence_drop(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
 
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_meshctrl_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool value);
+
 static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
     const uint8_t i_attr);
@@ -72,6 +76,7 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const
 {
     fapi2::buffer<uint64_t> l_pg_vector;
     fapi2::buffer<uint64_t> l_regions;
+    fapi2::buffer<uint8_t> l_ndl_meshctrl_setup;
     fapi2::buffer<uint8_t> l_attr_obus_ratio;
     fapi2::buffer<uint16_t> l_attr_pg;
     FAPI_INF("p9_sbe_startclock_chiplets: Entering ...");
@@ -81,6 +86,9 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const
                                  fapi2::TARGET_FILTER_XBUS | fapi2::TARGET_FILTER_ALL_PCI),
                          fapi2::TARGET_STATE_FUNCTIONAL);
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip,
+                           l_ndl_meshctrl_setup));
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip,
                            l_attr_obus_ratio));
 
@@ -91,6 +99,23 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const
 
         if(l_chipletID >= 9 && l_chipletID <= 12)
         {
+            if (l_chipletID == 9)
+            {
+                FAPI_TRY(p9_sbe_startclock_chiplets_meshctrl_setup(obus, l_ndl_meshctrl_setup.getBit<4>()));
+            }
+            else if (l_chipletID == 10)
+            {
+                FAPI_TRY(p9_sbe_startclock_chiplets_meshctrl_setup(obus, l_ndl_meshctrl_setup.getBit<5>()));
+            }
+            else if (l_chipletID == 11)
+            {
+                FAPI_TRY(p9_sbe_startclock_chiplets_meshctrl_setup(obus, l_ndl_meshctrl_setup.getBit<6>()));
+            }
+            else if (l_chipletID == 12)
+            {
+                FAPI_TRY(p9_sbe_startclock_chiplets_meshctrl_setup(obus, l_ndl_meshctrl_setup.getBit<7>()));
+            }
+
             FAPI_TRY(p9_sbe_startclock_chiplets_set_ob_ratio(obus,
                      l_attr_obus_ratio));
         }
@@ -174,6 +199,33 @@ fapi_try_exit:
 
 }
 
+/// @brief meshctrl setup
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     value              0 or 1 to be written into perv_cplt_ctrl1 reg
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_meshctrl_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, bool value)
+{
+    fapi2::buffer<uint64_t> l_data = 0;
+    l_data.setBit<21>();
+    FAPI_INF("p9_sbe_startclock_chiplets_meshctrl_setup: Entering ...");
+
+    if ( value )
+    {
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_OR, l_data));
+    }
+    else
+    {
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data));
+    }
+
+    FAPI_INF("p9_sbe_startclock_chiplets_meshctrl_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 /// @brief set obus ratio
 ///
 /// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target