p9_sbe_attr_setup

Support for BMC machines

Change-Id: I91148e7e83a79900e5e6a2fdde8bdb378bbb26de
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32110
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32115
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 272 insertions, 13 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
index 8fc95de1..4904dcc8 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -45,6 +45,36 @@ enum P9_SETUP_SBE_CONFIG_scratch4
 {
     // Scratch4 reg bit definitions
     ATTR_OBUS_RATIO_VALUE_BIT          = 21,
+    ATTR_EQ_GARD_STARTBIT = 0,
+    ATTR_EQ_GARD_LENGTH = 6,
+    ATTR_EC_GARD_STARTBIT = 8,
+    ATTR_EC_GARD_LENGTH = 24,
+    ATTR_I2C_BUS_DIV_REF_STARTBIT = 0,
+    ATTR_I2C_BUS_DIV_REF_LENGTH = 16,
+    ATTR_BOOT_FLAGS_STARTBIT = 0,
+    ATTR_BOOT_FLAGS_LENGTH = 32,
+    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
+    ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3,
+    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29,
+    ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3,
+    ATTR_CC_IPL_BIT = 0,
+    ATTR_INIT_ALL_CORES_BIT = 1,
+    ATTR_RISK_LEVEL_BIT = 2,
+    ATTR_DISABLE_HBBL_VECTORS_BIT = 3,
+    ATTR_MC_SYNC_MODE_BIT = 4,
+    ATTR_PLL_MUX_STARTBIT = 12,
+    ATTR_PLL_MUX_LENGTH = 20,
+
+    // Scratch4 reg bit definitions
+    ATTR_BOOT_FREQ_MULT_STARTBIT       = 0,
+    ATTR_BOOT_FREQ_MULT_LENGTH         = 16,
+    ATTR_NEST_PLL_BUCKET_STARTBIT      = 24,
+    ATTR_NEST_PLL_BUCKET_LENGTH        = 8,
+    ATTR_CP_FILTER_BYPASS_BIT          = 16,
+    ATTR_SS_FILTER_BYPASS_BIT          = 17,
+    ATTR_IO_FILTER_BYPASS_BIT          = 18,
+    ATTR_DPLL_BYPASS_BIT               = 19,
+    ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT   = 20,
 };
 
 fapi2::ReturnCode p9_sbe_attr_setup(const
@@ -57,6 +87,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
     fapi2::buffer<uint8_t> l_read_3 = 0;
     fapi2::buffer<uint16_t> l_read_4 = 0;
     fapi2::buffer<uint32_t> l_read_5 = 0;
+    fapi2::buffer<uint32_t> l_read_6 = 0;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     fapi2::buffer<uint64_t> l_data64;
     bool sbe_slave_chip = false;
@@ -112,7 +143,31 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5));
 
             l_read_1 = 0;
-            l_read_4 = 0;
+            l_read_5 = 0;
+        }
+        else
+        {
+            FAPI_DBG("Read Scratch_reg1");
+            //Getting SCRATCH_REGISTER_1 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM,
+                                    l_read_scratch_reg));
+
+            FAPI_DBG("Reading ATTR_EQ_GARD, ATTR_EC_GARD");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5));
+
+            l_read_1.extractToRight< 0, ATTR_EQ_GARD_LENGTH >(l_read_2);
+            l_read_5.extractToRight< 0, ATTR_EC_GARD_LENGTH >(l_read_6);
+
+            l_read_scratch_reg.insertFromRight< ATTR_EQ_GARD_STARTBIT, ATTR_EQ_GARD_LENGTH >(l_read_2);
+            l_read_scratch_reg.insertFromRight< ATTR_EC_GARD_STARTBIT, ATTR_EC_GARD_LENGTH >(l_read_6);
+
+            FAPI_DBG("Setting up value of Scratch_reg1");
+            //Setting SCRATCH_REGISTER_1 register value
+
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM,
+                                    l_read_scratch_reg));
+            l_read_scratch8.setBit<0>();
         }
     }
     //read_scratch2_reg
@@ -129,6 +184,24 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
         }
+        else
+        {
+            FAPI_DBG("Reading Scratch_reg2");
+            //Getting SCRATCH_REGISTER_2 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM,
+                                    l_read_scratch_reg));
+
+            FAPI_DBG("Reading ATTR_I2C_BUS_DIV_REF");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
+
+            l_read_scratch_reg.insertFromRight< ATTR_I2C_BUS_DIV_REF_STARTBIT, ATTR_I2C_BUS_DIV_REF_LENGTH >(l_read_4);
+
+            FAPI_DBG("Setting up value of Scratch_reg2");
+            //Setting SCRATCH_REGISTER_2 register value
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM,
+                                    l_read_scratch_reg));
+            l_read_scratch8.setBit<1>();
+        }
     }
 
     //read_scratch3_reg
@@ -147,18 +220,39 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_DBG("Setting up ATTR_IS_MPIPL");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl));
         }
+        else
+        {
+            FAPI_DBG("Reading Scratch_reg3");
+            //Getting SCRATCH_REGISTER_3 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_3_SCOM,
+                                    l_read_scratch_reg));
+
+            FAPI_DBG("Reading the BOOT_FLAGS");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FLAGS, FAPI_SYSTEM, l_read_5));
+
+            l_read_scratch_reg.insertFromRight< ATTR_BOOT_FLAGS_STARTBIT, ATTR_BOOT_FLAGS_LENGTH >(l_read_5);
+
+            FAPI_DBG("Setting up value of Scratch_reg3");
+            //Setting SCRATCH_REGISTER_3 register value
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_3_SCOM,
+                                    l_read_scratch_reg));
+
+            l_read_scratch8.setBit<2>();
+        }
     }
 
     //read_scratch4_reg
     {
+
+        uint8_t l_cp_filter_bypass = 0;
+        uint8_t l_ss_filter_bypass = 0;
+        uint8_t l_io_filter_bypass = 0;
+        uint8_t l_dpll_bypass = 0;
+        uint8_t l_nest_mem_x_o_pci_bypass = 0;
+        uint8_t l_attr_obus_ratio = 0;
+
         if ( l_read_scratch8.getBit<3>() )
         {
-            uint8_t l_cp_filter_bypass = 0;
-            uint8_t l_ss_filter_bypass = 0;
-            uint8_t l_io_filter_bypass = 0;
-            uint8_t l_dpll_bypass = 0;
-            uint8_t l_nest_mem_x_o_pci_bypass = 0;
-            uint8_t l_attr_obus_ratio = 0;
 
             FAPI_DBG("Reading Scratch_Reg4");
             //Getting SCRATCH_REGISTER_4 register value
@@ -190,17 +284,63 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             l_read_1 = 0;
             l_read_4 = 0;
         }
+        else
+        {
+            FAPI_DBG("Reading Scratch_reg4");
+            //Getting SCRATCH_REGISTER_4 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM,
+                                    l_read_scratch_reg));
+
+            FAPI_DBG("Reading PLL bypass attributes");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass),
+                     "Error from FAPI_ATTR_GET (ATTR_CP_FILTER_BYPASS");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, l_ss_filter_bypass),
+                     "Error from FAPI_ATTR_GET (ATTR_SS_FILTER_BYPASS");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass),
+                     "Error from FAPI_ATTR_GET (ATTR_IO_FILTER_BYPASS");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass),
+                     "Error from FAPI_ATTR_GET (ATTR_DPLL_BYPASS");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass),
+                     "Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS");
+
+            FAPI_DBG("Reading ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
+
+            l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
+            l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);
+
+            l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1);
+            l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1);
+            l_read_scratch_reg.writeBit<ATTR_IO_FILTER_BYPASS_BIT>(l_io_filter_bypass & 0x1);
+            l_read_scratch_reg.writeBit<ATTR_DPLL_BYPASS_BIT>(l_dpll_bypass & 0x1);
+            l_read_scratch_reg.writeBit<ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT>(l_nest_mem_x_o_pci_bypass & 0x1);
+
+            // Setting OBUS ratio
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip,
+                                   l_attr_obus_ratio));
+            l_read_scratch_reg.writeBit<ATTR_OBUS_RATIO_VALUE_BIT>(l_attr_obus_ratio & 0x1);
+
+            FAPI_DBG("Setting up value of Scratch_reg4");
+            //Setting SCRATCH_REGISTER_4 register value
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM,
+                                    l_read_scratch_reg));
+
+            l_read_scratch8.setBit<3>();
+        }
     }
     //read_scratch5_reg
     {
+
+        uint8_t l_system_ipl_phase = 0;
+        uint8_t l_force_all_cores = 0;
+        uint8_t l_risk_level = 0;
+        uint8_t l_disable_hbbl_vectors = 0;
+        uint32_t l_pll_mux = 0;
+        uint8_t l_mc_sync_mode = 0;
+
         if ( l_read_scratch8.getBit<4>() )
         {
-            uint8_t l_system_ipl_phase = 0;
-            uint8_t l_force_all_cores = 0;
-            uint8_t l_risk_level = 0;
-            uint8_t l_disable_hbbl_vectors = 0;
-            uint32_t l_pll_mux = 0;
-            uint8_t l_mc_sync_mode = 0;
 
             FAPI_DBG("Reading Scratch_reg5");
             //Getting SCRATCH_REGISTER_5 register value
@@ -247,6 +387,83 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
         }
+        else
+        {
+
+            FAPI_DBG("Reading Scratch_reg5");
+            //Getting SCRATCH_REGISTER_5 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM,
+                                    l_read_scratch_reg));
+
+            FAPI_DBG("Reading control flag attributes");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
+
+            // set cache contained flag
+            if (l_system_ipl_phase == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
+            {
+                l_read_scratch_reg.setBit<ATTR_CC_IPL_BIT>();
+            }
+            else
+            {
+                l_read_scratch_reg.clearBit<ATTR_CC_IPL_BIT>();
+            }
+
+            // set all cores flag
+            if (l_force_all_cores)
+            {
+                l_read_scratch_reg.setBit<ATTR_INIT_ALL_CORES_BIT>();
+            }
+            else
+            {
+                l_read_scratch_reg.clearBit<ATTR_INIT_ALL_CORES_BIT>();
+            }
+
+            // set risk level flag
+            if (l_risk_level == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
+            {
+                l_read_scratch_reg.setBit<ATTR_RISK_LEVEL_BIT>();
+            }
+            else
+            {
+                l_read_scratch_reg.clearBit<ATTR_RISK_LEVEL_BIT>();
+            }
+
+            // set disable of HBBL exception vector flag
+            if (l_disable_hbbl_vectors == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)
+            {
+                l_read_scratch_reg.setBit<ATTR_DISABLE_HBBL_VECTORS_BIT>();
+            }
+            else
+            {
+                l_read_scratch_reg.clearBit<ATTR_DISABLE_HBBL_VECTORS_BIT>();
+            }
+
+            // set MC sync mode
+            if (l_mc_sync_mode)
+            {
+                l_read_scratch_reg.setBit<ATTR_MC_SYNC_MODE_BIT>();
+            }
+            else
+            {
+                l_read_scratch_reg.clearBit<ATTR_MC_SYNC_MODE_BIT>();
+            }
+
+            FAPI_DBG("Reading PLL mux attributes");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
+            // set PLL MUX bits
+            l_read_scratch_reg.insert<ATTR_PLL_MUX_STARTBIT, ATTR_PLL_MUX_LENGTH, 0>(l_pll_mux);
+
+            FAPI_DBG("Setting up value of Scratch_reg5");
+            //Setting SCRATCH_REGISTER_5 register value
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM,
+                                    l_read_scratch_reg));
+
+            l_read_scratch8.setBit<4>();
+        }
     }
     //read_scratch6_reg
     {
@@ -283,8 +500,50 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
                                    l_read_3));
 
         }
+        else
+        {
+            FAPI_DBG("Reading Scratch_reg6");
+            //Getting SCRATCH_REGISTER_6 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM,
+                                    l_read_scratch_reg));
+
+            FAPI_DBG("Reading attribute for Hostboot slave bit");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip,
+                                   l_read_1));
+
+            if ( l_read_1 )
+            {
+                l_read_scratch_reg.clearBit<24>();
+            }
+            else
+            {
+                l_read_scratch_reg.setBit<24>();
+            }
+
+            FAPI_DBG("Reading ATTR_PROC_FABRIC_GROUP and CHIP_ID");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip,
+                                   l_read_1));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip,
+                                   l_read_2));
+
+            l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_FABRIC_GROUP_ID_LENGTH >(l_read_1);
+            l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_FABRIC_CHIP_ID_LENGTH >(l_read_2);
+
+            FAPI_DBG("Setting up value of Scratch_reg6");
+            //Setting SCRATCH_REGISTER_6 register value
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM,
+                                    l_read_scratch_reg));
+
+            l_read_scratch8.setBit<5>();
+        }
     }
 
+    FAPI_DBG("Setting Scratch8 for validity of Scratch register");
+    //Setting SCRATCH_REGISTER_8 register value
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_8_SCOM,
+                            l_read_scratch8));
+
+
     FAPI_INF("p9_sbe_attr_setup: Exiting ...");
 
 fapi_try_exit: