Level 2 Procedure - p9_sbe_tp_arrayinit

Change-Id: I00835e33507b10c010c1da11ffd1d2ed3de8a58e
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20800
Tested-by: Jenkins Server
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21846
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>

3 files changed, 109 insertions, 19 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
index b6e6f758..c61db071 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
@@ -20,27 +20,88 @@
 /// @file  p9_sbe_tp_arrayinit.C
 ///
 /// @brief SBE PRV Array Init Procedure
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
 //## auto_generated
 #include "p9_sbe_tp_arrayinit.H"
+
+#include "p9_misc_scom_addresses.H"
+#include "p9_perv_scom_addresses.H"
+#include "p9_perv_sbe_cmn.H"
+
+
+enum P9_SBE_TP_ARRAYINIT_Private_Constants
+{
+    REGIONS_EXCEPT_PIB_NET_PLL = 0x4FE,
+    SCAN_TYPES = 0xDCF,
+    LOOP_COUNTER = 0x0000000000042FFF,
+    START_ABIST_MATCH_VALUE = 0x0000000F00000000,
+    SELECT_SRAM = 0x1,
+    SELECT_EDRAM = 0x0
+};
+
 fapi2::ReturnCode p9_sbe_tp_arrayinit(const
                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
-    FAPI_DBG("p9_sbe_tp_arrayinit: Entering ...");
+    bool l_sram_abist_check = false;
+    auto l_perv_functional_vector =
+        i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+        (fapi2::TARGET_STATE_FUNCTIONAL);
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Entering ...");
+
+    FAPI_INF("Exclude PIBMEM from TP array init");
+    //Setting PIBMEM_REPAIR_REGISTER_0 register value
+    //PIB.PIBMEM_REPAIR_REGISTER_0 = 0x0000000000000001
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0,
+                            0x0000000000000001));
+
+    // Step 1: Array Init for PRV Cplt
+    // ===============================
+
+    // Get the TPChiplet target
+    for (auto it : l_perv_functional_vector)
+    {
+        uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, it, l_attr_chip_unit_pos));
+
+        if (l_attr_chip_unit_pos == 0x01)/* TPChiplet */
+        {
+            FAPI_INF("Call ARRAY INIT Module for Pervasive Chiplet");
+            FAPI_TRY(p9_perv_sbe_cmn_array_init_module(it,
+                     REGIONS_EXCEPT_PIB_NET_PLL, LOOP_COUNTER, SELECT_SRAM, SELECT_EDRAM,
+                     START_ABIST_MATCH_VALUE));
+
+            FAPI_INF("Check SRAM Abist Done");
+            //Getting CPLT_STAT0 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_CPLT_STAT0, l_data64));
+            //l_sram_abist_check = PERV.CPLT_STAT0.SRAM_ABIST_DONE_DC
+            l_sram_abist_check = l_data64.getBit<0>();
+            FAPI_ASSERT(l_sram_abist_check , fapi2::SRAM_ABIST_DONE_BIT_ERR()
+                        .set_READ_ABIST_DONE(l_sram_abist_check),
+                        "ERROR:ABIST_DONE_BIT_NOT_SET");
+            // Step 2: Scan0 for PRV Cplt
+            FAPI_INF("Call SCAN0 Module for Pervasive Chiplet");
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(it, REGIONS_EXCEPT_PIB_NET_PLL,
+                                                  SCAN_TYPES));
+            FAPI_INF("Add PIBMEM back to TP array init");
+            //Setting PIBMEM_REPAIR_REGISTER_0 register value
+            //PIB.PIBMEM_REPAIR_REGISTER_0 = 0x0
+            FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, 0));
+        }
+    }
 
-    FAPI_DBG("p9_sbe_tp_arrayinit: Exiting ...");
+    FAPI_DBG("Exiting ...");
 
-    return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
+    return fapi2::current_err;
 
 }
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H
index 96d80a52..2944dffa 100644
--- a/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H
@@ -20,15 +20,13 @@
 /// @file  p9_sbe_tp_arrayinit.H
 ///
 /// @brief SBE PRV Array Init Procedure
-// *!
-// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
-// *! BACKUP NAME :                   Email:
 //------------------------------------------------------------------------------
-// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
-// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
-// *HWP Team        : Perv
-// *HWP Level       : 1
-// *HWP Consumed by : SBE
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
 //------------------------------------------------------------------------------
 
 
diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml
new file mode 100644
index 00000000..065df788
--- /dev/null
+++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml
@@ -0,0 +1,31 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_tp_arrayinit_errors.xml. -->
+<!-- Halt codes for p9_sbe_tp_arrayinit -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_SRAM_ABIST_DONE_BIT_ERR</rc>
+    <description>SRAM abist done bit is not set</description>
+    <ffdc>READ_ABIST_DONE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>