p9_sbe_setup_boot_freq Level 2 - Setup boot frequency

Change-Id: Ifc543396f35f000dd82a175eeed1811f84514e48
Original-Change-Id: I2b123188915e54f159ff374a6399402d55a541e7
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21483
Tested-by: Jenkins Server
Reviewed-by: Bilicon Patil <bilpatil@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22883
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 162 insertions, 0 deletions

diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C
new file mode 100644
index 00000000..620d9c48
--- /dev/null
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C
@@ -0,0 +1,127 @@
+
+///
+/// @file  p9_sbe_setup_boot_freq.C
+/// @brief Setup Boot Frequency
+///
+// *HW Owner    : Sudheendra K Srivathsa <sudheendraks@in.ibm.com>
+// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+// *Team        : PM
+// *Consumed by : SBE
+// *Level       : 2
+///
+/// @verbatim
+///
+/// Procedure Summary:
+///   - Read frequency ATTR and write to the Quad PPM DPLL Freq Ctrl register
+///
+/// @endverbatim
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include "p9_sbe_setup_boot_freq.H"
+#include "p9_quad_scom_addresses.H"
+
+enum P9_SBE_SETUP_BOOT_FREQ_CONSTANTS
+{
+
+// Default configuration settings
+
+// Default boot_frequency in terms of a multiplier of the refclk frequency/8
+// This is value used if the mailbox value is zero
+//
+// Value implemented is 3.0GHz, @todo, RTC 140053 - Should it be 2 GHz for P9 ?
+//
+// 3000MHz / 16.667MHz = ~180 => 0xB4
+//
+// Note:  the above is aligned, as a value, to 0:10, written as bits 17:27 of PPM DPLL freq ctrl register
+// Bits 0:7 are DPLL.MULT_INTG(0:7), and Bits 8:10 are DPLL.MULT_FRAC(0:2)
+//
+DEFAULT_BOOT_FREQUENCY_MULTIPLIER =  0x00B4,
+
+};
+
+//-----------------------------------------------------------------------------
+// Procedure
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+BootFreqInitAttributes(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                  uint16_t &i_boot_frequency_multiplier)
+{
+
+    i_boot_frequency_multiplier = DEFAULT_BOOT_FREQUENCY_MULTIPLIER;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FMULT,i_target, i_boot_frequency_multiplier));
+
+    // If attribute values are zero, use the default values (hardcoded)
+
+    // check BOOT FREQ MULT
+    if (i_boot_frequency_multiplier == 0)
+    {
+        // Default voltage if mailbox value is not set
+
+        // @todo, L3 phase Eventually, this should replaced with an error point
+        // to indicate that the mailbox -> attributes haven't been setup
+
+        i_boot_frequency_multiplier  = DEFAULT_BOOT_FREQUENCY_MULTIPLIER;
+        FAPI_INF("DPLL boot frequency not set in attributes.  Setting to default of %d (%x)",
+               i_boot_frequency_multiplier, i_boot_frequency_multiplier);
+    }
+    else
+    {
+        FAPI_INF("DPLL boot frequency = %d (%x)",
+               i_boot_frequency_multiplier, i_boot_frequency_multiplier);
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+} // BootFreqInitAttributes
+
+
+fapi2::ReturnCode
+setDPLLFrequency(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                 const uint16_t i_DpllBootFreqMult
+               )
+{
+    fapi2::buffer<uint64_t> l_data;
+
+
+    auto l_present_eqs = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL);
+
+    l_data.insertFromRight<17,11>(i_DpllBootFreqMult);
+
+    for(auto l_tlst: l_present_eqs)
+    {
+       FAPI_TRY(fapi2::putScom(l_tlst,  EQ_QPPM_DPLL_FREQ, l_data));
+       //@todo,Determine ff_slew rate value RTC 140053
+       FAPI_TRY(fapi2::putScom(l_tlst,  EQ_QPPM_DPLL_CTRL,  0));
+
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+// Hardware procedure
+fapi2::ReturnCode
+p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    // Boot frequency variable
+    uint16_t l_boot_frequency_multiplier;
+
+    // Read Boot freq mult attribute
+    FAPI_TRY(BootFreqInitAttributes(i_target, l_boot_frequency_multiplier));
+
+    // Set Boot Frequency
+    
+    FAPI_TRY(setDPLLFrequency(i_target,
+                  l_boot_frequency_multiplier),
+            "Setting Boot Frequency");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+} // Procedure
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H
new file mode 100644
index 00000000..8f18431b
--- /dev/null
+++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H
@@ -0,0 +1,35 @@
+
+///
+/// @file  p9_sbe_setup_boot_freq.H
+/// @brief Setup Boot Frequency
+///
+/// *HW Owner    : Sudheendra K Srivathsa <sudheendraks@in.ibm.com>
+/// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+/// *Team        : PM
+/// *Consumed by : SBE
+/// *Level       : 2
+///
+
+#ifndef __P9_SBE_SETUP_BOOT_FREQ_H__
+#define __P9_SBE_SETUP_BOOT_FREQ_H__
+
+/// @typedef p9_sbe_setup_boot_freq_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_sbe_setup_boot_freq_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
+
+extern "C"
+{
+
+/// @brief Read an attribute containing the boot frequency and set that
+///        into each configured EQ chiplet.
+/// @param [in] i_target TARGET_TYPE_PROC_CHIP
+/// @attr
+/// @attritem ATTR_BOOT_FMULT - 11 bit frequency multiplier of refclk
+/// @return FAPI2_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+} // extern C
+
+#endif  // __P9_SBE_SETUP_BOOT_FREQ_H__