PLL configuration updates -- permit e2e bypass execution

p9_sbe_attr_setup
p9_setup_sbe_config
  transmit PLL bypass controls through MBOX Scratch 4 bits 16:20
  transmit PLL mux controls through MBOX Scratch 5 bits 12:31

p9_common_poweronoff
  increase polling delays to account for refclock speed

p9_hcd_cache_dpll_setup
  permit DPLL execution in bypass, based on ATTR_DPLL_BYPASS

p9_sbe_npll_setup
  permit NEST PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_mem_pll_setup
  permit MEM PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_chiplet_pll_setup
  permit X/O/PCI PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_tp_switch_gears
  skip adjustment of i2c bit divisor, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_attributes.xml
hb_temp_defaults.xml
  add defaults to enable platform CI

Change-Id: Icba6aee79d90b0280ba4818afd92c344c52f52ef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28611
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28613
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

8 files changed, 313 insertions, 183 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
index 744f0ae9..684161c2 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
@@ -1,7 +1,7 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C $ */
+/* $Source: src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C $ */
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
@@ -95,8 +95,13 @@ p9_hcd_cache_dpll_setup(
 {
     FAPI_INF(">>p9_hcd_cache_dpll_setup");
     fapi2::buffer<uint64_t>                  l_data64;
+    uint8_t                                  l_dpll_bypass;
     uint32_t                                 l_timeout;
 
+    auto l_parent_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DPLL_BYPASS, l_parent_chip, l_dpll_bypass),
+             "Error from FAPI_ATTR_GET (ATTR_DPLL_BYPASS)");
+
     //----------------------------
     // Prepare to start DPLL clock
     //----------------------------
@@ -108,8 +113,11 @@ p9_hcd_cache_dpll_setup(
     FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2)));
 
-    FAPI_DBG("Drop DPLL test mode and reset via NET_CTRL0[3,4]");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0)));
+    if (l_dpll_bypass == 0)
+    {
+        FAPI_DBG("Drop DPLL test mode and reset via NET_CTRL0[3,4]");
+        FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0)));
+    }
 
     FAPI_DBG("Drop DPLL clock region fence via NET_CTRL1[14]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(14)));
@@ -151,41 +159,48 @@ p9_hcd_cache_dpll_setup(
 
     // This is necessary to ensure that the DPLL is in Mode 1(ff_bypass = 1)
     // If not, the lock times will go from ~30us to 3-5ms
-    FAPI_DBG("Poll for DPLL to lock via QPPM_DPLL_STAT");
-    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
-                CACHE_DPLL_LOCK_TIMEOUT_IN_MS;
-
-    do
+    if (l_dpll_bypass == 0)
     {
-        FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64));
-        ///@todo disable poll for DPLL lock until model setting in place
-        break;
+        FAPI_DBG("Poll for DPLL to lock via QPPM_DPLL_STAT");
+        l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                    CACHE_DPLL_LOCK_TIMEOUT_IN_MS;
+
+        do
+        {
+            FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64));
+            ///@todo disable poll for DPLL lock until model setting in place
+            break;
+        }
+        while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0));
+
+        FAPI_ASSERT((l_timeout != 0),
+                    fapi2::PMPROC_DPLL_LOCK_TIMEOUT()
+                    .set_EQQPPMDPLLSTAT(l_data64),
+                    "DPLL Lock Timeout");
+        FAPI_DBG("DPLL is locked now");
+
+        FAPI_DBG("Drop DPLL bypass via NET_CTRL0[5]");
+        FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(5)));
+
+
+        FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
+        FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2)));
     }
-    while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0));
-
-    FAPI_ASSERT((l_timeout != 0),
-                fapi2::PMPROC_DPLL_LOCK_TIMEOUT()
-                .set_EQQPPMDPLLSTAT(l_data64),
-                "DPLL Lock Timeout");
-    FAPI_DBG("DPLL is locked now");
 
     //--------------------------
     // Cleaning up
     //--------------------------
 
-    FAPI_DBG("Drop DPLL bypass via NET_CTRL0[5]");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(5)));
-
-    FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
-    FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2)));
-
     FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2)));
 
-    FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]");
-    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
-    l_data64.insertFromRight<47, 5>(0x3);
-    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    if (l_dpll_bypass == 0)
+    {
+        FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]");
+        FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
+        l_data64.insertFromRight<47, 5>(0x3);
+        FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    }
 
     FAPI_DBG("Drop ANEP clock region fence via CPLT_CTRL1[10]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(10)));
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C
index 52916b7f..2ec24c73 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C
@@ -1,7 +1,7 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C $   */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C $ */
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
@@ -74,7 +74,7 @@ const uint64_t PPM_PFSNS[2] =   { C_PPM_PFSNS,
                                 };
 
 enum { FSM_IDLE_POLLING_HW_NS_DELAY = 10000,
-       FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 80000,
+       FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 320000,
        PFET_STATE_LENGTH = 2,
        VXX_PG_SEL_LEN = 4
      };
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
index ee741b8c..b6c8217d 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -1,7 +1,7 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C $     */
+/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C $ */
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
@@ -125,18 +125,54 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
         }
     }
 
+    //read_scratch3_reg
+    {
+        uint8_t l_is_mpipl = 0;
+
+        if ( l_read_scratch8.getBit<2>() )
+        {
+            FAPI_DBG("Reading Scratch_reg3");
+            //Getting SCRATCH_REGISTER_3 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_3_SCOM,
+                                    l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_
+
+            l_read_scratch_reg.extractToRight<2, 1>(l_is_mpipl);
+
+            FAPI_DBG("Setting up ATTR_IS_MPIPL");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl));
+        }
+    }
+
     //read_scratch4_reg
     {
         if ( l_read_scratch8.getBit<3>() )
         {
+            uint8_t l_cp_filter_bypass = 0;
+            uint8_t l_ss_filter_bypass = 0;
+            uint8_t l_io_filter_bypass = 0;
+            uint8_t l_dpll_bypass = 0;
+            uint8_t l_nest_mem_x_o_pci_bypass = 0;
+
             FAPI_DBG("Reading Scratch_Reg4");
             //Getting SCRATCH_REGISTER_4 register value
             FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM,
                                     l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4
 
             l_read_scratch_reg.extractToRight<0, 16>(l_read_4);
+            l_read_scratch_reg.extractToRight<16, 1>(l_cp_filter_bypass);
+            l_read_scratch_reg.extractToRight<17, 1>(l_ss_filter_bypass);
+            l_read_scratch_reg.extractToRight<18, 1>(l_io_filter_bypass);
+            l_read_scratch_reg.extractToRight<19, 1>(l_dpll_bypass);
+            l_read_scratch_reg.extractToRight<20, 1>(l_nest_mem_x_o_pci_bypass);
             l_read_scratch_reg.extractToRight<24, 8>(l_read_1);
 
+            FAPI_DBG("Setting up PLL bypass attributes");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, l_ss_filter_bypass));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass));
+
             FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
@@ -149,6 +185,13 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
     {
         if ( l_read_scratch8.getBit<4>() )
         {
+            uint8_t l_system_ipl_phase = 0;
+            uint8_t l_force_all_cores = 0;
+            uint8_t l_risk_level = 0;
+            uint8_t l_disable_hbbl_vectors = 0;
+            uint32_t l_pll_mux = 0;
+            uint8_t l_mc_sync_mode = 0;
+
             FAPI_DBG("Reading Scratch_reg5");
             //Getting SCRATCH_REGISTER_5 register value
             FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM,
@@ -156,47 +199,43 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
 
             if (l_read_scratch_reg.getBit<0>())
             {
-                l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED;
+                l_system_ipl_phase = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED;
             }
             else
             {
-                l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL;
+                l_system_ipl_phase = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL;
             }
 
-            l_read_2.writeBit<7>(l_read_scratch_reg.getBit<1>());
+            l_read_scratch_reg.extract<1, 1, 7>(l_force_all_cores);
 
             if (l_read_scratch_reg.getBit<2>())
             {
-                l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE;
+                l_risk_level = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE;
             }
             else
             {
-                l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE;
+                l_risk_level = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE;
             }
 
-            FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
-            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1));
-            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM,
-                                   l_read_2));
-            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_3));
-
-            l_read_1 = 0;
-            l_read_2  = 0;
-            l_read_3 = 0;
-
             if (l_read_scratch_reg.getBit<3>())
             {
-                l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE;
+                l_disable_hbbl_vectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE;
             }
             else
             {
-                l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE;
+                l_disable_hbbl_vectors = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE;
             }
 
-            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM,
-                                   l_read_1));
+            l_read_scratch_reg.extract<4, 1, 7>(l_mc_sync_mode);
+            l_read_scratch_reg.extract<12, 20, 0>(l_pll_mux);
 
-            l_read_1 = 0;
+            FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
         }
     }
     //read_scratch6_reg
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
index a152c465..e5da6efa 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
@@ -1,7 +1,7 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C $ */
+/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C $ */
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
@@ -64,7 +64,8 @@ static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
 
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
-    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool i_bypass);
 
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
@@ -85,6 +86,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     uint8_t l_read_attr = 0;
+    uint8_t l_bypass = 0;
     FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ...");
 
     for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
@@ -94,6 +96,9 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
         FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_bypass(l_chplt_trgt));
     }
 
+    FAPI_DBG("Reading bypass attribute");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_bypass));
+
     FAPI_DBG("Reading ATTR_mc_sync_mode");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
 
@@ -106,36 +111,39 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
             FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
         }
 
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
-                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
-        {
-            FAPI_DBG("release pll test enable for except pcie");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
-        }
-
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
-                                               fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
-              fapi2::TARGET_STATE_FUNCTIONAL))
-        {
-            FAPI_DBG("Release PLL reset");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
-        }
-
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        if (l_bypass == 0)
         {
-            FAPI_DBG("Check pll lock for PCIe");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
-        }
-
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
-                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
-        {
-            FAPI_DBG("Check pll lock for Xb,Ob");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                                   fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("release pll test enable for except pcie");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+            }
+
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                                   fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+                  fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("Release PLL reset");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
+            }
+
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("Check pll lock for PCIe");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
+            }
+
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                                   fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("Check pll lock for Xb,Ob");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+            }
         }
 
         for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
@@ -143,7 +151,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
                                                fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
               fapi2::TARGET_STATE_FUNCTIONAL))
         {
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt, l_bypass));
         }
     }
     else
@@ -162,13 +170,41 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
             FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
         }
 
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
-              fapi2::TARGET_STATE_FUNCTIONAL))
+        if (l_bypass == 0)
         {
-            FAPI_DBG("release pll test enable for except pcie");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                                   fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
+                  fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("release pll test enable for except pcie");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+            }
+
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                                   fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                                   fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("Release PLL reset");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
+            }
+
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("Check pll lock for pcie");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
+            }
+
+            for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+                 (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                                   fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
+                  fapi2::TARGET_STATE_FUNCTIONAL))
+            {
+                FAPI_DBG("check pll lock for Mc,Xb,Ob");
+                FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+            }
         }
 
         for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
@@ -176,32 +212,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
                                                fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
                                                fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
         {
-            FAPI_DBG("Release PLL reset");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
-        }
-
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
-        {
-            FAPI_DBG("Check pll lock for pcie");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
-        }
-
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
-              fapi2::TARGET_STATE_FUNCTIONAL))
-        {
-            FAPI_DBG("check pll lock for Mc,Xb,Ob");
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
-        }
-
-        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
-             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
-                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
-                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
-        {
-            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt, l_bypass));
         }
     }
 
@@ -269,25 +280,30 @@ fapi_try_exit:
 /// @brief Setup PLL for XBus, OBus, PCIe, (MC) chiplets
 ///
 /// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_bypass           Leave PLL in bypass?
 /// @return  FAPI2_RC_SUCCESS if success, else error code.
 static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
-    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool i_bypass)
 {
     fapi2::buffer<uint64_t> l_data64;
     FAPI_INF("p9_sbe_chiplet_pll_setup_function: Entering ...");
 
-    FAPI_DBG("Drop PLL Bypass");
-    //Setting NET_CTRL0 register value
-    l_data64.flush<1>();
-    l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>();  //NET_CTRL0.PLL_BYPASS = 0
-    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
-
-    FAPI_DBG("Set scan ratio to 4:1 as soon as PLL is out of bypass mode");
-    //Setting OPCG_ALIGN register value
-    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
-    l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
-    (0x3);  //OPCG_ALIGN.SCAN_RATIO = 0x3
-    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
+    if (i_bypass == 0)
+    {
+        FAPI_DBG("Drop PLL Bypass");
+        //Setting NET_CTRL0 register value
+        l_data64.flush<1>();
+        l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>();  //NET_CTRL0.PLL_BYPASS = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+
+        FAPI_DBG("Set scan ratio to 4:1 as soon as PLL is out of bypass mode");
+        //Setting OPCG_ALIGN register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
+        l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
+        (0x3);  //OPCG_ALIGN.SCAN_RATIO = 0x3
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
+    }
 
     FAPI_DBG("Reset PCB Slave error register");
     //Setting ERROR_REG register value
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
index 331fa528..6a25a858 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
@@ -1,7 +1,7 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C $     */
+/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C $ */
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
@@ -56,6 +56,7 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
 {
     fapi2::buffer<uint64_t> l_read_reg;
     uint8_t l_read_attr = 0;
+    uint8_t l_nest_bypass = 0;
     fapi2::buffer<uint64_t> l_data64_root_ctrl8;
     fapi2::buffer<uint64_t> l_data64_perv_ctrl0;
     FAPI_INF("p9_sbe_npll_setup: Entering ...");
@@ -186,14 +187,21 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
                                 l_data64_root_ctrl8));
     }
 
-    FAPI_DBG("Drop PLL test enable for Nest PLL");
-    //Setting PERV_CTRL0 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
-                            l_data64_perv_ctrl0));
-    //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0
-    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
-                            l_data64_perv_ctrl0));
+    FAPI_DBG("Reading ATTR_NEST_MEM_X_O_PCI_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_bypass),
+             "Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS)");
+
+    if ( l_nest_bypass == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for Nest PLL");
+        //Setting PERV_CTRL0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64_perv_ctrl0));
+        //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0
+        l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64_perv_ctrl0));
+    }
 
     FAPI_DBG("Reading ATTR_MC_SYNC_MODE");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
@@ -208,31 +216,34 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
                                 l_data64_root_ctrl8));
     }
 
-    FAPI_DBG("Release Nest PLL  reset");
-    //Setting PERV_CTRL0 register value
-    //PIB.PERV_CTRL0.TP_PLLRST_DC = 0
-    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
-                            l_data64_perv_ctrl0));
-
-    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
-
-    FAPI_DBG("check  NEST PLL lock");
-    //Getting PLL_LOCK_REG register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
-                            l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
-
-    FAPI_ASSERT(l_read_reg.getBit<3>(),
-                fapi2::NEST_PLL_ERR()
-                .set_NEST_PLL_READ(l_read_reg),
-                "ERROR:NEST PLL LOCK NOT SET");
-
-    FAPI_DBG("Release PLL bypass2");
-    //Setting PERV_CTRL0 register value
-    //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
-    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
-                            l_data64_perv_ctrl0));
+    if ( l_nest_bypass == 0x0 )
+    {
+        FAPI_DBG("Release Nest PLL  reset");
+        //Setting PERV_CTRL0 register value
+        //PIB.PERV_CTRL0.TP_PLLRST_DC = 0
+        l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64_perv_ctrl0));
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+        FAPI_DBG("check  NEST PLL lock");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+        FAPI_ASSERT(l_read_reg.getBit<3>(),
+                    fapi2::NEST_PLL_ERR()
+                    .set_NEST_PLL_READ(l_read_reg),
+                    "ERROR:NEST PLL LOCK NOT SET");
+
+        FAPI_DBG("Release PLL bypass2");
+        //Setting PERV_CTRL0 register value
+        //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
+        l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64_perv_ctrl0));
+    }
 
     FAPI_INF("p9_sbe_npll_setup: Exiting ...");
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C
index 828c855c..5c1159d5 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C
@@ -1,7 +1,7 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C $ */
+/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C $ */
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
@@ -58,25 +58,25 @@ enum P9_SBE_TP_SWITCH_GEARS_Private_Constants
 fapi2::ReturnCode p9_sbe_tp_switch_gears(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
-    fapi2::buffer<uint64_t> l_data64;
     FAPI_INF("p9_sbe_tp_switch_gears: Entering ...");
 
 #ifdef __PPE__
+    uint8_t l_nest_bypass = 0;
+    // - if we've just switched from refclock->PLL, we need to adjust the
+    // i2c bit rate divisor to account for the new frequency (plus
+    // check our ability to access the seeprom with this setting)
+    // - if no frequency change has occurred (nest PLL in bypass),
+    // skip all of these steps as the current divisor in place is appropriate
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_bypass));
+
+    if (l_nest_bypass == 0)
+    {
+        FAPI_TRY(p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(i_target_chip));
+        FAPI_TRY(p9_sbe_gear_switcher_i2c_stop_sequence(i_target_chip));
+        FAPI_DBG("Checking Magic number");
+        FAPI_TRY(p9_sbe_tp_switch_gears_check_magicnumber(i_target_chip));
+    }
 
-    FAPI_DBG("switch from refclock to PLL speed");
-    //Setting PERV_CTRL0 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
-    //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
-    l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
-
-    FAPI_TRY(p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
-                 i_target_chip));
-
-    FAPI_TRY(p9_sbe_gear_switcher_i2c_stop_sequence(i_target_chip));
-
-    FAPI_DBG("Checking Magic number");
-    FAPI_TRY(p9_sbe_tp_switch_gears_check_magicnumber(i_target_chip));
 fapi_try_exit:
 #endif
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 4972e342..2d68f08e 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -1,7 +1,7 @@
 <!-- IBM_PROLOG_BEGIN_TAG                                                   -->
 <!-- This is an automatically generated prolog.                             -->
 <!--                                                                        -->
-<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml $ -->
+<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml $ -->
 <!--                                                                        -->
 <!-- OpenPOWER sbe Project                                                  -->
 <!--                                                                        -->
@@ -464,6 +464,14 @@
            <value>0x1</value>
   </entry>
   <entry>
+           <name>ATTR_DPLL_BYPASS</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_NEST_MEM_X_O_PCI_BYPASS</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
            <name>ATTR_VDM_ENABLE</name>
            <value>0x0</value>
   </entry>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index 22a063c5..6000c9d6 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -1,7 +1,7 @@
 <!-- IBM_PROLOG_BEGIN_TAG                                                   -->
 <!-- This is an automatically generated prolog.                             -->
 <!--                                                                        -->
-<!-- $Source: import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml $ -->
+<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml $ -->
 <!--                                                                        -->
 <!-- OpenPOWER sbe Project                                                  -->
 <!--                                                                        -->
@@ -34,6 +34,10 @@
   <description>setup clock mux settings</description>
   <valueType>uint32</valueType>
   <platInit/>
+  <!-- TODO: Story 155081
+       Not supposed to be writeable, PPE needs to resolve this issue in
+       p9_sbe_attr_setup.C -->
+  <writeable/>
 </attribute>
 
 <attribute>
@@ -629,28 +633,65 @@
 <attribute>
     <id>ATTR_CP_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>To skip the locking sequence and check for lock of CP PLL</description>
+    <description>To skip the locking sequence and check for lock of CP filter PLL</description>
     <valueType>uint8</valueType>
     <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
 </attribute>
 
 <attribute>
     <id>ATTR_SS_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>To skip the locking sequence and check for lock of SS PLL</description>
+    <description>To skip the locking sequence and check for lock of SS filter PLL</description>
     <valueType>uint8</valueType>
     <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
 </attribute>
 
 <attribute>
     <id>ATTR_IO_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>To skip the locking sequence and check for lock of IO PLL</description>
+    <description>To skip the locking sequence and check for lock of IO filter PLL</description>
     <valueType>uint8</valueType>
     <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
 </attribute>
 
 <attribute>
+    <id>ATTR_DPLL_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Skip locking sequence and check for lock of DPLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_NEST_MEM_X_O_PCI_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
+</attribute>
+
+
+<attribute>
   <id>ATTR_TARGET_HAS_POWER</id>
   <targetType>TARGET_TYPE_PERV</targetType>
   <description>Functional Target has power</description>