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author | Abhishek Agarwal <abagarw8@in.ibm.com> | 2015-08-25 08:36:24 +0200 |
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committer | Amit J. Tendolkar <amit.tendolkar@in.ibm.com> | 2015-11-06 04:14:59 -0600 |
commit | 61734d5f04a19e5e1b9824964daf2f4e0f838b70 (patch) | |
tree | b6f7434f99212081cd9de356f68d3dc57ba6039f | |
parent | 96c85cbecf45a8da52b2e3200572b4562d98cb1e (diff) | |
download | talos-sbe-61734d5f04a19e5e1b9824964daf2f4e0f838b70.tar.gz talos-sbe-61734d5f04a19e5e1b9824964daf2f4e0f838b70.zip |
PERV SBE: Level 2 Procedure - p9_sbe_chiplet_pll_initf
Scan initializing PLL config bits for
XBus, OBus, PCIe, MC Chiplets
Change-Id: I3264fed3bd12d3fa120de5ca77e473e9be93a5c0
Original-Change-Id: I53dcb37413ba3c4bf53abf5d866ac014310333ae
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20068
Tested-by: Jenkins Server
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21837
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>
-rw-r--r-- | import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C | 101 | ||||
-rw-r--r-- | import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H | 21 |
2 files changed, 102 insertions, 20 deletions
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C index a0217a8c..b581c9c6 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C @@ -19,31 +19,112 @@ //------------------------------------------------------------------------------ /// @file p9_sbe_chiplet_pll_initf.C /// -/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : srinivas naga Email: srinivan@in.ibm.com +/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> -// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ //## auto_generated #include "p9_sbe_chiplet_pll_initf.H" +#include "p9_perv_sbe_cmn.H" +enum P9_SBE_CHIPLET_PLL_INITF_Private_Constants +{ + REGIONS_PLL_ONLY = 0x001, + SCAN_TYPES_GPTR = 0x200, + SCAN_TYPES_BNDY_FUNC = 0x808 +}; + fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { + uint8_t l_read_attr = 0; + auto l_perv_functional_vector = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_STATE_FUNCTIONAL); FAPI_DBG("Entering ..."); + FAPI_INF("Switch MC meshs to Nest mesh"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + if ( l_read_attr ) + { + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */) || + (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A + || l_attr_chip_unit_pos == 0x0B + || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || + (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E + || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || + (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) + { + continue; + } + + FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, + SCAN_TYPES_GPTR)); + + FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, + SCAN_TYPES_BNDY_FUNC)); + + //TODO:Load Ring Module : Scan initialize PLL BNDY chain + } + } + else + { + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x07 + || l_attr_chip_unit_pos == 0x08/* McChiplet */) || + (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */) || + (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A + || l_attr_chip_unit_pos == 0x0B + || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || + (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E + || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || + (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) + { + continue; + } + + FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, + SCAN_TYPES_GPTR)); + + FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, + SCAN_TYPES_BNDY_FUNC)); + + //TODO:Load Ring Module : Scan initialize PLL BNDY chain + } + } + FAPI_DBG("Exiting ..."); - return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H index b0d9cb7d..623df6a1 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H @@ -19,16 +19,14 @@ //------------------------------------------------------------------------------ /// @file p9_sbe_chiplet_pll_initf.H /// -/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls -// *! -// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com -// *! BACKUP NAME : srinivas naga Email: srinivan@in.ibm.com +/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets //------------------------------------------------------------------------------ -// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> -// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> -// *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ @@ -42,7 +40,10 @@ typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); -/// @brief load the pll config settings for L2 AND L3 plls +/// @brief If TRUE then skip MC chiplet +/// run scan0 module (scan region = PLL, scan_types = GPTR) +/// run scan0 module (scan region = PLL, scan_types = BNDY/FUNC) +/// Scan initialize PLL BNDY chain (chiplet =[CPLT], scan ring = PLL, scan type = BNDY) /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target /// @return FAPI2_RC_SUCCESS if success, else error code. |