p9_sbe_common: Level 3

Change-Id: I55fac6a40f6e53c8afd859ea262b44b36a20b33e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38784
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38789
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

3 files changed, 96 insertions, 264 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
index e3a6c601..deded1ea 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
@@ -31,7 +31,7 @@
 // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
 // *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
-// *HWP Level           : 2
+// *HWP Level           : 3
 // *HWP Consumed by     : SBE
 //------------------------------------------------------------------------------
 
@@ -266,9 +266,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
             l_sl_clkregion_status &= l_regions;
 
             FAPI_ASSERT(l_sl_clkregion_status == l_regions,
-                        fapi2::NEST_SL_ERR()
+                        fapi2::THOLD_ERR()
                         .set_TARGET_CHIPLET(i_target)
-                        .set_READ_CLK_SL(l_sl_clock_status),
+                        .set_CLOCK_CMD(i_clock_cmd)
+                        .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL)
+                        .set_REGIONS(i_regions)
+                        .set_READ_CLK(l_sl_clock_status),
                         "Clock running for sl type not matching with expected values");
         }
 
@@ -280,9 +283,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
             l_sl_clkregion_status &= l_regions;
 
             FAPI_ASSERT(l_sl_clkregion_status == l_regions,
-                        fapi2::NEST_SL_ERR()
+                        fapi2::THOLD_ERR()
                         .set_TARGET_CHIPLET(i_target)
-                        .set_READ_CLK_SL(l_sl_clock_status),
+                        .set_CLOCK_CMD(i_clock_cmd)
+                        .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL)
+                        .set_REGIONS(i_regions)
+                        .set_READ_CLK(l_sl_clock_status),
                         "Clock running for sl type not matching with expected values");
         }
     }
@@ -304,9 +310,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
             l_nsl_clkregion_status &= l_regions;
 
             FAPI_ASSERT(l_nsl_clkregion_status == l_regions,
-                        fapi2::NEST_NSL_ERR()
+                        fapi2::THOLD_ERR()
                         .set_TARGET_CHIPLET(i_target)
-                        .set_READ_CLK_NSL(l_nsl_clock_status),
+                        .set_CLOCK_CMD(i_clock_cmd)
+                        .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL)
+                        .set_REGIONS(i_regions)
+                        .set_READ_CLK(l_nsl_clock_status),
                         "Clock running for nsl type not matching with expected values");
         }
 
@@ -318,9 +327,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
             l_nsl_clkregion_status &= l_regions;
 
             FAPI_ASSERT(l_nsl_clkregion_status == l_regions,
-                        fapi2::NEST_NSL_ERR()
+                        fapi2::THOLD_ERR()
                         .set_TARGET_CHIPLET(i_target)
-                        .set_READ_CLK_NSL(l_nsl_clock_status),
+                        .set_CLOCK_CMD(i_clock_cmd)
+                        .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL)
+                        .set_REGIONS(i_regions)
+                        .set_READ_CLK(l_nsl_clock_status),
                         "Clock running for nsl type not matching with expected values");
         }
     }
@@ -342,9 +354,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
             l_ary_clkregion_status &= l_regions;
 
             FAPI_ASSERT(l_ary_clkregion_status == l_regions,
-                        fapi2::NEST_ARY_ERR()
+                        fapi2::THOLD_ERR()
                         .set_TARGET_CHIPLET(i_target)
-                        .set_READ_CLK_ARY(l_ary_clock_status),
+                        .set_CLOCK_CMD(i_clock_cmd)
+                        .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY)
+                        .set_REGIONS(i_regions)
+                        .set_READ_CLK(l_ary_clock_status),
                         "Clock running for ary type not matching with expected values");
         }
 
@@ -356,9 +371,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
             l_ary_clkregion_status &= l_regions;
 
             FAPI_ASSERT(l_ary_clkregion_status == l_regions,
-                        fapi2::NEST_ARY_ERR()
+                        fapi2::THOLD_ERR()
                         .set_TARGET_CHIPLET(i_target)
-                        .set_READ_CLK_ARY(l_ary_clock_status),
+                        .set_CLOCK_CMD(i_clock_cmd)
+                        .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY)
+                        .set_REGIONS(i_regions)
+                        .set_READ_CLK(l_ary_clock_status),
                         "Clock running for ary type not matching with expected values");
         }
     }
@@ -547,9 +565,12 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
                  l_exp_sl_clock_status, l_sl_clock_status);
 
         FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status,
-                    fapi2::SL_ERR()
+                    fapi2::THOLD_ERR()
                     .set_TARGET_CHIPLET(i_target)
-                    .set_READ_CLK_SL(l_sl_clock_status),
+                    .set_CLOCK_CMD(i_clock_cmd)
+                    .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL)
+                    .set_REGIONS(i_regions)
+                    .set_READ_CLK(l_sl_clock_status),
                     "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES");
 
         FAPI_DBG("Check for clocks running NSL");
@@ -560,9 +581,12 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
                  l_exp_nsl_clock_status, l_nsl_clock_status);
 
         FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status,
-                    fapi2::NSL_ERR()
+                    fapi2::THOLD_ERR()
                     .set_TARGET_CHIPLET(i_target)
-                    .set_READ_CLK_NSL(l_nsl_clock_status),
+                    .set_CLOCK_CMD(i_clock_cmd)
+                    .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL)
+                    .set_REGIONS(i_regions)
+                    .set_READ_CLK(l_nsl_clock_status),
                     "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE");
 
         FAPI_DBG("Check for clocks running ARY");
@@ -573,9 +597,12 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
                  l_exp_ary_clock_status, l_ary_clock_status);
 
         FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status,
-                    fapi2::ARY_ERR()
+                    fapi2::THOLD_ERR()
                     .set_TARGET_CHIPLET(i_target)
-                    .set_READ_CLK_ARY(l_ary_clock_status),
+                    .set_CLOCK_CMD(i_clock_cmd)
+                    .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY)
+                    .set_REGIONS(i_regions)
+                    .set_READ_CLK(l_ary_clock_status),
                     "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE");
     }
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H
index 0b365529..9ebf9158 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -31,7 +31,7 @@
 // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
 // *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
-// *HWP Level           : 2
+// *HWP Level           : 3
 // *HWP Consumed by     : SBE
 //------------------------------------------------------------------------------
 
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
index 7da59f59..ae0d4961 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
@@ -190,9 +190,13 @@
    <!-- ******************************************************************** -->
     <hwpError>
       <sbeError/>
-      <rc>RC_ARY_ERR</rc>
-      <description>ary_thold status not matching the expected value in clock start stop sequence</description>
+      <rc>RC_THOLD_ERR</rc>
+      <description>thold status not matching the expected value in clock start stop sequence</description>
       <ffdc>TARGET_CHIPLET</ffdc>
+      <ffdc>CLOCK_CMD</ffdc>
+      <ffdc>CLOCK_TYPE</ffdc>
+      <ffdc>REGIONS</ffdc>
+      <ffdc>READ_CLK</ffdc>
       <collectRegisterFfdc>
 	   <id>NET_CTRL_REGISTERS</id>
 	   <target>TARGET_CHIPLET</target>
@@ -233,103 +237,20 @@
 	   <target>TARGET_CHIPLET</target>
 	   <targetType>TARGET_TYPE_PERV</targetType>
       </collectRegisterFfdc>
-      <ffdc>READ_CLK_ARY</ffdc>
-    </hwpError>
-   <!-- ******************************************************************** -->
-    <hwpError>
-      <sbeError/>
-      <rc>RC_NSL_ERR</rc>
-      <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
-      <ffdc>TARGET_CHIPLET</ffdc>
-      <collectRegisterFfdc>
-	   <id>NET_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CONFIG_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OTHER_CPLT_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OPCG_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CC_STATUS_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>ERROR_STATUS_OF_CC</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>CC_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <ffdc>READ_CLK_NSL</ffdc>
-    </hwpError>
-   <!-- ******************************************************************** -->
-    <hwpError>
-      <sbeError/>
-      <rc>RC_SL_ERR</rc>
-      <description>sl_thold status not matching the expected value in clock start stop sequence</description>
-      <ffdc>TARGET_CHIPLET</ffdc>
-      <collectRegisterFfdc>
-	   <id>NET_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CONFIG_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OTHER_CPLT_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OPCG_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CC_STATUS_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>ERROR_STATUS_OF_CC</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>CC_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <ffdc>READ_CLK_SL</ffdc>
+      <callout>
+	<target>TARGET_CHIPLET</target>
+	<priority>HIGH</priority>
+      </callout>
+      <callout>
+	<procedure>CODE</procedure>
+	<priority>LOW</priority>
+      </callout>
+      <deconfigure>
+	<target>TARGET_CHIPLET</target>
+      </deconfigure>
+      <gard>
+	<target>TARGET_CHIPLET</target>
+      </gard>
     </hwpError>
    <!-- ******************************************************************** -->
     <hwpError>
@@ -380,6 +301,20 @@
       <ffdc>PERV_CPLT_STAT0</ffdc>
       <ffdc>LOOP_COUNT</ffdc>
       <ffdc>HW_DELAY</ffdc>
+      <callout>
+	<target>TARGET_CHIPLET</target>
+	<priority>HIGH</priority>
+      </callout>
+      <callout>
+	<procedure>CODE</procedure>
+	<priority>LOW</priority>
+      </callout>
+      <deconfigure>
+	<target>TARGET_CHIPLET</target>
+      </deconfigure>
+      <gard>
+	<target>TARGET_CHIPLET</target>
+      </gard>
     </hwpError>
    <!-- ******************************************************************** -->
     <hwpError>
@@ -430,150 +365,20 @@
       <ffdc>PERV_CPLT_STAT0</ffdc>
       <ffdc>LOOP_COUNT</ffdc>
       <ffdc>HW_DELAY</ffdc>
-    </hwpError>
-   <!-- ******************************************************************** -->
-    <hwpError>
-      <sbeError/>
-      <rc>RC_NEST_ARY_ERR</rc>
-      <description>ary_thold status not matching the expected value in clock start stop sequence</description>
-      <ffdc>TARGET_CHIPLET</ffdc>
-      <collectRegisterFfdc>
-	   <id>NET_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CONFIG_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OTHER_CPLT_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OPCG_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CC_STATUS_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>ERROR_STATUS_OF_CC</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>CC_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <ffdc>READ_CLK_ARY</ffdc>
-    </hwpError>
-   <!-- ******************************************************************** -->
-    <hwpError>
-      <sbeError/>
-      <rc>RC_NEST_NSL_ERR</rc>
-      <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
-      <ffdc>TARGET_CHIPLET</ffdc>
-      <collectRegisterFfdc>
-	   <id>NET_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CONFIG_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OTHER_CPLT_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OPCG_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CC_STATUS_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>ERROR_STATUS_OF_CC</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>CC_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <ffdc>READ_CLK_NSL</ffdc>
-    </hwpError>
-   <!-- ******************************************************************** -->
-    <hwpError>
-      <sbeError/>
-      <rc>RC_NEST_SL_ERR</rc>
-      <description>sl_thold status not matching the expected value in clock start stop sequence</description>
-      <ffdc>TARGET_CHIPLET</ffdc>
-      <collectRegisterFfdc>
-	   <id>NET_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CPLT_CONFIG_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OTHER_CPLT_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>OPCG_CTRL_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-     </collectRegisterFfdc>
-     <collectRegisterFfdc>
-	   <id>CC_STATUS_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>ERROR_STATUS_OF_CC</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <collectRegisterFfdc>
-	   <id>CC_REGISTERS</id>
-	   <target>TARGET_CHIPLET</target>
-	   <targetType>TARGET_TYPE_PERV</targetType>
-      </collectRegisterFfdc>
-      <ffdc>READ_CLK_SL</ffdc>
+      <callout>
+	<target>TARGET_CHIPLET</target>
+	<priority>HIGH</priority>
+      </callout>
+      <callout>
+	<procedure>CODE</procedure>
+	<priority>LOW</priority>
+      </callout>
+      <deconfigure>
+	<target>TARGET_CHIPLET</target>
+      </deconfigure>
+      <gard>
+	<target>TARGET_CHIPLET</target>
+      </gard>
     </hwpError>
    <!-- ******************************************************************** -->
 </hwpErrors>