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authorRaja Das <rajadas2@in.ibm.com>2016-12-01 21:46:57 -0600
committerSachin Gupta <sgupta2m@in.ibm.com>2017-03-21 04:36:03 -0400
commit3096fa341d7199ad69837d3fbc0200d1074e9a74 (patch)
treec85193beba21da24ce15c47bcc708fcabb4dbcb3
parent5c49c264d74e8d69e3dab8e7849dab69a0e60095 (diff)
downloadtalos-sbe-3096fa341d7199ad69837d3fbc0200d1074e9a74.tar.gz
talos-sbe-3096fa341d7199ad69837d3fbc0200d1074e9a74.zip
BMC Mpipl isteps updated, 50009 Reg updated for Major/Minor Istep
Change-Id: Id06d2f0e84f055feb3080b043f0ac3de3de5ab01 RTC: 164425 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33292 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
-rw-r--r--src/sbefw/sbecmdiplcontrol.C45
-rw-r--r--src/sbefw/sbecmdiplcontrol.H2
-rw-r--r--src/sbefw/sberegaccess.H6
-rwxr-xr-xsrc/test/testcases/testIstepAuto.py2
-rwxr-xr-xsrc/tools/debug/sbe-debug.py8
5 files changed, 54 insertions, 9 deletions
diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C
index 9b4e34fd..841c764c 100644
--- a/src/sbefw/sbecmdiplcontrol.C
+++ b/src/sbefw/sbecmdiplcontrol.C
@@ -183,6 +183,11 @@ ReturnCode istepWithProcSequenceDrtm( sbeIstepHwp_t i_hwp );
ReturnCode istepMpiplSetFunctionalState( sbeIstepHwp_t i_hwp );
ReturnCode istepMpiplQuadPoweroff( sbeIstepHwp_t i_hwp );
ReturnCode istepStopClockMpipl( sbeIstepHwp_t i_hwp );
+// BMC Isteps, No-op in Fsp
+ReturnCode istepMpiplDumpRegs( sbeIstepHwp_t i_hwp );
+ReturnCode istepMpiplQueryQuadAccessState( sbeIstepHwp_t i_hwp );
+ReturnCode istepMpiplHcdCoreStopClocks( sbeIstepHwp_t i_hwp );
+ReturnCode istepMpiplHcdCacheStopClocks( sbeIstepHwp_t i_hwp );
// Utility function to do TPM reset
ReturnCode performTpmReset();
@@ -247,6 +252,14 @@ static istepMap_t g_istepMpiplContinuePtrTbl[MPIPL_CONTINUE_MAX_SUBSTEPS] =
#ifdef SEEPROM_IMAGE
// Setup EC/EQ guard records
{ &istepMpiplSetFunctionalState, NULL},
+ // Collect master quad regs, BMC Only istep, No-op in FSP
+ { &istepMpiplDumpRegs, NULL},
+ // Query Master quad, BMC Only istep, No-op in Fsp
+ { &istepMpiplQueryQuadAccessState, NULL},
+ // Master Quad Core stop clocks, BMC Only istep, No-op in Fsp
+ { &istepMpiplHcdCoreStopClocks, NULL},
+ // Master Quad Cache stop clocks, BMC Only istep, No-op in Fsp
+ { &istepMpiplHcdCacheStopClocks, NULL},
// p9_quad_power_off
{ istepMpiplQuadPoweroff, { .eqHwp = &p9_quad_power_off} },
// No-op
@@ -1315,3 +1328,35 @@ ReturnCode istepStopClockMpipl( sbeIstepHwp_t i_hwp )
#undef SBE_FUNC
}
+// BMC - Istep
+ReturnCode istepMpiplDumpRegs( sbeIstepHwp_t i_hwp )
+{
+ #define SBE_FUNC "istepMpiplDumpRegs"
+ return FAPI2_RC_SUCCESS;
+ #undef SBE_FUNC
+}
+//----------------------------------------------------------------------------
+// BMC - Istep
+ReturnCode istepMpiplQueryQuadAccessState( sbeIstepHwp_t i_hwp )
+{
+ #define SBE_FUNC "istepMpiplQueryQuadAccessState"
+ return FAPI2_RC_SUCCESS;
+ #undef SBE_FUNC
+}
+//----------------------------------------------------------------------------
+// BMC - Istep
+ReturnCode istepMpiplHcdCoreStopClocks( sbeIstepHwp_t i_hwp )
+{
+ #define SBE_FUNC "istepMpiplHcdCoreStopClocks"
+ return FAPI2_RC_SUCCESS;
+ #undef SBE_FUNC
+}
+//----------------------------------------------------------------------------
+// BMC - Istep
+ReturnCode istepMpiplHcdCacheStopClocks( sbeIstepHwp_t i_hwp )
+{
+ #define SBE_FUNC "istepMpiplHcdCacheStopClocks"
+ return FAPI2_RC_SUCCESS;
+ #undef SBE_FUNC
+}
+//----------------------------------------------------------------------------
diff --git a/src/sbefw/sbecmdiplcontrol.H b/src/sbefw/sbecmdiplcontrol.H
index bd7b821a..0895cad6 100644
--- a/src/sbefw/sbecmdiplcontrol.H
+++ b/src/sbefw/sbecmdiplcontrol.H
@@ -56,8 +56,8 @@ static const uint32_t SBE_ISTEP_MPIPL_START = 96;
static const uint32_t SBE_ISTEP_MPIPL_CONTINUE = 97;
static const uint32_t SBE_ISTEP_STOPCLOCK = 98;
static const uint32_t MPIPL_START_MAX_SUBSTEPS = 8;
-static const uint32_t MPIPL_CONTINUE_MAX_SUBSTEPS = 3;
static const uint32_t ISTEP_STOPCLOCK_MAX_SUBSTEPS = 1;
+static const uint32_t MPIPL_CONTINUE_MAX_SUBSTEPS = 7;
// constants
static const uint32_t ISTEP2_MAX_SUBSTEPS = 17;
diff --git a/src/sbefw/sberegaccess.H b/src/sbefw/sberegaccess.H
index 2502b06a..473370f3 100644
--- a/src/sbefw/sberegaccess.H
+++ b/src/sbefw/sberegaccess.H
@@ -248,9 +248,9 @@ class SbeRegAccess
uint64_t iv_reserved1 : 3;
uint64_t iv_prevState : 4;
uint64_t iv_currState : 4;
- uint64_t iv_majorStep : 4;
- uint64_t iv_minorStep : 8;
- uint64_t iv_reserved2 : 8;
+ uint64_t iv_majorStep : 8; // Max major is 97
+ uint64_t iv_minorStep : 6; // Max minor is 34
+ uint64_t iv_reserved2 : 6; // Unused
uint64_t iv_unused : 32;
};
uint64_t iv_messagingReg;
diff --git a/src/test/testcases/testIstepAuto.py b/src/test/testcases/testIstepAuto.py
index 31eba163..c581727a 100755
--- a/src/test/testcases/testIstepAuto.py
+++ b/src/test/testcases/testIstepAuto.py
@@ -37,7 +37,7 @@ gIstepArray = {
4:[1, 34],#istep 4.1 to 4.34
5:[1, 2], #istep 5.1 to 5.2
96:[1, 8],#istep 96.1 to 96.8
- 97:[1, 3],#istep 97.1 to 97.3
+ 97:[1, 7], #istep 97.1 to 97.7
98:[1, 1] #istep 98.1 to 98.1
}
# MAIN Test Run Starts Here...
diff --git a/src/tools/debug/sbe-debug.py b/src/tools/debug/sbe-debug.py
index 522a8446..1d1d4a40 100755
--- a/src/tools/debug/sbe-debug.py
+++ b/src/tools/debug/sbe-debug.py
@@ -262,14 +262,14 @@ def parsevalue(iValue):
tempVal = iValue[10:14]
print "SBE Current State : %s (%s)" %(sbeStates[tempVal], tempVal)
- tempVal = iValue[14:18]
+ tempVal = iValue[14:22]
print "Istep Major : %s" %(int(tempVal, 2))
- tempVal = iValue[18:26]
+ tempVal = iValue[22:28]
print "Istep Minor : %s" %(int(tempVal, 2))
- tempVal = iValue[26:34]
- print "Reserved Bit [24:31] : %s" %(tempVal)
+ tempVal = iValue[28:34]
+ print "Reserved Bit [26:31] : %s" %(tempVal)
def usage():
print "usage: testarg.py [-h] [-l {trace,attr,ppestate,sbestate,sbestatus,sbelocalregister}]\n\
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