blob: 587c0bd7043471659cc48645e7840055a061f023 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
config ARCH_SIRF
bool "CSR SiRF" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0
select NO_IOPORT
select PINCTRL
select PINCTRL_SIRF
help
Support for CSR SiRFprimaII/Marco/Polo platforms
if ARCH_SIRF
menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
config ARCH_ATLAS6
bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
default y
select CPU_V7
select SIRF_IRQ
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config ARCH_PRIMA2
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
default y
select CPU_V7
select SIRF_IRQ
select ZONE_DMA
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config ARCH_MARCO
bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
default y
select ARM_GIC
select CPU_V7
select HAVE_SMP
select SMP_ON_UP
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
endmenu
config SIRF_IRQ
bool
endif
|