summaryrefslogtreecommitdiffstats
path: root/drivers/pci/dwc/pcie-histb.c
Commit message (Collapse)AuthorAgeFilesLines
* PCI: Collect all native drivers under drivers/pci/controller/Shawn Lin2018-06-081-472/+0
| | | | | | | | | | | | | | | | | | Native PCI drivers for root complex devices were originally all in drivers/pci/host/. Some of these devices can also be operated in endpoint mode. Drivers for endpoint mode didn't seem to fit in the "host" directory, so we put both the root complex and endpoint drivers in per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc. These per-device directories contain trivial Kconfig and Makefiles and clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and collect all the device-specific drivers there. No functional change intended. Link: https://lkml.kernel.org/r/1520304202-232891-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Merge branch 'lorenzo/pci/dwc-msi'Bjorn Helgaas2018-04-041-15/+0
|\ | | | | | | | | | | | | * lorenzo/pci/dwc-msi: PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256 PCI: dwc: Remove old MSI IRQs API PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
| * PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical APIGustavo Pimentel2018-03-061-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct msi_controller based API. Although the old implementation API is still available, pcie-designware will now use the multiplexed IRQ domains hierarchical API. Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* | PCI: histb: Add an optional regulator for PCIe port power controlShawn Guo2018-03-071-0/+21
| | | | | | | | | | | | | | | | | | | | The power supplies to PCIe port are often controlled by GPIO on some board designs. Let's add an optional regulator which can be backed by GPIO to control the power. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
* | PCI: histb: Fix error path of histb_pcie_host_enable()Shawn Guo2018-03-071-4/+3
|/ | | | | | | | | If clk_prepare_enable() call fails on a particular clock, we should not call clk_disable_unprepare() on this clock, but on the clocks that succeed from clk_prepare_enable() previously. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplateBjorn Helgaas2018-01-281-4/+1
| | | | | | | | | | | Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license. Remove the boilerplate GPL version 2 language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* PCI: hisi: Add HiSilicon STB SoC PCIe controller driverJianguo Sun2017-10-241-0/+470
Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
OpenPOWER on IntegriCloud