summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/dsi/dsi_phy.c
Commit message (Collapse)AuthorAgeFilesLines
* drm/msm/dsi: Split PHY drivers to separate filesHai Li2015-08-151-756/+0
| | | | | | | | This change moves each PHY type specific code into separate files. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Return void from msm_dsi_phy_disable()Hai Li2015-08-151-11/+5
| | | | | | | | We are not checking the return value from msm_dsi_phy_disable(). Change the return type to void. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Specify bitmask to set source PLLHai Li2015-08-151-5/+11
| | | | | | | | | The bit position to configure source PLL will change on new types of PHYs. The caller should pass down this information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add support for msm8x94Hai Li2015-08-151-0/+131
| | | | | | | | | DSI controller on msm8x94 is version 1.3, which requires different power supplies and works with 20nm DSI PHY. This change is to add the basic support for this version. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Update source PLL selection in DSI PHYHai Li2015-08-151-8/+26
| | | | | | | | | | | | | | The source PLL to be used by each DSI PHY should be decided by DSI manager based on dual DSI information, while the register programming to select PLL is different from one type of PHY to another. This change adds the H/W difference to PHY configuration and updates the interface between DSI manager and PHY. With this change, PLL selection can be supported on different targets. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Separate PHY to another platform deviceHai Li2015-06-111-40/+226
| | | | | | | | | | | | There are different types of PHY from one chipset to another, while the DSI host controller is relatively consistent across platforms. Also, the PLL inside PHY is providing the source of DSI byte and pixel clocks, which are used by DSI host controller. Separated devices for clock provider and clock consumer make DSI driver better fit into common clock framework. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Enable PLL driver in MSM DSIHai Li2015-06-111-0/+68
| | | | | | | | This change activates PLL driver for DSI to work with common clock framework. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add DSI PLL clock driver supportHai Li2015-06-111-1/+2
| | | | | | | | | | | | | | DSI byte clock and pixel clocks are sourced from DSI PLL. This change adds the DSI PLL source clock driver under common clock framework. This change handles DSI 28nm PLL only. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Wentao Xu <wentaox@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: use IS_ERR() to check msm_ioremap() returnFabian Frederick2015-06-111-2/+2
| | | | | | | msm_ioremap() never returns NULL. There's no need for IS_ERR_OR_NULL() Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Initial add DSI connector supportHai Li2015-04-011-0/+352
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
OpenPOWER on IntegriCloud