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path: root/drivers/gpu/drm/i915/intel_ddi.c
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* drm/i915: Consider SPLL as another shared pll, v2.Maarten Lankhorst2015-11-181-10/+65
* drm/i915: Rename DP link training functionsAnder Conselvan de Oliveira2015-10-061-1/+0
* drm/i915/bxt: DSI encoder support in CRTC modesetShashank Sharma2015-10-021-2/+5
* drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä2015-10-011-8/+8
* drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/Ville Syrjälä2015-09-301-23/+23
* drm/i915/ddi: use switch case instead of if ladder for ddi_get_encoder_portJani Nikula2015-09-301-7/+13
* drm/i915/ddi: warn instead of oops on invalid ddi encoder typeJani Nikula2015-09-301-2/+1
* drm/i915/bxt: Set oscaledcompmethod to enable scale valueSonika Jindal2015-09-301-2/+6
* drm/i915/bxt: eDP low vswing supportSonika Jindal2015-09-301-4/+19
* drm/i915: Parametrize DDI_BUF_TRANS registersVille Syrjälä2015-09-231-10/+9
* drm/i915/bxt: Fix wrongly placed ')' in I915_READ()Damien Lespiau2015-09-181-1/+1
* Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter2015-09-021-50/+25
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| * drm/i915: Don't use link_bw for PLL setupVille Syrjälä2015-09-011-7/+4
| * drm/i915/skl: Update DDI buffer translation programming.Rodrigo Vivi2015-08-261-50/+25
* | drm/i915: Put back lane_count into intel_dp and add link_rate tooVille Syrjälä2015-08-261-2/+3
* | drm/i915: Move intel_dp->lane_count into pipe_configVille Syrjälä2015-08-141-4/+6
* | drm/i915: Don't pass clock to DDI PLL select functionsVille Syrjälä2015-08-141-10/+10
* | drm/i915: Don't use link_bw for PLL setupVille Syrjälä2015-08-141-7/+4
* | drm/i915/bxt: WA for swapped HPD pins in A steppingSonika Jindal2015-08-141-1/+9
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* drm/i915: Per-DDI I_boost overrideAntti Koskipaa2015-08-141-8/+30
* drm/i915: Set alternate aux for DDI-ERodrigo Vivi2015-08-141-3/+2
* drm/i915: set FDI translations to NULL on SKLPaulo Zanoni2015-07-061-0/+1
* drm/i915/bxt: BUNs related to port PLLVandana Kannan2015-07-061-10/+5
* drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platformsVille Syrjälä2015-07-061-25/+24
* drm/i915/bxt: mask off the DPLL state checker bits we don't programImre Deak2015-07-031-0/+20
* drm/i915/bxt: add DDI port HW readout supportImre Deak2015-06-301-2/+20
* drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak2015-06-301-3/+13
* drm/i915/skl: Buffer translation improvementsDavid Weinehall2015-06-301-115/+394
* drm/i915/skl: Skip remaining dividers when deviation is 0Damien Lespiau2015-06-261-1/+8
* drm/i915/skl: Prefer even dividers for SKL DPLLsDamien Lespiau2015-06-261-0/+7
* drm/i915/skl: Replace the HDMI DPLL divider computation algorithmDamien Lespiau2015-06-261-74/+137
* drm/i915/bxt: fix DDI PHY vswing scale value settingImre Deak2015-06-121-18/+18
* drm/i915: Don't display the boot CDCLK twiceDamien Lespiau2015-06-121-4/+3
* drm/i915/bxt: edp1.4 Intermediate Freq supportSonika Jindal2015-06-031-23/+16
* drm/i915/skl: Don't try to store the wrong central frequencyDamien Lespiau2015-05-291-2/+0
* drm/i915: Correctly prefix HSW/BDW HDMI clock functionsDamien Lespiau2015-05-291-13/+12
* drm/i915/skl: Remove unnecessary () used with abs_diff()Damien Lespiau2015-05-291-1/+1
* drm/i915/skl: Remove unnecessary () used with div_u64()Damien Lespiau2015-05-291-3/+3
* drm/i915/skl: Factor out computing the DPLL paramaters from the dividersDamien Lespiau2015-05-291-64/+75
* drm/i915/skl: Use a more idomatic early returnDamien Lespiau2015-05-291-62/+59
* drm/i915/skl: Propagate the error if we fail to find a suitable DPLL dividerDamien Lespiau2015-05-291-2/+6
* drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failingDamien Lespiau2015-05-291-1/+2
* drm/i915/skl: Make sure to break when not finding suitable PLL dividersDamien Lespiau2015-05-291-0/+4
* drm/i915: remove useless DP and DDI encoder ->hot_plug hooksJani Nikula2015-05-291-15/+0
* drm/i915: group all hotplug related fields into a new struct in dev_privJani Nikula2015-05-291-1/+1
* drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau2015-05-211-2/+6
* drm/i915/bxt: Move around lane stagger calculationVandana Kannan2015-05-201-20/+20
* drm/i915/bxt: Port PLL programming BUNVandana Kannan2015-05-201-23/+56
* drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira2015-05-201-0/+9
* drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau2015-05-081-32/+32
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