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path:
root
/
drivers
/
gpu
/
drm
/
i915
/
i915_reg.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
drm/i915/icl: Define Panel power ctrl register
Madhav Chauhan
2018-12-03
1
-0
/
+11
*
drm/i915/icl: Define missing bitfield for shortplug reg
Madhav Chauhan
2018-12-03
1
-0
/
+1
*
i915/dp/fec: Configure the Forward Error Correction bits.
Anusha Srivatsa
2018-11-29
1
-0
/
+2
*
drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Manasi Navare
2018-11-29
1
-0
/
+1
*
drm/i915: Make CHICKEN_TRANS reg not depend on enum value
Imre Deak
2018-11-21
1
-3
/
+4
*
drm/i915: Make EDP PSR flags not depend on enum values
Imre Deak
2018-11-21
1
-3
/
+7
*
Revert "drm/i915/perf: add a parameter to control the size of OA buffer"
Joonas Lahtinen
2018-11-19
1
-2
/
+0
*
drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA
Mika Kuoppala
2018-11-14
1
-3
/
+1
*
drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DEN
Paulo Zanoni
2018-11-13
1
-2
/
+1
*
drm/i915: Polish the skl+ plane keyval/msk/max register setup
Ville Syrjälä
2018-11-09
1
-1
/
+1
*
drm/i915/icl: Define Plane Input CSC Coefficient Registers
Uma Shankar
2018-11-06
1
-0
/
+50
*
drm/i915/fia: FIA registers offset implementation.
Anusha Srivatsa
2018-11-02
1
-4
/
+6
*
drm/i915: also group device info array helper macros with others
Jani Nikula
2018-11-02
1
-12
/
+14
*
drm/i915: reorder and reindent the register choosing helper wrappers
Jani Nikula
2018-11-02
1
-14
/
+17
*
drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
Jani Nikula
2018-11-02
1
-1
/
+1
*
drm/i915: remove palette_offsets from device info in favor of _PICK()
Jani Nikula
2018-11-02
1
-9
/
+7
*
drm/i915/icl: Fix DSS_CTL register names
Anusha Srivatsa
2018-11-01
1
-11
/
+11
*
drm/i915/icl: WaAllowUMDToModifySamplerMode
Oscar Mateo
2018-11-01
1
-0
/
+2
*
drm/i915/icl: Add WaEnable32PlaneMode
Radhakrishna Sripada
2018-11-01
1
-0
/
+1
*
drm/i915/icl: Add DSS_CTL Registers
Anusha Srivatsa
2018-11-01
1
-0
/
+33
*
drm/i915/icl: Add DSI packet payload/header registers
Madhav Chauhan
2018-11-01
1
-0
/
+22
*
drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
Manasi Navare
2018-10-31
1
-2
/
+6
*
drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
Anusha Srivatsa
2018-10-31
1
-0
/
+1
*
drm/i915/icl: Define DSI timeout registers
Madhav Chauhan
2018-10-31
1
-0
/
+43
*
drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
Dhinakaran Pandiyan
2018-10-29
1
-10
/
+9
*
drm/i915: Fix VIDEO_DIP_CTL bit shifts
Dhinakaran Pandiyan
2018-10-29
1
-6
/
+6
*
drm/i915: Define Intel HDCP2.2 registers
Ramalingam C
2018-10-29
1
-0
/
+32
*
drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.
Maarten Lankhorst
2018-10-24
1
-0
/
+1
*
drm/i915/gen11: Program the chroma upsampler for HDR planes.
Maarten Lankhorst
2018-10-24
1
-0
/
+22
*
drm/i915/gen11: Program the scalers correctly for planar formats, v3.
Maarten Lankhorst
2018-10-24
1
-1
/
+3
*
drm/i915/perf: add a parameter to control the size of OA buffer
Lionel Landwerlin
2018-10-23
1
-0
/
+2
*
drm/i915/icl: Define DSI panel programming registers
Madhav Chauhan
2018-10-22
1
-0
/
+38
*
drm/i915/icl: Define TRANS_CONF register for DSI
Madhav Chauhan
2018-10-22
1
-0
/
+8
*
drm/i915/icl: Define DSI transcoder timing registers
Madhav Chauhan
2018-10-22
1
-0
/
+14
*
drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
Madhav Chauhan
2018-10-22
1
-0
/
+17
*
drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Madhav Chauhan
2018-10-22
1
-0
/
+45
*
drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Madhav Chauhan
2018-10-22
1
-0
/
+4
*
drm/i915/icl: Fix DDI/TC port clk_off bits
Mahesh Kumar
2018-10-16
1
-0
/
+3
*
drm/i915/icl: Introduce new macros to get combophy registers
Lucas De Marchi
2018-10-16
1
-104
/
+59
*
drm/i915/icl: Combine all port/combophy macros at one place
Mahesh Kumar
2018-10-16
1
-65
/
+72
*
drm/i915/icl: apply Display WA #1178 to fix type C dongles
Lucas De Marchi
2018-10-16
1
-0
/
+9
*
drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
Shashank Sharma
2018-10-15
1
-0
/
+2
*
drm/i915/icl:Add Wa_1606682166
Anuj Phogat
2018-10-09
1
-0
/
+1
*
drm/i915/icl: Add Wa_1406609255
Radhakrishna Sripada
2018-10-09
1
-0
/
+3
*
drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
José Roberto de Souza
2018-10-05
1
-2
/
+2
*
drm/i915: Add plane alpha blending support, v2.
Maarten Lankhorst
2018-10-02
1
-0
/
+2
*
drm/i915/icl: Define TA_TIMING_PARAM registers
Madhav Chauhan
2018-09-26
1
-0
/
+23
*
drm/i915/icl: Define data/clock lanes dphy timing registers
Madhav Chauhan
2018-09-26
1
-0
/
+58
*
drm/i915: Clean up scaler setup, v2.
Maarten Lankhorst
2018-09-21
1
-3
/
+4
*
drm/i915/skl+: Decode memory bandwidth and parameters
Mahesh Kumar
2018-09-13
1
-0
/
+18
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