summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/powerplay/inc
Commit message (Collapse)AuthorAgeFilesLines
* drm/amdgpu: update smu_v11_0_pptable.hAlex Deucher2020-02-111-14/+32
| | | | | | | | Update to the latest changes. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.5.x
* drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables (v2)Matt Coffin2020-02-041-0/+1
| | | | | | | | | | | | | | | | | Previously, the syfs functionality for restoring the default powerplay table was sourcing it's information from the currently-staged powerplay table. This patch adds a step to cache the first overdrive table that we see on boot, so that it can be used later to "restore" the powerplay table v2: sqaush my original with Matt's fix Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.5.x
* drm/amd/powerplay: fix navi10 system intermittent reboot issue V2Evan Quan2020-02-043-1/+7
| | | | | | | | | | | This workaround is needed only for Navi10 12 Gbps SKUs. V2: added SMU firmware version guard Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/amd/powerplay: update SMU12_DRIVER_IF_VERSION to 11Aaron Liu2020-01-141-1/+6
| | | | | | | | This patch updates SMU12_DRIVER_IF_VERSION to 11. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: unified VRAM address for driver table interaction with SMU V2Evan Quan2020-01-073-0/+14
| | | | | | | | | | | | By this, we can avoid to pass in the VRAM address on every table transferring. That puts extra unnecessary traffics on SMU on some cases(e.g. polling the amdgpu_pm_info sysfs interface). V2: document what the driver table is for and how it works Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: cache the watermark settings on system memoryEvan Quan2020-01-071-0/+1
| | | | | | | | | | So that we do not need to allocate a piece of VRAM for it. This is a preparation for coming change which unifies the VRAM address for all driver tables interaction with SMU. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add smu11_driver_if_arcturus.h new OOB membersEvan Quan2020-01-072-2/+8
| | | | | | | | This is to fit the latest SMC firmware and it's backward compatible. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/smu: add helper function smu_get_dpm_level_range() for smu driverKevin Wang2020-01-071-0/+2
| | | | | | | | | this function can help smu driver to query dpm level clock range from smu firmware. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/smu: make the set_performance_level logic easier to followAlex Deucher2020-01-071-0/+3
| | | | | | | | Have every asic provide a callback for this rather than a mix of generic and asic specific code. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: support custom power profile settingEvan Quan2020-01-071-4/+2
| | | | | | | | Support custom power profile mode settings on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/smu: add metrics table lockAlex Deucher2019-12-181-0/+1
| | | | | | | | | This table is used for lots of things, add it's own lock. Bug: https://gitlab.freedesktop.org/drm/amd/issues/900 Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/smu: fix spellingAlex Deucher2019-12-181-1/+1
| | | | | | | s/dispaly/display/g Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable pp one vf mode for vega10Yintian Tao2019-12-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Originally, due to the restriction from PSP and SMU, VF has to send message to hypervisor driver to handle powerplay change which is complicated and redundant. Currently, SMU and PSP can support VF to directly handle powerplay change by itself. Therefore, the old code about the handshake between VF and PF to handle powerplay will be removed and VF will use new the registers below to handshake with SMU. mmMP1_SMN_C2PMSG_101: register to handle SMU message mmMP1_SMN_C2PMSG_102: register to handle SMU parameter mmMP1_SMN_C2PMSG_103: register to handle SMU response v2: remove module parameter pp_one_vf v3: fix the parens v4: forbid vf to change smu feature v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute v6: change skip condition at vega10_copy_table_to_smc Signed-off-by: Yintian Tao <yttao@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: implement the get_enabled_mask callback for smu12Xiaomeng Hou2019-12-111-0/+3
| | | | | | | | implement sensor interface of feature mask for debugfs. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: implement interface to retrieve clock freq for renoirXiaomeng Hou2019-12-111-0/+4
| | | | | | | | | implement smu12 get_clk_freq interface to get clock frequency like MCLK/SCLK. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: unify smu send message functionLikun Gao2019-12-033-8/+6
| | | | | | | | | | | | | Drop smu_send_smc_msg function from ASIC specify structure. Reuse smu_send_smc_msg_with_param function for smu_send_smc_msg. Set paramer to 0 for smu_send_msg function, otherwise it will send with previous paramer value (Not a certain value). Materialize msg type for smu send message function definition. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: split swSMU baco_reset into enter and exitAlex Deucher2019-11-192-3/+6
| | | | | | | | | BACO - Bus Active, Chip Off So we can use it for power savings rather than just reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable gpu_busy_percent sys interface for renoir (v2)changzhu2019-11-191-0/+4
| | | | | | | | | | | | | | To get the value of gpu_busy_percent, it needs to realize get_current_activity_percent and get_metrics_table. The framework of renoir smu is different from old ones like raven. It needs to realize get_current_activity_percent and get_metrics_table in renoir_ppt.c like navi10. v2: remove unused variable (Alex) Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2Evan Quan2019-11-191-0/+1
| | | | | | | | | | | | | | Otherwise, without RLC reinitialization, the DPM reenablement will fail. That affects the custom pptable uploading. V2: setting/clearing uploading_custom_pp_table in smu_sys_set_pp_table() Reported-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Matt Coffin <mcoffin13@gmail.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add Powergate JPEG for RenoirLeo Liu2019-11-191-0/+2
| | | | | | | | | | Similar to SDMA, VCN etc. v2: add argument to both PowerUpJpeg and PowerDownJpeg messages Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add JPEG Powerplay interfaceLeo Liu2019-11-191-0/+3
| | | | | | | | It will be used for different SMU specific to HW Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: read pcie speed/width info (v2)Kenneth Feng2019-11-131-0/+8
| | | | | | | | | | sysfs interface to read pcie speed&width info on navi1x. v2: fix warning (trivial) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/smu_v11: Unify and fix power limitsMatt Coffin2019-11-113-1/+7
| | | | | | | | | | | | | | | | | | | [Why] On Navi10, and presumably arcterus, updating pp_table via sysfs would not re-scale the maximum possible power limit one can set. On navi10, the SMU code ignored the power percentage overdrive setting entirely, and would not allow you to exceed the default power limit at all. [How] Adding a function to the SMU interface to get the pptable version of the default power limit allows ASIC-specific code to provide the correct maximum-settable power limit for the current pptable. v3: fix spelling (Alex) Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/navi10: implement sclk/mclk OD via pp_od_clk_voltageMatt Coffin2019-11-111-0/+2
| | | | | | | | | | | | | | [Why] Before this patch, there was no way to use pp_od_clk_voltage on navi [How] Similar to the vega20 implementation, but using the common smc_v11_0 headers, implemented the pp_od_clk_voltage API for navi10's pptable implementation Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: dynamically disable ds and ulv for computeKenneth Feng2019-11-081-0/+2
| | | | | | | | | | | | | This is to improve the performance in the compute mode for vega10. For example, the original performance for a rocm bandwidth test: 2G internal GPU copy, is about 99GB/s. With the idle power features disabled dynamically, the porformance is promoted to about 215GB/s. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update Arcturus driver-smu interface headerEvan Quan2019-11-062-2/+2
| | | | | | | | | To fit the latest SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2Evan Quan2019-11-061-0/+1
| | | | | | | | | | Add xgmi pstate setting on powerplay routine. V2: split the change of is_support_sw_smu_xgmi into a separate patch Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Add interface for I2C transactions to SMU.Andrey Grodzovsky2019-10-251-0/+9
| | | | | | | | | | Will be used by Arcturus support for RAS page retirement. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: clear the swSMU code layerEvan Quan2019-10-253-10/+160
| | | | | | | | | | | With this cleanup, the APIs from amdgpu_smu.c will map to ASIC specific ones directly. Those can be shared around all SMU V11/V12 ASICs will be put in smu_v11_0.c and smu_v12_0.c respectively. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: split out those internal used swSMU APIs V2Evan Quan2019-10-251-160/+1
| | | | | | | | | | | | Those swSMU APIs used internally are moved to smu_internal.h while others are kept in amdgpu_smu.h. V2: give a better name smu_internal.h for the place to hold those internal APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add lock protection for swSMU APIs V2Evan Quan2019-10-251-75/+87
| | | | | | | | | | | | | | | | This is a quick and low risk fix. Those APIs which are exposed to other IPs or to support sysfs/hwmon interfaces or DAL will have lock protection. Meanwhile no lock protection is enforced for swSMU internal used APIs. Future optimization is needed. V2: strip the lock protection for all swSMU internal APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update Arcturus driver smu interface XGMI link partEvan Quan2019-10-252-9/+21
| | | | | | | | To fit the latest SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add renoir funcs to support dcHersen Wu2019-10-151-9/+7
| | | | | | | | | | | | there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: bug fix for pcie parameters overrideKenneth Feng2019-10-151-0/+8
| | | | | | | | | | | | | | | | | | | | | Bug fix for pcie paramerers override on swsmu. Below is a scenario to have this problem. pptable definition on pcie dpm: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:4, pcie lanes: *16 Then if we have a system only have the capbility: pcie gen speed: 3, pcie lanes: *8, we will override dpm 1 to pcie gen speed 3, pcie lanes *8. But the code skips the dpm 0 configuration. So the real pcie dpm parameters are: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:3, pcie lanes: *8 Then the wrong pcie lanes will be toggled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable df cstate control on swSMU routineEvan Quan2019-10-152-0/+4
| | | | | | | | | Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable df cstate control on powerplay routineEvan Quan2019-10-152-1/+3
| | | | | | | | | Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update the interface for getting dpm full scale clock ↵Prike Liang2019-10-031-3/+4
| | | | | | | | | | frequency Update get_dpm_uclk_limited to get more clock type full scale dpm frequency. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: implement the interface for setting soft freq rangePrike Liang2019-10-031-0/+3
| | | | | | | | | The APU soft freq range set by different way from DGPU, thus need implement the function respectively base on each common SMU part. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu ↵Prike Liang2019-10-031-0/+1
| | | | | | | | | | | | series For now APU has no smu_dpm_context structure for containing default/current related dpm tables, thus will needn't initialize smu_dpm_context to aviod APU null pointer issue. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add sensor lock support for smuKevin Wang2019-10-031-0/+1
| | | | | | | | | | | | | | | | | | | | | when multithreading access sysfs of amdgpu_pm_info at the sametime. the swsmu driver cause smu firmware hang. eg: single thread access: Message A + Param A ==> right Message B + Param B ==> right Message C + Param C ==> right multithreading access: Message A + Param B ==> error Message B + Param A ==> error Message C + Param C ==> right the patch will add sensor lock(mutex) to avoid this error. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update arcturus smu-driver interaction headerEvan Quan2019-10-032-8/+9
| | | | | | | | To pair the latest SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: remove duplicate macro of smu_get_uclk_dpm_statesKevin Wang2019-10-031-2/+0
| | | | | | | | | | | | remove duplicate macro of smu_get_uclk_dpm_states fix commit: drm/amd/powerplay: add the interface for getting ultimate frequency v3 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Add mode2 mode for GPU RESET in SMUchen gong2019-10-031-0/+10
| | | | | | | | Renoir need to use mode2 mode to implement GPU RESET Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add new mapping for APCC_DFLL featureXiaojie Yuan2019-10-031-0/+1
| | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: properly set mp1 state for SW SMU suspend/reset routineEvan Quan2019-09-161-0/+2
| | | | | | | | Set mp1 state properly for SW SMU suspend/reset routine. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update smu11_driver_if_arcturus.hEvan Quan2019-09-162-2/+6
| | | | | | | | Also bump the SMU11_DRIVER_IF_VERSION_ARCT. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: issue DC-BTC for arcturus on SMU initEvan Quan2019-09-163-5/+5
| | | | | | | | Need to perform DC-BTC for arcturus on bootup. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: replace smu->table_count with SMU_TABLE_COUNT in smu (v2)Kevin Wang2019-09-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | fix bellow patch issue: drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic ---- "This patch introduces new smu table type, it's to handle the different smu table defines for each asic with the same smu ip." before: use smu->table_count to represent the actual table count in smc firmware use actual table count to check smu function parameter about smu table after: use logic table count "SMU_TABLE_COUNT" to check function parameter because table id already mapped in smu driver, and smu function will use logic table id not actual table id to check func parameter. v2: squash in warning fix Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: do proper cleanups on hw_finiEvan Quan2019-09-131-0/+3
| | | | | | | | These are needed for smu_reset support. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update cached feature enablement status V3Evan Quan2019-09-131-1/+0
| | | | | | | | | | | | | Need to update in cache feature enablement status after pp_feature settings. Another fix for the commit below: drm/amd/powerplay: implment sysfs feature status function in smu V2: update smu_feature_update_enable_state() and relates V3: use bitmap_or and bitmap_andnot Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud