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* clk: renesas: move drivers to renesas directorySimon Horman2016-03-0315-3670/+0
| | | | | | | | | | | | | This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-shmobile-for-v4.6' of ↵Stephen Boyd2016-03-032-2/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull shmobile clk updates from Geert Uytterhoeven: - Fix a bug in the div6 clock driver that was exposed by CAN support on R-Car H3, - Add more module clocks for R-Car H3. * 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: shmobile: r8a7795: Add CAN FD peripheral clock clk: shmobile: r8a7795: Add CANFD clock clk: shmobile: r8a7795: Add CAN peripheral clock clk: shmobile: div6: Fix .recalc_rate() using a stale divisor clk: shmobile: r8a7795: Add LVDS module clock clk: shmobile: r8a7795: Add FCP clocks
| * clk: shmobile: r8a7795: Add CAN FD peripheral clockRamesh Shanmugasundaram2016-02-261-0/+1
| | | | | | | | | | Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: r8a7795: Add CANFD clockRamesh Shanmugasundaram2016-02-261-0/+1
| | | | | | | | | | Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: r8a7795: Add CAN peripheral clockRamesh Shanmugasundaram2016-02-261-0/+2
| | | | | | | | | | Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: div6: Fix .recalc_rate() using a stale divisorGeert Uytterhoeven2016-02-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpg_div6_clock_set_rate() only programs the new divisor if the clock isn't stopped. If the clock is stopped, it will update the cached divisor value only, which will be programmed into the clock registers when enabling the clock later. However, cpg_div6_clock_recalc_rate() reads the divisor from the clock registers instead of using the cached value, leading to an incorrect result if the clock is currently stopped. Make cpg_div6_clock_recalc_rate() use the cached value to fix this. Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
| * clk: shmobile: r8a7795: Add LVDS module clockLaurent Pinchart2016-02-261-0/+1
| | | | | | | | | | | | | | The parent clock hasn't been validated yet. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: r8a7795: Add FCP clocksLaurent Pinchart2016-02-261-0/+15
| | | | | | | | | | | | | | | | The parent clock isn't documented in the datasheet, use S2D1 as a best guess for now. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: shmobile: Free 'clock' on error pathStephen Boyd2016-02-251-0/+1
| | | | | | | | | | | | | | We forgot to free this clock when we return early in this code. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: shmobile: check for failureSudip Mukherjee2016-02-241-1/+5
|/ | | | | | | | | We were not checking the return from devm_add_action() which can fail. Start using the helper devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: shmobile: r8a7795: Add INTC-EX clockMagnus Damm2016-02-181-0/+1
| | | | | | | | | | | Add the "intc-ex" clock to the r8a7795 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: shmobile: r8a7795: Add USB-DMAC clocksYoshihiro Shimoda2016-02-081-0/+2
| | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: shmobile: r8a7795: Add SD divider supportDirk Behme2016-02-082-0/+232
| | | | | | | | | This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: shmobile: r8a7795: Add USB3.0 clocksYoshihiro Shimoda2016-01-251-0/+2
| | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge branch 'clk-renesas' into clk-nextMichael Turquette2015-12-311-0/+1
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| * clk: shmobile: r8a7795: Add SATA0 clockUlrich Hecht2015-12-311-0/+1
| | | | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | Merge branch 'clk-shmobile-for-v4.5' of ↵Michael Turquette2015-12-226-63/+1215
|\| | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
| * clk: shmobile: r8a7795: Add new CPG/MSSR driverGeert Uytterhoeven2015-12-084-0/+391
| | | | | | | | | | | | | | Add a new R-Car H3 Clock Pulse Generator / Module Standby and Software Reset driver, using the new CPG/MSSR driver core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: Add new CPG/MSSR driver coreGeert Uytterhoeven2015-12-082-0/+721
| | | | | | | | | | | | | | Add the common core for the new Renesas Clock Pulse Generator / Module Standby and Software Reset driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: div6: Extract cpg_div6_register()Geert Uytterhoeven2015-12-082-45/+94
| | | | | | | | | | | | | | | | Extract cpg_div6_register(), to allow registering div6 clocks from another clock driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| * clk: shmobile: div6: Make clock-output-names optionalGeert Uytterhoeven2015-12-081-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | Renesas DIV6 clocks provide a single clock output. Hence make the "clock-output-names" DT property optional instead of mandatory. In case the DT property is omitted the DT node name will be used. Rename the variable "name" to "clk_name" to make the code more similar with fixed-factor-clock.c, and to avoid a conflict with a nested local variable while we're at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: Rework CONFIG_ARCH_SHMOBILE_MULTIMagnus Damm2015-12-081-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Shmobile is all multiplatform these days, so get rid of the reference to CONFIG_ARCH_SHMOBILE_MULTI in drivers/clk/shmobile/. Also instead of always enabling DIV6 and MSTP adjust the Makefile to enable DIV6 and MSTP depending on if they are included in the SoC or not. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: shmobile: rcar-gen2: Spelling/Grammar: dependant of, ouputGeert Uytterhoeven2015-11-201-2/+2
|/ | | | | | | | s/dependant of/dependent on/ s/ouput/output/ Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-11-101-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "New and/or improved SoC support for this release: Marvell Berlin: - Enable standard DT-based cpufreq - Add CPU hotplug support Freescale: - Ethernet init for i.MX7D - Suspend/resume support for i.MX6UL Allwinner: - Support for R8 chipset (used on NTC's $9 C.H.I.P board) Mediatek: - SMP support for some platforms Uniphier: - L2 support - Cleaned up SMP support, etc. plus a handful of other patches around above functionality, and a few other smaller changes" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) ARM: uniphier: rework SMP operations to use trampoline code ARM: uniphier: add outer cache support Documentation: EXYNOS: Update bootloader interface on exynos542x ARM: mvebu: add broken-idle option ARM: orion5x: use mac_pton() helper ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned ARM: sunxi: Add R8 support ARM: digicolor: select pinctrl/gpio driver arm: berlin: add CPU hotplug support arm: berlin: use non-self-cleared reset register to reset cpu ARM: mediatek: add smp bringup code ARM: mediatek: enable gpt6 on boot up to make arch timer working soc: mediatek: Fix random hang up issue while kernel init soc: ti: qmss: make acc queue support optional in the driver soc: ti: add firmware file name as part of the driver Documentation: dt: soc: Add description for knav qmss driver ARM: S3C64XX: Use PWM lookup table for mach-smartq ARM: S3C64XX: Use PWM lookup table for mach-hmt ARM: S3C64XX: Use PWM lookup table for mach-crag6410 ARM: S3C64XX: Use PWM lookup table for smdk6410 ...
| * clk: shmobile: mstp: Consider "zb_clk" suitable for power managementGeert Uytterhoeven2015-09-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power manage a device. Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0), the Bus State Controller (BSC) is not power-managed by an MSTP clock, but by a plain CPG clock (zb_clk). Add a special case to handle this, so the clock is properly managed, and devices connected to the BSC work as expected. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | clk: shmobile: mstp: Drop bogus closing parenthesis in error messageGeert Uytterhoeven2015-10-161-1/+1
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: shmobile: r8a7778: Make r8a7778_rates[] and r8a7778_divs[] static constGeert Uytterhoeven2015-10-161-4/+4
|/ | | | | | | | r8a7778_rates[] and r8a7778_divs[] are only used in clk-r8a7778.c, and never modified. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'i2c/for-4.3' of ↵Linus Torvalds2015-09-081-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c updates from Wolfram Sang: "Features: - new drivers: Renesas EMEV2, register based MUX, NXP LPC2xxx - core: scans DT and assigns wakeup interrupts. no driver changes needed. - core: some refcouting issues fixed and better API for that - core: new helper function for best effort block read emulation - slave framework: proper DT bindings and userspace instantiation - some bigger work for xiic, pxa, omap drivers .. and quite a number of smaller driver fixes, cleanups, improvements" * 'i2c/for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (65 commits) i2c: mux: reg Change ioread endianness for readback i2c: mux: reg: fix compilation warnings i2c: mux: reg: simplify register size checking i2c: muxes: fix leaked i2c adapter device node references i2c: allow specifying separate wakeup interrupt in device tree of/irq: export of_get_irq_byname() i2c: xgene-slimpro: dma_mapping_error() doesn't return an error code i2c: Replace I2C_CROS_EC_TUNNEL dependency eeprom: at24: use i2c_smbus_read_i2c_block_data_or_emulated i2c: core: Add support for best effort block read emulation i2c: lpc2k: add driver i2c: mux: Add register-based mux i2c-mux-reg i2c: dt: describe generic bindings i2c: slave: print warning if slave flag not set i2c: support 10 bit and slave addresses in sysfs 'new_device' i2c: take address space into account when checking for used addresses i2c: apply DT flags when probing i2c: make address check indpendent from client struct i2c: rename address check functions i2c: apply address offset for slaves, too ...
| * clk: shmobile: emev2: deassert reset for IIC0/1Wolfram Sang2015-08-101-0/+6
| | | | | | | | | | | | | | | | We have a driver now for IIC, so disable reset for them. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2015-09-015-0/+96
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - memory controller work for ARM's PL172 memory controller - reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits) ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile memory: tegra: Add Tegra210 support memory: tegra: Add support for a variable-size client ID bitfield clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver ...
| * | clk: shmobile: rz: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Also update the reg property in the DT binding doc example to match the actual dtsi, which uses #address-cells and #size-cells == 1, not 2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | clk: shmobile: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-121-0/+87
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. The CPG/MSTP Clock Domain code will scan such devices for clocks that are suitable for power-managing the device, by looking for a clock that is compatible with "renesas,cpg-mstp-clocks". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script. @@ struct clk_hw *E; @@ -__clk_get_name(E->clk) +clk_hw_get_name(E) Acked-by: Heiko Stuebner <heiko@sntech.de> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Bresticker <abrestic@chromium.org> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Kevin Cernekee <cernekee@chromium.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()Stephen Boyd2015-08-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly converted with the following semantic patch: @@ struct clk_hw *E; @@ -__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E) Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chao Xie <chao.xie@marvell.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: shmobile: Remove unneeded #include <linux/clkdev.h>Geert Uytterhoeven2015-07-287-7/+7
|/ | | | | | | | | | | The CCF implementations for the various shmobile SoCs don't use clkdev functionality, hence drop the inclusion of <linux/clkdev.h>. Add the missing #include <linux/slab.h>, which was included implicitly through <asm/clkdev.h> before. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: emev2: Silence sparse warningsStephen Boyd2015-05-141-1/+1
| | | | | | | | | drivers/clk/shmobile/clk-emev2.c:37:14: warning: symbol 'smu_base' was not declared. Should it be static? Cc: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Cc: Magnus Damm <damm@opensource.se> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* ARM: shmobile: r8a7778: common clock framework CPG driverUlrich Hecht2015-02-272-0/+144
| | | | | | | | | Driver for the r8a7778's clocks that depend on the mode bits. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-214-4/+345
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * clk: shmobile: div6: Avoid division by zero in .round_rate()Geert Uytterhoeven2015-02-041-0/+3
| | | | | | | | | | | | | | | | | | Anyone may call clk_round_rate() with a zero rate value, so we have to protect against that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: shmobile: Add R-Car Gen2 ADSP clock supportSergei Shtylyov2015-01-081-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: Add R-Car Gen2 RCAN clock supportSergei Shtylyov2015-01-081-0/+40
| | | | | | | | | | | | | | | | | | | | Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the RCANCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but has no divider field, and so can't be supported by that driver... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: r8a73a4 common clock framework implementationUlrich Hecht2015-01-082-0/+242
| | | | | | | | | | | | | | | | | | | | Driver for the R8A73A4's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Michael Turquette <mturquette@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: Add r8a7793 supportHisashi Nakamura2015-01-081-0/+1
| | | | | | | | | | | | | | | | R-Car M2N (r8a7793) clock is handled in R-Car Gen2 clock driver. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: shmobile: div6: Avoid changing divisor in .disable()Geert Uytterhoeven2015-01-081-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While DIV6 clocks require the divisor field to be non-zero when stopping the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later if the divisor field is changed when stopping the clock. The reason for this is unknown. To fix this, do not touch the divisor field if it's already non-zero. On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0 Bus State Controller, which is clocked by the ZB clock. Without this fix, if the ZB clock is disabled during system suspend, and re-enabled during resume, the kernel locks up when the smsc911x driver tries to access the Ethernet registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* | clk: shmobile: fix sparse NULL pointer warningWei Yongjun2015-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes the following sparse warnings: drivers/clk/shmobile/clk-sh73a0.c:57:17: warning: Using plain integer as NULL pointer Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | clk: shmobile: sh73a0 common clock framework implementationUlrich Hecht2014-12-212-0/+219
|/ | | | | | | | | | | Driver for the SH73A0's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* clk: shmobile: div6: support selectable-input clocksUlrich Hecht2014-11-121-12/+101
| | | | | | | | | Support for setting the parent at initialization time based on the current hardware configuration in DIV6 clocks with selectable parents as found in the r8a73a4, r8a7740, sh73a0, and other SoCs. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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